From 4d2cd95ff51a7840c0ded5ddc463a0d1563cb6c0 Mon Sep 17 00:00:00 2001
From: Amir Arjomand <amirarjmandaqai@gmail.com>
Date: Mon, 8 Jul 2024 12:56:53 -0300
Subject: [PATCH] Save current changes before switching branches

---
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diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/golden_results (copy).xlsx b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/golden_results (copy).xlsx
new file mode 100644
index 00000000000..f5fb0192fb8
--- /dev/null
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/golden_results (copy).xlsx	
@@ -0,0 +1,13 @@
+ arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  tpu_like.small.os.v	  common	  677.72	  vpr	  2.29 GiB	  	  -1	  -1	  19.40	  195276	  5	  99.61	  -1	  -1	  109760	  -1	  -1	  492	  355	  32	  -1	  success	  327aa1d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T16:01:10	  gh-actions-runner-vtr-auto-spawned87	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  2400616	  355	  289	  25429	  18444	  2	  12313	  1433	  136	  136	  18496	  dsp_top	  auto	  208.3 MiB	  14.61	  359754	  2344.4 MiB	  16.75	  0.18	  5.12303	  -82671.4	  -5.12303	  2.1842	  6.09	  0.0412666	  0.0368158	  6.35102	  5.65512	  -1	  394367	  16	  5.92627e+08	  8.53857e+07	  4.08527e+08	  22087.3	  4.50	  8.69097	  7.85207	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  tpu_like.small.ws.v	  common	  722.22	  vpr	  2.30 GiB	  	  -1	  -1	  23.09	  242848	  5	  72.60	  -1	  -1	  117236	  -1	  -1	  686	  357	  58	  -1	  success	  327aa1d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T16:01:10	  gh-actions-runner-vtr-auto-spawned87	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  2415672	  357	  289	  25686	  20353	  2	  12799	  1656	  136	  136	  18496	  dsp_top	  auto	  233.3 MiB	  98.40	  226648	  2359.1 MiB	  20.07	  0.17	  8.31923	  -74283.8	  -8.31923	  2.78336	  6.05	  0.0420585	  0.0356747	  6.53862	  5.54952	  -1	  293644	  13	  5.92627e+08	  9.4632e+07	  4.08527e+08	  22087.3	  4.58	  8.69976	  7.55132	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  dla_like.small.v	  common	  2800.18	  vpr	  1.75 GiB	  	  -1	  -1	  94.38	  736748	  6	  754.09	  -1	  -1	  389988	  -1	  -1	  3895	  206	  132	  -1	  success	  327aa1d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T16:01:10	  gh-actions-runner-vtr-auto-spawned87	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  1840088	  206	  13	  165036	  139551	  1	  69732	  4358	  88	  88	  7744	  dsp_top	  auto	  1052.4 MiB	  1692.76	  601396	  1606.1 MiB	  88.48	  0.64	  5.30279	  -150931	  -5.30279	  5.30279	  1.96	  0.131322	  0.104184	  16.7561	  13.7761	  -1	  876475	  15	  2.4541e+08	  1.55281e+08	  1.69370e+08	  21871.2	  14.42	  24.7943	  21.0377	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  bnn.v	  common	  797.74	  vpr	  2.01 GiB	  	  -1	  -1	  84.28	  729308	  3	  56.57	  -1	  -1	  411036	  -1	  -1	  6190	  260	  0	  -1	  success	  327aa1d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T16:01:10	  gh-actions-runner-vtr-auto-spawned87	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  2106860	  260	  122	  206251	  154342	  1	  87361	  6635	  87	  87	  7569	  clb	  auto	  1300.8 MiB	  202.79	  910701	  1723.3 MiB	  174.17	  1.12	  6.77966	  -140235	  -6.77966	  6.77966	  1.97	  0.198989	  0.175034	  29.926	  24.7241	  -1	  1199797	  17	  2.37162e+08	  1.88714e+08	  1.65965e+08	  21927.0	  20.72	  41.872	  35.326	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  attention_layer.v	  common	  778.08	  vpr	  1002.21 MiB	  	  -1	  -1	  34.70	  314612	  5	  16.29	  -1	  -1	  135008	  -1	  -1	  1000	  1052	  194	  -1	  success	  327aa1d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T16:01:10	  gh-actions-runner-vtr-auto-spawned87	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  1026264	  1052	  32	  45971	  36479	  1	  23765	  2376	  82	  82	  6724	  dsp_top	  auto	  311.2 MiB	  549.16	  240205	  1002.2 MiB	  29.44	  0.19	  5.44091	  -87140.2	  -5.44091	  5.44091	  1.55	  0.049896	  0.0424754	  8.68648	  7.24743	  -1	  380516	  19	  2.09174e+08	  7.94825e+07	  1.47429e+08	  21925.8	  7.09	  11.8806	  10.0846	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  conv_layer_hls.v	  common	  494.69	  vpr	  1.34 GiB	  	  -1	  -1	  19.54	  264520	  3	  15.16	  -1	  -1	  56460	  -1	  -1	  1739	  1016	  21	  -1	  success	  327aa1d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T16:01:10	  gh-actions-runner-vtr-auto-spawned87	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  1406888	  1016	  2244	  12841	  14383	  1	  7131	  5032	  104	  104	  10816	  io	  auto	  138.0 MiB	  74.83	  73655	  1373.9 MiB	  27.72	  0.28	  4.66975	  -16444.1	  -4.66975	  4.66975	  5.72	  0.0687639	  0.0660952	  9.48152	  9.00606	  -1	  100883	  14	  3.44415e+08	  5.44618e+07	  2.37404e+08	  21949.3	  3.58	  12.2466	  11.6618	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  conv_layer.v	  common	  261.70	  vpr	  539.64 MiB	  	  -1	  -1	  14.31	  148624	  4	  106.09	  -1	  -1	  82672	  -1	  -1	  821	  91	  56	  -1	  success	  327aa1d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T16:01:10	  gh-actions-runner-vtr-auto-spawned87	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  552588	  91	  65	  33178	  28065	  2	  12714	  1075	  56	  56	  3136	  dsp_top	  auto	  245.3 MiB	  15.16	  162218	  539.6 MiB	  20.95	  0.16	  4.63337	  -55301.2	  -4.63337	  1.84791	  1.03	  0.064784	  0.0563394	  8.11436	  6.88378	  -1	  232737	  13	  9.76016e+07	  4.12774e+07	  6.79229e+07	  21659.1	  6.42	  11.3034	  9.78771	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  eltwise_layer.v	  common	  134.01	  vpr	  471.62 MiB	  	  -1	  -1	  5.54	  84604	  4	  10.22	  -1	  -1	  57240	  -1	  -1	  358	  152	  72	  -1	  success	  327aa1d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T16:01:10	  gh-actions-runner-vtr-auto-spawned87	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  482936	  152	  97	  14484	  12274	  2	  6814	  726	  56	  56	  3136	  dsp_top	  auto	  139.0 MiB	  7.49	  128840	  471.6 MiB	  10.79	  0.08	  3.7231	  -22257.6	  -3.7231	  1.56771	  1.07	  0.0418396	  0.0359169	  5.57189	  4.76335	  -1	  188991	  14	  9.76016e+07	  3.18294e+07	  6.79229e+07	  21659.1	  5.32	  7.49194	  6.52592	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  robot_rl.v	  common	  161.71	  vpr	  468.34 MiB	  	  -1	  -1	  16.70	  243012	  5	  9.37	  -1	  -1	  77484	  -1	  -1	  874	  3	  84	  -1	  success	  327aa1d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T16:01:10	  gh-actions-runner-vtr-auto-spawned87	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  479580	  3	  384	  24598	  22966	  1	  12280	  1363	  52	  52	  2704	  memory	  auto	  216.5 MiB	  18.36	  105021	  468.3 MiB	  24.33	  0.18	  5.54985	  -36353.1	  -5.54985	  5.54985	  0.84	  0.0529336	  0.0457202	  6.49893	  5.4558	  -1	  173035	  17	  8.30642e+07	  4.05203e+07	  5.85728e+07	  21661.5	  5.88	  9.68277	  8.27364	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  reduction_layer.v	  common	  112.24	  vpr	  312.18 MiB	  	  -1	  -1	  18.23	  305628	  6	  11.33	  -1	  -1	  74884	  -1	  -1	  659	  37	  52	  -1	  success	  327aa1d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T16:01:10	  gh-actions-runner-vtr-auto-spawned87	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  319672	  37	  17	  16436	  14191	  1	  8837	  765	  38	  38	  1444	  memory	  auto	  166.0 MiB	  19.17	  99898	  301.3 MiB	  12.00	  0.15	  5.43701	  -40617.4	  -5.43701	  5.43701	  0.38	  0.0444985	  0.0353751	  3.86054	  3.15721	  -1	  163885	  16	  4.31434e+07	  2.55478e+07	  3.09543e+07	  21436.5	  5.73	  6.27904	  5.31913	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  spmv.v	  common	  281.23	  vpr	  940.78 MiB	  	  -1	  -1	  9.42	  191424	  6	  15.99	  -1	  -1	  69580	  -1	  -1	  649	  82	  232	  -1	  success	  327aa1d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T16:01:10	  gh-actions-runner-vtr-auto-spawned87	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  963360	  82	  17	  16267	  14363	  1	  9085	  1012	  84	  84	  7056	  memory	  auto	  154.7 MiB	  20.89	  173262	  940.8 MiB	  9.92	  0.09	  4.77582	  -40195.5	  -4.77582	  4.77582	  2.76	  0.0348339	  0.0273197	  3.85139	  3.13376	  -1	  231971	  14	  2.2198e+08	  5.81696e+07	  1.54484e+08	  21894.0	  5.04	  5.62118	  4.72078	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  softmax.v	  common	  143.67	  vpr	  438.25 MiB	  	  -1	  -1	  12.83	  292752	  10	  10.84	  -1	  -1	  58644	  -1	  -1	  517	  402	  0	  -1	  success	  327aa1d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T16:01:10	  gh-actions-runner-vtr-auto-spawned87	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  448768	  402	  150	  12953	  11777	  1	  7813	  1106	  54	  54	  2916	  dsp_top	  auto	  131.0 MiB	  14.38	  80909	  438.2 MiB	  12.89	  0.09	  8.74709	  -12940.5	  -8.74709	  8.74709	  1.02	  0.0242371	  0.0213375	  3.69252	  3.20705	  -1	  130144	  17	  8.95105e+07	  2.38165e+07	  6.32721e+07	  21698.2	  3.46	  5.30986	  4.69795	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
diff --git a/yosys/.github/ISSUE_TEMPLATE/bug_report.yml b/yosys/.github/ISSUE_TEMPLATE/bug_report.yml
index 27cfd09b7de..e4c776ed914 100644
--- a/yosys/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/yosys/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -34,6 +34,7 @@ body:
         - macOS
         - Windows
         - BSD
+        - WebAssembly
       multiple: true
     validations:
       required: true
@@ -42,7 +43,7 @@ body:
     attributes:
       value: >
         When providing steps to reproduce the issue, please ensure that the issue
-        is reproducible in the current git master of Yosys. Also ensure to
+        is reproducible in the current git main of Yosys. Also ensure to
         provide all necessary source files needed.
 
 
diff --git a/yosys/.github/ISSUE_TEMPLATE/docs_report.yml b/yosys/.github/ISSUE_TEMPLATE/docs_report.yml
new file mode 100644
index 00000000000..aa65c63b9c9
--- /dev/null
+++ b/yosys/.github/ISSUE_TEMPLATE/docs_report.yml
@@ -0,0 +1,55 @@
+name: Documentation Report
+description: Report a problem with the Yosys documentation
+labels: ["pending-verification"]
+body:
+  - type: markdown
+    attributes:
+      value: >
+
+        If you have a general question, please ask it in the [Discussions](https://github.com/YosysHQ/yosys/discussions) area
+        or join our [IRC Channel](https://web.libera.chat/#yosys) or [Community Slack](https://join.slack.com/t/yosyshq/shared_invite/zt-1aopkns2q-EiQ97BeQDt_pwvE41sGSuA).
+
+
+        If you have found a bug in Yosys, or in building the documentation,
+        please fill out the Bug Report issue form, this form is for problems
+        with the live documentation on [Read the
+        Docs](https://yosyshq.readthedocs.io/projects/yosys/).  Please only
+        report problems that appear on the latest version of the documentation.
+
+
+        Please contact [YosysHQ GmbH](https://www.yosyshq.com/) if you need
+        commercial support for Yosys.
+
+  - type: input
+    id: docs_url
+    attributes:
+      label: Link to page
+      description: "Please provide a link to the page where the problem was found."
+      placeholder: "e.g. https://yosyshq.readthedocs.io/projects/yosys/"
+    validations:
+      required: true
+
+  - type: input
+    id: build_number
+    attributes:
+      label: Build number
+      description: "If possible, please provide the latest build number from https://readthedocs.org/projects/yosys/builds/."
+      placeholder: "e.g. Build #24078236"
+    validations:
+      required: false
+
+  - type: textarea
+    id: problem
+    attributes:
+      label: Issue
+      description: "Please describe what is incorrect, invalid, or missing."
+    validations:
+      required: true
+
+  - type: textarea
+    id: expected
+    attributes:
+      label: Expected
+      description: "If applicable, please describe what should appear instead."
+    validations:
+      required: false
diff --git a/yosys/.github/PULL_REQUEST_TEMPLATE.md b/yosys/.github/PULL_REQUEST_TEMPLATE.md
new file mode 100644
index 00000000000..82daf609d36
--- /dev/null
+++ b/yosys/.github/PULL_REQUEST_TEMPLATE.md
@@ -0,0 +1,5 @@
+_What are the reasons/motivation for this change?_
+
+_Explain how this is achieved._
+
+_If applicable, please suggest to reviewers how they can test the change._
diff --git a/yosys/.github/actions/setup-build-env/action.yml b/yosys/.github/actions/setup-build-env/action.yml
new file mode 100644
index 00000000000..345b6db8ada
--- /dev/null
+++ b/yosys/.github/actions/setup-build-env/action.yml
@@ -0,0 +1,33 @@
+name: Build environment setup
+description: Configure build env for Yosys builds
+runs:
+  using: composite
+  steps:
+    - name: Install Linux Dependencies
+      if: runner.os == 'Linux'
+      shell: bash
+      run: |
+        sudo apt-get update
+        sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
+
+    - name: Install macOS Dependencies
+      if: runner.os == 'macOS'
+      shell: bash
+      run: |
+        HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash autoconf
+
+    - name: Linux runtime environment
+      if: runner.os == 'Linux'
+      shell: bash
+      run: |
+        echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
+        echo "procs=$(nproc)" >> $GITHUB_ENV
+
+    - name: macOS runtime environment
+      if: runner.os == 'macOS'
+      shell: bash
+      run: |
+        echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
+        echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
+        echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
+        echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
diff --git a/yosys/.github/workflows/codeql.yml b/yosys/.github/workflows/codeql.yml
index 2a046703bc0..24ae7c89883 100644
--- a/yosys/.github/workflows/codeql.yml
+++ b/yosys/.github/workflows/codeql.yml
@@ -14,10 +14,11 @@ jobs:
       run: sudo apt-get install bison flex libreadline-dev tcl-dev libffi-dev
 
     - name: Checkout repository
-      uses: actions/checkout@v3
-
+      uses: actions/checkout@v4
+      with:
+       submodules: true
     - name: Initialize CodeQL
-      uses: github/codeql-action/init@v2
+      uses: github/codeql-action/init@v3
       with:
         languages: cpp
         queries: security-extended,security-and-quality
@@ -26,4 +27,4 @@ jobs:
       run: make yosys -j6
 
     - name: Perform CodeQL Analysis
-      uses: github/codeql-action/analyze@v2
+      uses: github/codeql-action/analyze@v3
diff --git a/yosys/.github/workflows/emcc.yml b/yosys/.github/workflows/emcc.yml
deleted file mode 100644
index 295d9554b81..00000000000
--- a/yosys/.github/workflows/emcc.yml
+++ /dev/null
@@ -1,18 +0,0 @@
-name: Emscripten Build
-
-on: [push, pull_request]
-
-jobs:
-  emcc:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: mymindstorm/setup-emsdk@v11
-      - uses: actions/checkout@v3
-      - name: Build
-        run: |
-          make config-emcc
-          make YOSYS_VER=latest
-      - uses: actions/upload-artifact@v3
-        with:
-          name: yosysjs
-          path: yosysjs-latest.zip
diff --git a/yosys/.github/workflows/extra-builds.yml b/yosys/.github/workflows/extra-builds.yml
new file mode 100644
index 00000000000..d7c6e13ff06
--- /dev/null
+++ b/yosys/.github/workflows/extra-builds.yml
@@ -0,0 +1,97 @@
+name: Test extra build flows
+
+on: [push, pull_request]
+
+jobs:
+  pre_job:
+    runs-on: ubuntu-latest
+    outputs:
+      should_skip: ${{ steps.skip_check.outputs.should_skip }}
+    steps:
+      - id: skip_check
+        uses: fkirc/skip-duplicate-actions@v5
+        with:
+          paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
+          # cancel previous builds if a new commit is pushed
+          cancel_others: 'true'
+          # only run on push *or* pull_request, not both
+          concurrent_skipping: 'same_content_newer'
+
+  vs-prep:
+    name: Prepare Visual Studio build
+    runs-on: ubuntu-latest
+    needs: [pre_job]
+    if: needs.pre_job.outputs.should_skip != 'true'
+    steps:
+      - uses: actions/checkout@v4
+        with:
+         submodules: true
+      - name: Build
+        run: make vcxsrc YOSYS_VER=latest
+      - uses: actions/upload-artifact@v4
+        with:
+          name: vcxsrc
+          path: yosys-win32-vcxsrc-latest.zip
+  
+  vs-build:
+    name: Visual Studio build
+    runs-on: windows-2019
+    needs: [vs-prep, pre_job]
+    if: needs.pre_job.outputs.should_skip != 'true'
+    steps:  
+      - uses: actions/download-artifact@v4
+        with:
+          name: vcxsrc
+          path: .
+      - name: unzip
+        run: unzip yosys-win32-vcxsrc-latest.zip
+      - name: setup-msbuild
+        uses: microsoft/setup-msbuild@v2
+      - name: MSBuild
+        working-directory: yosys-win32-vcxsrc-latest
+        run: msbuild YosysVS.sln /p:PlatformToolset=v142 /p:Configuration=Release /p:WindowsTargetPlatformVersion=10.0.17763.0
+
+  wasi-build:
+    name: WASI build
+    needs: pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+        with:
+         submodules: true
+      - name: Build
+        run: |
+          WASI_SDK=wasi-sdk-19.0
+          WASI_SDK_URL=https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/wasi-sdk-19.0-linux.tar.gz
+          if ! [ -d ${WASI_SDK} ]; then curl -L ${WASI_SDK_URL} | tar xzf -; fi
+
+          mkdir -p build
+          cat > build/Makefile.conf <<END
+          export PATH := $(pwd)/${WASI_SDK}/bin:${PATH}
+          WASI_SYSROOT := $(pwd)/${WASI_SDK}/share/wasi-sysroot
+
+          CONFIG := wasi
+          PREFIX := /
+
+          ENABLE_TCL := 0
+          ENABLE_READLINE := 0
+          ENABLE_PLUGINS := 0
+          ENABLE_ZLIB := 0
+          END
+
+          make -C build -f ../Makefile CXX=clang -j$(nproc)
+
+  nix-build:
+    name: "Build nix flake"
+    needs: pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          submodules: true
+      - uses: cachix/install-nix-action@v26
+        with:
+          install_url: https://releases.nixos.org/nix/nix-2.18.1/install
+      - run: nix build .?submodules=1
diff --git a/yosys/.github/workflows/test-build.yml b/yosys/.github/workflows/test-build.yml
new file mode 100644
index 00000000000..bf95688a15c
--- /dev/null
+++ b/yosys/.github/workflows/test-build.yml
@@ -0,0 +1,181 @@
+name: Build and run tests
+
+on: [push, pull_request]
+
+jobs:
+  pre_job:
+    runs-on: ubuntu-latest
+    outputs:
+      should_skip: ${{ steps.skip_check.outputs.should_skip }}
+    steps:
+      - id: skip_check
+        uses: fkirc/skip-duplicate-actions@v5
+        with:
+          paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
+          # cancel previous builds if a new commit is pushed
+          cancel_others: 'true'
+          # only run on push *or* pull_request, not both
+          concurrent_skipping: 'same_content_newer'
+  pre_docs_job:
+    runs-on: ubuntu-latest
+    outputs:
+      should_skip: ${{ steps.skip_check.outputs.should_skip }}
+    steps:
+      - id: skip_check
+        uses: fkirc/skip-duplicate-actions@v5
+        with:
+          paths_ignore: '["**/README.md"]'
+          # cancel previous builds if a new commit is pushed
+          cancel_others: 'true'
+          # only run on push *or* pull_request, not both
+          concurrent_skipping: 'same_content_newer'
+
+  build-yosys:
+    name: Reusable build
+    runs-on: ${{ matrix.os }}
+    needs: pre_docs_job
+    if: needs.pre_docs_job.outputs.should_skip != 'true'
+    env:
+      CC: clang
+    strategy:
+      matrix:
+        os: [ubuntu-latest, macos-latest]
+      fail-fast: false
+    steps:
+      - name: Checkout Yosys
+        uses: actions/checkout@v4
+        with:
+          submodules: true
+
+      - name: Setup environment
+        uses: ./.github/actions/setup-build-env
+
+      - name: Build
+        shell: bash
+        run: |
+          mkdir build
+          cd build
+          make -f ../Makefile config-$CC
+          make -f ../Makefile -j$procs
+
+      - name: Log yosys-config output
+        run: |
+          ./yosys-config || true
+
+      - name: Compress build
+        shell: bash
+        run: |
+          cd build
+          tar -cvf ../build.tar share/ yosys yosys-*
+
+      - name: Store build artifact
+        uses: actions/upload-artifact@v4
+        with:
+          name: build-${{ matrix.os }}
+          path: build.tar
+          retention-days: 1
+
+  test-yosys:
+    name: Run tests
+    runs-on: ${{ matrix.os }}
+    needs: [build-yosys, pre_job]
+    if: needs.pre_job.outputs.should_skip != 'true'
+    env:
+      CC: clang
+    strategy:
+      matrix:
+        os: [ubuntu-latest, macos-latest]
+      fail-fast: false
+    steps:
+      - name: Checkout Yosys
+        uses: actions/checkout@v4
+
+      - name: Setup environment
+        uses: ./.github/actions/setup-build-env
+
+      - name: Get iverilog
+        shell: bash
+        run: |
+          git clone https://github.com/steveicarus/iverilog.git
+          cd iverilog
+          echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
+
+      - name: Cache iverilog
+        id: cache-iverilog
+        uses: actions/cache@v4
+        with:
+          path: .local/
+          key: ${{ matrix.os }}-${{ env.IVERILOG_GIT }}
+
+      - name: Build iverilog
+        if: steps.cache-iverilog.outputs.cache-hit != 'true'
+        shell: bash
+        run: |
+          mkdir -p ${{ github.workspace }}/.local/
+          cd iverilog
+          autoconf
+          CC=gcc CXX=g++ ./configure --prefix=${{ github.workspace }}/.local
+          make -j$procs
+          make install
+
+      - name: Download build artifact
+        uses: actions/download-artifact@v4
+        with:
+          name: build-${{ matrix.os }}
+
+      - name: Uncompress build
+        shell: bash
+        run:
+          tar -xvf build.tar
+
+      - name: Log yosys-config output
+        run: |
+          ./yosys-config || true
+
+      - name: Run tests
+        shell: bash
+        run: |
+          make -j$procs test TARGETS= EXTRA_TARGETS= CONFIG=$CC
+
+      - name: Report errors
+        if: ${{ failure() }}
+        shell: bash
+        run: |
+          find tests/**/*.err -print -exec cat {} \;
+
+  test-docs:
+    name: Run docs tests
+    runs-on: ${{ matrix.os }}
+    needs: [build-yosys, pre_docs_job]
+    if: needs.pre_docs_job.outputs.should_skip != 'true'
+    env:
+      CC: clang
+    strategy:
+      matrix:
+        os: [ubuntu-latest]
+      fail-fast: false
+    steps:
+      - name: Checkout Yosys
+        uses: actions/checkout@v4
+
+      - name: Setup environment
+        uses: ./.github/actions/setup-build-env
+
+      - name: Download build artifact
+        uses: actions/download-artifact@v4
+        with:
+          name: build-${{ matrix.os }}
+
+      - name: Uncompress build
+        shell: bash
+        run:
+          tar -xvf build.tar
+
+      - name: Log yosys-config output
+        run: |
+          ./yosys-config || true
+
+      - name: Run tests
+        shell: bash
+        run: |
+          make -C docs test -j${{ env.procs }}
diff --git a/yosys/.github/workflows/test-compile.yml b/yosys/.github/workflows/test-compile.yml
new file mode 100644
index 00000000000..375ea7fc54a
--- /dev/null
+++ b/yosys/.github/workflows/test-compile.yml
@@ -0,0 +1,79 @@
+name: Compiler testing
+
+on: [push, pull_request]
+
+jobs:
+  pre_job:
+    runs-on: ubuntu-latest
+    outputs:
+      should_skip: ${{ steps.skip_check.outputs.should_skip }}
+    steps:
+      - id: skip_check
+        uses: fkirc/skip-duplicate-actions@v5
+        with:
+          paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
+          # cancel previous builds if a new commit is pushed
+          cancel_others: 'true'
+          # only run on push *or* pull_request, not both
+          concurrent_skipping: 'same_content_newer'
+
+  test-compile:
+    runs-on: ${{ matrix.os }}
+    needs: pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
+    env:
+      CXXFLAGS: ${{ startsWith(matrix.compiler, 'gcc') && '-Wp,-D_GLIBCXX_ASSERTIONS' || ''}}
+      CC_SHORT: ${{ startsWith(matrix.compiler, 'gcc') && 'gcc' || 'clang' }}
+    strategy:
+      matrix:
+        os:
+          - ubuntu-latest
+        compiler:
+          # oldest supported
+          - 'clang-14'
+          - 'gcc-10'
+          # newest
+          - 'clang'
+          - 'gcc'
+        include:
+          # macOS
+          - os: macos-13
+            compiler: 'clang'
+          # oldest clang not available on ubuntu-latest
+          - os: ubuntu-22.04
+            compiler: 'clang-11'
+      fail-fast: false
+    steps:
+      - name: Checkout Yosys
+        uses: actions/checkout@v4
+        with:
+          submodules: true
+
+      - name: Setup environment
+        uses: ./.github/actions/setup-build-env
+
+      - name: Setup Cpp
+        uses: aminya/setup-cpp@v1
+        with:
+          compiler: ${{ matrix.compiler }}
+
+      - name: Tool versions
+        shell: bash
+        run: |
+          $CC --version
+          $CXX --version
+
+      # minimum standard
+      - name: Build C++11
+        shell: bash
+        run: |
+          make config-$CC_SHORT
+          make -j$procs CXXSTD=c++11 compile-only
+
+      # maximum standard, only on newest compilers
+      - name: Build C++20
+        if: ${{ matrix.compiler == 'clang' || matrix.compiler == 'gcc'}}
+        shell: bash
+        run: |
+          make config-$CC_SHORT
+          make -j$procs CXXSTD=c++20 compile-only
diff --git a/yosys/.github/workflows/test-linux.yml b/yosys/.github/workflows/test-linux.yml
deleted file mode 100644
index eee556794af..00000000000
--- a/yosys/.github/workflows/test-linux.yml
+++ /dev/null
@@ -1,116 +0,0 @@
-name: Build and run tests (Linux)
-
-on: [push, pull_request]
-
-jobs:
-  test-linux:
-    runs-on: ${{ matrix.os.id }}
-    strategy:
-      matrix:
-        os:
-          - { id: ubuntu-20.04, name: focal }
-        compiler:
-          - 'clang-12'
-          - 'gcc-11'
-        cpp_std:
-          - 'c++11'
-          - 'c++14'
-          - 'c++17'
-          - 'c++20'
-        include:
-          # Limit the older compilers to C++11 mode
-          - os: { id: ubuntu-20.04, name: focal }
-            compiler: 'clang-11'
-            cpp_std: 'c++11'
-          - os: { id: ubuntu-20.04, name: focal }
-            compiler: 'gcc-10'
-            cpp_std: 'c++11'
-      fail-fast: false
-    steps:
-      - name: Install Dependencies
-        shell: bash
-        run: |
-          sudo apt-get update
-          sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
-
-      - name: Setup GCC
-        if: startsWith(matrix.compiler, 'gcc')
-        shell: bash
-        run: |
-          CXX=${CC/#gcc/g++}
-          sudo apt-add-repository ppa:ubuntu-toolchain-r/test
-          sudo apt-get update
-          sudo apt-get install $CC $CXX
-          echo "CC=$CC" >> $GITHUB_ENV
-          echo "CXX=$CXX" >> $GITHUB_ENV
-        env:
-          CC: ${{ matrix.compiler }}
-
-      - name: Setup Clang
-        if: startsWith(matrix.compiler, 'clang')
-        shell: bash
-        run: |
-          wget https://apt.llvm.org/llvm-snapshot.gpg.key
-          sudo apt-key add llvm-snapshot.gpg.key
-          rm llvm-snapshot.gpg.key
-          sudo apt-add-repository "deb https://apt.llvm.org/${{ matrix.os.name }}/ llvm-toolchain-${{ matrix.os.name }} main"
-          sudo apt-get update
-          CXX=${CC/#clang/clang++}
-          sudo apt-get install $CC $CXX
-          echo "CC=$CC" >> $GITHUB_ENV
-          echo "CXX=$CXX" >> $GITHUB_ENV
-        env:
-          CC: ${{ matrix.compiler }}
-
-      - name: Runtime environment
-        shell: bash
-        env:
-          WORKSPACE: ${{ github.workspace }}
-        run: |
-          echo "GITHUB_WORKSPACE=`pwd`" >> $GITHUB_ENV
-          echo "$GITHUB_WORKSPACE/.local/bin" >> $GITHUB_PATH
-          echo "procs=$(nproc)" >> $GITHUB_ENV
-
-      - name: Tool versions
-        shell: bash
-        run: |
-          $CC --version
-          $CXX --version
-
-      - name: Checkout Yosys
-        uses: actions/checkout@v3
-
-      - name: Get iverilog
-        shell: bash
-        run: |
-          git clone https://github.com/steveicarus/iverilog.git
-
-      - name: Cache iverilog
-        id: cache-iverilog
-        uses: actions/cache@v3
-        with:
-          path: .local/
-          key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }}
-
-      - name: Build iverilog
-        if: steps.cache-iverilog.outputs.cache-hit != 'true'
-        shell: bash
-        run: |
-          mkdir -p $GITHUB_WORKSPACE/.local/
-          cd iverilog
-          autoconf
-          CC=gcc CXX=g++ ./configure --prefix=$GITHUB_WORKSPACE/.local
-          make -j${{ env.procs }}
-          make install
-
-      - name: Build yosys
-        shell: bash
-        run: |
-          make config-${CC%%-*}
-          make -j${{ env.procs }} CCXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
-
-      - name: Run tests
-        if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'gcc-11')
-        shell: bash
-        run: |
-          make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
diff --git a/yosys/.github/workflows/test-macos.yml b/yosys/.github/workflows/test-macos.yml
deleted file mode 100644
index 04845723467..00000000000
--- a/yosys/.github/workflows/test-macos.yml
+++ /dev/null
@@ -1,73 +0,0 @@
-name: Build and run tests (macOS)
-
-on: [push, pull_request]
-
-jobs:
-  test-macos:
-    runs-on: ${{ matrix.os.id }}
-    strategy:
-      matrix:
-        os:
-          - { id: macos-11, name: 'Big Sur' }
-        cpp_std:
-          - 'c++11'
-          - 'c++17'
-      fail-fast: false
-    steps:
-      - name: Install Dependencies
-        run: |
-          brew install bison flex gawk libffi pkg-config bash
-
-      - name: Runtime environment
-        shell: bash
-        env:
-          WORKSPACE: ${{ github.workspace }}
-        run: |
-          echo "GITHUB_WORKSPACE=`pwd`" >> $GITHUB_ENV
-          echo "$GITHUB_WORKSPACE/.local/bin" >> $GITHUB_PATH
-          echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
-          echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
-          echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
-
-      - name: Tool versions
-        shell: bash
-        run: |
-          cc --version
-
-      - name: Checkout Yosys
-        uses: actions/checkout@v3
-
-      - name: Get iverilog
-        shell: bash
-        run: |
-          git clone https://github.com/steveicarus/iverilog.git
-
-      - name: Cache iverilog
-        id: cache-iverilog
-        uses: actions/cache@v3
-        with:
-          path: .local/
-          key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }}
-
-      - name: Build iverilog
-        if: steps.cache-iverilog.outputs.cache-hit != 'true'
-        shell: bash
-        run: |
-          mkdir -p $GITHUB_WORKSPACE/.local/
-          cd iverilog
-          autoconf
-          CC=gcc CXX=g++ ./configure --prefix=$GITHUB_WORKSPACE/.local/
-          make -j${{ env.procs }}
-          make install
-
-      - name: Build yosys
-        shell: bash
-        run: |
-          make config-clang
-          make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=cc CXX=cc LD=cc
-
-      - name: Run tests
-        if: matrix.cpp_std == 'c++11'
-        shell: bash
-        run: |
-          make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=cc CXX=cc LD=cc
diff --git a/yosys/.github/workflows/test-verific.yml b/yosys/.github/workflows/test-verific.yml
new file mode 100644
index 00000000000..54d9487acfb
--- /dev/null
+++ b/yosys/.github/workflows/test-verific.yml
@@ -0,0 +1,95 @@
+name: Build and run tests with Verific (Linux)
+
+on: [push, pull_request]
+
+jobs:
+  pre_job:
+    runs-on: ubuntu-latest
+    outputs:
+      should_skip: ${{ steps.skip_check.outputs.should_skip }}
+    steps:
+      - id: skip_check
+        uses: fkirc/skip-duplicate-actions@v5
+        with:
+          paths_ignore: '["**/README.md"]'
+          # don't cancel previous builds
+          cancel_others: 'true'
+          # only run on push *or* pull_request, not both
+          concurrent_skipping: 'same_content_newer'
+          # we have special actions when running on main, so this should be off
+          skip_after_successful_duplicate: 'false'
+
+  test-verific:
+    needs: pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
+    runs-on: [self-hosted, linux, x64]
+    steps:
+      - name: Checkout Yosys
+        uses: actions/checkout@v4
+        with:
+          persist-credentials: false
+          submodules: true
+      - name: Runtime environment
+        run: |
+          echo "procs=$(nproc)" >> $GITHUB_ENV
+
+      - name: Build Yosys
+        run: |
+          make config-clang
+          echo "ENABLE_VERIFIC := 1" >> Makefile.conf
+          echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf
+          echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf
+          echo "ENABLE_CCACHE := 1" >> Makefile.conf
+          make -j${{ env.procs }}
+
+      - name: Install Yosys
+        run: |
+          make install DESTDIR=${GITHUB_WORKSPACE}/.local PREFIX=
+
+      - name: Checkout Documentation
+        if: ${{ github.ref == 'refs/heads/main' }}
+        uses: actions/checkout@v4
+        with:
+          path: 'yosys-cmd-ref'
+          repository: 'YosysHQ-Docs/yosys-cmd-ref'
+          fetch-depth: 0
+          token: ${{ secrets.CI_DOCS_UPDATE_PAT }}
+          persist-credentials: true
+
+      - name: Update documentation
+        if: ${{ github.ref == 'refs/heads/main' }}
+        run: |
+          make docs
+          rm -rf docs/build
+          cd yosys-cmd-ref
+          rm -rf *
+          git checkout README.md
+          cp -R ../docs/* .
+          rm -rf util/__pycache__
+          git add -A .
+          git diff-index --quiet HEAD || git commit -m "Update"
+          git push
+
+      - name: Checkout SBY
+        uses: actions/checkout@v4
+        with:
+          repository: 'YosysHQ/sby'
+          path: 'sby'
+
+      - name: Build SBY
+        run: |
+          make -C sby install DESTDIR=${GITHUB_WORKSPACE}/.local PREFIX=
+
+      - name: Run Yosys tests
+        run: |
+          make -j${{ env.procs }} test
+
+      - name: Run Verific specific Yosys tests
+        run: |
+          make -C tests/sva
+          cd tests/svtypes && bash run-test.sh
+
+      - name: Run SBY tests
+        if: ${{ github.ref == 'refs/heads/main' }}
+        run: |
+          make -C sby run_ci
diff --git a/yosys/.github/workflows/update-flake-lock.yml b/yosys/.github/workflows/update-flake-lock.yml
new file mode 100644
index 00000000000..c7aa6ecab70
--- /dev/null
+++ b/yosys/.github/workflows/update-flake-lock.yml
@@ -0,0 +1,22 @@
+name: update-flake-lock
+on:
+  workflow_dispatch: # allows manual triggering
+  schedule:
+    - cron: '0 0 * * 0' # runs weekly on Sunday at 00:00
+
+jobs:
+  lockfile:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@v4
+      - name: Install Nix
+        uses: DeterminateSystems/nix-installer-action@main
+      - name: Update flake.lock
+        uses: DeterminateSystems/update-flake-lock@main
+        with:
+          token: ${{CI_CREATE_PR_TOKEN}}
+          pr-title: "Update flake.lock" # Title of PR to be created
+          pr-labels: |                  # Labels to be set on the PR
+            dependencies
+            automated
diff --git a/yosys/.github/workflows/version.yml b/yosys/.github/workflows/version.yml
index c2a1756e9c6..f73c68bdf12 100644
--- a/yosys/.github/workflows/version.yml
+++ b/yosys/.github/workflows/version.yml
@@ -10,9 +10,10 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
         with:
           fetch-depth: 0
+          submodules: true
       - name: Take last commit
         id: log
         run: echo "message=$(git log --no-merges -1 --oneline)" >> $GITHUB_OUTPUT
diff --git a/yosys/.github/workflows/vs.yml b/yosys/.github/workflows/vs.yml
deleted file mode 100644
index 428770e7200..00000000000
--- a/yosys/.github/workflows/vs.yml
+++ /dev/null
@@ -1,31 +0,0 @@
-name: Visual Studio Build
-
-on: [push, pull_request]
-
-jobs:
-  yosys-vcxsrc:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v3
-      - name: Build
-        run: make vcxsrc YOSYS_VER=latest
-      - uses: actions/upload-artifact@v3
-        with:
-          name: vcxsrc
-          path: yosys-win32-vcxsrc-latest.zip
-  
-  build:
-    runs-on: windows-2019
-    needs: yosys-vcxsrc
-    steps:  
-      - uses: actions/download-artifact@v3
-        with:
-          name: vcxsrc
-          path: .
-      - name: unzip
-        run: unzip yosys-win32-vcxsrc-latest.zip
-      - name: setup-msbuild
-        uses: microsoft/setup-msbuild@v1
-      - name: MSBuild
-        working-directory: yosys-win32-vcxsrc-latest
-        run: msbuild YosysVS.sln /p:PlatformToolset=v142 /p:Configuration=Release /p:WindowsTargetPlatformVersion=10.0.17763.0
diff --git a/yosys/.gitignore b/yosys/.gitignore
index 49b886e7e43..e82343e8947 100644
--- a/yosys/.gitignore
+++ b/yosys/.gitignore
@@ -1,9 +1,11 @@
 *.o
 *.d
+*.dwo
 .*.swp
 *.gch
 *.gcda
 *.gcno
+*~
 __pycache__
 /.cproject
 /.project
@@ -16,7 +18,6 @@ __pycache__
 /coverage.info
 /coverage_html
 /Makefile.conf
-/abc
 /viz.js
 /yosys
 /yosys.exe
@@ -44,3 +45,4 @@ __pycache__
 /tests/unit/bintest/
 /tests/unit/objtest/
 /tests/ystests
+/result
\ No newline at end of file
diff --git a/yosys/.gitmodules b/yosys/.gitmodules
new file mode 100644
index 00000000000..d88d4b1e5e9
--- /dev/null
+++ b/yosys/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "abc"]
+	path = abc
+	url = https://github.com/YosysHQ/abc
diff --git a/yosys/CHANGELOG b/yosys/CHANGELOG
index 585605abcdd..d8e13b041e5 100644
--- a/yosys/CHANGELOG
+++ b/yosys/CHANGELOG
@@ -2,6 +2,177 @@
 List of major changes and improvements between releases
 =======================================================
 
+Yosys 0.42 .. Yosys 0.43-dev
+--------------------------
+
+Yosys 0.41 .. Yosys 0.42
+--------------------------
+ * New commands and options
+    - Added "box_derive" pass to derive box modules.
+    - Added option "assert-mod-count" to "select" pass. 
+    - Added option "-header","-push" and "-pop" to "log" pass. 
+ * Intel support
+    - Dropped Quartus support in "synth_intel_alm" pass.
+
+Yosys 0.40 .. Yosys 0.41
+--------------------------
+ * New commands and options
+    - Added "cellmatch" pass for picking out standard cells automatically. 
+
+ * Various
+    - Extended the experimental incremental JSON API to allow arbitrary
+      smtlib subexpressions.
+    - Added support for using ABCs library merging when providing multiple
+      liberty files.
+
+ * Verific support
+    - Expose library name as module attribute.
+
+Yosys 0.39 .. Yosys 0.40
+--------------------------
+ * New commands and options
+    - Added option "-vhdl2019" to "read" and "verific" pass. 
+
+ * Various
+    - Major documentation overhaul.
+    - Added port statistics to "stat" command.
+    - Added new formatting features to cxxrtl backend.
+
+ * Verific support
+    - Added better support for VHDL constants import.
+    - Added support for VHDL 2009.
+
+Yosys 0.38 .. Yosys 0.39
+--------------------------
+ * New commands and options
+    - Added option "-extra-map" to "synth" pass. 
+    - Added option "-dont_use" to "dfflibmap" pass.
+    - Added option "-href" to "show" command.
+    - Added option "-noscopeinfo" to "flatten" pass.
+    - Added option "-scopename" to "flatten" pass.
+
+ * SystemVerilog
+    - Added support for packed multidimensional arrays.
+
+ * Various
+    - Added "$scopeinfo" cells to preserve information about
+      the hierarchy during flattening.
+    - Added sequential area output to "stat -liberty".
+    - Added ability to record/replay diagnostics in cxxrtl backend.
+ 
+ * Verific support
+    - Added attributes to module instantiation.
+
+Yosys 0.37 .. Yosys 0.38
+--------------------------
+ * New commands and options
+    - Added option "-tech" to "opt_lut" pass.
+    - Added option "-nokeep_prints" to "hierarchy" pass.
+    - Added option "-nolower" to "async2sync" and "clk2fflogic" pass.
+    - Added option "-lower" to "chformal" pass.
+
+ * Various
+    - Added $check cell to represent assertions with messages.
+    - Allow capturing $print cell output in CXXRTL.
+    - Added API to overwrite existing pass from plugin.
+    - Follow the XDG Base Directory Specification for storing history files.
+    - Without a known top module, derive all deferred modules (hierarchy pass).
+    - Detect and error out on combinational loops in write_aiger.
+
+ * Verific support
+    - Added option "-no-split-complex-ports" to "verific -import".
+
+Yosys 0.36 .. Yosys 0.37
+--------------------------
+ * New commands and options
+    - Added option "-nodisplay" to read_verilog.
+
+ * SystemVerilog
+    - Correct hierarchical path names for structs and unions.
+
+ * Various
+    - Print hierarchy for failed assertions in "sim" pass.
+    - Add "--present-only" option to "yosys-witness" to omit unused signals.
+    - Implement a generic record/replay interface for CXXRTL.
+    - Improved readability of emitted code with "write_verilog".
+
+Yosys 0.35 .. Yosys 0.36
+--------------------------
+ * New commands and options
+    - Added option "--" to pass arguments down to tcl when using -c option.
+    - Added ability on MacOS and Windows to pass options after arguments on cli.
+    - Added option "-cmp2softlogic" to synth_lattice.
+    - Added option "-lowpower" to "booth" pass.
+
+ * QuickLogic support
+    - Added "K6N10f" support.
+    - Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to 
+      "synth_quicklogic" pass.
+    - Added "ql_bram_merge" pass to merge 18K BRAM cells into TDP36K.
+    - Added "ql_bram_types" pass to change TDP36K depending on configuration.
+    - Added "ql_dsp_io_regs" pass to update QL_DSP2 depending on configuration.
+    - Added "ql_dsp_macc" pass to infer multiplier-accumulator DSP cells.
+    - Added "ql_dsp_simd" pass to merge DSP pairs to operate in SIMD mode.
+
+ * ECP5,iCE40 and Gowin support
+    - Enabled abc9 by default, added "-noabc9" option to disable.
+
+ * MachXO3 support
+    - Quality of results improvements.
+    - Enabled "booth" pass by default for it in "synth_lattice".
+
+ * Various
+    - Improved "peepopt" by adding shiftadd pattern support.
+    - Added "--incremental" mode to smtbmc.
+
+Yosys 0.34 .. Yosys 0.35
+--------------------------
+ * Various
+    - Improvements on "peepopt" shiftmul matcher.
+    - Improvements on "ram_style" attributes handling.
+
+ * Verific support
+    - Improved static elaboration for VHDL and mixed HDL designs.
+    - Expose "hdlname" attribute with original module name.
+    - Expose "architecture" attribute with VHDL architecture name.
+
+Yosys 0.33 .. Yosys 0.34
+--------------------------
+ * New commands and options
+    - Added option "-assert" to "sim" pass.
+    - Added option "-noinitstate" to "sim" pass.
+    - Added option "-dont_use" to "abc" pass.
+    - Added "dft_tag" pass to create tagging logic for data flow tracking.
+    - Added "future" pass to resolve future sampled value functions.
+    - Added "booth" pass to map $mul cells to Booth multipliers.
+    - Added option "-booth" to "synth" pass.
+
+ * SystemVerilog
+    - Added support for assignments within expressions, e.g., `x[y++] = z;` or
+      `x = (y *= 2) - 1;`.
+
+ * Verific support
+    - "src" attribute contain full location info.
+    - module parameters are kept after import.
+    - accurate access order semantics in memory inference.
+    - better "bind" support for mixed language projects.
+
+ * Various
+    - "show" command displays dot instead of box for wire aliases.
+
+Yosys 0.32 .. Yosys 0.33
+--------------------------
+ * Various
+    - Added "$print" cell, produced by "$display" and "$write"
+      Verilog tasks.
+    - Added "$print" cell handling in CXXRTL.
+
+ * Lattice FPGA support
+    - Added generic "synth_lattice" pass (for now MachXO2/XO3/XO3D)
+    - Removed "synth_machxo2" pass
+    - Pass "ecp5_gsr" renamed to "lattice_gsr"
+    - "synth_machxo2" equivalent is "synth_lattice -family xo2"
+
 Yosys 0.31 .. Yosys 0.32
 --------------------------
  * Verific support
diff --git a/yosys/CODEOWNERS b/yosys/CODEOWNERS
index a33a9a68ccb..879bb8dee21 100644
--- a/yosys/CODEOWNERS
+++ b/yosys/CODEOWNERS
@@ -10,6 +10,7 @@
 
 # PATH (can use glob)          USERNAME(S)
 
+CODEOWNERS                     @nakengelhardt
 passes/cmds/scratchpad.cc      @nakengelhardt
 frontends/rpc/                 @whitequark
 backends/cxxrtl/               @whitequark
@@ -18,7 +19,8 @@ passes/techmap/flowmap.cc      @whitequark
 passes/opt/opt_lut.cc          @whitequark
 passes/techmap/abc9*.cc        @eddiehung @Ravenslofty
 backends/aiger/xaiger.cc       @eddiehung
-
+docs/                          @KrystalDelusion
+.github/workflows/*.yml        @mmicko
 
 ## External Contributors
 # Only users with write permission to the repository get review
diff --git a/yosys/Makefile b/yosys/Makefile
index 630d65367b9..d2c56e9797b 100644
--- a/yosys/Makefile
+++ b/yosys/Makefile
@@ -1,8 +1,8 @@
 
-CONFIG := clang
+CONFIG := none
+# CONFIG := clang
 # CONFIG := gcc
 # CONFIG := afl-gcc
-# CONFIG := emcc
 # CONFIG := wasi
 # CONFIG := mxe
 # CONFIG := msys2-32
@@ -17,10 +17,12 @@ ENABLE_READLINE := 1
 ENABLE_EDITLINE := 0
 ENABLE_GHDL := 0
 ENABLE_VERIFIC := 0
+ENABLE_VERIFIC_SYSTEMVERILOG := 1
+ENABLE_VERIFIC_VHDL := 1
+ENABLE_VERIFIC_HIER_TREE := 1
+ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1
 ENABLE_VERIFIC_EDIF := 0
 ENABLE_VERIFIC_LIBERTY := 0
-DISABLE_VERIFIC_EXTENSIONS := 0
-DISABLE_VERIFIC_VHDL := 0
 ENABLE_COVER := 1
 ENABLE_LIBYOSYS := 0
 ENABLE_ZLIB := 1
@@ -92,14 +94,14 @@ VPATH := $(YOSYS_SRC)
 
 CXXSTD ?= c++11
 CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
-LDLIBS := $(LDLIBS) -lstdc++ -lm
-PLUGIN_LDFLAGS :=
-PLUGIN_LDLIBS :=
-EXE_LDFLAGS :=
+LIBS := $(LIBS) -lstdc++ -lm
+PLUGIN_LINKFLAGS :=
+PLUGIN_LIBS :=
+EXE_LINKFLAGS :=
 ifeq ($(OS), MINGW)
-EXE_LDFLAGS := -Wl,--export-all-symbols -Wl,--out-implib,libyosys_exe.a
-PLUGIN_LDFLAGS += -L"$(LIBDIR)"
-PLUGIN_LDLIBS := -lyosys_exe
+EXE_LINKFLAGS := -Wl,--export-all-symbols -Wl,--out-implib,libyosys_exe.a
+PLUGIN_LINKFLAGS += -L"$(LIBDIR)"
+PLUGIN_LIBS := -lyosys_exe
 endif
 
 PKG_CONFIG ?= pkg-config
@@ -109,7 +111,7 @@ STRIP ?= strip
 AWK ?= awk
 
 ifeq ($(OS), Darwin)
-PLUGIN_LDFLAGS += -undefined dynamic_lookup
+PLUGIN_LINKFLAGS += -undefined dynamic_lookup
 
 # homebrew search paths
 ifneq ($(shell :; command -v brew),)
@@ -117,10 +119,10 @@ BREW_PREFIX := $(shell brew --prefix)/opt
 $(info $$BREW_PREFIX is [${BREW_PREFIX}])
 ifeq ($(ENABLE_PYOSYS),1)
 CXXFLAGS += -I$(BREW_PREFIX)/boost/include/boost
-LDFLAGS += -L$(BREW_PREFIX)/boost/lib
+LINKFLAGS += -L$(BREW_PREFIX)/boost/lib
 endif
 CXXFLAGS += -I$(BREW_PREFIX)/readline/include
-LDFLAGS += -L$(BREW_PREFIX)/readline/lib
+LINKFLAGS += -L$(BREW_PREFIX)/readline/lib
 PKG_CONFIG_PATH := $(BREW_PREFIX)/libffi/lib/pkgconfig:$(PKG_CONFIG_PATH)
 PKG_CONFIG_PATH := $(BREW_PREFIX)/tcl-tk/lib/pkgconfig:$(PKG_CONFIG_PATH)
 export PATH := $(BREW_PREFIX)/bison/bin:$(BREW_PREFIX)/gettext/bin:$(BREW_PREFIX)/flex/bin:$(PATH)
@@ -129,19 +131,19 @@ export PATH := $(BREW_PREFIX)/bison/bin:$(BREW_PREFIX)/gettext/bin:$(BREW_PREFIX
 else ifneq ($(shell :; command -v port),)
 PORT_PREFIX := $(patsubst %/bin/port,%,$(shell :; command -v port))
 CXXFLAGS += -I$(PORT_PREFIX)/include
-LDFLAGS += -L$(PORT_PREFIX)/lib
+LINKFLAGS += -L$(PORT_PREFIX)/lib
 PKG_CONFIG_PATH := $(PORT_PREFIX)/lib/pkgconfig:$(PKG_CONFIG_PATH)
 export PATH := $(PORT_PREFIX)/bin:$(PATH)
 endif
 
 else
-LDFLAGS += -rdynamic
+LINKFLAGS += -rdynamic
 ifneq ($(OS), OpenBSD)
-LDLIBS += -lrt
+LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.32
+YOSYS_VER := 0.42+30
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -149,8 +151,7 @@ YOSYS_VER := 0.32
 # back to calling git directly.
 TARBALL_GIT_REV := $(shell cat $(YOSYS_SRC)/.gitcommit)
 ifeq ($(TARBALL_GIT_REV),$$Format:%h$$)
-#GIT_REV := $(shell GIT_DIR=$(YOSYS_SRC)/.git git rev-parse --short=9 HEAD || echo UNKNOWN)
-GIT_REV := $(shell echo UNKNOWN)
+GIT_REV := $(shell GIT_DIR=$(YOSYS_SRC)/.git git rev-parse --short=9 HEAD || echo UNKNOWN)
 else
 GIT_REV := $(TARBALL_GIT_REV)
 endif
@@ -158,17 +159,8 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline f3c6b41.. | wc -l`/;" Makefile
-
-# set 'ABCREV = default' to use abc/ as it is
-#
-# Note: If you do ABC development, make sure that 'abc' in this directory
-# is just a symlink to your actual ABC working directory, as 'make mrproper'
-# will remove the 'abc' directory and you do not want to accidentally
-# delete your work on ABC..
-ABCREV = bb64142
-ABCPULL = 1
-ABCURL ?= https://github.com/YosysHQ/abc
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9b6afcf.. | wc -l`/;" Makefile
+
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 
 # set ABCEXTERNAL = <abc-command> to use an external ABC instance
@@ -216,41 +208,38 @@ ABC_ARCHFLAGS += "-DABC_NO_RLIMIT"
 endif
 
 ifeq ($(CONFIG),clang)
-CXX = clang
-LD = clang++
+CXX = clang++
 CXXFLAGS += -std=$(CXXSTD) -Os
-ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -Wno-c++11-narrowing $(ABC_ARCHFLAGS)"
+ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H $(ABC_ARCHFLAGS)"
 
 ifneq ($(SANITIZER),)
 $(info [Clang Sanitizer] $(SANITIZER))
 CXXFLAGS += -g -O1 -fno-omit-frame-pointer -fno-optimize-sibling-calls -fsanitize=$(SANITIZER)
-LDFLAGS += -g -fsanitize=$(SANITIZER)
+LINKFLAGS += -g -fsanitize=$(SANITIZER)
 ifneq ($(findstring address,$(SANITIZER)),)
 ENABLE_COVER := 0
 endif
 ifneq ($(findstring memory,$(SANITIZER)),)
 CXXFLAGS += -fPIE -fsanitize-memory-track-origins
-LDFLAGS += -fPIE -fsanitize-memory-track-origins
+LINKFLAGS += -fPIE -fsanitize-memory-track-origins
 endif
 ifneq ($(findstring cfi,$(SANITIZER)),)
 CXXFLAGS += -flto
-LDFLAGS += -flto
+LINKFLAGS += -flto
 endif
 endif
 
 else ifeq ($(CONFIG),gcc)
-CXX = gcc
-LD = gcc
+CXX = g++
 CXXFLAGS += -std=$(CXXSTD) -Os
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H $(ABC_ARCHFLAGS)"
 
 else ifeq ($(CONFIG),gcc-static)
-LD = $(CXX)
-LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -static
-LDLIBS := $(filter-out -lrt,$(LDLIBS))
+LINKFLAGS := $(filter-out -rdynamic,$(LINKFLAGS)) -static
+LIBS := $(filter-out -lrt,$(LIBS))
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 CXXFLAGS += -std=$(CXXSTD) -Os
-ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-lm -lpthread -static" OPTFLAGS="-O" \
+ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(CXX)" ABC_USE_LIBSTDCXX=1 LIBS="-lm -lpthread -static" OPTFLAGS="-O" \
                        ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable $(ARCHFLAGS)" ABC_USE_NO_READLINE=1
 ifeq ($(DISABLE_ABC_THREADS),1)
 ABCMKARGS += "ABC_USE_NO_PTHREADS=1"
@@ -258,75 +247,31 @@ endif
 
 else ifeq ($(CONFIG),afl-gcc)
 CXX = AFL_QUIET=1 AFL_HARDEN=1 afl-gcc
-LD = AFL_QUIET=1 AFL_HARDEN=1 afl-gcc
 CXXFLAGS += -std=$(CXXSTD) -Os
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 
 else ifeq ($(CONFIG),cygwin)
-CXX = gcc
-LD = gcc
+CXX = g++
 CXXFLAGS += -std=gnu++11 -Os
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 
-else ifeq ($(CONFIG),emcc)
-CXX = emcc
-LD = emcc
-CXXFLAGS := -std=$(CXXSTD) $(filter-out -fPIC -ggdb,$(CXXFLAGS))
-ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DABC_MEMALIGN=8 -Wno-c++11-narrowing"
-EMCC_CXXFLAGS := -Os -Wno-warn-absolute-paths
-EMCC_LDFLAGS := --memory-init-file 0 --embed-file share
-EMCC_LDFLAGS += -s NO_EXIT_RUNTIME=1
-EMCC_LDFLAGS += -s EXPORTED_FUNCTIONS="['_main','_run','_prompt','_errmsg','_memset']"
-EMCC_LDFLAGS += -s TOTAL_MEMORY=134217728
-EMCC_LDFLAGS += -s EXPORTED_RUNTIME_METHODS='["ccall", "cwrap"]'
-# https://github.com/kripken/emscripten/blob/master/src/settings.js
-CXXFLAGS += $(EMCC_CXXFLAGS)
-LDFLAGS += $(EMCC_LDFLAGS)
-LDLIBS =
-EXE = .js
-
-DISABLE_SPAWN := 1
-
-TARGETS := $(filter-out $(PROGRAM_PREFIX)yosys-config,$(TARGETS))
-EXTRA_TARGETS += yosysjs-$(YOSYS_VER).zip
-
-ifeq ($(ENABLE_ABC),1)
-LINK_ABC := 1
-DISABLE_ABC_THREADS := 1
-endif
-
-viz.js:
-	wget -O viz.js.part https://github.com/mdaines/viz.js/releases/download/0.0.3/viz.js
-	mv viz.js.part viz.js
-
-yosysjs-$(YOSYS_VER).zip: yosys.js viz.js misc/yosysjs/*
-	rm -rf yosysjs-$(YOSYS_VER) yosysjs-$(YOSYS_VER).zip
-	mkdir -p yosysjs-$(YOSYS_VER)
-	cp viz.js misc/yosysjs/* yosys.js yosys.wasm yosysjs-$(YOSYS_VER)/
-	zip -r yosysjs-$(YOSYS_VER).zip yosysjs-$(YOSYS_VER)
-
-yosys.html: misc/yosys.html
-	$(P) cp misc/yosys.html yosys.html
-
 else ifeq ($(CONFIG),wasi)
 ifeq ($(WASI_SDK),)
-CXX = clang
-LD = clang++
+CXX = clang++
 AR = llvm-ar
 RANLIB = llvm-ranlib
 WASIFLAGS := -target wasm32-wasi --sysroot $(WASI_SYSROOT) $(WASIFLAGS)
 else
-CXX = $(WASI_SDK)/bin/clang
-LD = $(WASI_SDK)/bin/clang++
+CXX = $(WASI_SDK)/bin/clang++
 AR = $(WASI_SDK)/bin/ar
 RANLIB = $(WASI_SDK)/bin/ranlib
 WASIFLAGS := --sysroot $(WASI_SDK)/share/wasi-sysroot $(WASIFLAGS)
 endif
-CXXFLAGS := $(WASIFLAGS) -std=$(CXXSTD) -Os $(filter-out -fPIC,$(CXXFLAGS))
-LDFLAGS := $(WASIFLAGS) -Wl,-z,stack-size=1048576 $(filter-out -rdynamic,$(LDFLAGS))
-LDLIBS := $(filter-out -lrt,$(LDLIBS))
+CXXFLAGS := $(WASIFLAGS) -std=$(CXXSTD) -Os -D_WASI_EMULATED_PROCESS_CLOCKS $(filter-out -fPIC,$(CXXFLAGS))
+LINKFLAGS := $(WASIFLAGS) -Wl,-z,stack-size=1048576 $(filter-out -rdynamic,$(LINKFLAGS))
+LIBS := -lwasi-emulated-process-clocks $(filter-out -lrt,$(LIBS))
 ABCMKARGS += AR="$(AR)" RANLIB="$(RANLIB)"
-ABCMKARGS += ARCHFLAGS="$(WASIFLAGS) -DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING -DABC_NO_RLIMIT -Wno-c++11-narrowing"
+ABCMKARGS += ARCHFLAGS="$(WASIFLAGS) -D_WASI_EMULATED_PROCESS_CLOCKS -DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING -DABC_NO_RLIMIT"
 ABCMKARGS += OPTFLAGS="-Os"
 EXE = .wasm
 
@@ -340,40 +285,41 @@ endif
 else ifeq ($(CONFIG),mxe)
 PKG_CONFIG = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-pkg-config
 CXX = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-g++
-LD = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-g++
 CXXFLAGS += -std=$(CXXSTD) -Os -D_POSIX_SOURCE -DYOSYS_MXE_HACKS -Wno-attributes
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
-LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
-LDLIBS := $(filter-out -lrt,$(LDLIBS))
+LINKFLAGS := $(filter-out -rdynamic,$(LINKFLAGS)) -s
+LIBS := $(filter-out -lrt,$(LIBS))
 ABCMKARGS += ARCHFLAGS="-DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
 # TODO: Try to solve pthread linking issue in more appropriate way
-ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" LDFLAGS="-Wl,--allow-multiple-definition" ABC_USE_NO_READLINE=1 CC="/usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc"
+ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" LINKFLAGS="-Wl,--allow-multiple-definition" ABC_USE_NO_READLINE=1 CC="/usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc"
 EXE = .exe
 
 else ifeq ($(CONFIG),msys2-32)
 CXX = i686-w64-mingw32-g++
-LD = i686-w64-mingw32-g++
 CXXFLAGS += -std=$(CXXSTD) -Os -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
-LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
-LDLIBS := $(filter-out -lrt,$(LDLIBS))
+LINKFLAGS := $(filter-out -rdynamic,$(LINKFLAGS)) -s
+LIBS := $(filter-out -lrt,$(LIBS))
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
-ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="i686-w64-mingw32-gcc" CXX="$(CXX)"
+ABCMKARGS += LIBS="-lpthread -lshlwapi -s" ABC_USE_NO_READLINE=0 CC="i686-w64-mingw32-gcc" CXX="$(CXX)"
 EXE = .exe
 
 else ifeq ($(CONFIG),msys2-64)
 CXX = x86_64-w64-mingw32-g++
-LD = x86_64-w64-mingw32-g++
 CXXFLAGS += -std=$(CXXSTD) -Os -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
-LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
-LDLIBS := $(filter-out -lrt,$(LDLIBS))
+LINKFLAGS := $(filter-out -rdynamic,$(LINKFLAGS)) -s
+LIBS := $(filter-out -lrt,$(LIBS))
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
-ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="x86_64-w64-mingw32-gcc" CXX="$(CXX)"
+ABCMKARGS += LIBS="-lpthread -lshlwapi -s" ABC_USE_NO_READLINE=0 CC="x86_64-w64-mingw32-gcc" CXX="$(CXX)"
 EXE = .exe
 
-else ifneq ($(CONFIG),none)
-$(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, emcc, mxe, msys2-32, msys2-64)
+else ifeq ($(CONFIG),none)
+CXXFLAGS += -std=$(CXXSTD) -Os
+ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H $(ABC_ARCHFLAGS)"
+
+else
+$(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, mxe, msys2-32, msys2-64, none)
 endif
 
 ifeq ($(ENABLE_LIBYOSYS),1)
@@ -394,9 +340,9 @@ ifeq ($(BOOST_PYTHON_LIB),)
 $(error BOOST_PYTHON_LIB could not be detected. Please define manually)
 endif
 
-LDLIBS += $(shell $(PYTHON_CONFIG) --libs) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem
-# python-config --ldflags includes LDLIBS for some reason
-LDFLAGS += $(filter-out -l%,$(shell $(PYTHON_CONFIG) --ldflags))
+LIBS += $(shell $(PYTHON_CONFIG) --libs) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem
+# python-config --ldflags includes LIBS for some reason
+LINKFLAGS += $(filter-out -l%,$(shell $(PYTHON_CONFIG) --ldflags))
 CXXFLAGS += $(shell $(PYTHON_CONFIG) --includes) -DWITH_PYTHON
 
 PY_WRAPPER_FILE = kernel/python_wrappers
@@ -410,22 +356,22 @@ CXXFLAGS += -DYOSYS_ENABLE_READLINE
 ifeq ($(OS), $(filter $(OS),FreeBSD OpenBSD NetBSD))
 CXXFLAGS += -I/usr/local/include
 endif
-LDLIBS += -lreadline
+LIBS += -lreadline
 ifeq ($(LINK_CURSES),1)
-LDLIBS += -lcurses
+LIBS += -lcurses
 ABCMKARGS += "ABC_READLINE_LIBRARIES=-lcurses -lreadline"
 endif
 ifeq ($(LINK_TERMCAP),1)
-LDLIBS += -ltermcap
+LIBS += -ltermcap
 ABCMKARGS += "ABC_READLINE_LIBRARIES=-lreadline -ltermcap"
 endif
 ifeq ($(CONFIG),mxe)
-LDLIBS += -ltermcap
+LIBS += -ltermcap
 endif
 else
 ifeq ($(ENABLE_EDITLINE),1)
 CXXFLAGS += -DYOSYS_ENABLE_EDITLINE
-LDLIBS += -ledit -ltinfo -lbsd
+LIBS += -ledit -ltinfo -lbsd
 else
 ABCMKARGS += "ABC_USE_NO_READLINE=1"
 endif
@@ -444,9 +390,9 @@ CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-e
 ifeq ($(OS), MINGW)
 CXXFLAGS += -Ilibs/dlfcn-win32
 endif
-LDLIBS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --libs libffi || echo -lffi)
+LIBS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --libs libffi || echo -lffi)
 ifneq ($(OS), $(filter $(OS),FreeBSD OpenBSD NetBSD MINGW))
-LDLIBS += -ldl
+LIBS += -ldl
 endif
 endif
 
@@ -456,7 +402,7 @@ endif
 
 ifeq ($(ENABLE_ZLIB),1)
 CXXFLAGS += -DYOSYS_ENABLE_ZLIB
-LDLIBS += -lz
+LIBS += -lz
 endif
 
 
@@ -473,21 +419,21 @@ endif
 
 ifeq ($(CONFIG),mxe)
 CXXFLAGS += -DYOSYS_ENABLE_TCL
-LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 -lz -luserenv
+LIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 -lz -luserenv
 else
 CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --cflags tcl || echo -I$(TCL_INCLUDE)) -DYOSYS_ENABLE_TCL
-LDLIBS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --libs tcl || echo $(TCL_LIBS))
+LIBS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --libs tcl || echo $(TCL_LIBS))
 endif
 endif
 
 ifeq ($(ENABLE_GCOV),1)
 CXXFLAGS += --coverage
-LDFLAGS += --coverage
+LINKFLAGS += --coverage
 endif
 
 ifeq ($(ENABLE_GPROF),1)
 CXXFLAGS += -pg
-LDFLAGS += -pg
+LINKFLAGS += -pg
 endif
 
 ifeq ($(ENABLE_NDEBUG),1)
@@ -507,11 +453,11 @@ CXXFLAGS += -DYOSYS_ENABLE_ABC
 ifeq ($(LINK_ABC),1)
 CXXFLAGS += -DYOSYS_LINK_ABC
 ifeq ($(DISABLE_ABC_THREADS),0)
-LDLIBS += -lpthread
+LIBS += -lpthread
 endif
 else
 ifeq ($(ABCEXTERNAL),)
-TARGETS += $(PROGRAM_PREFIX)yosys-abc$(EXE)
+TARGETS := $(PROGRAM_PREFIX)yosys-abc$(EXE) $(TARGETS)
 endif
 endif
 endif
@@ -521,14 +467,30 @@ GHDL_PREFIX ?= $(PREFIX)
 GHDL_INCLUDE_DIR ?= $(GHDL_PREFIX)/include
 GHDL_LIB_DIR ?= $(GHDL_PREFIX)/lib
 CXXFLAGS += -I$(GHDL_INCLUDE_DIR) -DYOSYS_ENABLE_GHDL
-LDLIBS += $(GHDL_LIB_DIR)/libghdl.a $(file <$(GHDL_LIB_DIR)/libghdl.link)
+LIBS += $(GHDL_LIB_DIR)/libghdl.a $(file <$(GHDL_LIB_DIR)/libghdl.link)
 endif
 
-LDLIBS_VERIFIC =
+LIBS_VERIFIC =
 ifeq ($(ENABLE_VERIFIC),1)
 VERIFIC_DIR ?= /usr/local/src/verific_lib
-VERIFIC_COMPONENTS ?= verilog database util containers hier_tree
-ifneq ($(DISABLE_VERIFIC_VHDL),1)
+VERIFIC_COMPONENTS ?= database util containers
+ifeq ($(ENABLE_VERIFIC_HIER_TREE),1)
+VERIFIC_COMPONENTS += hier_tree
+CXXFLAGS += -DVERIFIC_HIER_TREE_SUPPORT
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/hier_tree),)
+VERIFIC_COMPONENTS += hier_tree
+endif
+endif
+ifeq ($(ENABLE_VERIFIC_SYSTEMVERILOG),1)
+VERIFIC_COMPONENTS += verilog
+CXXFLAGS += -DVERIFIC_SYSTEMVERILOG_SUPPORT
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/verilog),)
+VERIFIC_COMPONENTS += verilog
+endif
+endif
+ifeq ($(ENABLE_VERIFIC_VHDL),1)
 VERIFIC_COMPONENTS += vhdl
 CXXFLAGS += -DVERIFIC_VHDL_SUPPORT
 else
@@ -544,15 +506,19 @@ ifeq ($(ENABLE_VERIFIC_LIBERTY),1)
 VERIFIC_COMPONENTS += synlib
 CXXFLAGS += -DVERIFIC_LIBERTY_SUPPORT
 endif
-ifneq ($(DISABLE_VERIFIC_EXTENSIONS),1)
+ifeq ($(ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS),1)
 VERIFIC_COMPONENTS += extensions
 CXXFLAGS += -DYOSYSHQ_VERIFIC_EXTENSIONS
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/extensions),)
+VERIFIC_COMPONENTS += extensions
+endif
 endif
 CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
 ifeq ($(OS), Darwin)
-LDLIBS_VERIFIC += $(foreach comp,$(patsubst %,$(VERIFIC_DIR)/%/*-mac.a,$(VERIFIC_COMPONENTS)),-Wl,-force_load $(comp)) -lz
+LIBS_VERIFIC += $(foreach comp,$(patsubst %,$(VERIFIC_DIR)/%/*-mac.a,$(VERIFIC_COMPONENTS)),-Wl,-force_load $(comp)) -lz
 else
-LDLIBS_VERIFIC += -Wl,--whole-archive $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS)) -Wl,--no-whole-archive -lz
+LIBS_VERIFIC += -Wl,--whole-archive $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS)) -Wl,--no-whole-archive -lz
 endif
 endif
 
@@ -607,31 +573,37 @@ Q =
 S =
 endif
 
-$(eval $(call add_include_file,kernel/yosys.h))
-$(eval $(call add_include_file,kernel/hashlib.h))
-$(eval $(call add_include_file,kernel/log.h))
-$(eval $(call add_include_file,kernel/rtlil.h))
 $(eval $(call add_include_file,kernel/binding.h))
-$(eval $(call add_include_file,kernel/register.h))
 $(eval $(call add_include_file,kernel/cellaigs.h))
-$(eval $(call add_include_file,kernel/celltypes.h))
 $(eval $(call add_include_file,kernel/celledges.h))
+$(eval $(call add_include_file,kernel/celltypes.h))
 $(eval $(call add_include_file,kernel/consteval.h))
 $(eval $(call add_include_file,kernel/constids.inc))
-$(eval $(call add_include_file,kernel/sigtools.h))
-$(eval $(call add_include_file,kernel/modtools.h))
-$(eval $(call add_include_file,kernel/macc.h))
-$(eval $(call add_include_file,kernel/utils.h))
-$(eval $(call add_include_file,kernel/satgen.h))
-$(eval $(call add_include_file,kernel/qcsat.h))
+$(eval $(call add_include_file,kernel/cost.h))
 $(eval $(call add_include_file,kernel/ff.h))
 $(eval $(call add_include_file,kernel/ffinit.h))
+$(eval $(call add_include_file,kernel/ffmerge.h))
+$(eval $(call add_include_file,kernel/fmt.h))
 ifeq ($(ENABLE_ZLIB),1)
 $(eval $(call add_include_file,kernel/fstdata.h))
 endif
+$(eval $(call add_include_file,kernel/hashlib.h))
+$(eval $(call add_include_file,kernel/json.h))
+$(eval $(call add_include_file,kernel/log.h))
+$(eval $(call add_include_file,kernel/macc.h))
+$(eval $(call add_include_file,kernel/modtools.h))
 $(eval $(call add_include_file,kernel/mem.h))
+$(eval $(call add_include_file,kernel/qcsat.h))
+$(eval $(call add_include_file,kernel/register.h))
+$(eval $(call add_include_file,kernel/rtlil.h))
+$(eval $(call add_include_file,kernel/satgen.h))
+$(eval $(call add_include_file,kernel/scopeinfo.h))
+$(eval $(call add_include_file,kernel/sigtools.h))
+$(eval $(call add_include_file,kernel/timinginfo.h))
+$(eval $(call add_include_file,kernel/utils.h))
+$(eval $(call add_include_file,kernel/yosys.h))
+$(eval $(call add_include_file,kernel/yosys_common.h))
 $(eval $(call add_include_file,kernel/yw.h))
-$(eval $(call add_include_file,kernel/json.h))
 $(eval $(call add_include_file,libs/ezsat/ezsat.h))
 $(eval $(call add_include_file,libs/ezsat/ezminisat.h))
 ifeq ($(ENABLE_ZLIB),1)
@@ -644,21 +616,10 @@ $(eval $(call add_include_file,frontends/ast/ast.h))
 $(eval $(call add_include_file,frontends/ast/ast_binding.h))
 $(eval $(call add_include_file,frontends/blif/blifparse.h))
 $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h))
-$(eval $(call add_include_file,backends/cxxrtl/cxxrtl.h))
-$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd.h))
-$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_capi.cc))
-$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_capi.h))
-$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.cc))
-$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.h))
 
 OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
 OBJS += kernel/binding.o
-ifeq ($(ENABLE_ABC),1)
-ifneq ($(ABCEXTERNAL),)
-kernel/yosys.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
-endif
-endif
-OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o
+OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o
 ifeq ($(ENABLE_ZLIB),1)
 OBJS += kernel/fstdata.o
 endif
@@ -670,18 +631,19 @@ endif
 
 kernel/log.o: CXXFLAGS += -DYOSYS_SRC='"$(YOSYS_SRC)"'
 kernel/yosys.o: CXXFLAGS += -DYOSYS_DATDIR='"$(DATDIR)"' -DYOSYS_PROGRAM_PREFIX='"$(PROGRAM_PREFIX)"'
+ifeq ($(ENABLE_ABC),1)
+ifneq ($(ABCEXTERNAL),)
+kernel/yosys.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
+endif
+endif
 
 OBJS += libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o
 OBJS += libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o
 
 OBJS += libs/sha1/sha1.o
 
-ifneq ($(SMALL),1)
-
 OBJS += libs/json11/json11.o
 
-OBJS += libs/subcircuit/subcircuit.o
-
 OBJS += libs/ezsat/ezsat.o
 OBJS += libs/ezsat/ezminisat.o
 
@@ -696,6 +658,10 @@ OBJS += libs/fst/fastlz.o
 OBJS += libs/fst/lz4.o
 endif
 
+ifneq ($(SMALL),1)
+
+OBJS += libs/subcircuit/subcircuit.o
+
 include $(YOSYS_SRC)/frontends/*/Makefile.inc
 include $(YOSYS_SRC)/passes/*/Makefile.inc
 include $(YOSYS_SRC)/backends/*/Makefile.inc
@@ -704,6 +670,9 @@ include $(YOSYS_SRC)/techlibs/*/Makefile.inc
 else
 
 include $(YOSYS_SRC)/frontends/verilog/Makefile.inc
+ifeq ($(ENABLE_VERIFIC),1)
+include $(YOSYS_SRC)/frontends/verific/Makefile.inc
+endif
 include $(YOSYS_SRC)/frontends/rtlil/Makefile.inc
 include $(YOSYS_SRC)/frontends/ast/Makefile.inc
 include $(YOSYS_SRC)/frontends/blif/Makefile.inc
@@ -740,18 +709,20 @@ top-all: $(TARGETS) $(EXTRA_TARGETS)
 	@echo "  Build successful."
 	@echo ""
 
-ifeq ($(CONFIG),emcc)
-yosys.js: $(filter-out yosysjs-$(YOSYS_VER).zip,$(EXTRA_TARGETS))
-endif
+.PHONY: compile-only
+compile-only: $(OBJS) $(GENFILES) $(EXTRA_TARGETS)
+	@echo ""
+	@echo "  Compile successful."
+	@echo ""
 
 $(PROGRAM_PREFIX)yosys$(EXE): $(OBJS)
-	$(P) $(LD) -o $(PROGRAM_PREFIX)yosys$(EXE) $(EXE_LDFLAGS) $(LDFLAGS) $(OBJS) $(LDLIBS) $(LDLIBS_VERIFIC)
+	$(P) $(CXX) -o $(PROGRAM_PREFIX)yosys$(EXE) $(EXE_LINKFLAGS) $(LINKFLAGS) $(OBJS) $(LIBS) $(LIBS_VERIFIC)
 
 libyosys.so: $(filter-out kernel/driver.o,$(OBJS))
 ifeq ($(OS), Darwin)
-	$(P) $(LD) -o libyosys.so -shared -Wl,-install_name,$(LIBDIR)/libyosys.so $(LDFLAGS) $^ $(LDLIBS) $(LDLIBS_VERIFIC)
+	$(P) $(CXX) -o libyosys.so -shared -Wl,-install_name,$(LIBDIR)/libyosys.so $(LINKFLAGS) $^ $(LIBS) $(LIBS_VERIFIC)
 else
-	$(P) $(LD) -o libyosys.so -shared -Wl,-soname,$(LIBDIR)/libyosys.so $(LDFLAGS) $^ $(LDLIBS) $(LDLIBS_VERIFIC)
+	$(P) $(CXX) -o libyosys.so -shared -Wl,-soname,$(LIBDIR)/libyosys.so $(LINKFLAGS) $^ $(LIBS) $(LIBS_VERIFIC)
 endif
 
 %.o: %.cc
@@ -760,7 +731,7 @@ endif
 
 %.pyh: %.h
 	$(Q) mkdir -p $(dir $@)
-	$(P) cat $< | grep -E -v "#[ ]*(include|error)" | $(LD) $(CXXFLAGS) -x c++ -o $@ -E -P -
+	$(P) cat $< | grep -E -v "#[ ]*(include|error)" | $(CXX) $(CXXFLAGS) -x c++ -o $@ -E -P -
 
 ifeq ($(ENABLE_PYOSYS),1)
 $(PY_WRAPPER_FILE).cc: misc/$(PY_GEN_SCRIPT).py $(PY_WRAP_INCLUDES)
@@ -781,53 +752,52 @@ kernel/version_$(GIT_REV).cc: $(YOSYS_SRC)/Makefile
 
 ifeq ($(ENABLE_VERIFIC),1)
 CXXFLAGS_NOVERIFIC = $(foreach v,$(CXXFLAGS),$(if $(findstring $(VERIFIC_DIR),$(v)),,$(v)))
-LDLIBS_NOVERIFIC = $(foreach v,$(LDLIBS),$(if $(findstring $(VERIFIC_DIR),$(v)),,$(v)))
+LIBS_NOVERIFIC = $(foreach v,$(LIBS),$(if $(findstring $(VERIFIC_DIR),$(v)),,$(v)))
 else
 CXXFLAGS_NOVERIFIC = $(CXXFLAGS)
-LDLIBS_NOVERIFIC = $(LDLIBS)
+LIBS_NOVERIFIC = $(LIBS)
 endif
 
 $(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in
 	$(P) $(SED) -e 's#@CXXFLAGS@#$(subst -Ilibs/dlfcn-win32,,$(subst -I. -I"$(YOSYS_SRC)",-I"$(DATDIR)/include",$(strip $(CXXFLAGS_NOVERIFIC))))#;' \
-			-e 's#@CXX@#$(strip $(CXX))#;' -e 's#@LDFLAGS@#$(strip $(LDFLAGS) $(PLUGIN_LDFLAGS))#;' -e 's#@LDLIBS@#$(strip $(LDLIBS_NOVERIFIC) $(PLUGIN_LDLIBS))#;' \
+			-e 's#@CXX@#$(strip $(CXX))#;' -e 's#@LINKFLAGS@#$(strip $(LINKFLAGS) $(PLUGIN_LINKFLAGS))#;' -e 's#@LIBS@#$(strip $(LIBS_NOVERIFIC) $(PLUGIN_LIBS))#;' \
 			-e 's#@BINDIR@#$(strip $(BINDIR))#;' -e 's#@DATDIR@#$(strip $(DATDIR))#;' < $< > $(PROGRAM_PREFIX)yosys-config
 	$(Q) chmod +x $(PROGRAM_PREFIX)yosys-config
 
-abc/abc-$(ABCREV)$(EXE) abc/libabc-$(ABCREV).a:
-	$(P)
-ifneq ($(ABCREV),default)
-	$(Q) if test -d abc/.hg; then \
-		echo 'REEBE: NOP qverpgbel vf n ut jbexvat pbcl! Erzbir nop/ naq er-eha "znxr".' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; false; \
-	fi
-	$(Q) if test -d abc && test -d abc/.git && ! git -C abc diff-index --quiet HEAD; then \
-		echo 'REEBE: NOP pbagnvaf ybpny zbqvsvpngvbaf! Frg NOPERI=qrsnhyg va Lbflf Znxrsvyr!' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; false; \
+.PHONY: check-git-abc
+
+check-git-abc:
+	@if [ ! -d "$(YOSYS_SRC)/abc" ]; then \
+		echo "Error: The 'abc' directory does not exist."; \
+		echo "Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
+		exit 1; \
+	elif git -C "$(YOSYS_SRC)" submodule status abc 2>/dev/null | grep -q '^ '; then \
+		exit 0; \
+	elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && ! grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
+		echo "'abc' comes from a tarball. Continuing."; \
+		exit 0; \
+	elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
+		echo "Error: 'abc' is not configured as a git submodule."; \
+		echo "To resolve this:"; \
+		echo "1. Back up your changes: Save any modifications from the 'abc' directory to another location."; \
+		echo "2. Remove the existing 'abc' directory: Delete the 'abc' directory and all its contents."; \
+		echo "3. Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
+		echo "4. Reapply your changes: Move your saved changes back to the 'abc' directory, if necessary."; \
+		exit 1; \
+	else \
+		echo "Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
+		exit 1; \
 	fi
-	$(Q) if test -d abc && ! test -d abc/.git && ! test "`cat abc/.gitcommit | cut -c1-7`" = "$(ABCREV)"; then \
-		echo 'REEBE: Qbjaybnqrq NOP irefvbaf qbrf abg zngpu! Qbjaybnq sebz:' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; echo $(ABCURL)/archive/$(ABCREV).tar.gz; false; \
-	fi
-# set a variable so the test fails if git fails to run - when comparing outputs directly, empty string would match empty string
-	$(Q) if test -d abc && ! test -d abc/.git && test "`cat abc/.gitcommit | cut -c1-7`" = "$(ABCREV)"; then \
-		echo "Compiling local copy of ABC"; \
-	elif ! (cd abc 2> /dev/null && rev="`git rev-parse $(ABCREV)`" && test "`git rev-parse HEAD`" = "$$rev"); then \
-		test $(ABCPULL) -ne 0 || { echo 'REEBE: NOP abg hc gb qngr naq NOPCHYY frg gb 0 va Znxrsvyr!' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; exit 1; }; \
-		echo "Pulling ABC from $(ABCURL):"; set -x; \
-		test -d abc || git clone $(ABCURL) abc; \
-		cd abc && $(MAKE) DEP= clean && git fetch $(ABCURL) && git checkout $(ABCREV); \
-	fi
-endif
-	$(Q) rm -f abc/abc-[0-9a-f]*
-	$(Q) $(MAKE) -C abc $(S) $(ABCMKARGS) $(if $(filter %.a,$@),PROG="abc-$(ABCREV)",PROG="abc-$(ABCREV)$(EXE)") MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " $(if $(filter %.a,$@),libabc-$(ABCREV).a)
 
-ifeq ($(ABCREV),default)
-.PHONY: abc/abc-$(ABCREV)$(EXE)
-.PHONY: abc/libabc-$(ABCREV).a
-endif
+abc/abc$(EXE) abc/libabc.a: check-git-abc
+	$(P)
+	$(Q) mkdir -p abc && $(MAKE) -C $(PROGRAM_PREFIX)abc -f "$(realpath $(YOSYS_SRC)/abc/Makefile)" ABCSRC="$(realpath $(YOSYS_SRC)/abc/)" $(S) $(ABCMKARGS) $(if $(filter %.a,$@),PROG="abc",PROG="abc$(EXE)") MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " $(if $(filter %.a,$@),libabc.a)
 
-$(PROGRAM_PREFIX)yosys-abc$(EXE): abc/abc-$(ABCREV)$(EXE)
-	$(P) cp abc/abc-$(ABCREV)$(EXE) $(PROGRAM_PREFIX)yosys-abc$(EXE)
+$(PROGRAM_PREFIX)yosys-abc$(EXE): abc/abc$(EXE)
+	$(P) cp $< $(PROGRAM_PREFIX)yosys-abc$(EXE)
 
-$(PROGRAM_PREFIX)yosys-libabc.a: abc/libabc-$(ABCREV).a
-	$(P) cp abc/libabc-$(ABCREV).a $(PROGRAM_PREFIX)yosys-libabc.a
+$(PROGRAM_PREFIX)yosys-libabc.a: abc/libabc.a
+	$(P) cp $< $(PROGRAM_PREFIX)yosys-libabc.a
 
 ifneq ($(SEED),)
 SEEDOPT="-S $(SEED)"
@@ -841,9 +811,22 @@ else
 ABCOPT=""
 endif
 
+# When YOSYS_NOVERIFIC is set as a make variable, also export it to the
+# enviornment, so that `YOSYS_NOVERIFIC=1 make test` _and_
+# `make test YOSYS_NOVERIFIC=1` will run with verific disabled.
+ifeq ($(YOSYS_NOVERIFIC),1)
+export YOSYS_NOVERIFIC
+endif
+
 test: $(TARGETS) $(EXTRA_TARGETS)
 ifeq ($(ENABLE_VERIFIC),1)
+ifeq ($(YOSYS_NOVERIFIC),1)
+	@echo
+	@echo "Running tests without verific support due to YOSYS_NOVERIFIC=1"
+	@echo
+else
 	+cd tests/verific && bash run-test.sh $(SEEDOPT)
+endif
 endif
 	+cd tests/simple && bash run-test.sh $(SEEDOPT)
 	+cd tests/simple_abc9 && bash run-test.sh $(SEEDOPT)
@@ -877,12 +860,15 @@ endif
 	+cd tests/arch/gowin && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/nexus && bash run-test.sh $(SEEDOPT)
-	+cd tests/arch/quicklogic && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/quicklogic/pp3 && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/quicklogic/qlf_k6n10f && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/gatemate && bash run-test.sh $(SEEDOPT)
 	+cd tests/rpc && bash run-test.sh
 	+cd tests/memfile && bash run-test.sh
 	+cd tests/verilog && bash run-test.sh
 	+cd tests/xprop && bash run-test.sh $(SEEDOPT)
+	+cd tests/fmt && bash run-test.sh
+	+cd tests/cxxrtl && bash run-test.sh
 	@echo ""
 	@echo "  Passed \"make test\"."
 	@echo ""
@@ -912,7 +898,7 @@ ystests: $(TARGETS) $(EXTRA_TARGETS)
 # Unit test
 unit-test: libyosys.so
 	@$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CPPFLAGS="$(CPPFLAGS)" \
-		CXXFLAGS="$(CXXFLAGS)" LDLIBS="$(LDLIBS)" ROOTPATH="$(CURDIR)"
+		CXXFLAGS="$(CXXFLAGS)" LIBS="$(LIBS)" ROOTPATH="$(CURDIR)"
 
 clean-unit-test:
 	@$(MAKE) -C $(UNITESTPATH) clean
@@ -965,17 +951,47 @@ docs/source/cmd/abc.rst: $(TARGETS) $(EXTRA_TARGETS)
 	mkdir -p docs/source/cmd
 	./$(PROGRAM_PREFIX)yosys -p 'help -write-rst-command-reference-manual'
 
-PHONY: docs/gen_images docs/guidelines
+PHONY: docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs
+docs/gen_examples:
+	$(Q) $(MAKE) -C docs examples
+
 docs/gen_images:
-	$(Q) $(MAKE) -C docs/images all
+	$(Q) $(MAKE) -C docs images
 
 DOCS_GUIDELINE_FILES := GettingStarted CodingStyle
-docs/guidelines:
-	$(Q) mkdir -p docs/source/temp
-	$(Q) cp -f $(addprefix guidelines/,$(DOCS_GUIDELINE_FILES)) docs/source/temp
+docs/guidelines docs/source/generated:
+	$(Q) mkdir -p docs/source/generated
+	$(Q) cp -f $(addprefix guidelines/,$(DOCS_GUIDELINE_FILES)) docs/source/generated
+
+# some commands return an error and print the usage text to stderr
+define DOC_USAGE_STDERR
+docs/source/generated/$(1): $(PROGRAM_PREFIX)$(1) docs/source/generated
+	-$(Q) ./$$< --help 2> $$@
+endef
+DOCS_USAGE_STDERR := yosys-config yosys-filterlib
+
+# The in-tree ABC (yosys-abc) is only built when ABCEXTERNAL is not set.
+ifeq ($(ABCEXTERNAL),)
+DOCS_USAGE_STDERR += yosys-abc
+endif
+
+$(foreach usage,$(DOCS_USAGE_STDERR),$(eval $(call DOC_USAGE_STDERR,$(usage))))
+
+# others print to stdout
+define DOC_USAGE_STDOUT
+docs/source/generated/$(1): $(PROGRAM_PREFIX)$(1) docs/source/generated
+	$(Q) ./$$< --help > $$@
+endef
+DOCS_USAGE_STDOUT := yosys yosys-smtbmc yosys-witness
+$(foreach usage,$(DOCS_USAGE_STDOUT),$(eval $(call DOC_USAGE_STDOUT,$(usage))))
+
+docs/usage: $(addprefix docs/source/generated/,$(DOCS_USAGE_STDOUT) $(DOCS_USAGE_STDERR))
+
+docs/reqs:
+	$(Q) $(MAKE) -C docs reqs
 
 DOC_TARGET ?= html
-docs: docs/source/cmd/abc.rst docs/gen_images docs/guidelines
+docs: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs
 	$(Q) $(MAKE) -C docs $(DOC_TARGET)
 
 clean:
@@ -993,8 +1009,8 @@ clean:
 	rm -rf vloghtb/Makefile vloghtb/refdat vloghtb/rtl vloghtb/scripts vloghtb/spec vloghtb/check_yosys vloghtb/vloghammer_tb.tar.bz2 vloghtb/temp vloghtb/log_test_*
 	rm -f tests/svinterfaces/*.log_stdout tests/svinterfaces/*.log_stderr tests/svinterfaces/dut_result.txt tests/svinterfaces/reference_result.txt tests/svinterfaces/a.out tests/svinterfaces/*_syn.v tests/svinterfaces/*.diff
 	rm -f  tests/tools/cmp_tbdata
-	$(MAKE) -C docs clean
-	$(MAKE) -C docs/images clean
+	-$(MAKE) -C docs clean
+	-$(MAKE) -C docs/images clean
 	rm -rf docs/source/cmd docs/util/__pycache__
 
 clean-abc:
@@ -1011,11 +1027,12 @@ coverage:
 	genhtml coverage.info --output-directory coverage_html
 
 qtcreator:
+	echo "$(CXXFLAGS)" | grep -o '\-D[^ ]*' | tr ' ' '\n' | sed 's/-D/#define /' | sed 's/=/ /'> qtcreator.config
 	{ for file in $(basename $(OBJS)); do \
 		for prefix in cc y l; do if [ -f $${file}.$${prefix} ]; then echo $$file.$${prefix}; fi; done \
 	done; find backends frontends kernel libs passes -type f \( -name '*.h' -o -name '*.hh' \); } > qtcreator.files
 	{ echo .; find backends frontends kernel libs passes -type f \( -name '*.h' -o -name '*.hh' \) -printf '%h\n' | sort -u; } > qtcreator.includes
-	touch qtcreator.config qtcreator.creator
+	touch qtcreator.creator
 
 vcxsrc: $(GENFILES) $(EXTRA_TARGETS)
 	rm -rf yosys-win32-vcxsrc-$(YOSYS_VER){,.zip}
@@ -1058,14 +1075,6 @@ config-gcc-static: clean
 config-afl-gcc: clean
 	echo 'CONFIG := afl-gcc' > Makefile.conf
 
-config-emcc: clean
-	echo 'CONFIG := emcc' > Makefile.conf
-	echo 'ENABLE_TCL := 0' >> Makefile.conf
-	echo 'ENABLE_ABC := 0' >> Makefile.conf
-	echo 'ENABLE_PLUGINS := 0' >> Makefile.conf
-	echo 'ENABLE_READLINE := 0' >> Makefile.conf
-	echo 'ENABLE_ZLIB := 0' >> Makefile.conf
-
 config-wasi: clean
 	echo 'CONFIG := wasi' > Makefile.conf
 	echo 'ENABLE_TCL := 0' >> Makefile.conf
@@ -1107,8 +1116,8 @@ echo-yosys-ver:
 echo-git-rev:
 	@echo "$(GIT_REV)"
 
-echo-abc-rev:
-	@echo "$(ABCREV)"
+echo-cxx:
+	@echo "$(CXX)"
 
 -include libs/*/*.d
 -include frontends/*/*.d
diff --git a/yosys/README.md b/yosys/README.md
index 5e5a8ec3e12..4647efbe9d1 100644
--- a/yosys/README.md
+++ b/yosys/README.md
@@ -1,7 +1,7 @@
 ```
 yosys -- Yosys Open SYnthesis Suite
 
-Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>
+Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>
 
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above
@@ -105,11 +105,17 @@ For Cygwin use the following command to install all prerequisites, or select the
 
 	setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel
 
-To configure the build system to use a specific compiler, use one of
+The environment variable `CXX` can be used to control the C++ compiler used, or
+run one of the following:
 
 	$ make config-clang
 	$ make config-gcc
 
+Note that these will result in `make` ignoring the `CXX` environment variable,
+unless `CXX` is assigned in the call to make, e.g.
+
+  $ make CXX=$CXX
+
 For other compilers and build configurations it might be
 necessary to make some changes to the config section of the
 Makefile.
@@ -587,11 +593,19 @@ from SystemVerilog:
 - enums are supported (including inside packages)
 	- but are currently not strongly typed
 
-- packed structs and unions are supported.
+- packed structs and unions are supported
+	- arrays of packed structs/unions are currently not supported
+	- structure literals are currently not supported
+
+- multidimensional arrays are supported
+	- array assignment of unpacked arrays is currently not supported
+	- array literals are currently not supported
 
 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
   ports are inputs or outputs are supported.
 
+- Assignments within expressions are supported.
+
 
 Building the documentation
 ==========================
@@ -602,10 +616,12 @@ Simply visit https://yosys.readthedocs.io/en/latest/ instead.
 In addition to those packages listed above for building Yosys from source, the
 following are used for building the website: 
 
-	$ sudo apt-get install pdf2svg faketime
+	$ sudo apt install pdf2svg faketime
 
 PDFLaTeX, included with most LaTeX distributions, is also needed during the
-build process for the website.
+build process for the website.  Or, run the following:
+
+	$ sudo apt install texlive-latex-base texlive-latex-extra latexmk
 
 The Python package, Sphinx, is needed along with those listed in
 `docs/source/requirements.txt`:
diff --git a/yosys/backends/aiger/aiger.cc b/yosys/backends/aiger/aiger.cc
index bb804f230fb..f2cb5d9bcc7 100644
--- a/yosys/backends/aiger/aiger.cc
+++ b/yosys/backends/aiger/aiger.cc
@@ -54,6 +54,8 @@ struct AigerWriter
 
 	vector<pair<int, int>> aig_gates;
 	vector<int> aig_latchin, aig_latchinit, aig_outputs;
+	vector<SigBit> bit2aig_stack;
+	size_t next_loop_check = 1024;
 	int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
 	int aig_b = 0, aig_c = 0, aig_j = 0, aig_f = 0;
 
@@ -65,6 +67,8 @@ struct AigerWriter
 	int initstate_ff = 0;
 
 	dict<SigBit, int> ywmap_clocks;
+	vector<Cell *> ywmap_asserts;
+	vector<Cell *> ywmap_assumes;
 
 	int mkgate(int a0, int a1)
 	{
@@ -81,6 +85,23 @@ struct AigerWriter
 			return it->second;
 		}
 
+		if (bit2aig_stack.size() == next_loop_check) {
+			for (size_t i = 0; i < next_loop_check; ++i)
+			{
+				SigBit report_bit = bit2aig_stack[i];
+				if (report_bit != bit)
+					continue;
+				for (size_t j = i; j < next_loop_check; ++j) {
+					report_bit = bit2aig_stack[j];
+					if (report_bit.is_wire() && report_bit.wire->name.isPublic())
+						break;
+				}
+				log_error("Found combinational logic loop while processing signal %s.\n", log_signal(report_bit));
+			}
+			next_loop_check *= 2;
+		}
+		bit2aig_stack.push_back(bit);
+
 		// NB: Cannot use iterator returned from aig_map.insert()
 		//     since this function is called recursively
 
@@ -101,6 +122,8 @@ struct AigerWriter
 			a = initstate_ff;
 		}
 
+		bit2aig_stack.pop_back();
+
 		if (bit == State::Sx || bit == State::Sz)
 			log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
 
@@ -248,6 +271,7 @@ struct AigerWriter
 				unused_bits.erase(A);
 				unused_bits.erase(EN);
 				asserts.push_back(make_pair(A, EN));
+				ywmap_asserts.push_back(cell);
 				continue;
 			}
 
@@ -258,6 +282,7 @@ struct AigerWriter
 				unused_bits.erase(A);
 				unused_bits.erase(EN);
 				assumes.push_back(make_pair(A, EN));
+				ywmap_assumes.push_back(cell);
 				continue;
 			}
 
@@ -299,6 +324,9 @@ struct AigerWriter
 				continue;
 			}
 
+			if (cell->type == ID($scopeinfo))
+				continue;
+
 			log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
 		}
 
@@ -828,6 +856,19 @@ struct AigerWriter
 		for (auto &it : init_lines)
 			json.value(it.second);
 		json.end_array();
+
+		json.name("asserts");
+		json.begin_array();
+		for (Cell *cell : ywmap_asserts)
+			json.value(witness_path(cell));
+		json.end_array();
+
+		json.name("assumes");
+		json.begin_array();
+		for (Cell *cell : ywmap_assumes)
+			json.value(witness_path(cell));
+		json.end_array();
+
 		json.end_object();
 	}
 
diff --git a/yosys/backends/blif/blif.cc b/yosys/backends/blif/blif.cc
index 8e2c088c484..788b7f951f2 100644
--- a/yosys/backends/blif/blif.cc
+++ b/yosys/backends/blif/blif.cc
@@ -226,6 +226,9 @@ struct BlifDumper
 
 		for (auto cell : module->cells())
 		{
+			if (cell->type == ID($scopeinfo))
+				continue;
+
 			if (config->unbuf_types.count(cell->type)) {
 				auto portnames = config->unbuf_types.at(cell->type);
 				f << stringf(".names %s %s\n1 1\n",
diff --git a/yosys/backends/btor/test_cells.sh b/yosys/backends/btor/test_cells.sh
index 0a011932d22..f8bd797825e 100755
--- a/yosys/backends/btor/test_cells.sh
+++ b/yosys/backends/btor/test_cells.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -ex
 
diff --git a/yosys/backends/cxxrtl/Makefile.inc b/yosys/backends/cxxrtl/Makefile.inc
index aaa304502e0..dd77d2ad360 100644
--- a/yosys/backends/cxxrtl/Makefile.inc
+++ b/yosys/backends/cxxrtl/Makefile.inc
@@ -1,2 +1,11 @@
 
 OBJS += backends/cxxrtl/cxxrtl_backend.o
+
+$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/cxxrtl.h))
+$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h))
+$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h))
+$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h))
+$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc))
+$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h))
+$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc))
+$(eval $(call add_include_file,backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h))
diff --git a/yosys/backends/cxxrtl/cxxrtl_backend.cc b/yosys/backends/cxxrtl/cxxrtl_backend.cc
index 1b13985ab4e..8dc14863d60 100644
--- a/yosys/backends/cxxrtl/cxxrtl_backend.cc
+++ b/yosys/backends/cxxrtl/cxxrtl_backend.cc
@@ -24,6 +24,8 @@
 #include "kernel/celltypes.h"
 #include "kernel/mem.h"
 #include "kernel/log.h"
+#include "kernel/fmt.h"
+#include "kernel/scopeinfo.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -217,7 +219,7 @@ bool is_internal_cell(RTLIL::IdString type)
 
 bool is_effectful_cell(RTLIL::IdString type)
 {
-	return type.isPublic();
+	return type.in(ID($print), ID($check));
 }
 
 bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
@@ -281,6 +283,7 @@ struct FlowGraph {
 			CONNECT,
 			CELL_SYNC,
 			CELL_EVAL,
+			EFFECT_SYNC,
 			PROCESS_SYNC,
 			PROCESS_CASE,
 			MEM_RDPORT,
@@ -290,6 +293,7 @@ struct FlowGraph {
 		Type type;
 		RTLIL::SigSig connect = {};
 		const RTLIL::Cell *cell = nullptr;
+		std::vector<const RTLIL::Cell*> cells;
 		const RTLIL::Process *process = nullptr;
 		const Mem *mem = nullptr;
 		int portidx;
@@ -477,6 +481,15 @@ struct FlowGraph {
 		return node;
 	}
 
+	Node *add_effect_sync_node(std::vector<const RTLIL::Cell*> cells)
+	{
+		Node *node = new Node;
+		node->type = Node::Type::EFFECT_SYNC;
+		node->cells = cells;
+		nodes.push_back(node);
+		return node;
+	}
+
 	// Processes
 	void add_case_rule_defs_uses(Node *node, const RTLIL::CaseRule *case_)
 	{
@@ -593,22 +606,30 @@ std::vector<std::string> split_by(const std::string &str, const std::string &sep
 	return result;
 }
 
-std::string escape_cxx_string(const std::string &input)
+std::string escape_c_string(const std::string &input)
 {
-	std::string output = "\"";
+	std::string output;
+	output.push_back('"');
 	for (auto c : input) {
 		if (::isprint(c)) {
 			if (c == '\\')
 				output.push_back('\\');
 			output.push_back(c);
 		} else {
-			char l = c & 0xf, h = (c >> 4) & 0xf;
-			output.append("\\x");
-			output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
-			output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
+			char l = c & 0x3, m = (c >> 3) & 0x3, h = (c >> 6) & 0x3;
+			output.append("\\");
+			output.push_back('0' + h);
+			output.push_back('0' + m);
+			output.push_back('0' + l);
 		}
 	}
 	output.push_back('"');
+	return output;
+}
+
+std::string escape_cxx_string(const std::string &input)
+{
+	std::string output = escape_c_string(input);
 	if (output.find('\0') != std::string::npos) {
 		output.insert(0, "std::string {");
 		output.append(stringf(", %zu}", input.size()));
@@ -616,6 +637,20 @@ std::string escape_cxx_string(const std::string &input)
 	return output;
 }
 
+std::string basename(const std::string &filepath)
+{
+#ifdef _WIN32
+	const std::string dir_seps = "\\/";
+#else
+	const std::string dir_seps = "/";
+#endif
+	size_t sep_pos = filepath.find_last_of(dir_seps);
+	if (sep_pos != std::string::npos)
+		return filepath.substr(sep_pos + 1);
+	else
+		return filepath;
+}
+
 template<class T>
 std::string get_hdl_name(T *object)
 {
@@ -681,6 +716,7 @@ struct CxxrtlWorker {
 	bool split_intf = false;
 	std::string intf_filename;
 	std::string design_ns = "cxxrtl_design";
+	std::string print_output = "std::cout";
 	std::ostream *impl_f = nullptr;
 	std::ostream *intf_f = nullptr;
 
@@ -1102,7 +1138,7 @@ struct CxxrtlWorker {
 		f << indent << "// cell " << cell->name.str() << " syncs\n";
 		for (auto conn : cell->connections())
 			if (cell->output(conn.first))
-				if (is_cxxrtl_sync_port(cell, conn.first)) {
+				if (is_cxxrtl_sync_port(cell, conn.first) && !conn.second.empty()) {
 					f << indent;
 					dump_sigspec_lhs(conn.second, for_debug);
 					f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";
@@ -1189,6 +1225,144 @@ struct CxxrtlWorker {
 		}
 	}
 
+	void dump_print(const RTLIL::Cell *cell)
+	{
+		Fmt fmt;
+		fmt.parse_rtlil(cell);
+
+		f << indent << "if (";
+		dump_sigspec_rhs(cell->getPort(ID::EN));
+		f << " == value<1>{1u}) {\n";
+		inc_indent();
+			dict<std::string, RTLIL::SigSpec> fmt_args;
+			f << indent << "struct : public lazy_fmt {\n";
+			inc_indent();
+				f << indent << "std::string operator() () const override {\n";
+				inc_indent();
+					fmt.emit_cxxrtl(f, indent, [&](const RTLIL::SigSpec &sig) {
+						if (sig.size() == 0)
+							f << "value<0>()";
+						else {
+							std::string arg_name = "arg" + std::to_string(fmt_args.size());
+							fmt_args[arg_name] = sig;
+							f << arg_name;
+						}
+					}, "performer");
+				dec_indent();
+				f << indent << "}\n";
+				f << indent << "struct performer *performer;\n";
+				for (auto arg : fmt_args)
+					f << indent << "value<" << arg.second.size() << "> " << arg.first << ";\n";
+			dec_indent();
+			f << indent << "} formatter;\n";
+			f << indent << "formatter.performer = performer;\n";
+			for (auto arg : fmt_args) {
+				f << indent << "formatter." << arg.first << " = ";
+				dump_sigspec_rhs(arg.second);
+				f << ";\n";
+			}
+			f << indent << "if (performer) {\n";
+			inc_indent();
+				f << indent << "static const metadata_map attributes = ";
+				dump_metadata_map(cell->attributes);
+				f << ";\n";
+				f << indent << "performer->on_print(formatter, attributes);\n";
+			dec_indent();
+			f << indent << "} else {\n";
+			inc_indent();
+				f << indent << print_output << " << formatter();\n";
+			dec_indent();
+			f << indent << "}\n";
+		dec_indent();
+		f << indent << "}\n";
+	}
+
+	void dump_effect(const RTLIL::Cell *cell)
+	{
+		Fmt fmt;
+		fmt.parse_rtlil(cell);
+
+		f << indent << "if (";
+		dump_sigspec_rhs(cell->getPort(ID::EN));
+		f << ") {\n";
+		inc_indent();
+			dict<std::string, RTLIL::SigSpec> fmt_args;
+			f << indent << "struct : public lazy_fmt {\n";
+			inc_indent();
+				f << indent << "std::string operator() () const override {\n";
+				inc_indent();
+					fmt.emit_cxxrtl(f, indent, [&](const RTLIL::SigSpec &sig) {
+						if (sig.size() == 0)
+							f << "value<0>()";
+						else {
+							std::string arg_name = "arg" + std::to_string(fmt_args.size());
+							fmt_args[arg_name] = sig;
+							f << arg_name;
+						}
+					}, "performer");
+				dec_indent();
+				f << indent << "}\n";
+				f << indent << "struct performer *performer;\n";
+				for (auto arg : fmt_args)
+					f << indent << "value<" << arg.second.size() << "> " << arg.first << ";\n";
+			dec_indent();
+			f << indent << "} formatter;\n";
+			f << indent << "formatter.performer = performer;\n";
+			for (auto arg : fmt_args) {
+				f << indent << "formatter." << arg.first << " = ";
+				dump_sigspec_rhs(arg.second);
+				f << ";\n";
+			}
+			if (cell->hasPort(ID::A)) {
+				f << indent << "bool condition = (bool)";
+				dump_sigspec_rhs(cell->getPort(ID::A));
+				f << ";\n";
+			}
+			f << indent << "if (performer) {\n";
+			inc_indent();
+				f << indent << "static const metadata_map attributes = ";
+				dump_metadata_map(cell->attributes);
+				f << ";\n";
+				if (cell->type == ID($print)) {
+					f << indent << "performer->on_print(formatter, attributes);\n";
+				} else if (cell->type == ID($check)) {
+					std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
+					f << indent << "performer->on_check(";
+					if (flavor == "assert")
+						f << "flavor::ASSERT";
+					else if (flavor == "assume")
+						f << "flavor::ASSUME";
+					else if (flavor == "live")
+						f << "flavor::ASSERT_EVENTUALLY";
+					else if (flavor == "fair")
+						f << "flavor::ASSUME_EVENTUALLY";
+					else if (flavor == "cover")
+						f << "flavor::COVER";
+					else log_assert(false);
+					f << ", condition, formatter, attributes);\n";
+				} else log_assert(false);
+			dec_indent();
+			f << indent << "} else {\n";
+			inc_indent();
+				if (cell->type == ID($print)) {
+					f << indent << print_output << " << formatter();\n";
+				} else if (cell->type == ID($check)) {
+					std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
+					if (flavor == "assert" || flavor == "assume") {
+						f << indent << "if (!condition) {\n";
+						inc_indent();
+							f << indent << "std::cerr << formatter();\n";
+						dec_indent();
+						f << indent << "}\n";
+						f << indent << "CXXRTL_ASSERT(condition && \"Check failed\");\n";
+					}
+				} else log_assert(false);
+			dec_indent();
+			f << indent << "}\n";
+		dec_indent();
+		f << indent << "}\n";
+	}
+
 	void dump_cell_eval(const RTLIL::Cell *cell, bool for_debug = false)
 	{
 		std::vector<const RTLIL::Cell*> inlined_cells;
@@ -1202,6 +1376,38 @@ struct CxxrtlWorker {
 			f << " = ";
 			dump_cell_expr(cell, for_debug);
 			f << ";\n";
+		// Effectful cells
+		} else if (is_effectful_cell(cell->type)) {
+			log_assert(!for_debug);
+
+			// Sync effectful cells are grouped into EFFECT_SYNC nodes in the FlowGraph.
+			log_assert(!cell->getParam(ID::TRG_ENABLE).as_bool() || (cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0));
+
+			if (!cell->getParam(ID::TRG_ENABLE).as_bool()) { // async effectful cell
+				f << indent << "auto " << mangle(cell) << "_next = ";
+				dump_sigspec_rhs(cell->getPort(ID::EN));
+				f << ".concat(";
+				if (cell->type == ID($print))
+					dump_sigspec_rhs(cell->getPort(ID::ARGS));
+				else if (cell->type == ID($check))
+					dump_sigspec_rhs(cell->getPort(ID::A));
+				else log_assert(false);
+				f << ").val();\n";
+
+				f << indent << "if (" << mangle(cell) << " != " << mangle(cell) << "_next) {\n";
+				inc_indent();
+					dump_effect(cell);
+					f << indent << mangle(cell) << " = " << mangle(cell) << "_next;\n";
+				dec_indent();
+				f << indent << "}\n";
+			} else { // initial effectful cell
+				f << indent << "if (!" << mangle(cell) << ") {\n";
+				inc_indent();
+					dump_effect(cell);
+					f << indent << mangle(cell) << " = value<1>{1u};\n";
+				dec_indent();
+				f << indent << "}\n";
+			}
 		// Flip-flops
 		} else if (is_ff_cell(cell->type)) {
 			log_assert(!for_debug);
@@ -1298,7 +1504,7 @@ struct CxxrtlWorker {
 				f << indent;
 				dump_sigspec_lhs(cell->getPort(ID::Q));
 				f << " = ";
-				dump_sigspec_lhs(cell->getPort(ID::Q));
+				dump_sigspec_rhs(cell->getPort(ID::Q));
 				f << ".update(";
 				dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int()));
 				f << ", ";
@@ -1310,7 +1516,7 @@ struct CxxrtlWorker {
 				f << indent;
 				dump_sigspec_lhs(cell->getPort(ID::Q));
 				f << " = ";
-				dump_sigspec_lhs(cell->getPort(ID::Q));
+				dump_sigspec_rhs(cell->getPort(ID::Q));
 				f << ".update(";
 				dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int()));
 				f << ", ";
@@ -1321,8 +1527,9 @@ struct CxxrtlWorker {
 		} else if (is_internal_cell(cell->type)) {
 			log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str());
 		// User cells
+		} else if (for_debug) {
+			// Outlines are called on demand when computing the value of a debug item. Nothing to do here.
 		} else {
-			log_assert(!for_debug);
 			log_assert(cell->known());
 			bool buffered_inputs = false;
 			const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
@@ -1382,11 +1589,11 @@ struct CxxrtlWorker {
 			};
 			if (buffered_inputs) {
 				// If we have any buffered inputs, there's no chance of converging immediately.
-				f << indent << mangle(cell) << access << "eval();\n";
+				f << indent << mangle(cell) << access << "eval(performer);\n";
 				f << indent << "converged = false;\n";
 				assign_from_outputs(/*cell_converged=*/false);
 			} else {
-				f << indent << "if (" << mangle(cell) << access << "eval()) {\n";
+				f << indent << "if (" << mangle(cell) << access << "eval(performer)) {\n";
 				inc_indent();
 					assign_from_outputs(/*cell_converged=*/true);
 				dec_indent();
@@ -1580,6 +1787,47 @@ struct CxxrtlWorker {
 		}
 	}
 
+	void dump_cell_effect_sync(std::vector<const RTLIL::Cell*> &cells)
+	{
+		log_assert(!cells.empty());
+		const auto &trg = cells[0]->getPort(ID::TRG);
+		const auto &trg_polarity = cells[0]->getParam(ID::TRG_POLARITY);
+
+		f << indent << "if (";
+		for (int i = 0; i < trg.size(); i++) {
+			RTLIL::SigBit trg_bit = trg[i];
+			trg_bit = sigmaps[trg_bit.wire->module](trg_bit);
+			log_assert(trg_bit.wire);
+
+			if (i != 0)
+				f << " || ";
+
+			if (trg_polarity[i] == State::S1)
+				f << "posedge_";
+			else
+				f << "negedge_";
+			f << mangle(trg_bit);
+		}
+		f << ") {\n";
+		inc_indent();
+			std::sort(cells.begin(), cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
+				return a->getParam(ID::PRIORITY).as_int() > b->getParam(ID::PRIORITY).as_int();
+			});
+			for (auto cell : cells) {
+				log_assert(cell->getParam(ID::TRG_ENABLE).as_bool());
+				log_assert(cell->getPort(ID::TRG) == trg);
+				log_assert(cell->getParam(ID::TRG_POLARITY) == trg_polarity);
+
+				std::vector<const RTLIL::Cell*> inlined_cells;
+				collect_cell_eval(cell, /*for_debug=*/false, inlined_cells);
+				dump_inlined_cells(inlined_cells);
+				dump_effect(cell);
+			}
+		dec_indent();
+
+		f << indent << "}\n";
+	}
+
 	void dump_mem_rdport(const Mem *mem, int portidx, bool for_debug = false)
 	{
 		auto &port = mem->rd_ports[portidx];
@@ -1899,6 +2147,10 @@ struct CxxrtlWorker {
 				}
 			}
 			for (auto cell : module->cells()) {
+				// Async and initial effectful cells have additional state, which must be reset as well.
+				if (is_effectful_cell(cell->type))
+					if (!cell->getParam(ID::TRG_ENABLE).as_bool() || cell->getParam(ID::TRG_WIDTH).as_int() == 0)
+						f << indent << mangle(cell) << " = {};\n";
 				if (is_internal_cell(cell->type))
 					continue;
 				f << indent << mangle(cell);
@@ -1946,6 +2198,9 @@ struct CxxrtlWorker {
 						case FlowGraph::Node::Type::CELL_EVAL:
 							dump_cell_eval(node.cell);
 							break;
+						case FlowGraph::Node::Type::EFFECT_SYNC:
+							dump_cell_effect_sync(node.cells);
+							break;
 						case FlowGraph::Node::Type::PROCESS_CASE:
 							dump_process_case(node.process);
 							break;
@@ -2009,27 +2264,116 @@ struct CxxrtlWorker {
 				if (wire_type.type == WireType::MEMBER && edge_wires[wire])
 					f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
 				if (wire_type.is_buffered())
-					f << indent << "if (" << mangle(wire) << ".commit()) changed = true;\n";
+					f << indent << "if (" << mangle(wire) << ".commit(observer)) changed = true;\n";
 			}
 			if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
 				for (auto &mem : mod_memories[module]) {
 					if (!writable_memories.count({module, mem.memid}))
 						continue;
-					f << indent << "if (" << mangle(&mem) << ".commit()) changed = true;\n";
+					f << indent << "if (" << mangle(&mem) << ".commit(observer)) changed = true;\n";
 				}
 				for (auto cell : module->cells()) {
 					if (is_internal_cell(cell->type))
 						continue;
 					const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
-					f << indent << "if (" << mangle(cell) << access << "commit()) changed = true;\n";
+					f << indent << "if (" << mangle(cell) << access << "commit(observer)) changed = true;\n";
 				}
 			}
 			f << indent << "return changed;\n";
 		dec_indent();
 	}
 
+	void dump_serialized_metadata(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map) {
+		// Creating thousands metadata_map objects using initializer lists in a single function results in one of:
+		// 1. Megabytes of stack usage (with __attribute__((optnone))).
+		// 2. Minutes of compile time (without __attribute__((optnone))).
+		// So, don't create them.
+		std::string data;
+		auto put_u64 = [&](uint64_t value) {
+			for (size_t count = 0; count < 8; count++) {
+				data += (char)(value >> 56);
+				value <<= 8;
+			}
+		};
+		for (auto metadata_item : metadata_map) {
+			if (!metadata_item.first.isPublic())
+				continue;
+			if (metadata_item.second.size() > 64 && (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) == 0) {
+				f << indent << "/* attribute " << metadata_item.first.str().substr(1) << " is over 64 bits wide */\n";
+				continue;
+			}
+			data += metadata_item.first.str().substr(1) + '\0';
+			// In Yosys, a real is a type of string.
+			if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
+				double dvalue = std::stod(metadata_item.second.decode_string());
+				uint64_t uvalue;
+				static_assert(sizeof(dvalue) == sizeof(uvalue), "double must be 64 bits in size");
+				memcpy(&uvalue, &dvalue, sizeof(uvalue));
+				data += 'd';
+				put_u64(uvalue);
+			} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
+				data += 's';
+				data += metadata_item.second.decode_string();
+				data += '\0';
+			} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED) {
+				data += 'i';
+				put_u64((uint64_t)metadata_item.second.as_int(/*is_signed=*/true));
+			} else {
+				data += 'u';
+				put_u64(metadata_item.second.as_int(/*is_signed=*/false));
+			}
+		}
+		f << escape_c_string(data);
+	}
+
+	void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map) {
+		if (metadata_map.empty()) {
+			f << "metadata_map()";
+		} else {
+			f << "metadata_map({\n";
+			inc_indent();
+				for (auto metadata_item : metadata_map) {
+					if (!metadata_item.first.isPublic())
+						continue;
+					if (metadata_item.second.size() > 64 && (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) == 0) {
+						f << indent << "/* attribute " << metadata_item.first.str().substr(1) << " is over 64 bits wide */\n";
+						continue;
+					}
+					f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
+					// In Yosys, a real is a type of string.
+					if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
+						f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
+					} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
+						f << escape_cxx_string(metadata_item.second.decode_string());
+					} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED) {
+						f << "INT64_C(" << metadata_item.second.as_int(/*is_signed=*/true) << ")";
+					} else {
+						f << "UINT64_C(" << metadata_item.second.as_int(/*is_signed=*/false) << ")";
+					}
+					f << " },\n";
+				}
+			dec_indent();
+			f << indent << "})";
+		}
+	}
+
+	void dump_debug_attrs(const RTLIL::AttrObject *object, bool serialize = true)
+	{
+		dict<RTLIL::IdString, RTLIL::Const> attributes = object->attributes;
+		// Inherently necessary to get access to the object, so a waste of space to emit.
+		attributes.erase(ID::hdlname);
+		// Internal Yosys attribute that should be removed but isn't.
+		attributes.erase(ID::module_not_derived);
+		if (serialize) {
+			dump_serialized_metadata(attributes);
+		} else {
+			dump_metadata_map(attributes);
+		}
+	}
+
 	void dump_debug_info_method(RTLIL::Module *module)
 	{
+		size_t count_scopes = 0;
 		size_t count_public_wires = 0;
 		size_t count_member_wires = 0;
 		size_t count_undriven = 0;
@@ -2042,139 +2386,195 @@ struct CxxrtlWorker {
 		size_t count_skipped_wires = 0;
 		inc_indent();
 			f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
-			for (auto wire : module->wires()) {
-				const auto &debug_wire_type = debug_wire_types[wire];
-				if (!wire->name.isPublic())
-					continue;
-				count_public_wires++;
-				switch (debug_wire_type.type) {
-					case WireType::BUFFERED:
-					case WireType::MEMBER: {
-						// Member wire
-						std::vector<std::string> flags;
-
-						if (wire->port_input && wire->port_output)
-							flags.push_back("INOUT");
-						else if (wire->port_output)
-							flags.push_back("OUTPUT");
-						else if (wire->port_input)
-							flags.push_back("INPUT");
-
-						bool has_driven_sync = false;
-						bool has_driven_comb = false;
-						bool has_undriven = false;
-						if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
-							for (auto bit : SigSpec(wire))
-								if (!bit_has_state.count(bit))
-									has_undriven = true;
-								else if (bit_has_state[bit])
-									has_driven_sync = true;
-								else
-									has_driven_comb = true;
-						} else if (wire->port_output) {
-							switch (cxxrtl_port_type(module, wire->name)) {
-								case CxxrtlPortType::SYNC:
-									has_driven_sync = true;
-									break;
-								case CxxrtlPortType::COMB:
-									has_driven_comb = true;
-									break;
-								case CxxrtlPortType::UNKNOWN:
-									has_driven_sync = has_driven_comb = true;
-									break;
-							}
-						} else {
-							has_undriven = true;
-						}
-						if (has_undriven)
-							flags.push_back("UNDRIVEN");
-						if (!has_driven_sync && !has_driven_comb && has_undriven)
-							count_undriven++;
-						if (has_driven_sync)
-							flags.push_back("DRIVEN_SYNC");
-						if (has_driven_sync && !has_driven_comb && !has_undriven)
-							count_driven_sync++;
-						if (has_driven_comb)
-							flags.push_back("DRIVEN_COMB");
-						if (!has_driven_sync && has_driven_comb && !has_undriven)
-							count_driven_comb++;
-						if (has_driven_sync + has_driven_comb + has_undriven > 1)
-							count_mixed_driver++;
-
-						f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
-						f << ", debug_item(" << mangle(wire) << ", " << wire->start_offset;
-						bool first = true;
-						for (auto flag : flags) {
-							if (first) {
-								first = false;
-								f << ", ";
+			f << indent << "if (scopes) {\n";
+			inc_indent();
+				// The module is responsible for adding its own scope.
+				f << indent << "scopes->add(path.empty() ? path : path.substr(0, path.size() - 1), ";
+				f << escape_cxx_string(get_hdl_name(module)) << ", ";
+				dump_debug_attrs(module, /*serialize=*/false);
+				f << ", std::move(cell_attrs));\n";
+				count_scopes++;
+				// If there were any submodules that were flattened, the module is also responsible for adding them.
+				for (auto cell : module->cells()) {
+					if (cell->type != ID($scopeinfo)) continue;
+					if (cell->getParam(ID::TYPE).decode_string() == "module") {
+						auto module_attrs = scopeinfo_attributes(cell, ScopeinfoAttrs::Module);
+						auto cell_attrs = scopeinfo_attributes(cell, ScopeinfoAttrs::Cell);
+						cell_attrs.erase(ID::module_not_derived);
+						f << indent << "scopes->add(path, " << escape_cxx_string(get_hdl_name(cell)) << ", ";
+						f << escape_cxx_string(cell->get_string_attribute(ID(module))) << ", ";
+						dump_serialized_metadata(module_attrs);
+						f << ", ";
+						dump_serialized_metadata(cell_attrs);
+						f << ");\n";
+					} else log_assert(false && "Unknown $scopeinfo type");
+					count_scopes++;
+				}
+			dec_indent();
+			f << indent << "}\n";
+			f << indent << "if (items) {\n";
+			inc_indent();
+				for (auto wire : module->wires()) {
+					const auto &debug_wire_type = debug_wire_types[wire];
+					if (!wire->name.isPublic())
+						continue;
+					count_public_wires++;
+					switch (debug_wire_type.type) {
+						case WireType::BUFFERED:
+						case WireType::MEMBER: {
+							// Member wire
+							std::vector<std::string> flags;
+
+							if (wire->port_input && wire->port_output)
+								flags.push_back("INOUT");
+							else if (wire->port_output)
+								flags.push_back("OUTPUT");
+							else if (wire->port_input)
+								flags.push_back("INPUT");
+
+							bool has_driven_sync = false;
+							bool has_driven_comb = false;
+							bool has_undriven = false;
+							if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
+								for (auto bit : SigSpec(wire))
+									if (!bit_has_state.count(bit))
+										has_undriven = true;
+									else if (bit_has_state[bit])
+										has_driven_sync = true;
+									else
+										has_driven_comb = true;
+							} else if (wire->port_output) {
+								switch (cxxrtl_port_type(module, wire->name)) {
+									case CxxrtlPortType::SYNC:
+										has_driven_sync = true;
+										break;
+									case CxxrtlPortType::COMB:
+										has_driven_comb = true;
+										break;
+									case CxxrtlPortType::UNKNOWN:
+										has_driven_sync = has_driven_comb = true;
+										break;
+								}
 							} else {
-								f << "|";
+								has_undriven = true;
+							}
+							if (has_undriven)
+								flags.push_back("UNDRIVEN");
+							if (!has_driven_sync && !has_driven_comb && has_undriven)
+								count_undriven++;
+							if (has_driven_sync)
+								flags.push_back("DRIVEN_SYNC");
+							if (has_driven_sync && !has_driven_comb && !has_undriven)
+								count_driven_sync++;
+							if (has_driven_comb)
+								flags.push_back("DRIVEN_COMB");
+							if (!has_driven_sync && has_driven_comb && !has_undriven)
+								count_driven_comb++;
+							if (has_driven_sync + has_driven_comb + has_undriven > 1)
+								count_mixed_driver++;
+
+							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire)) << ", ";
+							dump_debug_attrs(wire);
+							f << ", " << mangle(wire);
+							if (wire->start_offset != 0 || !flags.empty()) {
+								f << ", " << wire->start_offset;
+								bool first = true;
+								for (auto flag : flags) {
+									if (first) {
+										first = false;
+										f << ", ";
+									} else {
+										f << "|";
+									}
+									f << "debug_item::" << flag;
+								}
 							}
-							f << "debug_item::" << flag;
+							f << ");\n";
+							count_member_wires++;
+							break;
+						}
+						case WireType::ALIAS: {
+							// Alias of a member wire
+							const RTLIL::Wire *aliasee = debug_wire_type.sig_subst.as_wire();
+							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire)) << ", ";
+							dump_debug_attrs(aliasee);
+							f << ", ";
+							// If the aliasee is an outline, then the alias must be an outline, too; otherwise downstream
+							// tooling has no way to find out about the outline.
+							if (debug_wire_types[aliasee].is_outline())
+								f << "debug_eval_outline";
+							else
+								f << "debug_alias()";
+							f << ", " << mangle(aliasee);
+							if (wire->start_offset != 0)
+								f << ", " << wire->start_offset;
+							f << ");\n";
+							count_alias_wires++;
+							break;
+						}
+						case WireType::CONST: {
+							// Wire tied to a constant
+							f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
+							dump_const(debug_wire_type.sig_subst.as_const());
+							f << ";\n";
+							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire)) << ", ";
+							dump_debug_attrs(wire);
+							f << ", const_" << mangle(wire);
+							if (wire->start_offset != 0)
+								f << ", " << wire->start_offset;
+							f << ");\n";
+							count_const_wires++;
+							break;
+						}
+						case WireType::OUTLINE: {
+							// Localized or inlined, but rematerializable wire
+							f << indent << "items->add(path, " << escape_cxx_string(get_hdl_name(wire)) << ", ";
+							dump_debug_attrs(wire);
+							f << ", debug_eval_outline, " << mangle(wire);
+							if (wire->start_offset != 0)
+								f << ", " << wire->start_offset;
+							f << ");\n";
+							count_inline_wires++;
+							break;
+						}
+						default: {
+							// Localized or inlined wire with no debug information
+							count_skipped_wires++;
+							break;
 						}
-						f << "));\n";
-						count_member_wires++;
-						break;
-					}
-					case WireType::ALIAS: {
-						// Alias of a member wire
-						const RTLIL::Wire *aliasee = debug_wire_type.sig_subst.as_wire();
-						f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
-						f << ", debug_item(";
-						// If the aliasee is an outline, then the alias must be an outline, too; otherwise downstream
-						// tooling has no way to find out about the outline.
-						if (debug_wire_types[aliasee].is_outline())
-							f << "debug_eval_outline";
-						else
-							f << "debug_alias()";
-						f << ", " << mangle(aliasee) << ", " << wire->start_offset << "));\n";
-						count_alias_wires++;
-						break;
-					}
-					case WireType::CONST: {
-						// Wire tied to a constant
-						f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
-						dump_const(debug_wire_type.sig_subst.as_const());
-						f << ";\n";
-						f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
-						f << ", debug_item(const_" << mangle(wire) << ", " << wire->start_offset << "));\n";
-						count_const_wires++;
-						break;
-					}
-					case WireType::OUTLINE: {
-						// Localized or inlined, but rematerializable wire
-						f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
-						f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", " << wire->start_offset << "));\n";
-						count_inline_wires++;
-						break;
 					}
-					default: {
-						// Localized or inlined wire with no debug information
-						count_skipped_wires++;
-						break;
+				}
+				if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
+					for (auto &mem : mod_memories[module]) {
+						if (!mem.memid.isPublic())
+							continue;
+						f << indent << "items->add(path, " << escape_cxx_string(mem.packed ? get_hdl_name(mem.cell) : get_hdl_name(mem.mem)) << ", ";
+						if (mem.packed) {
+							dump_debug_attrs(mem.cell);
+						} else {
+							dump_debug_attrs(mem.mem);
+						}
+						f << ", " << mangle(&mem) << ", ";
+						f << mem.start_offset << ");\n";
 					}
 				}
-			}
+			dec_indent();
+			f << indent << "}\n";
 			if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
-				for (auto &mem : mod_memories[module]) {
-					if (!mem.memid.isPublic())
-						continue;
-					f << indent << "items.add(path + " << escape_cxx_string(mem.packed ? get_hdl_name(mem.cell) : get_hdl_name(mem.mem));
-					f << ", debug_item(" << mangle(&mem) << ", ";
-					f << mem.start_offset << "));\n";
-				}
 				for (auto cell : module->cells()) {
 					if (is_internal_cell(cell->type))
 						continue;
 					const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
-					f << indent << mangle(cell) << access << "debug_info(items, ";
-					f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
+					f << indent << mangle(cell) << access;
+					f << "debug_info(items, scopes, path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ", ";
+					dump_debug_attrs(cell, /*serialize=*/false);
+					f << ");\n";
 				}
 			}
 		dec_indent();
 
 		log_debug("Debug information statistics for module `%s':\n", log_id(module));
+		log_debug("  Scopes: %zu", count_scopes);
 		log_debug("  Public wires: %zu, of which:\n", count_public_wires);
 		log_debug("    Member wires: %zu, of which:\n", count_member_wires);
 		log_debug("      Undriven:     %zu (incl. inputs)\n", count_undriven);
@@ -2190,33 +2590,6 @@ struct CxxrtlWorker {
 		}
 	}
 
-	void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
-	{
-		if (metadata_map.empty()) {
-			f << "metadata_map()";
-			return;
-		}
-		f << "metadata_map({\n";
-		inc_indent();
-			for (auto metadata_item : metadata_map) {
-				if (!metadata_item.first.begins_with("\\"))
-					continue;
-				f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
-				if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
-					f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
-				} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
-					f << escape_cxx_string(metadata_item.second.decode_string());
-				} else {
-					f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED);
-					if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED))
-						f << "u";
-				}
-				f << " },\n";
-			}
-		dec_indent();
-		f << indent << "})";
-	}
-
 	void dump_module_intf(RTLIL::Module *module)
 	{
 		dump_attrs(module);
@@ -2234,20 +2607,27 @@ struct CxxrtlWorker {
 				dump_reset_method(module);
 				f << indent << "}\n";
 				f << "\n";
-				f << indent << "bool eval() override {\n";
+				// No default argument, to prevent unintentional `return bb_foo::eval();` calls that drop performer.
+				f << indent << "bool eval(performer *performer) override {\n";
 				dump_eval_method(module);
 				f << indent << "}\n";
 				f << "\n";
-				f << indent << "bool commit() override {\n";
+				f << indent << "virtual bool commit(observer &observer) {\n";
 				dump_commit_method(module);
 				f << indent << "}\n";
 				f << "\n";
+				f << indent << "bool commit() override {\n";
+				f << indent << indent << "observer observer;\n";
+				f << indent << indent << "return commit(observer);\n";
+				f << indent << "}\n";
 				if (debug_info) {
-					f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n";
+					f << "\n";
+					f << indent << "void debug_info(debug_items *items, debug_scopes *scopes, "
+					            << "std::string path, metadata_map &&cell_attrs = {}) override {\n";
 					dump_debug_info_method(module);
 					f << indent << "}\n";
-					f << "\n";
 				}
+				f << "\n";
 				f << indent << "static std::unique_ptr<" << mangle(module);
 				f << template_params(module, /*is_decl=*/false) << "> ";
 				f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
@@ -2291,6 +2671,15 @@ struct CxxrtlWorker {
 					f << "\n";
 				bool has_cells = false;
 				for (auto cell : module->cells()) {
+					// Async and initial effectful cells have additional state, which requires storage.
+					if (is_effectful_cell(cell->type)) {
+						if (cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0)
+							f << indent << "value<1> " << mangle(cell) << ";\n"; // async initial cell
+						if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == ID($print))
+							f << indent << "value<" << (1 + cell->getParam(ID::ARGS_WIDTH).as_int()) << "> " << mangle(cell) << ";\n"; // {EN, ARGS}
+						if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == ID($check))
+							f << indent << "value<2> " << mangle(cell) << ";\n"; // {EN, A}
+					}
 					if (is_internal_cell(cell->type))
 						continue;
 					dump_attrs(cell);
@@ -2319,8 +2708,18 @@ struct CxxrtlWorker {
 				f << indent << "};\n";
 				f << "\n";
 				f << indent << "void reset() override;\n";
-				f << indent << "bool eval() override;\n";
-				f << indent << "bool commit() override;\n";
+				f << "\n";
+				f << indent << "bool eval(performer *performer = nullptr) override;\n";
+				f << "\n";
+				f << indent << "template<class ObserverT>\n";
+				f << indent << "bool commit(ObserverT &observer) {\n";
+				dump_commit_method(module);
+				f << indent << "}\n";
+				f << "\n";
+				f << indent << "bool commit() override {\n";
+				f << indent << indent << "observer observer;\n";
+				f << indent << indent << "return commit<>(observer);\n";
+				f << indent << "}\n";
 				if (debug_info) {
 					if (debug_eval) {
 						f << "\n";
@@ -2333,7 +2732,8 @@ struct CxxrtlWorker {
 							}
 					}
 					f << "\n";
-					f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n";
+					f << indent << "void debug_info(debug_items *items, debug_scopes *scopes, "
+					            << "std::string path, metadata_map &&cell_attrs = {}) override;\n";
 				}
 			dec_indent();
 			f << indent << "}; // struct " << mangle(module) << "\n";
@@ -2349,27 +2749,24 @@ struct CxxrtlWorker {
 		dump_reset_method(module);
 		f << indent << "}\n";
 		f << "\n";
-		f << indent << "bool " << mangle(module) << "::eval() {\n";
+		f << indent << "bool " << mangle(module) << "::eval(performer *performer) {\n";
 		dump_eval_method(module);
 		f << indent << "}\n";
-		f << "\n";
-		f << indent << "bool " << mangle(module) << "::commit() {\n";
-		dump_commit_method(module);
-		f << indent << "}\n";
-		f << "\n";
 		if (debug_info) {
 			if (debug_eval) {
+				f << "\n";
 				f << indent << "void " << mangle(module) << "::debug_eval() {\n";
 				dump_debug_eval_method(module);
 				f << indent << "}\n";
-				f << "\n";
 			}
+			f << "\n";
 			f << indent << "CXXRTL_EXTREMELY_COLD\n";
-			f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n";
+			f << indent << "void " << mangle(module) << "::debug_info(debug_items *items, debug_scopes *scopes, "
+			            << "std::string path, metadata_map &&cell_attrs) {\n";
 			dump_debug_info_method(module);
 			f << indent << "}\n";
-			f << "\n";
 		}
+		f << "\n";
 	}
 
 	void dump_design(RTLIL::Design *design)
@@ -2409,7 +2806,7 @@ struct CxxrtlWorker {
 			f << "#define " << include_guard << "\n";
 			f << "\n";
 			if (top_module != nullptr && debug_info) {
-				f << "#include <backends/cxxrtl/cxxrtl_capi.h>\n";
+				f << "#include <cxxrtl/capi/cxxrtl_capi.h>\n";
 				f << "\n";
 				f << "#ifdef __cplusplus\n";
 				f << "extern \"C\" {\n";
@@ -2427,7 +2824,7 @@ struct CxxrtlWorker {
 			}
 			f << "#ifdef __cplusplus\n";
 			f << "\n";
-			f << "#include <backends/cxxrtl/cxxrtl.h>\n";
+			f << "#include <cxxrtl/cxxrtl.h>\n";
 			f << "\n";
 			f << "using namespace cxxrtl;\n";
 			f << "\n";
@@ -2444,17 +2841,17 @@ struct CxxrtlWorker {
 		}
 
 		if (split_intf)
-			f << "#include \"" << intf_filename << "\"\n";
+			f << "#include \"" << basename(intf_filename) << "\"\n";
 		else
-			f << "#include <backends/cxxrtl/cxxrtl.h>\n";
+			f << "#include <cxxrtl/cxxrtl.h>\n";
 		f << "\n";
 		f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
 		f << "    defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
-		f << "#include <backends/cxxrtl/cxxrtl_capi.cc>\n";
+		f << "#include <cxxrtl/capi/cxxrtl_capi.cc>\n";
 		f << "#endif\n";
 		f << "\n";
 		f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
-		f << "#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>\n";
+		f << "#include <cxxrtl/capi/cxxrtl_capi_vcd.cc>\n";
 		f << "#endif\n";
 		f << "\n";
 		f << "using namespace cxxrtl_yosys;\n";
@@ -2601,6 +2998,16 @@ struct CxxrtlWorker {
 						register_edge_signal(sigmap, cell->getPort(ID::CLK),
 							cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
 				}
+
+				// Effectful cells may be triggered on posedge/negedge events.
+				if (is_effectful_cell(cell->type) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
+					for (size_t i = 0; i < (size_t)cell->getParam(ID::TRG_WIDTH).as_int(); i++) {
+						RTLIL::SigBit trg = cell->getPort(ID::TRG).extract(i, 1);
+						if (is_valid_clock(trg))
+							register_edge_signal(sigmap, trg,
+								cell->parameters[ID::TRG_POLARITY][i] == RTLIL::S1 ? RTLIL::STp : RTLIL::STn);
+					}
+				}
 			}
 
 			for (auto &mem : memories) {
@@ -2734,8 +3141,12 @@ struct CxxrtlWorker {
 			// Discover nodes reachable from primary outputs (i.e. members) and collect reachable wire users.
 			pool<FlowGraph::Node*, hash_ptr_ops> worklist;
 			for (auto node : flow.nodes) {
-				if (node->type == FlowGraph::Node::Type::CELL_EVAL && is_effectful_cell(node->cell->type))
-					worklist.insert(node); // node has effects
+				if (node->type == FlowGraph::Node::Type::CELL_EVAL && !is_internal_cell(node->cell->type))
+					worklist.insert(node); // node evaluates a submodule
+				else if (node->type == FlowGraph::Node::Type::CELL_EVAL && is_effectful_cell(node->cell->type))
+					worklist.insert(node); // node has async effects
+				else if (node->type == FlowGraph::Node::Type::EFFECT_SYNC)
+					worklist.insert(node); // node has sync effects
 				else if (node->type == FlowGraph::Node::Type::MEM_WRPORTS)
 					worklist.insert(node); // node is memory write
 				else if (node->type == FlowGraph::Node::Type::PROCESS_SYNC && is_memwr_process(node->process))
@@ -2792,9 +3203,23 @@ struct CxxrtlWorker {
 			}
 
 			// Emit reachable nodes in eval().
+			// Accumulate sync effectful cells per trigger condition.
+			dict<std::pair<RTLIL::SigSpec, RTLIL::Const>, std::vector<const RTLIL::Cell*>> effect_sync_cells;
 			for (auto node : node_order)
-				if (live_nodes[node])
-					schedule[module].push_back(*node);
+				if (live_nodes[node]) {
+					if (node->type == FlowGraph::Node::Type::CELL_EVAL &&
+							is_effectful_cell(node->cell->type) &&
+							node->cell->getParam(ID::TRG_ENABLE).as_bool() &&
+							node->cell->getParam(ID::TRG_WIDTH).as_int() != 0)
+						effect_sync_cells[make_pair(node->cell->getPort(ID::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell);
+					else
+						schedule[module].push_back(*node);
+				}
+
+			for (auto &it : effect_sync_cells) {
+				auto node = flow.add_effect_sync_node(it.second);
+				schedule[module].push_back(*node);
+			}
 
 			// For maximum performance, the state of the simulation (which is the same as the set of its double buffered
 			// wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain
@@ -2838,6 +3263,7 @@ struct CxxrtlWorker {
 						debug_wire_type = wire_type; // wire is a member
 
 					if (!debug_alias) continue;
+					if (wire->port_input || wire->port_output) continue; // preserve input/output metadata in flags
 					const RTLIL::Wire *it = wire;
 					while (flow.is_inlinable(it)) {
 						log_assert(flow.wire_comb_defs[it].size() == 1);
@@ -3098,7 +3524,8 @@ struct CxxrtlBackend : public Backend {
 		log("      value<8> p_i_data;\n");
 		log("      wire<8> p_o_data;\n");
 		log("\n");
-		log("      bool eval() override;\n");
+		log("      bool eval(performer *performer) override;\n");
+		log("      virtual bool commit(observer &observer);\n");
 		log("      bool commit() override;\n");
 		log("\n");
 		log("      static std::unique_ptr<bb_p_debug>\n");
@@ -3111,11 +3538,11 @@ struct CxxrtlBackend : public Backend {
 		log("    namespace cxxrtl_design {\n");
 		log("\n");
 		log("    struct stderr_debug : public bb_p_debug {\n");
-		log("      bool eval() override {\n");
+		log("      bool eval(performer *performer) override {\n");
 		log("        if (posedge_p_clk() && p_en)\n");
 		log("          fprintf(stderr, \"debug: %%02x\\n\", p_i_data.data[0]);\n");
 		log("        p_o_data.next = p_i_data;\n");
-		log("        return bb_p_debug::eval();\n");
+		log("        return bb_p_debug::eval(performer);\n");
 		log("      }\n");
 		log("    };\n");
 		log("\n");
@@ -3213,6 +3640,11 @@ struct CxxrtlBackend : public Backend {
 		log("        place the generated code into namespace <ns-name>. if not specified,\n");
 		log("        \"cxxrtl_design\" is used.\n");
 		log("\n");
+		log("    -print-output <stream>\n");
+		log("        $print cells in the generated code direct their output to <stream>.\n");
+		log("        must be one of \"std::cout\", \"std::cerr\". if not specified,\n");
+		log("        \"std::cout\" is used. explicitly provided performer overrides this.\n");
+		log("\n");
 		log("    -nohierarchy\n");
 		log("        use design hierarchy as-is. in most designs, a top module should be\n");
 		log("        present as it is exposed through the C API and has unbuffered outputs\n");
@@ -3351,6 +3783,14 @@ struct CxxrtlBackend : public Backend {
 				worker.design_ns = args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-print-output" && argidx+1 < args.size()) {
+				worker.print_output = args[++argidx];
+				if (!(worker.print_output == "std::cout" || worker.print_output == "std::cerr")) {
+					log_cmd_error("Invalid output stream \"%s\".\n", worker.print_output.c_str());
+					worker.print_output = "std::cout";
+				}
+				continue;
+			}
 			break;
 		}
 		extra_args(f, filename, args, argidx);
diff --git a/yosys/backends/cxxrtl/runtime/README.txt b/yosys/backends/cxxrtl/runtime/README.txt
new file mode 100644
index 00000000000..9ae7051cdcc
--- /dev/null
+++ b/yosys/backends/cxxrtl/runtime/README.txt
@@ -0,0 +1,18 @@
+This directory contains the runtime components of CXXRTL and should be placed on the include path
+when building the simulation using the `-I${YOSYS}/backends/cxxrtl/runtime` option. These components
+are not used in the Yosys binary; they are only built as a part of the simulation binary.
+
+The interfaces declared in `cxxrtl_capi*.h` contain the stable C API. These interfaces will not be
+changed in backward-incompatible ways unless no other option is available, and any breaking changes
+will be made in a way that causes the downstream code to fail in a visible way. The ABI of these
+interfaces is considered stable as well, and it will not use features complicating its use via
+libraries such as libffi or ctypes.
+
+The implementations in `cxxrtl_capi*.cc` are considered private; they are still placed in the include
+path to enable build-system-less builds (where the CXXRTL runtime component is included in the C++
+file of the simulation toplevel).
+
+The interfaces declared in `cxxrtl*.h` (without `capi`) are unstable and may change without notice.
+
+For clarity, all of the files in this directory and its subdirectories have unique names regardless
+of the directory where they are placed.
\ No newline at end of file
diff --git a/yosys/backends/cxxrtl/cxxrtl_capi.cc b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
similarity index 58%
rename from yosys/backends/cxxrtl/cxxrtl_capi.cc
rename to yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
index 227173ba87f..34801c2d118 100644
--- a/yosys/backends/cxxrtl/cxxrtl_capi.cc
+++ b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
@@ -16,10 +16,10 @@
  *
  */
 
-// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_capi.h`.
+// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl/capi/cxxrtl_capi.h`.
 
-#include <backends/cxxrtl/cxxrtl.h>
-#include <backends/cxxrtl/cxxrtl_capi.h>
+#include <cxxrtl/capi/cxxrtl_capi.h>
+#include <cxxrtl/cxxrtl.h>
 
 struct _cxxrtl_handle {
 	std::unique_ptr<cxxrtl::module> module;
@@ -35,19 +35,19 @@ cxxrtl_handle cxxrtl_create(cxxrtl_toplevel design) {
 	return cxxrtl_create_at(design, "");
 }
 
-cxxrtl_handle cxxrtl_create_at(cxxrtl_toplevel design, const char *root) {
-	std::string path = root;
-	if (!path.empty()) {
+cxxrtl_handle cxxrtl_create_at(cxxrtl_toplevel design, const char *top_path_) {
+	std::string top_path = top_path_;
+	if (!top_path.empty()) {
 		// module::debug_info() accepts either an empty path, or a path ending in space to simplify
 		// the logic in generated code. While this is sketchy at best to expose in the C++ API, this
 		// would be a lot worse in the C API, so don't expose it here.
-		assert(path.back() != ' ');
-		path += ' ';
+		assert(top_path.back() != ' ');
+		top_path += ' ';
 	}
 
 	cxxrtl_handle handle = new _cxxrtl_handle;
 	handle->module = std::move(design->module);
-	handle->module->debug_info(handle->objects, path);
+	handle->module->debug_info(&handle->objects, nullptr, top_path);
 	delete design;
 	return handle;
 }
@@ -90,3 +90,46 @@ void cxxrtl_enum(cxxrtl_handle handle, void *data,
 void cxxrtl_outline_eval(cxxrtl_outline outline) {
 	outline->eval();
 }
+
+int cxxrtl_attr_type(cxxrtl_attr_set attrs_, const char *name) {
+	auto attrs = (cxxrtl::metadata_map*)attrs_;
+	if (!attrs->count(name))
+		return CXXRTL_ATTR_NONE;
+	switch (attrs->at(name).value_type) {
+		case cxxrtl::metadata::UINT:
+			return CXXRTL_ATTR_UNSIGNED_INT;
+		case cxxrtl::metadata::SINT:
+			return CXXRTL_ATTR_SIGNED_INT;
+		case cxxrtl::metadata::STRING:
+			return CXXRTL_ATTR_STRING;
+		case cxxrtl::metadata::DOUBLE:
+			return CXXRTL_ATTR_DOUBLE;
+		default:
+			// Present unsupported attribute type the same way as no attribute at all.
+			return CXXRTL_ATTR_NONE;
+	}
+}
+
+uint64_t cxxrtl_attr_get_unsigned_int(cxxrtl_attr_set attrs_, const char *name) {
+	auto &attrs = *(cxxrtl::metadata_map*)attrs_;
+	assert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::UINT);
+	return attrs[name].as_uint();
+}
+
+int64_t cxxrtl_attr_get_signed_int(cxxrtl_attr_set attrs_, const char *name) {
+	auto &attrs = *(cxxrtl::metadata_map*)attrs_;
+	assert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::SINT);
+	return attrs[name].as_sint();
+}
+
+const char *cxxrtl_attr_get_string(cxxrtl_attr_set attrs_, const char *name) {
+	auto &attrs = *(cxxrtl::metadata_map*)attrs_;
+	assert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::STRING);
+	return attrs[name].as_string().c_str();
+}
+
+double cxxrtl_attr_get_double(cxxrtl_attr_set attrs_, const char *name) {
+	auto &attrs = *(cxxrtl::metadata_map*)attrs_;
+	assert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::DOUBLE);
+	return attrs[name].as_double();
+}
diff --git a/yosys/backends/cxxrtl/cxxrtl_capi.h b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h
similarity index 80%
rename from yosys/backends/cxxrtl/cxxrtl_capi.h
rename to yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h
index 2df2b7287f4..ae42733ad7f 100644
--- a/yosys/backends/cxxrtl/cxxrtl_capi.h
+++ b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h
@@ -55,8 +55,8 @@ cxxrtl_handle cxxrtl_create(cxxrtl_toplevel design);
 // Create a design handle at a given hierarchy position from a design toplevel.
 //
 // This operation is similar to `cxxrtl_create`, except the full hierarchical name of every object
-// is prepended with `root`.
-cxxrtl_handle cxxrtl_create_at(cxxrtl_toplevel design, const char *root);
+// is prepended with `top_path`.
+cxxrtl_handle cxxrtl_create_at(cxxrtl_toplevel design, const char *top_path);
 
 // Release all resources used by a design and its handle.
 void cxxrtl_destroy(cxxrtl_handle handle);
@@ -240,6 +240,11 @@ struct cxxrtl_object {
 	// through wires, the bits are double buffered. To avoid race conditions, user code should
 	// always read from `curr` and write to `next`. The `curr` pointer is always valid; for objects
 	// that cannot be modified, or cannot be modified in a race-free way, `next` is NULL.
+	//
+	// In case where `width == 0`, `curr` is a non-NULL pointer unique for the wire. That is,
+	// there is a 1-to-1 correspondence between simulation objects and `curr` pointers, regardless
+	// of whether they have storage or not. (Aliases' `curr` pointer equals that of some other
+	// simulated object.)
 	uint32_t *curr;
 	uint32_t *next;
 
@@ -249,6 +254,15 @@ struct cxxrtl_object {
 	// this field to NULL.
 	struct _cxxrtl_outline *outline;
 
+	// Opaque reference to an attribute set.
+	//
+	// See the documentation of `cxxrtl_attr_set` for details. When creating a `cxxrtl_object`, set
+	// this field to NULL.
+	//
+	// The lifetime of the pointers returned by `cxxrtl_attr_*` family of functions is the same as
+	// the lifetime of this structure.
+	struct _cxxrtl_attr_set *attrs;
+
 	// More description fields may be added in the future, but the existing ones will never change.
 };
 
@@ -304,6 +318,62 @@ typedef struct _cxxrtl_outline *cxxrtl_outline;
 // re-evaluated, otherwise the bits read from that object are meaningless.
 void cxxrtl_outline_eval(cxxrtl_outline outline);
 
+// Opaque reference to an attribute set.
+//
+// An attribute set is a map between attribute names (always strings) and values (which may have
+// several different types). To find out the type of an attribute, use `cxxrtl_attr_type`, and
+// to retrieve the value of an attribute, use `cxxrtl_attr_as_string`.
+typedef struct _cxxrtl_attr_set *cxxrtl_attr_set;
+
+// Type of an attribute.
+enum cxxrtl_attr_type {
+	// Attribute is not present.
+	CXXRTL_ATTR_NONE = 0,
+
+	// Attribute has an unsigned integer value.
+	CXXRTL_ATTR_UNSIGNED_INT = 1,
+
+	// Attribute has an unsigned integer value.
+	CXXRTL_ATTR_SIGNED_INT = 2,
+
+	// Attribute has a string value.
+	CXXRTL_ATTR_STRING = 3,
+
+	// Attribute has a double precision floating point value.
+	CXXRTL_ATTR_DOUBLE = 4,
+
+	// More attribute types may be defined in the future, but the existing values will never change.
+};
+
+// Determine the presence and type of an attribute in an attribute set.
+//
+// This function returns one of the possible `cxxrtl_attr_type` values.
+int cxxrtl_attr_type(cxxrtl_attr_set attrs, const char *name);
+
+// Retrieve an unsigned integer valued attribute from an attribute set.
+//
+// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_UNSIGNED_INT`.
+// If assertions are disabled, returns 0 if the attribute is missing or has an incorrect type.
+uint64_t cxxrtl_attr_get_unsigned_int(cxxrtl_attr_set attrs, const char *name);
+
+// Retrieve a signed integer valued attribute from an attribute set.
+//
+// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_SIGNED_INT`.
+// If assertions are disabled, returns 0 if the attribute is missing or has an incorrect type.
+int64_t cxxrtl_attr_get_signed_int(cxxrtl_attr_set attrs, const char *name);
+
+// Retrieve a string valued attribute from an attribute set. The returned string is zero-terminated.
+//
+// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_STRING`. If assertions
+// are disabled, returns NULL if the attribute is missing or has an incorrect type.
+const char *cxxrtl_attr_get_string(cxxrtl_attr_set attrs, const char *name);
+
+// Retrieve a double precision floating point valued attribute from an attribute set.
+//
+// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_DOUBLE`. If assertions
+// are disabled, returns NULL if the attribute is missing or has an incorrect type.
+double cxxrtl_attr_get_double(cxxrtl_attr_set attrs, const char *name);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/yosys/backends/cxxrtl/cxxrtl_vcd_capi.cc b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc
similarity index 95%
rename from yosys/backends/cxxrtl/cxxrtl_vcd_capi.cc
rename to yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc
index 52a9198b869..0949a9363eb 100644
--- a/yosys/backends/cxxrtl/cxxrtl_vcd_capi.cc
+++ b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc
@@ -16,10 +16,10 @@
  *
  */
 
-// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_vcd_capi.h`.
+// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl/capi/cxxrtl_capi_vcd.h`.
 
-#include <backends/cxxrtl/cxxrtl_vcd.h>
-#include <backends/cxxrtl/cxxrtl_vcd_capi.h>
+#include <cxxrtl/capi/cxxrtl_capi_vcd.h>
+#include <cxxrtl/cxxrtl_vcd.h>
 
 extern const cxxrtl::debug_items &cxxrtl_debug_items_from_handle(cxxrtl_handle handle);
 
diff --git a/yosys/backends/cxxrtl/cxxrtl_vcd_capi.h b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h
similarity index 97%
rename from yosys/backends/cxxrtl/cxxrtl_vcd_capi.h
rename to yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h
index d55afe2230e..844f3cb8c83 100644
--- a/yosys/backends/cxxrtl/cxxrtl_vcd_capi.h
+++ b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h
@@ -16,8 +16,8 @@
  *
  */
 
-#ifndef CXXRTL_VCD_CAPI_H
-#define CXXRTL_VCD_CAPI_H
+#ifndef CXXRTL_CAPI_VCD_H
+#define CXXRTL_CAPI_VCD_H
 
 // This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_vcd_capi.cc`.
 //
@@ -27,7 +27,7 @@
 #include <stddef.h>
 #include <stdint.h>
 
-#include <backends/cxxrtl/cxxrtl_capi.h>
+#include <cxxrtl/capi/cxxrtl_capi.h>
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/yosys/backends/cxxrtl/cxxrtl.h b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
similarity index 71%
rename from yosys/backends/cxxrtl/cxxrtl.h
rename to yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
index 5d0596f0d61..d1d6bd8dc68 100644
--- a/yosys/backends/cxxrtl/cxxrtl.h
+++ b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
@@ -28,6 +28,7 @@
 
 #include <cstddef>
 #include <cstdint>
+#include <cstring>
 #include <cassert>
 #include <limits>
 #include <type_traits>
@@ -38,8 +39,10 @@
 #include <memory>
 #include <functional>
 #include <sstream>
+#include <iostream>
 
-#include <backends/cxxrtl/cxxrtl_capi.h>
+// `cxxrtl::debug_item` has to inherit from `cxxrtl_object` to satisfy strict aliasing requirements.
+#include <cxxrtl/capi/cxxrtl_capi.h>
 
 #ifndef __has_attribute
 #	define __has_attribute(x) 0
@@ -144,7 +147,7 @@ struct value : public expr_base<value<Bits>> {
 	// These functions ensure that a conversion is never out of range, and should be always used, if at all
 	// possible, instead of direct manipulation of the `data` member. For very large types, .slice() and
 	// .concat() can be used to split them into more manageable parts.
-	template<class IntegerT>
+	template<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>
 	CXXRTL_ALWAYS_INLINE
 	IntegerT get() const {
 		static_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,
@@ -157,15 +160,32 @@ struct value : public expr_base<value<Bits>> {
 		return result;
 	}
 
-	template<class IntegerT>
+	template<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>
 	CXXRTL_ALWAYS_INLINE
-	void set(IntegerT other) {
+	IntegerT get() const {
+		auto unsigned_result = get<typename std::make_unsigned<IntegerT>::type>();
+		IntegerT result;
+		memcpy(&result, &unsigned_result, sizeof(IntegerT));
+		return result;
+	}
+
+	template<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>
+	CXXRTL_ALWAYS_INLINE
+	void set(IntegerT value) {
 		static_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,
 		              "set<T>() requires T to be an unsigned integral type");
 		static_assert(std::numeric_limits<IntegerT>::digits >= Bits,
 		              "set<T>() requires the value to be at least as wide as T is");
 		for (size_t n = 0; n < chunks; n++)
-			data[n] = (other >> (n * chunk::bits)) & chunk::mask;
+			data[n] = (value >> (n * chunk::bits)) & chunk::mask;
+	}
+
+	template<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>
+	CXXRTL_ALWAYS_INLINE
+	void set(IntegerT value) {
+		typename std::make_unsigned<IntegerT>::type unsigned_value;
+		memcpy(&unsigned_value, &value, sizeof(IntegerT));
+		set(unsigned_value);
 	}
 
 	// Operations with compile-time parameters.
@@ -418,6 +438,7 @@ struct value : public expr_base<value<Bits>> {
 			carry = (shift_bits == 0) ? 0
 				: data[n] >> (chunk::bits - shift_bits);
 		}
+		result.data[result.chunks - 1] &= result.msb_mask;
 		return result;
 	}
 
@@ -428,12 +449,12 @@ struct value : public expr_base<value<Bits>> {
 		// Detect shifts definitely large than Bits early.
 		for (size_t n = 1; n < amount.chunks; n++)
 			if (amount.data[n] != 0)
-				return {};
+				return (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();
 		// Past this point we can use the least significant chunk as the shift size.
 		size_t shift_chunks = amount.data[0] / chunk::bits;
 		size_t shift_bits   = amount.data[0] % chunk::bits;
 		if (shift_chunks >= chunks)
-			return {};
+			return (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();
 		value<Bits> result;
 		chunk::type carry = 0;
 		for (size_t n = 0; n < chunks - shift_chunks; n++) {
@@ -442,12 +463,13 @@ struct value : public expr_base<value<Bits>> {
 				: data[chunks - 1 - n] << (chunk::bits - shift_bits);
 		}
 		if (Signed && is_neg()) {
-			size_t top_chunk_idx  = (Bits - shift_bits) / chunk::bits;
-			size_t top_chunk_bits = (Bits - shift_bits) % chunk::bits;
+			size_t top_chunk_idx  = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) / chunk::bits;
+			size_t top_chunk_bits = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) % chunk::bits;
 			for (size_t n = top_chunk_idx + 1; n < chunks; n++)
 				result.data[n] = chunk::mask;
-			if (shift_bits != 0)
+			if (amount.data[0] != 0)
 				result.data[top_chunk_idx] |= chunk::mask << top_chunk_bits;
+			result.data[result.chunks - 1] &= result.msb_mask;
 		}
 		return result;
 	}
@@ -472,6 +494,7 @@ struct value : public expr_base<value<Bits>> {
 			carry = (shift_bits == 0) ? 0
 				: data[result.chunks + shift_chunks - 1 - n] << (chunk::bits - shift_bits);
 		}
+		result.data[result.chunks - 1] &= result.msb_mask;
 		return result;
 	}
 
@@ -507,12 +530,14 @@ struct value : public expr_base<value<Bits>> {
 		size_t count = 0;
 		for (size_t n = 0; n < chunks; n++) {
 			chunk::type x = data[chunks - 1 - n];
-			if (x == 0) {
-				count += (n == 0 ? Bits % chunk::bits : chunk::bits);
-			} else {
-				// This loop implements the find first set idiom as recognized by LLVM.
-				for (; x != 0; count++)
+			// First add to `count` as if the chunk is zero
+			constexpr size_t msb_chunk_bits = Bits % chunk::bits != 0 ? Bits % chunk::bits : chunk::bits;
+			count += (n == 0 ? msb_chunk_bits : chunk::bits);
+			// If the chunk isn't zero, correct the `count` value and return
+			if (x != 0) {
+				for (; x != 0; count--)
 					x >>= 1;
+				break;
 			}
 		}
 		return count;
@@ -541,7 +566,7 @@ struct value : public expr_base<value<Bits>> {
 	}
 
 	value<Bits> neg() const {
-		return value<Bits> { 0u }.sub(*this);
+		return value<Bits>().sub(*this);
 	}
 
 	bool ucmp(const value<Bits> &other) const {
@@ -575,6 +600,38 @@ struct value : public expr_base<value<Bits>> {
 		result.data[result.chunks - 1] &= result.msb_mask;
 		return result;
 	}
+
+	std::pair<value<Bits>, value<Bits>> udivmod(value<Bits> divisor) const {
+		value<Bits> quotient;
+		value<Bits> dividend = *this;
+		if (dividend.ucmp(divisor))
+			return {/*quotient=*/value<Bits>{0u}, /*remainder=*/dividend};
+		int64_t divisor_shift = divisor.ctlz() - dividend.ctlz();
+		assert(divisor_shift >= 0);
+		divisor = divisor.shl(value<Bits>{(chunk::type) divisor_shift});
+		for (size_t step = 0; step <= divisor_shift; step++) {
+			quotient = quotient.shl(value<Bits>{1u});
+			if (!dividend.ucmp(divisor)) {
+				dividend = dividend.sub(divisor);
+				quotient.set_bit(0, true);
+			}
+			divisor = divisor.shr(value<Bits>{1u});
+		}
+		return {quotient, /*remainder=*/dividend};
+	}
+
+	std::pair<value<Bits>, value<Bits>> sdivmod(const value<Bits> &other) const {
+		value<Bits + 1> quotient;
+		value<Bits + 1> remainder;
+		value<Bits + 1> dividend = sext<Bits + 1>();
+		value<Bits + 1> divisor = other.template sext<Bits + 1>();
+		if (is_neg()) dividend = dividend.neg();
+		if (other.is_neg()) divisor = divisor.neg();
+		std::tie(quotient, remainder) = dividend.udivmod(divisor);
+		if (is_neg() != other.is_neg()) quotient = quotient.neg();
+		if (is_neg()) remainder = remainder.neg();
+		return {quotient.template trunc<Bits>(), remainder.template trunc<Bits>()};
+	}
 };
 
 // Expression template for a slice, usable as lvalue or rvalue, and composable with other expression templates here.
@@ -741,8 +798,13 @@ struct wire {
 		next.template set<IntegerT>(other);
 	}
 
-	bool commit() {
+	// This method intentionally takes a mandatory argument (to make it more difficult to misuse in
+	// black box implementations, leading to missed observer events). It is generic over its argument
+	// to allow the `on_update` method to be non-virtual.
+	template<class ObserverT>
+	bool commit(ObserverT &observer) {
 		if (curr != next) {
+			observer.on_update(curr.chunks, curr.data, next.data);
 			curr = next;
 			return true;
 		}
@@ -816,12 +878,17 @@ struct memory {
 			write { index, val, mask, priority });
 	}
 
-	bool commit() {
+	// See the note for `wire::commit()`.
+	template<class ObserverT>
+	bool commit(ObserverT &observer) {
 		bool changed = false;
 		for (const write &entry : write_queue) {
 			value<Width> elem = data[entry.index];
 			elem = elem.update(entry.val, entry.mask);
-			changed |= (data[entry.index] != elem);
+			if (data[entry.index] != elem) {
+				observer.on_update(value<Width>::chunks, data[0].data, elem.data, entry.index);
+				changed |= true;
+			}
 			data[entry.index] = elem;
 		}
 		write_queue.clear();
@@ -840,14 +907,14 @@ struct metadata {
 
 	// In debug mode, using the wrong .as_*() function will assert.
 	// In release mode, using the wrong .as_*() function will safely return a default value.
-	const unsigned    uint_value = 0;
-	const signed      sint_value = 0;
+	const uint64_t    uint_value = 0;
+	const int64_t     sint_value = 0;
 	const std::string string_value = "";
 	const double      double_value = 0.0;
 
 	metadata() : value_type(MISSING) {}
-	metadata(unsigned value) : value_type(UINT), uint_value(value) {}
-	metadata(signed value) : value_type(SINT), sint_value(value) {}
+	metadata(uint64_t value) : value_type(UINT), uint_value(value) {}
+	metadata(int64_t value) : value_type(SINT), sint_value(value) {}
 	metadata(const std::string &value) : value_type(STRING), string_value(value) {}
 	metadata(const char *value) : value_type(STRING), string_value(value) {}
 	metadata(double value) : value_type(DOUBLE), double_value(value) {}
@@ -855,12 +922,12 @@ struct metadata {
 	metadata(const metadata &) = default;
 	metadata &operator=(const metadata &) = delete;
 
-	unsigned as_uint() const {
+	uint64_t as_uint() const {
 		assert(value_type == UINT);
 		return uint_value;
 	}
 
-	signed as_sint() const {
+	int64_t as_sint() const {
 		assert(value_type == SINT);
 		return sint_value;
 	}
@@ -874,10 +941,322 @@ struct metadata {
 		assert(value_type == DOUBLE);
 		return double_value;
 	}
+
+	// Internal CXXRTL use only.
+	static std::map<std::string, metadata> deserialize(const char *ptr) {
+		std::map<std::string, metadata> result;
+		std::string name;
+		// Grammar:
+		// string   ::= [^\0]+ \0
+		// metadata ::= [uid] .{8} | s <string>
+		// map      ::= ( <string> <metadata> )* \0
+		for (;;) {
+			if (*ptr) {
+				name += *ptr++;
+			} else if (!name.empty()) {
+				ptr++;
+				auto get_u64 = [&]() {
+					uint64_t result = 0;
+					for (size_t count = 0; count < 8; count++)
+						result = (result << 8) | *ptr++;
+					return result;
+				};
+				char type = *ptr++;
+				if (type == 'u') {
+					uint64_t value = get_u64();
+					result.emplace(name, value);
+				} else if (type == 'i') {
+					int64_t value = (int64_t)get_u64();
+					result.emplace(name, value);
+				} else if (type == 'd') {
+					double dvalue;
+					uint64_t uvalue = get_u64();
+					static_assert(sizeof(dvalue) == sizeof(uvalue), "double must be 64 bits in size");
+					memcpy(&dvalue, &uvalue, sizeof(dvalue));
+					result.emplace(name, dvalue);
+				} else if (type == 's') {
+					std::string value;
+					while (*ptr)
+						value += *ptr++;
+					ptr++;
+					result.emplace(name, value);
+				} else {
+					assert(false && "Unknown type specifier");
+					return result;
+				}
+				name.clear();
+			} else {
+				return result;
+			}
+		}
+	}
 };
 
 typedef std::map<std::string, metadata> metadata_map;
 
+struct performer;
+
+// An object that allows formatting a string lazily.
+struct lazy_fmt {
+	virtual std::string operator() () const = 0;
+};
+
+// Flavor of a `$check` cell.
+enum class flavor {
+	// Corresponds to a `$assert` cell in other flows, and a Verilog `assert ()` statement.
+	ASSERT,
+	// Corresponds to a `$assume` cell in other flows, and a Verilog `assume ()` statement.
+	ASSUME,
+	// Corresponds to a `$live` cell in other flows, and a Verilog `assert (eventually)` statement.
+	ASSERT_EVENTUALLY,
+	// Corresponds to a `$fair` cell in other flows, and a Verilog `assume (eventually)` statement.
+	ASSUME_EVENTUALLY,
+	// Corresponds to a `$cover` cell in other flows, and a Verilog `cover ()` statement.
+	COVER,
+};
+
+// An object that can be passed to a `eval()` method in order to act on side effects. The default behavior implemented
+// below is the same as the behavior of `eval(nullptr)`, except that `-print-output` option of `write_cxxrtl` is not
+// taken into account.
+struct performer {
+	// Called by generated formatting code to evaluate a Verilog `$time` expression.
+	virtual int64_t vlog_time() const { return 0; }
+
+	// Called by generated formatting code to evaluate a Verilog `$realtime` expression.
+	virtual double vlog_realtime() const { return vlog_time(); }
+
+	// Called when a `$print` cell is triggered.
+	virtual void on_print(const lazy_fmt &formatter, const metadata_map &attributes) {
+		std::cout << formatter();
+	}
+
+	// Called when a `$check` cell is triggered.
+	virtual void on_check(flavor type, bool condition, const lazy_fmt &formatter, const metadata_map &attributes) {
+		if (type == flavor::ASSERT || type == flavor::ASSUME) {
+			if (!condition)
+				std::cerr << formatter();
+			CXXRTL_ASSERT(condition && "Check failed");
+		}
+	}
+};
+
+// An object that can be passed to a `commit()` method in order to produce a replay log of every state change in
+// the simulation. Unlike `performer`, `observer` does not use virtual calls as their overhead is unacceptable, and
+// a comparatively heavyweight template-based solution is justified.
+struct observer {
+	// Called when the `commit()` method for a wire is about to update the `chunks` chunks at `base` with `chunks` chunks
+	// at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to the wire chunk count and
+	// `base` points to the first chunk.
+	void on_update(size_t chunks, const chunk_t *base, const chunk_t *value) {}
+
+	// Called when the `commit()` method for a memory is about to update the `chunks` chunks at `&base[chunks * index]`
+	// with `chunks` chunks at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to
+	// the memory element chunk count and `base` points to the first chunk of the first element of the memory.
+	void on_update(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) {}
+};
+
+// Must be kept in sync with `struct FmtPart` in kernel/fmt.h!
+// Default member initializers would make this a non-aggregate-type in C++11, so they are commented out.
+struct fmt_part {
+	enum {
+		LITERAL   = 0,
+		INTEGER   = 1,
+		STRING    = 2,
+		UNICHAR   = 3,
+		VLOG_TIME = 4,
+	} type;
+
+	// LITERAL type
+	std::string str;
+
+	// INTEGER/STRING/UNICHAR types
+	// + value<Bits> val;
+
+	// INTEGER/STRING/VLOG_TIME types
+	enum {
+		RIGHT	= 0,
+		LEFT	= 1,
+		NUMERIC	= 2,
+	} justify; // = RIGHT;
+	char padding; // = '\0';
+	size_t width; // = 0;
+
+	// INTEGER type
+	unsigned base; // = 10;
+	bool signed_; // = false;
+	enum {
+		MINUS		= 0,
+		PLUS_MINUS	= 1,
+		SPACE_MINUS	= 2,
+	} sign; // = MINUS;
+	bool hex_upper; // = false;
+	bool show_base; // = false;
+	bool group; // = false;
+
+	// VLOG_TIME type
+	bool realtime; // = false;
+	// + int64_t itime;
+	// + double ftime;
+
+	// Format the part as a string.
+	//
+	// The values of `vlog_time` and `vlog_realtime` are used for Verilog `$time` and `$realtime`, correspondingly.
+	template<size_t Bits>
+	std::string render(value<Bits> val, performer *performer = nullptr)
+	{
+		// We might want to replace some of these bit() calls with direct
+		// chunk access if it turns out to be slow enough to matter.
+		std::string buf;
+		std::string prefix;
+		switch (type) {
+			case LITERAL:
+				return str;
+
+			case STRING: {
+				buf.reserve(Bits/8);
+				for (int i = 0; i < Bits; i += 8) {
+					char ch = 0;
+					for (int j = 0; j < 8 && i + j < int(Bits); j++)
+						if (val.bit(i + j))
+							ch |= 1 << j;
+					if (ch != 0)
+						buf.append({ch});
+				}
+				std::reverse(buf.begin(), buf.end());
+				break;
+			}
+
+			case UNICHAR: {
+				uint32_t codepoint = val.template get<uint32_t>();
+				if (codepoint >= 0x10000)
+					buf += (char)(0xf0 |  (codepoint >> 18));
+				else if (codepoint >= 0x800)
+					buf += (char)(0xe0 |  (codepoint >> 12));
+				else if (codepoint >= 0x80)
+					buf += (char)(0xc0 |  (codepoint >>  6));
+				else
+					buf += (char)codepoint;
+				if (codepoint >= 0x10000)
+					buf += (char)(0x80 | ((codepoint >> 12) & 0x3f));
+				if (codepoint >= 0x800)
+					buf += (char)(0x80 | ((codepoint >>  6) & 0x3f));
+				if (codepoint >= 0x80)
+					buf += (char)(0x80 | ((codepoint >>  0) & 0x3f));
+				break;
+			}
+
+			case INTEGER: {
+				bool negative = signed_ && val.is_neg();
+				if (negative) {
+					prefix = "-";
+					val = val.neg();
+				} else {
+					switch (sign) {
+						case MINUS:       break;
+						case PLUS_MINUS:  prefix = "+"; break;
+						case SPACE_MINUS: prefix = " "; break;
+					}
+				}
+
+				size_t val_width = Bits;
+				if (base != 10) {
+					val_width = 1;
+					for (size_t index = 0; index < Bits; index++)
+						if (val.bit(index))
+							val_width = index + 1;
+				}
+
+				if (base == 2) {
+					if (show_base)
+						prefix += "0b";
+					for (size_t index = 0; index < val_width; index++) {
+						if (group && index > 0 && index % 4 == 0)
+							buf += '_';
+						buf += (val.bit(index) ? '1' : '0');
+					}
+				} else if (base == 8 || base == 16) {
+					if (show_base)
+						prefix += (base == 16) ? (hex_upper ? "0X" : "0x") : "0o";
+					size_t step = (base == 16) ? 4 : 3;
+					for (size_t index = 0; index < val_width; index += step) {
+						if (group && index > 0 && index % (4 * step) == 0)
+							buf += '_';
+						uint8_t value = val.bit(index) | (val.bit(index + 1) << 1) | (val.bit(index + 2) << 2);
+						if (step == 4)
+							value |= val.bit(index + 3) << 3;
+						buf += (hex_upper ? "0123456789ABCDEF" : "0123456789abcdef")[value];
+					}
+				} else if (base == 10) {
+					if (show_base)
+						prefix += "0d";
+					if (val.is_zero())
+						buf += '0';
+					value<(Bits > 4 ? Bits : 4)> xval = val.template zext<(Bits > 4 ? Bits : 4)>();
+					size_t index = 0;
+					while (!xval.is_zero()) {
+						if (group && index > 0 && index % 3 == 0)
+							buf += '_';
+						value<(Bits > 4 ? Bits : 4)> quotient, remainder;
+						if (Bits >= 4)
+							std::tie(quotient, remainder) = xval.udivmod(value<(Bits > 4 ? Bits : 4)>{10u});
+						else
+							std::tie(quotient, remainder) = std::make_pair(value<(Bits > 4 ? Bits : 4)>{0u}, xval);
+						buf += '0' + remainder.template trunc<4>().template get<uint8_t>();
+						xval = quotient;
+						index++;
+					}
+				} else assert(false && "Unsupported base for fmt_part");
+				if (justify == NUMERIC && group && padding == '0') {
+					int group_size = base == 10 ? 3 : 4;
+					while (prefix.size() + buf.size() < width) {
+						if (buf.size() % (group_size + 1) == group_size)
+							buf += '_';
+						buf += '0';
+					}
+				}
+				std::reverse(buf.begin(), buf.end());
+				break;
+			}
+
+			case VLOG_TIME: {
+				if (performer) {
+					buf = realtime ? std::to_string(performer->vlog_realtime()) : std::to_string(performer->vlog_time());
+				} else {
+					buf = realtime ? std::to_string(0.0) : std::to_string(0);
+				}
+				break;
+			}
+		}
+
+		std::string str;
+		assert(width == 0 || padding != '\0');
+		if (prefix.size() + buf.size() < width) {
+			size_t pad_width = width - prefix.size() - buf.size();
+			switch (justify) {
+				case LEFT:
+					str += prefix;
+					str += buf;
+					str += std::string(pad_width, padding);
+					break;
+				case RIGHT:
+					str += std::string(pad_width, padding);
+					str += prefix;
+					str += buf;
+					break;
+				case NUMERIC:
+					str += prefix;
+					str += std::string(pad_width, padding);
+					str += buf;
+					break;
+				}
+		} else {
+			str += prefix;
+			str += buf;
+		}
+		return str;
+	}
+};
+
 // Tag class to disambiguate values/wires and their aliases.
 struct debug_alias {};
 
@@ -889,6 +1268,9 @@ using debug_outline = ::_cxxrtl_outline;
 //
 // To avoid violating strict aliasing rules, this structure has to be a subclass of the one used
 // in the C API, or it would not be possible to cast between the pointers to these.
+//
+// The `attrs` member cannot be owned by this structure because a `cxxrtl_object` can be created
+// from external C code.
 struct debug_item : ::cxxrtl_object {
 	// Object types.
 	enum : uint32_t {
@@ -913,7 +1295,7 @@ struct debug_item : ::cxxrtl_object {
 
 	template<size_t Bits>
 	debug_item(value<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {
-		static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
+		static_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
 		              "value<Bits> is not compatible with C layout");
 		type    = VALUE;
 		flags   = flags_;
@@ -924,11 +1306,12 @@ struct debug_item : ::cxxrtl_object {
 		curr    = item.data;
 		next    = item.data;
 		outline = nullptr;
+		attrs   = nullptr;
 	}
 
 	template<size_t Bits>
 	debug_item(const value<Bits> &item, size_t lsb_offset = 0) {
-		static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
+		static_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
 		              "value<Bits> is not compatible with C layout");
 		type    = VALUE;
 		flags   = DRIVEN_COMB;
@@ -939,12 +1322,14 @@ struct debug_item : ::cxxrtl_object {
 		curr    = const_cast<chunk_t*>(item.data);
 		next    = nullptr;
 		outline = nullptr;
+		attrs   = nullptr;
 	}
 
 	template<size_t Bits>
 	debug_item(wire<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {
-		static_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
-		              sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),
+		static_assert(Bits == 0 ||
+		              (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
+		               sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),
 		              "wire<Bits> is not compatible with C layout");
 		type    = WIRE;
 		flags   = flags_;
@@ -955,11 +1340,12 @@ struct debug_item : ::cxxrtl_object {
 		curr    = item.curr.data;
 		next    = item.next.data;
 		outline = nullptr;
+		attrs   = nullptr;
 	}
 
 	template<size_t Width>
 	debug_item(memory<Width> &item, size_t zero_offset = 0) {
-		static_assert(sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),
+		static_assert(Width == 0 || sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),
 		              "memory<Width> is not compatible with C layout");
 		type    = MEMORY;
 		flags   = 0;
@@ -970,11 +1356,12 @@ struct debug_item : ::cxxrtl_object {
 		curr    = item.data ? item.data[0].data : nullptr;
 		next    = nullptr;
 		outline = nullptr;
+		attrs   = nullptr;
 	}
 
 	template<size_t Bits>
 	debug_item(debug_alias, const value<Bits> &item, size_t lsb_offset = 0) {
-		static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
+		static_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
 		              "value<Bits> is not compatible with C layout");
 		type    = ALIAS;
 		flags   = DRIVEN_COMB;
@@ -985,12 +1372,14 @@ struct debug_item : ::cxxrtl_object {
 		curr    = const_cast<chunk_t*>(item.data);
 		next    = nullptr;
 		outline = nullptr;
+		attrs   = nullptr;
 	}
 
 	template<size_t Bits>
 	debug_item(debug_alias, const wire<Bits> &item, size_t lsb_offset = 0) {
-		static_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
-		              sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),
+		static_assert(Bits == 0 ||
+		              (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
+		               sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),
 		              "wire<Bits> is not compatible with C layout");
 		type    = ALIAS;
 		flags   = DRIVEN_COMB;
@@ -1001,11 +1390,12 @@ struct debug_item : ::cxxrtl_object {
 		curr    = const_cast<chunk_t*>(item.curr.data);
 		next    = nullptr;
 		outline = nullptr;
+		attrs   = nullptr;
 	}
 
 	template<size_t Bits>
 	debug_item(debug_outline &group, const value<Bits> &item, size_t lsb_offset = 0) {
-		static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
+		static_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
 		              "value<Bits> is not compatible with C layout");
 		type    = OUTLINE;
 		flags   = DRIVEN_COMB;
@@ -1016,6 +1406,7 @@ struct debug_item : ::cxxrtl_object {
 		curr    = const_cast<chunk_t*>(item.data);
 		next    = nullptr;
 		outline = &group;
+		attrs   = nullptr;
 	}
 
 	template<size_t Bits, class IntegerT>
@@ -1036,11 +1427,38 @@ struct debug_item : ::cxxrtl_object {
 };
 static_assert(std::is_standard_layout<debug_item>::value, "debug_item is not compatible with C layout");
 
+} // namespace cxxrtl
+
+typedef struct _cxxrtl_attr_set {
+	cxxrtl::metadata_map map;
+} *cxxrtl_attr_set;
+
+namespace cxxrtl {
+
+// Representation of an attribute set in the C++ interface.
+using debug_attrs = ::_cxxrtl_attr_set;
+
 struct debug_items {
+	// Debug items may be composed of multiple parts, but the attributes are shared between all of them.
+	// There are additional invariants, not all of which are not checked by this code:
+	// - Memories and non-memories cannot be mixed together.
+	// - Bit indices (considering `lsb_at` and `width`) must not overlap.
+	// - Row indices (considering `depth` and `zero_at`) must be the same.
+	// - The `INPUT` and `OUTPUT` flags must be the same for all parts.
+	// Other than that, the parts can be quite different, e.g. it is OK to mix a value, a wire, an alias,
+	// and an outline, in the debug information for a single name in four parts.
 	std::map<std::string, std::vector<debug_item>> table;
-
-	void add(const std::string &name, debug_item &&item) {
-		std::vector<debug_item> &parts = table[name];
+	std::map<std::string, std::unique_ptr<debug_attrs>> attrs_table;
+
+	void add(const std::string &path, debug_item &&item, metadata_map &&item_attrs = {}) {
+		assert((path.empty() || path[path.size() - 1] != ' ') && path.find("  ") == std::string::npos);
+		std::unique_ptr<debug_attrs> &attrs = attrs_table[path];
+		if (attrs.get() == nullptr)
+			attrs = std::unique_ptr<debug_attrs>(new debug_attrs);
+		for (auto attr : item_attrs)
+			attrs->map.insert(attr);
+		item.attrs = attrs.get();
+		std::vector<debug_item> &parts = table[path];
 		parts.emplace_back(item);
 		std::sort(parts.begin(), parts.end(),
 			[](const debug_item &a, const debug_item &b) {
@@ -1048,31 +1466,82 @@ struct debug_items {
 			});
 	}
 
-	size_t count(const std::string &name) const {
-		if (table.count(name) == 0)
+	// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.
+	template<class... T>
+	void add(const std::string &base_path, const char *path, const char *serialized_item_attrs, T&&... args) {
+		add(base_path + path, debug_item(std::forward<T>(args)...), metadata::deserialize(serialized_item_attrs));
+	}
+
+	size_t count(const std::string &path) const {
+		if (table.count(path) == 0)
 			return 0;
-		return table.at(name).size();
+		return table.at(path).size();
 	}
 
-	const std::vector<debug_item> &parts_at(const std::string &name) const {
-		return table.at(name);
+	const std::vector<debug_item> &at(const std::string &path) const {
+		return table.at(path);
 	}
 
-	const debug_item &at(const std::string &name) const {
-		const std::vector<debug_item> &parts = table.at(name);
+	// Like `at()`, but operates only on single-part debug items.
+	const debug_item &operator [](const std::string &path) const {
+		const std::vector<debug_item> &parts = table.at(path);
 		assert(parts.size() == 1);
 		return parts.at(0);
 	}
 
-	const debug_item &operator [](const std::string &name) const {
-		return at(name);
+	bool is_memory(const std::string &path) const {
+		return at(path).at(0).type == debug_item::MEMORY;
+	}
+
+	const metadata_map &attrs(const std::string &path) const {
+		return attrs_table.at(path)->map;
 	}
 };
 
-// Tag class to disambiguate the default constructor used by the toplevel module that calls reset(),
+// Only `module` scopes are defined. The type is implicit, since Yosys does not currently support
+// any other scope types.
+struct debug_scope {
+	std::string module_name;
+	std::unique_ptr<debug_attrs> module_attrs;
+	std::unique_ptr<debug_attrs> cell_attrs;
+};
+
+struct debug_scopes {
+	std::map<std::string, debug_scope> table;
+
+	void add(const std::string &path, const std::string &module_name, metadata_map &&module_attrs, metadata_map &&cell_attrs) {
+		assert((path.empty() || path[path.size() - 1] != ' ') && path.find("  ") == std::string::npos);
+		assert(table.count(path) == 0);
+		debug_scope &scope = table[path];
+		scope.module_name = module_name;
+		scope.module_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { module_attrs });
+		scope.cell_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { cell_attrs });
+	}
+
+	// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.
+	void add(const std::string &base_path, const char *path, const char *module_name, const char *serialized_module_attrs, const char *serialized_cell_attrs) {
+		add(base_path + path, module_name, metadata::deserialize(serialized_module_attrs), metadata::deserialize(serialized_cell_attrs));
+	}
+
+	size_t contains(const std::string &path) const {
+		return table.count(path);
+	}
+
+	const debug_scope &operator [](const std::string &path) const {
+		return table.at(path);
+	}
+};
+
+// Tag class to disambiguate the default constructor used by the toplevel module that calls `reset()`,
 // and the constructor of interior modules that should not call it.
 struct interior {};
 
+// The core API of the `module` class consists of only four virtual methods: `reset()`, `eval()`,
+// `commit`, and `debug_info()`. (The virtual destructor is made necessary by C++.) Every other method
+// is a convenience method, and exists solely to simplify some common pattern for C++ API consumers.
+// No behavior may be added to such convenience methods that other parts of CXXRTL can rely on, since
+// there is no guarantee they will be called (and, for example, other CXXRTL libraries will often call
+// the `eval()` and `commit()` directly instead, as well as being exposed in the C API).
 struct module {
 	module() {}
 	virtual ~module() {}
@@ -1088,21 +1557,35 @@ struct module {
 
 	virtual void reset() = 0;
 
-	virtual bool eval() = 0;
+	// The `eval()` callback object, `performer`, is included in the virtual call signature since
+	// the generated code has broadly identical performance properties.
+	virtual bool eval(performer *performer = nullptr) = 0;
+
+	// The `commit()` callback object, `observer`, is not included in the virtual call signature since
+	// the generated code is severely pessimized by it. To observe commit events, the non-virtual
+	// `commit(observer *)` overload must be called directly on a `module` subclass.
 	virtual bool commit() = 0;
 
-	size_t step() {
+	size_t step(performer *performer = nullptr) {
 		size_t deltas = 0;
 		bool converged = false;
 		do {
-			converged = eval();
+			converged = eval(performer);
 			deltas++;
 		} while (commit() && !converged);
 		return deltas;
 	}
 
-	virtual void debug_info(debug_items &items, std::string path = "") {
-		(void)items, (void)path;
+	virtual void debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs = {}) {
+		(void)items, (void)scopes, (void)path, (void)cell_attrs;
+	}
+
+	// Compatibility method.
+#if __has_attribute(deprecated)
+	__attribute__((deprecated("Use `debug_info(&items, /*scopes=*/nullptr, path);` instead.")))
+#endif
+	void debug_info(debug_items &items, std::string path) {
+		debug_info(&items, /*scopes=*/nullptr, path);
 	}
 };
 
@@ -1520,35 +2003,23 @@ CXXRTL_ALWAYS_INLINE
 std::pair<value<BitsY>, value<BitsY>> divmod_uu(const value<BitsA> &a, const value<BitsB> &b) {
 	constexpr size_t Bits = max(BitsY, max(BitsA, BitsB));
 	value<Bits> quotient;
+	value<Bits> remainder;
 	value<Bits> dividend = a.template zext<Bits>();
 	value<Bits> divisor = b.template zext<Bits>();
-	if (dividend.ucmp(divisor))
-		return {/*quotient=*/value<BitsY> { 0u }, /*remainder=*/dividend.template trunc<BitsY>()};
-	uint32_t divisor_shift = dividend.ctlz() - divisor.ctlz();
-	divisor = divisor.shl(value<32> { divisor_shift });
-	for (size_t step = 0; step <= divisor_shift; step++) {
-		quotient = quotient.shl(value<1> { 1u });
-		if (!dividend.ucmp(divisor)) {
-			dividend = dividend.sub(divisor);
-			quotient.set_bit(0, true);
-		}
-		divisor = divisor.shr(value<1> { 1u });
-	}
-	return {quotient.template trunc<BitsY>(), /*remainder=*/dividend.template trunc<BitsY>()};
+	std::tie(quotient, remainder) = dividend.udivmod(divisor);
+	return {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};
 }
 
 template<size_t BitsY, size_t BitsA, size_t BitsB>
 CXXRTL_ALWAYS_INLINE
 std::pair<value<BitsY>, value<BitsY>> divmod_ss(const value<BitsA> &a, const value<BitsB> &b) {
-	value<BitsA + 1> ua = a.template sext<BitsA + 1>();
-	value<BitsB + 1> ub = b.template sext<BitsB + 1>();
-	if (ua.is_neg()) ua = ua.neg();
-	if (ub.is_neg()) ub = ub.neg();
-	value<BitsY> y, r;
-	std::tie(y, r) = divmod_uu<BitsY>(ua, ub);
-	if (a.is_neg() != b.is_neg()) y = y.neg();
-	if (a.is_neg()) r = r.neg();
-	return {y, r};
+	constexpr size_t Bits = max(BitsY, max(BitsA, BitsB));
+	value<Bits> quotient;
+	value<Bits> remainder;
+	value<Bits> dividend = a.template sext<Bits>();
+	value<Bits> divisor = b.template sext<Bits>();
+	std::tie(quotient, remainder) = dividend.sdivmod(divisor);
+	return {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};
 }
 
 template<size_t BitsY, size_t BitsA, size_t BitsB>
diff --git a/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h
new file mode 100644
index 00000000000..9aa3e105d2c
--- /dev/null
+++ b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h
@@ -0,0 +1,873 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2023  Catherine <whitequark@whitequark.org>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef CXXRTL_REPLAY_H
+#define CXXRTL_REPLAY_H
+
+#if !defined(WIN32)
+#include <unistd.h>
+#define O_BINARY 0
+#else
+#include <io.h>
+#endif
+
+#include <fcntl.h>
+#include <cstring>
+#include <cstdio>
+#include <atomic>
+#include <unordered_map>
+
+#include <cxxrtl/cxxrtl.h>
+#include <cxxrtl/cxxrtl_time.h>
+
+// Theory of operation
+// ===================
+//
+// Log format
+// ----------
+//
+// The replay log is a simple data format based on a sequence of 32-bit words. The following BNF-like grammar describes
+// enough detail to understand the overall structure of the log data and be able to read hex dumps. For a greater
+// degree of detail see the source code. The format is considered fully internal to CXXRTL and is subject to change
+// without notice.
+//
+// <file>           ::= <file-header> <definitions> <sample>+
+// <file-header>    ::= 0x52585843 0x00004c54
+// <definitions>    ::= <packet-define>* <packet-end>
+// <sample>         ::= <packet-sample> (<packet-change> | <packet-diag>)* <packet-end>
+// <packet-define>  ::= 0xc0000000 ...
+// <packet-sample>  ::= 0xc0000001 ...
+// <packet-change>  ::= 0x0??????? <chunk>+ | 0x1??????? <index> <chunk>+ | 0x2??????? | 0x3???????
+// <chunk>, <index> ::= 0x????????
+// <packet-diag>    ::= <packet-break> | <packet-print> | <packet-assert> | <packet-assume>
+// <packet-break>   ::= 0xc0000010 <message> <source-location>
+// <packet-print>   ::= 0xc0000011 <message> <source-location>
+// <packet-assert>  ::= 0xc0000012 <message> <source-location>
+// <packet-assume>  ::= 0xc0000013 <message> <source-location>
+// <packet-end>     ::= 0xFFFFFFFF
+//
+// The replay log contains sample data, however, it does not cover the entire design. Rather, it only contains sample
+// data for the subset of debug items containing _design state_: inputs and registers/latches. This keeps its size to
+// a minimum, and recording speed to a maximum. The player samples any missing data by setting the design state items
+// to the same values they had during recording, and re-evaluating the design.
+//
+// Packets for diagnostics (prints, breakpoints, assertions, and assumptions) are used solely for diagnostics emitted
+// by the C++ testbench driving the simulation, and are not recorded while evaluating the design. (Diagnostics emitted
+// by the RTL can be reconstructed at replay time, so recording them would be a waste of space.)
+//
+// Limits
+// ------
+//
+// The log may contain:
+//
+// * Up to 2**28-1 debug items containing design state.
+// * Up to 2**32 chunks per debug item.
+// * Up to 2**32 rows per memory.
+// * Up to 2**32 samples.
+//
+// Of these limits, the last two are most likely to be eventually exceeded by practical recordings. However, other
+// performance considerations will likely limit the size of such practical recordings first, so the log data format
+// will undergo a breaking change at that point.
+//
+// Operations
+// ----------
+//
+// As suggested by the name "replay log", this format is designed for recording (writing) once and playing (reading)
+// many times afterwards, such that reading the format can be done linearly and quickly. The log format is designed to
+// support three primary read operations:
+//
+// 1. Initialization
+// 2. Rewinding (to time T)
+// 3. Replaying (for N samples)
+//
+// During initialization, the player establishes the mapping between debug item names and their 28-bit identifiers in
+// the log. It is done once.
+//
+// During rewinding, the player begins reading at the latest non-incremental sample that still lies before the requested
+// sample time. It continues reading incremental samples after that point until it reaches the requested sample time.
+// This process is very cheap as the design is not evaluated; it is essentially a (convoluted) memory copy operation.
+//
+// During replaying, the player evaluates the design at the current time, which causes all debug items to assume
+// the values they had before recording. This process is expensive. Once done, the player advances to the next state
+// by reading the next (complete or incremental) sample, as above. Since a range of samples is replayed, this process
+// is repeated several times in a row.
+//
+// In principle, when replaying, the player could only read the state of the inputs and the time delta and use a normal
+// eval/commit loop to progress the simulation, which is fully deterministic so its calculated design state should be
+// exactly the same as the recorded design state. In practice, it is both faster and more reliable (in presence of e.g.
+// user-defined black boxes) to read the recorded values instead of calculating them.
+//
+// Note: The operations described above are conceptual and do not correspond exactly to methods on `cxxrtl::player`.
+// The `cxxrtl::player::replay()` method does not evaluate the design. This is so that delta cycles could be ignored
+// if they are not of interest while replaying.
+
+namespace cxxrtl {
+
+// A single diagnostic that can be manipulated as an object (including being written to and read from a file).
+// This differs from the base CXXRTL interface, where diagnostics can only be emitted via a procedure call, and are
+// not materialized as objects.
+struct diagnostic {
+	// The `BREAK` flavor corresponds to a breakpoint, which is a diagnostic type that can currently only be emitted
+	// by the C++ testbench code.
+	enum flavor {
+		BREAK  = 0,
+		PRINT  = 1,
+		ASSERT = 2,
+		ASSUME = 3,
+	};
+
+	flavor type;
+	std::string message;
+	std::string location; // same format as the `src` attribute of `$print` or `$check` cell
+
+	diagnostic()
+	: type(BREAK) {}
+
+	diagnostic(flavor type, const std::string &message, const std::string &location)
+	: type(type), message(message), location(location) {}
+
+	diagnostic(flavor type, const std::string &message, const char *file, unsigned line)
+	: type(type), message(message), location(std::string(file) + ':' + std::to_string(line)) {}
+};
+
+// A spool stores CXXRTL design state changes in a file.
+class spool {
+public:
+	// Unique pointer to a specific sample within a replay log. (Timestamps are not unique.)
+	typedef uint32_t pointer_t;
+
+	// Numeric identifier assigned to a debug item within a replay log. Range limited to [1, MAXIMUM_IDENT].
+	typedef uint32_t ident_t;
+
+	static constexpr uint16_t VERSION = 0x0400;
+
+	static constexpr uint64_t HEADER_MAGIC = 0x00004c5452585843;
+	static constexpr uint64_t VERSION_MASK = 0xffff000000000000;
+
+	static constexpr uint32_t PACKET_DEFINE  = 0xc0000000;
+
+	static constexpr uint32_t PACKET_SAMPLE  = 0xc0000001;
+	enum sample_flag : uint32_t {
+		EMPTY       = 0,
+		INCREMENTAL = 1,
+	};
+
+	static constexpr uint32_t MAXIMUM_IDENT  = 0x0fffffff;
+	static constexpr uint32_t CHANGE_MASK    = 0x30000000;
+
+	static constexpr uint32_t PACKET_CHANGE  = 0x00000000/* | ident */;
+	static constexpr uint32_t PACKET_CHANGEI = 0x10000000/* | ident */;
+	static constexpr uint32_t PACKET_CHANGEL = 0x20000000/* | ident */;
+	static constexpr uint32_t PACKET_CHANGEH = 0x30000000/* | ident */;
+
+	static constexpr uint32_t PACKET_DIAGNOSTIC = 0xc0000010/* | diagnostic::flavor */;
+	static constexpr uint32_t DIAGNOSTIC_MASK   = 0x0000000f;
+
+	static constexpr uint32_t PACKET_END     = 0xffffffff;
+
+	// Writing spools.
+
+	class writer {
+		int fd;
+		size_t position;
+		std::vector<uint32_t> buffer;
+
+		// These functions aren't overloaded because of implicit numeric conversions.
+
+		void emit_word(uint32_t word) {
+			if (position + 1 == buffer.size())
+				flush();
+			buffer[position++] = word;
+		}
+
+		void emit_dword(uint64_t dword) {
+			emit_word(dword >>  0);
+			emit_word(dword >> 32);
+		}
+
+		void emit_ident(ident_t ident) {
+			assert(ident <= MAXIMUM_IDENT);
+			emit_word(ident);
+		}
+
+		void emit_size(size_t size) {
+			assert(size <= std::numeric_limits<uint32_t>::max());
+			emit_word(size);
+		}
+
+		// Same implementation as `emit_size()`, different declared intent.
+		void emit_index(size_t index) {
+			assert(index <= std::numeric_limits<uint32_t>::max());
+			emit_word(index);
+		}
+
+		void emit_string(std::string str) {
+			// Align to a word boundary, and add at least one terminating \0.
+			str.resize(str.size() + (sizeof(uint32_t) - (str.size() + sizeof(uint32_t)) % sizeof(uint32_t)));
+			for (size_t index = 0; index < str.size(); index += sizeof(uint32_t)) {
+				uint32_t word;
+				memcpy(&word, &str[index], sizeof(uint32_t));
+				emit_word(word);
+			}
+		}
+
+		void emit_time(const time &timestamp) {
+			const value<time::bits> &raw_timestamp(timestamp);
+			emit_word(raw_timestamp.data[0]);
+			emit_word(raw_timestamp.data[1]);
+			emit_word(raw_timestamp.data[2]);
+		}
+
+	public:
+		// Creates a writer, and transfers ownership of `fd`, which must be open for appending.
+		//
+		// The buffer size is currently fixed to a "reasonably large" size, determined empirically by measuring writer
+		// performance on a representative design; large but not so large it would e.g. cause address space exhaustion
+		// on 32-bit platforms.
+		writer(spool &spool) : fd(spool.take_write()), position(0), buffer(32 * 1024 * 1024) {
+			assert(fd != -1);
+#if !defined(WIN32)
+			int result = ftruncate(fd, 0);
+#else
+			int result = _chsize_s(fd, 0);
+#endif
+			assert(result == 0);
+		}
+
+		writer(writer &&moved) : fd(moved.fd), position(moved.position), buffer(moved.buffer) {
+			moved.fd = -1;
+			moved.position = 0;
+		}
+
+		writer(const writer &) = delete;
+		writer &operator=(const writer &) = delete;
+
+		// Both write() calls and fwrite() calls are too expensive to perform implicitly. The API consumer must determine
+		// the optimal time to flush the writer and do that explicitly for best performance.
+		void flush() {
+			assert(fd != -1);
+			size_t data_size = position * sizeof(uint32_t);
+			size_t data_written = write(fd, buffer.data(), data_size);
+			assert(data_size == data_written);
+			position = 0;
+		}
+
+		~writer() {
+			if (fd != -1) {
+				flush();
+				close(fd);
+			}
+		}
+
+		void write_magic() {
+			// `CXXRTL` followed by version in binary. This header will read backwards on big-endian machines, which allows
+			// detection of this case, both visually and programmatically.
+			emit_dword(((uint64_t)VERSION << 48) | HEADER_MAGIC);
+		}
+
+		void write_define(ident_t ident, const std::string &name, size_t part_index, size_t chunks, size_t depth) {
+			emit_word(PACKET_DEFINE);
+			emit_ident(ident);
+			emit_string(name);
+			emit_index(part_index);
+			emit_size(chunks);
+			emit_size(depth);
+		}
+
+		void write_sample(bool incremental, pointer_t pointer, const time &timestamp) {
+			uint32_t flags = (incremental ? sample_flag::INCREMENTAL : 0);
+			emit_word(PACKET_SAMPLE);
+			emit_word(flags);
+			emit_word(pointer);
+			emit_time(timestamp);
+		}
+
+		void write_change(ident_t ident, size_t chunks, const chunk_t *data) {
+			assert(ident <= MAXIMUM_IDENT);
+
+			if (chunks == 1 && *data == 0) {
+				emit_word(PACKET_CHANGEL | ident);
+			} else if (chunks == 1 && *data == 1) {
+				emit_word(PACKET_CHANGEH | ident);
+			} else {
+				emit_word(PACKET_CHANGE | ident);
+				for (size_t offset = 0; offset < chunks; offset++)
+					emit_word(data[offset]);
+			}
+		}
+
+		void write_change(ident_t ident, size_t chunks, const chunk_t *data, size_t index) {
+			assert(ident <= MAXIMUM_IDENT);
+
+			emit_word(PACKET_CHANGEI | ident);
+			emit_index(index);
+			for (size_t offset = 0; offset < chunks; offset++)
+				emit_word(data[offset]);
+		}
+
+		void write_diagnostic(const diagnostic &diagnostic) {
+			emit_word(PACKET_DIAGNOSTIC | diagnostic.type);
+			emit_string(diagnostic.message);
+			emit_string(diagnostic.location);
+		}
+
+		void write_end() {
+			emit_word(PACKET_END);
+		}
+	};
+
+	// Reading spools.
+
+	class reader {
+		FILE *f;
+
+		uint32_t absorb_word() {
+			// If we're at end of file, `fread` will not write to `word`, and `PACKET_END` will be returned.
+			uint32_t word = PACKET_END;
+			fread(&word, sizeof(word), 1, f);
+			return word;
+		}
+
+		uint64_t absorb_dword() {
+			uint32_t lo = absorb_word();
+			uint32_t hi = absorb_word();
+			return ((uint64_t)hi << 32) | lo;
+		}
+
+		ident_t absorb_ident() {
+			ident_t ident = absorb_word();
+			assert(ident <= MAXIMUM_IDENT);
+			return ident;
+		}
+
+		size_t absorb_size() {
+			return absorb_word();
+		}
+
+		size_t absorb_index() {
+			return absorb_word();
+		}
+
+		std::string absorb_string() {
+			std::string str;
+			do {
+				size_t end = str.size();
+				str.resize(end + 4);
+				uint32_t word = absorb_word();
+				memcpy(&str[end], &word, sizeof(uint32_t));
+			} while (str.back() != '\0');
+			// Strings have no embedded zeroes besides the terminating one(s).
+			return str.substr(0, str.find('\0'));
+		}
+
+		time absorb_time() {
+			value<time::bits> raw_timestamp;
+			raw_timestamp.data[0] = absorb_word();
+			raw_timestamp.data[1] = absorb_word();
+			raw_timestamp.data[2] = absorb_word();
+			return time(raw_timestamp);
+		}
+
+	public:
+		typedef uint64_t pos_t;
+
+		// Creates a reader, and transfers ownership of `fd`, which must be open for reading.
+		reader(spool &spool) : f(fdopen(spool.take_read(), "r")) {
+			assert(f != nullptr);
+		}
+
+		reader(reader &&moved) : f(moved.f) {
+			moved.f = nullptr;
+		}
+
+		reader(const reader &) = delete;
+		reader &operator=(const reader &) = delete;
+
+		~reader() {
+			if (f != nullptr)
+				fclose(f);
+		}
+
+		pos_t position() {
+			return ftell(f);
+		}
+
+		void rewind(pos_t position) {
+			fseek(f, position, SEEK_SET);
+		}
+
+		void read_magic() {
+			uint64_t magic = absorb_dword();
+			assert((magic & ~VERSION_MASK) == HEADER_MAGIC);
+			assert((magic >> 48) == VERSION);
+		}
+
+		bool read_define(ident_t &ident, std::string &name, size_t &part_index, size_t &chunks, size_t &depth) {
+			uint32_t header = absorb_word();
+			if (header == PACKET_END)
+				return false;
+			assert(header == PACKET_DEFINE);
+			ident = absorb_ident();
+			name = absorb_string();
+			part_index = absorb_index();
+			chunks = absorb_size();
+			depth = absorb_size();
+			return true;
+		}
+
+		bool read_sample(bool &incremental, pointer_t &pointer, time &timestamp) {
+			uint32_t header = absorb_word();
+			if (header == PACKET_END)
+				return false;
+			assert(header == PACKET_SAMPLE);
+			uint32_t flags = absorb_word();
+			incremental = (flags & sample_flag::INCREMENTAL);
+			pointer = absorb_word();
+			timestamp = absorb_time();
+			return true;
+		}
+
+		bool read_header(uint32_t &header) {
+			header = absorb_word();
+			return header != PACKET_END;
+		}
+
+		// This method must be separate from `read_change_data` because `chunks` and `depth` can only be looked up
+		// if `ident` is known.
+		bool read_change_ident(uint32_t header, ident_t &ident) {
+			if ((header & ~(CHANGE_MASK | MAXIMUM_IDENT)) != 0)
+				return false; // some other packet
+			ident = header & MAXIMUM_IDENT;
+			return true;
+		}
+
+		void read_change_data(uint32_t header, size_t chunks, size_t depth, chunk_t *data) {
+			uint32_t index = 0;
+			switch (header & CHANGE_MASK) {
+				case PACKET_CHANGEL:
+					*data = 0;
+					return;
+				case PACKET_CHANGEH:
+					*data = 1;
+					return;
+				case PACKET_CHANGE:
+					break;
+				case PACKET_CHANGEI:
+					index = absorb_word();
+					assert(index < depth);
+					break;
+				default:
+					assert(false && "Unrecognized change packet");
+			}
+			for (size_t offset = 0; offset < chunks; offset++)
+				data[chunks * index + offset] = absorb_word();
+		}
+
+		bool read_diagnostic(uint32_t header, diagnostic &diagnostic) {
+			if ((header & ~DIAGNOSTIC_MASK) != PACKET_DIAGNOSTIC)
+				return false; // some other packet
+			uint32_t type = header & DIAGNOSTIC_MASK;
+			assert(type == diagnostic::BREAK  || type == diagnostic::PRINT ||
+			       type == diagnostic::ASSERT || type == diagnostic::ASSUME);
+			diagnostic.type = (diagnostic::flavor)type;
+			diagnostic.message = absorb_string();
+			diagnostic.location = absorb_string();
+			return true;
+		}
+	};
+
+	// Opening spools. For certain uses of the record/replay mechanism, two distinct open files (two open files, i.e.
+	// two distinct file pointers, and not just file descriptors, which share the file pointer if duplicated) are used,
+	// for a reader and writer thread. This class manages the lifetime of the descriptors for these files. When only
+	// one of them is used, the other is closed harmlessly when the spool is destroyed.
+private:
+	std::atomic<int> writefd;
+	std::atomic<int> readfd;
+
+public:
+	spool(const std::string &filename)
+		: writefd(open(filename.c_str(), O_CREAT|O_BINARY|O_WRONLY|O_APPEND, 0644)),
+		  readfd(open(filename.c_str(), O_BINARY|O_RDONLY)) {
+		assert(writefd.load() != -1 && readfd.load() != -1);
+	}
+
+	spool(spool &&moved) : writefd(moved.writefd.exchange(-1)), readfd(moved.readfd.exchange(-1)) {}
+
+	spool(const spool &) = delete;
+	spool &operator=(const spool &) = delete;
+
+	~spool() {
+		int fd;
+		if ((fd = writefd.exchange(-1)) != -1)
+			close(fd);
+		if ((fd = readfd.exchange(-1)) != -1)
+			close(fd);
+	}
+
+	// Atomically acquire a write file descriptor for the spool. Can be called once, and will return -1 the next time
+	// it is called. Thread-safe.
+	int take_write() {
+		return writefd.exchange(-1);
+	}
+
+	// Atomically acquire a read file descriptor for the spool. Can be called once, and will return -1 the next time
+	// it is called. Thread-safe.
+	int take_read() {
+		return readfd.exchange(-1);
+	}
+};
+
+// A CXXRTL recorder samples design state, producing complete or incremental updates, and writes them to a spool.
+class recorder {
+	struct variable {
+		spool::ident_t ident; /* <= spool::MAXIMUM_IDENT */
+		size_t chunks;
+		size_t depth; /* == 1 for wires */
+		chunk_t *curr;
+		bool memory;
+	};
+
+	spool::writer writer;
+	std::vector<variable> variables;
+	std::vector<size_t> inputs; // values of inputs must be recorded explicitly, as their changes are not observed
+	std::unordered_map<const chunk_t*, spool::ident_t> ident_lookup;
+	bool streaming = false; // whether variable definitions have been written
+	spool::pointer_t pointer = 0;
+	time timestamp;
+
+public:
+	template<typename ...Args>
+	recorder(Args &&...args) : writer(std::forward<Args>(args)...) {}
+
+	void start(module &module, std::string top_path = "") {
+		debug_items items;
+		module.debug_info(&items, /*scopes=*/nullptr, top_path);
+		start(items);
+	}
+
+	void start(const debug_items &items) {
+		assert(!streaming);
+
+		writer.write_magic();
+		for (auto item : items.table)
+			for (size_t part_index = 0; part_index < item.second.size(); part_index++) {
+				auto &part = item.second[part_index];
+				if ((part.flags & debug_item::INPUT) || (part.flags & debug_item::DRIVEN_SYNC) ||
+						(part.type == debug_item::MEMORY)) {
+					variable var;
+					var.ident = variables.size() + 1;
+					var.chunks = (part.width + sizeof(chunk_t) * 8 - 1) / (sizeof(chunk_t) * 8);
+					var.depth = part.depth;
+					var.curr = part.curr;
+					var.memory = (part.type == debug_item::MEMORY);
+					ident_lookup[var.curr] = var.ident;
+
+					assert(variables.size() < spool::MAXIMUM_IDENT);
+					if (part.flags & debug_item::INPUT)
+						inputs.push_back(variables.size());
+					variables.push_back(var);
+
+					writer.write_define(var.ident, item.first, part_index, var.chunks, var.depth);
+				}
+			}
+		writer.write_end();
+		streaming = true;
+	}
+
+	const time &latest_time() {
+		return timestamp;
+	}
+
+	const time &advance_time(const time &delta) {
+		assert(!delta.is_negative());
+		timestamp += delta;
+		return timestamp;
+	}
+
+	void record_complete() {
+		assert(streaming);
+
+		writer.write_sample(/*incremental=*/false, pointer++, timestamp);
+		for (auto var : variables) {
+			assert(var.ident != 0);
+			if (!var.memory)
+				writer.write_change(var.ident, var.chunks, var.curr);
+			else
+				for (size_t index = 0; index < var.depth; index++)
+					writer.write_change(var.ident, var.chunks, &var.curr[var.chunks * index], index);
+		}
+		writer.write_end();
+	}
+
+	// This function is generic over ModuleT to encourage observer callbacks to be inlined into the commit function.
+	template<class ModuleT>
+	bool record_incremental(ModuleT &module) {
+		assert(streaming);
+
+		struct : observer {
+			std::unordered_map<const chunk_t*, spool::ident_t> *ident_lookup;
+			spool::writer *writer;
+
+			CXXRTL_ALWAYS_INLINE
+			void on_update(size_t chunks, const chunk_t *base, const chunk_t *value) {
+				writer->write_change(ident_lookup->at(base), chunks, value);
+			}
+
+			CXXRTL_ALWAYS_INLINE
+			void on_update(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) {
+				writer->write_change(ident_lookup->at(base), chunks, value, index);
+			}
+		} record_observer;
+		record_observer.ident_lookup = &ident_lookup;
+		record_observer.writer = &writer;
+
+		writer.write_sample(/*incremental=*/true, pointer++, timestamp);
+		for (auto input_index : inputs) {
+			variable &var = variables.at(input_index);
+			assert(!var.memory);
+			writer.write_change(var.ident, var.chunks, var.curr);
+		}
+		bool changed = module.commit(record_observer);
+		writer.write_end();
+		return changed;
+	}
+
+	void record_diagnostic(const diagnostic &diagnostic) {
+		assert(streaming);
+
+		// Emit an incremental delta cycle per diagnostic to simplify the logic of the recorder. This is inefficient, but
+		// diagnostics should be rare enough that this inefficiency does not matter. If it turns out to be an issue, this
+		// code should be changed to accumulate diagnostics to a buffer that is flushed in `record_{complete,incremental}`
+		// and also in `advance_time` before the timestamp is changed. (Right now `advance_time` never writes to the spool.)
+		writer.write_sample(/*incremental=*/true, pointer++, timestamp);
+		writer.write_diagnostic(diagnostic);
+		writer.write_end();
+	}
+
+	void flush() {
+		writer.flush();
+	}
+};
+
+// A CXXRTL player reads samples from a spool, and changes the design state accordingly. To start reading samples,
+// a spool must have been initialized: the recorder must have been started and an initial complete sample must have
+// been written.
+class player {
+	struct variable {
+		size_t chunks;
+		size_t depth; /* == 1 for wires */
+		chunk_t *curr;
+	};
+
+	spool::reader reader;
+	std::unordered_map<spool::ident_t, variable> variables;
+	bool streaming = false; // whether variable definitions have been read
+	bool initialized = false; // whether a sample has ever been read
+	spool::pointer_t pointer = 0;
+	time timestamp;
+
+	std::map<spool::pointer_t, spool::reader::pos_t, std::greater<spool::pointer_t>> index_by_pointer;
+	std::map<time, spool::reader::pos_t, std::greater<time>> index_by_timestamp;
+
+	bool peek_sample(spool::pointer_t &pointer, time &timestamp) {
+		bool incremental;
+		auto position = reader.position();
+		bool success = reader.read_sample(incremental, pointer, timestamp);
+		reader.rewind(position);
+		return success;
+	}
+
+public:
+	template<typename ...Args>
+	player(Args &&...args) : reader(std::forward<Args>(args)...) {}
+
+	// The `top_path` must match the one given to the recorder.
+	void start(module &module, std::string top_path = "") {
+		debug_items items;
+		module.debug_info(&items, /*scopes=*/nullptr, top_path);
+		start(items);
+	}
+
+	void start(const debug_items &items) {
+		assert(!streaming);
+
+		reader.read_magic();
+		while (true) {
+			spool::ident_t ident;
+			std::string name;
+			size_t part_index;
+			size_t chunks;
+			size_t depth;
+			if (!reader.read_define(ident, name, part_index, chunks, depth))
+				break;
+			assert(variables.count(ident) == 0);
+			assert(items.count(name) != 0);
+			assert(part_index < items.count(name));
+
+			const debug_item &part = items.at(name).at(part_index);
+			assert(chunks == (part.width + sizeof(chunk_t) * 8 - 1) / (sizeof(chunk_t) * 8));
+			assert(depth == part.depth);
+
+			variable &var = variables[ident];
+			var.chunks = chunks;
+			var.depth = depth;
+			var.curr = part.curr;
+		}
+		assert(variables.size() > 0);
+		streaming = true;
+
+		// Establish the initial state of the design.
+		std::vector<diagnostic> diagnostics;
+		initialized = replay(&diagnostics);
+		assert(initialized && diagnostics.empty());
+	}
+
+	// Returns the pointer of the current sample.
+	spool::pointer_t current_pointer() {
+		assert(initialized);
+		return pointer;
+	}
+
+	// Returns the time of the current sample.
+	const time &current_time() {
+		assert(initialized);
+		return timestamp;
+	}
+
+	// Returns `true` if there is a next sample to read, and sets `pointer` to its pointer if there is.
+	bool get_next_pointer(spool::pointer_t &pointer) {
+		assert(streaming);
+		time timestamp;
+		return peek_sample(pointer, timestamp);
+	}
+
+	// Returns `true` if there is a next sample to read, and sets `timestamp` to its time if there is.
+	bool get_next_time(time &timestamp) {
+		assert(streaming);
+		uint32_t pointer;
+		return peek_sample(pointer, timestamp);
+	}
+
+	// If this function returns `true`, then `current_pointer() == at_pointer`, and the module contains values that
+	// correspond to this pointer in the replay log. To obtain a valid pointer, call `current_pointer()`; while pointers
+	// are monotonically increasing for each consecutive sample, using arithmetic operations to create a new pointer is
+	// not allowed. The `diagnostics` argument, if not `nullptr`, receives the diagnostics recorded in this sample.
+	bool rewind_to(spool::pointer_t at_pointer, std::vector<diagnostic> *diagnostics) {
+		assert(initialized);
+
+		// The pointers in the replay log start from one that is greater than `at_pointer`. In this case the pointer will
+		// never be reached.
+		assert(index_by_pointer.size() > 0);
+		if (at_pointer < index_by_pointer.rbegin()->first)
+			return false;
+
+		// Find the last complete sample whose pointer is less than or equal to `at_pointer`. Note that the comparison
+		// function used here is `std::greater`, inverting the direction of `lower_bound`.
+		auto position_it = index_by_pointer.lower_bound(at_pointer);
+		assert(position_it != index_by_pointer.end());
+		reader.rewind(position_it->second);
+
+		// Replay samples until eventually arriving to `at_pointer` or encountering end of file.
+		while(replay(diagnostics)) {
+			if (pointer == at_pointer)
+				return true;
+
+			if (diagnostics)
+				diagnostics->clear();
+		}
+		return false;
+	}
+
+	// If this function returns `true`, then `current_time() <= at_or_before_timestamp`, and the module contains values
+	// that correspond to `current_time()` in the replay log. If `current_time() == at_or_before_timestamp` and there
+	// are several consecutive samples with the same time, the module contains values that correspond to the first of
+	// these samples. The `diagnostics` argument, if not `nullptr`, receives the diagnostics recorded in this sample.
+	bool rewind_to_or_before(const time &at_or_before_timestamp, std::vector<diagnostic> *diagnostics) {
+		assert(initialized);
+
+		// The timestamps in the replay log start from one that is greater than `at_or_before_timestamp`. In this case
+		// the timestamp will never be reached. Otherwise, this function will always succeed.
+		assert(index_by_timestamp.size() > 0);
+		if (at_or_before_timestamp < index_by_timestamp.rbegin()->first)
+			return false;
+
+		// Find the last complete sample whose timestamp is less than or equal to `at_or_before_timestamp`. Note that
+		// the comparison function used here is `std::greater`, inverting the direction of `lower_bound`.
+		auto position_it = index_by_timestamp.lower_bound(at_or_before_timestamp);
+		assert(position_it != index_by_timestamp.end());
+		reader.rewind(position_it->second);
+
+		// Replay samples until eventually arriving to or past `at_or_before_timestamp` or encountering end of file.
+		while (replay(diagnostics)) {
+			if (timestamp == at_or_before_timestamp)
+				break;
+
+			time next_timestamp;
+			if (!get_next_time(next_timestamp))
+				break;
+			if (next_timestamp > at_or_before_timestamp)
+				break;
+
+			if (diagnostics)
+				diagnostics->clear();
+		}
+		return true;
+	}
+
+	// If this function returns `true`, then `current_pointer()` and `current_time()` are updated for the next sample
+	// and the module now contains values that correspond to that sample. If it returns `false`, there was no next sample
+	// to read. The `diagnostics` argument, if not `nullptr`, receives the diagnostics recorded in the next sample.
+	bool replay(std::vector<diagnostic> *diagnostics) {
+		assert(streaming);
+
+		bool incremental;
+		auto position = reader.position();
+		if (!reader.read_sample(incremental, pointer, timestamp))
+			return false;
+
+		// The very first sample that is read must be a complete sample. This is required for the rewind functions to work.
+		assert(initialized || !incremental);
+
+		// It is possible (though not very useful) to have several complete samples with the same timestamp in a row.
+		// Ensure that we associate the timestamp with the position of the first such complete sample. (This condition
+		// works because the player never jumps over a sample.)
+		if (!incremental && !index_by_pointer.count(pointer)) {
+			assert(!index_by_timestamp.count(timestamp));
+			index_by_pointer[pointer] = position;
+			index_by_timestamp[timestamp] = position;
+		}
+
+		uint32_t header;
+		while (reader.read_header(header)) {
+			spool::ident_t ident;
+			diagnostic diag;
+			if (reader.read_change_ident(header, ident)) {
+				variable &var = variables.at(ident);
+				reader.read_change_data(header, var.chunks, var.depth, var.curr);
+			} else if (reader.read_diagnostic(header, diag)) {
+				if (diagnostics)
+					diagnostics->push_back(diag);
+			} else assert(false && "Unrecognized packet header");
+		}
+		return true;
+	}
+};
+
+}
+
+#endif
diff --git a/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h
new file mode 100644
index 00000000000..f37c2b65640
--- /dev/null
+++ b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h
@@ -0,0 +1,231 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2023  Catherine <whitequark@whitequark.org>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef CXXRTL_TIME_H
+#define CXXRTL_TIME_H
+
+#include <cinttypes>
+#include <string>
+
+#include <cxxrtl/cxxrtl.h>
+
+namespace cxxrtl {
+
+// A timestamp or a difference in time, stored as a 96-bit number of femtoseconds (10e-15 s). The range and resolution
+// of this format can represent any VCD timestamp within approx. ±1255321.2 years, without the need for a timescale.
+class time {
+public:
+	static constexpr size_t bits = 96; // 3 chunks
+
+private:
+	static constexpr size_t resolution_digits = 15;
+
+	static_assert(sizeof(chunk_t) == 4, "a chunk is expected to be 32-bit");
+	static constexpr value<bits> resolution = value<bits> {
+		chunk_t(1000000000000000ull & 0xffffffffull), chunk_t(1000000000000000ull >> 32), 0u
+	};
+
+	// Signed number of femtoseconds from the beginning of time.
+	value<bits> raw;
+
+public:
+	constexpr time() {}
+
+	explicit constexpr time(const value<bits> &raw) : raw(raw) {}
+	explicit operator const value<bits> &() const { return raw; }
+
+	static constexpr time maximum() {
+		return time(value<bits> { 0xffffffffu, 0xffffffffu, 0x7fffffffu });
+	}
+
+	time(int64_t secs, int64_t femtos) {
+		value<64> secs_val;
+		secs_val.set(secs);
+		value<64> femtos_val;
+		femtos_val.set(femtos);
+		raw = secs_val.sext<bits>().mul<bits>(resolution).add(femtos_val.sext<bits>());
+	}
+
+	bool is_zero() const {
+		return raw.is_zero();
+	}
+
+	// Extracts the sign of the value.
+	bool is_negative() const {
+		return raw.is_neg();
+	}
+
+	// Extracts the number of whole seconds. Negative if the value is negative.
+	int64_t secs() const {
+		return raw.sdivmod(resolution).first.trunc<64>().get<int64_t>();
+	}
+
+	// Extracts the number of femtoseconds in the fractional second. Negative if the value is negative.
+	int64_t femtos() const {
+		return raw.sdivmod(resolution).second.trunc<64>().get<int64_t>();
+	}
+
+	bool operator==(const time &other) const {
+		return raw == other.raw;
+	}
+
+	bool operator!=(const time &other) const {
+		return raw != other.raw;
+	}
+
+	bool operator>(const time &other) const {
+		return other.raw.scmp(raw);
+	}
+
+	bool operator>=(const time &other) const {
+		return !raw.scmp(other.raw);
+	}
+
+	bool operator<(const time &other) const {
+		return raw.scmp(other.raw);
+	}
+
+	bool operator<=(const time &other) const {
+		return !other.raw.scmp(raw);
+	}
+
+	time operator+(const time &other) const {
+		return time(raw.add(other.raw));
+	}
+
+	time &operator+=(const time &other) {
+		*this = *this + other;
+		return *this;
+	}
+
+	time operator-() const {
+		return time(raw.neg());
+	}
+
+	time operator-(const time &other) const {
+		return *this + (-other);
+	}
+
+	time &operator-=(const time &other) {
+		*this = *this - other;
+		return *this;
+	}
+
+	operator std::string() const {
+		char buf[48]; // x=2**95; len(f"-{x/1_000_000_000_000_000}.{x^1_000_000_000_000_000}") == 48
+		int64_t secs = this->secs();
+		int64_t femtos = this->femtos();
+		snprintf(buf, sizeof(buf), "%s%" PRIi64 ".%015" PRIi64,
+			is_negative() ? "-" : "", secs >= 0 ? secs : -secs, femtos >= 0 ? femtos : -femtos);
+		return buf;
+	}
+
+#if __cplusplus >= 201603L
+	[[nodiscard("ignoring parse errors")]]
+#endif
+	bool parse(const std::string &str) {
+		enum {
+			parse_sign_opt,
+			parse_integral,
+			parse_fractional,
+		} state = parse_sign_opt;
+		bool negative = false;
+		int64_t integral = 0;
+		int64_t fractional = 0;
+		size_t frac_digits = 0;
+		for (auto chr : str) {
+			switch (state) {
+				case parse_sign_opt:
+					state = parse_integral;
+					if (chr == '+' || chr == '-') {
+						negative = (chr == '-');
+						break;
+					}
+					/* fallthrough */
+				case parse_integral:
+					if (chr >= '0' && chr <= '9') {
+						integral *= 10;
+						integral += chr - '0';
+					} else if (chr == '.') {
+						state = parse_fractional;
+					} else {
+						return false;
+					}
+					break;
+				case parse_fractional:
+					if (chr >= '0' && chr <= '9' && frac_digits < resolution_digits) {
+						fractional *= 10;
+						fractional += chr - '0';
+						frac_digits++;
+					} else {
+						return false;
+					}
+					break;
+			}
+		}
+		if (frac_digits == 0)
+			return false;
+		while (frac_digits++ < resolution_digits)
+			fractional *= 10;
+		*this = negative ? -time { integral, fractional} : time { integral, fractional };
+		return true;
+	}
+};
+
+// Out-of-line definition required until C++17.
+constexpr value<time::bits> time::resolution;
+
+std::ostream &operator<<(std::ostream &os, const time &val) {
+	os << (std::string)val;
+	return os;
+}
+
+// These literals are (confusingly) compatible with the ones from `std::chrono`: the `std::chrono` literals do not
+// have an underscore (e.g. 1ms) and the `cxxrtl::time` literals do (e.g. 1_ms). This syntactic difference is
+// a requirement of the C++ standard. Despite being compatible the literals should not be mixed in the same namespace.
+namespace time_literals {
+
+time operator""_s(unsigned long long seconds) {
+	return time { (int64_t)seconds, 0 };
+}
+
+time operator""_ms(unsigned long long milliseconds) {
+	return time { 0, (int64_t)milliseconds * 1000000000000 };
+}
+
+time operator""_us(unsigned long long microseconds) {
+	return time { 0, (int64_t)microseconds * 1000000000 };
+}
+
+time operator""_ns(unsigned long long nanoseconds) {
+	return time { 0, (int64_t)nanoseconds * 1000000 };
+}
+
+time operator""_ps(unsigned long long picoseconds) {
+	return time { 0, (int64_t)picoseconds * 1000 };
+}
+
+time operator""_fs(unsigned long long femtoseconds) {
+	return time { 0, (int64_t)femtoseconds };
+}
+
+};
+
+};
+
+#endif
diff --git a/yosys/backends/cxxrtl/cxxrtl_vcd.h b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
similarity index 99%
rename from yosys/backends/cxxrtl/cxxrtl_vcd.h
rename to yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
index b76922bbd8a..cb2ccf5fc26 100644
--- a/yosys/backends/cxxrtl/cxxrtl_vcd.h
+++ b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
@@ -19,7 +19,7 @@
 #ifndef CXXRTL_VCD_H
 #define CXXRTL_VCD_H
 
-#include <backends/cxxrtl/cxxrtl.h>
+#include <cxxrtl/cxxrtl.h>
 
 namespace cxxrtl {
 
diff --git a/yosys/backends/edif/edif.cc b/yosys/backends/edif/edif.cc
index 00fd7f54e39..553eb23d645 100644
--- a/yosys/backends/edif/edif.cc
+++ b/yosys/backends/edif/edif.cc
@@ -213,6 +213,9 @@ struct EdifBackend : public Backend {
 
 			for (auto cell : module->cells())
 			{
+				if (cell->type == ID($scopeinfo))
+					continue;
+
 				if (design->module(cell->type) == nullptr || design->module(cell->type)->get_blackbox_attribute()) {
 					lib_cell_ports[cell->type];
 					for (auto p : cell->connections())
diff --git a/yosys/backends/firrtl/firrtl.cc b/yosys/backends/firrtl/firrtl.cc
index fc1d628915c..dc76dbeecf5 100644
--- a/yosys/backends/firrtl/firrtl.cc
+++ b/yosys/backends/firrtl/firrtl.cc
@@ -980,6 +980,9 @@ struct FirrtlWorker
 				register_reverse_wire_map(y_id, cell->getPort(ID::Y));
 				continue;
 			}
+
+			if (cell->type == ID($scopeinfo))
+				continue;
 			log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
 		}
 
diff --git a/yosys/backends/firrtl/test.sh b/yosys/backends/firrtl/test.sh
index fe7e3a32912..dd675e91712 100644
--- a/yosys/backends/firrtl/test.sh
+++ b/yosys/backends/firrtl/test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -ex
 
 cd ../../
diff --git a/yosys/backends/jny/jny.cc b/yosys/backends/jny/jny.cc
index 9989feed599..1c163dba52e 100644
--- a/yosys/backends/jny/jny.cc
+++ b/yosys/backends/jny/jny.cc
@@ -124,7 +124,7 @@ struct JnyWriter
         design->sort();
 
         f << "{\n";
-        f << "  \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/master/misc/jny.schema.json\",\n";
+        f << "  \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\",\n";
         f << stringf("  \"generator\": \"%s\",\n", escape_string(yosys_version_str).c_str());
         f << "  \"version\": \"0.0.1\",\n";
         f << "  \"invocation\": \"" << escape_string(invk) << "\",\n";
@@ -426,7 +426,7 @@ struct JnyBackend : public Backend {
         log("        Don't include property information in the netlist output.\n");
         log("\n");
         log("The JSON schema for JNY output files is located in the \"jny.schema.json\" file\n");
-        log("which is located at \"https://raw.githubusercontent.com/YosysHQ/yosys/master/misc/jny.schema.json\"\n");
+        log("which is located at \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\"\n");
         log("\n");
     }
 
diff --git a/yosys/backends/json/json.cc b/yosys/backends/json/json.cc
index fd2c922fd5d..2f442c494f7 100644
--- a/yosys/backends/json/json.cc
+++ b/yosys/backends/json/json.cc
@@ -192,6 +192,10 @@ struct JsonWriter
 		for (auto c : module->cells()) {
 			if (use_selection && !module->selected(c))
 				continue;
+			// Eventually we will want to emit $scopeinfo, but currently this
+			// will break JSON netlist consumers like nextpnr
+			if (c->type == ID($scopeinfo))
+				continue;
 			f << stringf("%s\n", first ? "" : ",");
 			f << stringf("        %s: {\n", get_name(c->name).c_str());
 			f << stringf("          \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0");
diff --git a/yosys/backends/simplec/test00.sh b/yosys/backends/simplec/test00.sh
index ede75727378..9895a97e46b 100644
--- a/yosys/backends/simplec/test00.sh
+++ b/yosys/backends/simplec/test00.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -ex
 ../../yosys -p 'synth -top test; write_simplec -verbose -i8 test00_uut.c' test00_uut.v
 clang -o test00_tb test00_tb.c
diff --git a/yosys/backends/smt2/smt2.cc b/yosys/backends/smt2/smt2.cc
index 5e63e62370d..c702d5e7e54 100644
--- a/yosys/backends/smt2/smt2.cc
+++ b/yosys/backends/smt2/smt2.cc
@@ -1117,7 +1117,18 @@ struct Smt2Worker
 
 				string name_a = get_bool(cell->getPort(ID::A));
 				string name_en = get_bool(cell->getPort(ID::EN));
-				if (cell->name[0] == '$' && cell->attributes.count(ID::src))
+				bool private_name = cell->name[0] == '$';
+
+				if (!private_name && cell->has_attribute(ID::hdlname)) {
+					for (auto const &part : cell->get_hdlname_attribute()) {
+						if (part == "_witness_") {
+							private_name = true;
+							break;
+						}
+					}
+				}
+
+				if (private_name && cell->attributes.count(ID::src))
 					decls.push_back(stringf("; yosys-smt2-%s %d %s %s\n", cell->type.c_str() + 1, id, get_id(cell), cell->attributes.at(ID::src).decode_string().c_str()));
 				else
 					decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, get_id(cell)));
diff --git a/yosys/backends/smt2/smtbmc.py b/yosys/backends/smt2/smtbmc.py
index 02e15a1b502..c3bdcebbe96 100644
--- a/yosys/backends/smt2/smtbmc.py
+++ b/yosys/backends/smt2/smtbmc.py
@@ -17,7 +17,7 @@
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 #
 
-import os, sys, getopt, re, bisect
+import os, sys, getopt, re, bisect, json
 ##yosys-sys-path##
 from smtio import SmtIo, SmtOpts, MkVcd
 from ywio import ReadWitness, WriteWitness, WitnessValues
@@ -56,6 +56,9 @@
 keep_going = False
 check_witness = False
 detect_loops = False
+incremental = None
+track_assumes = False
+minimize_assumes = False
 so = SmtOpts()
 
 
@@ -185,6 +188,17 @@ def help():
         check if states are unique in temporal induction counter examples
         (this feature is experimental and incomplete)
 
+    --incremental
+        run in incremental mode (experimental)
+
+    --track-assumes
+        track individual assumptions and report a subset of used
+        assumptions that are sufficient for the reported outcome. This
+        can be used to debug PREUNSAT failures as well as to find a
+        smaller set of sufficient assumptions.
+
+    --minimize-assumes
+        when using --track-assumes, solve for a minimal set of sufficient assumptions.
 """ + so.helpmsg())
 
 def usage():
@@ -196,7 +210,8 @@ def usage():
     opts, args = getopt.getopt(sys.argv[1:], so.shortopts + "t:higcm:", so.longopts +
             ["help", "final-only", "assume-skipped=", "smtc=", "cex=", "aig=", "aig-noheader", "yw=", "btorwit=", "presat",
              "dump-vcd=", "dump-yw=", "dump-vlogtb=", "vlogtb-top=", "dump-smtc=", "dump-all", "noinfo", "append=",
-             "smtc-init", "smtc-top=", "noinit", "binary", "keep-going", "check-witness", "detect-loops"])
+             "smtc-init", "smtc-top=", "noinit", "binary", "keep-going", "check-witness", "detect-loops", "incremental",
+             "track-assumes", "minimize-assumes"])
 except:
     usage()
 
@@ -282,6 +297,13 @@ def usage():
         check_witness = True
     elif o == "--detect-loops":
         detect_loops = True
+    elif o == "--incremental":
+        from smtbmc_incremental import Incremental
+        incremental = Incremental()
+    elif o == "--track-assumes":
+        track_assumes = True
+    elif o == "--minimize-assumes":
+        minimize_assumes = True
     elif so.handle(o, a):
         pass
     else:
@@ -290,7 +312,7 @@ def usage():
 if len(args) != 1:
     usage()
 
-if sum([tempind, gentrace, covermode]) > 1:
+if sum([tempind, gentrace, covermode, incremental is not None]) > 1:
     usage()
 
 constr_final_start = None
@@ -440,12 +462,17 @@ def replace_netref(match):
 
 smt = SmtIo(opts=so)
 
+if track_assumes:
+    smt.smt2_options[':produce-unsat-assumptions'] = 'true'
+
 if noinfo and vcdfile is None and vlogtbfile is None and outconstr is None:
     smt.produce_models = False
 
 def print_msg(msg):
-    print("%s %s" % (smt.timestamp(), msg))
-    sys.stdout.flush()
+    if incremental:
+        incremental.print_msg(msg)
+    else:
+        print("%s %s" % (smt.timestamp(), msg), flush=True)
 
 print_msg("Solver: %s" % (so.solver))
 
@@ -640,15 +667,14 @@ def print_msg(msg):
                 num_steps = max(num_steps, step+2)
             step += 1
 
-if inywfile is not None:
-    if not got_topt:
-        skip_steps = 0
-        num_steps = 0
+ywfile_hierwitness_cache = None
 
-    with open(inywfile, "r") as f:
-        inyw = ReadWitness(f)
+def ywfile_hierwitness():
+    global ywfile_hierwitness_cache
+    if ywfile_hierwitness_cache is None:
+        ywfile_hierwitness = smt.hierwitness(topmod, allregs=True, blackbox=True)
 
-        inits, seqs, clocks, mems = smt.hierwitness(topmod, allregs=True, blackbox=True)
+        inits, seqs, clocks, mems = ywfile_hierwitness
 
         smt_wires = defaultdict(list)
         smt_mems = defaultdict(list)
@@ -659,90 +685,165 @@ def print_msg(msg):
         for mem in mems:
             smt_mems[mem["path"]].append(mem)
 
-        addr_re = re.compile(r'\\\[[0-9]+\]$')
-        bits_re = re.compile(r'[01?]*$')
+        ywfile_hierwitness_cache = inits, seqs, clocks, mems, smt_wires, smt_mems
 
-        for t, step in inyw.steps():
-            present_signals, missing = step.present_signals(inyw.sigmap)
-            for sig in present_signals:
-                bits = step[sig]
-                if not bits_re.match(bits):
-                    raise ValueError("unsupported bit value in Yosys witness file")
+    return ywfile_hierwitness_cache
 
-                sig_end = sig.offset + len(bits)
-                if sig.path in smt_wires:
-                    for wire in smt_wires[sig.path]:
-                        width, offset = wire["width"], wire["offset"]
+def_bits_re = re.compile(r'([01]+)')
 
-                        smt_bool = smt.net_width(topmod, wire["smtpath"]) == 1
+def smt_extract_mask(smt_expr, mask):
+    chunks = []
+    def_bits = ''
 
-                        offset = max(offset, 0)
+    mask_index_order = mask[::-1]
 
-                        end = width + offset
-                        common_offset = max(sig.offset, offset)
-                        common_end = min(sig_end, end)
-                        if common_end <= common_offset:
-                            continue
+    for matched in def_bits_re.finditer(mask_index_order):
+        chunks.append(matched.span())
+        def_bits += matched[0]
 
-                        smt_expr = smt.witness_net_expr(topmod, f"s{t}", wire)
+    if not chunks:
+        return
 
-                        if not smt_bool:
-                            slice_high = common_end - offset - 1
-                            slice_low = common_offset - offset
-                            smt_expr = "((_ extract %d %d) %s)" % (slice_high, slice_low, smt_expr)
+    if len(chunks) == 1:
+        start, end = chunks[0]
+        if start == 0 and end == len(mask_index_order):
+            combined_chunks = smt_expr
+        else:
+            combined_chunks = '((_ extract %d %d) %s)' % (end - 1, start, smt_expr)
+    else:
+        combined_chunks = '(let ((x %s)) (concat %s))' % (smt_expr, ' '.join(
+            '((_ extract %d %d) x)' % (end - 1, start)
+            for start, end in reversed(chunks)
+        ))
 
-                        bit_slice = bits[len(bits) - (common_end - sig.offset):len(bits) - (common_offset - sig.offset)]
+    return combined_chunks, ''.join(mask_index_order[start:end] for start, end in chunks)[::-1]
 
-                        if bit_slice.count("?") == len(bit_slice):
-                            continue
+def smt_concat(exprs):
+    if not isinstance(exprs, (tuple, list)):
+        exprs = tuple(exprs)
+    if not exprs:
+        return ""
+    if len(exprs) == 1:
+        return exprs[1]
+    return "(concat %s)" % ' '.join(exprs)
 
-                        if smt_bool:
-                            assert width == 1
-                            smt_constr = "(= %s %s)" % (smt_expr, "true" if bit_slice == "1" else "false")
-                        else:
-                            if "?" in bit_slice:
-                                mask = bit_slice.replace("0", "1").replace("?", "0")
-                                bit_slice = bit_slice.replace("?", "0")
-                                smt_expr = "(bvand %s #b%s)" % (smt_expr, mask)
+def ywfile_signal(sig, step, mask=None):
+    assert sig.width > 0
 
-                            smt_constr = "(= %s #b%s)" % (smt_expr, bit_slice)
+    inits, seqs, clocks, mems, smt_wires, smt_mems = ywfile_hierwitness()
+    sig_end = sig.offset + sig.width
 
-                        constr_assumes[t].append((inywfile, smt_constr))
+    output = []
 
-                if sig.memory_path:
-                    if sig.memory_path in smt_mems:
-                        for mem in smt_mems[sig.memory_path]:
-                            width, size, bv = mem["width"], mem["size"], mem["statebv"]
+    if sig.path in smt_wires:
+        for wire in smt_wires[sig.path]:
+            width, offset = wire["width"], wire["offset"]
 
-                            smt_expr = smt.net_expr(topmod, f"s{t}", mem["smtpath"])
+            smt_bool = smt.net_width(topmod, wire["smtpath"]) == 1
 
-                            if bv:
-                                word_low = sig.memory_addr * width
-                                word_high = word_low + width - 1
-                                smt_expr = "((_ extract %d %d) %s)" % (word_high, word_low, smt_expr)
-                            else:
-                                addr_width = (size - 1).bit_length()
-                                addr_bits = f"{sig.memory_addr:0{addr_width}b}"
-                                smt_expr = "(select %s #b%s )" % (smt_expr, addr_bits)
+            offset = max(offset, 0)
 
-                            if len(bits) < width:
-                                slice_high = sig.offset + len(bits) - 1
-                                smt_expr = "((_ extract %d %d) %s)" % (slice_high, sig.offset, smt_expr)
+            end = width + offset
+            common_offset = max(sig.offset, offset)
+            common_end = min(sig_end, end)
+            if common_end <= common_offset:
+                continue
 
-                            bit_slice = bits
+            smt_expr = smt.witness_net_expr(topmod, f"s{step}", wire)
 
-                            if "?" in bit_slice:
-                                mask = bit_slice.replace("0", "1").replace("?", "0")
-                                bit_slice = bit_slice.replace("?", "0")
-                                smt_expr = "(bvand %s #b%s)" % (smt_expr, mask)
+            if not smt_bool:
+                slice_high = common_end - offset - 1
+                slice_low = common_offset - offset
+                smt_expr = "((_ extract %d %d) %s)" % (slice_high, slice_low, smt_expr)
+            else:
+                smt_expr = "(ite %s #b1 #b0)" % smt_expr
 
-                            smt_constr = "(= %s #b%s)" % (smt_expr, bit_slice)
-                            constr_assumes[t].append((inywfile, smt_constr))
+            output.append(((common_offset - sig.offset), (common_end - sig.offset), smt_expr))
 
-            if not got_topt:
-                if not check_witness:
-                    skip_steps = max(skip_steps, t)
-                num_steps = max(num_steps, t+1)
+    if sig.memory_path:
+        if sig.memory_path in smt_mems:
+            for mem in smt_mems[sig.memory_path]:
+                width, size, bv = mem["width"], mem["size"], mem["statebv"]
+
+                smt_expr = smt.net_expr(topmod, f"s{step}", mem["smtpath"])
+
+                if bv:
+                    word_low = sig.memory_addr * width
+                    word_high = word_low + width - 1
+                    smt_expr = "((_ extract %d %d) %s)" % (word_high, word_low, smt_expr)
+                else:
+                    addr_width = (size - 1).bit_length()
+                    addr_bits = f"{sig.memory_addr:0{addr_width}b}"
+                    smt_expr = "(select %s #b%s )" % (smt_expr, addr_bits)
+
+                if sig.width < width:
+                    slice_high = sig.offset + sig.width - 1
+                    smt_expr = "((_ extract %d %d) %s)" % (slice_high, sig.offset, smt_expr)
+
+                output.append((0, sig.width, smt_expr))
+
+    output.sort()
+
+    output = [chunk for chunk in output if chunk[0] != chunk[1]]
+
+    pos = 0
+
+    for start, end, smt_expr in output:
+        assert start == pos
+        pos = end
+
+    assert pos == sig.width
+
+    if len(output) == 1:
+        return output[0][-1]
+    return smt_concat(smt_expr for start, end, smt_expr in reversed(output))
+
+def ywfile_constraints(inywfile, constr_assumes, map_steps=None, skip_x=False):
+    global ywfile_hierwitness_cache
+    if map_steps is None:
+        map_steps = {}
+
+    with open(inywfile, "r") as f:
+        inyw = ReadWitness(f)
+
+        inits, seqs, clocks, mems, smt_wires, smt_mems = ywfile_hierwitness()
+
+        bits_re = re.compile(r'[01?]*$')
+        max_t = -1
+
+        for t, step in inyw.steps():
+            present_signals, missing = step.present_signals(inyw.sigmap)
+            for sig in present_signals:
+                bits = step[sig]
+                if skip_x:
+                    bits = bits.replace('x', '?')
+                if not bits_re.match(bits):
+                    raise ValueError("unsupported bit value in Yosys witness file")
+
+                if bits.count('?') == len(bits):
+                    continue
+
+                smt_expr = ywfile_signal(sig, map_steps.get(t, t))
+
+                smt_expr, bits = smt_extract_mask(smt_expr, bits)
+
+                smt_constr = "(= %s #b%s)" % (smt_expr, bits)
+                constr_assumes[t].append((inywfile, smt_constr))
+
+            max_t = t
+        return max_t
+
+if inywfile is not None:
+    if not got_topt:
+        skip_steps = 0
+        num_steps = 0
+
+    max_t = ywfile_constraints(inywfile, constr_assumes)
+
+    if not got_topt:
+        if not check_witness:
+            skip_steps = max(skip_steps, max_t)
+        num_steps = max(num_steps, max_t+1)
 
 if btorwitfile is not None:
     with open(btorwitfile, "r") as f:
@@ -841,7 +942,7 @@ def print_msg(msg):
         skip_steps = step
         num_steps = step+1
 
-def collect_mem_trace_data(steps_start, steps_stop, vcd=None):
+def collect_mem_trace_data(steps, vcd=None):
     mem_trace_data = dict()
 
     for mempath in sorted(smt.hiermems(topmod)):
@@ -849,16 +950,16 @@ def collect_mem_trace_data(steps_start, steps_stop, vcd=None):
 
         expr_id = list()
         expr_list = list()
-        for i in range(steps_start, steps_stop):
+        for seq, i in enumerate(steps):
             for j in range(rports):
-                expr_id.append(('R', i-steps_start, j, 'A'))
-                expr_id.append(('R', i-steps_start, j, 'D'))
+                expr_id.append(('R', seq, j, 'A'))
+                expr_id.append(('R', seq, j, 'D'))
                 expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dA" % j))
                 expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dD" % j))
             for j in range(wports):
-                expr_id.append(('W', i-steps_start, j, 'A'))
-                expr_id.append(('W', i-steps_start, j, 'D'))
-                expr_id.append(('W', i-steps_start, j, 'M'))
+                expr_id.append(('W', seq, j, 'A'))
+                expr_id.append(('W', seq, j, 'D'))
+                expr_id.append(('W', seq, j, 'M'))
                 expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dA" % j))
                 expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dD" % j))
                 expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dM" % j))
@@ -943,14 +1044,14 @@ def collect_mem_trace_data(steps_start, steps_stop, vcd=None):
                 netpath[-1] += "<%0*x>" % ((len(addr)+3) // 4, int_addr)
                 vcd.add_net([topmod] + netpath, width)
 
-            for i in range(steps_start, steps_stop):
+            for seq, i in enumerate(steps):
                 if i not in mem_trace_data:
                     mem_trace_data[i] = list()
-                mem_trace_data[i].append((netpath, int_addr, "".join(tdata[i-steps_start])))
+                mem_trace_data[i].append((netpath, int_addr, "".join(tdata[seq])))
 
     return mem_trace_data
 
-def write_vcd_trace(steps_start, steps_stop, index):
+def write_vcd_trace(steps, index, seq_time=False):
     filename = vcdfile.replace("%", index)
     print_msg("Writing trace to VCD file: %s" % (filename))
 
@@ -971,10 +1072,10 @@ def write_vcd_trace(steps_start, steps_stop, index):
                     vcd.add_clock([topmod] + netpath, edge)
                 path_list.append(netpath)
 
-        mem_trace_data = collect_mem_trace_data(steps_start, steps_stop, vcd)
+        mem_trace_data = collect_mem_trace_data(steps, vcd)
 
-        for i in range(steps_start, steps_stop):
-            vcd.set_time(i)
+        for seq, i in enumerate(steps):
+            vcd.set_time(seq if seq_time else i)
             value_list = smt.get_net_bin_list(topmod, path_list, "s%d" % i)
             for path, value in zip(path_list, value_list):
                 vcd.set_net([topmod] + path, value)
@@ -982,7 +1083,14 @@ def write_vcd_trace(steps_start, steps_stop, index):
                 for path, addr, value in mem_trace_data[i]:
                     vcd.set_net([topmod] + path, value)
 
-        vcd.set_time(steps_stop)
+        if seq_time:
+            end_time = len(steps)
+        elif steps:
+            end_time = steps[-1] + 1
+        else:
+            end_time = 0
+
+        vcd.set_time(end_time)
 
 def detect_state_loop(steps_start, steps_stop):
     print_msg(f"Checking for loops in found induction counter example")
@@ -1027,7 +1135,7 @@ def escape_identifier(identifier):
 
 
 
-def write_vlogtb_trace(steps_start, steps_stop, index):
+def write_vlogtb_trace(steps, index):
     filename = vlogtbfile.replace("%", index)
     print_msg("Writing trace to Verilog testbench: %s" % (filename))
 
@@ -1092,7 +1200,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index):
         print("  initial begin", file=f)
 
         regs = sorted(smt.hiernets(vlogtb_topmod, regs_only=True))
-        regvals = smt.get_net_bin_list(vlogtb_topmod, regs, vlogtb_state.replace("@@step_idx@@", str(steps_start)))
+        regvals = smt.get_net_bin_list(vlogtb_topmod, regs, vlogtb_state.replace("@@step_idx@@", str(steps[0])))
 
         print("`ifndef VERILATOR", file=f)
         print("    #1;", file=f)
@@ -1107,7 +1215,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index):
         anyconsts = sorted(smt.hieranyconsts(vlogtb_topmod))
         for info in anyconsts:
             if info[3] is not None:
-                modstate = smt.net_expr(vlogtb_topmod, vlogtb_state.replace("@@step_idx@@", str(steps_start)), info[0])
+                modstate = smt.net_expr(vlogtb_topmod, vlogtb_state.replace("@@step_idx@@", str(steps[0])), info[0])
                 value = smt.bv2bin(smt.get("(|%s| %s)" % (info[1], modstate)))
                 print("    UUT.%s = %d'b%s;" % (".".join(escape_identifier(info[0] + [info[3]])), len(value), value), file=f);
 
@@ -1117,7 +1225,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index):
 
             addr_expr_list = list()
             data_expr_list = list()
-            for i in range(steps_start, steps_stop):
+            for i in steps:
                 for j in range(rports):
                     addr_expr_list.append(smt.mem_expr(vlogtb_topmod, vlogtb_state.replace("@@step_idx@@", str(i)), mempath, "R%dA" % j))
                     data_expr_list.append(smt.mem_expr(vlogtb_topmod, vlogtb_state.replace("@@step_idx@@", str(i)), mempath, "R%dD" % j))
@@ -1138,7 +1246,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index):
         print("", file=f)
         anyseqs = sorted(smt.hieranyseqs(vlogtb_topmod))
 
-        for i in range(steps_start, steps_stop):
+        for i in steps:
             pi_names = [[name] for name, _ in primary_inputs if name not in clock_inputs]
             pi_values = smt.get_net_bin_list(vlogtb_topmod, pi_names, vlogtb_state.replace("@@step_idx@@", str(i)))
 
@@ -1170,14 +1278,14 @@ def write_vlogtb_trace(steps_start, steps_stop, index):
                 print("  end", file=f)
                 print("  always @(posedge clock) begin", file=f)
 
-        print("    genclock <= cycle < %d;" % (steps_stop-1), file=f)
+        print("    genclock <= cycle < %d;" % (steps[-1]), file=f)
         print("    cycle <= cycle + 1;", file=f)
         print("  end", file=f)
 
         print("endmodule", file=f)
 
 
-def write_constr_trace(steps_start, steps_stop, index):
+def write_constr_trace(steps, index):
     filename = outconstr.replace("%", index)
     print_msg("Writing trace to constraints file: %s" % (filename))
 
@@ -1194,7 +1302,7 @@ def write_constr_trace(steps_start, steps_stop, index):
             constr_prefix = smtctop[1] + "."
 
     if smtcinit:
-        steps_start = steps_stop - 1
+        steps = [steps[-1]]
 
     with open(filename, "w") as f:
         primary_inputs = list()
@@ -1203,13 +1311,13 @@ def write_constr_trace(steps_start, steps_stop, index):
             width = smt.modinfo[constr_topmod].wsize[name]
             primary_inputs.append((name, width))
 
-        if steps_start == 0 or smtcinit:
+        if steps[0] == 0 or smtcinit:
             print("initial", file=f)
         else:
-            print("state %d" % steps_start, file=f)
+            print("state %d" % steps[0], file=f)
 
         regnames = sorted(smt.hiernets(constr_topmod, regs_only=True))
-        regvals = smt.get_net_list(constr_topmod, regnames, constr_state.replace("@@step_idx@@", str(steps_start)))
+        regvals = smt.get_net_list(constr_topmod, regnames, constr_state.replace("@@step_idx@@", str(steps[0])))
 
         for name, val in zip(regnames, regvals):
             print("assume (= [%s%s] %s)" % (constr_prefix, ".".join(name), val), file=f)
@@ -1220,7 +1328,7 @@ def write_constr_trace(steps_start, steps_stop, index):
 
             addr_expr_list = list()
             data_expr_list = list()
-            for i in range(steps_start, steps_stop):
+            for i in steps:
                 for j in range(rports):
                     addr_expr_list.append(smt.mem_expr(constr_topmod, constr_state.replace("@@step_idx@@", str(i)), mempath, "R%dA" % j))
                     data_expr_list.append(smt.mem_expr(constr_topmod, constr_state.replace("@@step_idx@@", str(i)), mempath, "R%dD" % j))
@@ -1236,7 +1344,7 @@ def write_constr_trace(steps_start, steps_stop, index):
             for addr, data in addr_data.items():
                 print("assume (= (select [%s%s] %s) %s)" % (constr_prefix, ".".join(mempath), addr, data), file=f)
 
-        for k in range(steps_start, steps_stop):
+        for k in steps:
             if not smtcinit:
                 print("", file=f)
                 print("state %d" % k, file=f)
@@ -1247,11 +1355,14 @@ def write_constr_trace(steps_start, steps_stop, index):
             for name, val in zip(pi_names, pi_values):
                 print("assume (= [%s%s] %s)" % (constr_prefix, ".".join(name), val), file=f)
 
-def write_yw_trace(steps_start, steps_stop, index, allregs=False):
-    filename = outywfile.replace("%", index)
-    print_msg("Writing trace to Yosys witness file: %s" % (filename))
+def write_yw_trace(steps, index, allregs=False, filename=None):
+    if filename is None:
+        if outywfile is None:
+            return
+        filename = outywfile.replace("%", index)
+        print_msg("Writing trace to Yosys witness file: %s" % (filename))
 
-    mem_trace_data = collect_mem_trace_data(steps_start, steps_stop)
+    mem_trace_data = collect_mem_trace_data(steps)
 
     with open(filename, "w") as f:
         inits, seqs, clocks, mems = smt.hierwitness(topmod, allregs)
@@ -1295,18 +1406,28 @@ def write_yw_trace(steps_start, steps_stop, index, allregs=False):
                 sig = yw.add_sig(word_path, overlap_start, overlap_end - overlap_start, True)
                 mem_init_values.append((sig, overlap_bits.replace("x", "?")))
 
-        for k in range(steps_start, steps_stop):
+        exprs = []
+        all_sigs = []
+
+        for i, k in enumerate(steps):
             step_values = WitnessValues()
 
-            if k == steps_start:
+            if not i:
                 for sig, value in mem_init_values:
                     step_values[sig] = value
                 sigs = inits + seqs
             else:
                 sigs = seqs
 
+            exprs.extend(smt.witness_net_expr(topmod, f"s{k}", sig) for sig in sigs)
+
+            all_sigs.append((step_values, sigs))
+
+        bvs = iter(smt.get_list(exprs))
+
+        for (step_values, sigs) in all_sigs:
             for sig in sigs:
-                value = smt.bv2bin(smt.get(smt.witness_net_expr(topmod, f"s{k}", sig)))
+                value = smt.bv2bin(next(bvs))
                 step_values[sig["sig"]] = value
             yw.step(step_values)
 
@@ -1314,17 +1435,24 @@ def write_yw_trace(steps_start, steps_stop, index, allregs=False):
 
 
 def write_trace(steps_start, steps_stop, index, allregs=False):
+    if steps_stop is None:
+        steps = steps_start
+        seq_time = True
+    else:
+        steps = list(range(steps_start, steps_stop))
+        seq_time = False
+
     if vcdfile is not None:
-        write_vcd_trace(steps_start, steps_stop, index)
+        write_vcd_trace(steps, index, seq_time=seq_time)
 
     if vlogtbfile is not None:
-        write_vlogtb_trace(steps_start, steps_stop, index)
+        write_vlogtb_trace(steps, index)
 
     if outconstr is not None:
-        write_constr_trace(steps_start, steps_stop, index)
+        write_constr_trace(steps, index)
 
     if outywfile is not None:
-        write_yw_trace(steps_start, steps_stop, index, allregs)
+        write_yw_trace(steps, index, allregs)
 
 
 def print_failed_asserts_worker(mod, state, path, extrainfo, infomap, infokey=()):
@@ -1442,6 +1570,44 @@ def get_active_assert_map(step, active):
 
     return assert_map
 
+assume_enables = {}
+
+def declare_assume_enables():
+    def recurse(mod, path, key_base=()):
+        for expr, desc in smt.modinfo[mod].assumes.items():
+            enable = f"|assume_enable {len(assume_enables)}|"
+            smt.smt2_assumptions[(expr, key_base)] = enable
+            smt.write(f"(declare-const {enable} Bool)")
+            assume_enables[(expr, key_base)] = (enable, path, desc)
+
+        for cell, submod in smt.modinfo[mod].cells.items():
+            recurse(submod, f"{path}.{cell}", (mod, cell, key_base))
+
+    recurse(topmod, topmod)
+
+if track_assumes:
+    declare_assume_enables()
+
+def smt_assert_design_assumes(step):
+    if not track_assumes:
+        smt_assert_consequent("(|%s_u| s%d)" % (topmod, step))
+        return
+
+    if not assume_enables:
+        return
+
+    def expr_for_assume(assume_key, base=None):
+        expr, key_base = assume_key
+        expr_prefix = f"(|{expr}| "
+        expr_suffix = ")"
+        while key_base:
+            mod, cell, key_base = key_base
+            expr_prefix += f"(|{mod}_h {cell}| "
+            expr_suffix += ")"
+        return f"{expr_prefix} s{step}{expr_suffix}"
+
+    for assume_key, (enable, path, desc) in assume_enables.items():
+        smt_assert_consequent(f"(=> {enable} {expr_for_assume(assume_key)})")
 
 states = list()
 asserts_antecedent_cache = [list()]
@@ -1596,7 +1762,18 @@ def smt_check_sat(expected=["sat", "unsat"]):
         smt_forall_assert()
     return smt.check_sat(expected=expected)
 
-if tempind:
+def report_tracked_assumptions(msg):
+    if track_assumes:
+        print_msg(msg)
+        for key in smt.get_unsat_assumptions(minimize=minimize_assumes):
+            enable, path, descr = assume_enables[key]
+            print_msg(f"  In {path}: {descr}")
+
+
+if incremental:
+    incremental.mainloop()
+
+elif tempind:
     retstatus = "FAILED"
     skip_counter = step_size
     for step in range(num_steps, -1, -1):
@@ -1605,7 +1782,7 @@ def smt_check_sat(expected=["sat", "unsat"]):
             break
 
         smt_state(step)
-        smt_assert_consequent("(|%s_u| s%d)" % (topmod, step))
+        smt_assert_design_assumes(step)
         smt_assert_antecedent("(|%s_h| s%d)" % (topmod, step))
         smt_assert_antecedent("(not (|%s_is| s%d))" % (topmod, step))
         smt_assert_consequent(get_constr_expr(constr_assumes, step))
@@ -1648,6 +1825,7 @@ def smt_check_sat(expected=["sat", "unsat"]):
 
         else:
             print_msg("Temporal induction successful.")
+            report_tracked_assumptions("Used assumptions:")
             retstatus = "PASSED"
             break
 
@@ -1673,7 +1851,7 @@ def smt_check_sat(expected=["sat", "unsat"]):
 
     while step < num_steps:
         smt_state(step)
-        smt_assert_consequent("(|%s_u| s%d)" % (topmod, step))
+        smt_assert_design_assumes(step)
         smt_assert_antecedent("(|%s_h| s%d)" % (topmod, step))
         smt_assert_consequent(get_constr_expr(constr_assumes, step))
 
@@ -1694,6 +1872,7 @@ def smt_check_sat(expected=["sat", "unsat"]):
             smt_assert("(distinct (covers_%d s%d) #b%s)" % (coveridx, step, "0" * len(cover_desc)))
 
             if smt_check_sat() == "unsat":
+                report_tracked_assumptions("Used assumptions:")
                 smt_pop()
                 break
 
@@ -1702,13 +1881,14 @@ def smt_check_sat(expected=["sat", "unsat"]):
                     print_msg("Appending additional step %d." % i)
                     smt_state(i)
                     smt_assert_antecedent("(not (|%s_is| s%d))" % (topmod, i))
-                    smt_assert_consequent("(|%s_u| s%d)" % (topmod, i))
+                    smt_assert_design_assumes(i)
                     smt_assert_antecedent("(|%s_h| s%d)" % (topmod, i))
                     smt_assert_antecedent("(|%s_t| s%d s%d)" % (topmod, i-1, i))
                     smt_assert_consequent(get_constr_expr(constr_assumes, i))
                 print_msg("Re-solving with appended steps..")
                 if smt_check_sat() == "unsat":
                     print("%s Cannot appended steps without violating assumptions!" % smt.timestamp())
+                    report_tracked_assumptions("Conflicting assumptions:")
                     found_failed_assert = True
                     retstatus = "FAILED"
                     break
@@ -1764,7 +1944,7 @@ def smt_check_sat(expected=["sat", "unsat"]):
     retstatus = "PASSED"
     while step < num_steps:
         smt_state(step)
-        smt_assert_consequent("(|%s_u| s%d)" % (topmod, step))
+        smt_assert_design_assumes(step)
         smt_assert_antecedent("(|%s_h| s%d)" % (topmod, step))
         smt_assert_consequent(get_constr_expr(constr_assumes, step))
 
@@ -1794,7 +1974,7 @@ def smt_check_sat(expected=["sat", "unsat"]):
             if step+i < num_steps:
                 smt_state(step+i)
                 smt_assert_antecedent("(not (|%s_is| s%d))" % (topmod, step+i))
-                smt_assert_consequent("(|%s_u| s%d)" % (topmod, step+i))
+                smt_assert_design_assumes(step + i)
                 smt_assert_antecedent("(|%s_h| s%d)" % (topmod, step+i))
                 smt_assert_antecedent("(|%s_t| s%d s%d)" % (topmod, step+i-1, step+i))
                 smt_assert_consequent(get_constr_expr(constr_assumes, step+i))
@@ -1808,7 +1988,8 @@ def smt_check_sat(expected=["sat", "unsat"]):
                     print_msg("Checking assumptions in steps %d to %d.." % (step, last_check_step))
 
                 if smt_check_sat() == "unsat":
-                    print("%s Assumptions are unsatisfiable!" % smt.timestamp())
+                    print_msg("Assumptions are unsatisfiable!")
+                    report_tracked_assumptions("Conficting assumptions:")
                     retstatus = "PREUNSAT"
                     break
 
@@ -1861,13 +2042,14 @@ def smt_check_sat(expected=["sat", "unsat"]):
                                 print_msg("Appending additional step %d." % i)
                                 smt_state(i)
                                 smt_assert_antecedent("(not (|%s_is| s%d))" % (topmod, i))
-                                smt_assert_consequent("(|%s_u| s%d)" % (topmod, i))
+                                smt_assert_design_assumes(i)
                                 smt_assert_antecedent("(|%s_h| s%d)" % (topmod, i))
                                 smt_assert_antecedent("(|%s_t| s%d s%d)" % (topmod, i-1, i))
                                 smt_assert_consequent(get_constr_expr(constr_assumes, i))
                             print_msg("Re-solving with appended steps..")
                             if smt_check_sat() == "unsat":
-                                print("%s Cannot append steps without violating assumptions!" % smt.timestamp())
+                                print_msg("Cannot append steps without violating assumptions!")
+                                report_tracked_assumptions("Conflicting assumptions:")
                                 retstatus = "FAILED"
                                 break
                         print_anyconsts(step)
@@ -1954,5 +2136,6 @@ def smt_check_sat(expected=["sat", "unsat"]):
 smt.write("(exit)")
 smt.wait()
 
-print_msg("Status: %s" % retstatus)
-sys.exit(0 if retstatus == "PASSED" else 1)
+if not incremental:
+    print_msg("Status: %s" % retstatus)
+    sys.exit(0 if retstatus == "PASSED" else 1)
diff --git a/yosys/backends/smt2/smtbmc_incremental.py b/yosys/backends/smt2/smtbmc_incremental.py
new file mode 100644
index 00000000000..0bd280b4a48
--- /dev/null
+++ b/yosys/backends/smt2/smtbmc_incremental.py
@@ -0,0 +1,616 @@
+from collections import defaultdict
+import json
+import typing
+import ywio
+
+if typing.TYPE_CHECKING:
+    import smtbmc
+else:
+    import sys
+
+    smtbmc = sys.modules["__main__"]
+
+
+class InteractiveError(Exception):
+    pass
+
+
+def mkkey(data):
+    if isinstance(data, list):
+        return tuple(map(mkkey, data))
+    elif isinstance(data, dict):
+        raise InteractiveError(f"JSON objects found in assumption key: {data!r}")
+    return data
+
+
+class Incremental:
+    def __init__(self):
+        self.traceidx = 0
+
+        self.state_set = set()
+        self.map_cache = {}
+
+        self._cached_hierwitness = {}
+        self._witness_index = None
+
+        self._yw_constraints = {}
+        self._define_sorts = {}
+
+    def setup(self):
+        generic_assert_map = smtbmc.get_assert_map(
+            smtbmc.topmod, "state", smtbmc.topmod
+        )
+        self.inv_generic_assert_map = {
+            tuple(data[1:]): key for key, data in generic_assert_map.items()
+        }
+        assert len(self.inv_generic_assert_map) == len(generic_assert_map)
+
+    def print_json(self, **kwargs):
+        print(json.dumps(kwargs), flush=True)
+
+    def print_msg(self, msg):
+        self.print_json(msg=msg)
+
+    def get_cached_assert(self, step, name):
+        try:
+            assert_map = self.map_cache[step]
+        except KeyError:
+            assert_map = self.map_cache[step] = smtbmc.get_assert_map(
+                smtbmc.topmod, f"s{step}", smtbmc.topmod
+            )
+        return assert_map[self.inv_generic_assert_map[name]][0]
+
+    def arg_step(self, cmd, declare=False, name="step", optional=False):
+        step = cmd.get(name, None)
+        if step is None and optional:
+            return None
+        if not isinstance(step, int):
+            if optional:
+                raise InteractiveError(f"{name} must be an integer")
+            else:
+                raise InteractiveError(f"integer {name} argument required")
+        if declare and step in self.state_set:
+            raise InteractiveError(f"step {step} already declared")
+        if not declare and step not in self.state_set:
+            raise InteractiveError(f"step {step} not declared")
+        return step
+
+    def expr_arg_len(self, expr, min_len, max_len=-1):
+        if max_len == -1:
+            max_len = min_len
+        arg_len = len(expr) - 1
+
+        if min_len is not None and arg_len < min_len:
+            if min_len == max_len:
+                raise InteractiveError(
+                    f"{json.dumps(expr[0])} expression must have "
+                    f"{min_len} argument{'s' if min_len != 1 else ''}"
+                )
+            else:
+                raise InteractiveError(
+                    f"{json.dumps(expr[0])} expression must have at least "
+                    f"{min_len} argument{'s' if min_len != 1 else ''}"
+                )
+        if max_len is not None and arg_len > max_len:
+            raise InteractiveError(
+                f"{json.dumps(expr[0])} expression can have at most "
+                f"{min_len} argument{'s' if max_len != 1 else ''}"
+            )
+
+    def expr_step(self, expr, smt_out):
+        self.expr_arg_len(expr, 1)
+        step = expr[1]
+        if step not in self.state_set:
+            raise InteractiveError(f"step {step} not declared")
+        smt_out.append(f"s{step}")
+        return "module", smtbmc.topmod
+
+    def expr_cell(self, expr, smt_out):
+        self.expr_arg_len(expr, 2)
+        position = len(smt_out)
+        smt_out.append(None)
+        arg_sort = self.expr(expr[2], smt_out, required_sort=["module", None])
+        smt_out.append(")")
+        module = arg_sort[1]
+        cell = expr[1]
+        submod = smtbmc.smt.modinfo[module].cells.get(cell)
+        if submod is None:
+            raise InteractiveError(f"module {module!r} has no cell {cell!r}")
+        smt_out[position] = f"(|{module}_h {cell}| "
+        return ("module", submod)
+
+    def expr_mod_constraint(self, expr, smt_out):
+        suffix = expr[0][3:]
+        self.expr_arg_len(expr, 1, 2 if suffix in ["_a", "_u", "_c"] else 1)
+        position = len(smt_out)
+        smt_out.append(None)
+        arg_sort = self.expr(expr[-1], smt_out, required_sort=["module", None])
+        module = arg_sort[1]
+        if len(expr) == 3:
+            smt_out[position] = f"(|{module}{suffix} {expr[1]}| "
+        else:
+            smt_out[position] = f"(|{module}{suffix}| "
+        smt_out.append(")")
+        return "Bool"
+
+    def expr_mod_constraint2(self, expr, smt_out):
+        self.expr_arg_len(expr, 2)
+
+        position = len(smt_out)
+        smt_out.append(None)
+        arg_sort = self.expr(expr[1], smt_out, required_sort=["module", None])
+        smt_out.append(" ")
+        self.expr(expr[2], smt_out, required_sort=arg_sort)
+        module = arg_sort[1]
+        suffix = expr[0][3:]
+        smt_out[position] = f"(|{module}{suffix}| "
+        smt_out.append(")")
+        return "Bool"
+
+    def expr_not(self, expr, smt_out):
+        self.expr_arg_len(expr, 1)
+
+        smt_out.append("(not ")
+        self.expr(expr[1], smt_out, required_sort="Bool")
+        smt_out.append(")")
+        return "Bool"
+
+    def expr_eq(self, expr, smt_out):
+        self.expr_arg_len(expr, 2)
+
+        smt_out.append("(= ")
+        arg_sort = self.expr(expr[1], smt_out)
+        if (
+            smtbmc.smt.unroll
+            and isinstance(arg_sort, (list, tuple))
+            and arg_sort[0] == "module"
+        ):
+            raise InteractiveError("state equality not supported in unroll mode")
+
+        smt_out.append(" ")
+        self.expr(expr[2], smt_out, required_sort=arg_sort)
+        smt_out.append(")")
+        return "Bool"
+
+    def expr_andor(self, expr, smt_out):
+        if len(expr) == 1:
+            smt_out.push({"and": "true", "or": "false"}[expr[0]])
+        elif len(expr) == 2:
+            self.expr(expr[1], smt_out, required_sort="Bool")
+        else:
+            sep = f"({expr[0]} "
+            for arg in expr[1:]:
+                smt_out.append(sep)
+                sep = " "
+                self.expr(arg, smt_out, required_sort="Bool")
+            smt_out.append(")")
+        return "Bool"
+
+    def expr_bv_binop(self, expr, smt_out):
+        self.expr_arg_len(expr, 2)
+
+        smt_out.append(f"({expr[0]} ")
+        arg_sort = self.expr(expr[1], smt_out, required_sort=("BitVec", None))
+        smt_out.append(" ")
+        self.expr(expr[2], smt_out, required_sort=arg_sort)
+        smt_out.append(")")
+        return arg_sort
+
+    def expr_extract(self, expr, smt_out):
+        self.expr_arg_len(expr, 3)
+
+        hi = expr[1]
+        lo = expr[2]
+
+        smt_out.append(f"((_ extract {hi} {lo}) ")
+
+        arg_sort = self.expr(expr[3], smt_out, required_sort=("BitVec", None))
+        smt_out.append(")")
+
+        if not (isinstance(hi, int) and 0 <= hi < arg_sort[1]):
+            raise InteractiveError(
+                f"high bit index must be 0 <= index < {arg_sort[1]}, is {hi!r}"
+            )
+        if not (isinstance(lo, int) and 0 <= lo <= hi):
+            raise InteractiveError(
+                f"low bit index must be 0 <= index < {hi}, is {lo!r}"
+            )
+
+        return "BitVec", hi - lo + 1
+
+    def expr_bv(self, expr, smt_out):
+        self.expr_arg_len(expr, 1)
+
+        arg = expr[1]
+        if not isinstance(arg, str) or arg.count("0") + arg.count("1") != len(arg):
+            raise InteractiveError("bv argument must contain only 0 or 1 bits")
+
+        smt_out.append("#b" + arg)
+
+        return "BitVec", len(arg)
+
+    def expr_yw(self, expr, smt_out):
+        self.expr_arg_len(expr, 1, 2)
+        if len(expr) == 2:
+            name = None
+            step = expr[1]
+        elif len(expr) == 3:
+            name = expr[1]
+            step = expr[2]
+
+        if step not in self.state_set:
+            raise InteractiveError(f"step {step} not declared")
+
+        if name not in self._yw_constraints:
+            raise InteractiveError(f"no yw file loaded as name {name!r}")
+
+        constraints = self._yw_constraints[name].get(step, [])
+
+        if len(constraints) == 0:
+            smt_out.append("true")
+        elif len(constraints) == 1:
+            smt_out.append(constraints[0])
+        else:
+            sep = "(and "
+            for constraint in constraints:
+                smt_out.append(sep)
+                sep = " "
+                smt_out.append(constraint)
+            smt_out.append(")")
+
+        return "Bool"
+
+    def expr_yw_sig(self, expr, smt_out):
+        self.expr_arg_len(expr, 3, 4)
+
+        step = expr[1]
+        path = expr[2]
+        offset = expr[3]
+        width = expr[4] if len(expr) == 5 else 1
+
+        if not isinstance(offset, int) or offset < 0:
+            raise InteractiveError(
+                f"offset must be a non-negative integer, got {json.dumps(offset)}"
+            )
+
+        if not isinstance(width, int) or width <= 0:
+            raise InteractiveError(
+                f"width must be a positive integer, got {json.dumps(width)}"
+            )
+
+        if not isinstance(path, list) or not all(isinstance(s, str) for s in path):
+            raise InteractiveError(
+                f"path must be a string list, got {json.dumps(path)}"
+            )
+
+        if step not in self.state_set:
+            raise InteractiveError(f"step {step} not declared")
+
+        smt_expr = smtbmc.ywfile_signal(
+            ywio.WitnessSig(path=path, offset=offset, width=width), step
+        )
+
+        smt_out.append(smt_expr)
+
+        return "BitVec", width
+
+    def expr_smtlib(self, expr, smt_out):
+        self.expr_arg_len(expr, 2)
+
+        smtlib_expr = expr[1]
+        sort = expr[2]
+
+        if not isinstance(smtlib_expr, str):
+            raise InteractiveError(
+                "raw SMT-LIB expression has to be a string, "
+                f"got {json.dumps(smtlib_expr)}"
+            )
+
+        if (
+            isinstance(sort, list)
+            and len(sort) == 2
+            and sort[0] == "BitVec"
+            and (sort[1] is None or isinstance(sort[1], int))
+        ):
+            sort = tuple(sort)
+        elif not isinstance(sort, str):
+            raise InteractiveError(f"unsupported raw SMT-LIB sort {json.dumps(sort)}")
+
+        smt_out.append(smtlib_expr)
+        return sort
+
+    def expr_label(self, expr, smt_out):
+        if len(expr) != 3:
+            raise InteractiveError(
+                f'expected ["!", label, sub_expr], got {json.dumps(expr)}'
+            )
+        label = expr[1]
+        subexpr = expr[2]
+
+        if not isinstance(label, str):
+            raise InteractiveError("expression label has to be a string")
+
+        smt_out.append("(! ")
+        sort = self.expr(subexpr, smt_out)
+        smt_out.append(" :named ")
+        smt_out.append(label)
+        smt_out.append(")")
+
+        return sort
+
+    def expr_def(self, expr, smt_out):
+        self.expr_arg_len(expr, 1)
+        sort = self._define_sorts.get(expr[1])
+        if sort is None:
+            raise InteractiveError(f"unknown definition {json.dumps(expr)}")
+        smt_out.append(expr[1])
+        return sort
+
+    expr_handlers = {
+        "step": expr_step,
+        "cell": expr_cell,
+        "mod_h": expr_mod_constraint,
+        "mod_is": expr_mod_constraint,
+        "mod_i": expr_mod_constraint,
+        "mod_a": expr_mod_constraint,
+        "mod_u": expr_mod_constraint,
+        "mod_t": expr_mod_constraint2,
+        "not": expr_not,
+        "and": expr_andor,
+        "or": expr_andor,
+        "bv": expr_bv,
+        "bvand": expr_bv_binop,
+        "bvor": expr_bv_binop,
+        "bvxor": expr_bv_binop,
+        "extract": expr_extract,
+        "def": expr_def,
+        "=": expr_eq,
+        "yw": expr_yw,
+        "yw_sig": expr_yw_sig,
+        "smtlib": expr_smtlib,
+        "!": expr_label,
+    }
+
+    def expr(self, expr, smt_out, required_sort=None):
+        if not isinstance(expr, (list, tuple)) or not expr:
+            raise InteractiveError(
+                f"expression must be a non-empty JSON array, found: {json.dumps(expr)}"
+            )
+        name = expr[0]
+
+        handler = self.expr_handlers.get(name)
+        if handler:
+            sort = handler(self, expr, smt_out)
+
+            if required_sort is not None:
+                if isinstance(required_sort, (list, tuple)):
+                    if (
+                        not isinstance(sort, (list, tuple))
+                        or len(sort) != len(required_sort)
+                        or any(
+                            r is not None and r != s
+                            for r, s in zip(required_sort, sort)
+                        )
+                    ):
+                        raise InteractiveError(
+                            f"required sort {json.dumps(required_sort)} "
+                            f"found sort {json.dumps(sort)}"
+                        )
+            return sort
+        raise InteractiveError(f"unknown expression {json.dumps(expr[0])}")
+
+    def expr_smt(self, expr, required_sort):
+        return self.expr_smt_and_sort(expr, required_sort)[0]
+
+    def expr_smt_and_sort(self, expr, required_sort=None):
+        smt_out = []
+        output_sort = self.expr(expr, smt_out, required_sort=required_sort)
+        out = "".join(smt_out)
+        return out, output_sort
+
+    def cmd_new_step(self, cmd):
+        step = self.arg_step(cmd, declare=True)
+        self.state_set.add(step)
+        smtbmc.smt_state(step)
+
+    def cmd_assert(self, cmd):
+        name = cmd.get("cmd")
+
+        assert_fn = {
+            "assert_antecedent": smtbmc.smt_assert_antecedent,
+            "assert_consequent": smtbmc.smt_assert_consequent,
+            "assert": smtbmc.smt_assert,
+        }[name]
+
+        assert_fn(self.expr_smt(cmd.get("expr"), "Bool"))
+
+    def cmd_assert_design_assumes(self, cmd):
+        step = self.arg_step(cmd)
+        smtbmc.smt_assert_design_assumes(step)
+
+    def cmd_get_design_assume(self, cmd):
+        key = mkkey(cmd.get("key"))
+        return smtbmc.assume_enables.get(key)
+
+    def cmd_update_assumptions(self, cmd):
+        expr = cmd.get("expr")
+        key = cmd.get("key")
+
+        key = mkkey(key)
+
+        result = smtbmc.smt.smt2_assumptions.pop(key, None)
+        if expr is not None:
+            expr = self.expr_smt(expr, "Bool")
+            smtbmc.smt.smt2_assumptions[key] = expr
+        return result
+
+    def cmd_get_unsat_assumptions(self, cmd):
+        return smtbmc.smt.get_unsat_assumptions(minimize=bool(cmd.get("minimize")))
+
+    def cmd_push(self, cmd):
+        smtbmc.smt_push()
+
+    def cmd_pop(self, cmd):
+        smtbmc.smt_pop()
+
+    def cmd_check(self, cmd):
+        return smtbmc.smt_check_sat()
+
+    def cmd_smtlib(self, cmd):
+        command = cmd.get("command")
+        response = cmd.get("response", False)
+        if not isinstance(command, str):
+            raise InteractiveError(
+                f"raw SMT-LIB command must be a string, found {json.dumps(command)}"
+            )
+        smtbmc.smt.write(command)
+        if response:
+            return smtbmc.smt.read()
+
+    def cmd_define(self, cmd):
+        expr = cmd.get("expr")
+        if expr is None:
+            raise InteractiveError("'define' copmmand requires 'expr' parameter")
+
+        expr, sort = self.expr_smt_and_sort(expr)
+
+        if isinstance(sort, tuple) and sort[0] == "module":
+            raise InteractiveError("'define' does not support module sorts")
+
+        define_name = f"|inc def {len(self._define_sorts)}|"
+
+        self._define_sorts[define_name] = sort
+
+        if isinstance(sort, tuple):
+            sort = f"(_ {' '.join(map(str, sort))})"
+
+        smtbmc.smt.write(f"(define-const {define_name} {sort} {expr})")
+
+        return {"name": define_name}
+
+    def cmd_design_hierwitness(self, cmd=None):
+        allregs = (cmd is None) or bool(cmd.get("allreges", False))
+        if self._cached_hierwitness[allregs] is not None:
+            return self._cached_hierwitness[allregs]
+        inits, seqs, clocks, mems = smtbmc.smt.hierwitness(smtbmc.topmod, allregs)
+        self._cached_hierwitness[allregs] = result = dict(
+            inits=inits, seqs=seqs, clocks=clocks, mems=mems
+        )
+        return result
+
+    def cmd_write_yw_trace(self, cmd):
+        steps = cmd.get("steps")
+        allregs = bool(cmd.get("allregs", False))
+
+        if steps is None:
+            steps = sorted(self.state_set)
+
+        path = cmd.get("path")
+
+        smtbmc.write_yw_trace(steps, self.traceidx, allregs=allregs, filename=path)
+
+        if path is None:
+            self.traceidx += 1
+
+    def cmd_read_yw_trace(self, cmd):
+        steps = cmd.get("steps")
+        path = cmd.get("path")
+        name = cmd.get("name")
+        skip_x = cmd.get("skip_x", False)
+        if path is None:
+            raise InteractiveError("path required")
+
+        constraints = defaultdict(list)
+
+        if steps is None:
+            steps = sorted(self.state_set)
+
+        map_steps = {i: int(j) for i, j in enumerate(steps)}
+
+        last_step = smtbmc.ywfile_constraints(
+            path, constraints, map_steps=map_steps, skip_x=skip_x
+        )
+
+        self._yw_constraints[name] = {
+            map_steps.get(i, i): [smtexpr for cexfile, smtexpr in constraint_list]
+            for i, constraint_list in constraints.items()
+        }
+
+        return dict(last_step=last_step)
+
+    def cmd_modinfo(self, cmd):
+        fields = cmd.get("fields", [])
+
+        mod = cmd.get("mod")
+        if mod is None:
+            mod = smtbmc.topmod
+        modinfo = smtbmc.smt.modinfo.get(mod)
+        if modinfo is None:
+            return None
+
+        result = dict(name=mod)
+        for field in fields:
+            result[field] = getattr(modinfo, field, None)
+        return result
+
+    def cmd_ping(self, cmd):
+        return cmd
+
+    cmd_handlers = {
+        "new_step": cmd_new_step,
+        "assert": cmd_assert,
+        "assert_antecedent": cmd_assert,
+        "assert_consequent": cmd_assert,
+        "assert_design_assumes": cmd_assert_design_assumes,
+        "get_design_assume": cmd_get_design_assume,
+        "update_assumptions": cmd_update_assumptions,
+        "get_unsat_assumptions": cmd_get_unsat_assumptions,
+        "push": cmd_push,
+        "pop": cmd_pop,
+        "check": cmd_check,
+        "smtlib": cmd_smtlib,
+        "define": cmd_define,
+        "design_hierwitness": cmd_design_hierwitness,
+        "write_yw_trace": cmd_write_yw_trace,
+        "read_yw_trace": cmd_read_yw_trace,
+        "modinfo": cmd_modinfo,
+        "ping": cmd_ping,
+    }
+
+    def handle_command(self, cmd):
+        if not isinstance(cmd, dict) or "cmd" not in cmd:
+            raise InteractiveError('object with "cmd" key required')
+
+        name = cmd.get("cmd", None)
+
+        handler = self.cmd_handlers.get(name)
+        if handler:
+            return handler(self, cmd)
+        else:
+            raise InteractiveError(f"unknown command: {name}")
+
+    def mainloop(self):
+        self.setup()
+        while True:
+            try:
+                cmd = input().strip()
+                if not cmd or cmd.startswith("#") or cmd.startswith("//"):
+                    continue
+                try:
+                    cmd = json.loads(cmd)
+                except json.decoder.JSONDecodeError as e:
+                    self.print_json(err=f"invalid JSON: {e}")
+                    continue
+            except EOFError:
+                break
+
+            try:
+                result = self.handle_command(cmd)
+            except InteractiveError as e:
+                self.print_json(err=str(e))
+                continue
+            except Exception as e:
+                self.print_json(err=f"internal error: {e}")
+                raise
+            else:
+                self.print_json(ok=result)
diff --git a/yosys/backends/smt2/smtio.py b/yosys/backends/smt2/smtio.py
index 0ec7f08f4dc..5fc3ab5a424 100644
--- a/yosys/backends/smt2/smtio.py
+++ b/yosys/backends/smt2/smtio.py
@@ -79,6 +79,20 @@ def except_hook(exctype, value, traceback):
 sys.excepthook = except_hook
 
 
+def recursion_helper(iteration, *request):
+    stack = [iteration(*request)]
+
+    while stack:
+        top = stack.pop()
+        try:
+            request = next(top)
+        except StopIteration:
+            continue
+
+        stack.append(top)
+        stack.append(iteration(*request))
+
+
 hex_dict = {
     "0": "0000", "1": "0001", "2": "0010", "3": "0011",
     "4": "0100", "5": "0101", "6": "0110", "7": "0111",
@@ -100,6 +114,7 @@ def __init__(self):
         self.clocks = dict()
         self.cells = dict()
         self.asserts = dict()
+        self.assumes = dict()
         self.covers = dict()
         self.maximize = set()
         self.minimize = set()
@@ -127,6 +142,7 @@ def __init__(self, opts=None):
         self.recheck = False
         self.smt2cache = [list()]
         self.smt2_options = dict()
+        self.smt2_assumptions = dict()
         self.p = None
         self.p_index = solvers_index
         solvers_index += 1
@@ -144,6 +160,7 @@ def __init__(self, opts=None):
             self.noincr = opts.noincr
             self.info_stmts = opts.info_stmts
             self.nocomments = opts.nocomments
+            self.smt2_options.update(opts.smt2_options)
 
         else:
             self.solver = "yices"
@@ -298,10 +315,22 @@ def replace_in_stmt(self, stmt, pat, repl):
         return stmt
 
     def unroll_stmt(self, stmt):
+        result = []
+        recursion_helper(self._unroll_stmt_into, stmt, result)
+        return result.pop()
+
+    def _unroll_stmt_into(self, stmt, output, depth=128):
         if not isinstance(stmt, list):
-            return stmt
+            output.append(stmt)
+            return
 
-        stmt = [self.unroll_stmt(s) for s in stmt]
+        new_stmt = []
+        for s in stmt:
+            if depth:
+                yield from self._unroll_stmt_into(s, new_stmt, depth - 1)
+            else:
+                yield s, new_stmt
+        stmt = new_stmt
 
         if len(stmt) >= 2 and not isinstance(stmt[0], list) and stmt[0] in self.unroll_decls:
             assert stmt[1] in self.unroll_objs
@@ -330,12 +359,19 @@ def unroll_stmt(self, stmt):
                     decl[2] = list()
 
                 if len(decl) > 0:
-                    decl = self.unroll_stmt(decl)
+                    tmp = []
+                    if depth:
+                        yield from self._unroll_stmt_into(decl, tmp, depth - 1)
+                    else:
+                        yield decl, tmp
+
+                    decl = tmp.pop()
                     self.write(self.unparse(decl), unroll=False)
 
-            return self.unroll_cache[key]
+            output.append(self.unroll_cache[key])
+            return
 
-        return stmt
+        output.append(stmt)
 
     def p_thread_main(self):
         while True:
@@ -569,6 +605,12 @@ def info(self, stmt):
             else:
                 self.modinfo[self.curmod].covers["%s_c %s" % (self.curmod, fields[2])] = fields[3]
 
+        if fields[1] == "yosys-smt2-assume":
+            if len(fields) > 4:
+                self.modinfo[self.curmod].assumes["%s_u %s" % (self.curmod, fields[2])] = f'{fields[4]} ({fields[3]})'
+            else:
+                self.modinfo[self.curmod].assumes["%s_u %s" % (self.curmod, fields[2])] = fields[3]
+
         if fields[1] == "yosys-smt2-maximize":
             self.modinfo[self.curmod].maximize.add(fields[2])
 
@@ -752,8 +794,13 @@ def read(self):
         return stmt
 
     def check_sat(self, expected=["sat", "unsat", "unknown", "timeout", "interrupted"]):
+        if self.smt2_assumptions:
+            assume_exprs = " ".join(self.smt2_assumptions.values())
+            check_stmt = f"(check-sat-assuming ({assume_exprs}))"
+        else:
+            check_stmt = "(check-sat)"
         if self.debug_print:
-            print("> (check-sat)")
+            print(f"> {check_stmt}")
         if self.debug_file and not self.nocomments:
             print("; running check-sat..", file=self.debug_file)
             self.debug_file.flush()
@@ -767,7 +814,7 @@ def check_sat(self, expected=["sat", "unsat", "unknown", "timeout", "interrupted
                     for cache_stmt in cache_ctx:
                         self.p_write(cache_stmt + "\n", False)
 
-            self.p_write("(check-sat)\n", True)
+            self.p_write(f"{check_stmt}\n", True)
 
             if self.timeinfo:
                 i = 0
@@ -835,7 +882,7 @@ def check_sat(self, expected=["sat", "unsat", "unknown", "timeout", "interrupted
 
         if self.debug_file:
             print("(set-info :status %s)" % result, file=self.debug_file)
-            print("(check-sat)", file=self.debug_file)
+            print(check_stmt, file=self.debug_file)
             self.debug_file.flush()
 
         if result not in expected:
@@ -912,6 +959,55 @@ def bv2bin(self, v):
     def bv2int(self, v):
         return int(self.bv2bin(v), 2)
 
+    def get_raw_unsat_assumptions(self):
+        if not self.smt2_assumptions:
+            return []
+        self.write("(get-unsat-assumptions)")
+        exprs = set(self.unparse(part) for part in self.parse(self.read()))
+        unsat_assumptions = []
+        for key, value in self.smt2_assumptions.items():
+            # normalize expression
+            value = self.unparse(self.parse(value))
+            if value in exprs:
+                exprs.remove(value)
+                unsat_assumptions.append(key)
+        return unsat_assumptions
+
+    def get_unsat_assumptions(self, minimize=False):
+        if not minimize:
+            return self.get_raw_unsat_assumptions()
+        orig_assumptions = self.smt2_assumptions
+
+        self.smt2_assumptions = dict(orig_assumptions)
+
+        required_assumptions = {}
+
+        while True:
+            candidate_assumptions = {}
+            for key in self.get_raw_unsat_assumptions():
+                if key not in required_assumptions:
+                    candidate_assumptions[key] = self.smt2_assumptions[key]
+
+            while candidate_assumptions:
+
+                candidate_key, candidate_assume = candidate_assumptions.popitem()
+
+                self.smt2_assumptions = {}
+                for key, assume in candidate_assumptions.items():
+                    self.smt2_assumptions[key] = assume
+                for key, assume in required_assumptions.items():
+                    self.smt2_assumptions[key] = assume
+                result = self.check_sat()
+
+                if result == 'unsat':
+                    candidate_assumptions = None
+                else:
+                    required_assumptions[candidate_key] = candidate_assume
+
+            if candidate_assumptions is not None:
+                self.smt2_assumptions = orig_assumptions
+                return list(required_assumptions)
+
     def get(self, expr):
         self.write("(get-value (%s))" % (expr))
         return self.parse(self.read())[0][1]
@@ -920,7 +1016,7 @@ def get_list(self, expr_list):
         if len(expr_list) == 0:
             return []
         self.write("(get-value (%s))" % " ".join(expr_list))
-        return [n[1] for n in self.parse(self.read())]
+        return [n[1] for n in self.parse(self.read()) if n]
 
     def get_path(self, mod, path):
         assert mod in self.modinfo
@@ -1058,7 +1154,7 @@ def wait(self):
 class SmtOpts:
     def __init__(self):
         self.shortopts = "s:S:v"
-        self.longopts = ["unroll", "noincr", "noprogress", "timeout=", "dump-smt2=", "logic=", "dummy=", "info=", "nocomments"]
+        self.longopts = ["unroll", "noincr", "noprogress", "timeout=", "dump-smt2=", "logic=", "dummy=", "info=", "nocomments", "smt2-option="]
         self.solver = "yices"
         self.solver_opts = list()
         self.debug_print = False
@@ -1071,6 +1167,7 @@ def __init__(self):
         self.logic = None
         self.info_stmts = list()
         self.nocomments = False
+        self.smt2_options = {}
 
     def handle(self, o, a):
         if o == "-s":
@@ -1097,6 +1194,13 @@ def handle(self, o, a):
             self.info_stmts.append(a)
         elif o == "--nocomments":
             self.nocomments = True
+        elif o == "--smt2-option":
+            args = a.split('=', 1)
+            if len(args) != 2:
+                print("--smt2-option expects an <option>=<value> argument")
+                sys.exit(1)
+            option, value = args
+            self.smt2_options[option] = value
         else:
             return False
         return True
@@ -1120,6 +1224,9 @@ def helpmsg(self):
         if solver is "dummy", read solver output from that file
         otherwise: write solver output to that file
 
+    --smt2-option <option>=<value>
+        enable an SMT-LIBv2 option.
+
     -v
         enable debug output
 
diff --git a/yosys/backends/smt2/test_cells.sh b/yosys/backends/smt2/test_cells.sh
index 34adb7af3c1..3f84d65a21a 100644
--- a/yosys/backends/smt2/test_cells.sh
+++ b/yosys/backends/smt2/test_cells.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -ex
 
diff --git a/yosys/backends/smt2/witness.py b/yosys/backends/smt2/witness.py
index 7d5a2469eb5..b7e25851cbb 100644
--- a/yosys/backends/smt2/witness.py
+++ b/yosys/backends/smt2/witness.py
@@ -33,10 +33,14 @@ def cli():
 Display a Yosys witness trace in a human readable format.
 """)
 @click.argument("input", type=click.File("r"))
-def display(input):
+@click.option("--skip-x", help="Treat x bits as unassigned.", is_flag=True)
+def display(input, skip_x):
     click.echo(f"Reading Yosys witness trace {input.name!r}...")
     inyw = ReadWitness(input)
 
+    if skip_x:
+        inyw.skip_x()
+
     def output():
 
         yield click.style("*** RTLIL bit-order below may differ from source level declarations ***", fg="red")
@@ -84,26 +88,69 @@ def stats(input):
 Transform a Yosys witness trace.
 
 Currently no transformations are implemented, so it is only useful for testing.
+If two or more inputs are provided they will be concatenated together into the output.
 """)
-@click.argument("input", type=click.File("r"))
+@click.argument("inputs", type=click.File("r"), nargs=-1)
 @click.argument("output", type=click.File("w"))
-def yw2yw(input, output):
-    click.echo(f"Copying yosys witness trace from {input.name!r} to {output.name!r}...")
-    inyw = ReadWitness(input)
+@click.option("--append", "-p", type=int, multiple=True,
+              help="Number of steps (+ve or -ve) to append to end of input trace. "
+                  +"Can be defined multiple times, following the same order as input traces. ")
+@click.option("--skip-x", help="Leave input x bits unassigned.", is_flag=True)
+def yw2yw(inputs, output, append, skip_x):
+    if len(inputs) == 0:
+        raise click.ClickException(f"no inputs specified")
+
     outyw = WriteWitness(output, "yosys-witness yw2yw")
+    join_inputs = len(inputs) > 1
+    inyws = {}
+
+    if not append:
+        # default to 0
+        append = [0] * len(inputs)
+    if len(append) != len(inputs):
+        print(f"Mismatch in number of --append values ({len(append)}) and input traces ({len(inputs)}).")
+        sys.exit(1)
+
+    for (input, p) in zip(inputs, append):
+        if (join_inputs):
+            click.echo(f"Loading signals from yosys witness trace {input.name!r}...")
+        inyw = ReadWitness(input)
+        if p:
+            click.echo(f"  appending {p} steps")
+            if (p + len(inyw) <= 0):
+                click.echo(f"  skipping {input.name!r} (only {len(inyw)} steps to skip)")
+                continue
+            inyw.append_steps(p)
+        inyws[input] = inyw
+        for clock in inyw.clocks:
+            if clock not in outyw.clocks:
+                outyw.add_clock(clock["path"], clock["offset"], clock["edge"])
 
-    for clock in inyw.clocks:
-        outyw.add_clock(clock["path"], clock["offset"], clock["edge"])
+        for sig in inyw.signals:
+            if sig not in outyw.signals:
+                outyw.add_sig(sig.path, sig.offset, sig.width, sig.init_only)
 
-    for sig in inyw.signals:
-        outyw.add_sig(sig.path, sig.offset, sig.width, sig.init_only)
+    init_values = sum([inyw.init_step() for inyw in inyws.values()], start=WitnessValues())
 
-    for t, values in inyw.steps():
-        outyw.step(values)
+    first_witness = True
+    for (input, inyw) in inyws.items():
+        click.echo(f"Copying yosys witness trace from {input.name!r} to {output.name!r}...")
+
+        if first_witness:
+            outyw.step(init_values, skip_x=skip_x)
+        else:
+            outyw.step(inyw.first_step(), skip_x=skip_x)
+
+        for t, values in inyw.steps(1):
+            outyw.step(values, skip_x=skip_x)
+
+        click.echo(f"  copied {t + 1} time steps.")
+        first_witness = False
 
     outyw.end_trace()
 
-    click.echo(f"Copied {outyw.t + 1} time steps.")
+    if join_inputs:
+        click.echo(f"Copied {outyw.t} total time steps.")
 
 
 class AigerMap:
@@ -135,7 +182,9 @@ def __init__(self, mapfile):
 @click.argument("input", type=click.File("r"))
 @click.argument("mapfile", type=click.File("r"))
 @click.argument("output", type=click.File("w"))
-def aiw2yw(input, mapfile, output):
+@click.option("--skip-x", help="Leave input x bits unassigned.", is_flag=True)
+@click.option("--present-only", help="Only include bits present in at least one time step.", is_flag=True)
+def aiw2yw(input, mapfile, output, skip_x, present_only):
     input_name = input.name
     click.echo(f"Converting AIGER witness trace {input_name!r} to Yosys witness trace {output.name!r}...")
     click.echo(f"Using Yosys witness AIGER map file {mapfile.name!r}")
@@ -163,16 +212,23 @@ def aiw2yw(input, mapfile, output):
     if not re.match(r'[0]*$', ffline):
         raise click.ClickException(f"{input_name}: non-default initial state not supported")
 
-    outyw = WriteWitness(output, 'yosys-witness aiw2yw')
+    if not present_only:
+        outyw = WriteWitness(output, "yosys-witness aiw2yw")
 
-    for clock in aiger_map.clocks:
-        outyw.add_clock(clock["path"], clock["offset"], clock["edge"])
+        for clock in aiger_map.clocks:
+            outyw.add_clock(clock["path"], clock["offset"], clock["edge"])
 
-    for (path, offset), id in aiger_map.sigmap.bit_to_id.items():
-        outyw.add_sig(path, offset, init_only=id in aiger_map.init_inputs)
+        for (path, offset), id in aiger_map.sigmap.bit_to_id.items():
+            outyw.add_sig(path, offset, init_only=id in aiger_map.init_inputs)
 
     missing = set()
+    seen = set()
+
+    buffered_steps = []
+
+    skip = "x?" if skip_x else "?"
 
+    t = -1
     while True:
         inline = next(input, None)
         if inline is None:
@@ -184,17 +240,20 @@ def aiw2yw(input, mapfile, output):
         if inline.startswith("#"):
             continue
 
-        if not re.match(r'[01x]*$', ffline):
+        t += 1
+
+        if not re.match(r"[01x]*$", inline):
             raise click.ClickException(f"{input_name}: unexpected data in AIGER witness file")
 
         if len(inline) != aiger_map.input_count:
             raise click.ClickException(
-                    f"{input_name}: {mapfile.name}: number of inputs does not match, "
-                    f"{len(inline)} in witness, {aiger_map.input_count} in map file")
+                f"{input_name}: {mapfile.name}: number of inputs does not match, "
+                f"{len(inline)} in witness, {aiger_map.input_count} in map file"
+            )
 
         values = WitnessValues()
         for i, v in enumerate(inline):
-            if outyw.t > 0 and i in aiger_map.init_inputs:
+            if v in skip or (t > 0 and i in aiger_map.init_inputs):
                 continue
 
             try:
@@ -202,11 +261,29 @@ def aiw2yw(input, mapfile, output):
             except IndexError:
                 bit = None
             if bit is None:
-                missing.insert(i)
+                missing.add(i)
+            elif present_only:
+                seen.add(i)
 
             values[bit] = v
 
-        outyw.step(values)
+        if present_only:
+            buffered_steps.append(values)
+        else:
+            outyw.step(values)
+
+    if present_only:
+        outyw = WriteWitness(output, "yosys-witness aiw2yw")
+
+        for clock in aiger_map.clocks:
+            outyw.add_clock(clock["path"], clock["offset"], clock["edge"])
+
+        for (path, offset), id in aiger_map.sigmap.bit_to_id.items():
+            if id in seen:
+                outyw.add_sig(path, offset, init_only=id in aiger_map.init_inputs)
+
+        for values in buffered_steps:
+            outyw.step(values)
 
     outyw.end_trace()
 
diff --git a/yosys/backends/smt2/ywio.py b/yosys/backends/smt2/ywio.py
index 39cfac41e25..023a2d351b3 100644
--- a/yosys/backends/smt2/ywio.py
+++ b/yosys/backends/smt2/ywio.py
@@ -165,8 +165,8 @@ def pretty(self):
         else:
             return f"{pretty_path(self.path)}[{self.offset}]"
 
-    def __eq__(self):
-        return self.sort_key
+    def __eq__(self, other):
+        return self.sort_key == other.sort_key
 
     def __hash__(self):
         return hash(self.sort_key)
@@ -294,6 +294,16 @@ def present_signals(self, sigmap):
 
         return sorted(signals), missing_signals
 
+    def __add__(self, other: "WitnessValues"):
+        new = WitnessValues()
+        new += self
+        new += other
+        return new
+
+    def __iadd__(self, other: "WitnessValues"):
+        for key, value in other.values.items():
+            self.values.setdefault(key, value)
+        return self
 
 class WriteWitness:
     def __init__(self, f, generator):
@@ -341,11 +351,14 @@ def write_header(self):
         self.out.name("steps")
         self.out.begin_array()
 
-    def step(self, values):
+    def step(self, values, skip_x=False):
         if not self.header_written:
             self.write_header()
 
-        self.out.value({"bits": values.pack(self.sigmap)})
+        packed = values.pack(self.sigmap)
+        if skip_x:
+            packed = packed.replace('x', '?')
+        self.out.value({"bits": packed})
 
         self.t += 1
 
@@ -380,14 +393,40 @@ def __init__(self, f):
 
         self.bits = [step["bits"] for step in data["steps"]]
 
+    def skip_x(self):
+        self.bits = [step.replace('x', '?') for step in self.bits]
+
+    def init_step(self):
+        return self.step(0)
+    
+    def non_init_bits(self):
+        if len(self) > 1:
+            return len(self.bits[1])
+        else:
+            return sum([sig.width for sig in self.signals if not sig.init_only])
+    
+    def first_step(self):
+        values = WitnessValues()
+        # may have issues when non_init_bits is 0
+        values.unpack(WitnessSigMap([sig for sig in self.signals if not sig.init_only]), self.bits[0][-self.non_init_bits():])
+        return values
+
     def step(self, t):
         values = WitnessValues()
         values.unpack(self.sigmap, self.bits[t])
         return values
 
-    def steps(self):
-        for i in range(len(self.bits)):
+    def steps(self, start=0):
+        for i in range(start, len(self.bits)):
             yield i, self.step(i)
 
+    def append_steps(self, t):
+        if not t:
+            pass
+        elif t < 0:
+            self.bits = self.bits[:t]
+        else:
+            self.bits.extend(["0"*self.non_init_bits()]*t)
+
     def __len__(self):
         return len(self.bits)
diff --git a/yosys/backends/smv/smv.cc b/yosys/backends/smv/smv.cc
index 49c2cc7a6c4..44e20038441 100644
--- a/yosys/backends/smv/smv.cc
+++ b/yosys/backends/smv/smv.cc
@@ -573,6 +573,9 @@ struct SmvWorker
 				continue;
 			}
 
+			if (cell->type == ID($scopeinfo))
+				continue;
+
 			if (cell->type[0] == '$') {
 				if (cell->type.in(ID($dffe), ID($sdff), ID($sdffe), ID($sdffce)) || cell->type.str().substr(0, 6) == "$_SDFF" || (cell->type.str().substr(0, 6) == "$_DFFE" && cell->type.str().size() == 10)) {
 					log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_smv`.\n",
diff --git a/yosys/backends/smv/test_cells.sh b/yosys/backends/smv/test_cells.sh
index 145b9c33b92..1347b70446b 100644
--- a/yosys/backends/smv/test_cells.sh
+++ b/yosys/backends/smv/test_cells.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -ex
 
diff --git a/yosys/backends/spice/spice.cc b/yosys/backends/spice/spice.cc
index f260276eb93..1160a01a188 100644
--- a/yosys/backends/spice/spice.cc
+++ b/yosys/backends/spice/spice.cc
@@ -72,6 +72,9 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
 
 	for (auto cell : module->cells())
 	{
+		if (cell->type == ID($scopeinfo))
+			continue;
+
 		f << stringf("X%d", cell_counter++);
 
 		std::vector<RTLIL::SigSpec> port_sigs;
diff --git a/yosys/backends/verilog/verilog_backend.cc b/yosys/backends/verilog/verilog_backend.cc
index 5ff191a9c16..31bbc996ffa 100644
--- a/yosys/backends/verilog/verilog_backend.cc
+++ b/yosys/backends/verilog/verilog_backend.cc
@@ -27,6 +27,7 @@
 #include "kernel/sigtools.h"
 #include "kernel/ff.h"
 #include "kernel/mem.h"
+#include "kernel/fmt.h"
 #include <string>
 #include <sstream>
 #include <set>
@@ -375,7 +376,7 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 	}
 }
 
-void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, char term = '\n', bool modattr = false, bool regattr = false, bool as_comment = false)
+void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, std::string term = "\n", bool modattr = false, bool regattr = false, bool as_comment = false)
 {
 	if (noattr)
 		return;
@@ -391,13 +392,13 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
 			f << stringf(" 1 ");
 		else
 			dump_const(f, it->second, -1, 0, false, as_comment);
-		f << stringf(" %s%c", as_comment ? "*/" : "*)", term);
+		f << stringf(" %s%s", as_comment ? "*/" : "*)", term.c_str());
 	}
 }
 
 void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 {
-	dump_attributes(f, indent, wire->attributes, '\n', /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name));
+	dump_attributes(f, indent, wire->attributes, "\n", /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name));
 #if 0
 	if (wire->port_input && !wire->port_output)
 		f << stringf("%s" "input %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : "");
@@ -988,7 +989,7 @@ void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell
 	f << stringf("%s" "assign ", indent.c_str());
 	dump_sigspec(f, cell->getPort(ID::Y));
 	f << stringf(" = %s ", op.c_str());
-	dump_attributes(f, "", cell->attributes, ' ');
+	dump_attributes(f, "", cell->attributes, " ");
 	dump_cell_expr_port(f, cell, "A", true);
 	f << stringf(";\n");
 }
@@ -1000,11 +1001,63 @@ void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell
 	f << stringf(" = ");
 	dump_cell_expr_port(f, cell, "A", true);
 	f << stringf(" %s ", op.c_str());
-	dump_attributes(f, "", cell->attributes, ' ');
+	dump_attributes(f, "", cell->attributes, " ");
 	dump_cell_expr_port(f, cell, "B", true);
 	f << stringf(";\n");
 }
 
+void dump_cell_expr_print(std::ostream &f, std::string indent, const RTLIL::Cell *cell)
+{
+	Fmt fmt;
+	fmt.parse_rtlil(cell);
+	std::vector<VerilogFmtArg> args = fmt.emit_verilog();
+
+	f << stringf("%s" "$write(", indent.c_str());
+	bool first = true;
+	for (auto &arg : args) {
+		if (first) {
+			first = false;
+		} else {
+			f << ", ";
+		}
+		switch (arg.type) {
+			case VerilogFmtArg::STRING:
+				dump_const(f, RTLIL::Const(arg.str));
+				break;
+			case VerilogFmtArg::INTEGER:
+				f << (arg.signed_ ? "$signed(" : "$unsigned(");
+				dump_sigspec(f, arg.sig);
+				f << ")";
+				break;
+			case VerilogFmtArg::TIME:
+				if (arg.realtime)
+					f << "$realtime";
+				else
+					f << "$time";
+				break;
+			default: log_abort();
+		}
+	}
+	f << stringf(");\n");
+}
+
+void dump_cell_expr_check(std::ostream &f, std::string indent, const RTLIL::Cell *cell)
+{
+	std::string flavor = cell->getParam(ID(FLAVOR)).decode_string();
+	if (flavor == "assert")
+		f << stringf("%s" "assert (", indent.c_str());
+	else if (flavor == "assume")
+		f << stringf("%s" "assume (", indent.c_str());
+	else if (flavor == "live")
+		f << stringf("%s" "assert (eventually ", indent.c_str());
+	else if (flavor == "fair")
+		f << stringf("%s" "assume (eventually ", indent.c_str());
+	else if (flavor == "cover")
+		f << stringf("%s" "cover (", indent.c_str());
+	dump_sigspec(f, cell->getPort(ID::A));
+	f << stringf(");\n");
+}
+
 bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 {
 	if (cell->type == ID($_NOT_)) {
@@ -1012,7 +1065,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		dump_sigspec(f, cell->getPort(ID::Y));
 		f << stringf(" = ");
 		f << stringf("~");
-		dump_attributes(f, "", cell->attributes, ' ');
+		dump_attributes(f, "", cell->attributes, " ");
+		dump_cell_expr_port(f, cell, "A", false);
+		f << stringf(";\n");
+		return true;
+	}
+
+	if (cell->type == ID($_BUF_)) {
+		f << stringf("%s" "assign ", indent.c_str());
+		dump_sigspec(f, cell->getPort(ID::Y));
+		f << stringf(" = ");
 		dump_cell_expr_port(f, cell, "A", false);
 		f << stringf(";\n");
 		return true;
@@ -1032,7 +1094,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			f << stringf("|");
 		if (cell->type.in(ID($_XOR_), ID($_XNOR_)))
 			f << stringf("^");
-		dump_attributes(f, "", cell->attributes, ' ');
+		dump_attributes(f, "", cell->attributes, " ");
 		f << stringf(" ");
 		if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
 			f << stringf("~(");
@@ -1049,7 +1111,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		f << stringf(" = ");
 		dump_cell_expr_port(f, cell, "S", false);
 		f << stringf(" ? ");
-		dump_attributes(f, "", cell->attributes, ' ');
+		dump_attributes(f, "", cell->attributes, " ");
 		dump_cell_expr_port(f, cell, "B", false);
 		f << stringf(" : ");
 		dump_cell_expr_port(f, cell, "A", false);
@@ -1063,7 +1125,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		f << stringf(" = !(");
 		dump_cell_expr_port(f, cell, "S", false);
 		f << stringf(" ? ");
-		dump_attributes(f, "", cell->attributes, ' ');
+		dump_attributes(f, "", cell->attributes, " ");
 		dump_cell_expr_port(f, cell, "B", false);
 		f << stringf(" : ");
 		dump_cell_expr_port(f, cell, "A", false);
@@ -1079,7 +1141,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		f << stringf(cell->type == ID($_AOI3_) ? " & " : " | ");
 		dump_cell_expr_port(f, cell, "B", false);
 		f << stringf(cell->type == ID($_AOI3_) ? ") |" : ") &");
-		dump_attributes(f, "", cell->attributes, ' ');
+		dump_attributes(f, "", cell->attributes, " ");
 		f << stringf(" ");
 		dump_cell_expr_port(f, cell, "C", false);
 		f << stringf(");\n");
@@ -1094,7 +1156,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		f << stringf(cell->type == ID($_AOI4_) ? " & " : " | ");
 		dump_cell_expr_port(f, cell, "B", false);
 		f << stringf(cell->type == ID($_AOI4_) ? ") |" : ") &");
-		dump_attributes(f, "", cell->attributes, ' ');
+		dump_attributes(f, "", cell->attributes, " ");
 		f << stringf(" (");
 		dump_cell_expr_port(f, cell, "C", false);
 		f << stringf(cell->type == ID($_AOI4_) ? " & " : " | ");
@@ -1196,7 +1258,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			f << stringf("%s" "assign ", indent.c_str());
 			dump_sigspec(f, cell->getPort(ID::Y));
 			f << stringf(" = $signed(%s) / ", buf_num.c_str());
-			dump_attributes(f, "", cell->attributes, ' ');
+			dump_attributes(f, "", cell->attributes, " ");
 			f << stringf("$signed(%s);\n", buf_b.c_str());
 			return true;
 		} else {
@@ -1219,7 +1281,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort(ID::A))-1, temp_id.c_str());
 			dump_cell_expr_port(f, cell, "A", true);
 			f << stringf(" %% ");
-			dump_attributes(f, "", cell->attributes, ' ');
+			dump_attributes(f, "", cell->attributes, " ");
 			dump_cell_expr_port(f, cell, "B", true);
 			f << stringf(";\n");
 
@@ -1294,7 +1356,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		f << stringf(" = ");
 		dump_sigspec(f, cell->getPort(ID::S));
 		f << stringf(" ? ");
-		dump_attributes(f, "", cell->attributes, ' ');
+		dump_attributes(f, "", cell->attributes, " ");
 		dump_sigspec(f, cell->getPort(ID::B));
 		f << stringf(" : ");
 		dump_sigspec(f, cell->getPort(ID::A));
@@ -1403,7 +1465,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		f << stringf(" = ");
 		dump_const(f, cell->parameters.at(ID::LUT));
 		f << stringf(" >> ");
-		dump_attributes(f, "", cell->attributes, ' ');
+		dump_attributes(f, "", cell->attributes, " ");
 		dump_sigspec(f, cell->getPort(ID::A));
 		f << stringf(";\n");
 		return true;
@@ -1753,6 +1815,55 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
+	if (cell->type == ID($print))
+	{
+		// Sync $print cells are accumulated and handled in dump_module.
+		if (cell->getParam(ID::TRG_ENABLE).as_bool())
+			return true;
+
+		f << stringf("%s" "always @*\n", indent.c_str());
+
+		f << stringf("%s" "  if (", indent.c_str());
+		dump_sigspec(f, cell->getPort(ID::EN));
+		f << stringf(")\n");
+
+		dump_cell_expr_print(f, indent + "    ", cell);
+		return true;
+	}
+
+	if (cell->type == ID($check))
+	{
+		// Sync $check cells are accumulated and handled in dump_module.
+		if (cell->getParam(ID::TRG_ENABLE).as_bool())
+			return true;
+
+		f << stringf("%s" "always @*\n", indent.c_str());
+
+		f << stringf("%s" "  if (", indent.c_str());
+		dump_sigspec(f, cell->getPort(ID::EN));
+		f << stringf(") begin\n");
+
+		std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
+		if (flavor == "assert" || flavor == "assume") {
+			Fmt fmt;
+			fmt.parse_rtlil(cell);
+			if (!fmt.parts.empty()) {
+				f << stringf("%s" "    if (!", indent.c_str());
+				dump_sigspec(f, cell->getPort(ID::A));
+				f << stringf(")\n");
+				dump_cell_expr_print(f, indent + "      ", cell);
+			}
+		} else {
+			f << stringf("%s" "  /* message omitted */\n", indent.c_str());
+		}
+
+		dump_cell_expr_check(f, indent + "    ", cell);
+
+		f << stringf("%s" "  end\n", indent.c_str());
+
+		return true;
+	}
+
 	// FIXME: $fsm
 
 	return false;
@@ -1760,6 +1871,13 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 {
+	// To keep the output compatible with other tools we ignore $scopeinfo
+	// cells that exist only to hold metadata. If in the future that metadata
+	// should be exposed as part of the write_verilog output it should be
+	// opt-in and/or represented as something else than a $scopeinfo cell.
+	if (cell->type == ID($scopeinfo))
+		return;
+
 	// Handled by dump_memory
 	if (cell->is_mem_cell())
 		return;
@@ -1778,7 +1896,8 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			if (it != cell->parameters.begin())
 				f << stringf(",");
 			f << stringf("\n%s  .%s(", indent.c_str(), id(it->first).c_str());
-			dump_const(f, it->second);
+			if (it->second.size() > 0)
+				dump_const(f, it->second);
 			f << stringf(")");
 		}
 		f << stringf("\n%s" ")", indent.c_str());
@@ -1841,36 +1960,90 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	}
 }
 
+void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec &trg, const RTLIL::Const &polarity, std::vector<const RTLIL::Cell*> &cells)
+{
+	if (trg.size() == 0) {
+		f << stringf("%s" "initial begin\n", indent.c_str());
+	} else {
+		f << stringf("%s" "always @(", indent.c_str());
+		for (int i = 0; i < trg.size(); i++) {
+			if (i != 0)
+				f << " or ";
+			if (polarity[i])
+				f << "posedge ";
+			else
+				f << "negedge ";
+			dump_sigspec(f, trg[i]);
+		}
+		f << ") begin\n";
+	}
+
+	std::sort(cells.begin(), cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
+		return a->getParam(ID::PRIORITY).as_int() > b->getParam(ID::PRIORITY).as_int();
+	});
+	for (auto cell : cells) {
+		f << stringf("%s" "  if (", indent.c_str());
+		dump_sigspec(f, cell->getPort(ID::EN));
+		f << stringf(") begin\n");
+
+		if (cell->type == ID($print)) {
+			dump_cell_expr_print(f, indent + "    ", cell);
+		} else if (cell->type == ID($check)) {
+			std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
+			if (flavor == "assert" || flavor == "assume") {
+				Fmt fmt;
+				fmt.parse_rtlil(cell);
+				if (!fmt.parts.empty()) {
+					f << stringf("%s" "    if (!", indent.c_str());
+					dump_sigspec(f, cell->getPort(ID::A));
+					f << stringf(")\n");
+					dump_cell_expr_print(f, indent + "      ", cell);
+				}
+			} else {
+				f << stringf("%s" "  /* message omitted */\n", indent.c_str());
+			}
+
+			dump_cell_expr_check(f, indent + "    ", cell);
+		}
+
+		f << stringf("%s" "  end\n", indent.c_str());
+	}
+
+	f << stringf("%s" "end\n", indent.c_str());
+}
+
 void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 {
-	if (simple_lhs) {
+	bool all_chunks_wires = true;
+	for (auto &chunk : left.chunks())
+		if (chunk.is_wire() && reg_wires.count(chunk.wire->name))
+			all_chunks_wires = false;
+	if (!simple_lhs && all_chunks_wires) {
+		f << stringf("%s" "assign ", indent.c_str());
+		dump_sigspec(f, left);
+		f << stringf(" = ");
+		dump_sigspec(f, right);
+		f << stringf(";\n");
+	} else {
 		int offset = 0;
 		for (auto &chunk : left.chunks()) {
-			f << stringf("%s" "assign ", indent.c_str());
+			if (chunk.is_wire() && reg_wires.count(chunk.wire->name))
+				f << stringf("%s" "always%s\n%s  ", indent.c_str(), systemverilog ? "_comb" : " @*", indent.c_str());
+			else
+				f << stringf("%s" "assign ", indent.c_str());
 			dump_sigspec(f, chunk);
 			f << stringf(" = ");
 			dump_sigspec(f, right.extract(offset, GetSize(chunk)));
 			f << stringf(";\n");
 			offset += GetSize(chunk);
 		}
-	} else {
-		f << stringf("%s" "assign ", indent.c_str());
-		dump_sigspec(f, left);
-		f << stringf(" = ");
-		dump_sigspec(f, right);
-		f << stringf(";\n");
 	}
 }
 
 void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw);
 
-void dump_case_body(std::ostream &f, std::string indent, RTLIL::CaseRule *cs, bool omit_trailing_begin = false)
+void dump_case_actions(std::ostream &f, std::string indent, RTLIL::CaseRule *cs)
 {
-	int number_of_stmts = cs->switches.size() + cs->actions.size();
-
-	if (!omit_trailing_begin && number_of_stmts >= 2)
-		f << stringf("%s" "begin\n", indent.c_str());
-
 	for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) {
 		if (it->first.size() == 0)
 			continue;
@@ -1880,7 +2053,64 @@ void dump_case_body(std::ostream &f, std::string indent, RTLIL::CaseRule *cs, bo
 		dump_sigspec(f, it->second);
 		f << stringf(";\n");
 	}
+}
+
+bool dump_proc_switch_ifelse(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw)
+{
+	for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
+		if ((*it)->compare.size() == 0) {
+			break;
+		} else if ((*it)->compare.size() == 1) {
+			int case_index = it - sw->cases.begin();
+			SigSpec compare = (*it)->compare.at(0);
+			if (case_index >= compare.size())
+				return false;
+			if (compare[case_index] != State::S1)
+				return false;
+			for (int bit_index = 0; bit_index < compare.size(); bit_index++)
+				if (bit_index != case_index && compare[bit_index] != State::Sa)
+					return false;
+		} else {
+			return false;
+		}
+	}
 
+	dump_attributes(f, indent, sw->attributes);
+	f << indent;
+	auto sig_it = sw->signal.begin();
+	for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it, ++sig_it) {
+		if (it != sw->cases.begin()) {
+			if ((*it)->compare.empty())
+				f << " else begin\n";
+			else
+				f << " else ";
+		}
+		if (!(*it)->compare.empty()) {
+			f << stringf("if (");
+			dump_sigspec(f, *sig_it);
+			f << stringf(") begin\n");
+		}
+
+		dump_case_actions(f, indent, (*it));
+		for (auto it2 = (*it)->switches.begin(); it2 != (*it)->switches.end(); ++it2)
+			dump_proc_switch(f, indent + "  ", *it2);
+
+		f << indent << "end";
+		if ((*it)->compare.empty())
+			break;
+	}
+	f << "\n";
+	return true;
+}
+
+void dump_case_body(std::ostream &f, std::string indent, RTLIL::CaseRule *cs, bool omit_trailing_begin = false)
+{
+	int number_of_stmts = cs->switches.size() + cs->actions.size();
+
+	if (!omit_trailing_begin && number_of_stmts >= 2)
+		f << stringf("%s" "begin\n", indent.c_str());
+
+	dump_case_actions(f, indent, cs);
 	for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it)
 		dump_proc_switch(f, indent + "  ", *it);
 
@@ -1903,17 +2133,18 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 		return;
 	}
 
+	if (dump_proc_switch_ifelse(f, indent, sw))
+		return;
+
 	dump_attributes(f, indent, sw->attributes);
 	f << stringf("%s" "casez (", indent.c_str());
 	dump_sigspec(f, sw->signal);
 	f << stringf(")\n");
 
-	bool got_default = false;
 	for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
-		dump_attributes(f, indent + "  ", (*it)->attributes, '\n', /*modattr=*/false, /*regattr=*/false, /*as_comment=*/true);
+		bool got_default = false;
+		dump_attributes(f, indent + "  ", (*it)->attributes, "\n", /*modattr=*/false, /*regattr=*/false, /*as_comment=*/true);
 		if ((*it)->compare.size() == 0) {
-			if (got_default)
-				continue;
 			f << stringf("%s  default", indent.c_str());
 			got_default = true;
 		} else {
@@ -1926,6 +2157,19 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 		}
 		f << stringf(":\n");
 		dump_case_body(f, indent + "    ", *it);
+
+		if (got_default) {
+			// If we followed up the default with more cases the Verilog
+			// semantics would be to match those *before* the default, but
+			// the RTLIL semantics are to match those *after* the default
+			// (so they can never be selected). Exit now.
+			break;
+		}
+	}
+
+	if (sw->cases.empty()) {
+		// Verilog does not allow empty cases.
+		f << stringf("%s  default: ;\n", indent.c_str());
 	}
 
 	f << stringf("%s" "endcase\n", indent.c_str());
@@ -2022,6 +2266,8 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
 
 void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 {
+	std::map<std::pair<RTLIL::SigSpec, RTLIL::Const>, std::vector<const RTLIL::Cell*>> sync_effect_cells;
+
 	reg_wires.clear();
 	reset_auto_counter(module);
 	active_module = module;
@@ -2037,11 +2283,15 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 					active_initdata[sig[i]] = val[i];
 		}
 
-	if (!module->processes.empty())
-		log_warning("Module %s contains unmapped RTLIL processes. RTLIL processes\n"
-				"can't always be mapped directly to Verilog always blocks. Unintended\n"
-				"changes in simulation behavior are possible! Use \"proc\" to convert\n"
-				"processes to logic networks and registers.\n", log_id(module));
+	bool has_sync_rules = false;
+	for (auto process : module->processes)
+		if (!process.second->syncs.empty())
+			has_sync_rules = true;
+	if (has_sync_rules)
+		log_warning("Module %s contains RTLIL processes with sync rules. Such RTLIL "
+				"processes can't always be mapped directly to Verilog always blocks. "
+				"unintended changes in simulation behavior are possible! Use \"proc\" "
+				"to convert processes to logic networks and registers.\n", log_id(module));
 
 	f << stringf("\n");
 	for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
@@ -2052,6 +2302,11 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		std::set<std::pair<RTLIL::Wire*,int>> reg_bits;
 		for (auto cell : module->cells())
 		{
+			if (cell->type.in(ID($print), ID($check)) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
+				sync_effect_cells[make_pair(cell->getPort(ID::TRG), cell->getParam(ID::TRG_POLARITY))].push_back(cell);
+				continue;
+			}
+
 			if (!RTLIL::builtin_ff_cell_types().count(cell->type) || !cell->hasPort(ID::Q) || cell->type.in(ID($ff), ID($_FF_)))
 				continue;
 
@@ -2075,7 +2330,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		}
 	}
 
-	dump_attributes(f, indent, module->attributes, '\n', /*modattr=*/true);
+	dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true);
 	f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
 	bool keep_running = true;
 	int cnt = 0;
@@ -2107,6 +2362,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 	for (auto cell : module->cells())
 		dump_cell(f, indent + "  ", cell);
 
+	for (auto &it : sync_effect_cells)
+		dump_sync_effect(f, indent + "  ", it.first.first, it.first.second, it.second);
+
 	for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
 		dump_process(f, indent + "  ", it->second);
 
diff --git a/yosys/cpu.aig b/yosys/cpu.aig
new file mode 100644
index 00000000000..6a860420f04
--- /dev/null
+++ b/yosys/cpu.aig
@@ -0,0 +1,1146 @@
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>c
+Generated by Yosys 0.41 (git sha1 c1ad37779ee, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)
diff --git a/yosys/cpu_reg.v b/yosys/cpu_reg.v
new file mode 100644
index 00000000000..bb5c29b839b
--- /dev/null
+++ b/yosys/cpu_reg.v
@@ -0,0 +1,330 @@
+`timescale 1 ps / 100 fs
+// fpga4student.com: FPGA projects, Verilog Projects, VHDL projects
+// Verilog project: 32-bit 5-stage Pipelined MIPS Processor in Verilog 
+// Register file 
+module regfile(
+ReadData1,
+ReadData2,
+WriteData,
+ReadRegister1,
+ReadRegister2,
+WriteRegister,
+RegWrite,
+reset,
+clk);
+
+input [4:0]ReadRegister1,ReadRegister2,WriteRegister;
+input [31:0] WriteData;
+input RegWrite,reset, clk;
+output [31:0] ReadData1, ReadData2;
+wire [31:0] WriteEn;
+wire [31:0] RegArray [0:31];
+integer i;
+     //----Decoder Block
+ decoder Decoder1( WriteEn,RegWrite,WriteRegister);
+ register reg0 (RegArray[0],32'b0,1'b1,1'b0, clk);
+ register reg1 (RegArray[1],WriteData,WriteEn[1],reset,clk);
+ register reg2 (RegArray[2],WriteData,WriteEn[2],reset,clk);
+ register reg3 (RegArray[3],WriteData,WriteEn[3],reset,clk);
+ register reg4 (RegArray[4],WriteData,WriteEn[4],reset,clk);
+ register reg5 (RegArray[5],WriteData,WriteEn[5],reset,clk);
+ register reg6 (RegArray[6],WriteData,WriteEn[6],reset,clk);
+ register reg7 (RegArray[7],WriteData,WriteEn[7],reset,clk);
+ register reg8 (RegArray[8],WriteData,WriteEn[8],reset,clk);
+ register reg9 (RegArray[9],WriteData,WriteEn[9],reset,clk);
+ register reg10 (RegArray[10],WriteData,WriteEn[10],reset,clk);
+ register reg11 (RegArray[11],WriteData,WriteEn[11],reset,clk);
+ register reg12 (RegArray[12],WriteData,WriteEn[12],reset,clk);
+ register reg13 (RegArray[13],WriteData,WriteEn[13],reset,clk);
+ register reg14 (RegArray[14],WriteData,WriteEn[14],reset,clk);
+ register reg15 (RegArray[15],WriteData,WriteEn[15],reset,clk);
+ register reg16 (RegArray[16],WriteData,WriteEn[16],reset,clk);
+ register reg17 (RegArray[17],WriteData,WriteEn[17],reset,clk);
+ register reg18 (RegArray[18],WriteData,WriteEn[18],reset,clk);
+ register reg19 (RegArray[19],WriteData,WriteEn[19],reset,clk);
+ register reg20 (RegArray[20],WriteData,WriteEn[20],reset,clk);
+ register reg21 (RegArray[21],WriteData,WriteEn[21],reset,clk);
+ register reg22 (RegArray[22],WriteData,WriteEn[22],reset,clk);
+ register reg23 (RegArray[23],WriteData,WriteEn[23],reset,clk);
+ register reg24 (RegArray[24],WriteData,WriteEn[24],reset,clk);
+ register reg25 (RegArray[25],WriteData,WriteEn[25],reset,clk);
+ register reg26 (RegArray[26],WriteData,WriteEn[26],reset,clk);
+ register reg27 (RegArray[27],WriteData,WriteEn[27],reset,clk);
+ register reg28 (RegArray[28],WriteData,WriteEn[28],reset,clk);
+ register reg29 (RegArray[29],WriteData,WriteEn[29],reset,clk);
+ register reg30 (RegArray[30],WriteData,WriteEn[30],reset,clk);
+ register reg31 (RegArray[31],WriteData,WriteEn[31],reset,clk); 
+ //----32x32to32 Multiplexor1 Block----
+    mux32x32to32 Mux1(ReadData1,RegArray[0], RegArray[1],RegArray[2], RegArray[3],RegArray[4],RegArray[5],RegArray[6],RegArray[7],
+ RegArray[8],RegArray[9],RegArray[10],RegArray[11],RegArray[12],RegArray[13],RegArray[14],RegArray[15],RegArray[16],RegArray[17],
+ RegArray[18], RegArray[19],RegArray[20],RegArray[21],RegArray[22],RegArray[23],RegArray[24],RegArray[25],RegArray[26],
+ RegArray[27], RegArray[28], RegArray[29],RegArray[30],RegArray[31], ReadRegister1
+      ); 
+           
+ //----32x32to32 Multiplexor2 Block----
+ mux32x32to32 Mux2(ReadData2,RegArray[0], RegArray[1],RegArray[2], RegArray[3],RegArray[4],RegArray[5],RegArray[6],RegArray[7],
+ RegArray[8],RegArray[9],RegArray[10],RegArray[11],RegArray[12],RegArray[13],RegArray[14],RegArray[15],RegArray[16],RegArray[17],
+ RegArray[18], RegArray[19],RegArray[20],RegArray[21],RegArray[22],RegArray[23],RegArray[24],RegArray[25],RegArray[26],
+ RegArray[27], RegArray[28], RegArray[29],RegArray[30],RegArray[31], ReadRegister2
+       );  
+endmodule
+
+//------------DFF-------------------
+module D_FF (q, d, reset, clk);
+output q;
+input d, reset, clk;
+reg q; // Indicate that q is stateholding
+ 
+always @(posedge clk or posedge reset)
+if (reset)
+q = 0; // On reset, set to 0
+else
+q = d; // Otherwise out = d 
+endmodule
+// 1 bit register 
+module RegBit(BitOut, BitData, WriteEn,reset, clk);
+output BitOut; // 1 bit of register
+input BitData, WriteEn; 
+input reset,clk;
+wire d,f1, f2; // input of D Flip-Flop
+wire reset;
+//assign reset=0;
+and #(50) U1(f1, BitOut, (~WriteEn));
+and #(50) U2(f2, BitData, WriteEn);
+or  #(50) U3(d, f1, f2);
+D_FF DFF0(BitOut, d, reset, clk);
+endmodule
+
+//32 bit register 
+module register(RegOut,RegIn,WriteEn,reset,clk); 
+output [31:0] RegOut;
+input [31:0] RegIn;
+input WriteEn,reset, clk;
+RegBit bit31(RegOut[31],RegIn[31],WriteEn,reset,clk);
+RegBit bit30(RegOut[30],RegIn[30],WriteEn,reset,clk);
+RegBit bit29(RegOut[29],RegIn[29],WriteEn,reset,clk); 
+RegBit bit28(RegOut[28],RegIn[28],WriteEn,reset,clk); 
+RegBit bit27(RegOut[27],RegIn[27],WriteEn,reset,clk); 
+RegBit bit26(RegOut[26],RegIn[26],WriteEn,reset,clk); 
+RegBit bit25(RegOut[25],RegIn[25],WriteEn,reset,clk); 
+RegBit bit24(RegOut[24],RegIn[24],WriteEn,reset,clk); 
+RegBit bit23(RegOut[23],RegIn[23],WriteEn,reset,clk); 
+RegBit bit22(RegOut[22],RegIn[22],WriteEn,reset,clk); 
+RegBit bit21(RegOut[21],RegIn[21],WriteEn,reset,clk); 
+RegBit bit20(RegOut[20],RegIn[20],WriteEn,reset,clk); 
+RegBit bit19(RegOut[19],RegIn[19],WriteEn,reset,clk); 
+RegBit bit18(RegOut[18],RegIn[18],WriteEn,reset,clk); 
+RegBit bit17(RegOut[17],RegIn[17],WriteEn,reset,clk); 
+RegBit bit16(RegOut[16],RegIn[16],WriteEn,reset,clk); 
+RegBit bit15(RegOut[15],RegIn[15],WriteEn,reset,clk); 
+RegBit bit14(RegOut[14],RegIn[14],WriteEn,reset,clk); 
+RegBit bit13(RegOut[13],RegIn[13],WriteEn,reset,clk); 
+RegBit bit12(RegOut[12],RegIn[12],WriteEn,reset,clk); 
+RegBit bit11(RegOut[11],RegIn[11],WriteEn,reset,clk); 
+RegBit bit10(RegOut[10],RegIn[10],WriteEn,reset,clk); 
+RegBit bit9 (RegOut[9], RegIn[9], WriteEn,reset,clk); 
+RegBit bit8 (RegOut[8], RegIn[8], WriteEn,reset,clk); 
+RegBit bit7 (RegOut[7], RegIn[7], WriteEn,reset,clk); 
+RegBit bit6 (RegOut[6], RegIn[6], WriteEn,reset,clk); 
+RegBit bit5 (RegOut[5], RegIn[5], WriteEn,reset,clk); 
+RegBit bit4 (RegOut[4], RegIn[4], WriteEn,reset,clk); 
+RegBit bit3 (RegOut[3], RegIn[3], WriteEn,reset,clk); 
+RegBit bit2 (RegOut[2], RegIn[2], WriteEn,reset,clk); 
+RegBit bit1 (RegOut[1], RegIn[1], WriteEn,reset,clk); 
+RegBit bit0 (RegOut[0], RegIn[0], WriteEn,reset,clk); 
+
+endmodule
+
+// Decoder 
+module decoder(WriteEn,RegWrite, WriteRegister);
+input RegWrite;
+input [4:0] WriteRegister;
+output [31:0] WriteEn;
+wire [31:0] OE; // Output Enable
+dec5to32 dec(OE,WriteRegister);
+assign WriteEn[0]=0;
+ and  #(50) gate1(WriteEn[1],OE[1],RegWrite);
+ and  #(50) gate2(WriteEn[2],OE[2],RegWrite);
+ and  #(50) gate3(WriteEn[3],OE[3],RegWrite);
+ and  #(50) gate4(WriteEn[4],OE[4],RegWrite);
+ and  #(50) gate5(WriteEn[5],OE[5],RegWrite);
+ and  #(50) gate6(WriteEn[6],OE[6],RegWrite);
+ and  #(50) gate7(WriteEn[7],OE[7],RegWrite);
+ and  #(50) gate8(WriteEn[8],OE[8],RegWrite);
+ and  #(50) gate9(WriteEn[9],OE[9],RegWrite);
+ and  #(50) gate10(WriteEn[10],OE[10],RegWrite);
+ and  #(50) gate11(WriteEn[11],OE[11],RegWrite);
+ and  #(50) gate12(WriteEn[12],OE[12],RegWrite);
+ and  #(50) gate13(WriteEn[13],OE[13],RegWrite);
+ and  #(50) gate14(WriteEn[14],OE[14],RegWrite);
+ and  #(50) gate15(WriteEn[15],OE[15],RegWrite);
+ and  #(50) gate16(WriteEn[16],OE[16],RegWrite);
+ and  #(50) gate17(WriteEn[17],OE[17],RegWrite);
+ and  #(50) gate18(WriteEn[18],OE[18],RegWrite);
+ and  #(50) gate19(WriteEn[19],OE[19],RegWrite);
+ and  #(50) gate20(WriteEn[20],OE[20],RegWrite);
+ and  #(50) gate21(WriteEn[21],OE[21],RegWrite);
+ and  #(50) gate22(WriteEn[22],OE[22],RegWrite);
+ and  #(50) gate23(WriteEn[23],OE[23],RegWrite);
+ and  #(50) gate24(WriteEn[24],OE[24],RegWrite);
+ and  #(50) gate25(WriteEn[25],OE[25],RegWrite);
+ and  #(50) gate26(WriteEn[26],OE[26],RegWrite);
+ and  #(50) gate27(WriteEn[27],OE[27],RegWrite);
+ and  #(50) gate28(WriteEn[28],OE[28],RegWrite);
+ and  #(50) gate29(WriteEn[29],OE[29],RegWrite);
+ and  #(50) gate30(WriteEn[30],OE[30],RegWrite);
+ and  #(50) gate31(WriteEn[31],OE[31],RegWrite);
+endmodule
+module andmore(g,a,b,c,d,e);
+  output g;
+  input a,b,c,d,e;
+  and #(50) and1(f1,a,b,c,d),
+            and2(g,f1,e);
+endmodule
+module dec5to32(Out,Adr);
+input [4:0] Adr; // Adr=Address of register
+output [31:0] Out;
+not #(50) Inv4(Nota, Adr[4]);
+not #(50) Inv3(Notb, Adr[3]);
+not #(50) Inv2(Notc, Adr[2]);
+not #(50) Inv1(Notd, Adr[1]);
+not #(50) Inv0(Note, Adr[0]);
+
+andmore a0(Out[0],  Nota,Notb,Notc,Notd,Note); // 00000
+andmore a1(Out[1],  Nota,Notb,Notc,Notd,Adr[0]); // 00001
+andmore a2(Out[2],  Nota,Notb,Notc,Adr[1],Note); //00010
+andmore a3(Out[3],  Nota,Notb,Notc,Adr[1],Adr[0]);
+andmore a4(Out[4],  Nota,Notb,Adr[2],Notd,Note);
+andmore a5(Out[5],  Nota,Notb,Adr[2],Notd,Adr[0]);
+andmore a6(Out[6],  Nota,Notb,Adr[2],Adr[1],Note);
+andmore a7(Out[7],  Nota,Notb,Adr[2],Adr[1],Adr[0]);
+andmore a8(Out[8],    Nota,Adr[3],Notc,Notd,Note);
+andmore a9(Out[9],    Nota,Adr[3],Notc,Notd,Adr[0]);
+andmore a10(Out[10],  Nota,Adr[3],Notc,Adr[1],Note);
+andmore a11(Out[11],  Nota,Adr[3],Notc,Adr[1],Adr[0]);
+andmore a12(Out[12],  Nota,Adr[3],Adr[2],Notd,Note);
+andmore a13(Out[13],  Nota,Adr[3],Adr[2],Notd,Adr[0]);
+andmore a14(Out[14],  Nota,Adr[3],Adr[2],Adr[1],Note);
+andmore a15(Out[15],  Nota,Adr[3],Adr[2],Adr[1],Adr[0]);
+andmore a16(Out[16],  Adr[4],Notb,Notc,Notd,Note);
+andmore a17(Out[17],  Adr[4],Notb,Notc,Notd,Adr[0]);
+andmore a18(Out[18],  Adr[4],Notb,Notc,Adr[1],Note);
+andmore a19(Out[19],  Adr[4],Notb,Notc,Adr[1],Adr[0]);
+andmore a20(Out[20],  Adr[4],Notb,Adr[2],Notd,Note);
+andmore a21(Out[21],  Adr[4],Notb,Adr[2],Notd,Adr[0]);
+andmore a22(Out[22],  Adr[4],Notb,Adr[2],Adr[1],Note);
+andmore a23(Out[23],  Adr[4],Notb,Adr[2],Adr[1],Adr[0]);
+andmore a24(Out[24],  Adr[4],Adr[3],Notc,Notd,Note);
+andmore a25(Out[25],  Adr[4],Adr[3],Notc,Notd,Adr[0]);
+andmore a26(Out[26],  Adr[4],Adr[3],Notc,Adr[1],Note);
+andmore a27(Out[27],  Adr[4],Adr[3],Notc,Adr[1],Adr[0]);
+andmore a28(Out[28],  Adr[4],Adr[3],Adr[2],Notd,Note);
+andmore a29(Out[29],  Adr[4],Adr[3],Adr[2],Notd,Adr[0]);
+andmore a30(Out[30],  Adr[4],Adr[3],Adr[2],Adr[1],Note);
+andmore a31(Out[31],  Adr[4],Adr[3],Adr[2],Adr[1],Adr[0]); // 11111
+endmodule
+
+//------------module multiplexor 32 to 1----------------
+module mux32to1(Out, In , Select);
+output Out;
+input [31:0] In; 
+input [4:0] Select; 
+wire [31:0] OE,f; // OE = Output Enable
+dec5to32 dec1(OE,Select);
+
+ and  #(50) g_0(f[0],OE[0],In[0]);
+ and  #(50) g_1(f[1],OE[1],In[1]);
+ and  #(50) g_2(f[2],OE[2],In[2]);
+ and  #(50) g_3(f[3],OE[3],In[3]);
+ and  #(50) g_4(f[4],OE[4],In[4]);
+ and  #(50) g_5(f[5],OE[5],In[5]);
+ and  #(50) g_6(f[6],OE[6],In[6]);
+ and  #(50) g_7(f[7],OE[7],In[7]);
+ and  #(50) g_8(f[8],OE[8],In[8]);
+ and  #(50) g_9(f[9],OE[9],In[9]);
+ and  #(50) g_10(f[10],OE[10],In[10]);
+ and  #(50) g_11(f[11],OE[11],In[11]);
+ and  #(50) g_12(f[12],OE[12],In[12]);
+ and  #(50) g_13(f[13],OE[13],In[13]);
+ and  #(50) g_14(f[14],OE[14],In[14]);
+ and  #(50) g_15(f[15],OE[15],In[15]);
+ and  #(50) g_16(f[16],OE[16],In[16]);
+ and  #(50) g_17(f[17],OE[17],In[17]);
+ and  #(50) g_18(f[18],OE[18],In[18]);
+ and  #(50) g_19(f[19],OE[19],In[19]);
+ and  #(50) g_20(f[20],OE[20],In[20]);
+ and  #(50) g_21(f[21],OE[21],In[21]);
+ and  #(50) g_22(f[22],OE[22],In[22]);
+ and  #(50) g_23(f[23],OE[23],In[23]);
+ and  #(50) g_24(f[24],OE[24],In[24]);
+ and  #(50) g_25(f[25],OE[25],In[25]);
+ and  #(50) g_26(f[26],OE[26],In[26]);
+ and  #(50) g_27(f[27],OE[27],In[27]);
+ and  #(50) g_28(f[28],OE[28],In[28]);
+ and  #(50) g_29(f[29],OE[29],In[29]);
+ and  #(50) g_30(f[30],OE[30],In[30]);
+ and  #(50) g_31(f[31],OE[31],In[31]);
+
+ 
+
+ or #(50) gate3(g3,f[0],f[1],f[2],f[3]);
+ or #(50) gate4(g4,f[4],f[5],f[6],f[7]);
+ or #(50) gate5(g5,f[8],f[9],f[10],f[11]);
+ or #(50) gate6(g6,f[12],f[13],f[14],f[15]);
+ or #(50) gate7(g7,f[16],f[17],f[18],f[19]);
+ or #(50) gate8(g8,f[20],f[21],f[22],f[23]);
+ or #(50) gate9(g9,f[24],f[25],f[26],f[27]);
+ or #(50) gate10(g10,f[28],f[29],f[30],f[31]);
+ or #(50) gate11(g11,g3,g4,g5,g6);
+ or #(50) gate12(g12,g7,g8,g9,10);
+ or #(50) gate(Out,g11,g12);
+ endmodule
+module mux32x32to32(ReadData,In0, In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,In16,In17,In18,In19,In20,In21,In22,In23, In24,In25,In26,In27,In28,In29,In30,In31,ReadRegister);
+
+input [31:0] In0, In1,In2,In3,In4,In5,In6,In7,In8,In9,In10,In11,In12,In13,In14,In15,In16,In17,In18,In19,In20,In21,In22,In23,In24,In25,In26,In27,In28,In29,In30,In31;
+input [4:0] ReadRegister;
+output [31:0] ReadData;
+reg [31:0] ArrayReg [0:31];
+integer j;
+always @(*)
+begin
+for (j=0;j<=31;j=j+1)
+          ArrayReg[j] = {In31[j], In30[j],In29[j],In28[j],In27[j],In26[j],In25[j],In24[j],In23[j],In22[j],In21[j],
+       In20[j],In19[j],In18[j],In17[j],In16[j],In15[j],In14[j],In13[j],In12[j],In11[j],
+       In10[j],In9[j],In8[j],In7[j],In6[j],In5[j],In4[j],In3[j],In2[j],In1[j],In0[j]};
+   
+end
+mux32to1  mux0(ReadData[0],ArrayReg[0],ReadRegister);
+mux32to1  mux1(ReadData[1],ArrayReg[1],ReadRegister);
+mux32to1  mux2(ReadData[2],ArrayReg[2],ReadRegister);
+mux32to1  mux3(ReadData[3],ArrayReg[3],ReadRegister);
+mux32to1  mux4(ReadData[4],ArrayReg[4],ReadRegister);
+mux32to1  mux5(ReadData[5],ArrayReg[5],ReadRegister);
+mux32to1  mux6(ReadData[6],ArrayReg[6],ReadRegister);
+mux32to1  mux7(ReadData[7],ArrayReg[7],ReadRegister);
+mux32to1  mux8(ReadData[8],ArrayReg[8],ReadRegister);
+mux32to1  mux9(ReadData[9],ArrayReg[9],ReadRegister);
+mux32to1  mux10(ReadData[10],ArrayReg[10],ReadRegister);
+mux32to1  mux11(ReadData[11],ArrayReg[11],ReadRegister); 
+mux32to1  mux12(ReadData[12],ArrayReg[12],ReadRegister);
+mux32to1  mux13(ReadData[13],ArrayReg[13],ReadRegister);
+mux32to1  mux14(ReadData[14],ArrayReg[14],ReadRegister);
+mux32to1  mux15(ReadData[15],ArrayReg[15],ReadRegister); 
+mux32to1  mux16(ReadData[16],ArrayReg[16],ReadRegister);
+mux32to1  mux17(ReadData[17],ArrayReg[17],ReadRegister);
+mux32to1  mux18(ReadData[18],ArrayReg[18],ReadRegister);
+mux32to1  mux19(ReadData[19],ArrayReg[19],ReadRegister);
+mux32to1  mux20(ReadData[20],ArrayReg[20],ReadRegister);
+mux32to1  mux21(ReadData[21],ArrayReg[21],ReadRegister);
+mux32to1  mux22(ReadData[22],ArrayReg[22],ReadRegister);
+mux32to1  mux23(ReadData[23],ArrayReg[23],ReadRegister);
+mux32to1  mux24(ReadData[24],ArrayReg[24],ReadRegister);
+mux32to1  mux25(ReadData[25],ArrayReg[25],ReadRegister);
+mux32to1  mux26(ReadData[26],ArrayReg[26],ReadRegister);
+mux32to1  mux27(ReadData[27],ArrayReg[27],ReadRegister);
+mux32to1  mux28(ReadData[28],ArrayReg[28],ReadRegister);
+mux32to1  mux29(ReadData[29],ArrayReg[29],ReadRegister);
+mux32to1  mux30(ReadData[30],ArrayReg[30],ReadRegister);
+mux32to1  mux31(ReadData[31],ArrayReg[31],ReadRegister);
+
+endmodule
\ No newline at end of file
diff --git a/yosys/docs/.gitignore b/yosys/docs/.gitignore
index e36f2309a01..65bbcdeaeb8 100644
--- a/yosys/docs/.gitignore
+++ b/yosys/docs/.gitignore
@@ -1,11 +1,9 @@
 /build/
 /source/cmd
-/source/temp
-/images/*.log
-/images/*.aux
-/images/*.pdf
-/images/*.svg
-/images/011/*.log
-/images/011/*.aux
-/images/011/*.pdf
-/images/011/*.svg
+/source/generated
+/source/_images/**/*.log
+/source/_images/**/*.aux
+/source/_images/**/*.pdf
+/source/_images/**/*.svg
+/source/_images/**/*.dot
+/source/_images/code_examples
diff --git a/yosys/docs/Makefile b/yosys/docs/Makefile
index 2319e1665c3..701157ee6c3 100644
--- a/yosys/docs/Makefile
+++ b/yosys/docs/Makefile
@@ -45,8 +45,11 @@ help:
 	@echo "  dummy      to check syntax errors of document sources"
 
 .PHONY: clean
-clean:
+clean: clean-examples
 	rm -rf $(BUILDDIR)/*
+	rm -rf source/cmd util/__pycache__
+	rm -rf source/generated
+	$(MAKE) -C source/_images clean
 
 .PHONY: html
 html:
@@ -224,3 +227,30 @@ dummy:
 	$(SPHINXBUILD) -b dummy $(ALLSPHINXOPTS) $(BUILDDIR)/dummy
 	@echo
 	@echo "Build finished. Dummy builder generates no files."
+
+PYTHON ?= python3
+
+.PHONY: test test-examples test-macros examples
+test: test-examples test-macros
+
+FORCE:
+Makefile-%: FORCE
+	$(MAKE) -C $(@D) $(*F)
+
+CODE_EXAMPLES := $(wildcard source/code_examples/*/Makefile)
+TEST_EXAMPLES := $(addsuffix -all,$(CODE_EXAMPLES))
+CLEAN_EXAMPLES := $(addsuffix -clean,$(CODE_EXAMPLES))
+test-examples: $(TEST_EXAMPLES)
+clean-examples: $(CLEAN_EXAMPLES)
+examples: $(TEST_EXAMPLES)
+
+test-macros:
+	$(PYTHON) tests/macro_commands.py
+
+.PHONY: images
+images:
+	$(MAKE) -C source/_images
+
+.PHONY: reqs
+reqs:
+	$(PYTHON) -m pip install -r source/requirements.txt
diff --git a/yosys/docs/images/011/example_out.tex b/yosys/docs/images/011/example_out.tex
deleted file mode 100644
index 831b036e993..00000000000
--- a/yosys/docs/images/011/example_out.tex
+++ /dev/null
@@ -1,18 +0,0 @@
-\documentclass[12pt,tikz]{standalone}
-\pdfinfoomitdate 1
-\pdfsuppressptexinfo 1
-\pdftrailerid{}
-\usepackage[utf8]{inputenc}
-\usepackage{tikz}
-\pagestyle{empty}
-
-\begin{document}
-\begin{tikzpicture}
-	\node[inner sep=0pt] at (0,0)
-		{\includegraphics[width=\linewidth]{example_00.pdf}};
-	\node[inner sep=0pt] at (0,-3.8)
-		{\includegraphics[width=\linewidth]{example_01.pdf}};
-	\node[inner sep=0pt] at (0,-7)
-		{\includegraphics[width=\linewidth]{example_02.pdf}};
-\end{tikzpicture}
-\end{document}
diff --git a/yosys/docs/images/011/select_prod.tex b/yosys/docs/images/011/select_prod.tex
deleted file mode 100644
index c4a3c6e379b..00000000000
--- a/yosys/docs/images/011/select_prod.tex
+++ /dev/null
@@ -1,19 +0,0 @@
-\documentclass[12pt,tikz]{standalone}
-\pdfinfoomitdate 1
-\pdfsuppressptexinfo 1
-\pdftrailerid{}
-\usepackage[utf8]{inputenc}
-\pagestyle{empty}
-
-\begin{document}
-\begin{tikzpicture}
-	\node[inner sep=0pt] at (0,0)
-		{\hfill \includegraphics[width=4cm,trim=0 1cm 0 1cm]{sumprod_02.pdf}};
-	\node[inner sep=0pt] at (0,-2.8)
-		{\includegraphics[width=\linewidth,trim=0 0cm 0 1cm]{sumprod_03.pdf}};
-	\node[inner sep=0pt] at (0,-6.2)
-		{\includegraphics[width=\linewidth,trim=0 0cm 0 1cm]{sumprod_04.pdf}};
-	\node[inner sep=0pt] at (0,-9.2)
-		{\includegraphics[width=\linewidth,trim=0 1cm 0 1cm]{sumprod_05.pdf}};
-\end{tikzpicture}
-\end{document}
diff --git a/yosys/docs/images/011/splitnets_libfile.tex b/yosys/docs/images/011/splitnets_libfile.tex
deleted file mode 100644
index 9669ef841b0..00000000000
--- a/yosys/docs/images/011/splitnets_libfile.tex
+++ /dev/null
@@ -1,15 +0,0 @@
-\documentclass[12pt,tikz]{standalone}
-\pdfinfoomitdate 1
-\pdfsuppressptexinfo 1
-\pdftrailerid{}
-\usepackage[utf8]{inputenc}
-\pagestyle{empty}
-
-\begin{document}
-\begin{tikzpicture}
-	\node[inner sep=0pt] at (0,0)
-		{\includegraphics[height=\linewidth]{cmos_00.pdf}};
-	\node[inner sep=0pt] at (2,-8)
-		{\includegraphics[width=\linewidth]{cmos_01.pdf}};
-\end{tikzpicture}
-\end{document}
diff --git a/yosys/docs/images/011/submod_dots.tex b/yosys/docs/images/011/submod_dots.tex
deleted file mode 100644
index 3d48b46e5a5..00000000000
--- a/yosys/docs/images/011/submod_dots.tex
+++ /dev/null
@@ -1,27 +0,0 @@
-\documentclass[12pt,tikz]{standalone}
-\pdfinfoomitdate 1
-\pdfsuppressptexinfo 1
-\pdftrailerid{}
-\usepackage[utf8]{inputenc}
-\pagestyle{empty}
-
-\begin{document}
-\begin{tikzpicture}
-	\node[inner sep=0pt] at (0,0)
-		{\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{submod_00.pdf}};
-	\node at (0, -2.5)
-		{\tt memdemo};
-	\node[inner sep=0pt] at (0,-5)
-		{\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{submod_01.pdf}};
-	\node at (0, -7.5)
-		{\tt scramble};
-	\node[inner sep=0pt] at (0, -11)
-		{\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{submod_02.pdf}};
-	\node at (0, -14.8)
-		{\tt outstage};
-	\node[inner sep=0pt] at (0,-16.6)
-		{\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{submod_03.pdf}};
-	\node at (0, -19)
-		{\tt selstage};
-\end{tikzpicture}
-\end{document}
diff --git a/yosys/docs/images/Makefile b/yosys/docs/images/Makefile
deleted file mode 100644
index a7216ec9010..00000000000
--- a/yosys/docs/images/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-all: dots tex svg tidy
-
-TEX_SOURCE:= $(wildcard *.tex)
-DOT_LOC:= ../source/APPNOTE_011_Design_Investigation
-DOT_SOURCE:= $(wildcard $(DOT_LOC)/*.dot)
-
-TEX_SOURCE+= 011/example_out.tex
-011/example_out.pdf: 011/example_00.pdf 011/example_01.pdf 011/example_02.pdf
-TEX_SOURCE+= 011/select_prod.tex
-011/select_prod.pdf: 011/sumprod_02.pdf 011/sumprod_03.pdf 011/sumprod_04.pdf 011/sumprod_05.pdf
-TEX_SOURCE+= 011/splitnets_libfile.tex
-011/splitnets_libfile.pdf: 011/cmos_00.pdf 011/cmos_01.pdf
-TEX_SOURCE+= 011/submod_dots.tex
-011/submod_dots.pdf: 011/submod_00.pdf 011/submod_01.pdf 011/submod_02.pdf 011/submod_03.pdf
-
-TEX_PDF:= $(patsubst %.tex,%.pdf,$(TEX_SOURCE))
-DOT_PDF:= $(addprefix 011/,$(notdir $(patsubst %.dot,%.pdf,$(DOT_SOURCE))))
-SVG_OUTPUT:= $(patsubst %.pdf,%.svg,$(TEX_PDF) $(DOT_PDF))
-
-dots: $(DOT_PDF)
-tex: $(TEX_PDF)
-svg: $(SVG_OUTPUT)
-
-011/%.pdf: $(DOT_LOC)/%.dot
-	faketime -f '2022-01-01 00:00:00 x0,001' dot -Tpdf -o $@ $<
-
-011/%.pdf: 011/%.tex
-	cd 011 && faketime -f '2022-01-01 00:00:00 x0,001' pdflatex $(<F) --interaction=nonstopmode
-
-%.pdf: %.tex
-	pdflatex $< --interaction=nonstopmode
-
-%.svg: %.pdf
-	pdf2svg $< $@
-
-.PHONY: clean tidy
-tidy:
-	rm -f *.log
-	rm -f *.aux
-	rm -f  011/*.log 011/*.aux
-clean: tidy
-	rm -f *.pdf
-	rm -f *.svg
-	rm -f 011/*.pdf 011/*.svg
diff --git a/yosys/docs/images/approach_flow.png b/yosys/docs/images/approach_flow.png
deleted file mode 100644
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GIT binary patch
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diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/cmos_00.dot b/yosys/docs/source/APPNOTE_011_Design_Investigation/cmos_00.dot
deleted file mode 100644
index 49c63008081..00000000000
--- a/yosys/docs/source/APPNOTE_011_Design_Investigation/cmos_00.dot
+++ /dev/null
@@ -1,34 +0,0 @@
-digraph "cmos_demo" {
-rankdir="LR";
-remincross=true;
-n4 [ shape=octagon, label="a", color="black", fontcolor="black" ];
-n5 [ shape=octagon, label="b", color="black", fontcolor="black" ];
-n6 [ shape=octagon, label="y", color="black", fontcolor="black" ];
-c10 [ shape=record, label="{{<p7> A|<p8> B|<p9> Y}|$g0\nNOR|{}}" ];
-c11 [ shape=record, label="{{<p7> A|<p9> Y}|$g1\nNOT|{}}" ];
-c12 [ shape=record, label="{{<p7> A|<p9> Y}|$g2\nNOT|{}}" ];
-c13 [ shape=record, label="{{<p7> A|<p8> B|<p9> Y}|$g3\nNOR|{}}" ];
-x0 [ shape=record, style=rounded, label="<s0> 1:1 - 0:0 " ];
-x0:e -> c13:p9:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", label=""];
-c14 [ shape=record, label="{{<p7> A|<p8> B|<p9> Y}|$g4\nNOR|{}}" ];
-x1 [ shape=record, style=rounded, label="<s0> 1:1 - 0:0 " ];
-x1:e -> c14:p8:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", label=""];
-x2 [ shape=record, style=rounded, label="<s0> 0:0 - 0:0 " ];
-x2:e -> c14:p9:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", label=""];
-n1 [ shape=diamond, label="$n4" ];
-n1:e -> c10:p9:w [color="black", label=""];
-n1:e -> c14:p7:w [color="black", label=""];
-n2 [ shape=diamond, label="$n5" ];
-n2:e -> c11:p9:w [color="black", label=""];
-n2:e -> c13:p7:w [color="black", label=""];
-n3 [ shape=diamond, label="$n6_1" ];
-n3:e -> c12:p9:w [color="black", label=""];
-n3:e -> c13:p8:w [color="black", label=""];
-n4:e -> c10:p8:w [color="black", label=""];
-n4:e -> c12:p7:w [color="black", label=""];
-n5:e -> c10:p7:w [color="black", label=""];
-n5:e -> c11:p7:w [color="black", label=""];
-n6:e -> x0:s0:w [color="black", label=""];
-n6:e -> x1:s0:w [color="black", label=""];
-n6:e -> x2:s0:w [color="black", label=""];
-}
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/cmos_01.dot b/yosys/docs/source/APPNOTE_011_Design_Investigation/cmos_01.dot
deleted file mode 100644
index ea6f4403ca8..00000000000
--- a/yosys/docs/source/APPNOTE_011_Design_Investigation/cmos_01.dot
+++ /dev/null
@@ -1,23 +0,0 @@
-digraph "cmos_demo" {
-rankdir="LR";
-remincross=true;
-n4 [ shape=octagon, label="a", color="black", fontcolor="black" ];
-n5 [ shape=octagon, label="b", color="black", fontcolor="black" ];
-n6 [ shape=octagon, label="y[0]", color="black", fontcolor="black" ];
-n7 [ shape=octagon, label="y[1]", color="black", fontcolor="black" ];
-c11 [ shape=record, label="{{<p8> A|<p9> B}|$g0\nNOR|{<p10> Y}}" ];
-c12 [ shape=record, label="{{<p8> A}|$g1\nNOT|{<p10> Y}}" ];
-c13 [ shape=record, label="{{<p8> A}|$g2\nNOT|{<p10> Y}}" ];
-c14 [ shape=record, label="{{<p8> A|<p9> B}|$g3\nNOR|{<p10> Y}}" ];
-c15 [ shape=record, label="{{<p8> A|<p9> B}|$g4\nNOR|{<p10> Y}}" ];
-c11:p10:e -> c15:p8:w [color="black", label=""];
-c12:p10:e -> c14:p8:w [color="black", label=""];
-c13:p10:e -> c14:p9:w [color="black", label=""];
-n4:e -> c11:p9:w [color="black", label=""];
-n4:e -> c13:p8:w [color="black", label=""];
-n5:e -> c11:p8:w [color="black", label=""];
-n5:e -> c12:p8:w [color="black", label=""];
-c15:p10:e -> n6:w [color="black", label=""];
-c14:p10:e -> n7:w [color="black", label=""];
-n7:e -> c15:p9:w [color="black", label=""];
-}
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/example.ys b/yosys/docs/source/APPNOTE_011_Design_Investigation/example.ys
deleted file mode 100644
index b1e956088cc..00000000000
--- a/yosys/docs/source/APPNOTE_011_Design_Investigation/example.ys
+++ /dev/null
@@ -1,11 +0,0 @@
-read_verilog example.v
-show -format dot -prefix example_00
-proc
-show -format dot -prefix example_01
-opt
-show -format dot -prefix example_02
-
-cd example
-select t:$add
-show -format dot -prefix example_03
-
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/example_00.dot b/yosys/docs/source/APPNOTE_011_Design_Investigation/example_00.dot
deleted file mode 100644
index 1e23ed0ead3..00000000000
--- a/yosys/docs/source/APPNOTE_011_Design_Investigation/example_00.dot
+++ /dev/null
@@ -1,23 +0,0 @@
-digraph "example" {
-rankdir="LR";
-remincross=true;
-n4 [ shape=octagon, label="a", color="black", fontcolor="black" ];
-n5 [ shape=octagon, label="b", color="black", fontcolor="black" ];
-n6 [ shape=octagon, label="c", color="black", fontcolor="black" ];
-n7 [ shape=octagon, label="clk", color="black", fontcolor="black" ];
-n8 [ shape=octagon, label="y", color="black", fontcolor="black" ];
-c12 [ shape=record, label="{{<p9> A|<p10> B}|$2\n$add|{<p11> Y}}" ];
-v0 [ label="2'00" ];
-c14 [ shape=record, label="{{<p9> A|<p10> B|<p13> S}|$3\n$mux|{<p11> Y}}" ];
-p1 [shape=box, style=rounded, label="PROC $1\nexample.v:3"];
-c12:p11:e -> c14:p10:w [color="black", style="setlinewidth(3)", label=""];
-c14:p11:e -> p1:w [color="black", style="setlinewidth(3)", label=""];
-n4:e -> c12:p9:w [color="black", label=""];
-n5:e -> c12:p10:w [color="black", label=""];
-n6:e -> c14:p13:w [color="black", label=""];
-n6:e -> p1:w [color="black", label=""];
-n7:e -> p1:w [color="black", label=""];
-p1:e -> n8:w [color="black", style="setlinewidth(3)", label=""];
-n8:e -> p1:w [color="black", style="setlinewidth(3)", label=""];
-v0:e -> c14:p9:w [color="black", style="setlinewidth(3)", label=""];
-}
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/example_01.dot b/yosys/docs/source/APPNOTE_011_Design_Investigation/example_01.dot
deleted file mode 100644
index e89292b51ac..00000000000
--- a/yosys/docs/source/APPNOTE_011_Design_Investigation/example_01.dot
+++ /dev/null
@@ -1,33 +0,0 @@
-digraph "example" {
-rankdir="LR";
-remincross=true;
-n6 [ shape=octagon, label="a", color="black", fontcolor="black" ];
-n7 [ shape=octagon, label="b", color="black", fontcolor="black" ];
-n8 [ shape=octagon, label="c", color="black", fontcolor="black" ];
-n9 [ shape=octagon, label="clk", color="black", fontcolor="black" ];
-n10 [ shape=octagon, label="y", color="black", fontcolor="black" ];
-c14 [ shape=record, label="{{<p11> A|<p12> B}|$2\n$add|{<p13> Y}}" ];
-c18 [ shape=record, label="{{<p15> CLK|<p16> D}|$7\n$dff|{<p17> Q}}" ];
-c20 [ shape=record, label="{{<p11> A|<p12> B|<p19> S}|$5\n$mux|{<p13> Y}}" ];
-v0 [ label="2'00" ];
-c21 [ shape=record, label="{{<p11> A|<p12> B|<p19> S}|$3\n$mux|{<p13> Y}}" ];
-x1 [shape=box, style=rounded, label="BUF"];
-x2 [shape=box, style=rounded, label="BUF"];
-n1 [ shape=diamond, label="$0\\y[1:0]" ];
-x2:e:e -> n1:w [color="black", style="setlinewidth(3)", label=""];
-c18:p17:e -> n10:w [color="black", style="setlinewidth(3)", label=""];
-n10:e -> c20:p11:w [color="black", style="setlinewidth(3)", label=""];
-c14:p13:e -> c21:p12:w [color="black", style="setlinewidth(3)", label=""];
-n3 [ shape=point ];
-c20:p13:e -> n3:w [color="black", style="setlinewidth(3)", label=""];
-n3:e -> c18:p16:w [color="black", style="setlinewidth(3)", label=""];
-n3:e -> x2:w:w [color="black", style="setlinewidth(3)", label=""];
-x1:e:e -> c20:p19:w [color="black", label=""];
-c21:p13:e -> c20:p12:w [color="black", style="setlinewidth(3)", label=""];
-n6:e -> c14:p11:w [color="black", label=""];
-n7:e -> c14:p12:w [color="black", label=""];
-n8:e -> c21:p19:w [color="black", label=""];
-n8:e -> x1:w:w [color="black", label=""];
-n9:e -> c18:p15:w [color="black", label=""];
-v0:e -> c21:p11:w [color="black", style="setlinewidth(3)", label=""];
-}
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/example_02.dot b/yosys/docs/source/APPNOTE_011_Design_Investigation/example_02.dot
deleted file mode 100644
index f950ed2ed2c..00000000000
--- a/yosys/docs/source/APPNOTE_011_Design_Investigation/example_02.dot
+++ /dev/null
@@ -1,20 +0,0 @@
-digraph "example" {
-rankdir="LR";
-remincross=true;
-n3 [ shape=octagon, label="a", color="black", fontcolor="black" ];
-n4 [ shape=octagon, label="b", color="black", fontcolor="black" ];
-n5 [ shape=octagon, label="c", color="black", fontcolor="black" ];
-n6 [ shape=octagon, label="clk", color="black", fontcolor="black" ];
-n7 [ shape=octagon, label="y", color="black", fontcolor="black" ];
-c11 [ shape=record, label="{{<p8> A|<p9> B}|$2\n$add|{<p10> Y}}" ];
-c15 [ shape=record, label="{{<p12> CLK|<p13> D}|$7\n$dff|{<p14> Q}}" ];
-c17 [ shape=record, label="{{<p8> A|<p9> B|<p16> S}|$5\n$mux|{<p10> Y}}" ];
-c17:p10:e -> c15:p13:w [color="black", style="setlinewidth(3)", label=""];
-c11:p10:e -> c17:p9:w [color="black", style="setlinewidth(3)", label=""];
-n3:e -> c11:p8:w [color="black", label=""];
-n4:e -> c11:p9:w [color="black", label=""];
-n5:e -> c17:p16:w [color="black", label=""];
-n6:e -> c15:p12:w [color="black", label=""];
-c15:p14:e -> n7:w [color="black", style="setlinewidth(3)", label=""];
-n7:e -> c17:p8:w [color="black", style="setlinewidth(3)", label=""];
-}
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/example_03.dot b/yosys/docs/source/APPNOTE_011_Design_Investigation/example_03.dot
deleted file mode 100644
index e19d24af78a..00000000000
--- a/yosys/docs/source/APPNOTE_011_Design_Investigation/example_03.dot
+++ /dev/null
@@ -1,11 +0,0 @@
-digraph "example" {
-rankdir="LR";
-remincross=true;
-v0 [ label="a" ];
-v1 [ label="b" ];
-v2 [ label="$2_Y" ];
-c4 [ shape=record, label="{{<p1> A|<p2> B}|$2\n$add|{<p3> Y}}" ];
-v0:e -> c4:p1:w [color="black", label=""];
-v1:e -> c4:p2:w [color="black", label=""];
-c4:p3:e -> v2:w [color="black", style="setlinewidth(3)", label=""];
-}
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/make.sh b/yosys/docs/source/APPNOTE_011_Design_Investigation/make.sh
deleted file mode 100644
index 3845dac6b31..00000000000
--- a/yosys/docs/source/APPNOTE_011_Design_Investigation/make.sh
+++ /dev/null
@@ -1,23 +0,0 @@
-#!/bin/bash
-set -ex
-if false; then
-	rm -f *.dot
-	../../yosys example.ys
-	../../yosys -p 'proc; opt; show -format dot -prefix splice' splice.v
-	../../yosys -p 'techmap; abc -liberty ../../techlibs/cmos/cmos_cells.lib;; show -format dot -prefix cmos_00' cmos.v
-	../../yosys -p 'techmap; splitnets -ports; abc -liberty ../../techlibs/cmos/cmos_cells.lib;; show -lib ../../techlibs/cmos/cmos_cells.v -format dot -prefix cmos_01' cmos.v
-	../../yosys -p 'opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00' sumprod.v
-	../../yosys -p 'opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01' sumprod.v
-	../../yosys -p 'opt; cd sumprod; select prod; show -format dot -prefix sumprod_02' sumprod.v
-	../../yosys -p 'opt; cd sumprod; select prod %ci; show -format dot -prefix sumprod_03' sumprod.v
-	../../yosys -p 'opt; cd sumprod; select prod %ci2; show -format dot -prefix sumprod_04' sumprod.v
-	../../yosys -p 'opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05' sumprod.v
-	../../yosys -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00' memdemo.v
-	../../yosys -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff' memdemo.v
-	../../yosys submod.ys
-	sed -i '/^label=/ d;' *.dot
-fi
-for dot_file in *.dot; do
-	pdf_file=${dot_file%.dot}.pdf
-	dot -Tpdf -o $pdf_file $dot_file
-done
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/memdemo_00.dot b/yosys/docs/source/APPNOTE_011_Design_Investigation/memdemo_00.dot
deleted file mode 100644
index 0336a9aac2a..00000000000
--- a/yosys/docs/source/APPNOTE_011_Design_Investigation/memdemo_00.dot
+++ /dev/null
@@ -1,138 +0,0 @@
-digraph "memdemo" {
-rankdir="LR";
-remincross=true;
-n24 [ shape=octagon, label="clk", color="black", fontcolor="black" ];
-n25 [ shape=octagon, label="d", color="black", fontcolor="black" ];
-n26 [ shape=diamond, label="mem[0]", color="black", fontcolor="black" ];
-n27 [ shape=diamond, label="mem[1]", color="black", fontcolor="black" ];
-n28 [ shape=diamond, label="mem[2]", color="black", fontcolor="black" ];
-n29 [ shape=diamond, label="mem[3]", color="black", fontcolor="black" ];
-n30 [ shape=diamond, label="s1", color="black", fontcolor="black" ];
-n31 [ shape=diamond, label="s2", color="black", fontcolor="black" ];
-n32 [ shape=octagon, label="y", color="black", fontcolor="black" ];
-c36 [ shape=record, label="{{<p33> A|<p34> B}|$28\n$add|{<p35> Y}}" ];
-c37 [ shape=record, label="{{<p33> A|<p34> B}|$31\n$add|{<p35> Y}}" ];
-c38 [ shape=record, label="{{<p33> A|<p34> B}|$34\n$add|{<p35> Y}}" ];
-c39 [ shape=record, label="{{<p33> A|<p34> B}|$37\n$add|{<p35> Y}}" ];
-c41 [ shape=record, label="{{<p33> A|<p34> B|<p40> S}|$110\n$mux|{<p35> Y}}" ];
-x0 [ shape=record, style=rounded, label="<s0> 1:1 - 0:0 " ];
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deleted file mode 100644
index 2ad92c78b2f..00000000000
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deleted file mode 100644
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index 1a672c484f1..00000000000
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diff --git a/yosys/docs/source/CHAPTER_Approach.rst b/yosys/docs/source/CHAPTER_Approach.rst
deleted file mode 100644
index 32980e788bf..00000000000
--- a/yosys/docs/source/CHAPTER_Approach.rst
+++ /dev/null
@@ -1,141 +0,0 @@
-.. _chapter:approach:
-
-Approach
-========
-
-Yosys is a tool for synthesising (behavioural) Verilog HDL code to target
-architecture netlists. Yosys aims at a wide range of application domains and
-thus must be flexible and easy to adapt to new tasks. This chapter covers the
-general approach followed in the effort to implement this tool.
-
-Data- and control-flow
-----------------------
-
-The data- and control-flow of a typical synthesis tool is very similar to the
-data- and control-flow of a typical compiler: different subsystems are called in
-a predetermined order, each consuming the data generated by the last subsystem
-and generating the data for the next subsystem (see :numref:`Fig. %s
-<fig:approach_flow>`).
-
-.. figure:: ../images/approach_flow.*
-	:class: width-helper
-	:name: fig:approach_flow
-
-	General data- and control-flow of a synthesis tool
-
-The first subsystem to be called is usually called a frontend. It does not
-process the data generated by another subsystem but instead reads the user
-input—in the case of a HDL synthesis tool, the behavioural HDL code.
-
-The subsystems that consume data from previous subsystems and produce data for
-the next subsystems (usually in the same or a similar format) are called passes.
-
-The last subsystem that is executed transforms the data generated by the last
-pass into a suitable output format and writes it to a disk file. This subsystem
-is usually called the backend.
-
-In Yosys all frontends, passes and backends are directly available as commands
-in the synthesis script. Thus the user can easily create a custom synthesis flow
-just by calling passes in the right order in a synthesis script.
-
-Internal formats in Yosys
--------------------------
-
-Yosys uses two different internal formats. The first is used to store an
-abstract syntax tree (AST) of a Verilog input file. This format is simply called
-AST and is generated by the Verilog Frontend. This data structure is consumed by
-a subsystem called AST Frontend [1]_. This AST Frontend then generates a design
-in Yosys' main internal format, the
-Register-Transfer-Level-Intermediate-Language (RTLIL) representation. It does
-that by first performing a number of simplifications within the AST
-representation and then generating RTLIL from the simplified AST data structure.
-
-The RTLIL representation is used by all passes as input and outputs. This has
-the following advantages over using different representational formats between
-different passes:
-
--  The passes can be rearranged in a different order and passes can be removed
-   or inserted.
-
--  Passes can simply pass-thru the parts of the design they don't change without
-   the need to convert between formats. In fact Yosys passes output the same
-   data structure they received as input and performs all changes in place.
-
--  All passes use the same interface, thus reducing the effort required to
-   understand a pass when reading the Yosys source code, e.g. when adding
-   additional features.
-
-The RTLIL representation is basically a netlist representation with the
-following additional features:
-
--  An internal cell library with fixed-function cells to represent RTL datapath
-   and register cells as well as logical gate-level cells (single-bit gates and
-   registers).
-
--  Support for multi-bit values that can use individual bits from wires as well
-   as constant bits to represent coarse-grain netlists.
-
--  Support for basic behavioural constructs (if-then-else structures and
-   multi-case switches with a sensitivity list for updating the outputs).
-
--  Support for multi-port memories.
-
-The use of RTLIL also has the disadvantage of having a very powerful format
-between all passes, even when doing gate-level synthesis where the more advanced
-features are not needed. In order to reduce complexity for passes that operate
-on a low-level representation, these passes check the features used in the input
-RTLIL and fail to run when unsupported high-level constructs are used. In such
-cases a pass that transforms the higher-level constructs to lower-level
-constructs must be called from the synthesis script first.
-
-.. _sec:typusecase:
-
-Typical use case
-----------------
-
-The following example script may be used in a synthesis flow to convert the
-behavioural Verilog code from the input file design.v to a gate-level netlist
-synth.v using the cell library described by the Liberty file :
-
-.. code:: yoscrypt
-   :number-lines:
-
-   # read input file to internal representation
-   read_verilog design.v
-
-   # convert high-level behavioral parts ("processes") to d-type flip-flops and muxes
-   proc
-
-   # perform some simple optimizations
-   opt
-
-   # convert high-level memory constructs to d-type flip-flops and multiplexers
-   memory
-
-   # perform some simple optimizations
-   opt
-
-   # convert design to (logical) gate-level netlists
-   techmap
-
-   # perform some simple optimizations
-   opt
-
-   # map internal register types to the ones from the cell library
-   dfflibmap -liberty cells.lib
-
-   # use ABC to map remaining logic to cells from the cell library
-   abc -liberty cells.lib
-
-   # cleanup
-   opt
-
-   # write results to output file
-   write_verilog synth.v
-
-A detailed description of the commands available in Yosys can be found in
-:ref:`cmd_ref`.
-
-.. [1]
-   In Yosys the term pass is only used to refer to commands that operate on the
-   RTLIL data structure.
diff --git a/yosys/docs/source/CHAPTER_Eval.rst b/yosys/docs/source/CHAPTER_Eval.rst
deleted file mode 100644
index 3d463d3f90b..00000000000
--- a/yosys/docs/source/CHAPTER_Eval.rst
+++ /dev/null
@@ -1,233 +0,0 @@
-.. _chapter:eval:
-
-Evaluation, conclusion, future Work
-===================================
-
-The Yosys source tree contains over 200 test cases [1]_ which are used
-in the make test make-target. Besides these there is an external Yosys
-benchmark and test case package that contains a few larger designs .
-This package contains the designs listed in
-Tab. \ `[tab:yosys-test-designs] <#tab:yosys-test-designs>`__.
-
-.. table:: Tests included in the yosys-tests package.
-
-   =========== ========= ================
-   ======================================================
-   Test-Design Source    Gates            Description / Comments
-   =========== ========= ================
-   ======================================================
-   aes_core    IWLS2005  :math:`41{,}837` AES Cipher written by Rudolf Usselmann
-   i2c         IWLS2005  :math:`1{,}072`  WISHBONE compliant I2C Master by Richard Herveille
-   openmsp430  OpenCores :math:`7{,}173`  MSP430 compatible CPU by Olivier Girard
-   or1200      OpenCores :math:`42{,}675` The OpenRISC 1200 CPU by Damjan Lampret
-   sasc        IWLS2005  :math:`456`      Simple Async. Serial Comm. Device by Rudolf Usselmann
-   simple_spi  IWLS2005  :math:`690`      MC68HC11E based SPI interface by Richard Herveille
-   spi         IWLS2005  :math:`2{,}478`  SPI IP core by Simon Srot
-   ss_pcm      IWLS2005  :math:`279`      PCM IO Slave by Rudolf Usselmann
-   systemcaes  IWLS2005  :math:`6{,}893`  AES core (using SystemC to Verilog) by Javier Castillo
-   usb_phy     IWLS2005  :math:`515`      USB 1.1 PHY by Rudolf Usselmann
-   =========== ========= ================
-   ======================================================
-
-Correctness of synthesis results
---------------------------------
-
-The following measures were taken to increase the confidence in the
-correctness of the Yosys synthesis results:
-
--  Yosys comes with a large selection [2]_ of small test cases that are
-   evaluated when the command make test is executed. During development
-   of Yosys it was shown that this collection of test cases is
-   sufficient to catch most bugs. The following more sophisticated test
-   procedures only caught a few additional bugs. Whenever this happened,
-   an appropriate test case was added to the collection of small test
-   cases for make test to ensure better testability of the feature in
-   question in the future.
-
--  The designs listed in
-   Tab. \ `[tab:yosys-test-designs] <#tab:yosys-test-designs>`__ where
-   validated using the formal verification tool Synopsys Formality. The
-   Yosys synthesis scripts used to synthesize the individual designs for
-   this test are slightly different per design in order to broaden the
-   coverage of Yosys features. The large majority of all errors
-   encountered using these tests are false-negatives, mostly related to
-   FSM encoding or signal naming in large array logic (such as in memory
-   blocks). Therefore the fsm_recode pass was extended so it can be used
-   to generate TCL commands for Synopsys Formality that describe the
-   relationship between old and new state encodings. Also the method
-   used to generate signal and cell names in the Verilog backend was
-   slightly modified in order to improve the automatic matching of net
-   names in Synopsys Formality. With these changes in place all designs
-   in Tab. \ `[tab:yosys-test-designs] <#tab:yosys-test-designs>`__
-   validate successfully using Formality.
-
--  VlogHammer is a set of scripts that auto-generate a large collection
-   of test cases [3]_ and synthesize them using Yosys and the following
-   freely available proprietary synthesis tools.
-
-   -  Xilinx Vivado WebPack (2013.2)
-
-   -  Xilinx ISE (XST) WebPack (14.5)
-
-   -  Altera Quartus II Web Edition (13.0)
-
-   The built-in SAT solver of Yosys is used to formally verify the Yosys
-   RTL- and Gate-Level netlists against the netlists generated by this
-   other tools. [4]_ When differences are found, the input pattern that
-   result in different outputs are used for simulating the original
-   Verilog code as well as the synthesis results using the following
-   Verilog simulators.
-
-   -  Xilinx ISIM (from Xilinx ISE 14.5 )
-
-   -  Modelsim 10.1d (from Quartus II 13.0 )
-
-   -  Icarus Verilog (no specific version)
-
-   The set of tests performed by VlogHammer systematically verify the
-   correct behaviour of
-
-   -  Yosys Verilog Frontend and RTL generation
-
-   -  Yosys Gate-Level Technology Mapping
-
-   -  Yosys SAT Models for RTL- and Gate-Level cells
-
-   -  Yosys Constant Evaluator Models for RTL- and Gate-Level cells
-
-   against the reference provided by the other tools. A few bugs related
-   to sign extensions and bit-width extensions where found (and have
-   been fixed meanwhile) using this approach. This test also revealed a
-   small number of bugs in the other tools (i.e. Vivado, XST, Quartus,
-   ISIM and Icarus Verilog; no bugs where found in Modelsim using
-   vlogHammer so far).
-
-Although complex software can never be expected to be fully bug-free
-:cite:p:`MURPHY`, it has been shown that Yosys is mature and
-feature-complete enough to handle most real-world cases correctly.
-
-Quality of synthesis results
-----------------------------
-
-In this section an attempt to evaluate the quality of Yosys synthesis
-results is made. To this end the synthesis results of a commercial FPGA
-synthesis tool when presented with the original HDL code vs. when
-presented with the Yosys synthesis result are compared.
-
-The OpenMSP430 and the OpenRISC 1200 test cases were synthesized using
-the following Yosys synthesis script:
-
-::
-
-   hierarchy -check
-   proc; opt; fsm; opt; memory; opt
-   techmap; opt; abc; opt
-
-The original RTL and the Yosys output where both passed to the Xilinx
-XST 14.5 FPGA synthesis tool. The following setting where used for XST:
-
-::
-
-   -p artix7
-   -use_dsp48 NO
-   -iobuf NO
-   -ram_extract NO
-   -rom_extract NO
-   -fsm_extract YES
-   -fsm_encoding Auto
-
-The results of this comparison is summarized in
-Tab. \ `[tab:synth-test] <#tab:synth-test>`__. The used FPGA resources
-(registers and LUTs) and performance (maximum frequency as reported by
-XST) are given per module (indentation indicates module hierarchy, the
-numbers are including all contained modules).
-
-For most modules the results are very similar between XST and Yosys. XST
-is used in both cases for the final mapping of logic to LUTs. So this
-comparison only compares the high-level synthesis functions (such as FSM
-extraction and encoding) of Yosys and XST.
-
-.. table:: Synthesis results (as reported by XST) for OpenMSP430 and
-OpenRISC 1200
-
-   ============================ ==== ==== ========== ==== =====
-   ==========
-   \                                                           
-   Module                       Regs LUTs Max. Freq. Regs LUTs  Max. Freq.
-   openMSP430                   689  2210 71 MHz     719  2779  53 MHz
-   1em omsp_clock_module        21   30   645 MHz    21   30    644 MHz
-   1em 1em omsp_sync_cell       2    —    1542 MHz   2    —     1542 MHz
-   1em 1em omsp_sync_reset      2    —    1542 MHz   2    —     1542 MHz
-   1em omsp_dbg                 143  344  292 MHz    149  430   353 MHz
-   1em 1em omsp_dbg_uart        76   135  377 MHz    79   139   389 MHz
-   1em omsp_execution_unit      266  911  80 MHz     266  1034  137 MHz
-   1em 1em omsp_alu             —    202  —          —    263   —
-   1em 1em omsp_register_file   231  478  285 MHz    231  506   293 MHz
-   1em omsp_frontend            115  340  178 MHz    118  527   206 MHz
-   1em omsp_mem_backbone        38   141  1087 MHz   38   144   1087 MHz
-   1em omsp_multiplier          73   397  129 MHz    102  1053  55 MHz
-   1em omsp_sfr                 6    18   1023 MHz   6    20    1023 MHz
-   1em omsp_watchdog            24   53   362 MHz    24   70    360 MHz
-   or1200_top                   7148 9969 135 MHz    7173 10238 108 MHz
-   1em or1200_alu               —    681  —          —    641   —
-   1em or1200_cfgr              —    11   —          —    11    —
-   1em or1200_ctrl              175  186  464 MHz    174  279   377 MHz
-   1em or1200_except            241  451  313 MHz    241  353   301 MHz
-   1em or1200_freeze            6    18   507 MHz    6    16    515 MHz
-   1em or1200_if                68   143  806 MHz    68   139   790 MHz
-   1em or1200_lsu               8    138  —          12   205   1306 MHz
-   1em 1em or1200_mem2reg       —    60   —          —    66    —
-   1em 1em or1200_reg2mem       —    29   —          —    29    —
-   1em or1200_mult_mac          394  2209 240 MHz    394  2230  241 MHz
-   1em 1em or1200_amultp2_32x32 256  1783 240 MHz    256  1770  241 MHz
-   1em or1200_operandmuxes      65   129  1145 MHz   65   129   1145 MHz
-   1em or1200_rf                1041 1722 822 MHz    1042 1722  581 MHz
-   1em or1200_sprs              18   432  724 MHz    18   469   722 MHz
-   1em or1200_wbmux             33   93   —          33   78    —
-   1em or1200_dc_top            —    5    —          —    5     —
-   1em or1200_dmmu_top          2445 1004 —          2445 1043  —
-   1em 1em or1200_dmmu_tlb      2444 975  —          2444 1013  —
-   1em or1200_du                67   56   859 MHz    67   56    859 MHz
-   1em or1200_ic_top            39   100  527 MHz    41   136   514 MHz
-   1em 1em or1200_ic_fsm        40   42   408 MHz    40   75    484 MHz
-   1em or1200_pic               38   50   1169 MHz   38   50    1177 MHz
-   1em or1200_tt                64   112  370 MHz    64   186   437 MHz
-   ============================ ==== ==== ========== ==== =====
-   ==========
-
-Conclusion and future Work
---------------------------
-
-Yosys is capable of correctly synthesizing real-world Verilog designs.
-The generated netlists are of a decent quality. However, in cases where
-dedicated hardware resources should be used for certain functions it is
-of course necessary to implement proper technology mapping for these
-functions in Yosys. This can be as easy as calling the techmap pass with
-an architecture-specific mapping file in the synthesis script. As no
-such thing has been done in the above tests, it is only natural that the
-resulting designs cannot benefit from these dedicated hardware
-resources.
-
-Therefore future work includes the implementation of
-architecture-specific technology mappings besides additional frontends
-(VHDL), backends (EDIF), and above all else, application specific
-passes. After all, this was the main motivation for the development of
-Yosys in the first place.
-
-.. [1]
-   Most of this test cases are copied from HANA or the ASIC-WORLD
-   website .
-
-.. [2]
-   At the time of this writing 269 test cases.
-
-.. [3]
-   At the time of this writing over 6600 test cases.
-
-.. [4]
-   A SAT solver is a program that can solve the boolean satisfiability
-   problem. The built-in SAT solver in Yosys can be used for formal
-   equivalence checking, amongst other things. See
-   Sec. \ \ `[cmd:sat] <#cmd:sat>`__ for details.
-
-.. footbibliography::
diff --git a/yosys/docs/source/CHAPTER_Intro.rst b/yosys/docs/source/CHAPTER_Intro.rst
deleted file mode 100644
index 90b001c2312..00000000000
--- a/yosys/docs/source/CHAPTER_Intro.rst
+++ /dev/null
@@ -1,96 +0,0 @@
-.. _chapter:intro:
-
-Introduction
-============
-
-This document presents the Free and Open Source (FOSS) Verilog HDL synthesis
-tool "Yosys". Its design and implementation as well as its performance on
-real-world designs is discussed in this document.
-
-History of Yosys
-----------------
-
-A Hardware Description Language (HDL) is a computer language used to describe
-circuits. A HDL synthesis tool is a computer program that takes a formal
-description of a circuit written in an HDL as input and generates a netlist that
-implements the given circuit as output.
-
-Currently the most widely used and supported HDLs for digital circuits are
-Verilog :cite:p:`Verilog2005,VerilogSynth` and :abbr:`VHDL (VHSIC HDL, where
-VHSIC is an acronym for Very-High-Speed Integrated Circuits)`
-:cite:p:`VHDL,VHDLSynth`. Both HDLs are used for test and verification purposes
-as well as logic synthesis, resulting in a set of synthesizable and a set of
-non-synthesizable language features. In this document we only look at the
-synthesizable subset of the language features.
-
-In recent work on heterogeneous coarse-grain reconfigurable logic
-:cite:p:`intersynth` the need for a custom application-specific HDL synthesis
-tool emerged. It was soon realised that a synthesis tool that understood Verilog
-or VHDL would be preferred over a synthesis tool for a custom HDL. Given an
-existing Verilog or VHDL front end, the work for writing the necessary
-additional features and integrating them in an existing tool can be estimated to
-be about the same as writing a new tool with support for a minimalistic custom
-HDL.
-
-The proposed custom HDL synthesis tool should be licensed under a Free and Open
-Source Software (FOSS) licence. So an existing FOSS Verilog or VHDL synthesis
-tool would have been needed as basis to build upon. The main advantages of
-choosing Verilog or VHDL is the ability to synthesize existing HDL code and to
-mitigate the requirement for circuit-designers to learn a new language. In order
-to take full advantage of any existing FOSS Verilog or VHDL tool, such a tool
-would have to provide a feature-complete implementation of the synthesizable HDL
-subset.
-
-Basic RTL synthesis is a well understood field :cite:p:`LogicSynthesis`. Lexing,
-parsing and processing of computer languages :cite:p:`Dragonbook` is a
-thoroughly researched field. All the information required to write such tools
-has been openly available for a long time, and it is therefore likely that a
-FOSS HDL synthesis tool with a feature-complete Verilog or VHDL front end must
-exist which can be used as a basis for a custom RTL synthesis tool.
-
-Due to the author's preference for Verilog over VHDL it was decided early on to
-go for Verilog instead of VHDL [#]_. So the existing FOSS Verilog synthesis
-tools were evaluated. The results of this evaluation are utterly devastating.
-Therefore a completely new Verilog synthesis tool was implemented and is
-recommended as basis for custom synthesis tools. This is the tool that is
-discussed in this document.
-
-Structure of this document
---------------------------
-
-The structure of this document is as follows:
-
-:numref:`Chapter %s <chapter:intro>` is this introduction.
-
-:numref:`Chapter %s <chapter:basics>` covers a short introduction to the world
-of HDL synthesis. Basic principles and the terminology are outlined in this
-chapter.
-
-:numref:`Chapter %s <chapter:approach>` gives the quickest possible outline to
-how the problem of implementing a HDL synthesis tool is approached in the case
-of Yosys.
-
-:numref:`Chapter %s <chapter:overview>` contains a more detailed overview of the
-implementation of Yosys. This chapter covers the data structures used in Yosys
-to represent a design in detail and is therefore recommended reading for
-everyone who is interested in understanding the Yosys internals.
-
-:numref:`Chapter %s <chapter:celllib>` covers the internal cell library used by
-Yosys. This is especially important knowledge for anyone who wants to understand
-the intermediate netlists used internally by Yosys.
-
-:numref:`Chapter %s <chapter:prog>` gives a tour to the internal APIs of Yosys.
-This is recommended reading for everyone who actually wants to read or write
-Yosys source code. The chapter concludes with an example loadable module for
-Yosys.
-
-Chapters :numref:`%s <chapter:verilog>`, :numref:`%s <chapter:opt>` and
-:numref:`%s <chapter:techmap>` cover three important pieces of the synthesis
-pipeline: The Verilog frontend, the optimization passes and the technology
-mapping to the target architecture, respectively.
-
-Various appendices, including a :ref:`cmd_ref`, complete this document.
-
-.. [#]
-   A quick investigation into FOSS VHDL tools yielded similar grim results for
-   FOSS VHDL synthesis tools.
diff --git a/yosys/docs/source/CHAPTER_Optimize.rst b/yosys/docs/source/CHAPTER_Optimize.rst
deleted file mode 100644
index 53e0a67aa09..00000000000
--- a/yosys/docs/source/CHAPTER_Optimize.rst
+++ /dev/null
@@ -1,330 +0,0 @@
-.. _chapter:opt:
-
-Optimizations
-=============
-
-Yosys employs a number of optimizations to generate better and cleaner results.
-This chapter outlines these optimizations.
-
-Simple optimizations
---------------------
-
-The Yosys pass opt runs a number of simple optimizations. This includes removing
-unused signals and cells and const folding. It is recommended to run this pass
-after each major step in the synthesis script. At the time of this writing the
-opt pass executes the following passes that each perform a simple optimization:
-
--  Once at the beginning of opt:
-
-   -  opt_expr
-   -  opt_merge -nomux
-
--  Repeat until result is stable:
-
-   -  opt_muxtree
-   -  opt_reduce
-   -  opt_merge
-   -  opt_rmdff
-   -  opt_clean
-   -  opt_expr
-
-The following section describes each of the opt\_ passes.
-
-The opt_expr pass
-~~~~~~~~~~~~~~~~~
-
-This pass performs const folding on the internal combinational cell types
-described in :numref:`Chap. %s <chapter:celllib>`. This means a cell with all
-constant inputs is replaced with the constant value this cell drives. In some
-cases this pass can also optimize cells with some constant inputs.
-
-.. table:: Const folding rules for $_AND\_ cells as used in opt_expr.
-   :name: tab:opt_expr_and
-   :align: center
-
-   ========= ========= ===========
-   A-Input   B-Input   Replacement
-   ========= ========= ===========
-   any       0         0
-   0         any       0
-   1         1         1
-   --------- --------- -----------
-   X/Z       X/Z       X
-   1         X/Z       X
-   X/Z       1         X
-   --------- --------- -----------
-   any       X/Z       0
-   X/Z       any       0
-   --------- --------- -----------
-   :math:`a` 1         :math:`a`
-   1         :math:`b` :math:`b`
-   ========= ========= ===========
-
-.. How to format table?
-
-:numref:`Table %s <tab:opt_expr_and>` shows the replacement rules used for
-optimizing an $_AND\_ gate. The first three rules implement the obvious const
-folding rules. Note that ‘any' might include dynamic values calculated by other
-parts of the circuit. The following three lines propagate undef (X) states.
-These are the only three cases in which it is allowed to propagate an undef
-according to Sec. 5.1.10 of IEEE Std. 1364-2005 :cite:p:`Verilog2005`.
-
-The next two lines assume the value 0 for undef states. These two rules are only
-used if no other substitutions are possible in the current module. If other
-substitutions are possible they are performed first, in the hope that the ‘any'
-will change to an undef value or a 1 and therefore the output can be set to
-undef.
-
-The last two lines simply replace an $_AND\_ gate with one constant-1 input with
-a buffer.
-
-Besides this basic const folding the opt_expr pass can replace 1-bit wide $eq
-and $ne cells with buffers or not-gates if one input is constant.
-
-The opt_expr pass is very conservative regarding optimizing $mux cells, as these
-cells are often used to model decision-trees and breaking these trees can
-interfere with other optimizations.
-
-The opt_muxtree pass
-~~~~~~~~~~~~~~~~~~~~
-
-This pass optimizes trees of multiplexer cells by analyzing the select inputs.
-Consider the following simple example:
-
-.. code:: verilog
-   :number-lines:
-
-   module uut(a, y); input a; output [1:0] y = a ? (a ? 1 : 2) : 3; endmodule
-
-The output can never be 2, as this would require ``a`` to be 1 for the outer
-multiplexer and 0 for the inner multiplexer. The opt_muxtree pass detects this
-contradiction and replaces the inner multiplexer with a constant 1, yielding the
-logic for ``y = a ? 1 : 3``.
-
-The opt_reduce pass
-~~~~~~~~~~~~~~~~~~~
-
-This is a simple optimization pass that identifies and consolidates identical
-input bits to $reduce_and and $reduce_or cells. It also sorts the input bits to
-ease identification of shareable $reduce_and and $reduce_or cells in other
-passes.
-
-This pass also identifies and consolidates identical inputs to multiplexer
-cells. In this case the new shared select bit is driven using a $reduce_or cell
-that combines the original select bits.
-
-Lastly this pass consolidates trees of $reduce_and cells and trees of $reduce_or
-cells to single large $reduce_and or $reduce_or cells.
-
-These three simple optimizations are performed in a loop until a stable result
-is produced.
-
-The opt_rmdff pass
-~~~~~~~~~~~~~~~~~~
-
-This pass identifies single-bit d-type flip-flops ($_DFF\_, $dff, and $adff
-cells) with a constant data input and replaces them with a constant driver.
-
-The opt_clean pass
-~~~~~~~~~~~~~~~~~~
-
-This pass identifies unused signals and cells and removes them from the design.
-It also creates an ``\unused_bits`` attribute on wires with unused bits. This
-attribute can be used for debugging or by other optimization passes.
-
-The opt_merge pass
-~~~~~~~~~~~~~~~~~~
-
-This pass performs trivial resource sharing. This means that this pass
-identifies cells with identical inputs and replaces them with a single instance
-of the cell.
-
-The option -nomux can be used to disable resource sharing for multiplexer cells
-($mux and $pmux. This can be useful as it prevents multiplexer trees to be
-merged, which might prevent opt_muxtree to identify possible optimizations.
-
-FSM extraction and encoding
----------------------------
-
-The fsm pass performs finite-state-machine (FSM) extraction and recoding. The
-fsm pass simply executes the following other passes:
-
--  Identify and extract FSMs:
-
-   -  fsm_detect
-   -  fsm_extract
-
--  Basic optimizations:
-
-   -  fsm_opt
-   -  opt_clean
-   -  fsm_opt
-
--  Expanding to nearby gate-logic (if called with -expand):
-
-   -  fsm_expand
-   -  opt_clean
-   -  fsm_opt
-
--  Re-code FSM states (unless called with -norecode):
-
-   -  fsm_recode
-
--  Print information about FSMs:
-
-   -  fsm_info
-
--  Export FSMs in KISS2 file format (if called with -export):
-
-   -  fsm_export
-
--  Map FSMs to RTL cells (unless called with -nomap):
-
-   -  fsm_map
-
-The fsm_detect pass identifies FSM state registers and marks them using the
-``\fsm_encoding = "auto"`` attribute. The fsm_extract extracts all FSMs marked
-using the ``\fsm_encoding`` attribute (unless ``\fsm_encoding`` is set to
-"none") and replaces the corresponding RTL cells with a $fsm cell. All other
-fsm\_ passes operate on these $fsm cells. The fsm_map call finally replaces the
-$fsm cells with RTL cells.
-
-Note that these optimizations operate on an RTL netlist. I.e. the fsm pass
-should be executed after the proc pass has transformed all RTLIL::Process
-objects to RTL cells.
-
-The algorithms used for FSM detection and extraction are influenced by a more
-general reported technique :cite:p:`fsmextract`.
-
-FSM detection
-~~~~~~~~~~~~~
-
-The fsm_detect pass identifies FSM state registers. It sets the ``\fsm_encoding
-= "auto"`` attribute on any (multi-bit) wire that matches the following
-description:
-
--  Does not already have the ``\fsm_encoding`` attribute.
--  Is not an output of the containing module.
--  Is driven by single $dff or $adff cell.
--  The ``\D``-Input of this $dff or $adff cell is driven by a multiplexer tree
-   that only has constants or the old state value on its leaves.
--  The state value is only used in the said multiplexer tree or by simple
-   relational cells that compare the state value to a constant (usually $eq
-   cells).
-
-This heuristic has proven to work very well. It is possible to overwrite it by
-setting ``\fsm_encoding = "auto"`` on registers that should be considered FSM
-state registers and setting ``\fsm_encoding = "none"`` on registers that match
-the above criteria but should not be considered FSM state registers.
-
-Note however that marking state registers with ``\fsm_encoding`` that are not
-suitable for FSM recoding can cause synthesis to fail or produce invalid
-results.
-
-FSM extraction
-~~~~~~~~~~~~~~
-
-The fsm_extract pass operates on all state signals marked with the
-(``\fsm_encoding != "none"``) attribute. For each state signal the following
-information is determined:
-
--  The state registers
-
--  The asynchronous reset state if the state registers use asynchronous reset
-
--  All states and the control input signals used in the state transition
-   functions
-
--  The control output signals calculated from the state signals and control
-   inputs
-
--  A table of all state transitions and corresponding control inputs- and
-   outputs
-
-The state registers (and asynchronous reset state, if applicable) is simply
-determined by identifying the driver for the state signal.
-
-From there the $mux-tree driving the state register inputs is recursively
-traversed. All select inputs are control signals and the leaves of the $mux-tree
-are the states. The algorithm fails if a non-constant leaf that is not the state
-signal itself is found.
-
-The list of control outputs is initialized with the bits from the state signal.
-It is then extended by adding all values that are calculated by cells that
-compare the state signal with a constant value.
-
-In most cases this will cover all uses of the state register, thus rendering the
-state encoding arbitrary. If however a design uses e.g. a single bit of the
-state value to drive a control output directly, this bit of the state signal
-will be transformed to a control output of the same value.
-
-Finally, a transition table for the FSM is generated. This is done by using the
-ConstEval C++ helper class (defined in kernel/consteval.h) that can be used to
-evaluate parts of the design. The ConstEval class can be asked to calculate a
-given set of result signals using a set of signal-value assignments. It can also
-be passed a list of stop-signals that abort the ConstEval algorithm if the value
-of a stop-signal is needed in order to calculate the result signals.
-
-The fsm_extract pass uses the ConstEval class in the following way to create a
-transition table. For each state:
-
-1. Create a ConstEval object for the module containing the FSM
-2. Add all control inputs to the list of stop signals
-3. Set the state signal to the current state
-4. Try to evaluate the next state and control output
-5. If step 4 was not successful:
-   
-   -  Recursively goto step 4 with the offending stop-signal set to 0.
-   -  Recursively goto step 4 with the offending stop-signal set to 1.
-
-6. If step 4 was successful: Emit transition
-
-Finally a $fsm cell is created with the generated transition table and added to
-the module. This new cell is connected to the control signals and the old
-drivers for the control outputs are disconnected.
-
-FSM optimization
-~~~~~~~~~~~~~~~~
-
-The fsm_opt pass performs basic optimizations on $fsm cells (not including state
-recoding). The following optimizations are performed (in this order):
-
--  Unused control outputs are removed from the $fsm cell. The attribute
-   ``\unused_bits`` (that is usually set by the opt_clean pass) is used to
-   determine which control outputs are unused.
-
--  Control inputs that are connected to the same driver are merged.
-
--  When a control input is driven by a control output, the control input is
-   removed and the transition table altered to give the same performance without
-   the external feedback path.
-
--  Entries in the transition table that yield the same output and only differ in
-   the value of a single control input bit are merged and the different bit is
-   removed from the sensitivity list (turned into a don't-care bit).
-
--  Constant inputs are removed and the transition table is altered to give an
-   unchanged behaviour.
-
--  Unused inputs are removed.
-
-FSM recoding
-~~~~~~~~~~~~
-
-The fsm_recode pass assigns new bit pattern to the states. Usually this also
-implies a change in the width of the state signal. At the moment of this writing
-only one-hot encoding with all-zero for the reset state is supported.
-
-The fsm_recode pass can also write a text file with the changes performed by it
-that can be used when verifying designs synthesized by Yosys using Synopsys
-Formality .
-
-Logic optimization
-------------------
-
-Yosys can perform multi-level combinational logic optimization on gate-level
-netlists using the external program ABC . The abc pass extracts the
-combinational gate-level parts of the design, passes it through ABC, and
-re-integrates the results. The abc pass can also be used to perform other
-operations using ABC, such as technology mapping (see :numref:`Sec %s
-<sec:techmap_extern>` for details).
diff --git a/yosys/docs/source/CHAPTER_Overview.rst b/yosys/docs/source/CHAPTER_Overview.rst
deleted file mode 100644
index 10d2ce47840..00000000000
--- a/yosys/docs/source/CHAPTER_Overview.rst
+++ /dev/null
@@ -1,571 +0,0 @@
-.. _chapter:overview:
-
-Implementation overview
-=======================
-
-Yosys is an extensible open source hardware synthesis tool. It is aimed at
-designers who are looking for an easily accessible, universal, and
-vendor-independent synthesis tool, as well as scientists who do research in
-electronic design automation (EDA) and are looking for an open synthesis
-framework that can be used to test algorithms on complex real-world designs.
-
-Yosys can synthesize a large subset of Verilog 2005 and has been tested with a
-wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the
-`openMSP430 CPU`_, the `OpenCores I2C master`_, and the `k68 CPU`_.
-
-.. _OpenRISC 1200 CPU: https://github.com/openrisc/or1200
-
-.. _openMSP430 CPU: http://opencores.org/projects/openmsp430
-
-.. _OpenCores I2C master: http://opencores.org/projects/i2c
-
-.. _k68 CPU: http://opencores.org/projects/k68
-
-As of this writing a Yosys VHDL frontend is in development.
-
-Yosys is written in C++ (using some features from the new C++11 standard). This
-chapter describes some of the fundamental Yosys data structures. For the sake of
-simplicity the C++ type names used in the Yosys implementation are used in this
-chapter, even though the chapter only explains the conceptual idea behind it and
-can be used as reference to implement a similar system in any language.
-
-Simplified data flow
---------------------
-
-:numref:`Figure %s <fig:Overview_flow>` shows the simplified data flow within
-Yosys. Rectangles in the figure represent program modules and ellipses internal
-data structures that are used to exchange design data between the program
-modules.
-
-Design data is read in using one of the frontend modules. The high-level HDL
-frontends for Verilog and VHDL code generate an abstract syntax tree (AST) that
-is then passed to the AST frontend. Note that both HDL frontends use the same
-AST representation that is powerful enough to cover the Verilog HDL and VHDL
-language.
-
-The AST Frontend then compiles the AST to Yosys's main internal data format, the
-RTL Intermediate Language (RTLIL). A more detailed description of this format is
-given in the next section.
-
-There is also a text representation of the RTLIL data structure that can be
-parsed using the RTLIL Frontend.
-
-The design data may then be transformed using a series of passes that all
-operate on the RTLIL representation of the design.
-
-Finally the design in RTLIL representation is converted back to text by one of
-the backends, namely the Verilog Backend for generating Verilog netlists and the
-RTLIL Backend for writing the RTLIL data in the same format that is understood
-by the RTLIL Frontend.
-
-With the exception of the AST Frontend, which is called by the high-level HDL
-frontends and can't be called directly by the user, all program modules are
-called by the user (usually using a synthesis script that contains text commands
-for Yosys).
-
-By combining passes in different ways and/or adding additional passes to Yosys
-it is possible to adapt Yosys to a wide range of applications. For this to be
-possible it is key that (1) all passes operate on the same data structure
-(RTLIL) and (2) that this data structure is powerful enough to represent the
-design in different stages of the synthesis.
-
-.. figure:: ../images/overview_flow.*
-	:class: width-helper
-	:name: fig:Overview_flow
-
-	Yosys simplified data flow (ellipses: data structures, rectangles:
-	program modules)
-
-The RTL Intermediate Language (RTLIL)
--------------------------------------
-
-All frontends, passes and backends in Yosys operate on a design in RTLIL
-representation. The only exception are the high-level frontends that use the AST
-representation as an intermediate step before generating RTLIL data.
-
-In order to avoid reinventing names for the RTLIL classes, they are simply
-referred to by their full C++ name, i.e. including the RTLIL:: namespace prefix,
-in this document.
-
-:numref:`Figure %s <fig:Overview_RTLIL>` shows a simplified Entity-Relationship
-Diagram (ER Diagram) of RTLIL. In :math:`1:N` relationships the arrow points
-from the :math:`N` side to the :math:`1`. For example one RTLIL::Design contains
-:math:`N` (zero to many) instances of RTLIL::Module. A two-pointed arrow
-indicates a :math:`1:1` relationship.
-
-The RTLIL::Design is the root object of the RTLIL data structure. There is
-always one "current design" in memory which passes operate on, frontends add
-data to and backends convert to exportable formats. But in some cases passes
-internally generate additional RTLIL::Design objects. For example when a pass is
-reading an auxiliary Verilog file such as a cell library, it might create an
-additional RTLIL::Design object and call the Verilog frontend with this other
-object to parse the cell library.
-
-.. figure:: ../images/overview_rtlil.*
-	:class: width-helper
-	:name: fig:Overview_RTLIL
-
-	Simplified RTLIL Entity-Relationship Diagram
-
-There is only one active RTLIL::Design object that is used by all frontends,
-passes and backends called by the user, e.g. using a synthesis script. The
-RTLIL::Design then contains zero to many RTLIL::Module objects. This corresponds
-to modules in Verilog or entities in VHDL. Each module in turn contains objects
-from three different categories:
-
--  RTLIL::Cell and RTLIL::Wire objects represent classical netlist data.
-
--  RTLIL::Process objects represent the decision trees (if-then-else statements,
-   etc.) and synchronization declarations (clock signals and sensitivity) from
-   Verilog always and VHDL process blocks.
-
--  RTLIL::Memory objects represent addressable memories (arrays).
-
-Usually the output of the synthesis procedure is a netlist, i.e. all
-RTLIL::Process and RTLIL::Memory objects must be replaced by RTLIL::Cell and
-RTLIL::Wire objects by synthesis passes.
-
-All features of the HDL that cannot be mapped directly to these RTLIL classes
-must be transformed to an RTLIL-compatible representation by the HDL frontend.
-This includes Verilog-features such as generate-blocks, loops and parameters.
-
-The following sections contain a more detailed description of the different
-parts of RTLIL and rationale behind some of the design decisions.
-
-RTLIL identifiers
-~~~~~~~~~~~~~~~~~
-
-All identifiers in RTLIL (such as module names, port names, signal names, cell
-types, etc.) follow the following naming convention: they must either start with
-a backslash (\) or a dollar sign ($).
-
-Identifiers starting with a backslash are public visible identifiers. Usually
-they originate from one of the HDL input files. For example the signal name
-"\\sig42" is most likely a signal that was declared using the name "sig42" in an
-HDL input file. On the other hand the signal name "$sig42" is an auto-generated
-signal name. The backends convert all identifiers that start with a dollar sign
-to identifiers that do not collide with identifiers that start with a backslash.
-
-This has three advantages:
-
--  First, it is impossible that an auto-generated identifier collides with an
-   identifier that was provided by the user.
-
--  Second, the information about which identifiers were originally provided by
-   the user is always available which can help guide some optimizations. For
-   example the "opt_rmunused" tries to preserve signals with a user-provided
-   name but doesn't hesitate to delete signals that have auto-generated names
-   when they just duplicate other signals.
-
--  Third, the delicate job of finding suitable auto-generated public visible
-   names is deferred to one central location. Internally auto-generated names
-   that may hold important information for Yosys developers can be used without
-   disturbing external tools. For example the Verilog backend assigns names in
-   the form \_integer\_.
-
-Whitespace and control characters (any character with an ASCII code 32 or less)
-are not allowed in RTLIL identifiers; most frontends and backends cannot support
-these characters in identifiers.
-
-In order to avoid programming errors, the RTLIL data structures check if all
-identifiers start with either a backslash or a dollar sign, and contain no
-whitespace or control characters. Violating these rules results in a runtime
-error.
-
-All RTLIL identifiers are case sensitive.
-
-Some transformations, such as flattening, may have to change identifiers
-provided by the user to avoid name collisions. When that happens, attribute
-"hdlname" is attached to the object with the changed identifier. This attribute
-contains one name (if emitted directly by the frontend, or is a result of
-disambiguation) or multiple names separated by spaces (if a result of
-flattening). All names specified in the "hdlname" attribute are public and do
-not include the leading "\".
-
-RTLIL::Design and RTLIL::Module
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The RTLIL::Design object is basically just a container for RTLIL::Module
-objects. In addition to a list of RTLIL::Module objects the RTLIL::Design also
-keeps a list of selected objects, i.e. the objects that passes should operate
-on. In most cases the whole design is selected and therefore passes operate on
-the whole design. But this mechanism can be useful for more complex synthesis
-jobs in which only parts of the design should be affected by certain passes.
-
-Besides the objects shown in the ER diagram in :numref:`Fig. %s
-<fig:Overview_RTLIL>` an RTLIL::Module object contains the following additional
-properties:
-
--  The module name
--  A list of attributes
--  A list of connections between wires
--  An optional frontend callback used to derive parametrized variations of the
-   module
-
-The attributes can be Verilog attributes imported by the Verilog frontend or
-attributes assigned by passes. They can be used to store additional metadata
-about modules or just mark them to be used by certain part of the synthesis
-script but not by others.
-
-Verilog and VHDL both support parametric modules (known as "generic entities" in
-VHDL). The RTLIL format does not support parametric modules itself. Instead each
-module contains a callback function into the AST frontend to generate a
-parametrized variation of the RTLIL::Module as needed. This callback then
-returns the auto-generated name of the parametrized variation of the module. (A
-hash over the parameters and the module name is used to prohibit the same
-parametrized variation from being generated twice. For modules with only a few
-parameters, a name directly containing all parameters is generated instead of a
-hash string.)
-
-.. _sec:rtlil_cell_wire:
-
-RTLIL::Cell and RTLIL::Wire
-~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-A module contains zero to many RTLIL::Cell and RTLIL::Wire objects. Objects of
-these types are used to model netlists. Usually the goal of all synthesis
-efforts is to convert all modules to a state where the functionality of the
-module is implemented only by cells from a given cell library and wires to
-connect these cells with each other. Note that module ports are just wires with
-a special property.
-
-An RTLIL::Wire object has the following properties:
-
--  The wire name
--  A list of attributes
--  A width (buses are just wires with a width > 1)
--  Bus direction (MSB to LSB or vice versa)
--  Lowest valid bit index (LSB or MSB depending on bus direction)
--  If the wire is a port: port number and direction (input/output/inout)
-
-As with modules, the attributes can be Verilog attributes imported by the
-Verilog frontend or attributes assigned by passes.
-
-In Yosys, busses (signal vectors) are represented using a single wire object
-with a width > 1. So Yosys does not convert signal vectors to individual
-signals. This makes some aspects of RTLIL more complex but enables Yosys to be
-used for coarse grain synthesis where the cells of the target architecture
-operate on entire signal vectors instead of single bit wires.
-
-In Verilog and VHDL, busses may have arbitrary bounds, and LSB can have either
-the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSB;
-however, information from the HDL frontend is preserved so that the bus will be
-correctly indexed in error messages, backend output, constraint files, etc.
-
-An RTLIL::Cell object has the following properties:
-
--  The cell name and type
--  A list of attributes
--  A list of parameters (for parametric cells)
--  Cell ports and the connections of ports to wires and constants
-
-The connections of ports to wires are coded by assigning an RTLIL::SigSpec to
-each cell port. The RTLIL::SigSpec data type is described in the next section.
-
-.. _sec:rtlil_sigspec:
-
-RTLIL::SigSpec
-~~~~~~~~~~~~~~
-
-A "signal" is everything that can be applied to a cell port. I.e.
-
--  | Any constant value of arbitrary bit-width
-   | 1em For example: ``1337, 16'b0000010100111001, 1'b1, 1'bx``
-
--  | All bits of a wire or a selection of bits from a wire
-   | 1em For example: ``mywire, mywire[24], mywire[15:8]``
-
--  | Concatenations of the above
-   | 1em For example: ``{16'd1337, mywire[15:8]}``
-
-The RTLIL::SigSpec data type is used to represent signals. The RTLIL::Cell
-object contains one RTLIL::SigSpec for each cell port.
-
-In addition, connections between wires are represented using a pair of
-RTLIL::SigSpec objects. Such pairs are needed in different locations. Therefore
-the type name RTLIL::SigSig was defined for such a pair.
-
-.. _sec:rtlil_process:
-
-RTLIL::Process
-~~~~~~~~~~~~~~
-
-When a high-level HDL frontend processes behavioural code it splits it up into
-data path logic (e.g. the expression a + b is replaced by the output of an adder
-that takes a and b as inputs) and an RTLIL::Process that models the control
-logic of the behavioural code. Let's consider a simple example:
-
-.. code:: verilog
-   :number-lines:
-
-   module ff_with_en_and_async_reset(clock, reset, enable, d, q);
-   input clock, reset, enable, d;
-   output reg q;
-   always @(posedge clock, posedge reset)
-       if (reset)
-           q <= 0;
-       else if (enable)
-           q <= d;
-   endmodule
-
-In this example there is no data path and therefore the RTLIL::Module generated
-by the frontend only contains a few RTLIL::Wire objects and an RTLIL::Process.
-The RTLIL::Process in RTLIL syntax:
-
-.. code:: RTLIL
-   :number-lines:
-
-   process $proc$ff_with_en_and_async_reset.v:4$1
-       assign $0\q[0:0] \q
-       switch \reset
-           case 1'1
-               assign $0\q[0:0] 1'0
-           case
-               switch \enable
-                   case 1'1
-                       assign $0\q[0:0] \d
-                   case
-               end
-       end
-       sync posedge \clock
-           update \q $0\q[0:0]
-       sync posedge \reset
-           update \q $0\q[0:0]
-   end
-
-This RTLIL::Process contains two RTLIL::SyncRule objects, two RTLIL::SwitchRule
-objects and five RTLIL::CaseRule objects. The wire $0\q[0:0] is an automatically
-created wire that holds the next value of \\q. The lines :math:`2 \dots 12`
-describe how $0\q[0:0] should be calculated. The lines :math:`13 \dots 16`
-describe how the value of $0\q[0:0] is used to update \\q.
-
-An RTLIL::Process is a container for zero or more RTLIL::SyncRule objects and
-exactly one RTLIL::CaseRule object, which is called the root case.
-
-An RTLIL::SyncRule object contains an (optional) synchronization condition
-(signal and edge-type), zero or more assignments (RTLIL::SigSig), and zero or
-more memory writes (RTLIL::MemWriteAction). The always synchronization condition
-is used to break combinatorial loops when a latch should be inferred instead.
-
-An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig)
-and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a
-container for zero or more RTLIL::CaseRule objects.
-
-In the above example the lines :math:`2 \dots 12` are the root case. Here
-$0\q[0:0] is first assigned the old value \\q as default value (line 2). The
-root case also contains an RTLIL::SwitchRule object (lines :math:`3 \dots 12`).
-Such an object is very similar to the C switch statement as it uses a control
-signal (\\reset in this case) to determine which of its cases should be active.
-The RTLIL::SwitchRule object then contains one RTLIL::CaseRule object per case.
-In this example there is a case [1]_ for \\reset == 1 that causes $0\q[0:0] to
-be set (lines 4 and 5) and a default case that in turn contains a switch that
-sets $0\q[0:0] to the value of \\d if \\enable is active (lines :math:`6 \dots
-11`).
-
-A case can specify zero or more compare values that will determine whether it
-matches. Each of the compare values must be the exact same width as the control
-signal. When more than one compare value is specified, the case matches if any
-of them matches the control signal; when zero compare values are specified, the
-case always matches (i.e. it is the default case).
-
-A switch prioritizes cases from first to last: multiple cases can match, but
-only the first matched case becomes active. This normally synthesizes to a
-priority encoder. The parallel_case attribute allows passes to assume that no
-more than one case will match, and full_case attribute allows passes to assume
-that exactly one case will match; if these invariants are ever dynamically
-violated, the behavior is undefined. These attributes are useful when an
-invariant invisible to the synthesizer causes the control signal to never take
-certain bit patterns.
-
-The lines :math:`13 \dots 16` then cause \\q to be updated whenever there is a
-positive clock edge on \\clock or \\reset.
-
-In order to generate such a representation, the language frontend must be able
-to handle blocking and nonblocking assignments correctly. However, the language
-frontend does not need to identify the correct type of storage element for the
-output signal or generate multiplexers for the decision tree. This is done by
-passes that work on the RTLIL representation. Therefore it is relatively easy to
-substitute these steps with other algorithms that target different target
-architectures or perform optimizations or other transformations on the decision
-trees before further processing them.
-
-One of the first actions performed on a design in RTLIL representation in most
-synthesis scripts is identifying asynchronous resets. This is usually done using
-the proc_arst pass. This pass transforms the above example to the following
-RTLIL::Process:
-
-.. code:: RTLIL
-   :number-lines:
-
-   process $proc$ff_with_en_and_async_reset.v:4$1
-       assign $0\q[0:0] \q
-       switch \enable
-           case 1'1
-               assign $0\q[0:0] \d
-           case
-       end
-       sync posedge \clock
-           update \q $0\q[0:0]
-       sync high \reset
-           update \q 1'0
-   end
-
-This pass has transformed the outer RTLIL::SwitchRule into a modified
-RTLIL::SyncRule object for the \\reset signal. Further processing converts the
-RTLIL::Process into e.g. a d-type flip-flop with asynchronous reset and a
-multiplexer for the enable signal:
-
-.. code:: RTLIL
-   :number-lines:
-
-   cell $adff $procdff$6
-       parameter \ARST_POLARITY 1'1
-       parameter \ARST_VALUE 1'0
-       parameter \CLK_POLARITY 1'1
-       parameter \WIDTH 1
-       connect \ARST \reset
-       connect \CLK \clock
-       connect \D $0\q[0:0]
-       connect \Q \q
-   end
-   cell $mux $procmux$3
-       parameter \WIDTH 1
-       connect \A \q
-       connect \B \d
-       connect \S \enable
-       connect \Y $0\q[0:0]
-   end
-
-Different combinations of passes may yield different results. Note that $adff
-and $mux are internal cell types that still need to be mapped to cell types from
-the target cell library.
-
-Some passes refuse to operate on modules that still contain RTLIL::Process
-objects as the presence of these objects in a module increases the complexity.
-Therefore the passes to translate processes to a netlist of cells are usually
-called early in a synthesis script. The proc pass calls a series of other passes
-that together perform this conversion in a way that is suitable for most
-synthesis tasks.
-
-.. _sec:rtlil_memory:
-
-RTLIL::Memory
-~~~~~~~~~~~~~
-
-For every array (memory) in the HDL code an RTLIL::Memory object is created. A
-memory object has the following properties:
-
--  The memory name
--  A list of attributes
--  The width of an addressable word
--  The size of the memory in number of words
-
-All read accesses to the memory are transformed to $memrd cells and all write
-accesses to $memwr cells by the language frontend. These cells consist of
-independent read- and write-ports to the memory. Memory initialization is
-transformed to $meminit cells by the language frontend. The ``\MEMID`` parameter
-on these cells is used to link them together and to the RTLIL::Memory object
-they belong to.
-
-The rationale behind using separate cells for the individual ports versus
-creating a large multiport memory cell right in the language frontend is that
-the separate $memrd and $memwr cells can be consolidated using resource sharing.
-As resource sharing is a non-trivial optimization problem where different
-synthesis tasks can have different requirements it lends itself to do the
-optimisation in separate passes and merge the RTLIL::Memory objects and $memrd
-and $memwr cells to multiport memory blocks after resource sharing is completed.
-
-The memory pass performs this conversion and can (depending on the options
-passed to it) transform the memories directly to d-type flip-flops and address
-logic or yield multiport memory blocks (represented using $mem cells).
-
-See :numref:`Sec. %s <sec:memcells>` for details about the memory cell types.
-
-Command interface and synthesis scripts
----------------------------------------
-
-Yosys reads and processes commands from synthesis scripts, command line
-arguments and an interactive command prompt. Yosys commands consist of a command
-name and an optional whitespace separated list of arguments. Commands are
-terminated using the newline character or a semicolon (;). Empty lines and lines
-starting with the hash sign (#) are ignored. See :numref:`Sec. %s
-<sec:typusecase>` for an example synthesis script.
-
-The command help can be used to access the command reference manual.
-
-Most commands can operate not only on the entire design but also specifically on
-selected parts of the design. For example the command dump will print all
-selected objects in the current design while dump foobar will only print the
-module foobar and dump \* will print the entire design regardless of the current
-selection.
-
-.. code:: yoscrypt
-
-	dump */t:$add %x:+[A] \*/w:\* %i
-
-The selection mechanism is very powerful. For example the command above will
-print all wires that are connected to the ``\A`` port of a ``$add`` cell.
-Detailed documentation of the select framework can be found in the command
-reference for the ``select`` command.
-
-Source tree and build system
-----------------------------
-
-The Yosys source tree is organized into the following top-level
-directories:
-
--  | backends/
-   | This directory contains a subdirectory for each of the backend modules.
-
--  | frontends/
-   | This directory contains a subdirectory for each of the frontend modules.
-
--  | kernel/
-   | This directory contains all the core functionality of Yosys. This includes
-     the functions and definitions for working with the RTLIL data structures
-     (rtlil.h and rtlil.cc), the main() function (driver.cc), the internal
-     framework for generating log messages (log.h and log.cc), the internal
-     framework for registering and calling passes (register.h and register.cc),
-     some core commands that are not really passes (select.cc, show.cc, …) and a
-     couple of other small utility libraries.
-
--  | passes/
-   | This directory contains a subdirectory for each pass or group of passes.
-     For example as of this writing the directory passes/opt/ contains the code
-     for seven passes: opt, opt_expr, opt_muxtree, opt_reduce, opt_rmdff,
-     opt_rmunused and opt_merge.
-
--  | techlibs/
-   | This directory contains simulation models and standard implementations for
-     the cells from the internal cell library.
-
--  | tests/
-   | This directory contains a couple of test cases. Most of the smaller tests
-     are executed automatically when make test is called. The larger tests must
-     be executed manually. Most of the larger tests require downloading external
-     HDL source code and/or external tools. The tests range from comparing
-     simulation results of the synthesized design to the original sources to
-     logic equivalence checking of entire CPU cores.
-
-The top-level Makefile includes frontends/\*/Makefile.inc,
-passes/\*/Makefile.inc and backends/\*/Makefile.inc. So when extending Yosys it
-is enough to create a new directory in frontends/, passes/ or backends/ with
-your sources and a Makefile.inc. The Yosys kernel automatically detects all
-commands linked with Yosys. So it is not needed to add additional commands to a
-central list of commands.
-
-Good starting points for reading example source code to learn how to write
-passes are passes/opt/opt_rmdff.cc and passes/opt/opt_merge.cc.
-
-See the top-level README file for a quick Getting Started guide and build
-instructions. The Yosys build is based solely on Makefiles.
-
-Users of the Qt Creator IDE can generate a QT Creator project file using make
-qtcreator. Users of the Eclipse IDE can use the "Makefile Project with Existing
-Code" project type in the Eclipse "New Project" dialog (only available after the
-CDT plugin has been installed) to create an Eclipse project in order to
-programming extensions to Yosys or just browse the Yosys code base.
-
-.. [1]
-   The syntax 1'1 in the RTLIL code specifies a constant with a length of one
-   bit (the first "1"), and this bit is a one (the second "1").
diff --git a/yosys/docs/source/CHAPTER_Prog.rst b/yosys/docs/source/CHAPTER_Prog.rst
deleted file mode 100644
index 23aeed5a50c..00000000000
--- a/yosys/docs/source/CHAPTER_Prog.rst
+++ /dev/null
@@ -1,46 +0,0 @@
-.. _chapter:prog:
-
-Programming Yosys extensions
-============================
-
-This chapter contains some bits and pieces of information about
-programming yosys extensions. Also consult the section on programming in
-the "Yosys Presentation" (can be downloaded from the Yosys website as
-PDF) and don't be afraid to ask questions on the YosysHQ Slack.
-
-Guidelines
-----------
-
-The guidelines directory contains notes on various aspects of Yosys
-development. The files GettingStarted and CodingStyle may be of
-particular interest, and are reproduced here.
-
-.. literalinclude:: temp/GettingStarted
-	:language: none
-	:caption: guidelines/GettingStarted
-
-.. literalinclude:: temp/CodingStyle
-	:language: none
-	:caption: guidelines/CodingStyle
-
-The "stubsnets" example module
-------------------------------
-
-The following is the complete code of the "stubsnets" example module. It
-is included in the Yosys source distribution as
-docs/source/CHAPTER_Prog/stubnets.cc.
-
-.. literalinclude:: CHAPTER_Prog/stubnets.cc
-	:language: c++
-	:linenos:
-	:caption: docs/source/CHAPTER_Prog/stubnets.cc
-
-.. literalinclude:: CHAPTER_Prog/Makefile
-	:language: makefile
-	:linenos:
-	:caption: docs/source/CHAPTER_Prog/Makefile
-
-.. literalinclude:: CHAPTER_Prog/test.v
-	:language: verilog
-	:linenos:
-	:caption: docs/source/CHAPTER_Prog/test.v
diff --git a/yosys/docs/source/CHAPTER_Verilog.rst b/yosys/docs/source/CHAPTER_Verilog.rst
deleted file mode 100644
index 484844fba04..00000000000
--- a/yosys/docs/source/CHAPTER_Verilog.rst
+++ /dev/null
@@ -1,666 +0,0 @@
-.. _chapter:verilog:
-
-The Verilog and AST frontends
-=============================
-
-This chapter provides an overview of the implementation of the Yosys Verilog and
-AST frontends. The Verilog frontend reads Verilog-2005 code and creates an
-abstract syntax tree (AST) representation of the input. This AST representation
-is then passed to the AST frontend that converts it to RTLIL data, as
-illustrated in :numref:`Fig. %s <fig:Verilog_flow>`.
-
-.. figure:: ../images/verilog_flow.*
-	:class: width-helper
-	:name: fig:Verilog_flow
-
-	Simplified Verilog to RTLIL data flow
-
-Transforming Verilog to AST
----------------------------
-
-The Verilog frontend converts the Verilog sources to an internal AST
-representation that closely resembles the structure of the original
-Verilog code. The Verilog frontend consists of three components, the
-Preprocessor, the Lexer and the Parser.
-
-The source code to the Verilog frontend can be found in
-frontends/verilog/ in the Yosys source tree.
-
-The Verilog preprocessor
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-The Verilog preprocessor scans over the Verilog source code and
-interprets some of the Verilog compiler directives such as
-:literal:`\`include`, :literal:`\`define` and :literal:`\`ifdef`.
-
-It is implemented as a C++ function that is passed a file descriptor as
-input and returns the pre-processed Verilog code as a ``std::string``.
-
-The source code to the Verilog Preprocessor can be found in
-frontends/verilog/preproc.cc in the Yosys source tree.
-
-The Verilog lexer
-~~~~~~~~~~~~~~~~~
-
-The Verilog Lexer is written using the lexer generator flex . Its source
-code can be found in frontends/verilog/verilog_lexer.l in the Yosys
-source tree. The lexer does little more than identifying all keywords
-and literals recognised by the Yosys Verilog frontend.
-
-The lexer keeps track of the current location in the Verilog source code
-using some global variables. These variables are used by the constructor
-of AST nodes to annotate each node with the source code location it
-originated from.
-
-Finally the lexer identifies and handles special comments such as
-"``// synopsys translate_off``" and "``// synopsys full_case``". (It is
-recommended to use :literal:`\`ifdef` constructs instead of the
-Synsopsys translate_on/off comments and attributes such as
-``(* full_case *)`` over "``// synopsys full_case``" whenever possible.)
-
-The Verilog parser
-~~~~~~~~~~~~~~~~~~
-
-The Verilog Parser is written using the parser generator bison . Its
-source code can be found in frontends/verilog/verilog_parser.y in the
-Yosys source tree.
-
-It generates an AST using the ``AST::AstNode`` data structure defined in
-frontends/ast/ast.h. An ``AST::AstNode`` object has the following
-properties:
-
-.. list-table:: AST node types with their corresponding Verilog constructs.
-    :name: tab:Verilog_AstNodeType
-    :widths: 50 50
-
-    * - AST Node Type
-      - Corresponding Verilog Construct
-    * - AST_NONE
-      - This Node type should never be used.
-    * - AST_DESIGN
-      - This node type is used for the top node of the AST tree. It has no corresponding Verilog construct.
-    * - AST_MODULE, AST_TASK, AST_FUNCTION
-      - ``module``, ``task`` and ``function``
-    * - AST_WIRE
-      - ``input``, ``output``, ``wire``, ``reg`` and ``integer``
-    * - AST_MEMORY
-      - Verilog Arrays
-    * - AST_AUTOWIRE
-      - Created by the simplifier when an undeclared signal name is used.
-    * - AST_PARAMETER, AST_LOCALPARAM
-      - ``parameter`` and ``localparam``
-    * - AST_PARASET
-      - Parameter set in cell instantiation
-    * - AST_ARGUMENT
-      - Port connection in cell instantiation
-    * - AST_RANGE
-      - Bit-Index in a signal or element index in array
-    * - AST_CONSTANT
-      - A literal value
-    * - AST_CELLTYPE
-      - The type of cell in cell instantiation
-    * - AST_IDENTIFIER
-      - An Identifier (signal name in expression or cell/task/etc. name in other contexts)
-    * - AST_PREFIX
-      - Construct an identifier in the form <prefix>[<index>].<suffix> (used only in advanced generate constructs)
-    * - AST_FCALL, AST_TCALL
-      - Call to function or task
-    * - AST_TO_SIGNED, AST_TO_UNSIGNED
-      - The ``$signed()`` and ``$unsigned()`` functions
-    * - AST_CONCAT, AST_REPLICATE
-      - The ``{...}`` and ``{...{...}}`` operators
-    * - AST_BIT_NOT, AST_BIT_AND, AST_BIT_OR, AST_BIT_XOR, AST_BIT_XNOR
-      - The bitwise operators ``~``, ``&``, ``|``, ``^`` and ``~^``
-    * - AST_REDUCE_AND, AST_REDUCE_OR, AST_REDUCE_XOR, AST_REDUCE_XNOR
-      - The unary reduction operators ``~``, ``&``, ``|``, ``^`` and ``~^``
-    * - AST_REDUCE_BOOL
-      - Conversion from multi-bit value to boolean value (equivalent to AST_REDUCE_OR)
-    * - AST_SHIFT_LEFT, AST_SHIFT_RIGHT, AST_SHIFT_SLEFT, AST_SHIFT_SRIGHT
-      - The shift operators ``<<``, ``>>``, ``<<<`` and ``>>>``
-    * - AST_LT, AST_LE, AST_EQ, AST_NE, AST_GE, AST_GT
-      - The relational operators ``<``, ``<=``, ``==``, ``!=``, ``>=`` and ``>``
-    * - AST_ADD, AST_SUB, AST_MUL, AST_DIV, AST_MOD, AST_POW
-      - The binary operators ``+``, ``-``, ``*``, ``/``, ``%`` and ``**``
-    * - AST_POS, AST_NEG
-      - The prefix operators ``+`` and ``-``
-    * - AST_LOGIC_AND, AST_LOGIC_OR, AST_LOGIC_NOT
-      - The logic operators ``&&``, ``||`` and ``!``
-    * - AST_TERNARY
-      - The ternary ``?:``-operator
-    * - AST_MEMRD AST_MEMWR
-      - Read and write memories. These nodes are generated by the AST simplifier for writes/reads to/from Verilog arrays.
-    * - AST_ASSIGN
-      - An ``assign`` statement
-    * - AST_CELL
-      - A cell instantiation
-    * - AST_PRIMITIVE
-      - A primitive cell (``and``, ``nand``, ``or``, etc.)
-    * - AST_ALWAYS, AST_INITIAL
-      - Verilog ``always``- and ``initial``-blocks
-    * - AST_BLOCK
-      - A ``begin``-``end``-block
-    * - AST_ASSIGN_EQ. AST_ASSIGN_LE
-      - Blocking (``=``) and nonblocking (``<=``) assignments within an ``always``- or ``initial``-block
-    * - AST_CASE. AST_COND, AST_DEFAULT
-      - The ``case`` (``if``) statements, conditions within a case and the default case respectively
-    * - AST_FOR
-      - A ``for``-loop with an ``always``- or ``initial``-block
-    * - AST_GENVAR, AST_GENBLOCK, AST_GENFOR, AST_GENIF
-      - The ``genvar`` and ``generate`` keywords and ``for`` and ``if`` within a generate block.
-    * - AST_POSEDGE, AST_NEGEDGE, AST_EDGE
-      - Event conditions for ``always`` blocks.
-
--  | The node type
-   | This enum (``AST::AstNodeType``) specifies the role of the node.
-     :numref:`Table %s <tab:Verilog_AstNodeType>`
-     contains a list of all node types.
-
--  | The child nodes
-   | This is a list of pointers to all children in the abstract syntax
-     tree.
-
--  | Attributes
-   | As almost every AST node might have Verilog attributes assigned to
-     it, the ``AST::AstNode`` has direct support for attributes. Note
-     that the attribute values are again AST nodes.
-
--  | Node content
-   | Each node might have additional content data. A series of member
-     variables exist to hold such data. For example the member
-     ``std::string str`` can hold a string value and is used e.g. in the
-     AST_IDENTIFIER node type to store the identifier name.
-
--  | Source code location
-   | Each ``AST::AstNode`` is automatically annotated with the current
-     source code location by the ``AST::AstNode`` constructor. It is
-     stored in the ``std::string filename`` and ``int linenum`` member
-     variables.
-
-The ``AST::AstNode`` constructor can be called with up to two child
-nodes that are automatically added to the list of child nodes for the
-new object. This simplifies the creation of AST nodes for simple
-expressions a bit. For example the bison code for parsing
-multiplications:
-
-.. code:: none
-   	:number-lines:
-
-	basic_expr '*' attr basic_expr {
-		$$ = new AstNode(AST_MUL, $1, $4);
-		append_attr($$, $3);
-	} |
-
-The generated AST data structure is then passed directly to the AST
-frontend that performs the actual conversion to RTLIL.
-
-Note that the Yosys command ``read_verilog`` provides the options ``-yydebug``
-and ``-dump_ast`` that can be used to print the parse tree or abstract
-syntax tree respectively.
-
-Transforming AST to RTLIL
--------------------------
-
-The AST Frontend converts a set of modules in AST representation to
-modules in RTLIL representation and adds them to the current design.
-This is done in two steps: simplification and RTLIL generation.
-
-The source code to the AST frontend can be found in ``frontends/ast/`` in
-the Yosys source tree.
-
-AST simplification
-~~~~~~~~~~~~~~~~~~
-
-A full-featured AST is too complex to be transformed into RTLIL
-directly. Therefore it must first be brought into a simpler form. This
-is done by calling the ``AST::AstNode::simplify()`` method of all
-AST_MODULE nodes in the AST. This initiates a recursive process that
-performs the following transformations on the AST data structure:
-
--  Inline all task and function calls.
-
--  Evaluate all ``generate``-statements and unroll all ``for``-loops.
-
--  Perform const folding where it is necessary (e.g. in the value part
-   of AST_PARAMETER, AST_LOCALPARAM, AST_PARASET and AST_RANGE nodes).
-
--  Replace AST_PRIMITIVE nodes with appropriate AST_ASSIGN nodes.
-
--  Replace dynamic bit ranges in the left-hand-side of assignments with
-   AST_CASE nodes with AST_COND children for each possible case.
-
--  Detect array access patterns that are too complicated for the
-   RTLIL::Memory abstraction and replace them with a set of signals and
-   cases for all reads and/or writes.
-
--  Otherwise replace array accesses with AST_MEMRD and AST_MEMWR nodes.
-
-In addition to these transformations, the simplifier also annotates the
-AST with additional information that is needed for the RTLIL generator,
-namely:
-
--  All ranges (width of signals and bit selections) are not only const
-   folded but (when a constant value is found) are also written to
-   member variables in the AST_RANGE node.
-
--  All identifiers are resolved and all AST_IDENTIFIER nodes are
-   annotated with a pointer to the AST node that contains the
-   declaration of the identifier. If no declaration has been found, an
-   AST_AUTOWIRE node is created and used for the annotation.
-
-This produces an AST that is fairly easy to convert to the RTLIL format.
-
-Generating RTLIL
-~~~~~~~~~~~~~~~~
-
-After AST simplification, the ``AST::AstNode::genRTLIL()`` method of
-each AST_MODULE node in the AST is called. This initiates a recursive
-process that generates equivalent RTLIL data for the AST data.
-
-The ``AST::AstNode::genRTLIL()`` method returns an ``RTLIL::SigSpec``
-structure. For nodes that represent expressions (operators, constants,
-signals, etc.), the cells needed to implement the calculation described
-by the expression are created and the resulting signal is returned. That
-way it is easy to generate the circuits for large expressions using
-depth-first recursion. For nodes that do not represent an expression
-(such as AST_CELL), the corresponding circuit is generated and an empty
-``RTLIL::SigSpec`` is returned.
-
-Synthesizing Verilog always blocks
---------------------------------------
-
-For behavioural Verilog code (code utilizing ``always``- and
-``initial``-blocks) it is necessary to also generate ``RTLIL::Process``
-objects. This is done in the following way:
-
-Whenever ``AST::AstNode::genRTLIL()`` encounters an ``always``- or
-``initial``-block, it creates an instance of
-``AST_INTERNAL::ProcessGenerator``. This object then generates the
-``RTLIL::Process`` object for the block. It also calls
-``AST::AstNode::genRTLIL()`` for all right-hand-side expressions
-contained within the block.
-
-First the ``AST_INTERNAL::ProcessGenerator`` creates a list of all
-signals assigned within the block. It then creates a set of temporary
-signals using the naming scheme $\ <number> \\\ <original_name> for each
-of the assigned signals.
-
-Then an ``RTLIL::Process`` is created that assigns all intermediate
-values for each left-hand-side signal to the temporary signal in its
-``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree.
-
-Finally a ``RTLIL::SyncRule`` is created for the ``RTLIL::Process`` that
-assigns the temporary signals for the final values to the actual
-signals.
-
-A process may also contain memory writes. A ``RTLIL::MemWriteAction`` is
-created for each of them.
-
-Calls to ``AST::AstNode::genRTLIL()`` are generated for right hand sides
-as needed. When blocking assignments are used,
-``AST::AstNode::genRTLIL()`` is configured using global variables to use
-the temporary signals that hold the correct intermediate values whenever
-one of the previously assigned signals is used in an expression.
-
-Unfortunately the generation of a correct
-``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree for behavioural code is a
-non-trivial task. The AST frontend solves the problem using the approach
-described on the following pages. The following example illustrates what
-the algorithm is supposed to do. Consider the following Verilog code:
-
-.. code:: verilog
-   :number-lines:
-
-   always @(posedge clock) begin
-       out1 = in1;
-       if (in2)
-           out1 = !out1;
-       out2 <= out1;
-       if (in3)
-           out2 <= out2;
-       if (in4)
-           if (in5)
-               out3 <= in6;
-           else
-               out3 <= in7;
-       out1 = out1 ^ out2;
-   end
-
-This is translated by the Verilog and AST frontends into the following
-RTLIL code (attributes, cell parameters and wire declarations not
-included):
-
-.. code:: RTLIL
-   :number-lines:
-
-   cell $logic_not $logic_not$<input>:4$2
-     connect \A \in1
-     connect \Y $logic_not$<input>:4$2_Y
-   end
-   cell $xor $xor$<input>:13$3
-     connect \A $1\out1[0:0]
-     connect \B \out2
-     connect \Y $xor$<input>:13$3_Y
-   end
-   process $proc$<input>:1$1
-     assign $0\out3[0:0] \out3
-     assign $0\out2[0:0] $1\out1[0:0]
-     assign $0\out1[0:0] $xor$<input>:13$3_Y
-     switch \in2
-       case 1'1
-         assign $1\out1[0:0] $logic_not$<input>:4$2_Y
-       case
-         assign $1\out1[0:0] \in1
-     end
-     switch \in3
-       case 1'1
-         assign $0\out2[0:0] \out2
-       case
-     end
-     switch \in4
-       case 1'1
-         switch \in5
-           case 1'1
-             assign $0\out3[0:0] \in6
-           case
-             assign $0\out3[0:0] \in7
-         end
-       case
-     end
-     sync posedge \clock
-       update \out1 $0\out1[0:0]
-       update \out2 $0\out2[0:0]
-       update \out3 $0\out3[0:0]
-   end
-
-Note that the two operators are translated into separate cells outside
-the generated process. The signal ``out1`` is assigned using blocking
-assignments and therefore ``out1`` has been replaced with a different
-signal in all expressions after the initial assignment. The signal
-``out2`` is assigned using nonblocking assignments and therefore is not
-substituted on the right-hand-side expressions.
-
-The ``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree must be interpreted
-the following way:
-
--  On each case level (the body of the process is the root case), first
-   the actions on this level are evaluated and then the switches within
-   the case are evaluated. (Note that the last assignment on line 13 of
-   the Verilog code has been moved to the beginning of the RTLIL process
-   to line 13 of the RTLIL listing.)
-
-   I.e. the special cases deeper in the switch hierarchy override the
-   defaults on the upper levels. The assignments in lines 12 and 22 of
-   the RTLIL code serve as an example for this.
-
-   Note that in contrast to this, the order within the
-   ``RTLIL::SwitchRule`` objects within a ``RTLIL::CaseRule`` is
-   preserved with respect to the original AST and Verilog code.
-
--  The whole ``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree describes an
-   asynchronous circuit. I.e. the decision tree formed by the switches
-   can be seen independently for each assigned signal. Whenever one
-   assigned signal changes, all signals that depend on the changed
-   signals are to be updated. For example the assignments in lines 16
-   and 18 in the RTLIL code in fact influence the assignment in line 12,
-   even though they are in the "wrong order".
-
-The only synchronous part of the process is in the ``RTLIL::SyncRule``
-object generated at line 35 in the RTLIL code. The sync rule is the only
-part of the process where the original signals are assigned. The
-synchronization event from the original Verilog code has been translated
-into the synchronization type (posedge) and signal (\\clock) for the
-``RTLIL::SyncRule`` object. In the case of this simple example the
-``RTLIL::SyncRule`` object is later simply transformed into a set of
-d-type flip-flops and the ``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree
-to a decision tree using multiplexers.
-
-In more complex examples (e.g. asynchronous resets) the part of the
-``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree that describes the
-asynchronous reset must first be transformed to the correct
-``RTLIL::SyncRule`` objects. This is done by the proc_adff pass.
-
-The ProcessGenerator algorithm
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The ``AST_INTERNAL::ProcessGenerator`` uses the following internal state
-variables:
-
--  | ``subst_rvalue_from`` and ``subst_rvalue_to``
-   | These two variables hold the replacement pattern that should be
-     used by ``AST::AstNode::genRTLIL()`` for signals with blocking
-     assignments. After initialization of
-     ``AST_INTERNAL::ProcessGenerator`` these two variables are empty.
-
--  | ``subst_lvalue_from`` and ``subst_lvalue_to``
-   | These two variables contain the mapping from left-hand-side signals
-     (\\\ <name>) to the current temporary signal for the same thing
-     (initially $0\\\ <name>).
-
--  | ``current_case``
-   | A pointer to a ``RTLIL::CaseRule`` object. Initially this is the
-     root case of the generated ``RTLIL::Process``.
-
-As the algorithm runs these variables are continuously modified as well
-as pushed to the stack and later restored to their earlier values by
-popping from the stack.
-
-On startup the ProcessGenerator generates a new ``RTLIL::Process``
-object with an empty root case and initializes its state variables as
-described above. Then the ``RTLIL::SyncRule`` objects are created using
-the synchronization events from the AST_ALWAYS node and the initial
-values of ``subst_lvalue_from`` and ``subst_lvalue_to``. Then the AST
-for this process is evaluated recursively.
-
-During this recursive evaluation, three different relevant types of AST
-nodes can be discovered: AST_ASSIGN_LE (nonblocking assignments),
-AST_ASSIGN_EQ (blocking assignments) and AST_CASE (``if`` or ``case``
-statement).
-
-Handling of nonblocking assignments
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-When an AST_ASSIGN_LE node is discovered, the following actions are
-performed by the ProcessGenerator:
-
--  The left-hand-side is evaluated using ``AST::AstNode::genRTLIL()``
-   and mapped to a temporary signal name using ``subst_lvalue_from`` and
-   ``subst_lvalue_to``.
-
--  The right-hand-side is evaluated using ``AST::AstNode::genRTLIL()``.
-   For this call, the values of ``subst_rvalue_from`` and
-   ``subst_rvalue_to`` are used to map blocking-assigned signals
-   correctly.
-
--  Remove all assignments to the same left-hand-side as this assignment
-   from the ``current_case`` and all cases within it.
-
--  Add the new assignment to the ``current_case``.
-
-Handling of blocking assignments
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-When an AST_ASSIGN_EQ node is discovered, the following actions are
-performed by the ProcessGenerator:
-
--  Perform all the steps that would be performed for a nonblocking
-   assignment (see above).
-
--  Remove the found left-hand-side (before lvalue mapping) from
-   ``subst_rvalue_from`` and also remove the respective bits from
-   ``subst_rvalue_to``.
-
--  Append the found left-hand-side (before lvalue mapping) to
-   ``subst_rvalue_from`` and append the found right-hand-side to
-   ``subst_rvalue_to``.
-
-Handling of cases and if-statements
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-When an AST_CASE node is discovered, the following actions are performed
-by the ProcessGenerator:
-
--  The values of ``subst_rvalue_from``, ``subst_rvalue_to``,
-   ``subst_lvalue_from`` and ``subst_lvalue_to`` are pushed to the
-   stack.
-
--  A new ``RTLIL::SwitchRule`` object is generated, the selection
-   expression is evaluated using ``AST::AstNode::genRTLIL()`` (with the
-   use of ``subst_rvalue_from`` and ``subst_rvalue_to``) and added to
-   the ``RTLIL::SwitchRule`` object and the object is added to the
-   ``current_case``.
-
--  All lvalues assigned to within the AST_CASE node using blocking
-   assignments are collected and saved in the local variable
-   ``this_case_eq_lvalue``.
-
--  New temporary signals are generated for all signals in
-   ``this_case_eq_lvalue`` and stored in ``this_case_eq_ltemp``.
-
--  The signals in ``this_case_eq_lvalue`` are mapped using
-   ``subst_rvalue_from`` and ``subst_rvalue_to`` and the resulting set
-   of signals is stored in ``this_case_eq_rvalue``.
-
-Then the following steps are performed for each AST_COND node within the
-AST_CASE node:
-
--  Set ``subst_rvalue_from``, ``subst_rvalue_to``, ``subst_lvalue_from``
-   and ``subst_lvalue_to`` to the values that have been pushed to the
-   stack.
-
--  Remove ``this_case_eq_lvalue`` from
-   ``subst_lvalue_from``/``subst_lvalue_to``.
-
--  Append ``this_case_eq_lvalue`` to ``subst_lvalue_from`` and append
-   ``this_case_eq_ltemp`` to ``subst_lvalue_to``.
-
--  Push the value of ``current_case``.
-
--  Create a new ``RTLIL::CaseRule``. Set ``current_case`` to the new
-   object and add the new object to the ``RTLIL::SwitchRule`` created
-   above.
-
--  Add an assignment from ``this_case_eq_rvalue`` to
-   ``this_case_eq_ltemp`` to the new ``current_case``.
-
--  Evaluate the compare value for this case using
-   ``AST::AstNode::genRTLIL()`` (with the use of ``subst_rvalue_from``
-   and ``subst_rvalue_to``) modify the new ``current_case`` accordingly.
-
--  Recursion into the children of the AST_COND node.
-
--  Restore ``current_case`` by popping the old value from the stack.
-
-Finally the following steps are performed:
-
--  The values of ``subst_rvalue_from``, ``subst_rvalue_to``,
-   ``subst_lvalue_from`` and ``subst_lvalue_to`` are popped from the
-   stack.
-
--  The signals from ``this_case_eq_lvalue`` are removed from the
-   ``subst_rvalue_from``/``subst_rvalue_to``-pair.
-
--  The value of ``this_case_eq_lvalue`` is appended to
-   ``subst_rvalue_from`` and the value of ``this_case_eq_ltemp`` is
-   appended to ``subst_rvalue_to``.
-
--  Map the signals in ``this_case_eq_lvalue`` using
-   ``subst_lvalue_from``/``subst_lvalue_to``.
-
--  Remove all assignments to signals in ``this_case_eq_lvalue`` in
-   ``current_case`` and all cases within it.
-
--  Add an assignment from ``this_case_eq_ltemp`` to
-   ``this_case_eq_lvalue`` to ``current_case``.
-
-Further analysis of the algorithm for cases and if-statements
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-With respect to nonblocking assignments the algorithm is easy: later
-assignments invalidate earlier assignments. For each signal assigned
-using nonblocking assignments exactly one temporary variable is
-generated (with the $0-prefix) and this variable is used for all
-assignments of the variable.
-
-Note how all the ``_eq_``-variables become empty when no blocking
-assignments are used and many of the steps in the algorithm can then be
-ignored as a result of this.
-
-For a variable with blocking assignments the algorithm shows the
-following behaviour: First a new temporary variable is created. This new
-temporary variable is then registered as the assignment target for all
-assignments for this variable within the cases for this AST_CASE node.
-Then for each case the new temporary variable is first assigned the old
-temporary variable. This assignment is overwritten if the variable is
-actually assigned in this case and is kept as a default value otherwise.
-
-This yields an ``RTLIL::CaseRule`` that assigns the new temporary
-variable in all branches. So when all cases have been processed a final
-assignment is added to the containing block that assigns the new
-temporary variable to the old one. Note how this step always overrides a
-previous assignment to the old temporary variable. Other than
-nonblocking assignments, the old assignment could still have an effect
-somewhere in the design, as there have been calls to
-``AST::AstNode::genRTLIL()`` with a
-``subst_rvalue_from``/``subst_rvalue_to``-tuple that contained the
-right-hand-side of the old assignment.
-
-The proc pass
-~~~~~~~~~~~~~
-
-The ProcessGenerator converts a behavioural model in AST representation
-to a behavioural model in ``RTLIL::Process`` representation. The actual
-conversion from a behavioural model to an RTL representation is
-performed by the proc pass and the passes it launches:
-
--  | proc_clean and proc_rmdead
-   | These two passes just clean up the ``RTLIL::Process`` structure.
-     The proc_clean pass removes empty parts (eg. empty assignments)
-     from the process and proc_rmdead detects and removes unreachable
-     branches from the process's decision trees.
-
--  | proc_arst
-   | This pass detects processes that describe d-type flip-flops with
-     asynchronous resets and rewrites the process to better reflect what
-     they are modelling: Before this pass, an asynchronous reset has two
-     edge-sensitive sync rules and one top-level for the reset path.
-     After this pass the sync rule for the reset is level-sensitive and
-     the top-level has been removed.
-
--  | proc_mux
-   | This pass converts the /-tree to a tree of multiplexers per written
-     signal. After this, the structure only contains the s that describe
-     the output registers.
-
--  | proc_dff
-   | This pass replaces the s to d-type flip-flops (with asynchronous
-     resets if necessary).
-
--  | proc_dff
-   | This pass replaces the s with $memwr cells.
-
--  | proc_clean
-   | A final call to proc_clean removes the now empty objects.
-
-Performing these last processing steps in passes instead of in the
-Verilog frontend has two important benefits:
-
-First it improves the transparency of the process. Everything that
-happens in a separate pass is easier to debug, as the RTLIL data
-structures can be easily investigated before and after each of the
-steps.
-
-Second it improves flexibility. This scheme can easily be extended to
-support other types of storage-elements, such as sr-latches or
-d-latches, without having to extend the actual Verilog frontend.
-
-Synthesizing Verilog arrays
----------------------------
-
-Add some information on the generation of $memrd and $memwr cells and
-how they are processed in the memory pass.
-
-Synthesizing parametric designs
--------------------------------
-
-Add some information on the ``RTLIL::Module::derive()`` method and how
-it is used to synthesize parametric modules via the hierarchy pass.
diff --git a/yosys/docs/source/_downloads/APPNOTE_010_Verilog_to_BLIF.pdf b/yosys/docs/source/_downloads/APPNOTE_010_Verilog_to_BLIF.pdf
new file mode 100644
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diff --git a/yosys/docs/source/_images/Makefile b/yosys/docs/source/_images/Makefile
new file mode 100644
index 00000000000..955805f9c58
--- /dev/null
+++ b/yosys/docs/source/_images/Makefile
@@ -0,0 +1,46 @@
+all: examples all_tex tidy
+
+# set a fake time in pdf generation to prevent unnecessary differences in output
+FAKETIME := TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001'
+
+# find all code example makefiles
+.PHONY: examples
+CODE_EXAMPLES := ../code_examples/*/Makefile
+examples: $(CODE_EXAMPLES)
+
+# target to convert specified dot file(s)
+.PHONY: convert
+TARG_DOT ?=
+convert: $(TARG_DOT:.dot=.pdf) $(TARG_DOT:.dot=.svg)
+
+# use empty FORCE target because .PHONY ignores % expansion, using find allows
+# us to generate everything in one pass, since we don't know all of the possible
+# outputs until the sub-makes run
+FORCE:
+../%/Makefile: FORCE
+	@make -C $(@D) dots
+	@mkdir -p $*
+	@find $(@D) -name *.dot -exec cp -u {} -t $* \;
+	@find $* -name *.dot -printf "%p " | xargs -i make --no-print-directory convert TARG_DOT="{}"
+
+# find and build all tex files
+.PHONY: all_tex
+TEX_FILES := $(wildcard **/*.tex)
+all_tex: $(TEX_FILES:.tex=.pdf) $(TEX_FILES:.tex=.svg)
+
+%.pdf: %.dot
+	$(FAKETIME) dot -Tpdf -o $@ $<
+
+%.pdf: %.tex
+	cd $(@D) && $(FAKETIME) pdflatex $(<F) --interaction=nonstopmode
+
+%.svg: %.pdf
+	pdf2svg $< $@
+
+.PHONY: clean tidy
+tidy:
+	rm -f  **/*.log **/*.aux
+
+clean: tidy
+	rm -rf code_examples
+	rm -f **/*.pdf **/*.svg
diff --git a/yosys/docs/images/approach_flow.tex b/yosys/docs/source/_images/internals/approach_flow.tex
similarity index 100%
rename from yosys/docs/images/approach_flow.tex
rename to yosys/docs/source/_images/internals/approach_flow.tex
diff --git a/yosys/docs/images/overview_flow.tex b/yosys/docs/source/_images/internals/overview_flow.tex
similarity index 100%
rename from yosys/docs/images/overview_flow.tex
rename to yosys/docs/source/_images/internals/overview_flow.tex
diff --git a/yosys/docs/images/overview_rtlil.tex b/yosys/docs/source/_images/internals/overview_rtlil.tex
similarity index 100%
rename from yosys/docs/images/overview_rtlil.tex
rename to yosys/docs/source/_images/internals/overview_rtlil.tex
diff --git a/yosys/docs/source/_images/internals/simplified_rtlil.tex b/yosys/docs/source/_images/internals/simplified_rtlil.tex
new file mode 100644
index 00000000000..9dc0a7d4c7a
--- /dev/null
+++ b/yosys/docs/source/_images/internals/simplified_rtlil.tex
@@ -0,0 +1,20 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\usepackage{amsmath}
+\usepackage{pgfplots}
+\usepackage{tikz}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}[every node/.style={transform shape}]
+	\tikzstyle{entity} = [draw, fill=gray!10, rectangle, minimum height=3em, minimum width=7em, node distance=5em, font={\ttfamily}]
+	\node[entity] (design) {RTLIL::Design};
+	\node[entity] (module) [right of=design, node distance=11em] {RTLIL::Module} edge [-latex] node[above] {\tiny 1 \hskip3em N} (design);
+
+	\node[entity] (wire) [fill=blue!10, right of=module, node distance=10em] {RTLIL::Wire} (wire.west) edge [-latex] (module);
+	\node[entity] (cell) [fill=blue!10, above of=wire] {RTLIL::Cell} (cell.west) edge [-latex] (module);
+\end{tikzpicture}
+\end{document}
diff --git a/yosys/docs/images/verilog_flow.tex b/yosys/docs/source/_images/internals/verilog_flow.tex
similarity index 100%
rename from yosys/docs/images/verilog_flow.tex
rename to yosys/docs/source/_images/internals/verilog_flow.tex
diff --git a/yosys/docs/images/basics_abstractions.tex b/yosys/docs/source/_images/primer/basics_abstractions.tex
similarity index 100%
rename from yosys/docs/images/basics_abstractions.tex
rename to yosys/docs/source/_images/primer/basics_abstractions.tex
diff --git a/yosys/docs/images/basics_ast.tex b/yosys/docs/source/_images/primer/basics_ast.tex
similarity index 100%
rename from yosys/docs/images/basics_ast.tex
rename to yosys/docs/source/_images/primer/basics_ast.tex
diff --git a/yosys/docs/images/basics_flow.tex b/yosys/docs/source/_images/primer/basics_flow.tex
similarity index 100%
rename from yosys/docs/images/basics_flow.tex
rename to yosys/docs/source/_images/primer/basics_flow.tex
diff --git a/yosys/docs/images/basics_parsetree.tex b/yosys/docs/source/_images/primer/basics_parsetree.tex
similarity index 100%
rename from yosys/docs/images/basics_parsetree.tex
rename to yosys/docs/source/_images/primer/basics_parsetree.tex
diff --git a/yosys/docs/source/_images/primer/levels_of_abstraction.tex b/yosys/docs/source/_images/primer/levels_of_abstraction.tex
new file mode 100644
index 00000000000..55725d08e12
--- /dev/null
+++ b/yosys/docs/source/_images/primer/levels_of_abstraction.tex
@@ -0,0 +1,42 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\usepackage{amsmath}
+\usepackage{pgfplots}
+\usepackage{tikz}
+\pagestyle{empty}
+\definecolor{MyBlue}{RGB}{85,130,180}
+
+\begin{document}
+\begin{tikzpicture}[scale=1.2, every node/.style={transform shape}]
+    \tikzstyle{lvl} = [draw, fill=MyBlue, rectangle, minimum height=2em, minimum width=15em]
+    \node[lvl] (sys) {System Level};
+    \node[lvl] (hl) [below of=sys] {High Level};
+    \node[lvl] (beh) [below of=hl] {Behavioral Level};
+    \node[lvl] (rtl) [below of=beh] {Register-Transfer Level (RTL)};
+    \node[lvl] (lg) [below of=rtl] {Logical Gate Level};
+    \node[lvl] (pg) [below of=lg] {Physical Gate Level};
+    \node[lvl] (sw) [below of=pg] {Switch Level};
+
+    \draw[dotted] (sys.east)  -- ++(1,0) coordinate (sysx);
+    \draw[dotted] (hl.east)  -- ++(1,0) coordinate (hlx);
+    \draw[dotted] (beh.east) -- ++(1,0) coordinate (behx);
+    \draw[dotted] (rtl.east) -- ++(1,0) coordinate (rtlx);
+    \draw[dotted] (lg.east)  -- ++(1,0) coordinate (lgx);
+    \draw[dotted] (pg.east)  -- ++(1,0) coordinate (pgx);
+    \draw[dotted] (sw.east)  -- ++(1,0) coordinate (swx);
+
+    \draw[gray,|->] (sysx) -- node[right] {System Design} (hlx);
+    \draw[|->|] (hlx) -- node[right] {High Level Synthesis (HLS)} (behx);
+    \draw[->|] (behx) -- node[right] {Behavioral Synthesis} (rtlx);
+    \draw[->|] (rtlx) -- node[right] {RTL Synthesis} (lgx);
+    \draw[->|] (lgx) -- node[right] {Logic Synthesis} (pgx);
+    \draw[gray,->|] (pgx) -- node[right] {Cell Library} (swx);
+
+    \draw[dotted] (behx) -- ++(4,0) coordinate (a);
+    \draw[dotted] (pgx) -- ++(4,0) coordinate (b);
+    \draw[|->|] (a) -- node[right] {Yosys} (b);
+\end{tikzpicture}
+\end{document}
diff --git a/yosys/docs/source/_static/custom.css b/yosys/docs/source/_static/custom.css
new file mode 100644
index 00000000000..b08194c0521
--- /dev/null
+++ b/yosys/docs/source/_static/custom.css
@@ -0,0 +1,20 @@
+/* Reduce whitespace in cmd def pages */
+.cmd.def .highlight-yoscrypt, .cmd.def .highlight pre {
+    padding: 0%;
+    margin: 0%;
+}
+
+.cmd.def .highlight-none, .cmd.def .highlight pre {
+    padding-top: 0%;
+    margin-top: 0%;
+}
+
+/* Make images full width */
+.width-helper {
+    max-width: 100%;
+}
+
+/* Prevent code block caption text from bunching into the caption number */
+.literal-block-wrapper .code-block-caption .caption-number {
+    padding-right: 0.5em
+}
diff --git a/yosys/docs/static/favico.png b/yosys/docs/source/_static/favico.png
similarity index 100%
rename from yosys/docs/static/favico.png
rename to yosys/docs/source/_static/favico.png
diff --git a/yosys/docs/static/logo.png b/yosys/docs/source/_static/logo.png
similarity index 100%
rename from yosys/docs/static/logo.png
rename to yosys/docs/source/_static/logo.png
diff --git a/yosys/docs/source/_static/yosyshq.css b/yosys/docs/source/_static/yosyshq.css
new file mode 100644
index 00000000000..447c8536743
--- /dev/null
+++ b/yosys/docs/source/_static/yosyshq.css
@@ -0,0 +1,40 @@
+/* Don't hide the right sidebar as we're placing our fixed links there */
+aside.no-toc {
+    display: block !important;
+}
+
+/* Colorful headings */
+h1 {
+    color: var(--color-brand-primary);
+  }
+  
+h2, h3, h4, h5, h6 {
+    color: var(--color-brand-content);
+}
+
+/* Use a different color for external links */
+a.external {
+    color: var(--color-brand-primary) !important;
+}
+
+.wy-table-responsive table td {
+    white-space: normal;
+}
+  
+th {
+    text-align: left;
+}
+
+body[data-theme="dark"] {
+    .invert-helper {
+        filter: url("data:image/svg+xml,<svg xmlns='http%3A//www.w3.org/2000/svg'><filter id='f'><feColorMatrix color-interpolation-filters='sRGB' type='matrix' values='1.47 -1.73 -0.467 0 0.867 -0.733 0.467 -0.467 0 0.867 -0.667 -1.07 1.07 0 0.867 0 0 0 1.0 0'></feColorMatrix></filter></svg>#f");
+    }
+}
+
+@media (prefers-color-scheme: dark) {
+    body:not([data-theme="light"]) {
+        .invert-helper {
+            filter: url("data:image/svg+xml,<svg xmlns='http%3A//www.w3.org/2000/svg'><filter id='f'><feColorMatrix color-interpolation-filters='sRGB' type='matrix' values='1.47 -1.73 -0.467 0 0.867 -0.733 0.467 -0.467 0 0.867 -0.667 -1.07 1.07 0 0.867 0 0 0 1.0 0'></feColorMatrix></filter></svg>#f");
+        }
+    }
+}
\ No newline at end of file
diff --git a/yosys/docs/source/_templates/page.html b/yosys/docs/source/_templates/page.html
new file mode 100644
index 00000000000..d830124c176
--- /dev/null
+++ b/yosys/docs/source/_templates/page.html
@@ -0,0 +1,44 @@
+{#
+
+See https://github.com/pradyunsg/furo/blob/main/src/furo/theme/furo/page.html for the original
+block this is overwriting.
+
+The part that is customized is between the "begin of custom part" and "end of custom part"
+comments below. It uses the same styles as the existing right sidebar code.
+
+#}
+{% extends "furo/page.html" %}
+{% block right_sidebar %}
+<div class="toc-sticky toc-scroll">
+	{# begin of custom part #}
+	<div class="toc-title-container">
+	<span class="toc-title">
+	YosysHQ
+	</span>
+	</div>
+	<div class="toc-tree-container yosyshq-links" style="padding-bottom: 0">
+	<div class="toc-tree">
+	<ul>
+	<li></li>
+	<li><a class="reference external" href="https://yosyshq.readthedocs.io">Docs</a></li>
+	<li><a class="reference external" href="https://blog.yosyshq.com">Blog</a></li>
+	<li><a class="reference external" href="https://www.yosyshq.com">Website</a></li>
+	</ul>
+	</div>
+	</div>
+	{# end of custom part #}
+	{% if not furo_hide_toc %}
+	<div class="toc-title-container">
+	<span class="toc-title">
+	{{ _("On this page") }}
+	</span>
+	</div>
+	<div class="toc-tree-container">
+	<div class="toc-tree">
+	{{ toc }}
+	</div>
+	</div>
+	{% endif %}
+</div>
+{% endblock %}
+	
\ No newline at end of file
diff --git a/yosys/docs/source/appendix.rst b/yosys/docs/source/appendix.rst
new file mode 100644
index 00000000000..0b0a2d15b5d
--- /dev/null
+++ b/yosys/docs/source/appendix.rst
@@ -0,0 +1,18 @@
+Appendix
+========
+
+.. toctree::
+	:maxdepth: 2
+	:includehidden:
+
+	appendix/primer
+	appendix/auxlibs
+	appendix/auxprogs
+
+	bib
+
+.. toctree::
+	:maxdepth: 1
+	:includehidden:
+
+	cmd_ref
diff --git a/yosys/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst b/yosys/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst
index a48401dcc18..ff404cb53d1 100644
--- a/yosys/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst
+++ b/yosys/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst
@@ -1,336 +1,363 @@
+:orphan:
+
 ====================================
 010: Converting Verilog to BLIF page
 ====================================
 
-Installation
-============
+Abstract
+========
+
+Verilog-2005 is a powerful Hardware Description Language (HDL) that can be used
+to easily create complex designs from small HDL code. It is the preferred method
+of design entry for many designers.
+
+The Berkeley Logic Interchange Format (BLIF) is a simple file format for
+exchanging sequential logic between programs. It is easy to generate and easy to
+parse and is therefore the preferred method of design entry for many authors of
+logic synthesis tools.
+
+Yosys is a feature-rich Open-Source Verilog synthesis tool that can be used to
+bridge the gap between the two file formats. It implements most of Verilog-2005
+and thus can be used to import modern behavioral Verilog designs into BLIF-based
+design flows without dependencies on proprietary synthesis tools.
+
+The scope of Yosys goes of course far beyond Verilog logic synthesis. But it is
+a useful and important feature and this Application Note will focus on this
+aspect of Yosys.
+
+Download
+========
+
+This document was originally published in April 2015:
+:download:`Converting Verilog to BLIF PDF</_downloads/APPNOTE_010_Verilog_to_BLIF.pdf>`
+
+..
+   Installation
+   ============
 
-Yosys written in C++ (using features from C++11) and is tested on modern
-Linux. It should compile fine on most UNIX systems with a C++11
-compiler. The README file contains useful information on building Yosys
-and its prerequisites.
+   Yosys written in C++ (using features from C++11) and is tested on modern
+   Linux. It should compile fine on most UNIX systems with a C++11
+   compiler. The README file contains useful information on building Yosys
+   and its prerequisites.
 
-Yosys is a large and feature-rich program with a couple of dependencies.
-It is, however, possible to deactivate some of the dependencies in the
-Makefile, resulting in features in Yosys becoming unavailable. When
-problems with building Yosys are encountered, a user who is only
-interested in the features of Yosys that are discussed in this
-Application Note may deactivate TCL, Qt and MiniSAT support in the
-Makefile and may opt against building yosys-abc.
+   Yosys is a large and feature-rich program with a couple of dependencies.
+   It is, however, possible to deactivate some of the dependencies in the
+   Makefile, resulting in features in Yosys becoming unavailable. When
+   problems with building Yosys are encountered, a user who is only
+   interested in the features of Yosys that are discussed in this
+   Application Note may deactivate TCL, Qt and MiniSAT support in the
+   Makefile and may opt against building yosys-abc.
 
-This Application Note is based on `Yosys GIT`_ `Rev. e216e0e`_  from 2013-11-23.
-The Verilog sources used for the examples are taken from `yosys-bigsim`_, a
-collection of real-world designs used for regression testing Yosys.
+   This Application Note is based on `Yosys GIT`_ `Rev. e216e0e`_  from 2013-11-23.
+   The Verilog sources used for the examples are taken from `yosys-bigsim`_, a
+   collection of real-world designs used for regression testing Yosys.
 
-.. _Yosys GIT: https://github.com/YosysHQ/yosys
+   .. _Yosys GIT: https://github.com/YosysHQ/yosys
 
-.. _Rev. e216e0e: https://github.com/YosysHQ/yosys/tree/e216e0e
+   .. _Rev. e216e0e: https://github.com/YosysHQ/yosys/tree/e216e0e
 
-.. _yosys-bigsim: https://github.com/YosysHQ/yosys-bigsim
+   .. _yosys-bigsim: https://github.com/YosysHQ/yosys-bigsim
 
-Getting started
-===============
+   Getting started
+   ===============
 
-We start our tour with the Navré processor from yosys-bigsim. The `Navré
-processor`_ is an Open Source AVR clone. It is a single module (softusb_navre)
-in a single design file (softusb_navre.v). It also is using only features that
-map nicely to the BLIF format, for example it only uses synchronous resets.
+   We start our tour with the Navré processor from yosys-bigsim. The `Navré
+   processor`_ is an Open Source AVR clone. It is a single module (softusb_navre)
+   in a single design file (softusb_navre.v). It also is using only features that
+   map nicely to the BLIF format, for example it only uses synchronous resets.
 
-.. _Navré processor: http://opencores.org/projects/navre
-
-Converting softusb_navre.v to softusb_navre.blif could not be easier:
+   .. _Navré processor: http://opencores.org/projects/navre
+
+   Converting softusb_navre.v to softusb_navre.blif could not be easier:
 
-.. code:: sh
+   .. code:: sh
 
-   yosys -o softusb_navre.blif -S softusb_navre.v
+      yosys -o softusb_navre.blif -S softusb_navre.v
 
-Behind the scenes Yosys is controlled by synthesis scripts that execute
-commands that operate on Yosys' internal state. For example, the -o
-softusb_navre.blif option just adds the command write_blif
-softusb_navre.blif to the end of the script. Likewise a file on the
-command line – softusb_navre.v in this case – adds the command
-read_verilog softusb_navre.v to the beginning of the synthesis script.
-In both cases the file type is detected from the file extension.
+   Behind the scenes Yosys is controlled by synthesis scripts that execute
+   commands that operate on Yosys' internal state. For example, the -o
+   softusb_navre.blif option just adds the command write_blif
+   softusb_navre.blif to the end of the script. Likewise a file on the
+   command line – softusb_navre.v in this case – adds the command
+   read_verilog softusb_navre.v to the beginning of the synthesis script.
+   In both cases the file type is detected from the file extension.
 
-Finally the option -S instantiates a built-in default synthesis script.
-Instead of using -S one could also specify the synthesis commands for
-the script on the command line using the -p option, either using
-individual options for each command or by passing one big command string
-with a semicolon-separated list of commands. But in most cases it is
-more convenient to use an actual script file.
+   Finally the option -S instantiates a built-in default synthesis script.
+   Instead of using -S one could also specify the synthesis commands for
+   the script on the command line using the -p option, either using
+   individual options for each command or by passing one big command string
+   with a semicolon-separated list of commands. But in most cases it is
+   more convenient to use an actual script file.
 
-Using a synthesis script
-========================
+   Using a synthesis script
+   ========================
 
-With a script file we have better control over Yosys. The following
-script file replicates what the command from the last section did:
+   With a script file we have better control over Yosys. The following
+   script file replicates what the command from the last section did:
 
-.. code:: yoscrypt
+   .. code:: yoscrypt
 
-   read_verilog softusb_navre.v
-   hierarchy
-   proc; opt; memory; opt; techmap; opt
-   write_blif softusb_navre.blif
-
-The first and last line obviously read the Verilog file and write the
-BLIF file.
-
-The 2nd line checks the design hierarchy and instantiates parametrized
-versions of the modules in the design, if necessary. In the case of this
-simple design this is a no-op. However, as a general rule a synthesis
-script should always contain this command as first command after reading
-the input files.
-
-The 3rd line does most of the actual work:
-
--  The command opt is the Yosys' built-in optimizer. It can perform some
-   simple optimizations such as const-folding and removing unconnected
-   parts of the design. It is common practice to call opt after each
-   major step in the synthesis procedure. In cases where too much
-   optimization is not appreciated (for example when analyzing a
-   design), it is recommended to call clean instead of opt.
-
--  The command proc converts processes (Yosys' internal representation
-   of Verilog always- and initial-blocks) to circuits of multiplexers
-   and storage elements (various types of flip-flops).
-
--  The command memory converts Yosys' internal representations of arrays
-   and array accesses to multi-port block memories, and then maps this
-   block memories to address decoders and flip-flops, unless the option
-   -nomap is used, in which case the multi-port block memories stay in
-   the design and can then be mapped to architecture-specific memory
-   primitives using other commands.
-
--  The command techmap turns a high-level circuit with coarse grain
-   cells such as wide adders and multipliers to a fine-grain circuit of
-   simple logic primitives and single-bit storage elements. The command
-   does that by substituting the complex cells by circuits of simpler
-   cells. It is possible to provide a custom set of rules for this
-   process in the form of a Verilog source file, as we will see in the
-   next section.
-
-Now Yosys can be run with the filename of the synthesis script as
-argument:
-
-.. code:: sh
-
-   yosys softusb_navre.ys
-
-Now that we are using a synthesis script we can easily modify how Yosys
-synthesizes the design. The first thing we should customize is the call
-to the hierarchy command:
-
-Whenever it is known that there are no implicit blackboxes in the
-design, i.e. modules that are referenced but are not defined, the
-hierarchy command should be called with the -check option. This will
-then cause synthesis to fail when implicit blackboxes are found in the
-design.
-
-The 2nd thing we can improve regarding the hierarchy command is that we
-can tell it the name of the top level module of the design hierarchy. It
-will then automatically remove all modules that are not referenced from
-this top level module.
-
-For many designs it is also desired to optimize the encodings for the
-finite state machines (FSMs) in the design. The fsm command finds FSMs,
-extracts them, performs some basic optimizations and then generate a
-circuit from the extracted and optimized description. It would also be
-possible to tell the fsm command to leave the FSMs in their extracted
-form, so they can be further processed using custom commands. But in
-this case we don't want that.
-
-So now we have the final synthesis script for generating a BLIF file for
-the Navré CPU:
-
-.. code:: yoscrypt
-
-   read_verilog softusb_navre.v
-   hierarchy -check -top softusb_navre
-   proc; opt; memory; opt; fsm; opt; techmap; opt
-   write_blif softusb_navre.blif
-
-Advanced example: The Amber23 ARMv2a CPU
-========================================
-
-Our 2nd example is the `Amber23 ARMv2a CPU`_. Once again we base our example on
-the Verilog code that is included in `yosys-bigsim`_.
-
-.. _Amber23 ARMv2a CPU: http://opencores.org/projects/amber
-
-.. code-block:: yoscrypt
-   :caption: `amber23.ys`
-   :name: amber23.ys
-
-   read_verilog a23_alu.v
-   read_verilog a23_barrel_shift_fpga.v
-   read_verilog a23_barrel_shift.v
-   read_verilog a23_cache.v
-   read_verilog a23_coprocessor.v
-   read_verilog a23_core.v
-   read_verilog a23_decode.v
-   read_verilog a23_execute.v
-   read_verilog a23_fetch.v
-   read_verilog a23_multiply.v
-   read_verilog a23_ram_register_bank.v
-   read_verilog a23_register_bank.v
-   read_verilog a23_wishbone.v
-   read_verilog generic_sram_byte_en.v
-   read_verilog generic_sram_line_en.v
-   hierarchy -check -top a23_core
-   add -global_input globrst 1
-   proc -global_arst globrst
-   techmap -map adff2dff.v
-   opt; memory; opt; fsm; opt; techmap
-   write_blif amber23.blif
-
-The problem with this core is that it contains no dedicated reset logic. Instead
-the coding techniques shown in :numref:`glob_arst` are used to define reset
-values for the global asynchronous reset in an FPGA implementation. This design
-can not be expressed in BLIF as it is. Instead we need to use a synthesis script
-that transforms this form to synchronous resets that can be expressed in BLIF.
-
-(Note that there is no problem if this coding techniques are used to
-model ROM, where the register is initialized using this syntax but is
-never updated otherwise.)
-
-:numref:`amber23.ys` shows the synthesis script for the Amber23 core. In line 17
-the add command is used to add a 1-bit wide global input signal with the name
-globrst. That means that an input with that name is added to each module in the
-design hierarchy and then all module instantiations are altered so that this new
-signal is connected throughout the whole design hierarchy.
-
-.. code-block:: verilog
-   :caption: Implicit coding of global asynchronous resets
-   :name: glob_arst
-
-   reg [7:0] a = 13, b;
-   initial b = 37;
-
-.. code-block:: verilog
-   :caption: `adff2dff.v`
-   :name: adff2dff.v
-
-   (* techmap_celltype = "$adff" *)
-   module adff2dff (CLK, ARST, D, Q);
-
-   parameter WIDTH = 1;
-   parameter CLK_POLARITY = 1;
-   parameter ARST_POLARITY = 1;
-   parameter ARST_VALUE = 0;
-
-   input CLK, ARST;
-   input [WIDTH-1:0] D;
-   output reg [WIDTH-1:0] Q;
-
-   wire [1023:0] _TECHMAP_DO_ = "proc";
-
-   wire _TECHMAP_FAIL_ =
-       !CLK_POLARITY || !ARST_POLARITY;
-
-   always @(posedge CLK)
-           if (ARST)
-                   Q <= ARST_VALUE;
-           else
-                   Q <= D;
-
-   endmodule
-
-In line 18 the proc command is called. But in this script the signal
-name globrst is passed to the command as a global reset signal for
-resetting the registers to their assigned initial values.
-
-Finally in line 19 the techmap command is used to replace all instances of
-flip-flops with asynchronous resets with flip-flops with synchronous resets. The
-map file used for this is shown in :numref:`adff2dff.v`. Note how the
-techmap_celltype attribute is used in line 1 to tell the techmap command which
-cells to replace in the design, how the \_TECHMAP_FAIL\_ wire in lines 15 and 16
-(which evaluates to a constant value) determines if the parameter set is
-compatible with this replacement circuit, and how the \_TECHMAP_DO\_ wire in
-line 13 provides a mini synthesis-script to be used to process this cell.
-
-.. code-block:: c
-   :caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled 
-             using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a 
-	     -mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx`` 
-	     set and booted with a custom setup routine written in ARM assembler.
-   :name: sieve
-
-   #include <stdint.h>
-   #include <stdbool.h>
-
-   #define BITMAP_SIZE 64
-   #define OUTPORT 0x10000000
-
-   static uint32_t bitmap[BITMAP_SIZE/32];
-
-   static void bitmap_set(uint32_t idx) { bitmap[idx/32] |= 1 << (idx % 32); }
-   static bool bitmap_get(uint32_t idx) { return (bitmap[idx/32] & (1 << (idx % 32))) != 0; }
-   static void output(uint32_t val) { *((volatile uint32_t*)OUTPORT) = val; }
-
-   int main() {
-       uint32_t i, j, k;
-       output(2);
-       for (i = 0; i < BITMAP_SIZE; i++) {
-           if (bitmap_get(i)) continue;
-           output(3+2*i);
-           for (j = 2*(3+2*i);; j += 3+2*i) {
-               if (j%2 == 0) continue;
-               k = (j-3)/2;
-               if (k >= BITMAP_SIZE) break;
-               bitmap_set(k);
-           }
-       }
-       output(0);
-       return 0;
-   }
-
-Verification of the Amber23 CPU
-===============================
-
-The BLIF file for the Amber23 core, generated using :numref:`amber23.ys` and
-:numref:`adff2dff.v` and the version of the Amber23 RTL source that is bundled
-with yosys-bigsim, was verified using the test-bench from yosys-bigsim. It
-successfully executed the program shown in :numref:`sieve` in the test-bench.
-
-For simulation the BLIF file was converted back to Verilog using `ABC`_. So this
-test includes the successful transformation of the BLIF file into ABC's internal
-format as well.
-
-.. _ABC: https://github.com/berkeley-abc/abc
-
-The only thing left to write about the simulation itself is that it
-probably was one of the most energy inefficient and time consuming ways
-of successfully calculating the first 31 primes the author has ever
-conducted.
-
-Limitations
-===========
-
-At the time of this writing Yosys does not support multi-dimensional
-memories, does not support writing to individual bits of array elements,
-does not support initialization of arrays with $readmemb and $readmemh,
-and has only limited support for tristate logic, to name just a few
-limitations.
-
-That being said, Yosys can synthesize an overwhelming majority of
-real-world Verilog RTL code. The remaining cases can usually be modified
-to be compatible with Yosys quite easily.
-
-The various designs in yosys-bigsim are a good place to look for
-examples of what is within the capabilities of Yosys.
-
-Conclusion
-==========
-
-Yosys is a feature-rich Verilog-2005 synthesis tool. It has many uses,
-but one is to provide an easy gateway from high-level Verilog code to
-low-level logic circuits.
-
-The command line option -S can be used to quickly synthesize Verilog
-code to BLIF files without a hassle.
-
-With custom synthesis scripts it becomes possible to easily perform
-high-level optimizations, such as re-encoding FSMs. In some extreme
-cases, such as the Amber23 ARMv2 CPU, the more advanced Yosys features
-can be used to change a design to fit a certain need without actually
-touching the RTL code.
+      read_verilog softusb_navre.v
+      hierarchy
+      proc; opt; memory; opt; techmap; opt
+      write_blif softusb_navre.blif
+
+   The first and last line obviously read the Verilog file and write the
+   BLIF file.
+
+   The 2nd line checks the design hierarchy and instantiates parametrized
+   versions of the modules in the design, if necessary. In the case of this
+   simple design this is a no-op. However, as a general rule a synthesis
+   script should always contain this command as first command after reading
+   the input files.
+
+   The 3rd line does most of the actual work:
+
+   -  The command opt is the Yosys' built-in optimizer. It can perform some
+      simple optimizations such as const-folding and removing unconnected
+      parts of the design. It is common practice to call opt after each
+      major step in the synthesis procedure. In cases where too much
+      optimization is not appreciated (for example when analyzing a
+      design), it is recommended to call clean instead of opt.
+
+   -  The command proc converts processes (Yosys' internal representation
+      of Verilog always- and initial-blocks) to circuits of multiplexers
+      and storage elements (various types of flip-flops).
+
+   -  The command memory converts Yosys' internal representations of arrays
+      and array accesses to multi-port block memories, and then maps this
+      block memories to address decoders and flip-flops, unless the option
+      -nomap is used, in which case the multi-port block memories stay in
+      the design and can then be mapped to architecture-specific memory
+      primitives using other commands.
+
+   -  The command techmap turns a high-level circuit with coarse grain
+      cells such as wide adders and multipliers to a fine-grain circuit of
+      simple logic primitives and single-bit storage elements. The command
+      does that by substituting the complex cells by circuits of simpler
+      cells. It is possible to provide a custom set of rules for this
+      process in the form of a Verilog source file, as we will see in the
+      next section.
+
+   Now Yosys can be run with the filename of the synthesis script as
+   argument:
+
+   .. code:: sh
+
+      yosys softusb_navre.ys
+
+   Now that we are using a synthesis script we can easily modify how Yosys
+   synthesizes the design. The first thing we should customize is the call
+   to the hierarchy command:
+
+   Whenever it is known that there are no implicit blackboxes in the
+   design, i.e. modules that are referenced but are not defined, the
+   hierarchy command should be called with the -check option. This will
+   then cause synthesis to fail when implicit blackboxes are found in the
+   design.
+
+   The 2nd thing we can improve regarding the hierarchy command is that we
+   can tell it the name of the top level module of the design hierarchy. It
+   will then automatically remove all modules that are not referenced from
+   this top level module.
+
+   For many designs it is also desired to optimize the encodings for the
+   finite state machines (FSMs) in the design. The fsm command finds FSMs,
+   extracts them, performs some basic optimizations and then generate a
+   circuit from the extracted and optimized description. It would also be
+   possible to tell the fsm command to leave the FSMs in their extracted
+   form, so they can be further processed using custom commands. But in
+   this case we don't want that.
+
+   So now we have the final synthesis script for generating a BLIF file for
+   the Navré CPU:
+
+   .. code:: yoscrypt
+
+      read_verilog softusb_navre.v
+      hierarchy -check -top softusb_navre
+      proc; opt; memory; opt; fsm; opt; techmap; opt
+      write_blif softusb_navre.blif
+
+   Advanced example: The Amber23 ARMv2a CPU
+   ========================================
+
+   Our 2nd example is the `Amber23 ARMv2a CPU`_. Once again we base our example on
+   the Verilog code that is included in `yosys-bigsim`_.
+
+   .. _Amber23 ARMv2a CPU: http://opencores.org/projects/amber
+
+   .. code-block:: yoscrypt
+      :caption: `amber23.ys`
+      :name: amber23.ys
+
+      read_verilog a23_alu.v
+      read_verilog a23_barrel_shift_fpga.v
+      read_verilog a23_barrel_shift.v
+      read_verilog a23_cache.v
+      read_verilog a23_coprocessor.v
+      read_verilog a23_core.v
+      read_verilog a23_decode.v
+      read_verilog a23_execute.v
+      read_verilog a23_fetch.v
+      read_verilog a23_multiply.v
+      read_verilog a23_ram_register_bank.v
+      read_verilog a23_register_bank.v
+      read_verilog a23_wishbone.v
+      read_verilog generic_sram_byte_en.v
+      read_verilog generic_sram_line_en.v
+      hierarchy -check -top a23_core
+      add -global_input globrst 1
+      proc -global_arst globrst
+      techmap -map adff2dff.v
+      opt; memory; opt; fsm; opt; techmap
+      write_blif amber23.blif
+
+   The problem with this core is that it contains no dedicated reset logic. Instead
+   the coding techniques shown in :numref:`glob_arst` are used to define reset
+   values for the global asynchronous reset in an FPGA implementation. This design
+   can not be expressed in BLIF as it is. Instead we need to use a synthesis script
+   that transforms this form to synchronous resets that can be expressed in BLIF.
+
+   (Note that there is no problem if this coding techniques are used to model ROM,
+   where the register is initialized using this syntax but is never updated
+   otherwise.)
+
+   :numref:`amber23.ys` shows the synthesis script for the Amber23 core. In line 17
+   the add command is used to add a 1-bit wide global input signal with the name
+   ``globrst``. That means that an input with that name is added to each module in the
+   design hierarchy and then all module instantiations are altered so that this new
+   signal is connected throughout the whole design hierarchy.
+
+   .. code-block:: verilog
+      :caption: Implicit coding of global asynchronous resets
+      :name: glob_arst
+
+      reg [7:0] a = 13, b;
+      initial b = 37;
+
+   .. code-block:: verilog
+      :caption: `adff2dff.v`
+      :name: adff2dff.v
+
+      (* techmap_celltype = "$adff" *)
+      module adff2dff (CLK, ARST, D, Q);
+
+      parameter WIDTH = 1;
+      parameter CLK_POLARITY = 1;
+      parameter ARST_POLARITY = 1;
+      parameter ARST_VALUE = 0;
+
+      input CLK, ARST;
+      input [WIDTH-1:0] D;
+      output reg [WIDTH-1:0] Q;
+
+      wire [1023:0] _TECHMAP_DO_ = "proc";
+
+      wire _TECHMAP_FAIL_ =
+         !CLK_POLARITY || !ARST_POLARITY;
+
+      always @(posedge CLK)
+            if (ARST)
+                     Q <= ARST_VALUE;
+            else
+                     Q <= D;
+
+      endmodule
+
+   In line 18 the :cmd:ref:`proc` command is called. But in this script the signal
+   name globrst is passed to the command as a global reset signal for resetting the
+   registers to their assigned initial values.
+
+   Finally in line 19 the techmap command is used to replace all instances of
+   flip-flops with asynchronous resets with flip-flops with synchronous resets. The
+   map file used for this is shown in :numref:`adff2dff.v`. Note how the
+   ``techmap_celltype`` attribute is used in line 1 to tell the techmap command
+   which cells to replace in the design, how the ``_TECHMAP_FAIL_`` wire in lines
+   15 and 16 (which evaluates to a constant value) determines if the parameter set
+   is compatible with this replacement circuit, and how the ``_TECHMAP_DO_`` wire
+   in line 13 provides a mini synthesis-script to be used to process this cell.
+
+   .. code-block:: c
+      :caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled 
+               using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a 
+         -mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx`` 
+         set and booted with a custom setup routine written in ARM assembler.
+      :name: sieve
+
+      #include <stdint.h>
+      #include <stdbool.h>
+
+      #define BITMAP_SIZE 64
+      #define OUTPORT 0x10000000
+
+      static uint32_t bitmap[BITMAP_SIZE/32];
+
+      static void bitmap_set(uint32_t idx) { bitmap[idx/32] |= 1 << (idx % 32); }
+      static bool bitmap_get(uint32_t idx) { return (bitmap[idx/32] & (1 << (idx % 32))) != 0; }
+      static void output(uint32_t val) { *((volatile uint32_t*)OUTPORT) = val; }
+
+      int main() {
+         uint32_t i, j, k;
+         output(2);
+         for (i = 0; i < BITMAP_SIZE; i++) {
+            if (bitmap_get(i)) continue;
+            output(3+2*i);
+            for (j = 2*(3+2*i);; j += 3+2*i) {
+                  if (j%2 == 0) continue;
+                  k = (j-3)/2;
+                  if (k >= BITMAP_SIZE) break;
+                  bitmap_set(k);
+            }
+         }
+         output(0);
+         return 0;
+      }
+
+   Verification of the Amber23 CPU
+   ===============================
+
+   The BLIF file for the Amber23 core, generated using :numref:`amber23.ys` and
+   :numref:`adff2dff.v` and the version of the Amber23 RTL source that is bundled
+   with yosys-bigsim, was verified using the test-bench from yosys-bigsim. It
+   successfully executed the program shown in :numref:`sieve` in the test-bench.
+
+   For simulation the BLIF file was converted back to Verilog using `ABC`_. So this
+   test includes the successful transformation of the BLIF file into ABC's internal
+   format as well.
+
+   .. _ABC: https://github.com/berkeley-abc/abc
+
+   The only thing left to write about the simulation itself is that it probably was
+   one of the most energy inefficient and time consuming ways of successfully
+   calculating the first 31 primes the author has ever conducted.
+
+   Limitations
+   ===========
+
+   At the time of this writing Yosys does not support multi-dimensional memories,
+   does not support writing to individual bits of array elements, does not support
+   initialization of arrays with ``$readmemb`` and ``$readmemh``, and has only
+   limited support for tristate logic, to name just a few limitations.
+
+   That being said, Yosys can synthesize an overwhelming majority of real-world
+   Verilog RTL code. The remaining cases can usually be modified to be compatible
+   with Yosys quite easily.
+
+   The various designs in yosys-bigsim are a good place to look for examples of
+   what is within the capabilities of Yosys.
+
+   Conclusion
+   ==========
+
+   Yosys is a feature-rich Verilog-2005 synthesis tool. It has many uses, but one
+   is to provide an easy gateway from high-level Verilog code to low-level logic
+   circuits.
+
+   The command line option ``-S`` can be used to quickly synthesize Verilog code to
+   BLIF files without a hassle.
+
+   With custom synthesis scripts it becomes possible to easily perform high-level
+   optimizations, such as re-encoding FSMs. In some extreme cases, such as the
+   Amber23 ARMv2 CPU, the more advanced Yosys features can be used to change a
+   design to fit a certain need without actually touching the RTL code.
diff --git a/yosys/docs/source/appendix/APPNOTE_011_Design_Investigation.rst b/yosys/docs/source/appendix/APPNOTE_011_Design_Investigation.rst
deleted file mode 100644
index 44819e28332..00000000000
--- a/yosys/docs/source/appendix/APPNOTE_011_Design_Investigation.rst
+++ /dev/null
@@ -1,965 +0,0 @@
-==========================================
-011: Interactive design investigation page
-==========================================
-
-Installation and prerequisites
-==============================
-
-This Application Note is based on the `Yosys GIT`_ `Rev. 2b90ba1`_ from
-2013-12-08. The README file covers how to install Yosys. The ``show`` command
-requires a working installation of `GraphViz`_ and `xdot` for generating the
-actual circuit diagrams.
-
-.. _Yosys GIT: https://github.com/YosysHQ/yosys
-
-.. _Rev. 2b90ba1: https://github.com/YosysHQ/yosys/tree/2b90ba1
-
-.. _GraphViz: http://www.graphviz.org/
-
-.. _xdot: https://github.com/jrfonseca/xdot.py
-
-Overview
-========
-
-This application note is structured as follows:
-
-:ref:`intro_show` introduces the ``show`` command and explains the symbols used
-in the circuit diagrams generated by it.
-
-:ref:`navigate` introduces additional commands used to navigate in the design,
-select portions of the design, and print additional information on the elements
-in the design that are not contained in the circuit diagrams.
-
-:ref:`poke` introduces commands to evaluate the design and solve SAT problems
-within the design.
-
-:ref:`conclusion` concludes the document and summarizes the key points.
-
-.. _intro_show:
-
-Introduction to the show command
-================================
-
-.. code-block:: console
-   :caption: Yosys script with ``show`` commands and example design
-   :name: example_src
-
-   $ cat example.ys
-   read_verilog example.v
-   show -pause
-   proc
-   show -pause
-   opt
-   show -pause
-
-   $ cat example.v
-   module example(input clk, a, b, c,
-                  output reg [1:0] y);
-       always @(posedge clk)
-           if (c)
-               y <= c ? a + b : 2'd0;
-   endmodule
-
-.. figure:: ../../images/011/example_out.*
-   :class: width-helper
-   :name: example_out
-   
-   Output of the three ``show`` commands from :numref:`example_src`
-
-The ``show`` command generates a circuit diagram for the design in its current
-state. Various options can be used to change the appearance of the circuit
-diagram, set the name and format for the output file, and so forth. When called
-without any special options, it saves the circuit diagram in a temporary file
-and launches ``xdot`` to display the diagram. Subsequent calls to show re-use the
-``xdot`` instance (if still running).
-
-A simple circuit
-----------------
-
-:numref:`example_src` shows a simple synthesis script and a Verilog file that
-demonstrate the usage of show in a simple setting. Note that ``show`` is called with
-the ``-pause`` option, that halts execution of the Yosys script until the user
-presses the Enter key. The ``show -pause`` command also allows the user to enter
-an interactive shell to further investigate the circuit before continuing
-synthesis.
-
-So this script, when executed, will show the design after each of the three
-synthesis commands. The generated circuit diagrams are shown in
-:numref:`example_out`.
-
-The first diagram (from top to bottom) shows the design directly after being
-read by the Verilog front-end. Input and output ports are displayed as octagonal
-shapes. Cells are displayed as rectangles with inputs on the left and outputs on
-the right side. The cell labels are two lines long: The first line contains a
-unique identifier for the cell and the second line contains the cell type.
-Internal cell types are prefixed with a dollar sign. The Yosys manual contains a
-chapter on the internal cell library used in Yosys.
-
-Constants are shown as ellipses with the constant value as label. The syntax
-``<bit_width>'<bits>`` is used for for constants that are not 32-bit wide and/or
-contain bits that are not 0 or 1 (i.e. ``x`` or ``z``). Ordinary 32-bit
-constants are written using decimal numbers.
-
-Single-bit signals are shown as thin arrows pointing from the driver to the
-load. Signals that are multiple bits wide are shown as think arrows.
-
-Finally *processes* are shown in boxes with round corners. Processes are Yosys'
-internal representation of the decision-trees and synchronization events
-modelled in a Verilog ``always``-block. The label reads ``PROC`` followed by a
-unique identifier in the first line and contains the source code location of the
-original ``always``-block in the 2nd line. Note how the multiplexer from the
-``?:``-expression is represented as a ``$mux`` cell but the multiplexer from the
-``if``-statement is yet still hidden within the process.
-
-The ``proc`` command transforms the process from the first diagram into a
-multiplexer and a d-type flip-flip, which brings us to the 2nd diagram.
-
-The Rhombus shape to the right is a dangling wire. (Wire nodes are only shown if
-they are dangling or have "public" names, for example names assigned from the
-Verilog input.) Also note that the design now contains two instances of a
-``BUF``-node. This are artefacts left behind by the ``proc``-command. It is
-quite usual to see such artefacts after calling commands that perform changes in
-the design, as most commands only care about doing the transformation in the
-least complicated way, not about cleaning up after them. The next call to
-``clean`` (or ``opt``, which includes ``clean`` as one of its operations) will
-clean up this artefacts. This operation is so common in Yosys scripts that it
-can simply be abbreviated with the ``;;`` token, which doubles as separator for
-commands. Unless one wants to specifically analyze this artefacts left behind
-some operations, it is therefore recommended to always call ``clean`` before
-calling ``show``.
-
-In this script we directly call ``opt`` as next step, which finally leads us to
-the 3rd diagram in :numref:`example_out`. Here we see that the ``opt`` command
-not only has removed the artifacts left behind by ``proc``, but also determined
-correctly that it can remove the first ``$mux`` cell without changing the
-behavior of the circuit.
-
-.. figure:: ../../images/011/splice.*
-   :class: width-helper
-   :name: splice_dia
-
-   Output of ``yosys -p 'proc; opt; show' splice.v``
-
-.. literalinclude:: ../APPNOTE_011_Design_Investigation/splice.v
-   :caption: ``splice.v``
-   :name: splice_src
-
-.. figure:: ../../images/011/splitnets_libfile.*
-   :class: width-helper
-   :name: splitnets_libfile
-
-   Effects of ``splitnets`` command and of providing a cell library. (The
-   circuit is a half-adder built from simple CMOS gates.)
-
-Break-out boxes for signal vectors
-----------------------------------
-
-As has been indicated by the last example, Yosys is can manage signal vectors
-(aka. multi-bit wires or buses) as native objects. This provides great
-advantages when analyzing circuits that operate on wide integers. But it also
-introduces some additional complexity when the individual bits of of a signal
-vector are accessed. The example ``show`` in :numref:`splice_src` demonstrates
-how such circuits are visualized by the ``show`` command.
-
-The key elements in understanding this circuit diagram are of course the boxes
-with round corners and rows labeled ``<MSB_LEFT>:<LSB_LEFT> -
-<MSB_RIGHT>:<LSB_RIGHT>``. Each of this boxes has one signal per row on one side
-and a common signal for all rows on the other side. The ``<MSB>:<LSB>`` tuples
-specify which bits of the signals are broken out and connected. So the top row
-of the box connecting the signals ``a`` and ``x`` indicates that the bit 0 (i.e.
-the range 0:0) from signal ``a`` is connected to bit 1 (i.e. the range 1:1) of
-signal ``x``.
-
-Lines connecting such boxes together and lines connecting such boxes to
-cell ports have a slightly different look to emphasise that they are not
-actual signal wires but a necessity of the graphical representation.
-This distinction seems like a technicality, until one wants to debug a
-problem related to the way Yosys internally represents signal vectors,
-for example when writing custom Yosys commands.
-
-Gate level netlists
--------------------
-
-Finally :numref:`splitnets_libfile` shows two common pitfalls when working with
-designs mapped to a cell library. The top figure has two problems: First Yosys
-did not have access to the cell library when this diagram was generated,
-resulting in all cell ports defaulting to being inputs. This is why all ports
-are drawn on the left side the cells are awkwardly arranged in a large column.
-Secondly the two-bit vector ``y`` requires breakout-boxes for its individual
-bits, resulting in an unnecessary complex diagram.
-
-For the 2nd diagram Yosys has been given a description of the cell library as
-Verilog file containing blackbox modules. There are two ways to load cell
-descriptions into Yosys: First the Verilog file for the cell library can be
-passed directly to the ``show`` command using the ``-lib <filename>`` option.
-Secondly it is possible to load cell libraries into the design with the
-``read_verilog -lib <filename>`` command. The 2nd method has the great advantage
-that the library only needs to be loaded once and can then be used in all
-subsequent calls to the ``show`` command.
-
-In addition to that, the 2nd diagram was generated after ``splitnet -ports`` was
-run on the design. This command splits all signal vectors into individual signal
-bits, which is often desirable when looking at gate-level circuits. The
-``-ports`` option is required to also split module ports. Per default the
-command only operates on interior signals.
-
-Miscellaneous notes
--------------------
-
-Per default the ``show`` command outputs a temporary dot file and launches
-``xdot`` to display it. The options ``-format``, ``-viewer`` and ``-prefix`` can
-be used to change format, viewer and filename prefix. Note that the ``pdf`` and
-``ps`` format are the only formats that support plotting multiple modules in one
-run.
-
-In densely connected circuits it is sometimes hard to keep track of the
-individual signal wires. For this cases it can be useful to call ``show`` with
-the ``-colors <integer>`` argument, which randomly assigns colors to the nets.
-The integer (> 0) is used as seed value for the random color assignments.
-Sometimes it is necessary it try some values to find an assignment of colors
-that looks good.
-
-The command ``help show`` prints a complete listing of all options supported by
-the ``show`` command.
-
-.. _navigate:
-
-Navigating the design
-=====================
-
-Plotting circuit diagrams for entire modules in the design brings us
-only helps in simple cases. For complex modules the generated circuit
-diagrams are just stupidly big and are no help at all. In such cases one
-first has to select the relevant portions of the circuit.
-
-In addition to *what* to display one also needs to carefully decide *when*
-to display it, with respect to the synthesis flow. In general it is a
-good idea to troubleshoot a circuit in the earliest state in which a
-problem can be reproduced. So if, for example, the internal state before
-calling the ``techmap`` command already fails to verify, it is better to
-troubleshoot the coarse-grain version of the circuit before ``techmap`` than
-the gate-level circuit after ``techmap``.
-
-.. Note:: It is generally recommended to verify the internal state of a
-   design by writing it to a Verilog file using ``write_verilog -noexpr``
-   and using the simulation models from ``simlib.v`` and ``simcells.v`` 
-   from the Yosys data directory (as printed by ``yosys-config --datdir``).
-
-Interactive navigation
-----------------------
-
-.. code-block:: none
-   :caption: Demonstration of ``ls`` and ``cd`` using ``example.v`` from :numref:`example_src`
-   :name: lscd
-
-   yosys> ls
-
-   1 modules:
-     example
-
-   yosys> cd example
-
-   yosys [example]> ls
-
-   7 wires:
-     $0\y[1:0]
-     $add$example.v:5$2_Y
-     a
-     b
-     c
-     clk
-     y
-
-   3 cells:
-     $add$example.v:5$2
-     $procdff$7
-     $procmux$5
-
-.. code-block:: RTLIL
-   :caption: Output of ``dump \$2`` using the design from :numref:`example_src` 
-             and :numref:`example_out`
-   :name: dump2
-
-     attribute \src "example.v:5"
-     cell $add $add$example.v:5$2
-       parameter \A_SIGNED 0
-       parameter \A_WIDTH 1
-       parameter \B_SIGNED 0
-       parameter \B_WIDTH 1
-       parameter \Y_WIDTH 2
-       connect \A \a
-       connect \B \b
-       connect \Y $add$example.v:5$2_Y
-     end
-
-Once the right state within the synthesis flow for debugging the circuit has
-been identified, it is recommended to simply add the ``shell`` command to the
-matching place in the synthesis script. This command will stop the synthesis at
-the specified moment and go to shell mode, where the user can interactively
-enter commands.
-
-For most cases, the shell will start with the whole design selected (i.e. when
-the synthesis script does not already narrow the selection). The command ``ls``
-can now be used to create a list of all modules. The command ``cd`` can be used
-to switch to one of the modules (type ``cd ..`` to switch back). Now the `ls`
-command lists the objects within that module. :numref:`lscd` demonstrates this
-using the design from :numref:`example_src`.
-
-There is a thing to note in :numref:`lscd`: We can see that the cell names from
-:numref:`example_out` are just abbreviations of the actual cell names, namely
-the part after the last dollar-sign. Most auto-generated names (the ones
-starting with a dollar sign) are rather long and contains some additional
-information on the origin of the named object. But in most cases those names can
-simply be abbreviated using the last part.
-
-Usually all interactive work is done with one module selected using the ``cd``
-command. But it is also possible to work from the design-context (``cd ..``). In
-this case all object names must be prefixed with ``<module_name>/``. For example
-``a*/b\*`` would refer to all objects whose names start with ``b`` from all
-modules whose names start with ``a``.
-
-The ``dump`` command can be used to print all information about an object. For
-example ``dump $2`` will print :numref:`dump2`. This can for example be useful
-to determine the names of nets connected to cells, as the net-names are usually
-suppressed in the circuit diagram if they are auto-generated.
-
-For the remainder of this document we will assume that the commands are
-run from module-context and not design-context.
-
-Working with selections
------------------------
-
-.. figure:: ../../images/011/example_03.*
-   :class: width-helper
-   :name: seladd
-
-   Output of ``show`` after ``select $2`` or ``select t:$add`` (see also
-   :numref:`example_out`)
-
-When a module is selected using the ``cd`` command, all commands (with a few
-exceptions, such as the ``read_`` and ``write_`` commands) operate only on the
-selected module. This can also be useful for synthesis scripts where different
-synthesis strategies should be applied to different modules in the design.
-
-But for most interactive work we want to further narrow the set of
-selected objects. This can be done using the ``select`` command.
-
-For example, if the command ``select $2`` is executed, a subsequent ``show``
-command will yield the diagram shown in :numref:`seladd`. Note that the nets are
-now displayed in ellipses. This indicates that they are not selected, but only
-shown because the diagram contains a cell that is connected to the net. This of
-course makes no difference for the circuit that is shown, but it can be a useful
-information when manipulating selections.
-
-Objects can not only be selected by their name but also by other properties. For
-example ``select t:$add`` will select all cells of type ``$add``. In this case
-this is also yields the diagram shown in :numref:`seladd`.
-
-.. literalinclude:: ../APPNOTE_011_Design_Investigation/foobaraddsub.v
-   :caption: Test module for operations on selections
-   :name: foobaraddsub
-   :language: verilog
-
-The output of ``help select`` contains a complete syntax reference for
-matching different properties.
-
-Many commands can operate on explicit selections. For example the command ``dump
-t:$add`` will print information on all ``$add`` cells in the active module.
-Whenever a command has ``[selection]`` as last argument in its usage help, this
-means that it will use the engine behind the ``select`` command to evaluate
-additional arguments and use the resulting selection instead of the selection
-created by the last ``select`` command.
-
-Normally the ``select`` command overwrites a previous selection. The commands
-``select -add`` and ``select -del`` can be used to add or remove objects from
-the current selection.
-
-The command ``select -clear`` can be used to reset the selection to the default,
-which is a complete selection of everything in the current module.
-
-Operations on selections
-------------------------
-
-.. literalinclude:: ../APPNOTE_011_Design_Investigation/sumprod.v
-   :caption: Another test module for operations on selections
-   :name: sumprod
-   :language: verilog
-
-.. figure:: ../../images/011/sumprod_00.*
-   :class: width-helper
-   :name: sumprod_00
-
-   Output of ``show a:sumstuff`` on :numref:`sumprod`
-
-The ``select`` command is actually much more powerful than it might seem on the
-first glimpse. When it is called with multiple arguments, each argument is
-evaluated and pushed separately on a stack. After all arguments have been
-processed it simply creates the union of all elements on the stack. So the
-following command will select all ``$add`` cells and all objects with the
-``foo`` attribute set:
-
-.. code-block:: yoscrypt
-
-   select t:$add a:foo
-
-(Try this with the design shown in :numref:`foobaraddsub`. Use the ``select
--list`` command to list the current selection.)
-
-In many cases simply adding more and more stuff to the selection is an
-ineffective way of selecting the interesting part of the design. Special
-arguments can be used to combine the elements on the stack. For example
-the ``%i`` arguments pops the last two elements from the stack, intersects
-them, and pushes the result back on the stack. So the following command
-will select all ``$add ``cells that have the ``foo`` attribute set:
-
-.. code-block:: yoscrypt
-
-   select t:$add a:foo %i
-
-The listing in :numref:`sumprod` uses the Yosys non-standard ``{... \*}`` syntax
-to set the attribute ``sumstuff`` on all cells generated by the first assign
-statement. (This works on arbitrary large blocks of Verilog code an can be used
-to mark portions of code for analysis.)
-
-Selecting ``a:sumstuff`` in this module will yield the circuit diagram shown in
-:numref:`sumprod_00`. As only the cells themselves are selected, but not the
-temporary wire ``$1_Y``, the two adders are shown as two disjunct parts. This
-can be very useful for global signals like clock and reset signals: just
-unselect them using a command such as ``select -del clk rst`` and each cell
-using them will get its own net label.
-
-In this case however we would like to see the cells connected properly. This can
-be achieved using the ``%x`` action, that broadens the selection, i.e. for each
-selected wire it selects all cells connected to the wire and vice versa. So
-``show a:sumstuff %x`` yields the diagram shown in :numref:`sumprod_01`.
-
-.. figure:: ../../images/011/sumprod_01.*
-   :class: width-helper
-   :name: sumprod_01
-
-   Output of ``show a:sumstuff %x`` on :numref:`sumprod`
-
-Selecting logic cones
----------------------
-
-:numref:`sumprod_01` shows what is called the ``input cone`` of ``sum``, i.e.
-all cells and signals that are used to generate the signal ``sum``. The ``%ci``
-action can be used to select the input cones of all object in the top selection
-in the stack maintained by the ``select`` command.
-
-As the ``%x`` action, this commands broadens the selection by one "step".
-But this time the operation only works against the direction of data
-flow. That means, wires only select cells via output ports and cells
-only select wires via input ports.
-
-:numref:`select_prod` show the sequence of diagrams generated by the following
-commands:
-
-.. code-block:: yoscrypt
-
-   show prod
-   show prod %ci
-   show prod %ci %ci
-   show prod %ci %ci %ci
-
-When selecting many levels of logic, repeating ``%ci`` over and over again can
-be a bit dull. So there is a shortcut for that: the number of iterations can be
-appended to the action. So for example the action ``%ci3`` is identical to
-performing the ``%ci`` action three times.
-
-The action ``%ci\*`` performs the ``%ci`` action over and over again until it
-has no effect anymore.
-
-.. figure:: ../../images/011/select_prod.*
-   :class: width-helper
-   :name: select_prod
-   
-   Objects selected by ``select prod \%ci...``
-
-In most cases there are certain cell types and/or ports that should not be
-considered for the ``%ci`` action, or we only want to follow certain cell types
-and/or ports. This can be achieved using additional patterns that can be
-appended to the ``%ci`` action.
-
-Lets consider the design from :numref:`memdemo_src`. It serves no purpose other
-than being a non-trivial circuit for demonstrating some of the advanced Yosys
-features. We synthesize the circuit using ``proc; opt; memory; opt`` and change
-to the ``memdemo`` module with ``cd memdemo``. If we type ``show`` now we see
-the diagram shown in :numref:`memdemo_00`.
-
-.. literalinclude:: ../APPNOTE_011_Design_Investigation/memdemo.v
-   :caption: Demo circuit for demonstrating some advanced Yosys features
-   :name: memdemo_src
-   :language: verilog
-
-.. figure:: ../../images/011/memdemo_00.*
-   :class: width-helper
-   :name: memdemo_00
-   
-   Complete circuit diagram for the design shown in :numref:`memdemo_src`
-
-But maybe we are only interested in the tree of multiplexers that select the
-output value. In order to get there, we would start by just showing the output
-signal and its immediate predecessors:
-
-.. code-block:: yoscrypt
-
-   show y %ci2
-
-From this we would learn that ``y`` is driven by a ``$dff cell``, that ``y`` is
-connected to the output port ``Q``, that the ``clk`` signal goes into the
-``CLK`` input port of the cell, and that the data comes from a auto-generated
-wire into the input ``D`` of the flip-flop cell.
-
-As we are not interested in the clock signal we add an additional pattern to the
-``%ci`` action, that tells it to only follow ports ``Q`` and ``D`` of ``$dff``
-cells:
-
-.. code-block:: yoscrypt
-
-   show y %ci2:+$dff[Q,D]
-
-To add a pattern we add a colon followed by the pattern to the ``%ci`` action.
-The pattern it self starts with ``-`` or ``+``, indicating if it is an include
-or exclude pattern, followed by an optional comma separated list of cell types,
-followed by an optional comma separated list of port names in square brackets.
-
-Since we know that the only cell considered in this case is a ``$dff`` cell,
-we could as well only specify the port names:
-
-.. code-block:: yoscrypt
-
-   show y %ci2:+[Q,D]
-
-Or we could decide to tell the ``%ci`` action to not follow the ``CLK`` input:
-
-.. code-block:: yoscrypt
-
-   show y %ci2:-[CLK]
-
-.. figure:: ../../images/011/memdemo_01.*
-   :class: width-helper
-   :name: memdemo_01
-   
-   Output of ``show y \%ci2:+\$dff[Q,D] \%ci*:-\$mux[S]:-\$dff``
-
-Next we would investigate the next logic level by adding another ``%ci2`` to
-the command:
-
-.. code-block:: yoscrypt
-
-   show y %ci2:-[CLK] %ci2
-
-From this we would learn that the next cell is a ``$mux`` cell and we would
-add additional pattern to narrow the selection on the path we are
-interested. In the end we would end up with a command such as
-
-.. code-block:: yoscrypt
-
-   show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff
-
-in which the first ``%ci`` jumps over the initial d-type flip-flop and the 2nd
-action selects the entire input cone without going over multiplexer select
-inputs and flip-flop cells. The diagram produces by this command is shown in
-:numref:`memdemo_01`.
-
-Similar to ``%ci`` exists an action ``%co`` to select output cones that accepts
-the same syntax for pattern and repetition. The ``%x`` action mentioned
-previously also accepts this advanced syntax.
-
-This actions for traversing the circuit graph, combined with the actions for
-boolean operations such as intersection (``%i``) and difference (``%d``) are
-powerful tools for extracting the relevant portions of the circuit under
-investigation.
-
-See ``help select`` for a complete list of actions available in selections.
-
-Storing and recalling selections
---------------------------------
-
-The current selection can be stored in memory with the command ``select -set
-<name>``. It can later be recalled using ``select @<name>``. In fact, the
-``@<name>`` expression pushes the stored selection on the stack maintained by
-the ``select`` command. So for example
-
-.. code-block:: yoscrypt
-
-   select @foo @bar %i
-
-will select the intersection between the stored selections ``foo`` and ``bar``.
-
-In larger investigation efforts it is highly recommended to maintain a
-script that sets up relevant selections, so they can easily be recalled,
-for example when Yosys needs to be re-run after a design or source code
-change.
-
-The ``history`` command can be used to list all recent interactive commands.
-This feature can be useful for creating such a script from the commands
-used in an interactive session.
-
-.. _poke:
-
-Advanced investigation techniques
-=================================
-
-When working with very large modules, it is often not enough to just select the
-interesting part of the module. Instead it can be useful to extract the
-interesting part of the circuit into a separate module. This can for example be
-useful if one wants to run a series of synthesis commands on the critical part
-of the module and wants to carefully read all the debug output created by the
-commands in order to spot a problem. This kind of troubleshooting is much easier
-if the circuit under investigation is encapsulated in a separate module.
-
-:numref:`submod` shows how the ``submod`` command can be used to split the
-circuit from :numref:`memdemo_src` and :numref:`memdemo_00` into its components.
-The ``-name`` option is used to specify the name of the new module and also the
-name of the new cell in the current module.
-
-.. figure:: ../../images/011/submod_dots.*
-   :class: width-helper
-   :name: submod_dots
-
-.. code-block:: yoscrypt
-   :caption: The circuit from :numref:`memdemo_src` and :numref:`memdemo_00` 
-             broken up using ``submod``
-   :name: submod
-
-   select -set outstage y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff
-   select -set selstage y %ci2:+$dff[Q,D] %ci*:-$dff @outstage %d
-   select -set scramble mem* %ci2 %ci*:-$dff mem* %d @selstage %d
-   submod -name scramble @scramble
-   submod -name outstage @outstage
-   submod -name selstage @selstage
-
-Evaluation of combinatorial circuits
-------------------------------------
-
-The ``eval`` command can be used to evaluate combinatorial circuits. For example
-(see :numref:`submod` for the circuit diagram of ``selstage``):
-
-::
-
-      yosys [selstage]> eval -set s2,s1 4'b1001 -set d 4'hc -show n2 -show n1
-
-      1. Executing EVAL pass (evaluate the circuit given an input).
-      Full command line: eval -set s2,s1 4'b1001 -set d 4'hc -show n2 -show n1
-      Eval result: \n2 = 2'10.
-      Eval result: \n1 = 2'10.
-
-So the ``-set`` option is used to set input values and the ``-show`` option is
-used to specify the nets to evaluate. If no ``-show`` option is specified, all
-selected output ports are used per default.
-
-If a necessary input value is not given, an error is produced. The option
-``-set-undef`` can be used to instead set all unspecified input nets to undef
-(``x``).
-
-The ``-table`` option can be used to create a truth table. For example:
-
-::
-
-      yosys [selstage]> eval -set-undef -set d[3:1] 0 -table s1,d[0]
-
-      10. Executing EVAL pass (evaluate the circuit given an input).
-      Full command line: eval -set-undef -set d[3:1] 0 -table s1,d[0]
-
-        \s1 \d [0] |  \n1  \n2
-       ---- ------ | ---- ----
-       2'00    1'0 | 2'00 2'00
-       2'00    1'1 | 2'xx 2'00
-       2'01    1'0 | 2'00 2'00
-       2'01    1'1 | 2'xx 2'01
-       2'10    1'0 | 2'00 2'00
-       2'10    1'1 | 2'xx 2'10
-       2'11    1'0 | 2'00 2'00
-       2'11    1'1 | 2'xx 2'11
-
-      Assumed undef (x) value for the following signals: \s2
-
-Note that the ``eval`` command (as well as the ``sat`` command discussed in the
-next sections) does only operate on flattened modules. It can not analyze
-signals that are passed through design hierarchy levels. So the ``flatten``
-command must be used on modules that instantiate other modules before this
-commands can be applied.
-
-Solving combinatorial SAT problems
-----------------------------------
-
-.. literalinclude:: ../APPNOTE_011_Design_Investigation/primetest.v
-   :language: verilog
-   :caption: A simple miter circuit for testing if a number is prime. But it has
-             a problem (see main text and :numref:`primesat`).
-   :name: primetest
-
-.. code-block::
-   :caption: Experiments with the miter circuit from :numref:`primetest`. 
-             The first attempt of proving that 31 is prime failed because the 
-             SAT solver found a creative way of factorizing 31 using integer 
-             overflow.
-   :name: primesat
-
-   yosys [primetest]> sat -prove ok 1 -set p 31
-
-   8. Executing SAT pass (solving SAT problems in the circuit).
-   Full command line: sat -prove ok 1 -set p 31
-
-   Setting up SAT problem:
-   Import set-constraint: \p = 16'0000000000011111
-   Final constraint equation: \p = 16'0000000000011111
-   Imported 6 cells to SAT database.
-   Import proof-constraint: \ok = 1'1
-   Final proof equation: \ok = 1'1
-
-   Solving problem with 2790 variables and 8241 clauses..
-   SAT proof finished - model found: FAIL!
-
-      ______                   ___       ___       _ _            _ _
-     (_____ \                 / __)     / __)     (_) |          | | |
-      _____) )___ ___   ___ _| |__    _| |__ _____ _| | _____  __| | |
-     |  ____/ ___) _ \ / _ (_   __)  (_   __|____ | | || ___ |/ _  |_|
-     | |   | |  | |_| | |_| || |       | |  / ___ | | || ____( (_| |_
-     |_|   |_|   \___/ \___/ |_|       |_|  \_____|_|\_)_____)\____|_|
-
-
-     Signal Name                 Dec        Hex                   Bin
-     -------------------- ---------- ---------- ---------------------
-     \a                        15029       3ab5      0011101010110101
-     \b                         4099       1003      0001000000000011
-     \ok                           0          0                     0
-     \p                           31         1f      0000000000011111
-
-   yosys [primetest]> sat -prove ok 1 -set p 31 -set a[15:8],b[15:8] 0
-
-   9. Executing SAT pass (solving SAT problems in the circuit).
-   Full command line: sat -prove ok 1 -set p 31 -set a[15:8],b[15:8] 0
-
-   Setting up SAT problem:
-   Import set-constraint: \p = 16'0000000000011111
-   Import set-constraint: { \a [15:8] \b [15:8] } = 16'0000000000000000
-   Final constraint equation: { \a [15:8] \b [15:8] \p } = { 16'0000000000000000 16'0000000000011111 }
-   Imported 6 cells to SAT database.
-   Import proof-constraint: \ok = 1'1
-   Final proof equation: \ok = 1'1
-
-   Solving problem with 2790 variables and 8257 clauses..
-   SAT proof finished - no model found: SUCCESS!
-
-                     /$$$$$$      /$$$$$$$$     /$$$$$$$
-                    /$$__  $$    | $$_____/    | $$__  $$
-                   | $$  \ $$    | $$          | $$  \ $$
-                   | $$  | $$    | $$$$$       | $$  | $$
-                   | $$  | $$    | $$__/       | $$  | $$
-                   | $$/$$ $$    | $$          | $$  | $$
-                   |  $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$
-                    \____ $$$|__/|________/|__/|_______/|__/
-                          \__/
-
-Often the opposite of the ``eval`` command is needed, i.e. the circuits output
-is given and we want to find the matching input signals. For small circuits with
-only a few input bits this can be accomplished by trying all possible input
-combinations, as it is done by the ``eval -table`` command. For larger circuits
-however, Yosys provides the ``sat`` command that uses a `SAT`_ solver,
-`MiniSAT`_, to solve this kind of problems.
-
-.. _SAT: http://en.wikipedia.org/wiki/Circuit_satisfiability
-
-.. _MiniSAT: http://minisat.se/
-
-The ``sat`` command works very similar to the ``eval`` command. The main
-difference is that it is now also possible to set output values and find the
-corresponding input values. For Example:
-
-::
-
-      yosys [selstage]> sat -show s1,s2,d -set s1 s2 -set n2,n1 4'b1001
-
-      11. Executing SAT pass (solving SAT problems in the circuit).
-      Full command line: sat -show s1,s2,d -set s1 s2 -set n2,n1 4'b1001
-
-      Setting up SAT problem:
-      Import set-constraint: \s1 = \s2
-      Import set-constraint: { \n2 \n1 } = 4'1001
-      Final constraint equation: { \n2 \n1 \s1 } = { 4'1001 \s2 }
-      Imported 3 cells to SAT database.
-      Import show expression: { \s1 \s2 \d }
-
-      Solving problem with 81 variables and 207 clauses..
-      SAT solving finished - model found:
-
-        Signal Name                 Dec        Hex             Bin
-        -------------------- ---------- ---------- ---------------
-        \d                            9          9            1001
-        \s1                           0          0              00
-        \s2                           0          0              00
-
-Note that the ``sat`` command supports signal names in both arguments to the
-``-set`` option. In the above example we used ``-set s1 s2`` to constraint
-``s1`` and ``s2`` to be equal. When more complex constraints are needed, a
-wrapper circuit must be constructed that checks the constraints and signals if
-the constraint was met using an extra output port, which then can be forced to a
-value using the ``-set`` option. (Such a circuit that contains the circuit under
-test plus additional constraint checking circuitry is called a ``miter``
-circuit.)
-
-:numref:`primetest` shows a miter circuit that is supposed to be used as a prime
-number test. If ``ok`` is 1 for all input values ``a`` and ``b`` for a given
-``p``, then ``p`` is prime, or at least that is the idea.
-
-The Yosys shell session shown in :numref:`primesat` demonstrates that SAT
-solvers can even find the unexpected solutions to a problem: Using integer
-overflow there actually is a way of "factorizing" 31. The clean solution would
-of course be to perform the test in 32 bits, for example by replacing ``p !=
-a*b`` in the miter with ``p != {16'd0,a}b``, or by using a temporary variable
-for the 32 bit product ``a*b``. But as 31 fits well into 8 bits (and as the
-purpose of this document is to show off Yosys features) we can also simply force
-the upper 8 bits of ``a`` and ``b`` to zero for the ``sat`` call, as is done in
-the second command in :numref:`primesat` (line 31).
-
-The ``-prove`` option used in this example works similar to ``-set``, but tries
-to find a case in which the two arguments are not equal. If such a case is not
-found, the property is proven to hold for all inputs that satisfy the other
-constraints.
-
-It might be worth noting, that SAT solvers are not particularly efficient at
-factorizing large numbers. But if a small factorization problem occurs as part
-of a larger circuit problem, the Yosys SAT solver is perfectly capable of
-solving it.
-
-Solving sequential SAT problems
--------------------------------
-
-.. code-block::
-   :caption: Solving a sequential SAT problem in the ``memdemo`` module from :numref:`memdemo_src`.
-   :name: memdemo_sat
-
-   yosys [memdemo]> sat -seq 6 -show y -show d -set-init-undef \
-       -max_undef -set-at 4 y 1 -set-at 5 y 2 -set-at 6 y 3
-
-   6. Executing SAT pass (solving SAT problems in the circuit).
-   Full command line: sat -seq 6 -show y -show d -set-init-undef
-       -max_undef -set-at 4 y 1 -set-at 5 y 2 -set-at 6 y 3
-
-   Setting up time step 1:
-   Final constraint equation: { } = { }
-   Imported 29 cells to SAT database.
-
-   Setting up time step 2:
-   Final constraint equation: { } = { }
-   Imported 29 cells to SAT database.
-
-   Setting up time step 3:
-   Final constraint equation: { } = { }
-   Imported 29 cells to SAT database.
-
-   Setting up time step 4:
-   Import set-constraint for timestep: \y = 4'0001
-   Final constraint equation: \y = 4'0001
-   Imported 29 cells to SAT database.
-
-   Setting up time step 5:
-   Import set-constraint for timestep: \y = 4'0010
-   Final constraint equation: \y = 4'0010
-   Imported 29 cells to SAT database.
-
-   Setting up time step 6:
-   Import set-constraint for timestep: \y = 4'0011
-   Final constraint equation: \y = 4'0011
-   Imported 29 cells to SAT database.
-
-   Setting up initial state:
-   Final constraint equation: { \y \s2 \s1 \mem[3] \mem[2] \mem[1]
-               \mem[0] } = 24'xxxxxxxxxxxxxxxxxxxxxxxx
-
-   Import show expression: \y
-   Import show expression: \d
-
-   Solving problem with 10322 variables and 27881 clauses..
-   SAT model found. maximizing number of undefs.
-   SAT solving finished - model found:
-
-     Time Signal Name                 Dec        Hex             Bin
-     ---- -------------------- ---------- ---------- ---------------
-     init \mem[0]                      --         --            xxxx
-     init \mem[1]                      --         --            xxxx
-     init \mem[2]                      --         --            xxxx
-     init \mem[3]                      --         --            xxxx
-     init \s1                          --         --              xx
-     init \s2                          --         --              xx
-     init \y                           --         --            xxxx
-     ---- -------------------- ---------- ---------- ---------------
-        1 \d                            0          0            0000
-        1 \y                           --         --            xxxx
-     ---- -------------------- ---------- ---------- ---------------
-        2 \d                            1          1            0001
-        2 \y                           --         --            xxxx
-     ---- -------------------- ---------- ---------- ---------------
-        3 \d                            2          2            0010
-        3 \y                            0          0            0000
-     ---- -------------------- ---------- ---------- ---------------
-        4 \d                            3          3            0011
-        4 \y                            1          1            0001
-     ---- -------------------- ---------- ---------- ---------------
-        5 \d                           --         --            001x
-        5 \y                            2          2            0010
-     ---- -------------------- ---------- ---------- ---------------
-        6 \d                           --         --            xxxx
-        6 \y                            3          3            0011
-
-The SAT solver functionality in Yosys can not only be used to solve
-combinatorial problems, but can also solve sequential problems. Let's consider
-the entire memdemo module from :numref:`memdemo_src` and suppose we want to know
-which sequence of input values for ``d`` will cause the output y to produce the
-sequence 1, 2, 3 from any initial state. :numref:`memdemo_sat` show the solution
-to this question, as produced by the following command:
-
-.. code-block:: yoscrypt
-
-      sat -seq 6 -show y -show d -set-init-undef \
-        -max_undef -set-at 4 y 1 -set-at 5 y 2 -set-at 6 y 3
-
-The ``-seq 6`` option instructs the ``sat`` command to solve a sequential
-problem in 6 time steps. (Experiments with lower number of steps have show that
-at least 3 cycles are necessary to bring the circuit in a state from which the
-sequence 1, 2, 3 can be produced.)
-
-The ``-set-init-undef`` option tells the ``sat`` command to initialize all
-registers to the undef (``x``) state. The way the ``x`` state is treated in
-Verilog will ensure that the solution will work for any initial state.
-
-The ``-max_undef`` option instructs the ``sat`` command to find a solution with
-a maximum number of undefs. This way we can see clearly which inputs bits are
-relevant to the solution.
-
-Finally the three ``-set-at`` options add constraints for the ``y`` signal to
-play the 1, 2, 3 sequence, starting with time step 4.
-
-It is not surprising that the solution sets ``d = 0`` in the first step, as this
-is the only way of setting the ``s1`` and ``s2`` registers to a known value. The
-input values for the other steps are a bit harder to work out manually, but the
-SAT solver finds the correct solution in an instant.
-
-There is much more to write about the ``sat`` command. For example, there is a
-set of options that can be used to performs sequential proofs using temporal
-induction :cite:p:`een2003temporal`. The command ``help sat`` can be used to
-print a list of all options with short descriptions of their functions.
-
-.. _conclusion:
-
-Conclusion
-==========
-
-Yosys provides a wide range of functions to analyze and investigate
-designs. For many cases it is sufficient to simply display circuit
-diagrams, maybe use some additional commands to narrow the scope of the
-circuit diagrams to the interesting parts of the circuit. But some cases
-require more than that. For this applications Yosys provides commands
-that can be used to further inspect the behavior of the circuit, either
-by evaluating which output values are generated from certain input
-values (``eval``) or by evaluation which input values and initial conditions
-can result in a certain behavior at the outputs (``sat``). The SAT command
-can even be used to prove (or disprove) theorems regarding the circuit,
-in more advanced cases with the additional help of a miter circuit.
-
-This features can be powerful tools for the circuit designer using Yosys
-as a utility for building circuits and the software developer using
-Yosys as a framework for new algorithms alike.
diff --git a/yosys/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst b/yosys/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst
index e9e44d1cd11..1874b014813 100644
--- a/yosys/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst
+++ b/yosys/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst
@@ -1,333 +1,353 @@
+:orphan:
+
 ====================================
 012: Converting Verilog to BTOR page
 ====================================
 
-Installation
-============
+Abstract
+========
+
+Verilog-2005 is a powerful Hardware Description Language (HDL) that can be used
+to easily create complex designs from small HDL code. BTOR is a bit-precise
+word-level format for model checking. It is a simple format and easy to parse.
+It allows to model the model checking problem over the theory of bit-vectors
+with one-dimensional arrays, thus enabling to model Verilog designs with
+registers and memories. Yosys is an Open-Source Verilog synthesis tool that can
+be used to convert Verilog designs with simple assertions to BTOR format.
+
+Download
+========
+
+This document was originally published in November 2013: 
+:download:`Converting Verilog to BTOR PDF</_downloads/APPNOTE_012_Verilog_to_BTOR.pdf>`
+
+..
+   Installation
+   ============
 
-Yosys written in C++ (using features from C++11) and is tested on modern Linux.
-It should compile fine on most UNIX systems with a C++11 compiler. The README
-file contains useful information on building Yosys and its prerequisites.
+   Yosys written in C++ (using features from C++11) and is tested on modern Linux.
+   It should compile fine on most UNIX systems with a C++11 compiler. The README
+   file contains useful information on building Yosys and its prerequisites.
 
-Yosys is a large and feature-rich program with some dependencies. For this work,
-we may deactivate other extra features such as TCL and ABC support in the
-Makefile.
+   Yosys is a large and feature-rich program with some dependencies. For this work,
+   we may deactivate other extra features such as TCL and ABC support in the
+   Makefile.
 
-This Application Note is based on `Yosys GIT`_ `Rev. 082550f` from 2015-04-04.
+   This Application Note is based on `Yosys GIT`_ `Rev. 082550f` from 2015-04-04.
 
-.. _Yosys GIT: https://github.com/YosysHQ/yosys
+   .. _Yosys GIT: https://github.com/YosysHQ/yosys
 
-.. _Rev. 082550f: https://github.com/YosysHQ/yosys/tree/082550f
+   .. _Rev. 082550f: https://github.com/YosysHQ/yosys/tree/082550f
 
-Quick start
-===========
+   Quick start
+   ===========
 
-We assume that the Verilog design is synthesizable and we also assume that the
-design does not have multi-dimensional memories. As BTOR implicitly initializes
-registers to zero value and memories stay uninitialized, we assume that the
-Verilog design does not contain initial blocks. For more details about the BTOR
-format, please refer to :cite:p:`btor`.
+   We assume that the Verilog design is synthesizable and we also assume that the
+   design does not have multi-dimensional memories. As BTOR implicitly initializes
+   registers to zero value and memories stay uninitialized, we assume that the
+   Verilog design does not contain initial blocks. For more details about the BTOR
+   format, please refer to :cite:p:`btor`.
 
-We provide a shell script ``verilog2btor.sh`` which can be used to convert a
-Verilog design to BTOR. The script can be found in the ``backends/btor``
-directory. The following example shows its usage:
+   We provide a shell script ``verilog2btor.sh`` which can be used to convert a
+   Verilog design to BTOR. The script can be found in the ``backends/btor``
+   directory. The following example shows its usage:
 
-.. code:: sh
+   .. code:: sh
 
-   verilog2btor.sh fsm.v fsm.btor test
+      verilog2btor.sh fsm.v fsm.btor test
 
-The script ``verilog2btor.sh`` takes three parameters. In the above example, the
-first parameter ``fsm.v`` is the input design, the second parameter ``fsm.btor``
-is the file name of BTOR output, and the third parameter ``test`` is the name of
-top module in the design.
+   The script ``verilog2btor.sh`` takes three parameters. In the above example, the
+   first parameter ``fsm.v`` is the input design, the second parameter ``fsm.btor``
+   is the file name of BTOR output, and the third parameter ``test`` is the name of
+   top module in the design.
 
-To specify the properties (that need to be checked), we have two
-options:
+   To specify the properties (that need to be checked), we have two
+   options:
 
--  We can use the Verilog ``assert`` statement in the procedural block or module
-   body of the Verilog design, as shown in :numref:`specifying_property_assert`.
-   This is the preferred option.
+   -  We can use the Verilog ``assert`` statement in the procedural block or module
+      body of the Verilog design, as shown in :numref:`specifying_property_assert`.
+      This is the preferred option.
 
--  We can use a single-bit output wire, whose name starts with ``safety``. The
-   value of this output wire needs to be driven low when the property is met,
-   i.e. the solver will try to find a model that makes the safety pin go high.
-   This is demonstrated in :numref:`specifying_property_output`.
+   -  We can use a single-bit output wire, whose name starts with ``safety``. The
+      value of this output wire needs to be driven low when the property is met,
+      i.e. the solver will try to find a model that makes the safety pin go high.
+      This is demonstrated in :numref:`specifying_property_output`.
 
-.. code-block:: verilog
-   :caption: Specifying property in Verilog design with ``assert``
-   :name: specifying_property_assert
+   .. code-block:: verilog
+      :caption: Specifying property in Verilog design with ``assert``
+      :name: specifying_property_assert
 
-   module test(input clk, input rst, output y);
+      module test(input clk, input rst, output y);
 
-     reg [2:0] state;
+      reg [2:0] state;
 
-     always @(posedge clk) begin
-       if (rst || state == 3) begin
-         state <= 0;
-       end else begin
-         assert(state < 3);
-         state <= state + 1;
-       end
-     end
+      always @(posedge clk) begin
+         if (rst || state == 3) begin
+            state <= 0;
+         end else begin
+            assert(state < 3);
+            state <= state + 1;
+         end
+      end
 
-     assign y = state[2];
+      assign y = state[2];
 
-     assert property (y !== 1'b1);
+      assert property (y !== 1'b1);
 
-   endmodule
+      endmodule
 
-.. code-block:: verilog
-   :caption: Specifying property in Verilog design with output wire
-   :name: specifying_property_output
+   .. code-block:: verilog
+      :caption: Specifying property in Verilog design with output wire
+      :name: specifying_property_output
 
-   module test(input clk, input rst,
-       output y, output safety1);
+      module test(input clk, input rst,
+         output y, output safety1);
 
-     reg [2:0] state;
+      reg [2:0] state;
 
-     always @(posedge clk) begin
-       if (rst || state == 3)
-         state <= 0;
-       else
-         state <= state + 1;
-     end
+      always @(posedge clk) begin
+         if (rst || state == 3)
+            state <= 0;
+         else
+            state <= state + 1;
+      end
 
-     assign y = state[2];
+      assign y = state[2];
 
-     assign safety1 = !(y !== 1'b1);
+      assign safety1 = !(y !== 1'b1);
 
-   endmodule
+      endmodule
 
-We can run `Boolector`_ ``1.4.1`` [1]_ on the generated BTOR file:
+   We can run `Boolector`_ ``1.4.1`` [1]_ on the generated BTOR file:
 
-.. _Boolector: http://fmv.jku.at/boolector/
+   .. _Boolector: http://fmv.jku.at/boolector/
 
-.. code:: sh
+   .. code:: sh
 
-   $ boolector fsm.btor
-   unsat
+      $ boolector fsm.btor
+      unsat
 
-We can also use `nuXmv`_, but on BTOR designs it does not support memories yet.
-With the next release of nuXmv, we will be also able to verify designs with
-memories.
+   We can also use `nuXmv`_, but on BTOR designs it does not support memories yet.
+   With the next release of nuXmv, we will be also able to verify designs with
+   memories.
 
-.. _nuXmv: https://es-static.fbk.eu/tools/nuxmv/index.php
+   .. _nuXmv: https://es-static.fbk.eu/tools/nuxmv/index.php
 
-Detailed flow
-=============
+   Detailed flow
+   =============
 
-Yosys is able to synthesize Verilog designs up to the gate level. We are
-interested in keeping registers and memories when synthesizing the design. For
-this purpose, we describe a customized Yosys synthesis flow, that is also
-provided by the ``verilog2btor.sh`` script. :numref:`btor_script_memory` shows
-the Yosys commands that are executed by ``verilog2btor.sh``.
+   Yosys is able to synthesize Verilog designs up to the gate level. We are
+   interested in keeping registers and memories when synthesizing the design. For
+   this purpose, we describe a customized Yosys synthesis flow, that is also
+   provided by the ``verilog2btor.sh`` script. :numref:`btor_script_memory` shows
+   the Yosys commands that are executed by ``verilog2btor.sh``.
 
-.. code-block:: yoscrypt
-   :caption: Synthesis Flow for BTOR with memories
-   :name: btor_script_memory
+   .. code-block:: yoscrypt
+      :caption: Synthesis Flow for BTOR with memories
+      :name: btor_script_memory
 
-   read_verilog -sv $1;
-   hierarchy -top $3; hierarchy -libdir $DIR;
-   hierarchy -check;
-   proc; opt;
-   opt_expr -mux_undef; opt;
-   rename -hide;;;
-   splice; opt;
-   memory_dff -wr_only; memory_collect;;
-   flatten;;
-   memory_unpack;
-   splitnets -driver;
-   setundef -zero -undriven;
-   opt;;;
-   write_btor $2;
+      read_verilog -sv $1;
+      hierarchy -top $3; hierarchy -libdir $DIR;
+      hierarchy -check;
+      proc; opt;
+      opt_expr -mux_undef; opt;
+      rename -hide;;;
+      splice; opt;
+      memory_dff -wr_only; memory_collect;;
+      flatten;;
+      memory_unpack;
+      splitnets -driver;
+      setundef -zero -undriven;
+      opt;;;
+      write_btor $2;
 
-Here is short description of what is happening in the script line by
-line:
+   Here is short description of what is happening in the script line by
+   line:
 
-#. Reading the input file.
+   #. Reading the input file.
 
-#. Setting the top module in the hierarchy and trying to read automatically the
-   files which are given as ``include`` in the file read in first line.
+   #. Setting the top module in the hierarchy and trying to read automatically the
+      files which are given as ``include`` in the file read in first line.
 
-#. Checking the design hierarchy.
+   #. Checking the design hierarchy.
 
-#. Converting processes to multiplexers (muxs) and flip-flops.
+   #. Converting processes to multiplexers (muxs) and flip-flops.
 
-#. Removing undef signals from muxs.
+   #. Removing undef signals from muxs.
 
-#. Hiding all signal names that are not used as module ports.
+   #. Hiding all signal names that are not used as module ports.
 
-#. Explicit type conversion, by introducing slice and concat cells in the
-   circuit.
+   #. Explicit type conversion, by introducing slice and concat cells in the
+      circuit.
 
-#. Converting write memories to synchronous memories, and collecting the
-   memories to multi-port memories.
+   #. Converting write memories to synchronous memories, and collecting the
+      memories to multi-port memories.
 
-#. Flattening the design to get only one module.
+   #. Flattening the design to get only one module.
 
-#. Separating read and write memories.
+   #. Separating read and write memories.
 
-#. Splitting the signals that are partially assigned
+   #. Splitting the signals that are partially assigned
 
-#. Setting undef to zero value.
+   #. Setting undef to zero value.
 
-#. Final optimization pass.
+   #. Final optimization pass.
 
-#. Writing BTOR file.
+   #. Writing BTOR file.
 
-For detailed description of the commands mentioned above, please refer
-to the Yosys documentation, or run ``yosys -h <command_name>``.
-
-The script presented earlier can be easily modified to have a BTOR file that
-does not contain memories. This is done by removing the line number 8 and 10,
-and introduces a new command ``memory`` at line number 8.
-:numref:`btor_script_without_memory` shows the modified Yosys script file:
-
-.. code-block:: sh
-   :caption: Synthesis Flow for BTOR without memories
-   :name: btor_script_without_memory
-
-   read_verilog -sv $1;
-   hierarchy -top $3; hierarchy -libdir $DIR;
-   hierarchy -check;
-   proc; opt;
-   opt_expr -mux_undef; opt;
-   rename -hide;;;
-   splice; opt;
-   memory;;
-   flatten;;
-   splitnets -driver;
-   setundef -zero -undriven;
-   opt;;;
-   write_btor $2;
-
-Example
-=======
-
-Here is an example Verilog design that we want to convert to BTOR:
-
-.. code-block:: verilog
-   :caption: Example - Verilog Design
-   :name: example_verilog
-
-   module array(input clk);
-
-     reg [7:0] counter;
-     reg [7:0] mem [7:0];
-
-     always @(posedge clk) begin
-       counter <= counter + 8'd1;
-       mem[counter] <= counter;
-     end
-
-     assert property (!(counter > 8'd0) ||
-       mem[counter - 8'd1] == counter - 8'd1);
-
-   endmodule
-
-The generated BTOR file that contain memories, using the script shown in
-:numref:`btor_memory`:
-
-.. code-block::
-   :caption: Example - Converted BTOR with memory
-   :name: btor_memory
-
-   1 var 1 clk
-   2 array 8 3
-   3 var 8 $auto$rename.cc:150:execute$20
-   4 const 8 00000001
-   5 sub 8 3 4
-   6 slice 3 5 2 0
-   7 read 8 2 6
-   8 slice 3 3 2 0
-   9 add 8 3 4
-   10 const 8 00000000
-   11 ugt 1 3 10
-   12 not 1 11
-   13 const 8 11111111
-   14 slice 1 13 0 0
-   15 one 1
-   16 eq 1 1 15
-   17 and 1 16 14
-   18 write 8 3 2 8 3
-   19 acond 8 3 17 18 2
-   20 anext 8 3 2 19
-   21 eq 1 7 5
-   22 or 1 12 21
-   23 const 1 1
-   24 one 1
-   25 eq 1 23 24
-   26 cond 1 25 22 24
-   27 root 1 -26
-   28 cond 8 1 9 3
-   29 next 8 3 28
-
-And the BTOR file obtained by the script shown in
-:numref:`btor_without_memory`, which expands the memory into individual
-elements:
-
-.. code-block::
-   :caption: Example - Converted BTOR with memory
-   :name: btor_without_memory
-
-   1 var 1 clk
-   2 var 8 mem[0]
-   3 var 8 $auto$rename.cc:150:execute$20
-   4 slice 3 3 2 0
-   5 slice 1 4 0 0
-   6 not 1 5
-   7 slice 1 4 1 1
-   8 not 1 7
-   9 slice 1 4 2 2
-   10 not 1 9
-   11 and 1 8 10
-   12 and 1 6 11
-   13 cond 8 12 3 2
-   14 cond 8 1 13 2
-   15 next 8 2 14
-   16 const 8 00000001
-   17 add 8 3 16
-   18 const 8 00000000
-   19 ugt 1 3 18
-   20 not 1 19
-   21 var 8 mem[2]
-   22 and 1 7 10
-   23 and 1 6 22
-   24 cond 8 23 3 21
-   25 cond 8 1 24 21
-   26 next 8 21 25
-   27 sub 8 3 16
-
-   ...
-
-   54 cond 1 53 50 52
-   55 root 1 -54
-
-   ...
-
-   77 cond 8 76 3 44
-   78 cond 8 1 77 44
-   79 next 8 44 78
-
-Limitations
-===========
-
-BTOR does not support initialization of memories and registers, i.e. they are
-implicitly initialized to value zero, so the initial block for memories need to
-be removed when converting to BTOR. It should also be kept in consideration that
-BTOR does not support the ``x`` or ``z`` values of Verilog.
-
-Another thing to bear in mind is that Yosys will convert multi-dimensional
-memories to one-dimensional memories and address decoders. Therefore
-out-of-bounds memory accesses can yield unexpected results.
-
-Conclusion
-==========
-
-Using the described flow, we can use Yosys to generate word-level verification
-benchmarks with or without memories from Verilog designs.
-
-.. [1]
-   Newer version of Boolector do not support sequential models.
-   Boolector 1.4.1 can be built with picosat-951. Newer versions of
-   picosat have an incompatible API.
+   For detailed description of the commands mentioned above, please refer
+   to the Yosys documentation, or run ``yosys -h <command_name>``.
+
+   The script presented earlier can be easily modified to have a BTOR file that
+   does not contain memories. This is done by removing the line number 8 and 10,
+   and introduces a new command :cmd:ref:`memory` at line number 8.
+   :numref:`btor_script_without_memory` shows the modified Yosys script file:
+
+   .. code-block:: sh
+      :caption: Synthesis Flow for BTOR without memories
+      :name: btor_script_without_memory
+
+      read_verilog -sv $1;
+      hierarchy -top $3; hierarchy -libdir $DIR;
+      hierarchy -check;
+      proc; opt;
+      opt_expr -mux_undef; opt;
+      rename -hide;;;
+      splice; opt;
+      memory;;
+      flatten;;
+      splitnets -driver;
+      setundef -zero -undriven;
+      opt;;;
+      write_btor $2;
+
+   Example
+   =======
+
+   Here is an example Verilog design that we want to convert to BTOR:
+
+   .. code-block:: verilog
+      :caption: Example - Verilog Design
+      :name: example_verilog
+
+      module array(input clk);
+
+      reg [7:0] counter;
+      reg [7:0] mem [7:0];
+
+      always @(posedge clk) begin
+         counter <= counter + 8'd1;
+         mem[counter] <= counter;
+      end
+
+      assert property (!(counter > 8'd0) ||
+         mem[counter - 8'd1] == counter - 8'd1);
+
+      endmodule
+
+   The generated BTOR file that contain memories, using the script shown in
+   :numref:`btor_memory`:
+
+   .. code-block::
+      :caption: Example - Converted BTOR with memory
+      :name: btor_memory
+
+      1 var 1 clk
+      2 array 8 3
+      3 var 8 $auto$rename.cc:150:execute$20
+      4 const 8 00000001
+      5 sub 8 3 4
+      6 slice 3 5 2 0
+      7 read 8 2 6
+      8 slice 3 3 2 0
+      9 add 8 3 4
+      10 const 8 00000000
+      11 ugt 1 3 10
+      12 not 1 11
+      13 const 8 11111111
+      14 slice 1 13 0 0
+      15 one 1
+      16 eq 1 1 15
+      17 and 1 16 14
+      18 write 8 3 2 8 3
+      19 acond 8 3 17 18 2
+      20 anext 8 3 2 19
+      21 eq 1 7 5
+      22 or 1 12 21
+      23 const 1 1
+      24 one 1
+      25 eq 1 23 24
+      26 cond 1 25 22 24
+      27 root 1 -26
+      28 cond 8 1 9 3
+      29 next 8 3 28
+
+   And the BTOR file obtained by the script shown in
+   :numref:`btor_without_memory`, which expands the memory into individual
+   elements:
+
+   .. code-block::
+      :caption: Example - Converted BTOR with memory
+      :name: btor_without_memory
+
+      1 var 1 clk
+      2 var 8 mem[0]
+      3 var 8 $auto$rename.cc:150:execute$20
+      4 slice 3 3 2 0
+      5 slice 1 4 0 0
+      6 not 1 5
+      7 slice 1 4 1 1
+      8 not 1 7
+      9 slice 1 4 2 2
+      10 not 1 9
+      11 and 1 8 10
+      12 and 1 6 11
+      13 cond 8 12 3 2
+      14 cond 8 1 13 2
+      15 next 8 2 14
+      16 const 8 00000001
+      17 add 8 3 16
+      18 const 8 00000000
+      19 ugt 1 3 18
+      20 not 1 19
+      21 var 8 mem[2]
+      22 and 1 7 10
+      23 and 1 6 22
+      24 cond 8 23 3 21
+      25 cond 8 1 24 21
+      26 next 8 21 25
+      27 sub 8 3 16
+
+      ...
+
+      54 cond 1 53 50 52
+      55 root 1 -54
+
+      ...
+
+      77 cond 8 76 3 44
+      78 cond 8 1 77 44
+      79 next 8 44 78
+
+   Limitations
+   ===========
+
+   BTOR does not support initialization of memories and registers, i.e. they are
+   implicitly initialized to value zero, so the initial block for memories need to
+   be removed when converting to BTOR. It should also be kept in consideration that
+   BTOR does not support the ``x`` or ``z`` values of Verilog.
+
+   Another thing to bear in mind is that Yosys will convert multi-dimensional
+   memories to one-dimensional memories and address decoders. Therefore
+   out-of-bounds memory accesses can yield unexpected results.
+
+   Conclusion
+   ==========
+
+   Using the described flow, we can use Yosys to generate word-level verification
+   benchmarks with or without memories from Verilog designs.
+
+   .. [1]
+      Newer version of Boolector do not support sequential models.
+      Boolector 1.4.1 can be built with picosat-951. Newer versions of
+      picosat have an incompatible API.
diff --git a/yosys/docs/source/appendix/CHAPTER_Auxlibs.rst b/yosys/docs/source/appendix/CHAPTER_Auxlibs.rst
deleted file mode 100644
index 361f00e025b..00000000000
--- a/yosys/docs/source/appendix/CHAPTER_Auxlibs.rst
+++ /dev/null
@@ -1,42 +0,0 @@
-Auxiliary libraries
-===================
-
-The Yosys source distribution contains some auxiliary libraries that are bundled
-with Yosys.
-
-SHA1
-----
-
-The files in ``libs/sha1/`` provide a public domain SHA1 implementation written
-by Steve Reid, Bruce Guenter, and Volker Grabsch. It is used for generating
-unique names when specializing parameterized modules.
-
-BigInt
-------
-
-The files in ``libs/bigint/`` provide a library for performing arithmetic with
-arbitrary length integers. It is written by Matt McCutchen.
-
-The BigInt library is used for evaluating constant expressions, e.g. using the
-ConstEval class provided in kernel/consteval.h.
-
-See also: http://mattmccutchen.net/bigint/
-
-.. _sec:SubCircuit:
-
-SubCircuit
-----------
-
-The files in ``libs/subcircuit`` provide a library for solving the subcircuit
-isomorphism problem. It is written by C. Wolf and based on the Ullmann Subgraph
-Isomorphism Algorithm :cite:p:`UllmannSubgraphIsomorphism`. It is used by the
-extract pass (see :doc:`../cmd/extract`).
-
-ezSAT
------
-
-The files in ``libs/ezsat`` provide a library for simplifying generating CNF
-formulas for SAT solvers. It also contains bindings of MiniSAT. The ezSAT
-library is written by C. Wolf. It is used by the sat pass (see
-:doc:`../cmd/sat`).
-
diff --git a/yosys/docs/source/appendix/CHAPTER_Auxprogs.rst b/yosys/docs/source/appendix/CHAPTER_Auxprogs.rst
deleted file mode 100644
index e4f6f62cfb6..00000000000
--- a/yosys/docs/source/appendix/CHAPTER_Auxprogs.rst
+++ /dev/null
@@ -1,29 +0,0 @@
-Auxiliary programs
-==================
-
-Besides the main yosys executable, the Yosys distribution contains a set of
-additional helper programs.
-
-yosys-config
-------------
-
-The yosys-config tool (an auto-generated shell-script) can be used to query
-compiler options and other information needed for building loadable modules for
-Yosys. See Sec. \ :numref:`chapter:prog` for details.
-
-.. _sec:filterlib:
-
-yosys-filterlib
----------------
-
-The yosys-filterlib tool is a small utility that can be used to strip or extract
-information from a Liberty file. See :numref:`Sec. %s <sec:techmap_extern>` for
-details.
-
-yosys-abc
----------
-
-This is a fork of ABC with a small set of custom modifications that have not yet
-been accepted upstream. Not all versions of Yosys work with all versions of ABC.
-So Yosys comes with its own yosys-abc to avoid compatibility issues between the
-two.
diff --git a/yosys/docs/source/appendix/CHAPTER_StateOfTheArt.rst b/yosys/docs/source/appendix/CHAPTER_StateOfTheArt.rst
deleted file mode 100644
index 894d0fbbe2b..00000000000
--- a/yosys/docs/source/appendix/CHAPTER_StateOfTheArt.rst
+++ /dev/null
@@ -1,410 +0,0 @@
-.. _chapter:sota:
-
-Evaluation of other OSS Verilog Synthesis Tools
-===============================================
-
-In this appendix [1]_ the existing FOSS Verilog synthesis tools [2]_ are
-evaluated. Extremely limited or application specific tools (e.g. pure
-Verilog Netlist parsers) as well as Verilog simulators are not included.
-These existing solutions are tested using a set of representative
-Verilog code snippets. It is shown that no existing FOSS tool implements
-even close to a sufficient subset of Verilog to be usable as synthesis
-tool for a wide range existing Verilog code.
-
-The packages evaluated are:
-
--  Icarus Verilog  [3]_
-
--  Verilog-to-Routing (VTR) / Odin-II
-   :cite:p:`vtr2012}`:raw-latex:`\cite{Odin`
-
--  HDL Analyzer and Netlist Architect (HANA)
-
--  Verilog front-end to VIS (vl2mv) :cite:p:`Cheng93vl2mv:a`
-
-In each of the following sections Verilog modules that test a certain
-Verilog language feature are presented and the support for these
-features is tested in all the tools mentioned above. It is evaluated
-whether the tools under test successfully generate netlists for the
-Verilog input and whether these netlists match the simulation behavior
-of the designs using testbenches.
-
-All test cases are verified to be synthesizeable using Xilinx XST from
-the Xilinx WebPACK suite.
-
-Trivial features such as support for simple structural Verilog are not
-explicitly tested.
-
-Vl2mv and Odin-II generate output in the BLIF (Berkeley Logic
-Interchange Format) and BLIF-MV (an extended version of BLIF) formats
-respectively. ABC is used to convert this output to Verilog for
-verification using testbenches.
-
-Icarus Verilog generates EDIF (Electronic Design Interchange Format)
-output utilizing LPM (Library of Parameterized Modules) cells. The EDIF
-files are converted to Verilog using edif2ngd and netgen from Xilinx
-WebPACK. A hand-written implementation of the LPM cells utilized by the
-generated netlists is used for verification.
-
-Following these functional tests, a quick analysis of the extensibility
-of the tools under test is provided in a separate section.
-
-The last section of this chapter finally concludes these series of
-evaluations with a summary of the results.
-
-.. code:: verilog
-   :number-lines:
-
-   module uut_always01(clock,
-   		reset, count);
-
-   input clock, reset;
-   output [3:0] count;
-   reg [3:0] count;
-
-   always @(posedge clock)
-   	count <= reset ?
-   		0 : count + 1;
-
-
-
-   endmodule
-
-.. code:: verilog
-
-   module uut_always02(clock,
-   		reset, count);
-
-   input clock, reset;
-   output [3:0] count;
-   reg [3:0] count;
-
-   always @(posedge clock) begin
-   	count <= count + 1;
-   	if (reset)
-   		count <= 0;
-   end
-
-   endmodule
-
-[fig:StateOfTheArt_always12]
-
-.. code:: verilog
-   :number-lines:
-
-   module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7,
-   		out1, out2, out3);
-
-   input clock, in1, in2, in3, in4, in5, in6, in7;
-   output out1, out2, out3;
-   reg out1, out2, out3;
-
-   always @(posedge clock) begin
-   	out1 = in1;
-   	if (in2)
-   		out1 = !out1;
-   	out2 <= out1;
-   	if (in3)
-   		out2 <= out2;
-   	if (in4)
-   		if (in5)
-   			out3 <= in6;
-   		else
-   			out3 <= in7;
-   	out1 = out1 ^ out2;
-   end
-
-   endmodule
-
-[fig:StateOfTheArt_always3]
-
-.. _sec:blocking_nonblocking:
-
-Always blocks and blocking vs. nonblocking assignments
-------------------------------------------------------
-
-The "always"-block is one of the most fundamental non-trivial Verilog
-language features. It can be used to model a combinatorial path (with
-optional registers on the outputs) in a way that mimics a regular
-programming language.
-
-Within an always block, if- and case-statements can be used to model
-multiplexers. Blocking assignments (:math:`=`) and nonblocking
-assignments (:math:`<=`) are used to populate the leaf-nodes of these
-multiplexer trees. Unassigned leaf-nodes default to feedback paths that
-cause the output register to hold the previous value. More advanced
-synthesis tools often convert these feedback paths to register enable
-signals or even generate circuits with clock gating.
-
-Registers assigned with nonblocking assignments (:math:`<=`) behave
-differently from variables in regular programming languages: In a
-simulation they are not updated immediately after being assigned.
-Instead the right-hand sides are evaluated and the results stored in
-temporary memory locations. After all pending updates have been prepared
-in this way they are executed, thus yielding semi-parallel execution of
-all nonblocking assignments.
-
-For synthesis this means that every occurrence of that register in an
-expression addresses the output port of the corresponding register
-regardless of the question whether the register has been assigned a new
-value in an earlier command in the same always block. Therefore with
-nonblocking assignments the order of the assignments has no effect on
-the resulting circuit as long as the left-hand sides of the assignments
-are unique.
-
-The three example codes in
-:numref:`Fig. %s <fig:StateOfTheArt_always12>`
-and :numref:`Fig. %s <fig:StateOfTheArt_always3>`
-use all these features and can thus be used to test the synthesis tools
-capabilities to synthesize always blocks correctly.
-
-The first example is only using the most fundamental Verilog features.
-All tools under test were able to successfully synthesize this design.
-
-.. code:: verilog
-   :number-lines:
-
-   module uut_arrays01(clock, we, addr, wr_data, rd_data);
-
-   input clock, we;
-   input [3:0] addr, wr_data;
-   output [3:0] rd_data;
-   reg [3:0] rd_data;
-
-   reg [3:0] memory [15:0];
-
-   always @(posedge clock) begin
-   	if (we)
-   		memory[addr] <= wr_data;
-   	rd_data <= memory[addr];
-   end
-
-   endmodule
-
-[fig:StateOfTheArt_arrays]
-
-The 2nd example is functionally identical to the 1st one but is using an
-if-statement inside the always block. Odin-II fails to synthesize it and
-instead produces the following error message:
-
-::
-
-   ERROR: (File: always02.v) (Line number: 13)
-   You've defined the driver "count~0" twice
-
-Vl2mv does not produce an error message but outputs an invalid synthesis
-result that is not using the reset input at all.
-
-Icarus Verilog also doesn't produce an error message but generates an
-invalid output for this 2nd example. The code generated by Icarus
-Verilog only implements the reset path for the count register,
-effectively setting the output to constant 0.
-
-So of all tools under test only HANA was able to create correct
-synthesis results for the 2nd example.
-
-The 3rd example is using blocking and nonblocking assignments and many
-if statements. Odin also fails to synthesize this example:
-
-::
-
-   ERROR: (File: always03.v) (Line number: 8)
-   ODIN doesn't handle blocking statements in Sequential blocks
-
-HANA, Icarus Verilog and vl2mv create invalid synthesis results for the
-3rd example.
-
-So unfortunately none of the tools under test provide a complete and
-correct implementation of blocking and nonblocking assignments.
-
-Arrays for memory modelling
----------------------------
-
-Verilog arrays are part of the synthesizeable subset of Verilog and are
-commonly used to model addressable memory. The Verilog code in
-:numref:`Fig. %s <fig:StateOfTheArt_arrays>`
-demonstrates this by implementing a single port memory.
-
-For this design HANA, vl2m and ODIN-II generate error messages
-indicating that arrays are not supported.
-
-.. code:: verilog
-   :number-lines:
-
-   module uut_forgen01(a, y);
-
-   input [4:0] a;
-   output y;
-
-   integer i, j;
-   reg [31:0] lut;
-
-   initial begin
-   	for (i = 0; i < 32; i = i+1) begin
-   		lut[i] = i > 1;
-   		for (j = 2; j*j <= i; j = j+1)
-   			if (i % j == 0)
-   				lut[i] = 0;
-   	end
-   end
-
-   assign y = lut[a];
-
-   endmodule
-
-[fig:StateOfTheArt_for]
-
-Icarus Verilog produces an invalid output that is using the address only
-for reads. Instead of using the address input for writes, the generated
-design simply loads the data to all memory locations whenever the
-write-enable input is active, effectively turning the design into a
-single 4-bit D-Flip-Flop with enable input.
-
-As all tools under test already fail this simple test, there is nothing
-to gain by continuing tests on this aspect of Verilog synthesis such as
-synthesis of dual port memories, correct handling of write collisions,
-and so forth.
-
-.. code:: verilog
-   :number-lines:
-
-   module uut_forgen02(a, b, cin, y, cout);
-
-   parameter WIDTH = 8;
-
-   input [WIDTH-1:0] a, b;
-   input cin;
-
-   output [WIDTH-1:0] y;
-   output cout;
-
-   genvar i;
-   wire [WIDTH-1:0] carry;
-
-   generate
-   	for (i = 0; i < WIDTH; i=i+1) begin:adder
-   		wire [2:0] D;
-   		assign D[1:0] = { a[i], b[i] };
-   		if (i == 0) begin:chain
-   			assign D[2] = cin;
-   		end else begin:chain
-   			assign D[2] = carry[i-1];
-   		end
-   		assign y[i] = ^D;
-   		assign carry[i] = &D[1:0] | (^D[1:0] & D[2]);
-   	end
-   endgenerate
-
-   assign cout = carry[WIDTH-1];
-
-   endmodule
-
-[fig:StateOfTheArt_gen]
-
-For-loops and generate blocks
------------------------------
-
-For-loops and generate blocks are more advanced Verilog features. These
-features allow the circuit designer to add program code to her design
-that is evaluated during synthesis to generate (parts of) the circuits
-description; something that could only be done using a code generator
-otherwise.
-
-For-loops are only allowed in synthesizeable Verilog if they can be
-completely unrolled. Then they can be a powerful tool to generate array
-logic or static lookup tables. The code in
-:numref:`Fig. %s <fig:StateOfTheArt_for>` generates a
-circuit that tests a 5 bit value for being a prime number using a static
-lookup table.
-
-Generate blocks can be used to model array logic in complex parametric
-designs. The code in
-:numref:`Fig. %s <fig:StateOfTheArt_gen>` implements a
-ripple-carry adder with parametric width from simple assign-statements
-and logic operations using a Verilog generate block.
-
-All tools under test failed to synthesize both test cases. HANA creates
-invalid output in both cases. Icarus Verilog creates invalid output for
-the first test and fails with an error for the second case. The other
-two tools fail with error messages for both tests.
-
-Extensibility
--------------
-
-This section briefly discusses the extensibility of the tools under test
-and their internal data- and control-flow. As all tools under test
-already failed to synthesize simple Verilog always-blocks correctly, not
-much resources have been spent on evaluating the extensibility of these
-tools and therefore only a very brief discussion of the topic is
-provided here.
-
-HANA synthesizes for a built-in library of standard cells using two
-passes over an AST representation of the Verilog input. This approach
-executes fast but limits the extensibility as everything happens in only
-two comparable complex AST walks and there is no universal intermediate
-representation that is flexible enough to be used in arbitrary
-optimizations.
-
-Odin-II and vl2m are both front ends to existing synthesis flows. As
-such they only try to quickly convert the Verilog input into the
-internal representation of their respective flows (BLIF). So
-extensibility is less of an issue here as potential extensions would
-likely be implemented in other components of the flow.
-
-Icarus Verilog is clearly designed to be a simulation tool rather than a
-synthesis tool. The synthesis part of Icarus Verilog is an ad-hoc add-on
-to Icarus Verilog that aims at converting an internal representation
-that is meant for generation of a virtual machine based simulation code
-to netlists.
-
-Summary and Outlook
--------------------
-
-Table \ :numref:`tab:StateOfTheArt_sum` summarizes
-the tests performed. Clearly none of the tools under test make a serious
-attempt at providing a feature-complete implementation of Verilog. It
-can be argued that Odin-II performed best in the test as it never
-generated incorrect code but instead produced error messages indicating
-that unsupported Verilog features where used in the Verilog input.
-
-In conclusion, to the best knowledge of the author, there is no FOSS
-Verilog synthesis tool other than Yosys that is anywhere near feature
-completeness and therefore there is no other candidate for a generic
-Verilog front end and/or synthesis framework to be used as a basis for
-custom synthesis tools.
-
-Yosys could also replace vl2m and/or Odin-II in their respective flows
-or function as a pre-compiler that can translate full-featured Verilog
-code to the simple subset of Verilog that is understood by vl2m and
-Odin-II.
-
-Yosys is designed for extensibility. It can be used as-is to synthesize
-Verilog code to netlists, but its main purpose is to be used as basis
-for custom tools. Yosys is structured in a language dependent Verilog
-front end and language independent synthesis code (which is in itself
-structured in independent passes). This architecture will simplify
-implementing additional HDL front ends and/or additional synthesis
-passes.
-
-Chapter \ :numref:`<CHAPTER_eval>` contains a more detailed
-evaluation of Yosys using real-world designs that are far out of reach
-for any of the other tools discussed in this appendix.
-
-…passed 2em …produced error 2em :math:`\skull` …incorrect output
-
-[tab:StateOfTheArt_sum]
-
-.. [1]
-   This appendix is an updated version of an unpublished student
-   research paper. :cite:p:`VerilogFossEval`
-
-.. [2]
-   To the author's best knowledge, all relevant tools that existed at
-   the time of this writing are included. But as there is no formal
-   channel through which such tools are published it is hard to give any
-   guarantees in that matter.
-
-.. [3]
-   Icarus Verilog is mainly a simulation tool but also supported
-   synthesis up to version 0.8. Therefore version 0.8.7 is used for this
-   evaluation.)
diff --git a/yosys/docs/source/appendix/auxlibs.rst b/yosys/docs/source/appendix/auxlibs.rst
new file mode 100644
index 00000000000..321cb52c4d1
--- /dev/null
+++ b/yosys/docs/source/appendix/auxlibs.rst
@@ -0,0 +1,81 @@
+Auxiliary libraries
+===================
+
+The Yosys source distribution contains some auxiliary libraries that are
+compiled into Yosys and can be used in plugins.
+
+BigInt
+------
+
+The files in ``libs/bigint/`` provide a library for performing arithmetic with
+arbitrary length integers. It is written by Matt McCutchen.
+
+The BigInt library is used for evaluating constant expressions, e.g. using the
+ConstEval class provided in kernel/consteval.h.
+
+See also: http://mattmccutchen.net/bigint/
+
+dlfcn-win32
+-----------
+
+The ``dlfcn`` library enables runtime loading of plugins without requiring
+recompilation of Yosys.  The files in ``libs/dlfcn-win32`` provide an
+implementation of ``dlfcn`` for Windows.
+
+See also: https://github.com/dlfcn-win32/dlfcn-win32
+
+ezSAT
+-----
+
+The files in ``libs/ezsat`` provide a library for simplifying generating CNF
+formulas for SAT solvers. It also contains bindings of MiniSAT. The ezSAT
+library is written by C. Wolf. It is used by the :cmd:ref:`sat` pass (see
+:doc:`/cmd/sat`).
+
+fst
+---
+
+``libfst`` files from `gtkwave`_ are included in ``libs/fst`` to support
+reading/writing signal traces from/to the GTKWave developed FST format.  This is
+primarily used in the :cmd:ref:`sim` command.
+
+.. _gtkwave: https://github.com/gtkwave/gtkwave
+
+json11
+------
+
+For reading/writing designs from/to JSON, :cmd:ref:`read_json` and
+:cmd:ref:`write_json` should be used.  For everything else there is the `json11
+library`_:
+
+   json11 is a tiny JSON library for C++11, providing JSON parsing and
+   serialization.
+
+This library is used for outputting machine-readable statistics (:cmd:ref:`stat`
+with ``-json`` flag), using the RPC frontend (:cmd:ref:`connect_rpc`), and the
+yosys-witness ``yw`` format.
+
+.. _json11 library: https://github.com/dropbox/json11
+
+MiniSAT
+-------
+
+The files in ``libs/minisat`` provide a high-performance SAT solver, used by the
+:cmd:ref:`sat` command.
+
+SHA1
+----
+
+The files in ``libs/sha1/`` provide a public domain SHA1 implementation written
+by Steve Reid, Bruce Guenter, and Volker Grabsch. It is used for generating
+unique names when specializing parameterized modules.
+
+.. _sec:SubCircuit:
+
+SubCircuit
+----------
+
+The files in ``libs/subcircuit`` provide a library for solving the subcircuit
+isomorphism problem. It is written by C. Wolf and based on the Ullmann Subgraph
+Isomorphism Algorithm :cite:p:`UllmannSubgraphIsomorphism`. It is used by the
+extract pass (see :doc:`../cmd/extract`).
diff --git a/yosys/docs/source/appendix/auxprogs.rst b/yosys/docs/source/appendix/auxprogs.rst
new file mode 100644
index 00000000000..c239136b64e
--- /dev/null
+++ b/yosys/docs/source/appendix/auxprogs.rst
@@ -0,0 +1,62 @@
+Auxiliary programs
+==================
+
+Besides the main yosys executable, the Yosys distribution contains a set of
+additional helper programs.
+
+yosys-config
+------------
+
+The ``yosys-config`` tool (an auto-generated shell-script) can be used to query
+compiler options and other information needed for building loadable modules for
+Yosys. See :doc:`/yosys_internals/extending_yosys/extensions` for details.
+
+.. literalinclude:: /generated/yosys-config
+    :start-at: Usage
+
+.. _sec:filterlib:
+
+yosys-filterlib
+---------------
+
+.. todo:: how does a filterlib rules-file work?
+
+The ``yosys-filterlib`` tool is a small utility that can be used to strip or
+extract information from a Liberty file.  This can be useful for removing
+sensitive or proprietary information such as timing or other trade secrets.
+
+.. literalinclude:: /generated/yosys-filterlib
+    :start-at: Usage
+
+yosys-abc
+---------
+
+This is a fork of ABC with a small set of custom modifications that have not yet
+been accepted upstream. Not all versions of Yosys work with all versions of ABC.
+So Yosys comes with its own yosys-abc to avoid compatibility issues between the
+two.
+
+.. literalinclude:: /generated/yosys-abc
+    :start-at: usage
+
+yosys-smtbmc
+------------
+
+The ``yosys-smtbmc`` tool is a utility used by SBY for interacting with smt
+solvers.
+
+.. literalinclude:: /generated/yosys-smtbmc
+
+yosys-witness
+-------------
+
+``yosys-witness`` is a new tool to inspect and convert yosys witness traces.
+This is used in SBY and SCY for producing traces in a consistent format
+independent of the solver.
+
+.. literalinclude:: /generated/yosys-witness
+    :start-at: Usage
+
+.. note:: ``yosys-witness`` requires `click`_ Python package for use.
+
+.. _click: https://pypi.org/project/click/
diff --git a/yosys/docs/source/appendix/env_vars.rst b/yosys/docs/source/appendix/env_vars.rst
new file mode 100644
index 00000000000..26cc37c8133
--- /dev/null
+++ b/yosys/docs/source/appendix/env_vars.rst
@@ -0,0 +1,31 @@
+Yosys environment variables
+===========================
+
+``HOME``
+   Yosys command history is stored in :file:`$HOME/.yosys_history`.  Graphics
+   (from :cmd:ref:`show` and :cmd:ref:`viz` commands) will output to this
+   directory by default.  This environment variable is also used in some cases
+   for resolving filenames with :file:`~`.
+
+``PATH``
+   May be used in OpenBSD builds for finding the location of Yosys executable.
+
+``TMPDIR``
+   Used for storing temporary files.
+
+``ABC``
+   When compiling Yosys with out-of-tree ABC using :makevar:`ABCEXTERNAL`, this
+   variable can be used to override the external ABC executable.
+
+``YOSYS_NOVERIFIC``
+   If Yosys was built with Verific, this environment variable can be used to
+   temporarily disable Verific support.
+
+``YOSYS_COVER_DIR`` and ``YOSYS_COVER_FILE``
+   When using code coverage, these environment variables control the output file
+   name/location.
+
+``YOSYS_ABORT_ON_LOG_ERROR``
+   Can be used for debugging Yosys internals.  Setting it to 1 causes abort() to
+   be called when Yosys terminates with an error message.
+
diff --git a/yosys/docs/source/CHAPTER_Basics.rst b/yosys/docs/source/appendix/primer.rst
similarity index 97%
rename from yosys/docs/source/CHAPTER_Basics.rst
rename to yosys/docs/source/appendix/primer.rst
index 618bec545a9..50656af780e 100644
--- a/yosys/docs/source/CHAPTER_Basics.rst
+++ b/yosys/docs/source/appendix/primer.rst
@@ -3,8 +3,8 @@
 
 .. _chapter:basics:
 
-Basic principles
-================
+A primer on digital circuit synthesis
+=====================================
 
 This chapter contains a short introduction to the basic principles of digital
 circuit synthesis.
@@ -23,8 +23,8 @@ circuit to a functionally equivalent low-level representation of a circuit.
 :numref:`Figure %s <fig:Basics_abstractions>` lists the different levels of
 abstraction and how they relate to different kinds of synthesis.
 
-.. figure:: ../images/basics_abstractions.*
-	:class: width-helper
+.. figure:: /_images/primer/basics_abstractions.*
+	:class: width-helper invert-helper
 	:name: fig:Basics_abstractions
 
 	Different levels of abstraction and synthesis.
@@ -161,7 +161,7 @@ At the logical gate level the design is represented by a netlist that uses only
 cells from a small number of single-bit cells, such as basic logic gates (AND,
 OR, NOT, XOR, etc.) and registers (usually D-Type Flip-flops).
 
-A number of netlist formats exists that can be used on this level, e.g. the
+A number of netlist formats exists that can be used on this level, e.g. the
 Electronic Design Interchange Format (EDIF), but for ease of simulation often a
 HDL netlist is used. The latter is a HDL file (Verilog or VHDL) that only uses
 the most basic language constructs for instantiation and connecting of cells.
@@ -172,7 +172,7 @@ good) mapping of the logic gate netlist to an equivalent netlist of physically
 available gate types.
 
 The simplest approach to logic synthesis is two-level logic synthesis, where a
-logic function is converted into a sum-of-products representation, e.g. using a
+logic function is converted into a sum-of-products representation, e.g. using a
 Karnaugh map. This is a simple approach, but has exponential worst-case effort
 and cannot make efficient use of physical gates other than AND/NAND-, OR/NOR-
 and NOT-Gates.
@@ -196,7 +196,7 @@ Physical gate level
 On the physical gate level only gates are used that are physically available on
 the target architecture. In some cases this may only be NAND, NOR and NOT gates
 as well as D-Type registers. In other cases this might include cells that are
-more complex than the cells used at the logical gate level (e.g. complete
+more complex than the cells used at the logical gate level (e.g. complete
 half-adders). In the case of an FPGA-based design the physical gate level
 representation is a netlist of LUTs with optional output registers, as these are
 the basic building blocks of FPGA logic cells.
@@ -345,7 +345,7 @@ covered by the Verilog synthesis standard and when writing new designs one
 should limit herself or himself to these cases.
 
 In behavioural modelling, blocking assignments (=) and non-blocking assignments
-(<=) can be used. The concept of blocking vs. non-blocking assignment is one of
+(<=) can be used. The concept of blocking vs. non-blocking assignment is one of
 the most misunderstood constructs in Verilog :cite:p:`Cummings00`.
 
 The blocking assignment behaves exactly like an assignment in any imperative
@@ -498,12 +498,12 @@ Then the synthesizable description is transformed to lower-level representations
 using a series of tools and the results are again verified using simulation.
 This process is illustrated in :numref:`Fig. %s <fig:Basics_flow>`.
 
-.. figure:: ../images/basics_flow.*
-	:class: width-helper
+.. figure:: /_images/primer/basics_flow.*
+	:class: width-helper invert-helper
 	:name: fig:Basics_flow
 
 	Typical design flow.  Green boxes represent manually created models.
-	Orange boxes represent modesl generated by synthesis tools.
+	Orange boxes represent models generated by synthesis tools.
 
 
 In this example the System Level Model and the Behavioural Model are both
@@ -515,8 +515,8 @@ Gate-Level Model are verified and the design process is finished.
 However, in any real-world design effort there will be multiple iterations for
 this design process. The reason for this can be the late change of a design
 requirement or the fact that the analysis of a low-abstraction model
-(e.g. gate-level timing analysis) revealed that a design change is required in
-order to meet the design requirements (e.g. maximum possible clock speed).
+(e.g. gate-level timing analysis) revealed that a design change is required in
+order to meet the design requirements (e.g. maximum possible clock speed).
 
 Whenever the behavioural model or the system level model is changed their
 equivalence must be re-verified by re-running the simulations and comparing the
@@ -572,7 +572,7 @@ of lexical tokens given in :numref:`Tab. %s <tab:Basics_tokens>`.
 	TOK_SEMICOLON  \-
 	============== ===============
 
-The lexer is usually generated by a lexer generator (e.g. flex ) from a
+The lexer is usually generated by a lexer generator (e.g. flex ) from a
 description file that is using regular expressions to specify the text pattern
 that should match the individual tokens.
 
@@ -586,7 +586,7 @@ use the Token-Type to make a decision on the grammatical role of a token.
 
 The parser then transforms the list of tokens into a parse tree that closely
 resembles the productions from the computer languages grammar. As the lexer, the
-parser is also typically generated by a code generator (e.g. bison ) from a
+parser is also typically generated by a code generator (e.g. bison) from a
 grammar description in Backus-Naur Form (BNF).
 
 Let's consider the following BNF (in Bison syntax):
@@ -597,8 +597,8 @@ Let's consider the following BNF (in Bison syntax):
    assign_stmt: TOK_ASSIGN TOK_IDENTIFIER TOK_EQ expr TOK_SEMICOLON;
    expr: TOK_IDENTIFIER | TOK_NUMBER | expr TOK_PLUS expr;
 
-.. figure:: ../images/basics_parsetree.*
-	:class: width-helper
+.. figure:: /_images/primer/basics_parsetree.*
+	:class: width-helper invert-helper
 	:name: fig:Basics_parsetree
 
 	Example parse tree for the Verilog expression 
@@ -610,7 +610,7 @@ whole as data structure in memory. Instead the parser calls user-specified code
 snippets (so-called reduce-functions) for all inner nodes of the parse tree in
 depth-first order.
 
-In some very simple applications (e.g. code generation for stack machines) it is
+In some very simple applications (e.g. code generation for stack machines) it is
 possible to perform the task at hand directly in the reduce functions. But
 usually the reduce functions are only used to build an in-memory data structure
 with the relevant information from the parse tree. This data structure is called
@@ -626,8 +626,8 @@ Usually the AST is then converted into yet another representation that is more
 suitable for further processing. In compilers this is often an assembler-like
 three-address-code intermediate representation. :cite:p:`Dragonbook`
 
-.. figure:: ../images/basics_ast.*
-	:class: width-helper
+.. figure:: /_images/primer/basics_ast.*
+	:class: width-helper invert-helper
 	:name: fig:Basics_ast
 
 	Example abstract syntax tree for the Verilog expression 
diff --git a/yosys/docs/source/bib.rst b/yosys/docs/source/bib.rst
index 21f85a869e2..2675cec16cb 100644
--- a/yosys/docs/source/bib.rst
+++ b/yosys/docs/source/bib.rst
@@ -7,3 +7,4 @@
 
 .. bibliography:: literature.bib
 
+.. todo:: see if we can get the two hanging appnotes as lit references
diff --git a/yosys/docs/source/cmd_ref.rst b/yosys/docs/source/cmd_ref.rst
index 4b9dc91f3e1..acf2d1d4141 100644
--- a/yosys/docs/source/cmd_ref.rst
+++ b/yosys/docs/source/cmd_ref.rst
@@ -3,9 +3,14 @@
 ================================================================================
 Command line reference
 ================================================================================
+
+.. literalinclude:: /generated/yosys
+    :start-at: Usage
+
 .. toctree::
 	:caption: Command reference
 	:maxdepth: 1
 	:glob:
 
-	cmd/*
+	/appendix/env_vars
+	/cmd/*
diff --git a/yosys/manual/PRESENTATION_ExAdv/.gitignore b/yosys/docs/source/code_examples/.gitignore
similarity index 50%
rename from yosys/manual/PRESENTATION_ExAdv/.gitignore
rename to yosys/docs/source/code_examples/.gitignore
index cf658897d52..b4a858a0134 100644
--- a/yosys/manual/PRESENTATION_ExAdv/.gitignore
+++ b/yosys/docs/source/code_examples/.gitignore
@@ -1 +1,2 @@
 *.dot
+*.pdf
diff --git a/yosys/manual/PRESENTATION_ExOth/axis_master.v b/yosys/docs/source/code_examples/axis/axis_master.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExOth/axis_master.v
rename to yosys/docs/source/code_examples/axis/axis_master.v
diff --git a/yosys/manual/PRESENTATION_ExOth/axis_test.v b/yosys/docs/source/code_examples/axis/axis_test.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExOth/axis_test.v
rename to yosys/docs/source/code_examples/axis/axis_test.v
diff --git a/yosys/manual/PRESENTATION_ExOth/axis_test.ys b/yosys/docs/source/code_examples/axis/axis_test.ys
similarity index 70%
rename from yosys/manual/PRESENTATION_ExOth/axis_test.ys
rename to yosys/docs/source/code_examples/axis/axis_test.ys
index 19663ac7733..a55d017d9d6 100644
--- a/yosys/manual/PRESENTATION_ExOth/axis_test.ys
+++ b/yosys/docs/source/code_examples/axis/axis_test.ys
@@ -2,4 +2,4 @@ read_verilog -sv axis_master.v axis_test.v
 hierarchy -top axis_test
 
 proc; flatten;;
-sat -falsify -seq 50 -prove-asserts
+sat -seq 50 -prove-asserts
diff --git a/yosys/manual/PRESENTATION_Prog/.gitignore b/yosys/docs/source/code_examples/extensions/.gitignore
similarity index 76%
rename from yosys/manual/PRESENTATION_Prog/.gitignore
rename to yosys/docs/source/code_examples/extensions/.gitignore
index ccdd6bd5c68..675a532eda6 100644
--- a/yosys/manual/PRESENTATION_Prog/.gitignore
+++ b/yosys/docs/source/code_examples/extensions/.gitignore
@@ -1,2 +1,3 @@
 my_cmd.so
 my_cmd.d
+*.log
diff --git a/yosys/docs/source/code_examples/extensions/Makefile b/yosys/docs/source/code_examples/extensions/Makefile
new file mode 100644
index 00000000000..8b5fa106af1
--- /dev/null
+++ b/yosys/docs/source/code_examples/extensions/Makefile
@@ -0,0 +1,32 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+.PHONY: all dots
+all: dots test0.log test1.log test2.log
+dots: test1.dot
+
+CXXFLAGS=$(shell $(YOSYS)-config --cxxflags)
+DATDIR=$(shell $(YOSYS)-config --datdir)
+
+my_cmd.so: my_cmd.cc
+	$(YOSYS)-config --exec --cxx $(subst $(DATDIR),../../../../share,$(CXXFLAGS)) --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
+
+test0.log: my_cmd.so
+	$(YOSYS) -QTl test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' -f verilog absval_ref.v
+	mv test0.log_new test0.log
+
+test1.log: my_cmd.so
+	$(YOSYS) -QTl test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' -f verilog absval_ref.v
+	mv test1.log_new test1.log
+
+test1.dot: my_cmd.so
+	$(YOSYS) -m ./my_cmd.so -p 'test1; show -format dot -prefix test1'
+
+test2.log: my_cmd.so
+	$(YOSYS) -QTl test2.log_new -m ./my_cmd.so -p 'hierarchy -top test; test2' -f verilog sigmap_test.v
+	mv test2.log_new test2.log
+
+.PHONY: clean
+clean:
+	rm -f *.d *.so *.dot
diff --git a/yosys/manual/PRESENTATION_Prog/absval_ref.v b/yosys/docs/source/code_examples/extensions/absval_ref.v
similarity index 69%
rename from yosys/manual/PRESENTATION_Prog/absval_ref.v
rename to yosys/docs/source/code_examples/extensions/absval_ref.v
index ca0a115a0a7..3f547b50b28 100644
--- a/yosys/manual/PRESENTATION_Prog/absval_ref.v
+++ b/yosys/docs/source/code_examples/extensions/absval_ref.v
@@ -1,3 +1,3 @@
 module absval_ref(input signed [3:0] a, output [3:0] y);
-    assign y = a[3] ? -a : a;
+	assign y = a[3] ? -a : a;
 endmodule
diff --git a/yosys/manual/PRESENTATION_Prog/my_cmd.cc b/yosys/docs/source/code_examples/extensions/my_cmd.cc
similarity index 97%
rename from yosys/manual/PRESENTATION_Prog/my_cmd.cc
rename to yosys/docs/source/code_examples/extensions/my_cmd.cc
index 9cb4b8e38b1..36ddbe1758f 100644
--- a/yosys/manual/PRESENTATION_Prog/my_cmd.cc
+++ b/yosys/docs/source/code_examples/extensions/my_cmd.cc
@@ -14,7 +14,7 @@ struct MyPass : public Pass {
 
         log("Modules in current design:\n");
         for (auto mod : design->modules())
-            log("  %s (%zd wires, %zd cells)\n", log_id(mod),
+            log("  %s (%d wires, %d cells)\n", log_id(mod),
                     GetSize(mod->wires()), GetSize(mod->cells()));
     }
 } MyPass;
diff --git a/yosys/manual/PRESENTATION_Prog/sigmap_test.v b/yosys/docs/source/code_examples/extensions/sigmap_test.v
similarity index 67%
rename from yosys/manual/PRESENTATION_Prog/sigmap_test.v
rename to yosys/docs/source/code_examples/extensions/sigmap_test.v
index 18dcf5eb78e..8d0b4383689 100644
--- a/yosys/manual/PRESENTATION_Prog/sigmap_test.v
+++ b/yosys/docs/source/code_examples/extensions/sigmap_test.v
@@ -1,3 +1,3 @@
 module test(input a, output x, y);
-assign x = a, y = a;
+	assign x = a, y = a;
 endmodule
diff --git a/yosys/docs/source/code_examples/fifo/Makefile b/yosys/docs/source/code_examples/fifo/Makefile
new file mode 100644
index 00000000000..0a1186a62d4
--- /dev/null
+++ b/yosys/docs/source/code_examples/fifo/Makefile
@@ -0,0 +1,24 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+DOT_NAMES = addr_gen_hier addr_gen_proc addr_gen_clean
+DOT_NAMES += rdata_proc rdata_flat rdata_adffe rdata_memrdv2 rdata_alumacc rdata_coarse
+MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates 
+MAPDOT_NAMES += rdata_map_ffs rdata_map_luts rdata_map_cells
+
+DOTS := $(addsuffix .dot,$(DOT_NAMES))
+MAPDOTS := $(addsuffix .dot,$(MAPDOT_NAMES))
+
+all: dots fifo.out fifo.stat
+dots: $(DOTS) $(MAPDOTS)
+
+$(DOTS) fifo.out: fifo.v fifo.ys
+	$(YOSYS) fifo.ys -l fifo.out -Q -T
+
+$(MAPDOTS) fifo.stat: fifo.v fifo_map.ys
+	$(YOSYS) fifo_map.ys
+
+.PHONY: clean
+clean:
+	rm -f *.dot
diff --git a/yosys/docs/source/code_examples/fifo/fifo.libmap b/yosys/docs/source/code_examples/fifo/fifo.libmap
new file mode 100644
index 00000000000..5889b7cfd43
--- /dev/null
+++ b/yosys/docs/source/code_examples/fifo/fifo.libmap
@@ -0,0 +1,65 @@
+
+yosys> debug memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt -no-auto-huge
+
+yosys> memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt -no-auto-huge
+
+4. Executing MEMORY_LIBMAP pass (mapping memories to cells).
+Memory fifo.data mapping candidates (post-geometry):
+- logic fallback
+  - cost: 2048.000000
+- $__ICE40_RAM4K_:
+  - option HAS_BE 0
+  - emulation score: 7
+  - replicates (for ports): 1
+  - replicates (for data): 1
+  - mux score: 0
+  - demux score: 0
+  - cost: 78.000000
+  - abits 11 dbits 2 4 8 16
+  - chosen base width 8
+  - swizzle 0 1 2 3 4 5 6 7
+  - emulate read-first behavior
+  - write port 0: port group W
+    - widths 2 4 8
+  - read port 0: port group R
+    - widths 2 4 8 16
+    - emulate transparency with write port 0
+- $__ICE40_RAM4K_:
+  - option HAS_BE 1
+  - emulation score: 7
+  - replicates (for ports): 1
+  - replicates (for data): 1
+  - mux score: 0
+  - demux score: 0
+  - cost: 78.000000
+  - abits 11 dbits 2 4 8 16
+  - byte width 1
+  - chosen base width 8
+  - swizzle 0 1 2 3 4 5 6 7
+  - emulate read-first behavior
+  - write port 0: port group W
+    - widths 16
+  - read port 0: port group R
+    - widths 2 4 8 16
+    - emulate transparency with write port 0
+Memory fifo.data mapping candidates (after post-geometry prune):
+- logic fallback
+  - cost: 2048.000000
+- $__ICE40_RAM4K_:
+  - option HAS_BE 0
+  - emulation score: 7
+  - replicates (for ports): 1
+  - replicates (for data): 1
+  - mux score: 0
+  - demux score: 0
+  - cost: 78.000000
+  - abits 11 dbits 2 4 8 16
+  - chosen base width 8
+  - swizzle 0 1 2 3 4 5 6 7
+  - emulate read-first behavior
+  - write port 0: port group W
+    - widths 2 4 8
+  - read port 0: port group R
+    - widths 2 4 8 16
+    - emulate transparency with write port 0
+mapping memory fifo.data via $__ICE40_RAM4K_
diff --git a/yosys/docs/source/code_examples/fifo/fifo.stat b/yosys/docs/source/code_examples/fifo/fifo.stat
new file mode 100644
index 00000000000..263c618e326
--- /dev/null
+++ b/yosys/docs/source/code_examples/fifo/fifo.stat
@@ -0,0 +1,57 @@
+
+yosys> stat
+
+2. Printing statistics.
+
+=== fifo ===
+
+   Number of wires:                 28
+   Number of wire bits:            219
+   Number of public wires:           9
+   Number of public wire bits:      45
+   Number of memories:               1
+   Number of memory bits:         2048
+   Number of processes:              3
+   Number of cells:                  9
+     $add                            1
+     $logic_and                      2
+     $logic_not                      2
+     $memrd                          1
+     $sub                            1
+     addr_gen                        2
+
+=== addr_gen ===
+
+   Number of wires:                  8
+   Number of wire bits:             60
+   Number of public wires:           4
+   Number of public wire bits:      11
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              2
+   Number of cells:                  2
+     $add                            1
+     $eq                             1
+
+
+yosys> stat -top fifo
+
+17. Printing statistics.
+
+=== fifo ===
+
+   Number of wires:                 94
+   Number of wire bits:            260
+   Number of public wires:          94
+   Number of public wire bits:     260
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                138
+     $scopeinfo                      2
+     SB_CARRY                       26
+     SB_DFF                         26
+     SB_DFFER                       25
+     SB_LUT4                        58
+     SB_RAM40_4K                     1
+
diff --git a/yosys/docs/source/code_examples/fifo/fifo.v b/yosys/docs/source/code_examples/fifo/fifo.v
new file mode 100644
index 00000000000..769dfafd4c9
--- /dev/null
+++ b/yosys/docs/source/code_examples/fifo/fifo.v
@@ -0,0 +1,71 @@
+// address generator/counter
+module addr_gen 
+#(  parameter MAX_DATA=256,
+	localparam AWIDTH = $clog2(MAX_DATA)
+) ( input en, clk, rst,
+	output reg [AWIDTH-1:0] addr
+);
+	initial addr <= 0;
+
+	// async reset
+	// increment address when enabled
+	always @(posedge clk or posedge rst)
+		if (rst)
+			addr <= 0;
+		else if (en) begin
+			if (addr == MAX_DATA-1)
+				addr <= 0;
+			else
+				addr <= addr + 1;
+		end
+endmodule //addr_gen
+
+// Define our top level fifo entity
+module fifo 
+#(  parameter MAX_DATA=256,
+	localparam AWIDTH = $clog2(MAX_DATA)
+) ( input wen, ren, clk, rst,
+	input [7:0] wdata,
+	output reg [7:0] rdata,
+	output reg [AWIDTH:0] count
+);
+	// fifo storage
+	// sync read before write
+	wire [AWIDTH-1:0] waddr, raddr;
+	reg [7:0] data [MAX_DATA-1:0];
+	always @(posedge clk) begin
+		if (wen)
+			data[waddr] <= wdata;
+		rdata <= data[raddr];
+	end // storage
+
+	// addr_gen for both write and read addresses
+	addr_gen #(.MAX_DATA(MAX_DATA))
+	fifo_writer (
+		.en     (wen),
+		.clk    (clk),
+		.rst    (rst),
+		.addr   (waddr)
+	);
+
+	addr_gen #(.MAX_DATA(MAX_DATA))
+	fifo_reader (
+		.en     (ren),
+		.clk    (clk),
+		.rst    (rst),
+		.addr   (raddr)
+	);
+
+	// status signals
+	initial count <= 0;
+
+	always @(posedge clk or posedge rst) begin
+		if (rst)
+			count <= 0;
+		else if (wen && !ren)
+			count <= count + 1;
+		else if (ren && !wen)
+			count <= count - 1;
+	end
+
+endmodule
diff --git a/yosys/docs/source/code_examples/fifo/fifo.ys b/yosys/docs/source/code_examples/fifo/fifo.ys
new file mode 100644
index 00000000000..57a28e63e8e
--- /dev/null
+++ b/yosys/docs/source/code_examples/fifo/fifo.ys
@@ -0,0 +1,82 @@
+# ========================================================
+# throw in some extra text to match what we expect if we were opening an
+# interactive terminal
+log $ yosys fifo.v
+log 
+log -- Parsing `fifo.v' using frontend ` -vlog2k' --
+read_verilog -defer fifo.v
+
+# turn command echoes on to use the log output as a console session
+echo on
+hierarchy -top addr_gen
+select -module addr_gen
+select -list
+select t:*
+select -list
+select -set new_cells %
+select -clear
+show -format dot -prefix addr_gen_show addr_gen
+show -format dot -prefix new_cells_show -notitle @new_cells
+show -color maroon3 @new_cells -color cornflowerblue p:* -notitle -format dot -prefix addr_gen_hier
+
+# ========================================================
+proc -noopt
+select -set new_cells t:$mux t:*dff
+show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_proc
+
+# ========================================================
+opt_expr; clean
+select -set new_cells t:$eq
+show -color cornflowerblue @new_cells -notitle -format dot -prefix addr_gen_clean
+
+# ========================================================
+design -reset
+read_verilog fifo.v
+hierarchy -check -top fifo
+proc
+select -set new_cells t:$memrd
+show -color maroon3 c:fifo_reader -color cornflowerblue @new_cells -notitle -format dot -prefix rdata_proc o:rdata %ci*
+
+# ========================================================
+
+flatten;;
+select -set rdata_path o:rdata %ci*
+select -set new_cells @rdata_path o:rdata %ci3 %d i:* %d
+show -color maroon3 @new_cells -notitle -format dot -prefix rdata_flat @rdata_path
+
+# ========================================================
+
+opt_dff
+select -set new_cells t:$adffe
+show -color maroon3 @new_cells -notitle -format dot -prefix rdata_adffe o:rdata %ci*
+
+# ========================================================
+
+wreduce
+show -notitle -format dot -prefix rdata_wreduce o:rdata %ci*
+
+# unclear if this is necessary or only because of bug(s)
+opt_clean
+
+# ========================================================
+
+memory_dff
+select -set new_cells t:$memrd_v2
+show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdata %ci*
+
+# ========================================================
+
+alumacc
+select -set new_cells t:$alu t:$macc
+show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci*
+
+# ========================================================
+
+memory_collect
+# or use the following commands:
+# design -reset
+# read_verilog fifo.v
+# synth_ice40 -top fifo -run begin:map_ram
+select -set new_cells t:$mem_v2
+select -set rdata_path @new_cells %ci*:-$mem_v2[WR_DATA,WR_ADDR,WR_EN] @new_cells %co* %%
+show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse @rdata_path
diff --git a/yosys/docs/source/code_examples/fifo/fifo_map.ys b/yosys/docs/source/code_examples/fifo/fifo_map.ys
new file mode 100644
index 00000000000..f5a3edeb485
--- /dev/null
+++ b/yosys/docs/source/code_examples/fifo/fifo_map.ys
@@ -0,0 +1,57 @@
+read_verilog fifo.v
+echo on
+tee -o fifo.stat stat
+echo off
+synth_ice40 -top fifo -run begin:map_ram
+# this point should be the same as rdata_coarse
+
+# ========================================================
+
+echo on
+tee -o fifo.libmap debug memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt -no-auto-huge
+echo off
+synth_ice40 -top fifo -run map_ram:map_ffram
+select -set mem t:SB_RAM40_4K
+select -set remap @mem %ci:+SB_RAM40_4K[RADDR] @mem %co %%
+select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
+show -color cornflowerblue @remap -notitle -format dot -prefix rdata_map_ram @rdata_path
+
+# ========================================================
+
+synth_ice40 -top fifo -run map_ffram:map_gates
+select -set mem t:SB_RAM40_4K
+select -set remap @mem %co @mem %d
+select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
+show -color maroon3 @mem -color cornflowerblue @remap -notitle -format dot -prefix rdata_map_ffram @rdata_path
+
+# ========================================================
+
+synth_ice40 -top fifo -run map_gates:map_ffs
+select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
+select -set multibit t:$_MUX_ t:$_DFFE_*_
+select -set alu t:$_OR_ t:$_NOT_ t:$lut %% %ci %% w:fifo_reader.addr %d i:* %d
+show -color maroon3 @multibit -color cornflowerblue @alu -notitle -format dot -prefix rdata_map_gates @rdata_path
+
+# ========================================================
+
+synth_ice40 -top fifo -run map_ffs:map_luts
+select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
+select -set dff t:SB_DFFER
+select -set primitives t:$_AND_ %ci i:* %d
+show -color maroon3 @dff -color cornflowerblue @primitives -notitle -format dot -prefix rdata_map_ffs @rdata_path
+
+# ========================================================
+
+synth_ice40 -top fifo -run map_luts:map_cells
+select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
+show -color maroon3 t:SB_CARRY -color cornflowerblue t:$lut -notitle -format dot -prefix rdata_map_luts @rdata_path
+
+# ========================================================
+
+synth_ice40 -top fifo -run map_cells:
+select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
+show -color maroon3 t:SB_LUT* -notitle -format dot -prefix rdata_map_cells @rdata_path
+
+echo on
+tee -a fifo.stat stat -top fifo
+echo off
diff --git a/yosys/docs/source/code_examples/intro/.gitignore b/yosys/docs/source/code_examples/intro/.gitignore
new file mode 100644
index 00000000000..9f8173c6d17
--- /dev/null
+++ b/yosys/docs/source/code_examples/intro/.gitignore
@@ -0,0 +1 @@
+synth.v
diff --git a/yosys/docs/source/code_examples/intro/Makefile b/yosys/docs/source/code_examples/intro/Makefile
new file mode 100644
index 00000000000..009c82c6219
--- /dev/null
+++ b/yosys/docs/source/code_examples/intro/Makefile
@@ -0,0 +1,15 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+DOTS = counter_00.dot counter_01.dot counter_02.dot counter_03.dot
+
+all: dots
+dots: $(DOTS)
+
+$(DOTS): counter.v counter.ys mycells.lib
+	$(YOSYS) counter.ys
+
+.PHONY: clean
+clean:
+	rm -f *.dot
diff --git a/yosys/manual/PRESENTATION_Intro/counter.v b/yosys/docs/source/code_examples/intro/counter.v
similarity index 100%
rename from yosys/manual/PRESENTATION_Intro/counter.v
rename to yosys/docs/source/code_examples/intro/counter.v
diff --git a/yosys/docs/source/code_examples/intro/counter.ys b/yosys/docs/source/code_examples/intro/counter.ys
new file mode 100644
index 00000000000..e327a6f6b81
--- /dev/null
+++ b/yosys/docs/source/code_examples/intro/counter.ys
@@ -0,0 +1,31 @@
+# read design
+read_verilog counter.v
+hierarchy -check -top counter
+
+show -notitle -format dot -prefix counter_00
+
+# the high-level stuff
+proc; opt
+memory; opt
+fsm; opt
+
+show -notitle -format dot -prefix counter_01
+
+# mapping to internal cell library
+techmap; opt
+
+splitnets -ports;; show -notitle -format dot -prefix counter_02
+
+# mapping flip-flops to mycells.lib
+dfflibmap -liberty mycells.lib
+
+# mapping logic to mycells.lib
+abc -liberty mycells.lib
+
+# cleanup
+clean
+
+show -notitle -lib mycells.v -format dot -prefix counter_03
+
+# write synthesized design
+write_verilog synth.v
diff --git a/yosys/manual/PRESENTATION_Intro/mycells.lib b/yosys/docs/source/code_examples/intro/mycells.lib
similarity index 100%
rename from yosys/manual/PRESENTATION_Intro/mycells.lib
rename to yosys/docs/source/code_examples/intro/mycells.lib
diff --git a/yosys/manual/PRESENTATION_Intro/mycells.v b/yosys/docs/source/code_examples/intro/mycells.v
similarity index 100%
rename from yosys/manual/PRESENTATION_Intro/mycells.v
rename to yosys/docs/source/code_examples/intro/mycells.v
diff --git a/yosys/docs/source/code_examples/macc/Makefile b/yosys/docs/source/code_examples/macc/Makefile
new file mode 100644
index 00000000000..e93fe065734
--- /dev/null
+++ b/yosys/docs/source/code_examples/macc/Makefile
@@ -0,0 +1,19 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+DOTS = macc_simple_xmap.dot macc_xilinx_xmap.dot
+
+all: dots
+dots: $(DOTS)
+
+macc_simple_xmap.dot: macc_simple_*.v macc_simple_test.ys
+	$(YOSYS) macc_simple_test.ys
+
+macc_xilinx_xmap.dot: macc_xilinx_*.v macc_xilinx_test.ys
+	$(YOSYS) macc_xilinx_test.ys
+
+.PHONY: clean
+clean:
+	rm -f *.dot
+
diff --git a/yosys/manual/PRESENTATION_ExAdv/macc_simple_test.v b/yosys/docs/source/code_examples/macc/macc_simple_test.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/macc_simple_test.v
rename to yosys/docs/source/code_examples/macc/macc_simple_test.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/macc_simple_test.ys b/yosys/docs/source/code_examples/macc/macc_simple_test.ys
similarity index 60%
rename from yosys/manual/PRESENTATION_ExAdv/macc_simple_test.ys
rename to yosys/docs/source/code_examples/macc/macc_simple_test.ys
index 8d106a28c9d..70496c05769 100644
--- a/yosys/manual/PRESENTATION_ExAdv/macc_simple_test.ys
+++ b/yosys/docs/source/code_examples/macc/macc_simple_test.ys
@@ -1,10 +1,10 @@
 read_verilog macc_simple_test.v
 hierarchy -check -top test;;
 
-show -prefix macc_simple_test_00a -format pdf -notitle -lib macc_simple_xmap.v
+show -prefix macc_simple_test_00a -format dot -notitle -lib macc_simple_xmap.v
 
 extract -constports -map macc_simple_xmap.v;;
-show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
+show -prefix macc_simple_test_00b -format dot -notitle -lib macc_simple_xmap.v
 
 #################################################
 
@@ -12,10 +12,10 @@ design -reset
 read_verilog macc_simple_test_01.v
 hierarchy -check -top test;;
 
-show -prefix macc_simple_test_01a -format pdf -notitle -lib macc_simple_xmap.v
+show -prefix macc_simple_test_01a -format dot -notitle -lib macc_simple_xmap.v
 
 extract -map macc_simple_xmap.v;;
-show -prefix macc_simple_test_01b -format pdf -notitle -lib macc_simple_xmap.v
+show -prefix macc_simple_test_01b -format dot -notitle -lib macc_simple_xmap.v
 
 #################################################
 
@@ -23,10 +23,10 @@ design -reset
 read_verilog macc_simple_test_02.v
 hierarchy -check -top test;;
 
-show -prefix macc_simple_test_02a -format pdf -notitle -lib macc_simple_xmap.v
+show -prefix macc_simple_test_02a -format dot -notitle -lib macc_simple_xmap.v
 
 extract -map macc_simple_xmap.v;;
-show -prefix macc_simple_test_02b -format pdf -notitle -lib macc_simple_xmap.v
+show -prefix macc_simple_test_02b -format dot -notitle -lib macc_simple_xmap.v
 
 #################################################
 
@@ -34,4 +34,4 @@ design -reset
 read_verilog macc_simple_xmap.v
 hierarchy -check -top macc_16_16_32;;
 
-show -prefix macc_simple_xmap -format pdf -notitle
+show -prefix macc_simple_xmap -format dot -notitle
diff --git a/yosys/manual/PRESENTATION_ExAdv/macc_simple_test_01.v b/yosys/docs/source/code_examples/macc/macc_simple_test_01.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/macc_simple_test_01.v
rename to yosys/docs/source/code_examples/macc/macc_simple_test_01.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/macc_simple_test_02.v b/yosys/docs/source/code_examples/macc/macc_simple_test_02.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/macc_simple_test_02.v
rename to yosys/docs/source/code_examples/macc/macc_simple_test_02.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/macc_simple_xmap.v b/yosys/docs/source/code_examples/macc/macc_simple_xmap.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/macc_simple_xmap.v
rename to yosys/docs/source/code_examples/macc/macc_simple_xmap.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v b/yosys/docs/source/code_examples/macc/macc_xilinx_swap_map.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
rename to yosys/docs/source/code_examples/macc/macc_xilinx_swap_map.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/macc_xilinx_test.v b/yosys/docs/source/code_examples/macc/macc_xilinx_test.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
rename to yosys/docs/source/code_examples/macc/macc_xilinx_test.v
diff --git a/yosys/docs/source/code_examples/macc/macc_xilinx_test.ys b/yosys/docs/source/code_examples/macc/macc_xilinx_test.ys
new file mode 100644
index 00000000000..47bf399b20a
--- /dev/null
+++ b/yosys/docs/source/code_examples/macc/macc_xilinx_test.ys
@@ -0,0 +1,53 @@
+# ============================================================================
+# part a
+read_verilog macc_xilinx_test.v
+read_verilog -lib -icells macc_xilinx_unwrap_map.v
+read_verilog -lib -icells macc_xilinx_xmap.v
+hierarchy -check ;;
+# end part a
+show -prefix macc_xilinx_test1a -format dot -notitle test1
+show -prefix macc_xilinx_test2a -format dot -notitle test2
+
+# ============================================================================
+# part b
+techmap -map macc_xilinx_swap_map.v;;
+# end part b
+show -prefix macc_xilinx_test1b -format dot -notitle test1
+show -prefix macc_xilinx_test2b -format dot -notitle test2
+
+# ============================================================================
+# part c
+techmap -map macc_xilinx_wrap_map.v
+
+connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
+             -unsigned $__add_wrapper Y Y_WIDTH;;
+# end part c
+show -prefix macc_xilinx_test1c -format dot -notitle test1
+show -prefix macc_xilinx_test2c -format dot -notitle test2
+
+# ============================================================================
+# part d
+design -push
+read_verilog macc_xilinx_xmap.v
+techmap -map macc_xilinx_swap_map.v
+techmap -map macc_xilinx_wrap_map.v;;
+design -save __macc_xilinx_xmap
+design -pop
+
+extract -constports -ignore_parameters \
+        -map %__macc_xilinx_xmap       \
+        -swap $__add_wrapper A,B ;;
+# end part d
+show -prefix macc_xilinx_test1d -format dot -notitle test1
+show -prefix macc_xilinx_test2d -format dot -notitle test2
+
+# ============================================================================
+# part e
+techmap -map macc_xilinx_unwrap_map.v;;
+# end part e
+show -prefix macc_xilinx_test1e -format dot -notitle test1
+show -prefix macc_xilinx_test2e -format dot -notitle test2
+
+design -load __macc_xilinx_xmap
+show -prefix macc_xilinx_xmap -format dot -notitle
+
diff --git a/yosys/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v b/yosys/docs/source/code_examples/macc/macc_xilinx_unwrap_map.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
rename to yosys/docs/source/code_examples/macc/macc_xilinx_unwrap_map.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v b/yosys/docs/source/code_examples/macc/macc_xilinx_wrap_map.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
rename to yosys/docs/source/code_examples/macc/macc_xilinx_wrap_map.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v b/yosys/docs/source/code_examples/macc/macc_xilinx_xmap.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
rename to yosys/docs/source/code_examples/macc/macc_xilinx_xmap.v
diff --git a/yosys/docs/source/code_examples/macro_commands/fsm.ys b/yosys/docs/source/code_examples/macro_commands/fsm.ys
new file mode 100644
index 00000000000..627df1209ae
--- /dev/null
+++ b/yosys/docs/source/code_examples/macro_commands/fsm.ys
@@ -0,0 +1,27 @@
+#start:It also calls opt_clean as needed:
+#end:Options:
+# Identify and extract FSMs:
+fsm_detect
+fsm_extract
+
+# Basic optimizations:
+fsm_opt
+opt_clean
+fsm_opt
+
+# Expanding to nearby gate-logic (if called with -expand):
+fsm_expand
+opt_clean
+fsm_opt
+
+# Re-code FSM states (unless called with -norecode):
+fsm_recode
+
+# Print information about FSMs:
+fsm_info
+
+# Export FSMs in KISS2 file format (if called with -export):
+fsm_export
+
+# Map FSMs to RTL cells (unless called with -nomap):
+fsm_map
diff --git a/yosys/docs/source/code_examples/macro_commands/memory.ys b/yosys/docs/source/code_examples/macro_commands/memory.ys
new file mode 100644
index 00000000000..ea4800a1cc1
--- /dev/null
+++ b/yosys/docs/source/code_examples/macro_commands/memory.ys
@@ -0,0 +1,15 @@
+#start:passes in a useful order:
+#end:This converts memories to word-wide DFFs and address decoders
+opt_mem
+opt_mem_priority
+opt_mem_feedback
+memory_bmux2rom
+memory_dff
+opt_clean
+memory_share
+opt_mem_widen
+memory_memx                         (when called with -memx)
+opt_clean
+memory_collect
+memory_bram -rules <bram_rules>     (when called with -bram)
+memory_map                          (skipped if called with -nomap)
diff --git a/yosys/docs/source/code_examples/macro_commands/opt.ys b/yosys/docs/source/code_examples/macro_commands/opt.ys
new file mode 100644
index 00000000000..cb883bc589a
--- /dev/null
+++ b/yosys/docs/source/code_examples/macro_commands/opt.ys
@@ -0,0 +1,14 @@
+#start: passes in the following order:
+#end: When called with -fast
+opt_expr
+opt_merge -nomux
+
+do
+    opt_muxtree
+    opt_reduce
+    opt_merge
+    opt_share  (-full only)
+    opt_dff  (except when called with -noff)
+    opt_clean
+    opt_expr
+while <changed design>
diff --git a/yosys/docs/source/code_examples/macro_commands/proc.ys b/yosys/docs/source/code_examples/macro_commands/proc.ys
new file mode 100644
index 00000000000..7a78ce0c6b8
--- /dev/null
+++ b/yosys/docs/source/code_examples/macro_commands/proc.ys
@@ -0,0 +1,14 @@
+#start: passes in the most common order.
+#end: This replaces the processes
+proc_clean # removes empty branches and processes
+proc_rmdead # removes unreachable branches
+proc_prune
+proc_init # special handling of “initial� blocks
+proc_arst # identifies modeling of async resets
+proc_rom
+proc_mux # converts decision trees to multiplexer networks
+proc_dlatch
+proc_dff # extracts registers from processes
+proc_memwr
+proc_clean # this should remove all the processes, provided all went fine
+opt_expr -keepdc
diff --git a/yosys/docs/source/code_examples/macro_commands/synth_ice40.ys b/yosys/docs/source/code_examples/macro_commands/synth_ice40.ys
new file mode 100644
index 00000000000..443b8e0b026
--- /dev/null
+++ b/yosys/docs/source/code_examples/macro_commands/synth_ice40.ys
@@ -0,0 +1,90 @@
+#start:The following commands are executed by this synthesis command:
+#end:blif:
+begin:
+    read_verilog -D ICE40_HX -lib -specify +/ice40/cells_sim.v
+    hierarchy -check -top <top>
+    proc
+
+flatten:
+    flatten
+    tribuf -logic
+    deminout
+
+coarse:
+    opt_expr
+    opt_clean
+    check
+    opt -nodffe -nosdff
+    fsm
+    opt
+    wreduce
+    peepopt
+    opt_clean
+    share
+    techmap
+    opt_expr
+    opt_clean
+    memory_dff
+    wreduce t:$mul
+    techmap
+    select a:mul2dsp
+    setattr -unset mul2dsp
+    opt_expr -fine
+    wreduce
+    select -clear
+    ice40_dsp
+    chtype -set $mul t:$__soft_mul
+    alumacc
+    opt
+    memory -nomap [-no-rw-check]
+    opt_clean
+
+map_ram:
+    memory_libmap
+    techmap
+    ice40_braminit
+
+map_ffram:
+    opt -fast -mux_undef -undriven -fine
+    memory_map
+    opt -undriven -fine
+
+map_gates:
+    ice40_wrapcarry
+    techmap
+    opt -fast
+    abc -dff -D 1 
+    ice40_opt
+
+map_ffs:
+    dfflegalize
+    techmap
+    opt_expr -mux_undef
+    simplemap
+    ice40_opt -full
+
+map_luts:
+    abc
+    ice40_opt
+    techmap
+    simplemap
+    techmap
+    flowmap
+    read_verilog
+    abc9
+    ice40_wrapcarry -unwrap
+    techmap
+    clean
+    opt_lut -tech ice40
+
+map_cells:
+    techmap
+    clean
+
+check:
+    autoname
+    hierarchy -check
+    stat
+    check -noinit
+    blackbox =A:whitebox
+        
\ No newline at end of file
diff --git a/yosys/docs/source/code_examples/opt/Makefile b/yosys/docs/source/code_examples/opt/Makefile
new file mode 100644
index 00000000000..4cb51e90bec
--- /dev/null
+++ b/yosys/docs/source/code_examples/opt/Makefile
@@ -0,0 +1,20 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+DOT_NAMES = opt_share opt_muxtree opt_merge opt_expr
+
+DOTS := $(addsuffix .dot,$(DOT_NAMES))
+
+all: dots
+dots: $(DOTS)
+
+%_full.dot: %.ys
+	$(YOSYS) $<
+
+%.dot: %_full.dot
+	gvpack -u $*_full.dot -o $@
+
+.PHONY: clean
+clean:
+	rm -f *.dot
diff --git a/yosys/docs/source/code_examples/opt/opt_expr.ys b/yosys/docs/source/code_examples/opt/opt_expr.ys
new file mode 100644
index 00000000000..e87da339ed8
--- /dev/null
+++ b/yosys/docs/source/code_examples/opt/opt_expr.ys
@@ -0,0 +1,17 @@
+read_verilog <<EOT
+
+module uut(
+    input a,
+    output y, z
+);  
+    assign y = a == a;
+    assign z = a != a;
+endmodule
+
+EOT
+
+copy uut after
+opt_expr after
+clean
+
+show -format dot -prefix opt_expr_full -notitle -color cornflowerblue uut
diff --git a/yosys/docs/source/code_examples/opt/opt_merge.ys b/yosys/docs/source/code_examples/opt/opt_merge.ys
new file mode 100644
index 00000000000..38434ca3a22
--- /dev/null
+++ b/yosys/docs/source/code_examples/opt/opt_merge.ys
@@ -0,0 +1,18 @@
+read_verilog <<EOT
+
+module uut(
+    input  [3:0] a, b,
+    output [3:0] y, z
+);
+    assign y = a + b;
+    assign z = b + a;
+endmodule
+
+EOT
+
+copy uut after
+opt_merge after
+clean
+
+show -format dot -prefix opt_merge_full -notitle -color cornflowerblue uut
+
diff --git a/yosys/docs/source/code_examples/opt/opt_muxtree.ys b/yosys/docs/source/code_examples/opt/opt_muxtree.ys
new file mode 100644
index 00000000000..b9d394c0865
--- /dev/null
+++ b/yosys/docs/source/code_examples/opt/opt_muxtree.ys
@@ -0,0 +1,17 @@
+read_verilog <<EOT
+
+module uut(
+    input a, b, c, d,
+    output y
+);  
+    assign y = a ? (a ? b : c) : d;
+endmodule
+
+EOT
+
+copy uut after
+opt_muxtree after
+clean
+
+show -format dot -prefix opt_muxtree_full -notitle -color cornflowerblue uut
+
diff --git a/yosys/docs/source/code_examples/opt/opt_share.ys b/yosys/docs/source/code_examples/opt/opt_share.ys
new file mode 100644
index 00000000000..bcf63874876
--- /dev/null
+++ b/yosys/docs/source/code_examples/opt/opt_share.ys
@@ -0,0 +1,17 @@
+read_verilog <<EOT
+
+module uut(
+    input  [15:0] a, b,
+    input         sel,
+    output [15:0] res,
+);
+    assign res = {sel ? a + b : a - b};
+endmodule
+
+EOT
+
+copy uut after
+opt_share after
+clean
+
+show -format dot -prefix opt_share_full -notitle -color cornflowerblue uut
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/primetest.v b/yosys/docs/source/code_examples/primetest.v
similarity index 100%
rename from yosys/docs/source/APPNOTE_011_Design_Investigation/primetest.v
rename to yosys/docs/source/code_examples/primetest.v
diff --git a/yosys/docs/source/code_examples/scrambler/Makefile b/yosys/docs/source/code_examples/scrambler/Makefile
new file mode 100644
index 00000000000..de475b8b1a1
--- /dev/null
+++ b/yosys/docs/source/code_examples/scrambler/Makefile
@@ -0,0 +1,14 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+.PHONY: all dots
+all: dots
+dots: scrambler_p01.dot scrambler_p02.dot
+
+scrambler_p01.dot scrambler_p02.dot: scrambler.ys scrambler.v
+	$(YOSYS) scrambler.ys
+
+.PHONY: clean
+clean:
+	rm -f *.dot
diff --git a/yosys/manual/PRESENTATION_ExOth/scrambler.v b/yosys/docs/source/code_examples/scrambler/scrambler.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExOth/scrambler.v
rename to yosys/docs/source/code_examples/scrambler/scrambler.v
diff --git a/yosys/manual/PRESENTATION_ExOth/scrambler.ys b/yosys/docs/source/code_examples/scrambler/scrambler.ys
similarity index 69%
rename from yosys/manual/PRESENTATION_ExOth/scrambler.ys
rename to yosys/docs/source/code_examples/scrambler/scrambler.ys
index 2ef14c56e5f..f14caa6f738 100644
--- a/yosys/manual/PRESENTATION_ExOth/scrambler.ys
+++ b/yosys/docs/source/code_examples/scrambler/scrambler.ys
@@ -1,4 +1,3 @@
-
 read_verilog scrambler.v
 
 hierarchy; proc;;
@@ -7,8 +6,8 @@ cd scrambler
 submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d
 cd ..
 
-show -prefix scrambler_p01 -format pdf -notitle scrambler
-show -prefix scrambler_p02 -format pdf -notitle xorshift32
+show -prefix scrambler_p01 -format dot -notitle scrambler
+show -prefix scrambler_p02 -format dot -notitle xorshift32
 
 echo on
 
diff --git a/yosys/docs/source/code_examples/selections/Makefile b/yosys/docs/source/code_examples/selections/Makefile
new file mode 100644
index 00000000000..bb506ff38eb
--- /dev/null
+++ b/yosys/docs/source/code_examples/selections/Makefile
@@ -0,0 +1,32 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+SUMPROD = sumprod_00 sumprod_01 sumprod_02 sumprod_03 sumprod_04 sumprod_05
+SUMPROD_DOTS := $(addsuffix .dot,$(SUMPROD))
+
+MEMDEMO = memdemo_00 memdemo_01
+MEMDEMO_DOTS := $(addsuffix .dot,$(MEMDEMO))
+
+SUBMOD = submod_00 submod_01 submod_02 submod_03
+SUBMOD_DOTS := $(addsuffix .dot,$(SUBMOD))
+
+.PHONY: all dots
+all: dots
+dots: select.dot $(SUMPROD_DOTS) $(MEMDEMO_DOTS) $(SUBMOD_DOTS)
+
+select.dot: select.v select.ys
+	$(YOSYS) select.ys
+
+$(SUMPROD_DOTS): sumprod.v sumprod.ys
+	$(YOSYS) sumprod.ys
+
+$(MEMDEMO_DOTS): memdemo.v memdemo.ys
+	$(YOSYS) memdemo.ys
+
+$(SUBMOD_DOTS): memdemo.v submod.ys
+	$(YOSYS) submod.ys
+
+.PHONY: clean
+clean:
+	rm -rf *.dot
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/foobaraddsub.v b/yosys/docs/source/code_examples/selections/foobaraddsub.v
similarity index 100%
rename from yosys/docs/source/APPNOTE_011_Design_Investigation/foobaraddsub.v
rename to yosys/docs/source/code_examples/selections/foobaraddsub.v
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/memdemo.v b/yosys/docs/source/code_examples/selections/memdemo.v
similarity index 100%
rename from yosys/docs/source/APPNOTE_011_Design_Investigation/memdemo.v
rename to yosys/docs/source/code_examples/selections/memdemo.v
diff --git a/yosys/docs/source/code_examples/selections/memdemo.ys b/yosys/docs/source/code_examples/selections/memdemo.ys
new file mode 100644
index 00000000000..cb7700a7e04
--- /dev/null
+++ b/yosys/docs/source/code_examples/selections/memdemo.ys
@@ -0,0 +1,10 @@
+read_verilog memdemo.v
+prep -top memdemo; memory; opt
+
+cd memdemo
+show -format dot -prefix memdemo_00
+show -format dot -prefix memdemo_01 y %ci2
+show -format dot -prefix memdemo_02 y %ci5
+show -format dot -prefix memdemo_03 y %ci5:-$mux[S]
+show -format dot -prefix memdemo_04 y %ci*:-[CLK,S]:+$dff,$mux
+show -format dot -prefix memdemo_05 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff
diff --git a/yosys/manual/PRESENTATION_ExAdv/select.v b/yosys/docs/source/code_examples/selections/select.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/select.v
rename to yosys/docs/source/code_examples/selections/select.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/select.ys b/yosys/docs/source/code_examples/selections/select.ys
similarity index 73%
rename from yosys/manual/PRESENTATION_ExAdv/select.ys
rename to yosys/docs/source/code_examples/selections/select.ys
index 9832c104b3d..e9a775f1fdf 100644
--- a/yosys/manual/PRESENTATION_ExAdv/select.ys
+++ b/yosys/docs/source/code_examples/selections/select.ys
@@ -1,10 +1,10 @@
 read_verilog select.v
-hierarchy -check -top test
-proc; opt
+prep -top test
+
 cd test
 select -set cone_a state_a %ci*:-$dff
 select -set cone_b state_b %ci*:-$dff
 select -set cone_ab @cone_a @cone_b %i
-show -prefix select -format pdf -notitle \
+show -prefix select -format dot -notitle \
      -color red @cone_ab -color magenta @cone_a \
      -color blue @cone_b
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/submod.ys b/yosys/docs/source/code_examples/selections/submod.ys
similarity index 94%
rename from yosys/docs/source/APPNOTE_011_Design_Investigation/submod.ys
rename to yosys/docs/source/code_examples/selections/submod.ys
index 29ad61076a9..c252153c619 100644
--- a/yosys/docs/source/APPNOTE_011_Design_Investigation/submod.ys
+++ b/yosys/docs/source/code_examples/selections/submod.ys
@@ -1,5 +1,5 @@
 read_verilog memdemo.v
-proc; opt; memory; opt
+prep -top memdemo; memory; opt
 
 cd memdemo
 select -set outstage y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/sumprod.v b/yosys/docs/source/code_examples/selections/sumprod.v
similarity index 100%
rename from yosys/docs/source/APPNOTE_011_Design_Investigation/sumprod.v
rename to yosys/docs/source/code_examples/selections/sumprod.v
diff --git a/yosys/docs/source/code_examples/selections/sumprod.ys b/yosys/docs/source/code_examples/selections/sumprod.ys
new file mode 100644
index 00000000000..67e2a28d5c9
--- /dev/null
+++ b/yosys/docs/source/code_examples/selections/sumprod.ys
@@ -0,0 +1,13 @@
+read_verilog sumprod.v
+prep -top sumprod
+cd sumprod
+
+show -format dot -prefix sumprod_00 a:sumstuff
+show -format dot -prefix sumprod_01 a:sumstuff %x
+show -format dot -prefix sumprod_02 prod
+show -format dot -prefix sumprod_03 prod %ci
+show -format dot -prefix sumprod_04 prod %ci2
+show -format dot -prefix sumprod_05 prod %ci3
+
+dump -o sumprod.out prod %ci
+dump -a sumprod.out prod %ci2
diff --git a/yosys/docs/source/code_examples/show/Makefile b/yosys/docs/source/code_examples/show/Makefile
new file mode 100644
index 00000000000..4b269a4aba1
--- /dev/null
+++ b/yosys/docs/source/code_examples/show/Makefile
@@ -0,0 +1,29 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+EXAMPLE = example_first example_second example_third
+EXAMPLE_DOTS := $(addsuffix .dot,$(EXAMPLE))
+
+CMOS = cmos_00 cmos_01
+CMOS_DOTS := $(addsuffix .dot,$(CMOS))
+
+.PHONY: all dots
+all: dots example.out
+dots: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS)
+
+splice.dot: splice.v
+	$(YOSYS) -p 'prep -top splice_demo; show -format dot -prefix splice' splice.v
+
+$(EXAMPLE_DOTS): example.v example.ys
+	$(YOSYS) example.ys
+
+example.out: example_lscd.ys example.v
+	$(YOSYS) $< -l $@ -Q -T
+
+$(CMOS_DOTS): cmos.v cmos.ys
+	$(YOSYS) cmos.ys
+
+.PHONY: clean
+clean:
+	rm -rf *.dot
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/cmos.v b/yosys/docs/source/code_examples/show/cmos.v
similarity index 100%
rename from yosys/docs/source/APPNOTE_011_Design_Investigation/cmos.v
rename to yosys/docs/source/code_examples/show/cmos.v
diff --git a/yosys/docs/source/code_examples/show/cmos.ys b/yosys/docs/source/code_examples/show/cmos.ys
new file mode 100644
index 00000000000..7158de1d0dc
--- /dev/null
+++ b/yosys/docs/source/code_examples/show/cmos.ys
@@ -0,0 +1,17 @@
+# pitfall
+read_verilog cmos.v
+prep -top cmos_demo
+techmap
+abc -liberty ../intro/mycells.lib;; 
+show -format dot -prefix cmos_00
+
+# reset
+design -reset
+
+# fixed output
+read_verilog cmos.v
+prep -top cmos_demo
+techmap
+splitnets -ports
+abc -liberty ../intro/mycells.lib;; 
+show -lib ../intro/mycells.v -format dot -prefix cmos_01
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/example.v b/yosys/docs/source/code_examples/show/example.v
similarity index 100%
rename from yosys/docs/source/APPNOTE_011_Design_Investigation/example.v
rename to yosys/docs/source/code_examples/show/example.v
diff --git a/yosys/docs/source/code_examples/show/example.ys b/yosys/docs/source/code_examples/show/example.ys
new file mode 100644
index 00000000000..a5332f13486
--- /dev/null
+++ b/yosys/docs/source/code_examples/show/example.ys
@@ -0,0 +1,6 @@
+read_verilog example.v
+show -format dot -prefix example_first
+proc
+show -format dot -prefix example_second
+opt
+show -format dot -prefix example_third
diff --git a/yosys/docs/source/code_examples/show/example_lscd.ys b/yosys/docs/source/code_examples/show/example_lscd.ys
new file mode 100644
index 00000000000..de24842285a
--- /dev/null
+++ b/yosys/docs/source/code_examples/show/example_lscd.ys
@@ -0,0 +1,8 @@
+read_verilog example.v
+echo on
+ls
+cd example
+ls
+dump $2
+cd ..
+echo off
diff --git a/yosys/docs/source/code_examples/show/example_show.ys b/yosys/docs/source/code_examples/show/example_show.ys
new file mode 100644
index 00000000000..711af84d9f2
--- /dev/null
+++ b/yosys/docs/source/code_examples/show/example_show.ys
@@ -0,0 +1,6 @@
+read_verilog example.v
+show -pause # first
+proc
+show -pause # second
+opt
+show -pause # third
diff --git a/yosys/docs/source/APPNOTE_011_Design_Investigation/splice.v b/yosys/docs/source/code_examples/show/splice.v
similarity index 81%
rename from yosys/docs/source/APPNOTE_011_Design_Investigation/splice.v
rename to yosys/docs/source/code_examples/show/splice.v
index 1cf7274c059..1f7c92f4d04 100644
--- a/yosys/docs/source/APPNOTE_011_Design_Investigation/splice.v
+++ b/yosys/docs/source/code_examples/show/splice.v
@@ -1,7 +1,8 @@
 module splice_demo(a, b, c, d, e, f, x, y);
 
 input [1:0] a, b, c, d, e, f;
-output [1:0] x = {a[0], a[1]};
+output [1:0] x;
+assign x = {a[0], a[1]};
 
 output [11:0] y;
 assign {y[11:4], y[1:0], y[3:2]} =
diff --git a/yosys/docs/source/CHAPTER_Prog/.gitignore b/yosys/docs/source/code_examples/stubnets/.gitignore
similarity index 100%
rename from yosys/docs/source/CHAPTER_Prog/.gitignore
rename to yosys/docs/source/code_examples/stubnets/.gitignore
diff --git a/yosys/docs/source/CHAPTER_Prog/Makefile b/yosys/docs/source/code_examples/stubnets/Makefile
similarity index 87%
rename from yosys/docs/source/CHAPTER_Prog/Makefile
rename to yosys/docs/source/code_examples/stubnets/Makefile
index 8e326bdc266..ec501f006ca 100644
--- a/yosys/docs/source/CHAPTER_Prog/Makefile
+++ b/yosys/docs/source/code_examples/stubnets/Makefile
@@ -1,3 +1,8 @@
+.PHONY: all dots
+all: dots
+dots:
+
+.PHONY: test
 test: stubnets.so
 	yosys -ql test1.log -m ./stubnets.so test.v -p "stubnets"
 	yosys -ql test2.log -m ./stubnets.so test.v -p "opt; stubnets"
@@ -7,6 +12,7 @@ test: stubnets.so
 stubnets.so: stubnets.cc
 	yosys-config --exec --cxx --cxxflags --ldflags -o $@ -shared $^ --ldlibs
 
+.PHONY: clean
 clean:
 	rm -f test1.log test2.log test3.log
 	rm -f stubnets.so stubnets.d
diff --git a/yosys/docs/source/CHAPTER_Prog/stubnets.cc b/yosys/docs/source/code_examples/stubnets/stubnets.cc
similarity index 100%
rename from yosys/docs/source/CHAPTER_Prog/stubnets.cc
rename to yosys/docs/source/code_examples/stubnets/stubnets.cc
diff --git a/yosys/docs/source/CHAPTER_Prog/test.v b/yosys/docs/source/code_examples/stubnets/test.v
similarity index 100%
rename from yosys/docs/source/CHAPTER_Prog/test.v
rename to yosys/docs/source/code_examples/stubnets/test.v
diff --git a/yosys/docs/source/code_examples/synth_flow/Makefile b/yosys/docs/source/code_examples/synth_flow/Makefile
new file mode 100644
index 00000000000..cc5a34b26b5
--- /dev/null
+++ b/yosys/docs/source/code_examples/synth_flow/Makefile
@@ -0,0 +1,22 @@
+
+TARGETS += proc_01 proc_02 proc_03
+TARGETS += memory_01 memory_02
+TARGETS += techmap_01
+
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+DOTS = $(addsuffix .dot,$(TARGETS))
+
+.PHONY: all dots
+all: dots
+dots: $(DOTS)
+
+%.dot: %.v %.ys
+	$(YOSYS) -p 'script $*.ys; show -notitle -prefix $* -format dot'
+
+.PHONY: clean
+clean:
+	rm -f *.dot
+
diff --git a/yosys/manual/PRESENTATION_ExSyn/memory_01.v b/yosys/docs/source/code_examples/synth_flow/memory_01.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExSyn/memory_01.v
rename to yosys/docs/source/code_examples/synth_flow/memory_01.v
diff --git a/yosys/manual/PRESENTATION_ExSyn/memory_01.ys b/yosys/docs/source/code_examples/synth_flow/memory_01.ys
similarity index 100%
rename from yosys/manual/PRESENTATION_ExSyn/memory_01.ys
rename to yosys/docs/source/code_examples/synth_flow/memory_01.ys
diff --git a/yosys/manual/PRESENTATION_ExSyn/memory_02.v b/yosys/docs/source/code_examples/synth_flow/memory_02.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExSyn/memory_02.v
rename to yosys/docs/source/code_examples/synth_flow/memory_02.v
diff --git a/yosys/manual/PRESENTATION_ExSyn/memory_02.ys b/yosys/docs/source/code_examples/synth_flow/memory_02.ys
similarity index 100%
rename from yosys/manual/PRESENTATION_ExSyn/memory_02.ys
rename to yosys/docs/source/code_examples/synth_flow/memory_02.ys
diff --git a/yosys/manual/PRESENTATION_ExSyn/proc_01.v b/yosys/docs/source/code_examples/synth_flow/proc_01.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExSyn/proc_01.v
rename to yosys/docs/source/code_examples/synth_flow/proc_01.v
diff --git a/yosys/manual/PRESENTATION_ExSyn/proc_01.ys b/yosys/docs/source/code_examples/synth_flow/proc_01.ys
similarity index 100%
rename from yosys/manual/PRESENTATION_ExSyn/proc_01.ys
rename to yosys/docs/source/code_examples/synth_flow/proc_01.ys
diff --git a/yosys/manual/PRESENTATION_ExSyn/proc_02.v b/yosys/docs/source/code_examples/synth_flow/proc_02.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExSyn/proc_02.v
rename to yosys/docs/source/code_examples/synth_flow/proc_02.v
diff --git a/yosys/manual/PRESENTATION_ExSyn/proc_02.ys b/yosys/docs/source/code_examples/synth_flow/proc_02.ys
similarity index 100%
rename from yosys/manual/PRESENTATION_ExSyn/proc_02.ys
rename to yosys/docs/source/code_examples/synth_flow/proc_02.ys
diff --git a/yosys/manual/PRESENTATION_ExSyn/proc_03.v b/yosys/docs/source/code_examples/synth_flow/proc_03.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExSyn/proc_03.v
rename to yosys/docs/source/code_examples/synth_flow/proc_03.v
diff --git a/yosys/manual/PRESENTATION_ExSyn/proc_03.ys b/yosys/docs/source/code_examples/synth_flow/proc_03.ys
similarity index 100%
rename from yosys/manual/PRESENTATION_ExSyn/proc_03.ys
rename to yosys/docs/source/code_examples/synth_flow/proc_03.ys
diff --git a/yosys/manual/PRESENTATION_ExSyn/techmap_01.v b/yosys/docs/source/code_examples/synth_flow/techmap_01.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExSyn/techmap_01.v
rename to yosys/docs/source/code_examples/synth_flow/techmap_01.v
diff --git a/yosys/manual/PRESENTATION_ExSyn/techmap_01.ys b/yosys/docs/source/code_examples/synth_flow/techmap_01.ys
similarity index 100%
rename from yosys/manual/PRESENTATION_ExSyn/techmap_01.ys
rename to yosys/docs/source/code_examples/synth_flow/techmap_01.ys
diff --git a/yosys/manual/PRESENTATION_ExSyn/techmap_01_map.v b/yosys/docs/source/code_examples/synth_flow/techmap_01_map.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExSyn/techmap_01_map.v
rename to yosys/docs/source/code_examples/synth_flow/techmap_01_map.v
diff --git a/yosys/docs/source/code_examples/techmap/Makefile b/yosys/docs/source/code_examples/techmap/Makefile
new file mode 100644
index 00000000000..e900fea4c5f
--- /dev/null
+++ b/yosys/docs/source/code_examples/techmap/Makefile
@@ -0,0 +1,26 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+.PHONY: all dots
+all: dots
+dots: red_or3x1.dot sym_mul.dot mymul.dot mulshift.dot addshift.dot
+
+red_or3x1.dot: red_or3x1_*
+	$(YOSYS) red_or3x1_test.ys
+
+sym_mul.dot: sym_mul_*
+	$(YOSYS) sym_mul_test.ys
+
+mymul.dot: mymul_*
+	$(YOSYS) mymul_test.ys
+
+mulshift.dot: mulshift_*
+	$(YOSYS) mulshift_test.ys
+
+addshift.dot: addshift_*
+	$(YOSYS) addshift_test.ys
+
+.PHONY: clean
+clean:
+	rm -f *.dot
diff --git a/yosys/manual/PRESENTATION_ExAdv/addshift_map.v b/yosys/docs/source/code_examples/techmap/addshift_map.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/addshift_map.v
rename to yosys/docs/source/code_examples/techmap/addshift_map.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/addshift_test.v b/yosys/docs/source/code_examples/techmap/addshift_test.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/addshift_test.v
rename to yosys/docs/source/code_examples/techmap/addshift_test.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/addshift_test.ys b/yosys/docs/source/code_examples/techmap/addshift_test.ys
similarity index 67%
rename from yosys/manual/PRESENTATION_ExAdv/addshift_test.ys
rename to yosys/docs/source/code_examples/techmap/addshift_test.ys
index c08f1106a25..c15691b3353 100644
--- a/yosys/manual/PRESENTATION_ExAdv/addshift_test.ys
+++ b/yosys/docs/source/code_examples/techmap/addshift_test.ys
@@ -3,4 +3,4 @@ hierarchy -check -top test
 
 techmap -map addshift_map.v;;
 
-show -prefix addshift -format pdf -notitle
+show -prefix addshift -format dot -notitle
diff --git a/yosys/manual/PRESENTATION_ExAdv/mulshift_map.v b/yosys/docs/source/code_examples/techmap/mulshift_map.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/mulshift_map.v
rename to yosys/docs/source/code_examples/techmap/mulshift_map.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/mulshift_test.v b/yosys/docs/source/code_examples/techmap/mulshift_test.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/mulshift_test.v
rename to yosys/docs/source/code_examples/techmap/mulshift_test.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/mulshift_test.ys b/yosys/docs/source/code_examples/techmap/mulshift_test.ys
similarity index 64%
rename from yosys/manual/PRESENTATION_ExAdv/mulshift_test.ys
rename to yosys/docs/source/code_examples/techmap/mulshift_test.ys
index c5dac49eb9b..79daaf0c429 100644
--- a/yosys/manual/PRESENTATION_ExAdv/mulshift_test.ys
+++ b/yosys/docs/source/code_examples/techmap/mulshift_test.ys
@@ -4,4 +4,4 @@ hierarchy -check -top test
 techmap -map sym_mul_map.v \
         -map mulshift_map.v;;
 
-show -prefix mulshift -format pdf -notitle -lib sym_mul_cells.v
+show -prefix mulshift -format dot -notitle -lib sym_mul_cells.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/mymul_map.v b/yosys/docs/source/code_examples/techmap/mymul_map.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/mymul_map.v
rename to yosys/docs/source/code_examples/techmap/mymul_map.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/mymul_test.v b/yosys/docs/source/code_examples/techmap/mymul_test.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/mymul_test.v
rename to yosys/docs/source/code_examples/techmap/mymul_test.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/mymul_test.ys b/yosys/docs/source/code_examples/techmap/mymul_test.ys
similarity index 84%
rename from yosys/manual/PRESENTATION_ExAdv/mymul_test.ys
rename to yosys/docs/source/code_examples/techmap/mymul_test.ys
index 48203e31992..b7176fdc49a 100644
--- a/yosys/manual/PRESENTATION_ExAdv/mymul_test.ys
+++ b/yosys/docs/source/code_examples/techmap/mymul_test.ys
@@ -12,4 +12,4 @@ flatten miter
 sat -verify -prove trigger 0 miter
 
 splitnets -ports test_mapped/A
-show -prefix mymul -format pdf -notitle test_mapped
+show -prefix mymul -format dot -notitle test_mapped
diff --git a/yosys/manual/PRESENTATION_ExAdv/red_or3x1_cells.v b/yosys/docs/source/code_examples/techmap/red_or3x1_cells.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/red_or3x1_cells.v
rename to yosys/docs/source/code_examples/techmap/red_or3x1_cells.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/red_or3x1_map.v b/yosys/docs/source/code_examples/techmap/red_or3x1_map.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/red_or3x1_map.v
rename to yosys/docs/source/code_examples/techmap/red_or3x1_map.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/red_or3x1_test.v b/yosys/docs/source/code_examples/techmap/red_or3x1_test.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/red_or3x1_test.v
rename to yosys/docs/source/code_examples/techmap/red_or3x1_test.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/red_or3x1_test.ys b/yosys/docs/source/code_examples/techmap/red_or3x1_test.ys
similarity index 63%
rename from yosys/manual/PRESENTATION_ExAdv/red_or3x1_test.ys
rename to yosys/docs/source/code_examples/techmap/red_or3x1_test.ys
index b9234603494..891b8177b89 100644
--- a/yosys/manual/PRESENTATION_ExAdv/red_or3x1_test.ys
+++ b/yosys/docs/source/code_examples/techmap/red_or3x1_test.ys
@@ -4,4 +4,4 @@ hierarchy -check -top test
 techmap -map red_or3x1_map.v;;
 
 splitnets -ports
-show -prefix red_or3x1 -format pdf -notitle -lib red_or3x1_cells.v
+show -prefix red_or3x1 -format dot -notitle -lib red_or3x1_cells.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/sym_mul_cells.v b/yosys/docs/source/code_examples/techmap/sym_mul_cells.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/sym_mul_cells.v
rename to yosys/docs/source/code_examples/techmap/sym_mul_cells.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/sym_mul_map.v b/yosys/docs/source/code_examples/techmap/sym_mul_map.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/sym_mul_map.v
rename to yosys/docs/source/code_examples/techmap/sym_mul_map.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/sym_mul_test.v b/yosys/docs/source/code_examples/techmap/sym_mul_test.v
similarity index 100%
rename from yosys/manual/PRESENTATION_ExAdv/sym_mul_test.v
rename to yosys/docs/source/code_examples/techmap/sym_mul_test.v
diff --git a/yosys/manual/PRESENTATION_ExAdv/sym_mul_test.ys b/yosys/docs/source/code_examples/techmap/sym_mul_test.ys
similarity index 57%
rename from yosys/manual/PRESENTATION_ExAdv/sym_mul_test.ys
rename to yosys/docs/source/code_examples/techmap/sym_mul_test.ys
index 0c07e7e877c..f19bee64a95 100644
--- a/yosys/manual/PRESENTATION_ExAdv/sym_mul_test.ys
+++ b/yosys/docs/source/code_examples/techmap/sym_mul_test.ys
@@ -3,4 +3,4 @@ hierarchy -check -top test
 
 techmap -map sym_mul_map.v;;
 
-show -prefix sym_mul -format pdf -notitle -lib sym_mul_cells.v
+show -prefix sym_mul -format dot -notitle -lib sym_mul_cells.v
diff --git a/yosys/docs/source/conf.py b/yosys/docs/source/conf.py
index ab9618c8b47..c9c923e8231 100644
--- a/yosys/docs/source/conf.py
+++ b/yosys/docs/source/conf.py
@@ -4,48 +4,61 @@
 
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
-copyright ='2022 YosysHQ GmbH'
+copyright ='2024 YosysHQ GmbH'
+yosys_ver = "0.42"
 
 # select HTML theme
-html_theme = 'press'
-html_logo = '../static/logo.png'
-html_favicon = '../static/favico.png'
+html_theme = 'furo'
+templates_path = ["_templates"]
+html_logo = '_static/logo.png'
+html_favicon = '_static/favico.png'
 html_css_files = ['yosyshq.css', 'custom.css']
-html_sidebars = {'**': ['util/searchbox.html', 'util/sidetoc.html']}
+
+html_theme_options = {
+    "sidebar_hide_name": True,
+
+    "light_css_variables": {
+        "color-brand-primary": "#d6368f",
+        "color-brand-content": "#4b72b8",
+        "color-api-name": "#8857a3",
+        "color-api-pre-name": "#4b72b8",
+        "color-link": "#8857a3",
+    },
+
+    "dark_css_variables": {
+        "color-brand-primary": "#e488bb",
+        "color-brand-content": "#98bdff",
+        "color-api-name": "#8857a3",
+        "color-api-pre-name": "#4b72b8",
+        "color-link": "#be95d5",
+    },
+}
 
 # These folders are copied to the documentation's HTML output
-html_static_path = ['../static', "../images"]
+html_static_path = ['_static', "_images"]
 
 # code blocks style 
 pygments_style = 'colorful'
 highlight_language = 'none'
 
-html_theme_options = {
-    'external_links' : [
-        ('YosysHQ Docs', 'https://yosyshq.readthedocs.io'),
-        ('Blog', 'https://blog.yosyshq.com'),
-        ('Website', 'https://www.yosyshq.com'),
-    ],
-}
-
 extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.bibtex']
 
 # Ensure that autosectionlabel will produce unique names
 autosectionlabel_prefix_document = True
 autosectionlabel_maxdepth = 1
 
+# set version
+if os.getenv("READTHEDOCS") and os.getenv("READTHEDOCS_VERSION") == "latest":
+    release = yosys_ver + "-dev"
+else:
+    release = yosys_ver
+
 # assign figure numbers
 numfig = True
 
 bibtex_bibfiles = ['literature.bib']
-
-# unused docs
-exclude_patterns = [
-	"CHAPTER_Eval.rst",
-	"appendix/CHAPTER_StateOfTheArt.rst"
-]
-
 latex_elements = {
+        'releasename': 'Version',
         'preamble': r'''
 \usepackage{lmodern}
 \usepackage{comment}
@@ -53,10 +66,17 @@
 '''
 }
 
+# include todos during rewrite
+extensions.append('sphinx.ext.todo')
+todo_include_todos = False
+
+# custom cmd-ref parsing/linking
+sys.path += [os.path.dirname(__file__) + "/../"]
+extensions.append('util.cmdref')
+
 def setup(sphinx):
-	sys.path += [os.path.dirname(__file__) + "/../util"]
-	from RtlilLexer import RtlilLexer
+	from util.RtlilLexer import RtlilLexer
 	sphinx.add_lexer("RTLIL", RtlilLexer)
 
-	from YoscryptLexer import YoscryptLexer
+	from util.YoscryptLexer import YoscryptLexer
 	sphinx.add_lexer("yoscrypt", YoscryptLexer)
\ No newline at end of file
diff --git a/yosys/docs/source/getting_started/example_synth.rst b/yosys/docs/source/getting_started/example_synth.rst
new file mode 100644
index 00000000000..ae0a9a36620
--- /dev/null
+++ b/yosys/docs/source/getting_started/example_synth.rst
@@ -0,0 +1,855 @@
+Synthesis starter
+-----------------
+
+This page will be a guided walkthrough of the prepackaged iCE40 FPGA synthesis
+script - :cmd:ref:`synth_ice40`.  We will take a simple design through each
+step, looking at the commands being called and what they do to the design. While
+:cmd:ref:`synth_ice40` is specific to the iCE40 platform, most of the operations
+we will be discussing are common across the majority of FPGA synthesis scripts.
+Thus, this document will provide a good foundational understanding of how
+synthesis in Yosys is performed, regardless of the actual architecture being
+used.
+
+.. seealso:: Advanced usage docs for
+   :doc:`/using_yosys/synthesis/synth`
+
+Demo design
+~~~~~~~~~~~
+
+.. role:: yoscrypt(code)
+   :language: yoscrypt
+
+First, let's quickly look at the design we'll be synthesizing:
+
+.. todo:: reconsider including the whole (~77 line) design like this
+
+.. literalinclude:: /code_examples/fifo/fifo.v
+   :language: Verilog
+   :linenos:
+   :caption: :file:`fifo.v`
+   :name: fifo-v
+
+.. todo:: fifo.v description
+
+Loading the design
+~~~~~~~~~~~~~~~~~~
+
+Let's load the design into Yosys.  From the command line, we can call ``yosys
+fifo.v``.  This will open an interactive Yosys shell session and immediately
+parse the code from :ref:`fifo-v` and convert it into an Abstract Syntax Tree
+(AST).  If you are interested in how this happens, there is more information in
+the document, :doc:`/yosys_internals/flow/verilog_frontend`.  For now, suffice
+it to say that we do this to simplify further processing of the design.  You
+should see something like the following:
+
+.. literalinclude:: /code_examples/fifo/fifo.out
+   :language: console
+   :start-at: $ yosys fifo.v
+   :end-before: echo on
+
+.. seealso:: Advanced usage docs for
+   :doc:`/using_yosys/more_scripting/load_design`
+
+Elaboration
+~~~~~~~~~~~
+
+Now that we are in the interactive shell, we can call Yosys commands directly.
+Our overall goal is to call :yoscrypt:`synth_ice40 -top fifo`, but for now we
+can run each of the commands individually for a better sense of how each part
+contributes to the flow.  We will also start with just a single module;
+``addr_gen``.
+
+At the bottom of the :cmd:ref:`help` output for
+:cmd:ref:`synth_ice40` is the complete list of commands called by this script.
+Let's start with the section labeled ``begin``:
+
+.. literalinclude:: /cmd/synth_ice40.rst
+   :language: yoscrypt
+   :start-after: begin:
+   :end-before: flatten:
+   :dedent:
+   :caption: ``begin`` section
+   :name: synth_begin
+
+:yoscrypt:`read_verilog -D ICE40_HX -lib -specify +/ice40/cells_sim.v` loads the
+iCE40 cell models which allows us to include platform specific IP blocks in our
+design.  PLLs are a common example of this, where we might need to reference
+``SB_PLL40_CORE`` directly rather than being able to rely on mapping passes
+later.  Since our simple design doesn't use any of these IP blocks, we can skip
+this command for now.  Because these cell models will also be needed once we
+start mapping to hardware we will still need to load them later.
+
+.. note::
+
+   ``+/`` is a dynamic reference to the Yosys ``share`` directory.  By default,
+   this is ``/usr/local/share/yosys``.  If using a locally built version of
+   Yosys from the source directory, this will be the ``share`` folder in the
+   same directory.
+
+.. _addr_gen_example:
+
+The addr_gen module
+^^^^^^^^^^^^^^^^^^^
+
+Since we're just getting started, let's instead begin with :yoscrypt:`hierarchy
+-top addr_gen`.  This command declares that the top level module is
+``addr_gen``, and everything else can be discarded.
+
+.. literalinclude:: /code_examples/fifo/fifo.v
+   :language: Verilog
+   :start-at: module addr_gen
+   :end-at: endmodule //addr_gen
+   :lineno-match:
+   :caption: ``addr_gen`` module source
+   :name: addr_gen-v
+
+.. note::
+
+   :cmd:ref:`hierarchy` should always be the first command after the design has
+   been read.  By specifying the top module, :cmd:ref:`hierarchy` will also set
+   the ``(* top *)`` attribute on it.  This is used by other commands that need
+   to know which module is the top.
+
+.. use doscon for a console-like display that supports the `yosys> [command]` format.
+
+.. literalinclude:: /code_examples/fifo/fifo.out
+   :language: doscon
+   :start-at: yosys> hierarchy -top addr_gen
+   :end-before: yosys> select
+   :caption: :yoscrypt:`hierarchy -top addr_gen` output
+   :name: hierarchy_output
+
+Our ``addr_gen`` circuit now looks like this:
+
+.. figure:: /_images/code_examples/fifo/addr_gen_hier.*
+   :class: width-helper invert-helper
+   :name: addr_gen_hier
+
+   ``addr_gen`` module after :cmd:ref:`hierarchy`
+
+Simple operations like ``addr + 1`` and ``addr == MAX_DATA-1`` can be extracted
+from our ``always @`` block in :ref:`addr_gen-v`. This gives us the highlighted
+``$add`` and ``$eq`` cells we see. But control logic (like the ``if .. else``)
+and memory elements (like the ``addr <= 0``) are not so straightforward.  These
+get put into "processes", shown in the schematic as ``PROC``.  Note how the
+second line refers to the line numbers of the start/end of the corresponding
+``always @`` block.  In the case of an ``initial`` block, we instead see the
+``PROC`` referring to line 0.
+
+To handle these, let us now introduce the next command: :doc:`/cmd/proc`.
+:cmd:ref:`proc` is a macro command like :cmd:ref:`synth_ice40`.  Rather than
+modifying the design directly, it instead calls a series of other commands.  In
+the case of :cmd:ref:`proc`, these sub-commands work to convert the behavioral
+logic of processes into multiplexers and registers.  Let's see what happens when
+we run it.  For now, we will call :yoscrypt:`proc -noopt` to prevent some
+automatic optimizations which would normally happen.
+
+.. figure:: /_images/code_examples/fifo/addr_gen_proc.*
+   :class: width-helper invert-helper
+   :name: addr_gen_proc
+
+   ``addr_gen`` module after :yoscrypt:`proc -noopt`
+
+There are now a few new cells from our ``always @``, which have been
+highlighted.  The ``if`` statements are now modeled with ``$mux`` cells, while
+the register uses an ``$adff`` cell.  If we look at the terminal output we can
+also see all of the different ``proc_*`` commands being called.  We will look at
+each of these in more detail in :doc:`/using_yosys/synthesis/proc`.
+
+Notice how in the top left of :ref:`addr_gen_proc` we have a floating wire,
+generated from the initial assignment of 0 to the ``addr`` wire.  However, this
+initial assignment is not synthesizable, so this will need to be cleaned up
+before we can generate the physical hardware.  We can do this now by calling
+:cmd:ref:`clean`.  We're also going to call :cmd:ref:`opt_expr` now, which would
+normally be called at the end of :cmd:ref:`proc`.  We can call both commands at
+the same time by separating them with a colon and space: :yoscrypt:`opt_expr;
+clean`.
+
+.. figure:: /_images/code_examples/fifo/addr_gen_clean.*
+   :class: width-helper invert-helper
+   :name: addr_gen_clean
+
+   ``addr_gen`` module after :yoscrypt:`opt_expr; clean`
+
+You may also notice that the highlighted ``$eq`` cell input of ``255`` has
+changed to ``8'11111111``.  Constant values are presented in the format
+``<bit_width>'<bits>``, with 32-bit values instead using the decimal number.
+This indicates that the constant input has been reduced from 32-bit wide to
+8-bit wide.  This is a side-effect of running :cmd:ref:`opt_expr`, which
+performs constant folding and simple expression rewriting.    For more on why
+this happens, refer to :doc:`/using_yosys/synthesis/opt` and the :ref:`section
+on opt_expr <adv_opt_expr>`.
+
+.. note::
+
+   :doc:`/cmd/clean` can also be called with two semicolons after any command,
+   for example we could have called :yoscrypt:`opt_expr;;` instead of
+   :yoscrypt:`opt_expr; clean`.  You may notice some scripts will end each line
+   with ``;;``.  It is beneficial to run :cmd:ref:`clean` before inspecting
+   intermediate products to remove disconnected parts of the circuit which have
+   been left over, and in some cases can reduce the processing required in
+   subsequent commands.
+
+.. todo:: consider a brief glossary for terms like adff
+
+.. seealso:: Advanced usage docs for
+   
+   - :doc:`/using_yosys/synthesis/proc`
+   - :doc:`/using_yosys/synthesis/opt`
+
+The full example
+^^^^^^^^^^^^^^^^
+
+Let's now go back and check on our full design by using :yoscrypt:`hierarchy
+-check -top fifo`.  By passing the ``-check`` option there we are also telling
+the :cmd:ref:`hierarchy` command that if the design includes any non-blackbox
+modules without an implementation it should return an error.
+
+Note that if we tried to run this command now then we would get an error.  This
+is because we already removed all of the modules other than ``addr_gen``.  We
+could restart our shell session, but instead let's use two new commands:
+
+- :doc:`/cmd/design`, and
+- :doc:`/cmd/read_verilog`.
+
+.. literalinclude:: /code_examples/fifo/fifo.out
+   :language: doscon
+   :start-at: design -reset
+   :end-before: yosys> proc
+   :caption: reloading :file:`fifo.v` and running :yoscrypt:`hierarchy -check -top fifo`
+
+Notice how this time we didn't see any of those `$abstract` modules?  That's
+because when we ran ``yosys fifo.v``, the first command Yosys called was
+:yoscrypt:`read_verilog -defer fifo.v`.  The ``-defer`` option there tells
+:cmd:ref:`read_verilog` only read the abstract syntax tree and defer actual
+compilation to a later :cmd:ref:`hierarchy` command. This is useful in cases
+where the default parameters of modules yield invalid code which is not
+synthesizable. This is why Yosys defers compilation automatically and is one of
+the reasons why hierarchy should always be the first command after loading the
+design.  If we know that our design won't run into this issue, we can skip the
+``-defer``.
+
+.. todo:: :cmd:ref:`hierarchy` failure modes
+
+.. note::
+
+   The number before a command's output increments with each command run.  Don't
+   worry if your numbers don't match ours!  The output you are seeing comes from
+   the same script that was used to generate the images in this document,
+   included in the source as :file:`fifo.ys`. There are extra commands being run
+   which you don't see, but feel free to try them yourself, or play around with
+   different commands.  You can always start over with a clean slate by calling
+   ``exit`` or hitting :kbd:`ctrl+d` (i.e. EOF) and re-launching the Yosys
+   interactive terminal.  :kbd:`ctrl+c` (i.e. SIGINT) will also end the terminal
+   session but will return an error code rather than exiting gracefully.
+
+We can also run :cmd:ref:`proc` now to finish off the full :ref:`synth_begin`.
+Because the design schematic is quite large, we will be showing just the data
+path for the ``rdata`` output.  If you would like to see the entire design for
+yourself, you can do so with :doc:`/cmd/show`.  Note that the :cmd:ref:`show`
+command only works with a single module, so you may need to call it with
+:yoscrypt:`show fifo`.  :ref:`show_intro` section in
+:doc:`/getting_started/scripting_intro` has more on how to use :cmd:ref:`show`.
+
+.. figure:: /_images/code_examples/fifo/rdata_proc.*
+   :class: width-helper invert-helper
+   :name: rdata_proc
+
+   ``rdata`` output after :cmd:ref:`proc`
+
+The highlighted ``fifo_reader`` block contains an instance of the
+:ref:`addr_gen_proc` that we looked at earlier.  Notice how the type is shown as
+``$paramod\\addr_gen\\MAX_DATA=s32'...``.  This is a "parametric module": an
+instance of the ``addr_gen`` module with the ``MAX_DATA`` parameter set to the
+given value.
+
+The other highlighted block is a ``$memrd`` cell.  At this stage of synthesis we
+don't yet know what type of memory is going to be implemented, but we *do* know
+that ``rdata <= data[raddr];`` could be implemented as a read from memory. Note
+that the ``$memrd`` cell here is asynchronous, with both the clock and enable
+signal undefined; shown with the ``1'x`` inputs.
+
+.. seealso:: Advanced usage docs for
+   :doc:`/using_yosys/synthesis/proc`
+
+Flattening
+~~~~~~~~~~
+
+At this stage of a synthesis flow there are a few other commands we could run.
+In :cmd:ref:`synth_ice40` we get these:
+
+.. literalinclude:: /cmd/synth_ice40.rst
+   :language: yoscrypt
+   :start-after: flatten:
+   :end-before: coarse:
+   :dedent:
+   :name: synth_flatten
+   :caption: ``flatten`` section
+
+First off is :cmd:ref:`flatten`.  Flattening the design like this can allow for
+optimizations between modules which would otherwise be missed.  Let's run
+:yoscrypt:`flatten;;` on our design.
+
+.. literalinclude:: /code_examples/fifo/fifo.out
+   :language: doscon
+   :start-at: yosys> flatten
+   :end-before: yosys> select
+   :name: flat_clean
+   :caption: output of :yoscrypt:`flatten;;`
+
+.. figure:: /_images/code_examples/fifo/rdata_flat.*
+   :class: width-helper invert-helper
+   :name: rdata_flat
+
+   ``rdata`` output after :yoscrypt:`flatten;;`
+
+.. role:: yoterm(code)
+   :language: doscon
+
+The pieces have moved around a bit, but we can see :ref:`addr_gen_proc` from
+earlier has replaced the ``fifo_reader`` block in :ref:`rdata_proc`.  We can
+also see that the ``addr`` output has been renamed to :file:`fifo_reader.addr`
+and merged with the ``raddr`` wire feeding into the ``$memrd`` cell.  This wire
+merging happened during the call to :cmd:ref:`clean` which we can see in the
+:ref:`flat_clean`.
+
+.. note:: 
+
+   :cmd:ref:`flatten` and :cmd:ref:`clean` would normally be combined into a
+   single :yoterm:`yosys> flatten;;` output, but they appear separately here as
+   a side effect of using :cmd:ref:`echo` for generating the terminal style
+   output.
+
+Depending on the target architecture, this stage of synthesis might also see
+commands such as :cmd:ref:`tribuf` with the ``-logic`` option and
+:cmd:ref:`deminout`.  These remove tristate and inout constructs respectively,
+replacing them with logic suitable for mapping to an FPGA.  Since we do not have
+any such constructs in our example running these commands does not change our
+design.
+
+The coarse-grain representation
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+At this stage, the design is in coarse-grain representation.  It still looks
+recognizable, and cells are word-level operators with parametrizable width. This
+is the stage of synthesis where we do things like const propagation, expression
+rewriting, and trimming unused parts of wires.
+
+This is also where we convert our FSMs and hard blocks like DSPs or memories.
+Such elements have to be inferred from patterns in the design and there are
+special passes for each.  Detection of these patterns can also be affected by
+optimizations and other transformations done previously.
+
+.. note::
+
+   While the iCE40 flow had a :ref:`synth_flatten` and put :cmd:ref:`proc` in
+   the :ref:`synth_begin`, some synthesis scripts will instead include these in
+   this section.
+
+Part 1
+^^^^^^
+
+In the iCE40 flow, we start with the following commands:
+
+.. literalinclude:: /cmd/synth_ice40.rst
+   :language: yoscrypt
+   :start-after: coarse:
+   :end-before: wreduce
+   :dedent:
+   :caption: ``coarse`` section (part 1)
+   :name: synth_coarse1
+
+We've already come across :cmd:ref:`opt_expr`, and :cmd:ref:`opt_clean` is the
+same as :cmd:ref:`clean` but with more verbose output.  The :cmd:ref:`check`
+pass identifies a few obvious problems which will cause errors later.  Calling
+it here lets us fail faster rather than wasting time on something we know is
+impossible.
+
+Next up is :yoscrypt:`opt -nodffe -nosdff` performing a set of simple
+optimizations on the design.  This command also ensures that only a specific
+subset of FF types are included, in preparation for the next command:
+:doc:`/cmd/fsm`.  Both :cmd:ref:`opt` and :cmd:ref:`fsm` are macro commands
+which are explored in more detail in :doc:`/using_yosys/synthesis/opt` and
+:doc:`/using_yosys/synthesis/fsm` respectively.
+
+Up until now, the data path for ``rdata`` has remained the same since
+:ref:`rdata_flat`.  However the next call to :cmd:ref:`opt` does cause a change.
+Specifically, the call to :cmd:ref:`opt_dff` without the ``-nodffe -nosdff``
+options is able to fold one of the ``$mux`` cells into the ``$adff`` to form an
+``$adffe`` cell; highlighted below:
+
+.. literalinclude:: /code_examples/fifo/fifo.out
+   :language: doscon
+   :start-at: yosys> opt_dff
+   :end-before: yosys> select
+   :caption: output of :cmd:ref:`opt_dff`
+
+.. figure:: /_images/code_examples/fifo/rdata_adffe.*
+   :class: width-helper invert-helper
+   :name: rdata_adffe
+
+   ``rdata`` output after :cmd:ref:`opt_dff`
+
+.. seealso:: Advanced usage docs for
+   
+   - :doc:`/using_yosys/synthesis/fsm`
+   - :doc:`/using_yosys/synthesis/opt`
+
+Part 2
+^^^^^^
+
+The next group of commands performs a series of optimizations:
+
+.. literalinclude:: /cmd/synth_ice40.rst
+   :language: yoscrypt
+   :start-at: wreduce
+   :end-before: t:$mul
+   :dedent:
+   :caption: ``coarse`` section (part 2)
+   :name: synth_coarse2
+
+First up is :doc:`/cmd/wreduce`.  If we run this we get the following:
+
+.. literalinclude:: /code_examples/fifo/fifo.out
+   :language: doscon
+   :start-at: yosys> wreduce
+   :end-before: yosys> select
+   :caption: output of :cmd:ref:`wreduce`
+
+Looking at the data path for ``rdata``, the most relevant of these width
+reductions are the ones affecting ``fifo.$flatten\fifo_reader.$add$fifo.v``.
+That is the ``$add`` cell incrementing the fifo_reader address.  We can look at
+the schematic and see the output of that cell has now changed.
+
+.. todo:: pending bugfix in :cmd:ref:`wreduce` and/or :cmd:ref:`opt_clean`
+
+.. figure:: /_images/code_examples/fifo/rdata_wreduce.*
+   :class: width-helper invert-helper
+   :name: rdata_wreduce
+
+   ``rdata`` output after :cmd:ref:`wreduce`
+
+The next two (new) commands are :doc:`/cmd/peepopt` and :doc:`/cmd/share`.
+Neither of these affect our design, and they're explored in more detail in
+:doc:`/using_yosys/synthesis/opt`, so let's skip over them.  :yoscrypt:`techmap
+-map +/cmp2lut.v -D LUT_WIDTH=4` optimizes certain comparison operators by
+converting them to LUTs instead.  The usage of :cmd:ref:`techmap` is explored
+more in :doc:`/using_yosys/synthesis/techmap_synth`.
+
+Our next command to run is
+:doc:`/cmd/memory_dff`.
+
+.. literalinclude:: /code_examples/fifo/fifo.out
+   :language: doscon
+   :start-at: yosys> memory_dff
+   :end-before: yosys> select
+   :caption: output of :cmd:ref:`memory_dff`
+
+.. figure:: /_images/code_examples/fifo/rdata_memrdv2.*
+   :class: width-helper invert-helper
+   :name: rdata_memrdv2
+
+   ``rdata`` output after :cmd:ref:`memory_dff`
+
+As the title suggests, :cmd:ref:`memory_dff` has merged the output ``$dff`` into
+the ``$memrd`` cell and converted it to a ``$memrd_v2`` (highlighted).  This has
+also connected the ``CLK`` port to the ``clk`` input as it is now a synchronous
+memory read with appropriate enable (``EN=1'1``) and reset (``ARST=1'0`` and
+``SRST=1'0``) inputs.
+
+.. seealso:: Advanced usage docs for
+   
+   - :doc:`/using_yosys/synthesis/opt`
+   - :doc:`/using_yosys/synthesis/techmap_synth`
+   - :doc:`/using_yosys/synthesis/memory`
+
+Part 3
+^^^^^^
+
+The third part of the :cmd:ref:`synth_ice40` flow is a series of commands for
+mapping to DSPs.  By default, the iCE40 flow will not map to the hardware DSP
+blocks and will only be performed if called with the ``-dsp`` flag:
+:yoscrypt:`synth_ice40 -dsp`.  While our example has nothing that could be
+mapped to DSPs we can still take a quick look at the commands here and describe
+what they do.
+
+.. literalinclude:: /cmd/synth_ice40.rst
+   :language: yoscrypt
+   :start-at: t:$mul
+   :end-before: alumacc
+   :dedent:
+   :caption: ``coarse`` section (part 3)
+   :name: synth_coarse3
+
+:yoscrypt:`wreduce t:$mul` performs width reduction again, this time targetting
+only cells of type ``$mul``.  :yoscrypt:`techmap -map +/mul2dsp.v -map
++/ice40/dsp_map.v ... -D DSP_NAME=$__MUL16X16` uses :cmd:ref:`techmap` to map
+``$mul`` cells to ``$__MUL16X16`` which are, in turn, mapped to the iCE40
+``SB_MAC16``.  Any multipliers which aren't compatible with conversion to
+``$__MUL16X16`` are relabelled to ``$__soft_mul`` before :cmd:ref:`chtype`
+changes them back to ``$mul``.
+
+During the mul2dsp conversion, some of the intermediate signals are marked with
+the attribute ``mul2dsp``.  By calling :yoscrypt:`select a:mul2dsp` we restrict
+the following commands to only operate on the cells and wires used for these
+signals.  :cmd:ref:`setattr` removes the now unnecessary ``mul2dsp`` attribute.
+:cmd:ref:`opt_expr` we've already come across for const folding and simple
+expression rewriting, the ``-fine`` option just enables more fine-grain
+optimizations.  Then we perform width reduction a final time and clear the
+selection.
+
+.. todo:: ``ice40_dsp`` is pmgen
+
+Finally we have :cmd:ref:`ice40_dsp`: similar to the :cmd:ref:`memory_dff`
+command we saw in the previous section, this merges any surrounding registers
+into the ``SB_MAC16`` cell.  This includes not just the input/output registers,
+but also pipeline registers and even a post-adder where applicable: turning a
+multiply + add into a single multiply-accumulate.
+
+.. seealso:: Advanced usage docs for
+   :doc:`/using_yosys/synthesis/techmap_synth`
+
+Part 4
+^^^^^^
+
+That brings us to the fourth and final part for the iCE40 synthesis flow:
+
+.. literalinclude:: /cmd/synth_ice40.rst
+   :language: yoscrypt
+   :start-at: alumacc
+   :end-before: map_ram:
+   :dedent:
+   :caption: ``coarse`` section (part 4)
+   :name: synth_coarse4
+
+Where before each type of arithmetic operation had its own cell, e.g. ``$add``,
+we now want to extract these into ``$alu`` and ``$macc`` cells which can help
+identify opportunities for reusing logic.  We do this by running
+:cmd:ref:`alumacc`, which we can see produce the following changes in our
+example design:
+
+.. literalinclude:: /code_examples/fifo/fifo.out
+   :language: doscon
+   :start-at: yosys> alumacc
+   :end-before: yosys> select
+   :caption: output of :cmd:ref:`alumacc`
+
+.. figure:: /_images/code_examples/fifo/rdata_alumacc.*
+   :class: width-helper invert-helper
+   :name: rdata_alumacc
+
+   ``rdata`` output after :cmd:ref:`alumacc`
+
+Once these cells have been inserted, the call to :cmd:ref:`opt` can combine
+cells which are now identical but may have been missed due to e.g. the
+difference between ``$add`` and ``$sub``.
+
+The other new command in this part is :doc:`/cmd/memory`.  :cmd:ref:`memory` is
+another macro command which we examine in more detail in
+:doc:`/using_yosys/synthesis/memory`.  For this document, let us focus just on
+the step most relevant to our example: :cmd:ref:`memory_collect`. Up until this
+point, our memory reads and our memory writes have been totally disjoint cells;
+operating on the same memory only in the abstract. :cmd:ref:`memory_collect`
+combines all of the reads and writes for a memory block into a single cell.
+
+.. figure:: /_images/code_examples/fifo/rdata_coarse.*
+   :class: width-helper invert-helper
+   :name: rdata_coarse
+
+   ``rdata`` output after :cmd:ref:`memory_collect`
+
+Looking at the schematic after running :cmd:ref:`memory_collect` we see that our
+``$memrd_v2`` cell has been replaced with a ``$mem_v2`` cell named ``data``, the
+same name that we used in :ref:`fifo-v`. Where before we had a single set of
+signals for address and enable, we now have one set for reading (``RD_*``) and
+one for writing (``WR_*``), as well as both ``WR_DATA`` input and ``RD_DATA``
+output.
+
+.. seealso:: Advanced usage docs for
+
+   - :doc:`/using_yosys/synthesis/opt`
+   - :doc:`/using_yosys/synthesis/memory`
+
+Final note
+^^^^^^^^^^
+
+Having now reached the end of the the coarse-grain representation, we could also
+have gotten here by running :yoscrypt:`synth_ice40 -top fifo -run :map_ram`
+after loading the design.  The :yoscrypt:`-run <from_label>:<to_label>` option
+with an empty ``<from_label>`` starts from the :ref:`synth_begin`, while the
+``<to_label>`` runs up to but including the :ref:`map_ram`.
+
+Hardware mapping
+~~~~~~~~~~~~~~~~
+
+The remaining sections each map a different type of hardware and are much more
+architecture dependent than the previous sections.  As such we will only be
+looking at each section very briefly.
+
+If you skipped calling :yoscrypt:`read_verilog -D ICE40_HX -lib -specify
++/ice40/cells_sim.v` earlier, do it now.
+
+Memory blocks
+^^^^^^^^^^^^^
+
+Mapping to hard memory blocks uses a combination of :cmd:ref:`memory_libmap` and
+:cmd:ref:`techmap`.
+
+.. literalinclude:: /cmd/synth_ice40.rst
+   :language: yoscrypt
+   :start-after: map_ram:
+   :end-before: map_ffram:
+   :dedent:
+   :name: map_ram
+   :caption: ``map_ram`` section
+
+.. figure:: /_images/code_examples/fifo/rdata_map_ram.*
+   :class: width-helper invert-helper
+   :name: rdata_map_ram
+
+   ``rdata`` output after :ref:`map_ram`
+
+The :ref:`map_ram` converts the generic ``$mem_v2`` into the iCE40
+``SB_RAM40_4K`` (highlighted). We can also see the memory address has been
+remapped, and the data bits have been reordered (or swizzled).  There is also
+now a ``$mux`` cell controlling the value of ``rdata``.  In :ref:`fifo-v` we
+wrote our memory as read-before-write, however the ``SB_RAM40_4K`` has undefined
+behaviour when reading from and writing to the same address in the same cycle.
+As a result, extra logic is added so that the generated circuit matches the
+behaviour of the verilog.  :ref:`no_rw_check` describes how we could change our
+verilog to match our hardware instead.
+
+If we run :cmd:ref:`memory_libmap` under the :cmd:ref:`debug` command we can see
+candidates which were identified for mapping, along with the costs of each and
+what logic requires emulation.
+
+.. literalinclude:: /code_examples/fifo/fifo.libmap
+   :language: doscon
+   :lines: 2, 6-
+
+The ``$__ICE40_RAM4K_`` cell is defined in the file |techlibs/ice40/brams.txt|_,
+with the mapping to ``SB_RAM40_4K`` done by :cmd:ref:`techmap` using
+|techlibs/ice40/brams_map.v|_.  Any leftover memory cells are then converted
+into flip flops (the ``logic fallback``) with :cmd:ref:`memory_map`.
+
+.. |techlibs/ice40/brams.txt| replace:: :file:`techlibs/ice40/brams.txt`
+.. _techlibs/ice40/brams.txt: https://github.com/YosysHQ/yosys/tree/main/techlibs/ice40/brams.txt
+.. |techlibs/ice40/brams_map.v| replace:: :file:`techlibs/ice40/brams_map.v`
+.. _techlibs/ice40/brams_map.v: https://github.com/YosysHQ/yosys/tree/main/techlibs/ice40/brams_map.v
+
+.. literalinclude:: /cmd/synth_ice40.rst
+   :language: yoscrypt
+   :start-after: map_ffram:
+   :end-before: map_gates:
+   :dedent:
+   :name: map_ffram
+   :caption: ``map_ffram`` section
+
+.. figure:: /_images/code_examples/fifo/rdata_map_ffram.*
+   :class: width-helper invert-helper
+   :name: rdata_map_ffram
+
+   ``rdata`` output after :ref:`map_ffram`
+
+.. note::
+
+   The visual clutter on the ``RDATA`` output port (highlighted) is an
+   unfortunate side effect of :cmd:ref:`opt_clean` on the swizzled data bits. In
+   connecting the ``$mux`` input port directly to ``RDATA`` to reduce the number
+   of wires, the ``$techmap579\data.0.0.RDATA`` wire becomes more visually
+   complex.
+
+.. seealso:: Advanced usage docs for
+   
+   - :doc:`/using_yosys/synthesis/techmap_synth`
+   - :doc:`/using_yosys/synthesis/memory`
+
+Arithmetic
+^^^^^^^^^^
+
+Uses :cmd:ref:`techmap` to map basic arithmetic logic to hardware.  This sees
+somewhat of an explosion in cells as multi-bit ``$mux`` and ``$adffe`` are
+replaced with single-bit ``$_MUX_`` and ``$_DFFE_PP0P_`` cells, while the
+``$alu`` is replaced with primitive ``$_OR_`` and ``$_NOT_`` gates and a
+``$lut`` cell.
+
+.. literalinclude:: /cmd/synth_ice40.rst
+   :language: yoscrypt
+   :start-after: map_gates:
+   :end-before: map_ffs:
+   :dedent:
+   :name: map_gates
+   :caption: ``map_gates`` section
+
+.. figure:: /_images/code_examples/fifo/rdata_map_gates.*
+   :class: width-helper invert-helper
+   :name: rdata_map_gates
+
+   ``rdata`` output after :ref:`map_gates`
+
+.. seealso:: Advanced usage docs for
+   :doc:`/using_yosys/synthesis/techmap_synth`
+
+Flip-flops
+^^^^^^^^^^
+
+Convert FFs to the types supported in hardware with :cmd:ref:`dfflegalize`, and
+then use :cmd:ref:`techmap` to map them.  In our example, this converts the
+``$_DFFE_PP0P_`` cells to ``SB_DFFER``.
+
+We also run :cmd:ref:`simplemap` here to convert any remaining cells which could
+not be mapped to hardware into gate-level primitives.  This includes optimizing
+``$_MUX_`` cells where one of the inputs is a constant ``1'0``, replacing it
+instead with an ``$_AND_`` cell.
+
+.. literalinclude:: /cmd/synth_ice40.rst
+   :language: yoscrypt
+   :start-after: map_ffs:
+   :end-before: map_luts:
+   :dedent:
+   :name: map_ffs
+   :caption: ``map_ffs`` section
+
+.. figure:: /_images/code_examples/fifo/rdata_map_ffs.*
+   :class: width-helper invert-helper
+   :name: rdata_map_ffs
+
+   ``rdata`` output after :ref:`map_ffs`
+
+.. seealso:: Advanced usage docs for
+   :doc:`/using_yosys/synthesis/techmap_synth`
+
+LUTs
+^^^^
+
+:cmd:ref:`abc` and :cmd:ref:`techmap` are used to map LUTs; converting primitive
+cell types to use ``$lut`` and ``SB_CARRY`` cells.  Note that the iCE40 flow
+uses :cmd:ref:`abc9` rather than :cmd:ref:`abc`. For more on what these do, and
+what the difference between these two commands are, refer to
+:doc:`/using_yosys/synthesis/abc`.
+
+.. literalinclude:: /cmd/synth_ice40.rst
+   :language: yoscrypt
+   :start-after: map_luts:
+   :end-before: map_cells:
+   :dedent:
+   :name: map_luts
+   :caption: ``map_luts`` section
+
+.. figure:: /_images/code_examples/fifo/rdata_map_luts.*
+   :class: width-helper invert-helper
+   :name: rdata_map_luts
+
+   ``rdata`` output after :ref:`map_luts`
+
+Finally we use :cmd:ref:`techmap` to map the generic ``$lut`` cells to iCE40
+``SB_LUT4`` cells.
+
+.. literalinclude:: /cmd/synth_ice40.rst
+   :language: yoscrypt
+   :start-after: map_cells:
+   :end-before: check:
+   :dedent:
+   :name: map_cells
+   :caption: ``map_cells`` section
+
+.. figure:: /_images/code_examples/fifo/rdata_map_cells.*
+   :class: width-helper invert-helper
+   :name: rdata_map_cells
+
+   ``rdata`` output after :ref:`map_cells`
+
+.. seealso:: Advanced usage docs for
+   
+   - :doc:`/using_yosys/synthesis/techmap_synth`
+   - :doc:`/using_yosys/synthesis/abc`
+
+Other cells
+^^^^^^^^^^^
+
+The following commands may also be used for mapping other cells:
+
+:cmd:ref:`hilomap`
+    Some architectures require special driver cells for driving a constant hi or
+    lo value. This command replaces simple constants with instances of such
+    driver cells.
+
+:cmd:ref:`iopadmap`
+    Top-level input/outputs must usually be implemented using special I/O-pad
+    cells. This command inserts such cells to the design.
+
+These commands tend to either be in the :ref:`map_cells` or after the
+:ref:`check` depending on the flow.
+
+Final steps
+~~~~~~~~~~~~
+
+The next section of the iCE40 synth flow performs some sanity checking and final
+tidy up:
+
+.. literalinclude:: /cmd/synth_ice40.rst
+   :language: yoscrypt
+   :start-after: check:
+   :end-before: blif:
+   :dedent:
+   :name: check
+   :caption: ``check`` section
+
+The new commands here are:
+
+- :doc:`/cmd/autoname`,
+- :doc:`/cmd/stat`, and
+- :doc:`/cmd/blackbox`.
+
+The output from :cmd:ref:`stat` is useful for checking resource utilization;
+providing a list of cells used in the design and the number of each, as well as
+the number of other resources used such as wires and processes.  For this
+design, the final call to :cmd:ref:`stat` should look something like the
+following:
+
+.. literalinclude:: /code_examples/fifo/fifo.stat
+   :language: doscon
+   :start-at: yosys> stat -top fifo
+
+Note that the :yoscrypt:`-top fifo` here is optional.  :cmd:ref:`stat` will
+automatically use the module with the ``top`` attribute set, which ``fifo`` was
+when we called :cmd:ref:`hierarchy`.  If no module is marked ``top``, then stats
+will be shown for each module selected.
+
+The :cmd:ref:`stat` output is also useful as a kind of sanity-check: Since we
+have already run :cmd:ref:`proc`, we wouldn't expect there to be any processes.
+We also expect ``data`` to use hard memory; if instead of an ``SB_RAM40_4K`` saw
+a high number of flip-flops being used we might suspect something was wrong.
+
+If we instead called :cmd:ref:`stat` immediately after :yoscrypt:`read_verilog
+fifo.v` we would see something very different:
+
+.. literalinclude:: /code_examples/fifo/fifo.stat
+   :language: doscon
+   :start-at: yosys> stat
+   :end-before: yosys> stat -top fifo
+
+Notice how ``fifo`` and ``addr_gen`` are listed separately, and the statistics
+for ``fifo`` show 2 ``addr_gen`` modules.  Because this is before the memory has
+been mapped, we also see that there is 1 memory with 2048 memory bits; matching
+our 8-bit wide ``data`` memory with 256 values (:math:`8*256=2048`).
+
+Synthesis output
+^^^^^^^^^^^^^^^^
+
+The iCE40 synthesis flow has the following output modes available:
+
+- :doc:`/cmd/write_blif`,
+- :doc:`/cmd/write_edif`, and
+- :doc:`/cmd/write_json`.
+
+As an example, if we called :yoscrypt:`synth_ice40 -top fifo -json fifo.json`,
+our synthesized ``fifo`` design will be output as :file:`fifo.json`.  We can
+then read the design back into Yosys with :cmd:ref:`read_json`, but make sure
+you use :yoscrypt:`design -reset` or open a new interactive terminal first.  The
+JSON output we get can also be loaded into `nextpnr`_ to do place and route; but
+that is beyond the scope of this documentation.
+
+.. _nextpnr: https://github.com/YosysHQ/nextpnr
+
+.. seealso:: :doc:`/cmd/synth_ice40`
diff --git a/yosys/docs/source/getting_started/index.rst b/yosys/docs/source/getting_started/index.rst
new file mode 100644
index 00000000000..7a92c212ae6
--- /dev/null
+++ b/yosys/docs/source/getting_started/index.rst
@@ -0,0 +1,13 @@
+Getting started with Yosys
+==========================
+
+This section covers how to get started with Yosys, from installation to a guided
+walkthrough of synthesizing a design for hardware, and finishing with an
+introduction to writing re-usable Yosys scripts.
+
+.. toctree::
+   :maxdepth: 3
+
+   installation
+   example_synth
+   scripting_intro
diff --git a/yosys/docs/source/getting_started/installation.rst b/yosys/docs/source/getting_started/installation.rst
new file mode 100644
index 00000000000..4dd5244b912
--- /dev/null
+++ b/yosys/docs/source/getting_started/installation.rst
@@ -0,0 +1,216 @@
+Installation
+------------
+
+This document will guide you through the process of installing Yosys.
+
+CAD suite(s)
+~~~~~~~~~~~~
+
+Yosys is part of the `Tabby CAD Suite
+<https://www.yosyshq.com/tabby-cad-datasheet>`_ and the `OSS CAD Suite
+<https://github.com/YosysHQ/oss-cad-suite-build>`_! The easiest way to use yosys
+is to install the binary software suite, which contains all required
+dependencies and related tools.
+
+* `Contact YosysHQ <https://www.yosyshq.com/contact>`_ for a `Tabby CAD Suite
+  <https://www.yosyshq.com/tabby-cad-datasheet>`_ Evaluation License and
+  download link
+* OR go to https://github.com/YosysHQ/oss-cad-suite-build/releases to download
+  the free OSS CAD Suite
+* Follow the `Install Instructions on GitHub
+  <https://github.com/YosysHQ/oss-cad-suite-build#installation>`_
+
+Make sure to get a Tabby CAD Suite Evaluation License if you need features such
+as industry-grade SystemVerilog and VHDL parsers!
+
+For more information about the difference between Tabby CAD Suite and the OSS
+CAD Suite, please visit https://www.yosyshq.com/tabby-cad-datasheet
+
+Many Linux distributions also provide Yosys binaries, some more up to date than
+others. Check with your package manager!
+
+Targeted architectures
+^^^^^^^^^^^^^^^^^^^^^^
+
+The `OSS CAD Suite`_ releases `nightly builds`_ for the following architectures:
+
+.. only:: html
+
+   - linux-x64 |linux-x64|
+      - Most personal Linux based computers
+
+   - darwin-x64 |darwin-x64|
+      - macOS 12 or later with Intel CPU
+
+   - darwin-arm64 |darwin-arm64|
+      - macOS 12 or later with M1/M2 CPU
+
+   - windows-x64 |windows-x64|
+      - Targeted for Windows 10 and 11
+
+   - linux-arm64 |linux-arm64|
+
+.. _OSS CAD Suite: https://github.com/YosysHQ/oss-cad-suite-build
+.. _nightly builds: https://github.com/YosysHQ/oss-cad-suite-build/releases/latest
+
+.. |linux-x64| image:: https://github.com/YosysHQ/oss-cad-suite-build/actions/workflows/linux-x64.yml/badge.svg
+.. |darwin-x64| image:: https://github.com/YosysHQ/oss-cad-suite-build/actions/workflows/darwin-x64.yml/badge.svg
+.. |darwin-arm64| image:: https://github.com/YosysHQ/oss-cad-suite-build/actions/workflows/darwin-arm64.yml/badge.svg
+.. |windows-x64| image:: https://github.com/YosysHQ/oss-cad-suite-build/actions/workflows/windows-x64.yml/badge.svg
+.. |linux-arm64| image:: https://github.com/YosysHQ/oss-cad-suite-build/actions/workflows/linux-arm64.yml/badge.svg
+
+Building from source
+~~~~~~~~~~~~~~~~~~~~
+
+Refer to the `readme`_ for the most up-to-date install instructions.
+
+.. _readme: https://github.com/YosysHQ/yosys#building-from-source
+
+Supported platforms
+^^^^^^^^^^^^^^^^^^^
+
+The following platforms are supported and regularly tested:
+
+- Linux
+- macOS
+
+Other platforms which may work, but instructions may not be up to date and are
+not regularly tested:
+
+- FreeBSD
+- WSL
+- Windows with (e.g.) Cygwin
+
+Build prerequisites
+^^^^^^^^^^^^^^^^^^^
+
+A C++ compiler with C++11 support is required as well as some standard tools
+such as GNU Flex, GNU Bison, Make and Python.  Some additional tools: readline,
+libffi, Tcl and zlib; are optional but enabled by default (see
+:makevar:`ENABLE_*` settings in Makefile). Graphviz and Xdot are used by the
+:cmd:ref:`show` command to display schematics.
+
+Installing all prerequisites for Ubuntu 20.04:
+
+.. code:: console
+
+   sudo sudo apt-get install build-essential clang bison flex \
+      libreadline-dev gawk tcl-dev libffi-dev git make \
+      graphviz xdot pkg-config python3 libboost-system-dev \
+      libboost-python-dev libboost-filesystem-dev zlib1g-dev
+
+Installing all prerequisites for macOS 11 (with Homebrew):
+
+.. code:: console
+
+   brew install bison flex gawk libffi git graphviz \
+      pkg-config python3 tcl-tk xdot bash boost-python3
+
+Running the build system
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+From the root `yosys` directory, call the following commands:
+
+.. code:: console
+   
+   make
+   sudo make install
+
+This will build and then install Yosys, making it available on the command line
+as `yosys`.  Note that this also downloads, builds, and installs `ABC`_ (using
+:program:`yosys-abc` as the executable name).
+
+.. _ABC: https://github.com/berkeley-abc/abc
+
+The default compiler is ``clang``, to change between ``clang`` and ``gcc``, use
+one of the following:
+
+.. code:: console
+
+   make config-clang
+   make config-gcc
+
+To use a compiler different than the default, use:
+
+.. code:: console
+
+   make CXX="g++-11"
+
+.. seealso:: 
+
+   Refer to :doc:`/test_suites` for details on testing Yosys once compiled.
+
+Source tree and build system
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The Yosys source tree is organized into the following top-level
+directories:
+
+``backends/``
+   This directory contains a subdirectory for each of the backend modules.
+
+``docs/``
+   Contains the source for this documentation, including images and sample code.
+
+``examples/``
+   Contains example code for using Yosys with some other tools including a demo
+   of the Yosys Python api, and synthesizing for various toolchains such as
+   Intel and Anlogic.
+
+``frontends/``
+   This directory contains a subdirectory for each of the frontend modules.
+
+``guidelines/``
+   Contains developer guidelines, including the code of conduct and coding style
+   guide.
+
+``kernel/``
+   This directory contains all the core functionality of Yosys. This includes
+   the functions and definitions for working with the RTLIL data structures
+   (:file:`rtlil.{h|cc}`), the ``main()`` function (:file:`driver.cc`), the
+   internal framework for generating log messages (:file:`log.{h|cc}`), the
+   internal framework for registering and calling passes
+   (:file:`register.{h|cc}`), some core commands that are not really passes
+   (:file:`select.cc`, :file:`show.cc`, …) and a couple of other small utility
+   libraries.
+
+``libs/``
+   Libraries packaged with Yosys builds are contained in this folder.  See
+   :doc:`/appendix/auxlibs`.
+
+``misc/``
+   Other miscellany which doesn't fit anywhere else.
+
+``passes/``
+   This directory contains a subdirectory for each pass or group of passes. For
+   example as of this writing the directory :file:`passes/hierarchy/` contains the
+   code for three passes: :cmd:ref:`hierarchy`, :cmd:ref:`submod`, and
+   :cmd:ref:`uniquify`.
+
+``techlibs/``
+   This directory contains simulation models and standard implementations for
+   the cells from the internal cell library.
+
+``tests/``
+   This directory contains the suite of unit tests and regression tests used by
+   Yosys.  See :doc:`/test_suites`.
+
+The top-level Makefile includes :file:`frontends/{*}/Makefile.inc`,
+:file:`passes/{*}/Makefile.inc` and :file:`backends/{*}/Makefile.inc`. So when
+extending Yosys it is enough to create a new directory in :file:`frontends/`,
+:file:`passes/` or :file:`backends/` with your sources and a
+:file:`Makefile.inc`. The Yosys kernel automatically detects all commands linked
+with Yosys. So it is not needed to add additional commands to a central list of
+commands.
+
+Good starting points for reading example source code to learn how to write
+passes are :file:`passes/opt/opt_dff.cc` and :file:`passes/opt/opt_merge.cc`.
+
+See the top-level README file for a quick Getting Started guide and build
+instructions. The Yosys build is based solely on Makefiles.
+
+Users of the Qt Creator IDE can generate a QT Creator project file using make
+qtcreator. Users of the Eclipse IDE can use the "Makefile Project with Existing
+Code" project type in the Eclipse "New Project" dialog (only available after the
+CDT plugin has been installed) to create an Eclipse project in order to
+programming extensions to Yosys or just browse the Yosys code base.
diff --git a/yosys/docs/source/getting_started/scripting_intro.rst b/yosys/docs/source/getting_started/scripting_intro.rst
new file mode 100644
index 00000000000..a6b4cb6bb42
--- /dev/null
+++ b/yosys/docs/source/getting_started/scripting_intro.rst
@@ -0,0 +1,227 @@
+Scripting in Yosys
+------------------
+
+On the previous page we went through a synthesis script, running each command in
+the interactive Yosys shell.  On this page, we will be introducing the script
+file format and how you can make your own synthesis scripts.
+
+Yosys script files typically use the :file:`.ys` extension and contain a set of
+commands for Yosys to run sequentially.  These commands are the same ones we
+were using on the previous page like :cmd:ref:`read_verilog` and
+:cmd:ref:`hierarchy`.
+
+Script parsing
+~~~~~~~~~~~~~~
+
+As with the interactive shell, each command consists of the command name, and an
+optional whitespace separated list of arguments. Commands are terminated with
+the newline character, and anything after a hash sign ``#`` is a comment (i.e.
+it is ignored).
+
+It is also possible to terminate commands with a semicolon ``;``.  This is
+particularly useful in conjunction with the ``-p <command>`` command line
+option, where ``<command>`` can be a string with multiple commands separated by
+semicolon. In-line comments can also be made with the colon ``:``, where the end
+of the comment is a semicolon ``;`` or a new line.
+
+.. code-block::
+   :caption: Using the ``-p`` option
+
+   $ yosys -p "read_verilog fifo.v; :this is a comment; prep"
+
+.. warning::
+
+   The space after the semicolon is required for correct parsing. ``log a;log
+   b;`` for example will display ``a;log b`` instead of ``a`` and ``b`` as might
+   be expected.
+
+Another special character that can be used in Yosys scripts is the bang ``!``.
+Anything after the bang will be executed as a shell command.  This can only be
+terminated with a new line.  Any semicolons, hashes, or other special characters
+will be passed to the shell.  If an error code is returned from the shell it
+will be raised by Yosys.  :cmd:ref:`exec` provides a much more flexible way of
+executing commands, allowing the output to be logged and more control over when
+to generate errors.
+
+The synthesis starter script
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. role:: yoscrypt(code)
+   :language: yoscrypt
+
+All of the images and console output used in
+:doc:`/getting_started/example_synth` were generated by Yosys, using Yosys
+script files found in :file:`docs/source/code_examples/fifo`. If you haven't
+already, let's take a look at some of those script files now.
+
+.. literalinclude:: /code_examples/fifo/fifo.ys
+   :language: yoscrypt
+   :lineno-match:
+   :start-at: echo on
+   :end-before: design -reset
+   :caption: A section of :file:`fifo.ys`, generating the images used for :ref:`addr_gen_example`
+   :name: fifo-ys
+
+The first command there, :yoscrypt:`echo on`, uses :cmd:ref:`echo` to enable
+command echoes on.  This is how we generated the code listing for
+:ref:`hierarchy_output`.  Turning command echoes on prints the ``yosys>
+hierarchy -top addr_gen`` line, making the output look the same as if it were an
+interactive terminal.  :yoscrypt:`hierarchy -top addr_gen` is of course the
+command we were demonstrating, including the output text and an image of the
+design schematic after running it.
+
+We briefly touched on :cmd:ref:`select` when it came up in
+:cmd:ref:`synth_ice40`, but let's look at it more now.
+
+.. _select_intro:
+
+Selections intro
+^^^^^^^^^^^^^^^^
+
+The :cmd:ref:`select` command is used to modify and view the list of selected
+objects:
+
+.. literalinclude:: /code_examples/fifo/fifo.out
+   :language: doscon
+   :start-at: yosys> select
+   :end-before: yosys> show
+
+When we call :yoscrypt:`select -module addr_gen` we are changing the currently
+active selection from the whole design, to just the ``addr_gen`` module.  Notice
+how this changes the ``yosys`` at the start of each command to ``yosys
+[addr_gen]``?  This indicates that any commands we run at this point will *only*
+operate on the ``addr_gen`` module.  When we then call :yoscrypt:`select -list`
+we get a list of all objects in the ``addr_gen`` module, including the module
+itself, as well as all of the wires, inputs, outputs, processes, and cells.
+
+Next we perform another selection, :yoscrypt:`select t:*`.  The ``t:`` part
+signifies we are matching on the *cell type*, and the ``*`` means to match
+anything.  For this (very simple) selection, we are trying to find all of the
+cells, regardless of their type.  The active selection is now shown as
+``[addr_gen]*``, indicating some sub-selection of the ``addr_gen`` module.  This
+gives us the ``$add`` and ``$eq`` cells, which we want to highlight for the
+:ref:`addr_gen_hier` image.
+
+.. _select_new_cells:
+
+We can assign a name to a selection with :yoscrypt:`select -set`.  In our case
+we are using the name ``new_cells``, and telling it to use the current
+selection, indicated by the ``%`` symbol.  We can then use this named selection
+by referring to it as ``@new_cells``, which we will see later.  Then we clear
+the selection so that the following commands can operate on the full design.
+While we split that out for this document, we could have done the same thing in
+a single line by calling :yoscrypt:`select -set new_cells addr_gen/t:*`.  If we
+know we only have the one module in our design, we can even skip the `addr_gen/`
+part.  Looking further down :ref:`the fifo.ys code <fifo-ys>` we can see this
+with :yoscrypt:`select -set new_cells t:$mux t:*dff`.  We can also see in that
+command that selections don't have to be limited to a single statement.
+
+Many commands also support an optional ``[selection]`` argument which can be
+used to override the currently selected objects.  We could, for example, call
+:yoscrypt:`clean addr_gen` to have :cmd:ref:`clean` operate on *just* the
+``addr_gen`` module.
+
+Detailed documentation of the select framework can be found under
+:doc:`/using_yosys/more_scripting/selections` or in the command reference at
+:doc:`/cmd/select`.
+
+.. _show_intro:
+
+Displaying schematics
+^^^^^^^^^^^^^^^^^^^^^
+
+While the :cmd:ref:`select` command is very useful, sometimes nothing beats
+being able to see a design for yourself.  This is where :cmd:ref:`show` comes
+in.  Note that this document is just an introduction to the :cmd:ref:`show`
+command, only covering the basics.  For more information, including a guide on
+what the different symbols represent, see :ref:`interactive_show` and the
+:doc:`/using_yosys/more_scripting/interactive_investigation` page.
+
+.. figure:: /_images/code_examples/fifo/addr_gen_show.*
+   :class: width-helper invert-helper
+   :name: addr_gen_show
+
+   Calling :yoscrypt:`show addr_gen` after :cmd:ref:`hierarchy`
+
+.. note:: 
+
+   The :cmd:ref:`show` command requires a working installation of `GraphViz`_
+   and `xdot`_ for displaying the actual circuit diagrams.
+   
+.. _GraphViz: http://www.graphviz.org/
+.. _xdot: https://github.com/jrfonseca/xdot.py
+
+This is the first :yoscrypt:`show` command we called in :file:`fifo.ys`,
+:ref:`as we saw above <fifo-ys>`.  If we look at the log output for this image
+we see the following:
+
+.. literalinclude:: /code_examples/fifo/fifo.out
+   :language: doscon
+   :start-at: -prefix addr_gen_show
+   :end-before: yosys> show
+
+Calling :cmd:ref:`show` with :yoscrypt:`-format dot` tells it we want to output
+a :file:`.dot` file rather than opening it for display.  The :yoscrypt:`-prefix
+addr_gen_show` option indicates we want the file to be called
+:file:`addr_gen_show.{*}`. Remember, we do this in :file:`fifo.ys` because we
+need to store the image for displaying in the documentation you're reading.  But
+if you just want to display the images locally you can skip these two options.
+The ``-format`` option internally calls the ``dot`` command line program from
+GraphViz to convert to formats other than :file:`.dot`.  Check `GraphViz output
+docs`_ for more on available formats.
+
+.. _GraphViz output docs: https://graphviz.org/docs/outputs/
+
+.. note::
+
+   If you are using a POSIX based version of Yosys (such as for Mac or Linux),
+   xdot will be opened in the background and Yosys can continue to be used. If
+   it it still open, future calls to :yoscrypt:`show` will use the same xdot
+   instance.
+
+The ``addr_gen`` at the end tells it we only want the ``addr_gen`` module, just
+like when we called :yoscrypt:`select -module addr_gen` in :ref:`select_intro`.
+That last parameter doesn't have to be a module name, it can be any valid
+selection string.  Remember when we :ref:`assigned a name to a
+selection<select_new_cells>` and called it ``new_cells``?  We saw in the
+:yoscrypt:`select -list` output that it contained two cells, an ``$add`` and an
+``$eq``.  We can call :cmd:ref:`show` on that selection just as easily:
+
+.. figure:: /_images/code_examples/fifo/new_cells_show.*
+   :class: width-helper invert-helper
+   :name: new_cells_show
+
+   Calling :yoscrypt:`show -notitle @new_cells`
+
+We could have gotten the same output with :yoscrypt:`show -notitle t:$add t:$eq`
+if we didn't have the named selection. By adding the :yoscrypt:`-notitle` flag
+there we can also get rid of the ``addr_gen`` title that would have been
+automatically added.  The last two images were both added for this introduction.
+The next image is the first one we saw in :doc:`/getting_started/example_synth`:
+showing the full ``addr_gen`` module while also highlighting ``@new_cells`` and
+the two ``PROC`` blocks.  To achieve this highlight, we make use of the
+:yoscrypt:`-color` option:
+
+.. figure:: /_images/code_examples/fifo/addr_gen_hier.*
+   :class: width-helper invert-helper
+
+   Calling :yoscrypt:`show -color maroon3 @new_cells -color cornflowerblue p:* -notitle`
+
+As described in the the :cmd:ref:`help` output for :cmd:ref:`show` (or by
+clicking on the :cmd:ref:`show` link), colors are specified as :yoscrypt:`-color
+<color> <object>`.  Color names for the ``<color>`` portion can be found on the
+`GraphViz color docs`_.  Unlike the final :cmd:ref:`show` parameter which can
+have be any selection string, the ``<object>`` part must be a single selection
+expression or named selection.  That means while we can use ``@new_cells``, we
+couldn't use ``t:$eq t:$add``.  In general, if a command lists ``[selection]``
+as its final parameter it can be any selection string.  Any selections that are
+not the final parameter, such as those used in options, must be a single
+expression instead.
+
+.. _GraphViz color docs: https://graphviz.org/doc/info/colors
+
+For all of the options available to :cmd:ref:`show`, check the command reference
+at :doc:`/cmd/show`.
+
+.. seealso:: :ref:`interactive_show` on the
+   :doc:`/using_yosys/more_scripting/interactive_investigation` page.
diff --git a/yosys/docs/source/index.rst b/yosys/docs/source/index.rst
index 111aea873a4..582551f7486 100644
--- a/yosys/docs/source/index.rst
+++ b/yosys/docs/source/index.rst
@@ -1,73 +1,45 @@
-:Abstract:
-	Most of today's digital design is done in HDL code (mostly Verilog or 
-	VHDL) and with the help of HDL synthesis tools.
-
-	In special cases such as synthesis for coarse-grain cell libraries or
-	when testing new synthesis algorithms it might be necessary to write a
-	custom HDL synthesis tool or add new features to an existing one. In
-	these cases the availability of a Free and Open Source (FOSS) synthesis
-	tool that can be used as basis for custom tools would be helpful.
-
-	In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys)
-	was developed. This document covers the design and implementation of
-	this tool. At the moment the main focus of Yosys lies on the high-level
-	aspects of digital synthesis. The pre-existing FOSS logic-synthesis tool
-	ABC is used by Yosys to perform advanced gate-level optimizations.
-
-	An evaluation of Yosys based on real-world designs is included. It is
-	shown that Yosys can be used as-is to synthesize such designs. The
-	results produced by Yosys in this tests where successfully verified
-	using formal verification and are comparable in quality to the results
-	produced by a commercial synthesis tool.
-
-	This document was originally published as bachelor thesis at the Vienna
-	University of Technology :cite:p:`BACC`.
-
 ================================================================================
-Yosys manual
+Yosys Open SYnthesis Suite
 ================================================================================
 
-.. toctree::
-	:maxdepth: 2
-	:caption: Manual
-	:numbered:
+Yosys is an open source framework for RTL synthesis.  To learn more about Yosys,
+see :doc:`/introduction`.  For a quick guide on how to get started using Yosys,
+check out :doc:`/getting_started/index`.  For the complete list of commands
+available, go to :ref:`commandindex`.
 
-	CHAPTER_Intro
-	CHAPTER_Basics.rst
-	CHAPTER_Approach.rst
-	CHAPTER_Overview.rst
-	CHAPTER_CellLib.rst
-	CHAPTER_Prog.rst
+.. note::
 
-	CHAPTER_Verilog.rst
-	CHAPTER_Optimize.rst
-	CHAPTER_Techmap.rst
-	CHAPTER_Memorymap.rst
-	CHAPTER_Eval.rst
+   This documentation recently went through a major restructure.  If you're
+   looking for something from the previous version and can't find it here,
+   please `let us know`_.  Documentation from before the restructure can still
+   be found by switching to `version 0.36`_ or earlier.  Note that the previous
+   theme does not include a version switcher.
 
-.. raw:: latex
+.. _let us know: https://github.com/YosysHQ/yosys/issues/new/choose
+.. _version 0.36: https://yosyshq.readthedocs.io/projects/yosys/en/0.36/
 
-	\appendix
+.. todo:: look into command ref improvements
 
-.. toctree::
-	:maxdepth: 2
-	:includehidden:
-	:caption: Appendix
+   - Search bar with live drop down suggestions for matching on title /
+     autocompleting commands
+   - Scroll the left sidebar to the current location on page load
+   - Also the formatting/linking in pdf is broken
 
-	appendix/CHAPTER_Auxlibs.rst
-	appendix/CHAPTER_Auxprogs.rst
+.. todolist::
 
-	appendix/CHAPTER_TextRtlil.rst
-	appendix/APPNOTE_010_Verilog_to_BLIF.rst 
-	appendix/APPNOTE_011_Design_Investigation.rst 
-	appendix/APPNOTE_012_Verilog_to_BTOR.rst
-	appendix/CHAPTER_StateOfTheArt.rst
+.. only:: html
 
-	bib
+   Table of contents
+   -----------------
 
 .. toctree::
-	:maxdepth: 1
-	:includehidden:
+   :maxdepth: 3
+   :includehidden:
 
-	cmd_ref
+   introduction
+   getting_started/index
+   using_yosys/index
+   yosys_internals/index
+   test_suites
 
+   appendix
diff --git a/yosys/docs/source/introduction.rst b/yosys/docs/source/introduction.rst
new file mode 100644
index 00000000000..1d9cd008044
--- /dev/null
+++ b/yosys/docs/source/introduction.rst
@@ -0,0 +1,248 @@
+What is Yosys
+=============
+
+Yosys began as a BSc thesis project by Claire Wolf intended to support synthesis
+for a CGRA (coarse-grained reconfigurable architecture).  It then expanded into
+more general infrastructure for research on synthesis.
+
+Modern Yosys has full support for the synthesizable subset of Verilog-2005 and
+has been described as "the GCC of hardware synthesis."  Freely available and
+`open source`_, Yosys finds use across hobbyist and commercial applications as
+well as academic.
+
+.. _open source: https://github.com/YosysHQ/yosys
+
+.. note:: Yosys is released under the ISC License:
+
+   A permissive license lets people do anything with your code with proper
+   attribution and without warranty. The ISC license is functionally equivalent
+   to the BSD 2-Clause and MIT licenses, removing some language that is no
+   longer necessary.
+
+Together with the place and route tool `nextpnr`_, Yosys can be used to program
+some FPGAs with a fully end-to-end open source flow (Lattice iCE40 and ECP5). It
+also does the synthesis portion for the `OpenLane flow`_, targeting the SkyWater
+130nm open source PDK for fully open source ASIC design.  Yosys can also do
+formal verification with backends for solver formats like `SMT2`_.
+
+.. _nextpnr: https://github.com/YosysHQ/nextpnr
+.. _OpenLane flow: https://github.com/The-OpenROAD-Project/OpenLane
+.. _SMT2: https://smtlib.cs.uiowa.edu/
+
+Yosys, and the accompanying Open Source EDA ecosystem, is currently maintained
+by `Yosys Headquarters`_, with many of the core developers employed by `YosysHQ
+GmbH`_.  A commercial extension, `Tabby CAD Suite`_, includes the Verific
+frontend for industry-grade SystemVerilog and VHDL support, formal verification
+with SVA, and formal apps.
+
+.. _Yosys Headquarters: https://github.com/YosysHQ
+.. _YosysHQ GmbH: https://www.yosyshq.com/about
+.. _Tabby CAD Suite: https://www.yosyshq.com/tabby-cad-datasheet
+
+.. figure:: /_static/logo.png
+    :class: width-helper
+
+What you can do with Yosys
+--------------------------
+
+- Read and process (most of) modern Verilog-2005 code
+- Perform all kinds of operations on netlist (RTL, Logic, Gate)
+- Perform logic optimizations and gate mapping with ABC
+
+Typical applications for Yosys
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- Synthesis of final production designs
+- Pre-production synthesis (trial runs before investing in other tools)
+- Conversion of full-featured Verilog to simple Verilog
+- Conversion of Verilog to other formats (BLIF, BTOR, etc)
+- Demonstrating synthesis algorithms (e.g. for educational purposes)
+- Framework for experimenting with new algorithms
+- Framework for building custom flows (Not limited to synthesis but also formal
+  verification, reverse engineering, ...)
+
+Things you can't do
+~~~~~~~~~~~~~~~~~~~
+
+- Process high-level languages such as C/C++/SystemC
+- Create physical layouts (place&route)
+
+  - Check out `nextpnr`_ for that
+
+.. todo:: nextpnr for FPGAs, consider mentioning openlane, vpr, coriolis
+
+.. _nextpnr: https://github.com/YosysHQ/nextpnr
+
+The Yosys family
+----------------
+
+As mentioned above, `YosysHQ`_ maintains not just Yosys but an entire family of
+tools built around it.  In no particular order:
+
+.. _YosysHQ: https://github.com/YosysHQ
+
+SBY for formal verification
+   Yosys provides input parsing and conversion to the formats used by the solver
+   engines.  Yosys also provides a unified witness framework for providing cover
+   traces and counter examples for engines which don't natively support this.
+   `SBY source`_ | `SBY docs`_
+
+.. _SBY source: https://github.com/YosysHQ/sby
+.. _SBY docs: https://yosyshq.readthedocs.io/projects/sby
+
+EQY for equivalence checking
+   In addition to input parsing and preparation, Yosys provides  the plugin
+   support enabling EQY to operate on designs directly. `EQY source`_ | `EQY
+   docs`_
+
+.. _EQY source: https://github.com/YosysHQ/eqy
+.. _EQY docs: https://yosyshq.readthedocs.io/projects/eqy
+
+MCY for mutation coverage
+   Yosys is used to read the source design, generate a list of possible
+   mutations to maximise design coverage, and then perform selected mutations.
+   `MCY source`_ | `MCY docs`_
+
+.. _MCY source: https://github.com/YosysHQ/mcy
+.. _MCY docs: https://yosyshq.readthedocs.io/projects/mcy
+
+SCY for deep formal traces
+   Since SCY generates and runs SBY, Yosys provides the same utility for SCY as
+   it does for SBY.  Yosys additionally provides the trace concatenation needed
+   for outputting the deep traces. `SCY source`_
+
+.. _SCY source: https://github.com/YosysHQ/scy
+
+The original thesis abstract
+----------------------------
+
+The first version of the Yosys documentation was published as a bachelor thesis
+at the Vienna University of Technology :cite:p:`BACC`.
+
+:Abstract:
+	Most of today's digital design is done in HDL code (mostly Verilog or 
+	VHDL) and with the help of HDL synthesis tools.
+
+	In special cases such as synthesis for coarse-grain cell libraries or
+	when testing new synthesis algorithms it might be necessary to write a
+	custom HDL synthesis tool or add new features to an existing one. In
+	these cases the availability of a Free and Open Source (FOSS) synthesis
+	tool that can be used as basis for custom tools would be helpful.
+
+	In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys)
+	was developed. This document covers the design and implementation of
+	this tool. At the moment the main focus of Yosys lies on the high-level
+	aspects of digital synthesis. The pre-existing FOSS logic-synthesis tool
+	ABC is used by Yosys to perform advanced gate-level optimizations.
+
+	An evaluation of Yosys based on real-world designs is included. It is
+	shown that Yosys can be used as-is to synthesize such designs. The
+	results produced by Yosys in this tests where successfully verified
+	using formal verification and are comparable in quality to the results
+	produced by a commercial synthesis tool.
+
+Yosys is a Verilog HDL synthesis tool. This means that it takes a behavioural
+design description as input and generates an RTL, logical gate or physical gate
+level description of the design as output. Yosys' main strengths are behavioural
+and RTL synthesis. A wide range of commands (synthesis passes) exist within
+Yosys that can be used to perform a wide range of synthesis tasks within the
+domain of behavioural, rtl and logic synthesis. Yosys is designed to be
+extensible and therefore is a good basis for implementing custom synthesis tools
+for specialised tasks.
+
+.. figure:: /_images/primer/levels_of_abstraction.*
+    :class: width-helper invert-helper
+    :name: fig:Levels_of_abstraction
+
+    Where Yosys exists in the layers of abstraction
+
+Benefits of open source HDL synthesis
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- Cost (also applies to ``free as in free beer`` solutions): 
+  
+  Today the cost for a mask set in 180nm technology is far less than
+  the cost for the design tools needed to design the mask layouts. Open Source
+  ASIC flows are an important enabler for ASIC-level Open Source Hardware.
+
+- Availability and Reproducibility: 
+  
+  If you are a researcher who is publishing, you want to use tools that everyone
+  else can also use. Even if most universities have access to all major
+  commercial tools, you usually do not have easy access to the version that was
+  used in a research project a couple of years ago. With Open Source tools you
+  can even release the source code of the tool you have used alongside your data.
+
+- Framework: 
+  
+  Yosys is not only a tool. It is a framework that can be used as basis for other
+  developments, so researchers and hackers alike do not need to re-invent the
+  basic functionality. Extensibility was one of Yosys' design goals.
+
+- All-in-one: 
+  
+  Because of the framework characteristics of Yosys, an increasing number of features
+  become available in one tool. Yosys not only can be used for circuit synthesis but
+  also for formal equivalence checking, SAT solving, and for circuit analysis, to
+  name just a few other application domains. With proprietary software one needs to
+  learn a new tool for each of these applications.
+
+- Educational Tool: 
+  
+  Proprietary synthesis tools are at times very secretive about their inner
+  workings. They often are ``black boxes``. Yosys is very open about its
+  internals and it is easy to observe the different steps of synthesis.
+
+History of Yosys
+~~~~~~~~~~~~~~~~
+
+.. todo:: Consider a less academic version of the History of Yosys
+
+A Hardware Description Language (HDL) is a computer language used to describe
+circuits. A HDL synthesis tool is a computer program that takes a formal
+description of a circuit written in an HDL as input and generates a netlist that
+implements the given circuit as output.
+
+Currently the most widely used and supported HDLs for digital circuits are
+Verilog :cite:p:`Verilog2005,VerilogSynth` and :abbr:`VHDL (VHSIC HDL, where
+VHSIC is an acronym for Very-High-Speed Integrated Circuits)`
+:cite:p:`VHDL,VHDLSynth`. Both HDLs are used for test and verification purposes
+as well as logic synthesis, resulting in a set of synthesizable and a set of
+non-synthesizable language features. In this document we only look at the
+synthesizable subset of the language features.
+
+In recent work on heterogeneous coarse-grain reconfigurable logic
+:cite:p:`intersynth` the need for a custom application-specific HDL synthesis
+tool emerged. It was soon realised that a synthesis tool that understood Verilog
+or VHDL would be preferred over a synthesis tool for a custom HDL. Given an
+existing Verilog or VHDL front end, the work for writing the necessary
+additional features and integrating them in an existing tool can be estimated to
+be about the same as writing a new tool with support for a minimalistic custom
+HDL.
+
+The proposed custom HDL synthesis tool should be licensed under a Free and Open
+Source Software (FOSS) licence. So an existing FOSS Verilog or VHDL synthesis
+tool would have been needed as basis to build upon. The main advantages of
+choosing Verilog or VHDL is the ability to synthesize existing HDL code and to
+mitigate the requirement for circuit-designers to learn a new language. In order
+to take full advantage of any existing FOSS Verilog or VHDL tool, such a tool
+would have to provide a feature-complete implementation of the synthesizable HDL
+subset.
+
+Basic RTL synthesis is a well understood field :cite:p:`LogicSynthesis`. Lexing,
+parsing and processing of computer languages :cite:p:`Dragonbook` is a
+thoroughly researched field. All the information required to write such tools
+has been openly available for a long time, and it is therefore likely that a
+FOSS HDL synthesis tool with a feature-complete Verilog or VHDL front end must
+exist which can be used as a basis for a custom RTL synthesis tool.
+
+Due to the author's preference for Verilog over VHDL it was decided early on to
+go for Verilog instead of VHDL [#]_. So the existing FOSS Verilog synthesis
+tools were evaluated. The results of this evaluation are utterly devastating.
+Therefore a completely new Verilog synthesis tool was implemented and is
+recommended as basis for custom synthesis tools. This is the tool that is
+discussed in this document.
+
+.. [#]
+   A quick investigation into FOSS VHDL tools yielded similar grim results for
+   FOSS VHDL synthesis tools.
diff --git a/yosys/docs/source/requirements.txt b/yosys/docs/source/requirements.txt
index d357a83b7cc..74c8dd090cb 100644
--- a/yosys/docs/source/requirements.txt
+++ b/yosys/docs/source/requirements.txt
@@ -1,2 +1,2 @@
-sphinx-press-theme
+furo
 sphinxcontrib-bibtex
diff --git a/yosys/docs/source/test_suites.rst b/yosys/docs/source/test_suites.rst
new file mode 100644
index 00000000000..7a6b7497774
--- /dev/null
+++ b/yosys/docs/source/test_suites.rst
@@ -0,0 +1,25 @@
+Testing Yosys
+=============
+
+.. todo:: more about the included test suite
+
+Automatic testing
+-----------------
+
+.. only:: html
+
+   The `Yosys Git repo`_ has automatic testing of builds and running of the
+   included test suite on the following platforms:
+
+   - Ubuntu |test-linux|
+   - macOS |test-macos|
+
+.. _Yosys Git repo: https://github.com/YosysHQ/yosys
+
+.. |test-linux| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-linux.yml/badge.svg?branch=main
+.. |test-macos| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-macos.yml/badge.svg?branch=main
+
+For up to date information, including OS versions, refer to `the git actions
+page`_.
+
+.. _the git actions page: https://github.com/YosysHQ/yosys/actions
diff --git a/yosys/docs/source/using_yosys/index.rst b/yosys/docs/source/using_yosys/index.rst
new file mode 100644
index 00000000000..55bd5c29151
--- /dev/null
+++ b/yosys/docs/source/using_yosys/index.rst
@@ -0,0 +1,17 @@
+Using Yosys (advanced)
+======================
+
+While much of Yosys is focused around synthesis, there are also a number of
+other useful things that can be accomplished with Yosys scripts or in an
+interactive shell.  As such this section is broken into two parts:
+:doc:`/using_yosys/synthesis/index` expands on the
+:doc:`/getting_started/example_synth` and goes into further detail on the major
+commands used in synthesis; :doc:`/using_yosys/more_scripting/index` covers the
+ways Yosys can interact with designs for a deeper investigation.
+
+.. toctree::
+   :maxdepth: 2
+   :hidden:
+
+   synthesis/index
+   more_scripting/index
diff --git a/yosys/docs/source/using_yosys/more_scripting/index.rst b/yosys/docs/source/using_yosys/more_scripting/index.rst
new file mode 100644
index 00000000000..490a5a7ad8b
--- /dev/null
+++ b/yosys/docs/source/using_yosys/more_scripting/index.rst
@@ -0,0 +1,14 @@
+More scripting
+--------------
+
+.. todo:: brief overview for the more scripting index
+
+.. toctree::
+   :maxdepth: 3
+
+   load_design
+   selections
+   interactive_investigation
+   model_checking
+
+.. troubleshooting
diff --git a/yosys/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/yosys/docs/source/using_yosys/more_scripting/interactive_investigation.rst
new file mode 100644
index 00000000000..db34f041bb9
--- /dev/null
+++ b/yosys/docs/source/using_yosys/more_scripting/interactive_investigation.rst
@@ -0,0 +1,813 @@
+Interactive design investigation
+--------------------------------
+
+.. todo:: interactive design opening text
+
+.. role:: yoscrypt(code)
+   :language: yoscrypt
+
+.. _interactive_show:
+
+A look at the show command
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. TODO:: merge into :doc:`/getting_started/scripting_intro` show section
+
+This section explores the :cmd:ref:`show` command and explains the symbols used
+in the circuit diagrams generated by it. The code used is included in the Yosys
+code base under |code_examples/show|_.
+
+.. |code_examples/show| replace:: :file:`docs/source/code_examples/show`
+.. _code_examples/show: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/show
+
+A simple circuit
+^^^^^^^^^^^^^^^^
+
+:ref:`example_v` below provides the Verilog code for a simple circuit which we
+will use to demonstrate the usage of :cmd:ref:`show` in a simple setting.
+
+.. literalinclude:: /code_examples/show/example.v
+   :language: Verilog
+   :caption: :file:`example.v`
+   :name: example_v
+
+The Yosys synthesis script we will be running is included as
+:numref:`example_ys`. Note that :cmd:ref:`show` is called with the ``-pause``
+option, that halts execution of the Yosys script until the user presses the
+Enter key. Using :yoscrypt:`show -pause` also allows the user to enter an
+interactive shell to further investigate the circuit before continuing
+synthesis.
+
+.. literalinclude:: /code_examples/show/example_show.ys
+   :language: yoscrypt
+   :caption: :file:`example_show.ys`
+   :name: example_ys
+
+This script, when executed, will show the design after each of the three
+synthesis commands. We will now look at each of these diagrams and explain what
+is shown.
+
+.. note::
+
+   The images uses in this document are generated from the :file:`example.ys`
+   file, rather than :file:`example_show.ys`.  :file:`example.ys` outputs the
+   schematics as :file:`.dot` files rather than displaying them directly.  You
+   can view these images yourself by running :file:`yosys example.ys` and then
+   ``xdot example_first.dot`` etc.
+
+.. figure:: /_images/code_examples/show/example_first.*
+   :class: width-helper invert-helper
+   
+   Output of the first :cmd:ref:`show` command in :numref:`example_ys`
+
+The first output shows the design directly after being read by the Verilog
+front-end. Input and output ports are displayed as octagonal shapes. Cells are
+displayed as rectangles with inputs on the left and outputs on the right side.
+The cell labels are two lines long: The first line contains a unique identifier
+for the cell and the second line contains the cell type. Internal cell types are
+prefixed with a dollar sign. For more details on the internal cell library, see
+:doc:`/yosys_internals/formats/cell_library`.
+
+Constants are shown as ellipses with the constant value as label. The syntax
+``<bit_width>'<bits>`` is used for constants that are not 32-bit wide and/or
+contain bits that are not 0 or 1 (i.e. ``x`` or ``z``). Ordinary 32-bit
+constants are written using decimal numbers.
+
+Single-bit signals are shown as thin arrows pointing from the driver to the
+load. Signals that are multiple bits wide are shown as think arrows.
+
+Finally *processes* are shown in boxes with round corners. Processes are Yosys'
+internal representation of the decision-trees and synchronization events
+modelled in a Verilog ``always``-block. The label reads ``PROC`` followed by a
+unique identifier in the first line and contains the source code location of the
+original ``always``-block in the second line. Note how the multiplexer from the
+``?:``-expression is represented as a ``$mux`` cell but the multiplexer from the
+``if``-statement is yet still hidden within the process.
+
+The :cmd:ref:`proc` command transforms the process from the first diagram into a
+multiplexer and a d-type flip-flop, which brings us to the second diagram:
+
+.. figure:: /_images/code_examples/show/example_second.*
+   :class: width-helper invert-helper
+   
+   Output of the second :cmd:ref:`show` command in :numref:`example_ys`
+
+The Rhombus shape to the right is a dangling wire. (Wire nodes are only shown if
+they are dangling or have "public" names, for example names assigned from the
+Verilog input.) Also note that the design now contains two instances of a
+``BUF``-node. These are artefacts left behind by the :cmd:ref:`proc` command. It
+is quite usual to see such artefacts after calling commands that perform changes
+in the design, as most commands only care about doing the transformation in the
+least complicated way, not about cleaning up after them. The next call to
+:cmd:ref:`clean` (or :cmd:ref:`opt`, which includes :cmd:ref:`clean` as one of
+its operations) will clean up these artefacts. This operation is so common in
+Yosys scripts that it can simply be abbreviated with the ``;;`` token, which
+doubles as separator for commands. Unless one wants to specifically analyze this
+artefacts left behind some operations, it is therefore recommended to always
+call :cmd:ref:`clean` before calling :cmd:ref:`show`.
+
+In this script we directly call :cmd:ref:`opt` as the next step, which finally
+leads us to the third diagram: 
+
+.. figure:: /_images/code_examples/show/example_third.*
+   :class: width-helper invert-helper
+   :name: example_out
+   
+   Output of the third :cmd:ref:`show` command in :ref:`example_ys`
+   
+Here we see that the :cmd:ref:`proc` command not only has removed the artifacts
+left behind by :cmd:ref:`proc`, but also determined correctly that it can remove
+the first ``$mux`` cell without changing the behavior of the circuit.
+
+Break-out boxes for signal vectors
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The code listing below shows a simple circuit which uses a lot of spliced signal
+accesses.
+
+.. literalinclude:: /code_examples/show/splice.v
+   :caption: :file:`splice.v`
+   :name: splice_src
+
+Notice how the output for this circuit from the :cmd:ref:`show` command
+(:numref:`splice_dia`) appears quite complex. This is an unfortunate side effect
+of the way Yosys handles signal vectors (aka. multi-bit wires or buses) as
+native objects. While this provides great advantages when analyzing circuits
+that operate on wide integers, it also introduces some additional complexity
+when the individual bits of of a signal vector are accessed.
+
+.. figure:: /_images/code_examples/show/splice.*
+   :class: width-helper invert-helper
+   :name: splice_dia
+
+   Output of ``yosys -p 'prep -top splice_demo; show' splice.v``
+
+The key elements in understanding this circuit diagram are of course the boxes
+with round corners and rows labeled ``<MSB_LEFT>:<LSB_LEFT> -
+<MSB_RIGHT>:<LSB_RIGHT>``. Each of these boxes have one signal per row on one
+side and a common signal for all rows on the other side. The ``<MSB>:<LSB>``
+tuples specify which bits of the signals are broken out and connected. So the
+top row of the box connecting the signals ``a`` and ``x`` indicates that the bit
+0 (i.e. the range 0:0) from signal ``a`` is connected to bit 1 (i.e. the range
+1:1) of signal ``x``.
+
+Lines connecting such boxes together and lines connecting such boxes to cell
+ports have a slightly different look to emphasise that they are not actual
+signal wires but a necessity of the graphical representation. This distinction
+seems like a technicality, until one wants to debug a problem related to the way
+Yosys internally represents signal vectors, for example when writing custom
+Yosys commands.
+
+Gate level netlists
+^^^^^^^^^^^^^^^^^^^
+
+:numref:`first_pitfall` shows two common pitfalls when working with designs
+mapped to a cell library:
+
+.. figure:: /_images/code_examples/show/cmos_00.*
+   :class: width-helper invert-helper
+   :name: first_pitfall
+
+   A half-adder built from simple CMOS gates, demonstrating common pitfalls when 
+   using :cmd:ref:`show`
+
+.. literalinclude:: /code_examples/show/cmos.ys
+   :language: yoscrypt
+   :start-after: pitfall
+   :end-at: cmos_00
+   :name: pitfall_code
+   :caption: Generating :numref:`first_pitfall`
+   
+First, Yosys did not have access to the cell library when this diagram was
+generated, resulting in all cell ports defaulting to being inputs. This is why
+all ports are drawn on the left side the cells are awkwardly arranged in a large
+column. Secondly the two-bit vector ``y`` requires breakout-boxes for its
+individual bits, resulting in an unnecessary complex diagram.
+
+.. figure:: /_images/code_examples/show/cmos_01.*
+   :class: width-helper invert-helper
+   :name: second_pitfall
+
+   Effects of :cmd:ref:`splitnets` command and of providing a cell library on 
+   design in :numref:`first_pitfall`
+
+.. literalinclude:: /code_examples/show/cmos.ys
+   :language: yoscrypt
+   :start-after: fixed
+   :end-at: cmos_01
+   :name: pitfall_avoided
+   :caption: Generating :numref:`second_pitfall`
+
+For :numref:`second_pitfall`, Yosys has been given a description of the cell
+library as Verilog file containing blackbox modules. There are two ways to load
+cell descriptions into Yosys: First the Verilog file for the cell library can be
+passed directly to the :cmd:ref:`show` command using the ``-lib <filename>``
+option. Secondly it is possible to load cell libraries into the design with the
+:yoscrypt:`read_verilog -lib <filename>` command. The second method has the
+great advantage that the library only needs to be loaded once and can then be
+used in all subsequent calls to the :cmd:ref:`show` command.
+
+In addition to that, :numref:`second_pitfall` was generated after
+:yoscrypt:`splitnet -ports` was run on the design. This command splits all
+signal vectors into individual signal bits, which is often desirable when
+looking at gate-level circuits. The ``-ports`` option is required to also split
+module ports. Per default the command only operates on interior signals.
+
+Miscellaneous notes
+^^^^^^^^^^^^^^^^^^^
+
+Per default the :cmd:ref:`show` command outputs a temporary dot file and
+launches ``xdot`` to display it. The options ``-format``, ``-viewer`` and
+``-prefix`` can be used to change format, viewer and filename prefix. Note that
+the ``pdf`` and ``ps`` format are the only formats that support plotting
+multiple modules in one run.  The ``dot`` format can be used to output multiple
+modules, however ``xdot`` will raise an error when trying to read them.
+
+In densely connected circuits it is sometimes hard to keep track of the
+individual signal wires. For these cases it can be useful to call
+:cmd:ref:`show` with the ``-colors <integer>`` argument, which randomly assigns
+colors to the nets. The integer (> 0) is used as seed value for the random color
+assignments. Sometimes it is necessary it try some values to find an assignment
+of colors that looks good.
+
+The command :yoscrypt:`help show` prints a complete listing of all options
+supported by the :cmd:ref:`show` command.
+
+Navigating the design
+~~~~~~~~~~~~~~~~~~~~~
+
+Plotting circuit diagrams for entire modules in the design brings us only helps
+in simple cases. For complex modules the generated circuit diagrams are just
+stupidly big and are no help at all. In such cases one first has to select the
+relevant portions of the circuit.
+
+In addition to *what* to display one also needs to carefully decide *when* to
+display it, with respect to the synthesis flow. In general it is a good idea to
+troubleshoot a circuit in the earliest state in which a problem can be
+reproduced. So if, for example, the internal state before calling the
+:cmd:ref:`techmap` command already fails to verify, it is better to troubleshoot
+the coarse-grain version of the circuit before :cmd:ref:`techmap` than the
+gate-level circuit after :cmd:ref:`techmap`.
+
+.. Note:: 
+
+   It is generally recommended to verify the internal state of a design by
+   writing it to a Verilog file using :yoscrypt:`write_verilog -noexpr` and
+   using the simulation models from :file:`simlib.v` and :file:`simcells.v` from
+   the Yosys data directory (as printed by ``yosys-config --datdir``).
+
+Interactive navigation
+^^^^^^^^^^^^^^^^^^^^^^
+
+Once the right state within the synthesis flow for debugging the circuit has
+been identified, it is recommended to simply add the :cmd:ref:`shell` command to
+the matching place in the synthesis script. This command will stop the synthesis
+at the specified moment and go to shell mode, where the user can interactively
+enter commands.
+
+For most cases, the shell will start with the whole design selected (i.e. when
+the synthesis script does not already narrow the selection). The command
+:cmd:ref:`ls` can now be used to create a list of all modules. The command
+:cmd:ref:`cd` can be used to switch to one of the modules (type ``cd ..`` to
+switch back). Now the :cmd:ref:`ls` command lists the objects within that
+module. This is demonstrated below using :file:`example.v` from `A simple
+circuit`_:
+
+.. literalinclude:: /code_examples/show/example.out
+   :language: doscon
+   :start-at: yosys> ls
+   :end-before: yosys [example]> dump
+   :caption: Output of :cmd:ref:`ls` and :cmd:ref:`cd` after running :file:`yosys example.v`
+   :name: lscd
+
+When a module is selected using the :cmd:ref:`cd` command, all commands (with a
+few exceptions, such as the ``read_`` and ``write_`` commands) operate only on
+the selected module. This can also be useful for synthesis scripts where
+different synthesis strategies should be applied to different modules in the
+design.
+
+We can see that the cell names from :numref:`example_out` are just abbreviations
+of the actual cell names, namely the part after the last dollar-sign. Most
+auto-generated names (the ones starting with a dollar sign) are rather long and
+contains some additional information on the origin of the named object. But in
+most cases those names can simply be abbreviated using the last part.
+
+Usually all interactive work is done with one module selected using the
+:cmd:ref:`cd` command. But it is also possible to work from the design-context
+(``cd ..``). In this case all object names must be prefixed with
+``<module_name>/``. For example ``a*/b*`` would refer to all objects whose names
+start with ``b`` from all modules whose names start with ``a``.
+
+The :cmd:ref:`dump` command can be used to print all information about an
+object. For example, calling :yoscrypt:`dump $2` after the :yoscrypt:`cd
+example` above:
+
+.. literalinclude:: /code_examples/show/example.out
+   :language: RTLIL
+   :start-after: yosys [example]> dump
+   :end-before: yosys [example]> cd
+   :dedent:
+   :caption: Output of :yoscrypt:`dump $2` after :numref:`lscd`
+   :name: dump2
+
+This can for example be useful to determine the names of nets connected to
+cells, as the net-names are usually suppressed in the circuit diagram if they
+are auto-generated.  Note that the output is in the RTLIL representation,
+described in :doc:`/yosys_internals/formats/rtlil_rep`.
+
+Interactive Design Investigation
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Yosys can also be used to investigate designs (or netlists created from other
+tools).
+
+- The selection mechanism, especially patterns such as ``%ci`` and ``%co``, can
+  be used to figure out how parts of the design are connected.
+- Commands such as :cmd:ref:`submod`, :cmd:ref:`expose`, and :cmd:ref:`splice`
+  can be used to transform the design into an equivalent design that is easier
+  to analyse.
+- Commands such as :cmd:ref:`eval` and :cmd:ref:`sat` can be used to investigate
+  the behavior of the circuit.
+- :doc:`/cmd/show`.
+- :doc:`/cmd/dump`.
+- :doc:`/cmd/add` and :doc:`/cmd/delete` can be used to modify and reorganize a
+  design dynamically.
+  
+The code used is included in the Yosys code base under
+|code_examples/scrambler|_.
+
+.. |code_examples/scrambler| replace:: :file:`docs/source/code_examples/scrambler`
+.. _code_examples/scrambler: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/scrambler
+
+Changing design hierarchy
+^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Commands such as :cmd:ref:`flatten` and :cmd:ref:`submod` can be used to change
+the design hierarchy, i.e. flatten the hierarchy or moving parts of a module to
+a submodule. This has applications in synthesis scripts as well as in reverse
+engineering and analysis.  An example using :cmd:ref:`submod` is shown below for
+reorganizing a module in Yosys and checking the resulting circuit.
+
+.. literalinclude:: /code_examples/scrambler/scrambler.v
+   :language: verilog
+   :caption: :file:`scrambler.v`
+
+.. literalinclude:: /code_examples/scrambler/scrambler.ys
+   :language: yoscrypt
+   :caption: :file:`scrambler.ys`
+   :end-before: cd ..
+
+.. figure:: /_images/code_examples/scrambler/scrambler_p01.*
+    :class: width-helper invert-helper
+
+.. figure:: /_images/code_examples/scrambler/scrambler_p02.*
+    :class: width-helper invert-helper
+
+Analyzing the resulting circuit with :doc:`/cmd/eval`:
+
+.. todo:: replace inline code
+
+.. code:: text
+
+    > cd xorshift32
+    > rename n2 in
+    > rename n1 out
+
+    > eval -set in 1 -show out
+    Eval result: \out = 270369.
+
+    > eval -set in 270369 -show out
+    Eval result: \out = 67634689.
+
+    > sat -set out 632435482
+    Signal Name                 Dec        Hex                                   Bin
+    -------------------- ---------- ---------- -------------------------------------
+    \in                   745495504   2c6f5bd0      00101100011011110101101111010000
+    \out                  632435482   25b2331a      00100101101100100011001100011010
+
+Behavioral changes
+^^^^^^^^^^^^^^^^^^
+
+Commands such as :cmd:ref:`techmap` can be used to make behavioral changes to
+the design, for example changing asynchronous resets to synchronous resets. This
+has applications in design space exploration (evaluation of various
+architectures for one circuit).
+
+The following techmap map file replaces all positive-edge async reset flip-flops
+with positive-edge sync reset flip-flops. The code is taken from the example
+Yosys script for ASIC synthesis of the Amber ARMv2 CPU.
+
+.. todo:: replace inline code
+
+.. code:: verilog
+
+    (* techmap_celltype = "$adff" *)
+    module adff2dff (CLK, ARST, D, Q);
+
+        parameter WIDTH = 1;
+        parameter CLK_POLARITY = 1;
+        parameter ARST_POLARITY = 1;
+        parameter ARST_VALUE = 0;
+
+        input CLK, ARST;
+        input [WIDTH-1:0] D;
+        output reg [WIDTH-1:0] Q;
+
+        wire [1023:0] _TECHMAP_DO_ = "proc";
+
+        wire _TECHMAP_FAIL_ = !CLK_POLARITY || !ARST_POLARITY;
+
+        always @(posedge CLK)
+            if (ARST)
+                Q <= ARST_VALUE;
+            else
+                Q <= D;
+
+    endmodule
+
+For more on the :cmd:ref:`techmap` command, see the page on
+:doc:`/yosys_internals/techmap`.
+
+Advanced investigation techniques
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+When working with very large modules, it is often not enough to just select the
+interesting part of the module. Instead it can be useful to extract the
+interesting part of the circuit into a separate module. This can for example be
+useful if one wants to run a series of synthesis commands on the critical part
+of the module and wants to carefully read all the debug output created by the
+commands in order to spot a problem. This kind of troubleshooting is much easier
+if the circuit under investigation is encapsulated in a separate module.
+
+Recall the ``memdemo`` design from :ref:`advanced_logic_cones`:
+
+.. figure:: /_images/code_examples/selections/memdemo_00.*
+   :class: width-helper invert-helper
+   
+   ``memdemo``
+
+Because this produces a rather large circuit, it can be useful to split it into
+smaller parts for viewing and working with.  :numref:`submod` does exactly that,
+utilising the :cmd:ref:`submod` command to split the circuit into three
+sections: ``outstage``, ``selstage``, and ``scramble``.
+
+.. literalinclude:: /code_examples/selections/submod.ys
+   :language: yoscrypt
+   :caption: Using :cmd:ref:`submod` to break up the circuit from :file:`memdemo.v`
+   :start-after: cd memdemo
+   :end-before: cd ..
+   :name: submod
+
+The ``-name`` option is used to specify the name of the new module and also the
+name of the new cell in the current module. The resulting circuits are shown
+below.
+
+.. figure:: /_images/code_examples/selections/submod_02.*
+   :class: width-helper invert-helper
+   
+   ``outstage``
+
+.. figure:: /_images/code_examples/selections/submod_03.*
+   :class: width-helper invert-helper
+   :name: selstage
+   
+   ``selstage``
+
+.. figure:: /_images/code_examples/selections/submod_01.*
+   :class: width-helper invert-helper
+   
+   ``scramble``
+
+Evaluation of combinatorial circuits
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The :cmd:ref:`eval` command can be used to evaluate combinatorial circuits. As
+an example, we will use the ``selstage`` subnet of ``memdemo`` which we found
+above and is shown in :numref:`selstage`.
+
+.. todo:: replace inline code
+
+::
+
+      yosys [selstage]> eval -set s2,s1 4'b1001 -set d 4'hc -show n2 -show n1
+
+      1. Executing EVAL pass (evaluate the circuit given an input).
+      Full command line: eval -set s2,s1 4'b1001 -set d 4'hc -show n2 -show n1
+      Eval result: \n2 = 2'10.
+      Eval result: \n1 = 2'10.
+
+So the ``-set`` option is used to set input values and the ``-show`` option is
+used to specify the nets to evaluate. If no ``-show`` option is specified, all
+selected output ports are used per default.
+
+If a necessary input value is not given, an error is produced. The option
+``-set-undef`` can be used to instead set all unspecified input nets to undef
+(``x``).
+
+The ``-table`` option can be used to create a truth table. For example:
+
+::
+
+      yosys [selstage]> eval -set-undef -set d[3:1] 0 -table s1,d[0]
+
+      10. Executing EVAL pass (evaluate the circuit given an input).
+      Full command line: eval -set-undef -set d[3:1] 0 -table s1,d[0]
+
+        \s1 \d [0] |  \n1  \n2
+       ---- ------ | ---- ----
+       2'00    1'0 | 2'00 2'00
+       2'00    1'1 | 2'xx 2'00
+       2'01    1'0 | 2'00 2'00
+       2'01    1'1 | 2'xx 2'01
+       2'10    1'0 | 2'00 2'00
+       2'10    1'1 | 2'xx 2'10
+       2'11    1'0 | 2'00 2'00
+       2'11    1'1 | 2'xx 2'11
+
+      Assumed undef (x) value for the following signals: \s2
+
+Note that the :cmd:ref:`eval` command (as well as the :cmd:ref:`sat` command
+discussed in the next sections) does only operate on flattened modules. It can
+not analyze signals that are passed through design hierarchy levels. So the
+:cmd:ref:`flatten` command must be used on modules that instantiate other
+modules before these commands can be applied.
+
+Solving combinatorial SAT problems
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Often the opposite of the :cmd:ref:`eval` command is needed, i.e. the circuits
+output is given and we want to find the matching input signals. For small
+circuits with only a few input bits this can be accomplished by trying all
+possible input combinations, as it is done by the ``eval -table`` command. For
+larger circuits however, Yosys provides the :cmd:ref:`sat` command that uses a
+`SAT`_ solver, `MiniSAT`_, to solve this kind of problems.
+
+.. _SAT: http://en.wikipedia.org/wiki/Circuit_satisfiability
+
+.. _MiniSAT: http://minisat.se/
+
+.. note:: 
+    
+    While it is possible to perform model checking directly in Yosys, it 
+    is highly recommended to use SBY or EQY for formal hardware verification.
+
+The :cmd:ref:`sat` command works very similar to the :cmd:ref:`eval` command.
+The main difference is that it is now also possible to set output values and
+find the corresponding input values. For Example:
+
+.. todo:: replace inline code
+
+::
+
+      yosys [selstage]> sat -show s1,s2,d -set s1 s2 -set n2,n1 4'b1001
+
+      11. Executing SAT pass (solving SAT problems in the circuit).
+      Full command line: sat -show s1,s2,d -set s1 s2 -set n2,n1 4'b1001
+
+      Setting up SAT problem:
+      Import set-constraint: \s1 = \s2
+      Import set-constraint: { \n2 \n1 } = 4'1001
+      Final constraint equation: { \n2 \n1 \s1 } = { 4'1001 \s2 }
+      Imported 3 cells to SAT database.
+      Import show expression: { \s1 \s2 \d }
+
+      Solving problem with 81 variables and 207 clauses..
+      SAT solving finished - model found:
+
+        Signal Name                 Dec        Hex             Bin
+        -------------------- ---------- ---------- ---------------
+        \d                            9          9            1001
+        \s1                           0          0              00
+        \s2                           0          0              00
+
+Note that the :cmd:ref:`sat` command supports signal names in both arguments to
+the ``-set`` option. In the above example we used ``-set s1 s2`` to constraint
+``s1`` and ``s2`` to be equal. When more complex constraints are needed, a
+wrapper circuit must be constructed that checks the constraints and signals if
+the constraint was met using an extra output port, which then can be forced to a
+value using the ``-set`` option. (Such a circuit that contains the circuit under
+test plus additional constraint checking circuitry is called a ``miter``
+circuit.)
+
+.. literalinclude:: /code_examples/primetest.v
+   :language: verilog
+   :caption: :file:`primetest.v`, a simple miter circuit for testing if a number is
+             prime. But it has a problem.
+   :name: primetest
+
+:numref:`primetest` shows a miter circuit that is supposed to be used as a prime
+number test. If ``ok`` is 1 for all input values ``a`` and ``b`` for a given
+``p``, then ``p`` is prime, or at least that is the idea.
+
+.. todo:: replace inline code
+
+.. code-block::
+   :caption: Experiments with the miter circuit from :file:`primetest.v`.
+   :name: prime_shell
+
+   yosys [primetest]> sat -prove ok 1 -set p 31
+
+   1. Executing SAT pass (solving SAT problems in the circuit).
+   Full command line: sat -prove ok 1 -set p 31
+
+   Setting up SAT problem:
+   Import set-constraint: \p = 16'0000000000011111
+   Final constraint equation: \p = 16'0000000000011111
+   Imported 6 cells to SAT database.
+   Import proof-constraint: \ok = 1'1
+   Final proof equation: \ok = 1'1
+
+   Solving problem with 2790 variables and 8241 clauses..
+   SAT proof finished - model found: FAIL!
+
+      ______                   ___       ___       _ _            _ _
+     (_____ \                 / __)     / __)     (_) |          | | |
+      _____) )___ ___   ___ _| |__    _| |__ _____ _| | _____  __| | |
+     |  ____/ ___) _ \ / _ (_   __)  (_   __|____ | | || ___ |/ _  |_|
+     | |   | |  | |_| | |_| || |       | |  / ___ | | || ____( (_| |_
+     |_|   |_|   \___/ \___/ |_|       |_|  \_____|_|\_)_____)\____|_|
+
+
+     Signal Name                 Dec        Hex                   Bin
+     -------------------- ---------- ---------- ---------------------
+     \a                        15029       3ab5      0011101010110101
+     \b                         4099       1003      0001000000000011
+     \ok                           0          0                     0
+     \p                           31         1f      0000000000011111
+
+The Yosys shell session shown in :numref:`prime_shell` demonstrates that SAT
+solvers can even find the unexpected solutions to a problem: Using integer
+overflow there actually is a way of "factorizing" 31. The clean solution would
+of course be to perform the test in 32 bits, for example by replacing ``p !=
+a*b`` in the miter with ``p != {16'd0,a}b``, or by using a temporary variable
+for the 32 bit product ``a*b``. But as 31 fits well into 8 bits (and as the
+purpose of this document is to show off Yosys features) we can also simply force
+the upper 8 bits of ``a`` and ``b`` to zero for the :cmd:ref:`sat` call, as is
+done below.
+
+.. todo:: replace inline code
+
+.. code-block::
+   :caption: Miter circuit from :file:`primetest.v`, with the upper 8 bits of ``a``
+             and ``b`` constrained to prevent overflow.
+   :name: prime_fixed
+
+   yosys [primetest]> sat -prove ok 1 -set p 31 -set a[15:8],b[15:8] 0
+
+   1. Executing SAT pass (solving SAT problems in the circuit).
+   Full command line: sat -prove ok 1 -set p 31 -set a[15:8],b[15:8] 0
+
+   Setting up SAT problem:
+   Import set-constraint: \p = 16'0000000000011111
+   Import set-constraint: { \a [15:8] \b [15:8] } = 16'0000000000000000
+   Final constraint equation: { \a [15:8] \b [15:8] \p } = { 16'0000000000000000 16'0000000000011111 }
+   Imported 6 cells to SAT database.
+   Import proof-constraint: \ok = 1'1
+   Final proof equation: \ok = 1'1
+
+   Solving problem with 2790 variables and 8257 clauses..
+   SAT proof finished - no model found: SUCCESS!
+
+                     /$$$$$$      /$$$$$$$$     /$$$$$$$
+                    /$$__  $$    | $$_____/    | $$__  $$
+                   | $$  \ $$    | $$          | $$  \ $$
+                   | $$  | $$    | $$$$$       | $$  | $$
+                   | $$  | $$    | $$__/       | $$  | $$
+                   | $$/$$ $$    | $$          | $$  | $$
+                   |  $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$
+                    \____ $$$|__/|________/|__/|_______/|__/
+                          \__/
+
+The ``-prove`` option used in :numref:`prime_fixed` works similar to ``-set``,
+but tries to find a case in which the two arguments are not equal. If such a
+case is not found, the property is proven to hold for all inputs that satisfy
+the other constraints.
+
+It might be worth noting, that SAT solvers are not particularly efficient at
+factorizing large numbers. But if a small factorization problem occurs as part
+of a larger circuit problem, the Yosys SAT solver is perfectly capable of
+solving it.
+
+Solving sequential SAT problems
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The SAT solver functionality in Yosys can not only be used to solve
+combinatorial problems, but can also solve sequential problems. Let's consider
+the ``memdemo`` design from :ref:`advanced_logic_cones` again, and suppose we
+want to know which sequence of input values for ``d`` will cause the output y to
+produce the sequence 1, 2, 3 from any initial state. Let's use the following
+command:
+
+.. todo:: replace inline code?
+
+.. code-block:: yoscrypt
+
+      sat -seq 6 -show y -show d -set-init-undef \
+        -max_undef -set-at 4 y 1 -set-at 5 y 2 -set-at 6 y 3
+
+The ``-seq 6`` option instructs the :cmd:ref:`sat` command to solve a sequential
+problem in 6 time steps. (Experiments with lower number of steps have show that
+at least 3 cycles are necessary to bring the circuit in a state from which the
+sequence 1, 2, 3 can be produced.)
+
+The ``-set-init-undef`` option tells the :cmd:ref:`sat` command to initialize
+all registers to the undef (``x``) state. The way the ``x`` state is treated in
+Verilog will ensure that the solution will work for any initial state.
+
+The ``-max_undef`` option instructs the :cmd:ref:`sat` command to find a
+solution with a maximum number of undefs. This way we can see clearly which
+inputs bits are relevant to the solution.
+
+Finally the three ``-set-at`` options add constraints for the ``y`` signal to
+play the 1, 2, 3 sequence, starting with time step 4.
+
+This produces the following output:
+
+.. todo:: replace inline code
+
+.. code-block::
+   :caption: Solving a sequential SAT problem in the ``memdemo`` module.
+   :name: memdemo_sat
+
+   yosys [memdemo]> sat -seq 6 -show y -show d -set-init-undef \
+       -max_undef -set-at 4 y 1 -set-at 5 y 2 -set-at 6 y 3
+
+   1. Executing SAT pass (solving SAT problems in the circuit).
+   Full command line: sat -seq 6 -show y -show d -set-init-undef
+       -max_undef -set-at 4 y 1 -set-at 5 y 2 -set-at 6 y 3
+
+   Setting up time step 1:
+   Final constraint equation: { } = { }
+   Imported 29 cells to SAT database.
+
+   Setting up time step 2:
+   Final constraint equation: { } = { }
+   Imported 29 cells to SAT database.
+
+   Setting up time step 3:
+   Final constraint equation: { } = { }
+   Imported 29 cells to SAT database.
+
+   Setting up time step 4:
+   Import set-constraint for timestep: \y = 4'0001
+   Final constraint equation: \y = 4'0001
+   Imported 29 cells to SAT database.
+
+   Setting up time step 5:
+   Import set-constraint for timestep: \y = 4'0010
+   Final constraint equation: \y = 4'0010
+   Imported 29 cells to SAT database.
+
+   Setting up time step 6:
+   Import set-constraint for timestep: \y = 4'0011
+   Final constraint equation: \y = 4'0011
+   Imported 29 cells to SAT database.
+
+   Setting up initial state:
+   Final constraint equation: { \y \s2 \s1 \mem[3] \mem[2] \mem[1]
+               \mem[0] } = 24'xxxxxxxxxxxxxxxxxxxxxxxx
+
+   Import show expression: \y
+   Import show expression: \d
+
+   Solving problem with 10322 variables and 27881 clauses..
+   SAT model found. maximizing number of undefs.
+   SAT solving finished - model found:
+
+     Time Signal Name                 Dec        Hex             Bin
+     ---- -------------------- ---------- ---------- ---------------
+     init \mem[0]                      --         --            xxxx
+     init \mem[1]                      --         --            xxxx
+     init \mem[2]                      --         --            xxxx
+     init \mem[3]                      --         --            xxxx
+     init \s1                          --         --              xx
+     init \s2                          --         --              xx
+     init \y                           --         --            xxxx
+     ---- -------------------- ---------- ---------- ---------------
+        1 \d                            0          0            0000
+        1 \y                           --         --            xxxx
+     ---- -------------------- ---------- ---------- ---------------
+        2 \d                            1          1            0001
+        2 \y                           --         --            xxxx
+     ---- -------------------- ---------- ---------- ---------------
+        3 \d                            2          2            0010
+        3 \y                            0          0            0000
+     ---- -------------------- ---------- ---------- ---------------
+        4 \d                            3          3            0011
+        4 \y                            1          1            0001
+     ---- -------------------- ---------- ---------- ---------------
+        5 \d                           --         --            001x
+        5 \y                            2          2            0010
+     ---- -------------------- ---------- ---------- ---------------
+        6 \d                           --         --            xxxx
+        6 \y                            3          3            0011
+
+It is not surprising that the solution sets ``d = 0`` in the first step, as this
+is the only way of setting the ``s1`` and ``s2`` registers to a known value. The
+input values for the other steps are a bit harder to work out manually, but the
+SAT solver finds the correct solution in an instant.
+
+There is much more to write about the :cmd:ref:`sat` command. For example, there
+is a set of options that can be used to performs sequential proofs using
+temporal induction :cite:p:`een2003temporal`. The command ``help sat`` can be
+used to print a list of all options with short descriptions of their functions.
diff --git a/yosys/docs/source/using_yosys/more_scripting/load_design.rst b/yosys/docs/source/using_yosys/more_scripting/load_design.rst
new file mode 100644
index 00000000000..d64c50959bd
--- /dev/null
+++ b/yosys/docs/source/using_yosys/more_scripting/load_design.rst
@@ -0,0 +1,40 @@
+Loading a design
+~~~~~~~~~~~~~~~~
+
+keyword: Frontends
+
+- :doc:`/cmd/read_verilog`
+
+.. todo:: include ``read_verilog <<EOF``, also other methods of loading designs
+
+.. code-block:: yoscrypt
+
+    read_verilog file1.v
+    read_verilog -I include_dir -D enable_foo -D WIDTH=12 file2.v
+    read_verilog -lib cell_library.v
+
+    verilog_defaults -add -I include_dir
+    read_verilog file3.v
+    read_verilog file4.v
+    verilog_defaults -clear
+
+    verilog_defaults -push
+    verilog_defaults -add -I include_dir
+    read_verilog file5.v
+    read_verilog file6.v
+    verilog_defaults -pop
+
+.. todo:: more info on other ``read_*`` commands, also is this the first time we
+   mention verific?
+
+Others:
+
+- :doc:`/cmd/read`
+- `GHDL plugin`_ for VHDL
+- :doc:`/cmd/read_rtlil` (direct textual representation of Yosys internal state)
+- :doc:`/cmd/read_aiger`
+- :doc:`/cmd/read_blif`
+- :doc:`/cmd/read_json`
+- :doc:`/cmd/read_liberty`
+
+.. _GHDL plugin: https://github.com/ghdl/ghdl-yosys-plugin
diff --git a/yosys/docs/source/using_yosys/more_scripting/model_checking.rst b/yosys/docs/source/using_yosys/more_scripting/model_checking.rst
new file mode 100644
index 00000000000..92a9d85ce67
--- /dev/null
+++ b/yosys/docs/source/using_yosys/more_scripting/model_checking.rst
@@ -0,0 +1,120 @@
+Symbolic model checking
+-----------------------
+
+.. todo:: check text context
+
+.. note:: 
+    
+    While it is possible to perform model checking directly in Yosys, it 
+    is highly recommended to use SBY or EQY for formal hardware verification.
+
+Symbolic Model Checking (SMC) is used to formally prove that a circuit has (or
+has not) a given property.
+
+One application is Formal Equivalence Checking: Proving that two circuits are
+identical. For example this is a very useful feature when debugging custom
+passes in Yosys.
+
+Other applications include checking if a module conforms to interface standards.
+
+The :cmd:ref:`sat` command in Yosys can be used to perform Symbolic Model
+Checking.
+
+Checking techmap
+~~~~~~~~~~~~~~~~
+
+.. todo:: add/expand supporting text
+
+Let's take a look at an example included in the Yosys code base under
+|code_examples/synth_flow|_:
+
+.. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
+.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
+
+.. literalinclude:: /code_examples/synth_flow/techmap_01_map.v
+   :language: verilog
+   :caption: :file:`techmap_01_map.v`
+
+.. literalinclude:: /code_examples/synth_flow/techmap_01.v
+   :language: verilog
+   :caption: :file:`techmap_01.v`
+
+.. literalinclude:: /code_examples/synth_flow/techmap_01.ys
+   :language: yoscrypt
+   :caption: :file:`techmap_01.ys`
+
+To see if it is correct we can use the following code:
+
+.. todo:: replace inline code
+
+.. code:: yoscrypt
+
+    # read test design
+    read_verilog techmap_01.v
+    hierarchy -top test
+
+    # create two version of the design: test_orig and test_mapped
+    copy test test_orig
+    rename test test_mapped
+
+    # apply the techmap only to test_mapped
+    techmap -map techmap_01_map.v test_mapped
+
+    # create a miter circuit to test equivalence
+    miter -equiv -make_assert -make_outputs test_orig test_mapped miter
+    flatten miter
+
+    # run equivalence check
+    sat -verify -prove-asserts -show-inputs -show-outputs miter
+
+Result:
+
+.. code::
+
+    Solving problem with 945 variables and 2505 clauses..
+    SAT proof finished - no model found: SUCCESS!
+
+AXI4 Stream Master
+~~~~~~~~~~~~~~~~~~
+
+The code used in this section is included in the Yosys code base under
+|code_examples/axis|_.
+
+.. |code_examples/axis| replace:: :file:`docs/source/code_examples/axis`
+.. _code_examples/axis: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/axis
+
+The following AXI4 Stream Master has a bug. But the bug is not exposed if the
+slave keeps ``tready`` asserted all the time. (Something a test bench might do.)
+
+Symbolic Model Checking can be used to expose the bug and find a sequence of
+values for ``tready`` that yield the incorrect behavior.
+
+.. todo:: add/expand supporting text
+
+.. literalinclude:: /code_examples/axis/axis_master.v
+   :language: verilog
+   :caption: :file:`axis_master.v`
+
+.. literalinclude:: /code_examples/axis/axis_test.v
+   :language: verilog
+   :caption: :file:`axis_test.v`
+
+.. literalinclude:: /code_examples/axis/axis_test.ys
+   :language: yoscrypt
+   :caption: :file:`test.ys`
+
+Result with unmodified :file:`axis_master.v`:
+
+.. todo:: replace inline code
+
+.. code::
+
+    Solving problem with 159344 variables and 442126 clauses..
+    SAT proof finished - model found: FAIL!
+
+Result with fixed :file:`axis_master.v`:
+
+.. code::
+
+    Solving problem with 159144 variables and 441626 clauses..
+    SAT proof finished - no model found: SUCCESS!
diff --git a/yosys/docs/source/using_yosys/more_scripting/selections.rst b/yosys/docs/source/using_yosys/more_scripting/selections.rst
new file mode 100644
index 00000000000..b0028347499
--- /dev/null
+++ b/yosys/docs/source/using_yosys/more_scripting/selections.rst
@@ -0,0 +1,422 @@
+Selections
+----------
+
+.. role:: yoscrypt(code)
+   :language: yoscrypt
+
+The selection framework
+~~~~~~~~~~~~~~~~~~~~~~~
+
+.. todo:: reduce overlap with :doc:`/getting_started/scripting_intro` select section
+
+The :cmd:ref:`select` command can be used to create a selection for subsequent
+commands. For example:
+
+.. code:: yoscrypt
+
+    select foobar         # select the module foobar
+    delete                # delete selected objects
+
+Normally the :cmd:ref:`select` command overwrites a previous selection. The
+commands :yoscrypt:`select -add` and :yoscrypt:`select -del` can be used to add
+or remove objects from the current selection.
+
+The command :yoscrypt:`select -clear` can be used to reset the selection to the
+default, which is a complete selection of everything in the current module.
+
+This selection framework can also be used directly in many other commands.
+Whenever a command has ``[selection]`` as last argument in its usage help, this
+means that it will use the engine behind the :cmd:ref:`select` command to
+evaluate additional arguments and use the resulting selection instead of the
+selection created by the last :cmd:ref:`select` command.
+
+For example, the command :cmd:ref:`delete` will delete everything in the current
+selection; while :yoscrypt:`delete foobar` will only delete the module foobar.
+If no :cmd:ref:`select` command has been made, then the "current selection" will
+be the whole design.
+
+.. note:: Many of the examples on this page make use of the :cmd:ref:`show` 
+   command to visually demonstrate the effect of selections.  For a more 
+   detailed look at this command, refer to :ref:`interactive_show`.
+
+How to make a selection
+~~~~~~~~~~~~~~~~~~~~~~~
+
+Selection by object name
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+The easiest way to select objects is by object name. This is usually only done
+in synthesis scripts that are hand-tailored for a specific design.
+
+.. code:: yoscrypt
+
+    select foobar         # select module foobar
+    select foo*           # select all modules whose names start with foo
+    select foo*/bar*      # select all objects matching bar* from modules matching foo*
+    select */clk          # select objects named clk from all modules
+
+Module and design context
+^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Commands can be executed in *module/* or *design/* context. Until now, all
+commands have been executed in design context. The :cmd:ref:`cd` command can be
+used to switch to module context.
+
+In module context, all commands only effect the active module. Objects in the
+module are selected without the ``<module_name>/`` prefix. For example:
+
+.. code:: yoscrypt
+
+    cd foo                # switch to module foo
+    delete bar            # delete object foo/bar
+
+    cd mycpu              # switch to module mycpu
+    dump reg_*            # print details on all objects whose names start with reg_
+
+    cd ..                 # switch back to design
+
+Note: Most synthesis scripts never switch to module context. But it is a very
+powerful tool which we explore more in
+:doc:`/using_yosys/more_scripting/interactive_investigation`.
+
+Selecting by object property or type
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Special patterns can be used to select by object property or type. For example:
+
+- select all wires whose names start with ``reg_``: :yoscrypt:`select w:reg_*`
+- select all objects with the attribute ``foobar`` set: :yoscrypt:`select
+  a:foobar`
+- select all objects with the attribute ``foobar`` set to 42: :yoscrypt:`select
+  a:foobar=42`
+- select all modules with the attribute ``blabla`` set: :yoscrypt:`select
+  A:blabla`
+- select all $add cells from the module foo: :yoscrypt:`select foo/t:$add`
+
+A complete list of pattern expressions can be found in :doc:`/cmd/select`.
+
+Operations on selections
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Combining selections
+^^^^^^^^^^^^^^^^^^^^
+
+The :cmd:ref:`select` command is actually much more powerful than it might seem
+at first glance. When it is called with multiple arguments, each argument is
+evaluated and pushed separately on a stack. After all arguments have been
+processed it simply creates the union of all elements on the stack. So
+:yoscrypt:`select t:$add a:foo` will select all ``$add`` cells and all objects
+with the ``foo`` attribute set:   
+
+.. literalinclude:: /code_examples/selections/foobaraddsub.v
+   :caption: Test module for operations on selections
+   :name: foobaraddsub
+   :language: verilog
+
+.. code-block::
+   :caption: Output for command ``select t:$add a:foo -list`` on :numref:`foobaraddsub`
+
+   yosys> select t:$add a:foo -list
+   foobaraddsub/$add$foobaraddsub.v:6$3
+   foobaraddsub/$sub$foobaraddsub.v:5$2
+   foobaraddsub/$add$foobaraddsub.v:4$1
+
+In many cases simply adding more and more stuff to the selection is an
+ineffective way of selecting the interesting part of the design. Special
+arguments can be used to combine the elements on the stack. For example the
+``%i`` arguments pops the last two elements from the stack, intersects them, and
+pushes the result back on the stack. So :yoscrypt:`select t:$add a:foo %i` will
+select all ``$add`` cells that have the ``foo`` attribute set:
+
+.. code-block::
+   :caption: Output for command ``select t:$add a:foo %i -list`` on :numref:`foobaraddsub`
+   
+   yosys> select t:$add a:foo %i -list
+   foobaraddsub/$add$foobaraddsub.v:4$1
+
+Some of the special ``%``-codes:
+
+- ``%u``: union of top two elements on stack -- pop 2, push 1
+- ``%d``: difference of top two elements on stack -- pop 2, push 1
+- ``%i``: intersection of top two elements on stack -- pop 2, push 1
+- ``%n``: inverse of top element on stack -- pop 1, push 1
+
+See :doc:`/cmd/select` for the full list.
+
+Expanding selections
+^^^^^^^^^^^^^^^^^^^^
+
+:numref:`sumprod` uses the Yosys non-standard ``{... *}`` syntax to set the
+attribute ``sumstuff`` on all cells generated by the first assign statement.
+(This works on arbitrary large blocks of Verilog code and can be used to mark
+portions of code for analysis.)
+
+.. literalinclude:: /code_examples/selections/sumprod.v
+   :caption: Another test module for operations on selections
+   :name: sumprod
+   :language: verilog
+
+Selecting ``a:sumstuff`` in this module will yield the following circuit
+diagram:
+
+.. figure:: /_images/code_examples/selections/sumprod_00.*
+   :class: width-helper invert-helper
+   :name: sumprod_00
+
+   Output of ``show a:sumstuff`` on :numref:`sumprod`
+
+As only the cells themselves are selected, but not the temporary wire ``$1_Y``,
+the two adders are shown as two disjunct parts. This can be very useful for
+global signals like clock and reset signals: just unselect them using a command
+such as :yoscrypt:`select -del clk rst` and each cell using them will get its
+own net label.
+
+In this case however we would like to see the cells connected properly. This can
+be achieved using the ``%x`` action, that broadens the selection, i.e. for each
+selected wire it selects all cells connected to the wire and vice versa. So
+:yoscrypt:`show a:sumstuff %x` yields the diagram shown in :numref:`sumprod_01`:
+
+.. figure:: /_images/code_examples/selections/sumprod_01.*
+   :class: width-helper invert-helper
+   :name: sumprod_01
+
+   Output of ``show a:sumstuff %x`` on :numref:`sumprod`
+
+.. _selecting_logic_cones:
+
+Selecting logic cones
+^^^^^^^^^^^^^^^^^^^^^
+
+:numref:`sumprod_01` shows what is called the ``input cone`` of ``sum``, i.e.
+all cells and signals that are used to generate the signal ``sum``. The ``%ci``
+action can be used to select the input cones of all object in the top selection
+in the stack maintained by the :cmd:ref:`select` command.
+
+As with the ``%x`` action, these commands broaden the selection by one "step".
+But this time the operation only works against the direction of data flow. That
+means, wires only select cells via output ports and cells only select wires via
+input ports.
+
+The following sequence of diagrams demonstrates this step-wise expansion:
+
+.. figure:: /_images/code_examples/selections/sumprod_02.*
+   :class: width-helper invert-helper
+
+   Output of :yoscrypt:`show prod` on :numref:`sumprod`
+
+.. figure:: /_images/code_examples/selections/sumprod_03.*
+   :class: width-helper invert-helper
+
+   Output of :yoscrypt:`show prod %ci` on :numref:`sumprod`
+
+.. figure:: /_images/code_examples/selections/sumprod_04.*
+   :class: width-helper invert-helper
+
+   Output of :yoscrypt:`show prod %ci %ci` on :numref:`sumprod`
+
+.. figure:: /_images/code_examples/selections/sumprod_05.*
+   :class: width-helper invert-helper
+
+   Output of :yoscrypt:`show prod %ci %ci %ci` on :numref:`sumprod`
+
+Notice the subtle difference between :yoscrypt:`show prod %ci` and
+:yoscrypt:`show prod %ci %ci`.  Both images show the ``$mul`` cell driven by
+some inputs ``$3_Y`` and ``c``.  However it is not until the second image,
+having called ``%ci`` the second time, that :cmd:ref:`show` is able to
+distinguish between ``$3_Y`` being a wire and ``c`` being an input.  We can see
+this better with the :cmd:ref:`dump` command instead:
+
+.. literalinclude:: /code_examples/selections/sumprod.out
+   :language: RTLIL
+   :end-at: end
+   :caption: Output of :yoscrypt:`dump prod %ci`
+
+.. literalinclude:: /code_examples/selections/sumprod.out
+   :language: RTLIL
+   :start-after: end
+   :caption: Output of :yoscrypt:`dump prod %ci %ci`
+
+When selecting many levels of logic, repeating ``%ci`` over and over again can
+be a bit dull. So there is a shortcut for that: the number of iterations can be
+appended to the action. So for example the action ``%ci3`` is identical to
+performing the ``%ci`` action three times.
+
+The action ``%ci*`` performs the ``%ci`` action over and over again until it
+has no effect anymore.
+
+.. _advanced_logic_cones:
+
+Advanced logic cone selection
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+In most cases there are certain cell types and/or ports that should not be
+considered for the ``%ci`` action, or we only want to follow certain cell types
+and/or ports. This can be achieved using additional patterns that can be
+appended to the ``%ci`` action.
+
+Lets consider :numref:`memdemo_src`. It serves no purpose other than being a
+non-trivial circuit for demonstrating some of the advanced Yosys features. This
+code is available in ``docs/source/code_examples/selections`` of the Yosys
+source repository.
+
+.. literalinclude:: /code_examples/selections/memdemo.v
+   :caption: :file:`memdemo.v`
+   :name: memdemo_src
+   :language: verilog
+
+The script :file:`memdemo.ys` is used to generate the images included here. Let's
+look at the first section:
+
+.. literalinclude:: /code_examples/selections/memdemo.ys
+   :caption: Synthesizing :ref:`memdemo_src`
+   :name: memdemo_ys
+   :language: yoscrypt
+   :end-at: opt
+
+This loads :numref:`memdemo_src` and synthesizes the included module. Note that
+this code can be copied and run directly in a Yosys command line session,
+provided :file:`memdemo.v` is in the same directory. We can now change to the
+``memdemo`` module with ``cd memdemo``, and call :cmd:ref:`show` to see the
+diagram in :numref:`memdemo_00`.
+
+.. figure:: /_images/code_examples/selections/memdemo_00.*
+   :class: width-helper invert-helper
+   :name: memdemo_00
+   
+   Complete circuit diagram for the design shown in :numref:`memdemo_src`
+
+There's a lot going on there, but maybe we are only interested in the tree of
+multiplexers that select the output value. Let's start by just showing the
+output signal, ``y``, and its immediate predecessors. Remember `Selecting logic
+cones`_ from above, we can use :yoscrypt:`show y %ci2`:
+
+.. figure:: /_images/code_examples/selections/memdemo_01.*
+   :class: width-helper invert-helper
+   :name: memdemo_01
+   
+   Output of :yoscrypt:`show y %ci2`
+
+From this we would learn that ``y`` is driven by a ``$dff cell``, that ``y`` is
+connected to the output port ``Q``, that the ``clk`` signal goes into the
+``CLK`` input port of the cell, and that the data comes from an auto-generated
+wire into the input ``D`` of the flip-flop cell (indicated by the ``$`` at the
+start of the name).  Let's go a bit further now and try :yoscrypt:`show y %ci5`:
+
+.. figure:: /_images/code_examples/selections/memdemo_02.*
+   :class: width-helper invert-helper
+   :name: memdemo_02
+   
+   Output of :yoscrypt:`show y %ci5`
+
+That's starting to get a bit messy, so maybe we want to ignore the mux select
+inputs. To add a pattern we add a colon followed by the pattern to the ``%ci``
+action. The pattern itself starts with ``-`` or ``+``, indicating if it is an
+include or exclude pattern, followed by an optional comma separated list of cell
+types, followed by an optional comma separated list of port names in square
+brackets.  In this case, we want to exclude the ``S`` port of the ``$mux`` cell
+type with :yoscrypt:`show y %ci5:-$mux[S]`:
+
+.. figure:: /_images/code_examples/selections/memdemo_03.*
+   :class: width-helper invert-helper
+   :name: memdemo_03
+   
+   Output of :yoscrypt:`show y %ci5:-$mux[S]`
+
+We could use a command such as :yoscrypt:`show y %ci2:+$dff[Q,D]
+%ci*:-$mux[S]:-$dff` in which the first ``%ci`` jumps over the initial d-type
+flip-flop and the 2nd action selects the entire input cone without going over
+multiplexer select inputs and flip-flop cells:
+
+.. figure:: /_images/code_examples/selections/memdemo_05.*
+   :class: width-helper invert-helper
+   :name: memdemo_05
+   
+   Output of ``show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff``
+
+Or we could use :yoscrypt:`show y %ci*:-[CLK,S]:+$dff:+$mux` instead, following
+the input cone all the way but only following ``$dff`` and ``$mux`` cells, and
+ignoring any ports named ``CLK`` or ``S``:
+
+.. TODO:: pending discussion on whether rule ordering is a bug or a feature
+
+.. figure:: /_images/code_examples/selections/memdemo_04.*
+   :class: width-helper invert-helper
+   :name: memdemo_04
+   
+   Output of :yoscrypt:`show y %ci*:-[CLK,S]:+$dff,$mux`
+
+Similar to ``%ci`` exists an action ``%co`` to select output cones that accepts
+the same syntax for pattern and repetition. The ``%x`` action mentioned
+previously also accepts this advanced syntax.
+
+These actions for traversing the circuit graph, combined with the actions for
+boolean operations such as intersection (``%i``) and difference (``%d``) are
+powerful tools for extracting the relevant portions of the circuit under
+investigation.
+
+Again, see :doc:`/cmd/select` for full documentation of these expressions.
+
+Incremental selection
+^^^^^^^^^^^^^^^^^^^^^
+
+Sometimes a selection can most easily be described by a series of add/delete
+operations. As mentioned previously, the commands :yoscrypt:`select -add` and
+:yoscrypt:`select -del` respectively add or remove objects from the current
+selection instead of overwriting it.
+
+.. code:: yoscrypt
+
+    select -none            # start with an empty selection
+    select -add reg_*       # select a bunch of objects
+    select -del reg_42      # but not this one
+    select -add state %ci   # and add more stuff
+
+Within a select expression the token ``%`` can be used to push the previous selection
+on the stack.
+
+.. code:: yoscrypt
+
+    select t:$add t:$sub    # select all $add and $sub cells
+    select % %ci % %d       # select only the input wires to those cells
+
+Storing and recalling selections
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. todo:: reflow for not presentation
+
+The current selection can be stored in memory with the command ``select -set
+<name>``. It can later be recalled using ``select @<name>``. In fact, the
+``@<name>`` expression pushes the stored selection on the stack maintained by
+the :cmd:ref:`select` command. So for example :yoscrypt:`select @foo @bar %i`
+will select the intersection between the stored selections ``foo`` and ``bar``.
+
+In larger investigation efforts it is highly recommended to maintain a script
+that sets up relevant selections, so they can easily be recalled, for example
+when Yosys needs to be re-run after a design or source code change.
+
+The :cmd:ref:`history` command can be used to list all recent interactive
+commands. This feature can be useful for creating such a script from the
+commands used in an interactive session.
+
+Remember that select expressions can also be used directly as arguments to most
+commands. Some commands also accept a single select argument to some options. In
+those cases selection variables must be used to capture more complex selections.
+
+Example code from |code_examples/selections|_:
+
+.. |code_examples/selections| replace:: :file:`docs/source/code_examples/selections`
+.. _code_examples/selections: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/selections
+
+.. literalinclude:: /code_examples/selections/select.v
+   :language: verilog
+   :caption: :file:`select.v`
+
+.. literalinclude:: /code_examples/selections/select.ys
+   :language: yoscrypt
+   :caption: :file:`select.ys`
+   :name: select_ys
+
+.. figure:: /_images/code_examples/selections/select.*
+    :class: width-helper invert-helper
+
+    Circuit diagram produced by :numref:`select_ys`
diff --git a/yosys/docs/source/using_yosys/more_scripting/troubleshooting.rst b/yosys/docs/source/using_yosys/more_scripting/troubleshooting.rst
new file mode 100644
index 00000000000..a17a552d2e4
--- /dev/null
+++ b/yosys/docs/source/using_yosys/more_scripting/troubleshooting.rst
@@ -0,0 +1,6 @@
+Troubleshooting
+~~~~~~~~~~~~~~~
+
+.. todo:: troubleshooting document(?)
+
+See :doc:`/cmd/bugpoint`
diff --git a/yosys/docs/source/using_yosys/synthesis/abc.rst b/yosys/docs/source/using_yosys/synthesis/abc.rst
new file mode 100644
index 00000000000..928b320186d
--- /dev/null
+++ b/yosys/docs/source/using_yosys/synthesis/abc.rst
@@ -0,0 +1,103 @@
+The ABC toolbox
+---------------
+
+.. role:: yoscrypt(code)
+   :language: yoscrypt
+
+ABC_, from the University of California, Berkeley, is a logic toolbox used for
+fine-grained optimisation and LUT mapping.
+
+Yosys has two different commands, which both use this logic toolbox, but use it
+in different ways.
+
+The :cmd:ref:`abc` pass can be used for both ASIC (e.g. :yoscrypt:`abc
+-liberty`) and FPGA (:yoscrypt:`abc -lut`) mapping, but this page will focus on
+FPGA mapping.
+
+The :cmd:ref:`abc9` pass generally provides superior mapping quality due to
+being aware of combination boxes and DFF and LUT timings, giving it a more
+global view of the mapping problem.
+
+.. _ABC: https://github.com/berkeley-abc/abc
+
+ABC: the unit delay model, simple and efficient
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The :cmd:ref:`abc` pass uses a highly simplified view of an FPGA:
+
+- An FPGA is made up of a network of inputs that connect through LUTs to a
+  network of outputs. These inputs may actually be I/O pins, D flip-flops,
+  memory blocks or DSPs, but ABC is unaware of this.
+- Each LUT has 1 unit of delay between an input and its output, and this applies
+  for all inputs of a LUT, and for all sizes of LUT up to the maximum LUT size
+  allowed; e.g. the delay between the input of a LUT2 and its output is the same
+  as the delay between the input of a LUT6 and its output.
+- A LUT may take up a variable number of area units. This is constant for each
+  size of LUT; e.g. a LUT4 may take up 1 unit of area, but a LUT5 may take up 2
+  units of area, but this applies for all LUT4s and LUT5s.
+
+This is known as the "unit delay model", because each LUT uses one unit of
+delay.
+
+From this view, the problem ABC has to solve is finding a mapping of the network
+to LUTs that has the lowest delay, and then optimising the mapping for size
+while maintaining this delay.
+
+This approach has advantages:
+
+- It is simple and easy to implement.
+- Working with unit delays is fast to manipulate.
+- It reflects *some* FPGA families, for example, the iCE40HX/LP fits the
+  assumptions of the unit delay model quite well (almost all synchronous blocks,
+  except for adders).
+
+But this approach has drawbacks, too:
+
+- The network of inputs and outputs with only LUTs means that a lot of
+  combinational cells (multipliers and LUTRAM) are invisible to the unit delay
+  model, meaning the critical path it optimises for is not necessarily the
+  actual critical path.
+- LUTs are implemented as multiplexer trees, so there is a delay caused by the
+  result propagating through the remaining multiplexers. This means the
+  assumption of delay being equal isn't true in physical hardware, and is
+  proportionally larger for larger LUTs.
+- Even synchronous blocks have arrival times (propagation delay between clock
+  edge to output changing) and setup times (requirement for input to be stable
+  before clock edge) which affect the delay of a path.
+
+ABC9: the generalised delay model, realistic and flexible
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ABC9 uses a more detailed and accurate model of an FPGA:
+
+- An FPGA is made up of a network of inputs that connect through LUTs and
+  combinational boxes to a network of outputs. These boxes have specified delays
+  between inputs and outputs, and may have an associated network ("white boxes")
+  or not ("black boxes"), but must be treated as a whole.
+- Each LUT has a specified delay between an input and its output in arbitrary
+  delay units, and this varies for all inputs of a LUT and for all sizes of LUT,
+  but each size of LUT has the same associated delay; e.g. the delay between
+  input A and output is different between a LUT2 and a LUT6, but is constant for
+  all LUT6s.
+- A LUT may take up a variable number of area units. This is constant for each
+  size of LUT; e.g. a LUT4 may take up 1 unit of area, but a LUT5 may take up 2
+  units of area, but this applies for all LUT4s and LUT5s.
+
+This is known as the "generalised delay model", because it has been generalised
+to arbitrary delay units. ABC9 doesn't actually care what units you use here,
+but the Yosys convention is picoseconds. Note the introduction of boxes as a
+concept. While the generalised delay model does not require boxes, they
+naturally fit into it to represent combinational delays. Even synchronous delays
+like arrival and setup can be emulated with combinational boxes that act as a
+delay. This is further extended to white boxes, where the mapper is able to see
+inside a box, and remove orphan boxes with no outputs, such as adders.
+
+Again, ABC9 finds a mapping of the network to LUTs that has the lowest delay,
+and then minimises it to find the lowest area, but it has a lot more information
+to work with about the network.
+
+The result here is that ABC9 can remove boxes (like adders) to reduce area,
+optimise better around those boxes, and also permute inputs to give the critical
+path the fastest inputs.
+
+.. todo:: more about logic minimization & register balancing et al with ABC
diff --git a/yosys/docs/source/using_yosys/synthesis/cell_libs.rst b/yosys/docs/source/using_yosys/synthesis/cell_libs.rst
new file mode 100644
index 00000000000..92b6dab3f58
--- /dev/null
+++ b/yosys/docs/source/using_yosys/synthesis/cell_libs.rst
@@ -0,0 +1,125 @@
+Mapping to cell libraries
+-------------------------
+
+.. role:: yoscrypt(code)
+   :language: yoscrypt
+
+While much of this documentation focuses on the use of Yosys with FPGAs, it is
+also possible to map to cell libraries which can be used in designing ASICs.
+This section will cover a brief `example project`_, available in the Yosys
+source code under :file:`docs/source/code_examples/intro/`.  The project
+contains a simple ASIC synthesis script (:file:`counter.ys`), a digital design
+written in Verilog (:file:`counter.v`), and a simple CMOS cell library
+(:file:`mycells.lib`).  Many of the early steps here are already covered in more
+detail in the :doc:`/getting_started/example_synth` document.
+
+.. note::
+
+   The :file:`counter.ys` script includes the commands used to generate the
+   images in this document.  Code snippets in this document skip these commands;
+   including line numbers to allow the reader to follow along with the source.
+   
+   To learn more about these commands, check out :ref:`interactive_show`.
+
+.. _example project: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/intro
+
+A simple counter
+~~~~~~~~~~~~~~~~
+
+First, let's quickly look at the design:
+
+.. literalinclude:: /code_examples/intro/counter.v
+   :language: Verilog
+   :linenos:
+   :name: counter-v
+   :caption: :file:`counter.v`
+
+This is a simple counter with reset and enable.  If the reset signal, ``rst``,
+is high then the counter will reset to 0.  Otherwise, if the enable signal,
+``en``, is high then the ``count`` register will increment by 1 each rising edge
+of the clock, ``clk``.  
+
+Loading the design
+~~~~~~~~~~~~~~~~~~
+
+.. literalinclude:: /code_examples/intro/counter.ys
+   :language: yoscrypt
+   :lines: 1-3
+   :lineno-match:
+   :caption: :file:`counter.ys` - read design
+
+Our circuit now looks like this:
+
+.. figure:: /_images/code_examples/intro/counter_00.*
+   :class: width-helper invert-helper
+   :name: counter-hierarchy
+
+   ``counter`` after :cmd:ref:`hierarchy`
+
+Coarse-grain representation
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. literalinclude:: /code_examples/intro/counter.ys
+   :language: yoscrypt
+   :lines: 7-10
+   :lineno-match:
+   :caption: :file:`counter.ys` - the high-level stuff
+
+.. figure:: /_images/code_examples/intro/counter_01.*
+   :class: width-helper invert-helper
+
+   Coarse-grain representation of the ``counter`` module
+
+Logic gate mapping
+~~~~~~~~~~~~~~~~~~
+
+.. literalinclude:: /code_examples/intro/counter.ys
+   :language: yoscrypt
+   :lines: 14-15
+   :lineno-match:
+   :caption: :file:`counter.ys` - mapping to internal cell library
+
+.. figure:: /_images/code_examples/intro/counter_02.*
+   :class: width-helper invert-helper
+
+   ``counter`` after :cmd:ref:`techmap`
+
+Mapping to hardware
+~~~~~~~~~~~~~~~~~~~
+
+For this example, we are using a Liberty file to describe a cell library which
+our internal cell library will be mapped to:
+
+.. literalinclude:: /code_examples/intro/mycells.lib
+   :language: Liberty
+   :linenos:
+   :name: mycells-lib
+   :caption: :file:`mycells.lib`
+
+Recall that the Yosys built-in logic gate types are ``$_NOT_``, ``$_AND_``,
+``$_OR_``, ``$_XOR_``, and ``$_MUX_`` with an assortment of dff memory types.
+:ref:`mycells-lib` defines our target cells as ``BUF``, ``NOT``, ``NAND``,
+``NOR``, and ``DFF``.  Mapping between these is performed with the commands
+:cmd:ref:`dfflibmap` and :cmd:ref:`abc` as follows:
+
+.. literalinclude:: /code_examples/intro/counter.ys
+   :language: yoscrypt
+   :lines: 20-27
+   :lineno-match:
+   :caption: :file:`counter.ys` - mapping to hardware
+
+The final version of our ``counter`` module looks like this:
+
+.. figure:: /_images/code_examples/intro/counter_03.*
+   :class: width-helper invert-helper
+
+   ``counter`` after hardware cell mapping
+
+Before finally being output as a verilog file with :cmd:ref:`write_verilog`,
+which can then be loaded into another tool:
+
+.. literalinclude:: /code_examples/intro/counter.ys
+   :language: yoscrypt
+   :lines: 30-31
+   :lineno-match:
+   :caption: :file:`counter.ys` - write synthesized design
diff --git a/yosys/docs/source/using_yosys/synthesis/extract.rst b/yosys/docs/source/using_yosys/synthesis/extract.rst
new file mode 100644
index 00000000000..c9b76840e3b
--- /dev/null
+++ b/yosys/docs/source/using_yosys/synthesis/extract.rst
@@ -0,0 +1,231 @@
+The extract pass
+----------------
+
+- Like the :cmd:ref:`techmap` pass, the :cmd:ref:`extract` pass is called with a
+  map file. It compares the circuits inside the modules of the map file with the
+  design and looks for sub-circuits in the design that match any of the modules
+  in the map file.
+- If a match is found, the :cmd:ref:`extract` pass will replace the matching
+  subcircuit with an instance of the module from the map file.
+- In a way the :cmd:ref:`extract` pass is the inverse of the techmap pass.
+
+.. todo:: add/expand supporting text, also mention custom pattern matching and
+   pmgen
+
+Example code can be found in |code_examples/macc|_.
+
+.. |code_examples/macc| replace:: :file:`docs/source/code_examples/macc`
+.. _code_examples/macc: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/macc
+
+
+.. literalinclude:: /code_examples/macc/macc_simple_test.ys
+    :language: yoscrypt
+    :lines: 1-2
+
+.. figure:: /_images/code_examples/macc/macc_simple_test_00a.*
+    :class: width-helper invert-helper
+    
+    before :cmd:ref:`extract`
+
+.. literalinclude:: /code_examples/macc/macc_simple_test.ys
+    :language: yoscrypt
+    :lines: 6
+
+.. figure:: /_images/code_examples/macc/macc_simple_test_00b.*
+    :class: width-helper invert-helper
+    
+    after :cmd:ref:`extract`
+
+.. literalinclude:: /code_examples/macc/macc_simple_test.v
+   :language: verilog
+   :caption: :file:`macc_simple_test.v`
+
+.. literalinclude:: /code_examples/macc/macc_simple_xmap.v
+   :language: verilog
+   :caption: :file:`macc_simple_xmap.v`
+
+.. literalinclude:: /code_examples/macc/macc_simple_test_01.v
+   :language: verilog
+   :caption: :file:`macc_simple_test_01.v`
+
+.. figure:: /_images/code_examples/macc/macc_simple_test_01a.*
+    :class: width-helper invert-helper
+
+.. figure:: /_images/code_examples/macc/macc_simple_test_01b.*
+    :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/macc/macc_simple_test_02.v
+   :language: verilog
+   :caption: :file:`macc_simple_test_02.v`
+
+.. figure:: /_images/code_examples/macc/macc_simple_test_02a.*
+    :class: width-helper invert-helper
+
+.. figure:: /_images/code_examples/macc/macc_simple_test_02b.*
+    :class: width-helper invert-helper
+
+The wrap-extract-unwrap method
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Often a coarse-grain element has a constant bit-width, but can be used to
+implement operations with a smaller bit-width. For example, a 18x25-bit multiplier
+can also be used to implement 16x20-bit multiplication.
+
+A way of mapping such elements in coarse grain synthesis is the
+wrap-extract-unwrap method:
+
+wrap
+  Identify candidate-cells in the circuit and wrap them in a cell with a
+  constant wider bit-width using :cmd:ref:`techmap`. The wrappers use the same
+  parameters as the original cell, so the information about the original width
+  of the ports is preserved. Then use the :cmd:ref:`connwrappers` command to
+  connect up the bit-extended in- and outputs of the wrapper cells.
+
+extract
+  Now all operations are encoded using the same bit-width as the coarse grain
+  element. The :cmd:ref:`extract` command can be used to replace circuits with
+  cells of the target architecture.
+
+unwrap
+  The remaining wrapper cell can be unwrapped using :cmd:ref:`techmap`.
+
+Example: DSP48_MACC
+~~~~~~~~~~~~~~~~~~~
+
+This section details an example that shows how to map MACC operations of
+arbitrary size to MACC cells with a 18x25-bit multiplier and a 48-bit adder
+(such as the Xilinx DSP48 cells).
+
+Preconditioning: :file:`macc_xilinx_swap_map.v`
+
+Make sure ``A`` is the smaller port on all multipliers
+
+.. todo:: add/expand supporting text
+
+.. literalinclude:: /code_examples/macc/macc_xilinx_swap_map.v
+   :language: verilog
+   :caption: :file:`macc_xilinx_swap_map.v`
+
+Wrapping multipliers: :file:`macc_xilinx_wrap_map.v`
+
+.. literalinclude:: /code_examples/macc/macc_xilinx_wrap_map.v
+   :language: verilog
+   :lines: 1-46
+   :caption: :file:`macc_xilinx_wrap_map.v`
+
+Wrapping adders: :file:`macc_xilinx_wrap_map.v`
+
+.. literalinclude:: /code_examples/macc/macc_xilinx_wrap_map.v
+   :language: verilog
+   :lines: 48-89
+   :caption: :file:`macc_xilinx_wrap_map.v`
+
+Extract: :file:`macc_xilinx_xmap.v`
+
+.. literalinclude:: /code_examples/macc/macc_xilinx_xmap.v
+   :language: verilog
+   :caption: :file:`macc_xilinx_xmap.v`
+
+... simply use the same wrapping commands on this module as on the design to
+create a template for the :cmd:ref:`extract` command.
+
+Unwrapping multipliers: :file:`macc_xilinx_unwrap_map.v`
+
+.. literalinclude:: /code_examples/macc/macc_xilinx_unwrap_map.v
+   :language: verilog
+   :lines: 1-30
+   :caption: ``$__mul_wrapper`` module in :file:`macc_xilinx_unwrap_map.v`
+
+Unwrapping adders: :file:`macc_xilinx_unwrap_map.v`
+
+.. literalinclude:: /code_examples/macc/macc_xilinx_unwrap_map.v
+   :language: verilog
+   :lines: 32-61
+   :caption: ``$__add_wrapper`` module in :file:`macc_xilinx_unwrap_map.v`
+
+.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
+   :language: verilog
+   :lines: 1-6
+   :caption: ``test1`` of :file:`macc_xilinx_test.v`
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test1a.*
+    :class: width-helper invert-helper
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test1b.*
+    :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
+   :language: verilog
+   :lines: 8-13
+   :caption: ``test2`` of :file:`macc_xilinx_test.v`
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test2a.*
+    :class: width-helper invert-helper
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test2b.*
+    :class: width-helper invert-helper
+
+Wrapping in ``test1``:
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test1b.*
+    :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
+    :language: yoscrypt
+    :start-after: part c
+    :end-before: end part c
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
+    :class: width-helper invert-helper
+
+Wrapping in ``test2``:
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test2b.*
+    :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
+    :language: yoscrypt
+    :start-after: part c
+    :end-before: end part c
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
+    :class: width-helper invert-helper
+
+Extract in ``test1``:
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
+    :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
+    :language: yoscrypt
+    :start-after: part d
+    :end-before: end part d
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test1d.*
+    :class: width-helper invert-helper
+
+Extract in ``test2``:
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
+    :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
+    :language: yoscrypt
+    :start-after: part d
+    :end-before: end part d
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
+    :class: width-helper invert-helper
+
+Unwrap in ``test2``:
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
+    :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
+    :language: yoscrypt
+    :start-after: part e
+    :end-before: end part e
+
+.. figure:: /_images/code_examples/macc/macc_xilinx_test2e.*
+    :class: width-helper invert-helper
\ No newline at end of file
diff --git a/yosys/docs/source/using_yosys/synthesis/fsm.rst b/yosys/docs/source/using_yosys/synthesis/fsm.rst
new file mode 100644
index 00000000000..e1ed5513397
--- /dev/null
+++ b/yosys/docs/source/using_yosys/synthesis/fsm.rst
@@ -0,0 +1,142 @@
+FSM handling
+============
+
+The :cmd:ref:`fsm` command identifies, extracts, optimizes (re-encodes), and
+re-synthesizes finite state machines. It again is a macro that calls a series of
+other commands:
+
+.. literalinclude:: /code_examples/macro_commands/fsm.ys
+   :language: yoscrypt
+   :start-after: #end:
+   :caption: Passes called by :cmd:ref:`fsm`
+
+See also :doc:`/cmd/fsm`.
+
+The algorithms used for FSM detection and extraction are influenced by a more
+general reported technique :cite:p:`fsmextract`.
+
+FSM detection
+~~~~~~~~~~~~~
+
+The :cmd:ref:`fsm_detect` pass identifies FSM state registers. It sets the
+``\fsm_encoding = "auto"`` attribute on any (multi-bit) wire that matches the
+following description:
+
+-  Does not already have the ``\fsm_encoding`` attribute.
+-  Is not an output of the containing module.
+-  Is driven by single ``$dff`` or ``$adff`` cell.
+-  The ``\D``-Input of this ``$dff`` or ``$adff`` cell is driven by a
+   multiplexer tree that only has constants or the old state value on its
+   leaves.
+-  The state value is only used in the said multiplexer tree or by simple
+   relational cells that compare the state value to a constant (usually ``$eq``
+   cells).
+
+This heuristic has proven to work very well. It is possible to overwrite it by
+setting ``\fsm_encoding = "auto"`` on registers that should be considered FSM
+state registers and setting ``\fsm_encoding = "none"`` on registers that match
+the above criteria but should not be considered FSM state registers.
+
+Note however that marking state registers with ``\fsm_encoding`` that are not
+suitable for FSM recoding can cause synthesis to fail or produce invalid
+results.
+
+FSM extraction
+~~~~~~~~~~~~~~
+
+The :cmd:ref:`fsm_extract` pass operates on all state signals marked with the
+(``\fsm_encoding != "none"``) attribute. For each state signal the following
+information is determined:
+
+-  The state registers
+
+-  The asynchronous reset state if the state registers use asynchronous reset
+
+-  All states and the control input signals used in the state transition
+   functions
+
+-  The control output signals calculated from the state signals and control
+   inputs
+
+-  A table of all state transitions and corresponding control inputs- and
+   outputs
+
+The state registers (and asynchronous reset state, if applicable) is simply
+determined by identifying the driver for the state signal.
+
+From there the ``$mux-tree`` driving the state register inputs is recursively
+traversed. All select inputs are control signals and the leaves of the
+``$mux-tree`` are the states. The algorithm fails if a non-constant leaf that is
+not the state signal itself is found.
+
+The list of control outputs is initialized with the bits from the state signal.
+It is then extended by adding all values that are calculated by cells that
+compare the state signal with a constant value.
+
+In most cases this will cover all uses of the state register, thus rendering the
+state encoding arbitrary. If however a design uses e.g. a single bit of the
+state value to drive a control output directly, this bit of the state signal
+will be transformed to a control output of the same value.
+
+Finally, a transition table for the FSM is generated. This is done by using the
+ConstEval C++ helper class (defined in kernel/consteval.h) that can be used to
+evaluate parts of the design. The ConstEval class can be asked to calculate a
+given set of result signals using a set of signal-value assignments. It can also
+be passed a list of stop-signals that abort the ConstEval algorithm if the value
+of a stop-signal is needed in order to calculate the result signals.
+
+The :cmd:ref:`fsm_extract` pass uses the ConstEval class in the following way to
+create a transition table. For each state:
+
+1. Create a ConstEval object for the module containing the FSM
+2. Add all control inputs to the list of stop signals
+3. Set the state signal to the current state
+4. Try to evaluate the next state and control output
+5. If step 4 was not successful:
+   
+   -  Recursively goto step 4 with the offending stop-signal set to 0.
+   -  Recursively goto step 4 with the offending stop-signal set to 1.
+
+6. If step 4 was successful: Emit transition
+
+Finally a ``$fsm`` cell is created with the generated transition table and added
+to the module. This new cell is connected to the control signals and the old
+drivers for the control outputs are disconnected.
+
+FSM optimization
+~~~~~~~~~~~~~~~~
+
+The :cmd:ref:`fsm_opt` pass performs basic optimizations on ``$fsm`` cells (not
+including state recoding). The following optimizations are performed (in this
+order):
+
+-  Unused control outputs are removed from the ``$fsm`` cell. The attribute
+   ``\unused_bits`` (that is usually set by the :cmd:ref:`opt_clean` pass) is
+   used to determine which control outputs are unused.
+
+-  Control inputs that are connected to the same driver are merged.
+
+-  When a control input is driven by a control output, the control input is
+   removed and the transition table altered to give the same performance without
+   the external feedback path.
+
+-  Entries in the transition table that yield the same output and only differ in
+   the value of a single control input bit are merged and the different bit is
+   removed from the sensitivity list (turned into a don't-care bit).
+
+-  Constant inputs are removed and the transition table is altered to give an
+   unchanged behaviour.
+
+-  Unused inputs are removed.
+
+FSM recoding
+~~~~~~~~~~~~
+
+The :cmd:ref:`fsm_recode` pass assigns new bit pattern to the states. Usually
+this also implies a change in the width of the state signal. At the moment of
+this writing only one-hot encoding with all-zero for the reset state is
+supported.
+
+The :cmd:ref:`fsm_recode` pass can also write a text file with the changes
+performed by it that can be used when verifying designs synthesized by Yosys
+using Synopsys Formality.
diff --git a/yosys/docs/source/using_yosys/synthesis/index.rst b/yosys/docs/source/using_yosys/synthesis/index.rst
new file mode 100644
index 00000000000..c00a940daa6
--- /dev/null
+++ b/yosys/docs/source/using_yosys/synthesis/index.rst
@@ -0,0 +1,35 @@
+Synthesis in detail
+-------------------
+
+Synthesis can generally be broken down into coarse-grain synthesis, and
+fine-grain synthesis.  We saw this in :doc:`/getting_started/example_synth`
+where a design was loaded and elaborated and then went through a series of
+coarse-grain optimizations before being mapped to hard blocks and fine-grain
+cells.  Most commands in Yosys will target either coarse-grain representation or
+fine-grain representation, with only a select few compatible with both states.
+
+Commands such as :cmd:ref:`proc`, :cmd:ref:`fsm`, and :cmd:ref:`memory` rely on
+the additional information in the coarse-grain representation, along with a
+number of optimizations such as :cmd:ref:`wreduce`, :cmd:ref:`share`, and
+:cmd:ref:`alumacc`.  :cmd:ref:`opt` provides optimizations which are useful in
+both states, while :cmd:ref:`techmap` is used to convert coarse-grain cells
+to the corresponding fine-grain representation.
+
+Single-bit cells (logic gates, FFs) as well as LUTs, half-adders, and
+full-adders make up the bulk of the fine-grain representation and are necessary
+for commands such as :cmd:ref:`abc`\ /:cmd:ref:`abc9`, :cmd:ref:`simplemap`,
+:cmd:ref:`dfflegalize`, and :cmd:ref:`memory_map`.
+
+.. toctree::
+   :maxdepth: 3
+
+   synth
+   proc
+   fsm
+   memory
+   opt
+   techmap_synth
+   extract
+   abc
+   cell_libs
+
diff --git a/yosys/docs/source/CHAPTER_Memorymap.rst b/yosys/docs/source/using_yosys/synthesis/memory.rst
similarity index 81%
rename from yosys/docs/source/CHAPTER_Memorymap.rst
rename to yosys/docs/source/using_yosys/synthesis/memory.rst
index cdc381eed81..0f5e1bd3010 100644
--- a/yosys/docs/source/CHAPTER_Memorymap.rst
+++ b/yosys/docs/source/using_yosys/synthesis/memory.rst
@@ -1,19 +1,111 @@
-.. _chapter:memorymap:
+Memory handling
+===============
+
+The :cmd:ref:`memory` command
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+In the RTL netlist, memory reads and writes are individual cells. This makes
+consolidating the number of ports for a memory easier. The :cmd:ref:`memory`
+pass transforms memories to an implementation. Per default that is logic for
+address decoders and registers. It also is a macro command that calls the other
+common ``memory_*`` passes in a sensible order:
+
+.. literalinclude:: /code_examples/macro_commands/memory.ys
+   :language: yoscrypt
+   :start-after: #end:
+   :caption: Passes called by :cmd:ref:`memory`
+
+.. todo:: Make ``memory_*`` notes less quick
+
+Some quick notes:
+
+-  :cmd:ref:`memory_dff` merges registers into the memory read- and write cells.
+-  :cmd:ref:`memory_collect` collects all read and write cells for a memory and
+   transforms them into one multi-port memory cell.
+-  :cmd:ref:`memory_map` takes the multi-port memory cell and transforms it to
+   address decoder logic and registers.
+
+For more information about :cmd:ref:`memory`, such as disabling certain sub
+commands, see :doc:`/cmd/memory`.
+
+Example
+-------
+
+.. todo:: describe ``memory`` images
+
+|code_examples/synth_flow|_.
+
+.. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
+.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
+
+.. figure:: /_images/code_examples/synth_flow/memory_01.*
+   :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/synth_flow/memory_01.ys
+   :language: yoscrypt
+   :caption: :file:`memory_01.ys`
+
+.. literalinclude:: /code_examples/synth_flow/memory_01.v
+   :language: verilog
+   :caption: :file:`memory_01.v`
+
+.. figure:: /_images/code_examples/synth_flow/memory_02.*
+   :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/synth_flow/memory_02.v
+   :language: verilog
+   :caption: :file:`memory_02.v`
+
+.. literalinclude:: /code_examples/synth_flow/memory_02.ys
+   :language: yoscrypt
+   :caption: :file:`memory_02.ys`
+
+.. _memory_map:
 
 Memory mapping
-==============
+^^^^^^^^^^^^^^
+
+Usually it is preferred to use architecture-specific RAM resources for memory.
+For example:
+
+.. code-block:: yoscrypt
+
+    memory -nomap
+    memory_libmap -lib my_memory_map.txt
+    techmap -map my_memory_map.v
+    memory_map
+
+:cmd:ref:`memory_libmap` attempts to convert memory cells (``$mem_v2`` etc) into
+hardware supported memory using a provided library (:file:`my_memory_map.txt` in the
+example above).  Where necessary, emulation logic is added to ensure functional
+equivalence before and after this conversion. :yoscrypt:`techmap -map
+my_memory_map.v` then uses :cmd:ref:`techmap` to map to hardware primitives. Any
+leftover memory cells unable to be converted are then picked up by
+:cmd:ref:`memory_map` and mapped to DFFs and address decoders.
 
-Documentation for the Yosys ``memory_libmap`` memory mapper.  Note that not all supported patterns
-are included in this document, of particular note is that combinations of multiple patterns should
-generally work.  For example, `Write port with byte enables`_ could be used in conjunction with any
-of the simple dual port (SDP) models.  In general if a hardware memory definition does not support a
-given configuration, additional logic will be instantiated to guarantee behaviour is consistent with
-simulation.
+.. note::
 
-See also: `passes/memory/memlib.md <https://github.com/YosysHQ/yosys/blob/master/passes/memory/memlib.md>`_
+   More information about what mapping options are available and associated
+   costs of each can be found by enabling debug outputs.  This can be done with
+   the :cmd:ref:`debug` command, or by using the ``-g`` flag when calling Yosys
+   to globally enable debug messages.
 
-Additional notes
-----------------
+For more on the lib format for :cmd:ref:`memory_libmap`, see
+`passes/memory/memlib.md
+<https://github.com/YosysHQ/yosys/blob/main/passes/memory/memlib.md>`_
+
+Supported memory patterns
+^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Note that not all supported patterns are included in this document, of
+particular note is that combinations of multiple patterns should generally work.
+For example, `wbe`_ could be used in conjunction with any of the simple dual
+port (SDP) models.  In general if a hardware memory definition does not support
+a given configuration, additional logic will be instantiated to guarantee
+behaviour is consistent with simulation.
+
+Notes
+-----
 
 Memory kind selection
 ~~~~~~~~~~~~~~~~~~~~~
@@ -94,7 +186,9 @@ Initial data
 Most FPGA targets support initializing all kinds of memory to user-provided values.  If explicit
 initialization is not used the initial memory value is undefined.  Initial data can be provided by
 either initial statements writing memory cells one by one of ``$readmemh`` or ``$readmemb`` system
-tasks.  For an example pattern, see `Synchronous read port with initial value`_.
+tasks.  For an example pattern, see `sr_init`_.
+
+.. _wbe:
 
 Write port with byte enables
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -127,6 +221,8 @@ Write port with byte enables
 Simple dual port (SDP) memory patterns
 --------------------------------------
 
+.. todo:: assorted enables, e.g. cen, wen+ren
+
 Asynchronous-read SDP
 ~~~~~~~~~~~~~~~~~~~~~
 
@@ -180,6 +276,8 @@ Synchronous SDP read first
 			read_data <= mem[read_addr];
 	end
 
+.. _no_rw_check:
+
 Synchronous SDP with undefined collision behavior
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -197,8 +295,8 @@ Synchronous SDP with undefined collision behavior
 		if (read_enable) begin
 			read_data <= mem[read_addr];
 		
-		// 👇 this if block 👇
 		if (write_enable && read_addr == write_addr)
+			// this if block
 			read_data <= 'x;
 		end
 	end
@@ -218,6 +316,8 @@ Synchronous SDP with undefined collision behavior
 			read_data <= mem[read_addr];
 	end
 
+.. _sdp_wf:
+
 Synchronous SDP with write-first behavior
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -247,6 +347,7 @@ Synchronous SDP with write-first behavior (alternate pattern)
 
 .. code:: verilog
 
+	reg [ADDR_WIDTH - 1 : 0] read_addr_reg;
 	reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
 
 	always @(posedge clk) begin
@@ -333,6 +434,8 @@ Synchronous single-port RAM with write-first behavior
 				read_data <= mem[addr];
 	end
 
+.. _sr_init:
+
 Synchronous read port with initial value
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -373,7 +476,7 @@ Synchronous reset, reset priority over enable
 			mem[write_addr] <= write_data;
 
 		if (read_reset)
-			read_data <= {sval};
+			read_data <= 'h1234;
 		else if (read_enable)
 			read_data <= mem[read_addr];
 	end
@@ -407,8 +510,8 @@ Synchronous read port with asynchronous reset
 			mem[write_addr] <= write_data;
 	end
 
-	always @(posedge clk, posedge reset_read) begin
-		if (reset_read)
+	always @(posedge clk, posedge read_reset) begin
+		if (read_reset)
 			read_data <= 'h1234;
 		else if (read_enable)
 			read_data <= mem[read_addr];
@@ -434,6 +537,8 @@ Asymmetric memory is supported on all targets, but may require emulation circuit
 natively supported.  Note that when the memory is larger than the underlying block RAM primitive,
 hardware asymmetric memory support is likely not to be used even if present as it is more expensive.
 
+.. _wide_sr:
+
 Wide synchronous read port
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -589,14 +694,14 @@ TDP with multiple read ports
 	assign read_data_b = mem[read_addr_b];
 	assign read_data_c = mem[read_addr_c];
 
-Not yet supported patterns
---------------------------
+Patterns only supported with Verific
+------------------------------------
 
 Synchronous SDP with write-first behavior via blocking assignments
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-- Would require modifications to the Yosys Verilog frontend.
-- Use `Synchronous SDP with write-first behavior`_ instead
+- Use `sdp_wf`_ for compatibility with Yosys
+  Verilog frontend.
 
 .. code:: verilog
 
@@ -613,8 +718,8 @@ Synchronous SDP with write-first behavior via blocking assignments
 Asymmetric memories via part selection
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-- Would require major changes to the Verilog frontend.
-- Build wide ports out of narrow ports instead (see `Wide synchronous read port`_)
+- Build wide ports out of narrow ports instead (see `wide_sr`_) for
+  compatibility with Yosys Verilog frontend.
 
 .. code:: verilog
 
diff --git a/yosys/docs/source/using_yosys/synthesis/opt.rst b/yosys/docs/source/using_yosys/synthesis/opt.rst
new file mode 100644
index 00000000000..2a06aadd118
--- /dev/null
+++ b/yosys/docs/source/using_yosys/synthesis/opt.rst
@@ -0,0 +1,230 @@
+Optimization passes
+===================
+
+Yosys employs a number of optimizations to generate better and cleaner results.
+This chapter outlines these optimizations.
+
+.. todo:: "outlines these optimizations" or "outlines *some*.."?
+
+The :cmd:ref:`opt` macro command
+--------------------------------
+
+The Yosys pass :cmd:ref:`opt` runs a number of simple optimizations. This
+includes removing unused signals and cells and const folding. It is recommended
+to run this pass after each major step in the synthesis script.  As listed in
+:doc:`/cmd/opt`, this macro command calls the following ``opt_*`` commands:
+
+.. literalinclude:: /code_examples/macro_commands/opt.ys
+   :language: yoscrypt
+   :start-after: #end:
+   :caption: Passes called by :cmd:ref:`opt`
+
+.. _adv_opt_expr:
+
+Constant folding and simple expression rewriting - :cmd:ref:`opt_expr`
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. todo:: unsure if this is too much detail and should be in :doc:`/yosys_internals/index`
+
+This pass performs constant folding on the internal combinational cell types
+described in :doc:`/yosys_internals/formats/cell_library`. This means a cell
+with all constant inputs is replaced with the constant value this cell drives.
+In some cases this pass can also optimize cells with some constant inputs.
+
+.. table:: Const folding rules for ``$_AND_`` cells as used in :cmd:ref:`opt_expr`.
+   :name: tab:opt_expr_and
+   :align: center
+
+   ========= ========= ===========
+   A-Input   B-Input   Replacement
+   ========= ========= ===========
+   any       0         0
+   0         any       0
+   1         1         1
+   --------- --------- -----------
+   X/Z       X/Z       X
+   1         X/Z       X
+   X/Z       1         X
+   --------- --------- -----------
+   any       X/Z       0
+   X/Z       any       0
+   --------- --------- -----------
+   :math:`a` 1         :math:`a`
+   1         :math:`b` :math:`b`
+   ========= ========= ===========
+
+:numref:`Table %s <tab:opt_expr_and>` shows the replacement rules used for
+optimizing an ``$_AND_`` gate. The first three rules implement the obvious const
+folding rules. Note that 'any' might include dynamic values calculated by other
+parts of the circuit. The following three lines propagate undef (X) states.
+These are the only three cases in which it is allowed to propagate an undef
+according to Sec. 5.1.10 of IEEE Std. 1364-2005 :cite:p:`Verilog2005`.
+
+The next two lines assume the value 0 for undef states. These two rules are only
+used if no other substitutions are possible in the current module. If other
+substitutions are possible they are performed first, in the hope that the 'any'
+will change to an undef value or a 1 and therefore the output can be set to
+undef.
+
+The last two lines simply replace an ``$_AND_`` gate with one constant-1 input
+with a buffer.
+
+Besides this basic const folding the :cmd:ref:`opt_expr` pass can replace 1-bit
+wide ``$eq`` and ``$ne`` cells with buffers or not-gates if one input is
+constant.  Equality checks may also be reduced in size if there are redundant
+bits in the arguments (i.e. bits which are constant on both inputs).  This can,
+for example, result in a 32-bit wide constant like ``255`` being reduced to the
+8-bit value of ``8'11111111`` if the signal being compared is only 8-bit as in
+:ref:`addr_gen_clean` of :doc:`/getting_started/example_synth`.
+
+The :cmd:ref:`opt_expr` pass is very conservative regarding optimizing ``$mux``
+cells, as these cells are often used to model decision-trees and breaking these
+trees can interfere with other optimizations.
+
+.. literalinclude:: /code_examples/opt/opt_expr.ys
+   :language: Verilog
+   :start-after: read_verilog <<EOT
+   :end-before: EOT
+   :caption: example verilog for demonstrating :cmd:ref:`opt_expr`
+
+.. figure:: /_images/code_examples/opt/opt_expr.*
+   :class: width-helper invert-helper
+
+   Before and after :cmd:ref:`opt_expr`
+
+Merging identical cells - :cmd:ref:`opt_merge`
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This pass performs trivial resource sharing. This means that this pass
+identifies cells with identical inputs and replaces them with a single instance
+of the cell.
+
+The option ``-nomux`` can be used to disable resource sharing for multiplexer
+cells (``$mux`` and ``$pmux``.) This can be useful as it prevents multiplexer
+trees to be merged, which might prevent :cmd:ref:`opt_muxtree` to identify
+possible optimizations.
+
+.. literalinclude:: /code_examples/opt/opt_merge.ys
+   :language: Verilog
+   :start-after: read_verilog <<EOT
+   :end-before: EOT
+   :caption: example verilog for demonstrating :cmd:ref:`opt_merge`
+
+.. figure:: /_images/code_examples/opt/opt_merge.*
+   :class: width-helper invert-helper
+
+   Before and after :cmd:ref:`opt_merge`
+
+Removing never-active branches from multiplexer tree - :cmd:ref:`opt_muxtree`
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This pass optimizes trees of multiplexer cells by analyzing the select inputs.
+Consider the following simple example:
+
+.. literalinclude:: /code_examples/opt/opt_muxtree.ys
+   :language: Verilog
+   :start-after: read_verilog <<EOT
+   :end-before: EOT
+   :caption: example verilog for demonstrating :cmd:ref:`opt_muxtree`
+
+The output can never be ``c``, as this would require ``a`` to be 1 for the outer
+multiplexer and 0 for the inner multiplexer. The :cmd:ref:`opt_muxtree` pass
+detects this contradiction and replaces the inner multiplexer with a constant 1,
+yielding the logic for ``y = a ? b : d``.
+
+.. figure:: /_images/code_examples/opt/opt_muxtree.*
+   :class: width-helper invert-helper
+
+   Before and after :cmd:ref:`opt_muxtree`
+
+Simplifying large MUXes and AND/OR gates - :cmd:ref:`opt_reduce`
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This is a simple optimization pass that identifies and consolidates identical
+input bits to ``$reduce_and`` and ``$reduce_or`` cells. It also sorts the input
+bits to ease identification of shareable ``$reduce_and`` and ``$reduce_or``
+cells in other passes.
+
+This pass also identifies and consolidates identical inputs to multiplexer
+cells. In this case the new shared select bit is driven using a ``$reduce_or``
+cell that combines the original select bits.
+
+Lastly this pass consolidates trees of ``$reduce_and`` cells and trees of
+``$reduce_or`` cells to single large ``$reduce_and`` or ``$reduce_or`` cells.
+
+These three simple optimizations are performed in a loop until a stable result
+is produced.
+
+Merging mutually exclusive cells with shared inputs - :cmd:ref:`opt_share`
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This pass identifies mutually exclusive cells of the same type that:
+   a. share an input signal, and
+   b. drive the same ``$mux``, ``$_MUX_``, or ``$pmux`` multiplexing cell,
+
+allowing the cell to be merged and the multiplexer to be moved from
+multiplexing its output to multiplexing the non-shared input signals.
+
+.. literalinclude:: /code_examples/opt/opt_share.ys
+   :language: Verilog
+   :start-after: read_verilog <<EOT
+   :end-before: EOT
+   :caption: example verilog for demonstrating :cmd:ref:`opt_share`
+
+.. figure:: /_images/code_examples/opt/opt_share.*
+   :class: width-helper invert-helper
+
+   Before and after :cmd:ref:`opt_share`
+
+When running :cmd:ref:`opt` in full, the original ``$mux`` (labeled ``$3``) is
+optimized away by :cmd:ref:`opt_expr`.
+
+Performing DFF optimizations - :cmd:ref:`opt_dff`
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This pass identifies single-bit d-type flip-flops (``$_DFF_``, ``$dff``, and
+``$adff`` cells) with a constant data input and replaces them with a constant
+driver.  It can also merge clock enables and synchronous reset multiplexers,
+removing unused control inputs.
+
+Called with ``-nodffe`` and ``-nosdff``, this pass is used to prepare a design
+for :doc:`/using_yosys/synthesis/fsm`.
+
+Removing unused cells and wires - :cmd:ref:`opt_clean` pass
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This pass identifies unused signals and cells and removes them from the design.
+It also creates an ``\unused_bits`` attribute on wires with unused bits. This
+attribute can be used for debugging or by other optimization passes.
+
+When to use :cmd:ref:`opt` or :cmd:ref:`clean`
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Usually it does not hurt to call :cmd:ref:`opt` after each regular command in
+the synthesis script. But it increases the synthesis time, so it is favourable
+to only call :cmd:ref:`opt` when an improvement can be achieved.
+
+It is generally a good idea to call :cmd:ref:`opt` before inherently expensive
+commands such as :cmd:ref:`sat` or :cmd:ref:`freduce`, as the possible gain is
+much higher in these cases as the possible loss.
+
+The :cmd:ref:`clean` command, which is an alias for :cmd:ref:`opt_clean` with
+fewer outputs, on the other hand is very fast and many commands leave a mess
+(dangling signal wires, etc). For example, most commands do not remove any wires
+or cells. They just change the connections and depend on a later call to clean
+to get rid of the now unused objects. So the occasional ``;;``, which itself is
+an alias for :cmd:ref:`clean`, is a good idea in every synthesis script, e.g:
+
+.. code-block:: yoscrypt
+
+   hierarchy; proc; opt; memory; opt_expr;; fsm;;
+
+Other optimizations
+-------------------
+
+.. todo:: more on the other optimizations
+
+- :doc:`/cmd/wreduce`
+- :doc:`/cmd/peepopt`
+- :doc:`/cmd/share`
+- :cmd:ref:`abc` and :cmd:ref:`abc9`, see also: :doc:`abc`.
diff --git a/yosys/docs/source/using_yosys/synthesis/proc.rst b/yosys/docs/source/using_yosys/synthesis/proc.rst
new file mode 100644
index 00000000000..d90aa087dc7
--- /dev/null
+++ b/yosys/docs/source/using_yosys/synthesis/proc.rst
@@ -0,0 +1,67 @@
+Converting process blocks
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. role:: yoscrypt(code)
+   :language: yoscrypt
+
+The Verilog frontend converts ``always``-blocks to RTL netlists for the
+expressions and "processess" for the control- and memory elements. The
+:cmd:ref:`proc` command then transforms these "processess" to netlists of RTL
+multiplexer and register cells. It also is a macro command that calls the other
+``proc_*`` commands in a sensible order:
+
+.. literalinclude:: /code_examples/macro_commands/proc.ys
+   :language: yoscrypt
+   :start-after: #end:
+   :caption: Passes called by :cmd:ref:`proc`
+
+After all the ``proc_*`` commands, :cmd:ref:`opt_expr` is called. This can be
+disabled by calling :yoscrypt:`proc -noopt`.  For more information about
+:cmd:ref:`proc`, such as disabling certain sub commands, see :doc:`/cmd/proc`.
+
+Many commands can not operate on modules with "processess" in them. Usually a
+call to :cmd:ref:`proc` is the first command in the actual synthesis procedure
+after design elaboration.
+
+Example
+^^^^^^^
+
+.. todo:: describe ``proc`` images
+
+|code_examples/synth_flow|_.
+
+.. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
+.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
+
+.. literalinclude:: /code_examples/synth_flow/proc_01.v
+   :language: verilog
+   :caption: :file:`proc_01.v`
+
+.. literalinclude:: /code_examples/synth_flow/proc_01.ys
+   :language: yoscrypt
+   :caption: :file:`proc_01.ys`
+
+.. figure:: /_images/code_examples/synth_flow/proc_01.*
+   :class: width-helper invert-helper
+
+.. figure:: /_images/code_examples/synth_flow/proc_02.*
+   :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/synth_flow/proc_02.v
+   :language: verilog
+   :caption: :file:`proc_02.v`
+
+.. literalinclude:: /code_examples/synth_flow/proc_02.ys
+   :language: yoscrypt
+   :caption: :file:`proc_02.ys`
+
+.. figure:: /_images/code_examples/synth_flow/proc_03.*
+   :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/synth_flow/proc_03.ys
+   :language: yoscrypt
+   :caption: :file:`proc_03.ys`
+
+.. literalinclude:: /code_examples/synth_flow/proc_03.v
+   :language: verilog
+   :caption: :file:`proc_03.v`
diff --git a/yosys/docs/source/using_yosys/synthesis/synth.rst b/yosys/docs/source/using_yosys/synthesis/synth.rst
new file mode 100644
index 00000000000..cba7db1a7a9
--- /dev/null
+++ b/yosys/docs/source/using_yosys/synthesis/synth.rst
@@ -0,0 +1,49 @@
+Synth commands
+--------------
+
+.. todo:: comment on common ``synth_*`` options, like ``-run``
+
+Packaged ``synth_*`` commands
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The following is a list of all synth commands included in Yosys for different
+platforms.  Each command runs a script of sub commands specific to the platform
+being targeted.  Note that not all of these scripts are actively maintained and
+may not be up-to-date.
+
+- :doc:`/cmd/synth_achronix`
+- :doc:`/cmd/synth_anlogic`
+- :doc:`/cmd/synth_coolrunner2`
+- :doc:`/cmd/synth_easic`
+- :doc:`/cmd/synth_ecp5`
+- :doc:`/cmd/synth_efinix`
+- :doc:`/cmd/synth_fabulous`
+- :doc:`/cmd/synth_gatemate`
+- :doc:`/cmd/synth_gowin`
+- :doc:`/cmd/synth_greenpak4`
+- :doc:`/cmd/synth_ice40`
+- :doc:`/cmd/synth_intel` (MAX10, Cyclone IV)
+- :doc:`/cmd/synth_intel_alm` (Cyclone V, Arria V, Cyclone 10 GX)
+- :doc:`/cmd/synth_lattice`
+- :doc:`/cmd/synth_nexus`
+- :doc:`/cmd/synth_quicklogic`
+- :doc:`/cmd/synth_sf2`
+- :doc:`/cmd/synth_xilinx`
+
+General synthesis
+~~~~~~~~~~~~~~~~~
+
+In addition to the above hardware-specific synth commands, there is also
+:doc:`/cmd/prep`.  This command is limited to coarse-grain synthesis, without
+getting into any architecture-specific mappings or optimizations.  Among other
+things, this is useful for design verification.
+
+The following commands are executed by the :cmd:ref:`prep` command:
+
+.. literalinclude:: /cmd/prep.rst
+   :start-at: begin:
+   :end-before: .. raw:: latex
+   :dedent:
+
+:doc:`/getting_started/example_synth` covers most of these commands and what
+they do.
diff --git a/yosys/docs/source/CHAPTER_Techmap.rst b/yosys/docs/source/using_yosys/synthesis/techmap_synth.rst
similarity index 89%
rename from yosys/docs/source/CHAPTER_Techmap.rst
rename to yosys/docs/source/using_yosys/synthesis/techmap_synth.rst
index 6cd1eb44f39..dc9d8b1954b 100644
--- a/yosys/docs/source/CHAPTER_Techmap.rst
+++ b/yosys/docs/source/using_yosys/synthesis/techmap_synth.rst
@@ -1,8 +1,8 @@
-.. _chapter:techmap:
-
 Technology mapping 
 ==================
 
+.. todo:: less academic, check text is coherent
+
 Previous chapters outlined how HDL code is transformed into an RTL netlist. The
 RTL netlist is still based on abstract coarse-grain cell types like arbitrary
 width adders and even multipliers. This chapter covers how an RTL netlist is
@@ -10,8 +10,8 @@ transformed into a functionally equivalent netlist utilizing the cell types
 available in the target architecture.
 
 Technology mapping is often performed in two phases. In the first phase RTL
-cells are mapped to an internal library of single-bit cells (see :numref:`Sec.
-%s <sec:celllib_gates>`). In the second phase this netlist of internal gate
+cells are mapped to an internal library of single-bit cells (see
+:ref:`sec:celllib_gates`). In the second phase this netlist of internal gate
 types is transformed to a netlist of gates from the target technology library.
 
 When the target architecture provides coarse-grain cells (such as block ram or
@@ -29,11 +29,11 @@ provided implementation.
 
 When no map file is provided, techmap uses a built-in map file that maps the
 Yosys RTL cell types to the internal gate library used by Yosys. The curious
-reader may find this map file as techlibs/common/techmap.v in the Yosys source
+reader may find this map file as `techlibs/common/techmap.v` in the Yosys source
 tree.
 
 Additional features have been added to techmap to allow for conditional mapping
-of cells (see :doc:`cmd/techmap`). This can for example be useful if the target
+of cells (see :doc:`/cmd/techmap`). This can for example be useful if the target
 architecture supports hardware multipliers for certain bit-widths but not for
 others.
 
@@ -52,14 +52,14 @@ cell type but only combinations of cells.
 
 For these cases Yosys provides the extract pass that can match a given set of
 modules against a design and identify the portions of the design that are
-identical (i.e. isomorphic subcircuits) to any of the given modules. These
+identical (i.e. isomorphic subcircuits) to any of the given modules. These
 matched subcircuits are then replaced by instances of the given modules.
 
 The extract pass also finds basic variations of the given modules, such as
 swapped inputs on commutative cell types.
 
 In addition to this the extract pass also has limited support for frequent
-subcircuit mining, i.e. the process of finding recurring subcircuits in the
+subcircuit mining, i.e. the process of finding recurring subcircuits in the
 design. This has a few applications, including the design of new coarse-grain
 architectures :cite:p:`intersynthFdlBookChapter`.
 
@@ -73,11 +73,13 @@ SubCircuit library that can also be used stand-alone without Yosys (see
 Gate-level technology mapping
 -----------------------------
 
+.. todo:: newer techmap libraries appear to be largely ``.v`` instead of ``.lib``
+
 On the gate-level the target architecture is usually described by a "Liberty
 file". The Liberty file format is an industry standard format that can be used
 to describe the behaviour and other properties of standard library cells .
 
-Mapping a design utilizing the Yosys internal gate library (e.g. as a result of
+Mapping a design utilizing the Yosys internal gate library (e.g. as a result of
 mapping it to this representation using the techmap pass) is performed in two
 phases.
 
diff --git a/yosys/docs/source/yosys_internals/extending_yosys/abc_flow.rst b/yosys/docs/source/yosys_internals/extending_yosys/abc_flow.rst
new file mode 100644
index 00000000000..86afd3336f6
--- /dev/null
+++ b/yosys/docs/source/yosys_internals/extending_yosys/abc_flow.rst
@@ -0,0 +1,76 @@
+Setting up a flow for ABC9
+--------------------------
+
+Much of the configuration comes from attributes and ``specify`` blocks in
+Verilog simulation models.
+
+``specify`` syntax
+~~~~~~~~~~~~~~~~~~
+
+Since ``specify`` is a relatively obscure part of the Verilog standard, a quick
+guide to the syntax:
+
+.. code-block:: verilog
+
+   specify                           // begins a specify block
+     (A => B) = 123;                 // simple combinational path from A to B with a delay of 123.
+     (A *> B) = 123;                 // simple combinational path from A to all bits of B with a delay of 123 for all.
+     if (FOO) (A => B) = 123;        // paths may apply under specific conditions.
+     (posedge CLK => (Q : D)) = 123; // combinational path triggered on the positive edge of CLK; used for clock-to-Q arrival paths.
+     $setup(A, posedge CLK, 123);    // setup constraint for an input relative to a clock.
+   endspecify                        // ends a specify block
+
+By convention, all delays in ``specify`` blocks are in integer picoseconds.
+Files containing ``specify`` blocks should be read with the ``-specify`` option
+to :cmd:ref:`read_verilog` so that they aren't skipped.
+
+LUTs
+^^^^
+
+LUTs need to be annotated with an ``(* abc9_lut=N *)`` attribute, where ``N`` is
+the relative area of that LUT model. For example, if an architecture can combine
+LUTs to produce larger LUTs, then the combined LUTs would have increasingly
+larger ``N``. Conversely, if an architecture can split larger LUTs into smaller
+LUTs, then the smaller LUTs would have smaller ``N``.
+
+LUTs are generally specified with simple combinational paths from the LUT inputs
+to the LUT output.
+
+DFFs
+^^^^
+
+DFFs should be annotated with an ``(* abc9_flop *)`` attribute, however ABC9 has
+some specific requirements for this to be valid: - the DFF must initialise to
+zero (consider using :cmd:ref:`dfflegalize` to ensure this). - the DFF cannot
+have any asynchronous resets/sets (see the simplification idiom and the Boxes
+section for what to do here).
+
+It is worth noting that in pure ``abc9`` mode, only the setup and arrival times
+are passed to ABC9 (specifically, they are modelled as buffers with the given
+delay). In ``abc9 -dff``, the flop itself is passed to ABC9, permitting
+sequential optimisations.
+
+Some vendors have universal DFF models which include async sets/resets even when
+they're unused. Therefore *the simplification idiom* exists to handle this: by
+using a ``techmap`` file to discover flops which have a constant driver to those
+asynchronous controls, they can be mapped into an intermediate, simplified flop
+which qualifies as an ``(* abc9_flop *)``, ran through :cmd:ref:`abc9`, and then
+mapped back to the original flop. This is used in :cmd:ref:`synth_intel_alm` and
+:cmd:ref:`synth_quicklogic` for the PolarPro3.
+
+DFFs are usually specified to have setup constraints against the clock on the
+input signals, and an arrival time for the ``Q`` output.
+
+Boxes
+^^^^^
+
+A "box" is a purely-combinational piece of hard logic. If the logic is exposed
+to ABC9, it's a "whitebox", otherwise it's a "blackbox". Carry chains would be
+best implemented as whiteboxes, but a DSP would be best implemented as a
+blackbox (multipliers are too complex to easily work with). LUT RAMs can be
+implemented as whiteboxes too.
+
+Boxes are arguably the biggest advantage that ABC9 has over ABC: by being aware
+of carry chains and DSPs, it avoids optimising for a path that isn't the actual
+critical path, while the generally-longer paths result in ABC9 being able to
+reduce design area by mapping other logic to larger-but-slower cells.
diff --git a/yosys/docs/source/yosys_internals/extending_yosys/extensions.rst b/yosys/docs/source/yosys_internals/extending_yosys/extensions.rst
new file mode 100644
index 00000000000..f10c634b015
--- /dev/null
+++ b/yosys/docs/source/yosys_internals/extending_yosys/extensions.rst
@@ -0,0 +1,272 @@
+Writing extensions
+==================
+
+.. role:: yoscrypt(code)
+   :language: yoscrypt
+
+.. todo:: check text is coherent
+
+.. todo:: update to use :file:`/code_examples/extensions/test*.log`
+
+This chapter contains some bits and pieces of information about programming
+yosys extensions. Don't be afraid to ask questions on the YosysHQ Slack.
+
+The `guidelines/` directory of the Yosys source code contains notes on various
+aspects of Yosys development. In particular, the files GettingStarted and
+CodingStyle may be of interest.
+
+.. todo:: what's in guidelines/GettingStarted that's missing from the manual?
+
+Quick guide
+-----------
+
+Code examples from this section are included in the
+|code_examples/extensions|_ directory of the Yosys source code.
+
+.. |code_examples/extensions| replace:: :file:`docs/source/code_examples/extensions`
+.. _code_examples/extensions: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/extensions
+
+
+Program components and data formats
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+See :doc:`/yosys_internals/formats/rtlil_rep` document for more information
+about the internal data storage format used in Yosys and the classes that it
+provides.
+
+This document will focus on the much simpler version of RTLIL left after the
+commands :cmd:ref:`proc` and :cmd:ref:`memory` (or :yoscrypt:`memory -nomap`):
+
+.. figure:: /_images/internals/simplified_rtlil.*
+    :class: width-helper invert-helper
+    :name: fig:Simplified_RTLIL
+
+    Simplified RTLIL entity-relationship diagram without memories and processes
+
+It is possible to only work on this simpler version:
+
+.. todo:: consider replacing inline code
+
+.. code:: c++
+
+    for (RTLIL::Module *module : design->selected_modules() {
+        if (module->has_memories_warn() || module->has_processes_warn())
+            continue;
+        ....
+    }
+
+When trying to understand what a command does, creating a small test case to
+look at the output of :cmd:ref:`dump` and :cmd:ref:`show` before and after the
+command has been executed can be helpful.
+:doc:`/using_yosys/more_scripting/selections` has more information on using
+these commands.
+
+Creating a command
+~~~~~~~~~~~~~~~~~~
+
+.. todo:: add/expand supporting text
+
+Let's create a very simple test command which prints the arguments we called it
+with, and lists off the current design's modules.
+
+.. literalinclude:: /code_examples/extensions/my_cmd.cc
+   :language: c++
+   :lines: 1, 4, 6, 7-20
+   :caption: Example command :yoscrypt:`my_cmd` from :file:`my_cmd.cc`
+   
+Note that we are making a global instance of a class derived from
+``Yosys::Pass``, which we get by including :file:`kernel/yosys.h`.
+
+Compiling to a plugin
+~~~~~~~~~~~~~~~~~~~~~
+
+Yosys can be extended by adding additional C++ code to the Yosys code base, or
+by loading plugins into Yosys.  For maintainability it is generally recommended
+to create plugins.
+
+The following command compiles our example :yoscrypt:`my_cmd` to a Yosys plugin:
+
+.. todo:: replace inline code
+
+.. code:: shell
+
+   yosys-config --exec --cxx --cxxflags --ldflags \
+   -o my_cmd.so -shared my_cmd.cc --ldlibs
+
+Or shorter:
+
+.. code:: shell
+
+   yosys-config --build my_cmd.so my_cmd.cc
+
+Running Yosys with the ``-m`` option allows the plugin to be used.  Here's a
+quick example that also uses the ``-p`` option to run :yoscrypt:`my_cmd foo
+bar`.
+
+.. code:: shell-session
+
+   $ yosys -m ./my_cmd.so -p 'my_cmd foo bar'
+
+   -- Running command `my_cmd foo bar' --
+   Arguments to my_cmd:
+     my_cmd
+     foo
+     bar
+   Modules in current design:
+
+Creating modules from scratch
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Let's create the following module using the RTLIL API:
+
+.. literalinclude:: /code_examples/extensions/absval_ref.v
+   :language: Verilog
+   :caption: absval_ref.v
+
+We'll do the same as before and format it as a a ``Yosys::Pass``.
+
+.. literalinclude:: /code_examples/extensions/my_cmd.cc
+   :language: c++
+   :lines: 23-47
+   :caption: :yoscrypt:`test1` - creating the absval module, from :file:`my_cmd.cc`
+
+.. code:: shell-session
+
+   $ yosys -m ./my_cmd.so -p 'test1' -Q
+
+   -- Running command `test1' --
+   Name of this module: absval
+
+And if we look at the schematic for this new module we see the following:
+
+.. figure:: /_images/code_examples/extensions/test1.*
+   :class: width-helper invert-helper
+
+   Output of ``yosys -m ./my_cmd.so -p 'test1; show'``
+
+Modifying modules
+~~~~~~~~~~~~~~~~~
+
+Most commands modify existing modules, not create new ones.
+
+When modifying existing modules, stick to the following DOs and DON'Ts:
+
+- Do not remove wires. Simply disconnect them and let a successive
+  :cmd:ref:`clean` command worry about removing it.
+- Use ``module->fixup_ports()`` after changing the ``port_*`` properties of
+  wires.
+- You can safely remove cells or change the ``connections`` property of a cell,
+  but be careful when changing the size of the ``SigSpec`` connected to a cell
+  port.
+- Use the ``SigMap`` helper class (see next section) when you need a unique
+  handle for each signal bit.
+
+Using the SigMap helper class
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Consider the following module:
+
+.. literalinclude:: /code_examples/extensions/sigmap_test.v
+   :language: Verilog
+   :caption: :file:`sigmap_test.v`
+
+In this case ``a``, ``x``, and ``y`` are all different names for the same
+signal. However:
+
+.. todo:: use my_cmd.cc literalincludes
+
+.. code:: C++
+
+    RTLIL::SigSpec a(module->wire("\\a")), x(module->wire("\\x")),
+                                           y(module->wire("\\y"));
+    log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
+
+The ``SigMap`` helper class can be used to map all such aliasing signals to a
+unique signal from the group (usually the wire that is directly driven by a cell
+or port).
+
+.. code:: C++
+
+    SigMap sigmap(module);
+    log("%d %d %d\n", sigmap(a) == sigmap(x), sigmap(x) == sigmap(y),
+                      sigmap(y) == sigmap(a)); // will print "1 1 1"
+
+Printing log messages
+~~~~~~~~~~~~~~~~~~~~~
+
+The ``log()`` function is a ``printf()``-like function that can be used to
+create log messages.
+
+Use ``log_signal()`` to create a C-string for a SigSpec object:
+
+.. code:: C++
+
+    log("Mapped signal x: %s\n", log_signal(sigmap(x)));
+
+The pointer returned by ``log_signal()`` is automatically freed by the log
+framework at a later time.
+
+Use ``log_id()`` to create a C-string for an ``RTLIL::IdString``:
+
+.. code:: C++
+
+    log("Name of this module: %s\n", log_id(module->name));
+
+Use ``log_header()`` and ``log_push()``/\ ``log_pop()`` to structure log
+messages:
+
+.. todo:: replace inline code
+
+.. code:: C++
+
+    log_header(design, "Doing important stuff!\n");
+    log_push();
+    for (int i = 0; i < 10; i++)
+        log("Log message #%d.\n", i);
+    log_pop();
+
+Error handling
+~~~~~~~~~~~~~~
+
+Use ``log_error()`` to report a non-recoverable error:
+
+.. todo:: replace inline code
+
+.. code:: C++
+
+    if (design->modules.count(module->name) != 0)
+        log_error("A module with the name %s already exists!\n",
+                   RTLIL::id2cstr(module->name));
+
+Use ``log_cmd_error()`` to report a recoverable error:
+
+.. code:: C++
+
+    if (design->selection_stack.back().empty())
+        log_cmd_error("This command can't operator on an empty selection!\n");
+
+Use ``log_assert()`` and ``log_abort()`` instead of ``assert()`` and ``abort()``.
+
+The "stubnets" example module
+------------------------------
+
+The following is the complete code of the "stubnets" example module. It is
+included in the Yosys source distribution under |code_examples/stubnets|_.
+
+.. |code_examples/stubnets| replace:: :file:`docs/source/code_examples/stubnets`
+.. _code_examples/stubnets: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/stubnets
+
+.. literalinclude:: /code_examples/stubnets/stubnets.cc
+    :language: c++
+    :linenos:
+    :caption: :file:`stubnets.cc`
+
+.. literalinclude:: /code_examples/stubnets/Makefile
+    :language: makefile
+    :linenos:
+    :caption: :file:`Makefile`
+
+.. literalinclude:: /code_examples/stubnets/test.v
+    :language: verilog
+    :linenos:
+    :caption: :file:`test.v`
diff --git a/yosys/docs/source/yosys_internals/extending_yosys/index.rst b/yosys/docs/source/yosys_internals/extending_yosys/index.rst
new file mode 100644
index 00000000000..c2dc6cd2b8b
--- /dev/null
+++ b/yosys/docs/source/yosys_internals/extending_yosys/index.rst
@@ -0,0 +1,11 @@
+Extending Yosys
+---------------
+
+.. todo:: brief overview for the extending Yosys index
+
+.. toctree::
+   :maxdepth: 3
+
+   extensions
+   abc_flow
+
diff --git a/yosys/docs/source/yosys_internals/flow/control_and_data.rst b/yosys/docs/source/yosys_internals/flow/control_and_data.rst
new file mode 100644
index 00000000000..70a84747f9e
--- /dev/null
+++ b/yosys/docs/source/yosys_internals/flow/control_and_data.rst
@@ -0,0 +1,31 @@
+Control and data flow
+=====================
+
+.. todo:: less academic
+
+The data- and control-flow of a typical synthesis tool is very similar to the
+data- and control-flow of a typical compiler: different subsystems are called in
+a predetermined order, each consuming the data generated by the last subsystem
+and generating the data for the next subsystem (see :numref:`Fig. %s
+<fig:approach_flow>`).
+
+.. figure:: /_images/internals/approach_flow.*
+	:class: width-helper invert-helper
+	:name: fig:approach_flow
+
+	General data- and control-flow of a synthesis tool
+
+The first subsystem to be called is usually called a frontend. It does not
+process the data generated by another subsystem but instead reads the user
+input—in the case of a HDL synthesis tool, the behavioural HDL code.
+
+The subsystems that consume data from previous subsystems and produce data for
+the next subsystems (usually in the same or a similar format) are called passes.
+
+The last subsystem that is executed transforms the data generated by the last
+pass into a suitable output format and writes it to a disk file. This subsystem
+is usually called the backend.
+
+In Yosys all frontends, passes and backends are directly available as commands
+in the synthesis script. Thus the user can easily create a custom synthesis flow
+just by calling passes in the right order in a synthesis script.
diff --git a/yosys/docs/source/yosys_internals/flow/index.rst b/yosys/docs/source/yosys_internals/flow/index.rst
new file mode 100644
index 00000000000..c7ab0ebccda
--- /dev/null
+++ b/yosys/docs/source/yosys_internals/flow/index.rst
@@ -0,0 +1,19 @@
+Internal flow
+=============
+
+A (usually short) synthesis script controls Yosys.
+
+These scripts contain three types of commands:
+
+- **Frontends**, that read input files (usually Verilog);
+- **Passes**, that perform transformations on the design in memory;
+- **Backends**, that write the design in memory to a file (various formats are
+  available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .).
+
+.. toctree:: 
+	:maxdepth: 3
+
+	overview
+	control_and_data
+	verilog_frontend
+
diff --git a/yosys/docs/source/yosys_internals/flow/overview.rst b/yosys/docs/source/yosys_internals/flow/overview.rst
new file mode 100644
index 00000000000..b357e5b50ea
--- /dev/null
+++ b/yosys/docs/source/yosys_internals/flow/overview.rst
@@ -0,0 +1,49 @@
+Flow overview
+=============
+
+.. todo:: less academic
+
+:numref:`Figure %s <fig:Overview_flow>` shows the simplified data flow within
+Yosys. Rectangles in the figure represent program modules and ellipses internal
+data structures that are used to exchange design data between the program
+modules.
+
+Design data is read in using one of the frontend modules. The high-level HDL
+frontends for Verilog and VHDL code generate an abstract syntax tree (AST) that
+is then passed to the AST frontend. Note that both HDL frontends use the same
+AST representation that is powerful enough to cover the Verilog HDL and VHDL
+language.
+
+The AST Frontend then compiles the AST to Yosys's main internal data format, the
+RTL Intermediate Language (RTLIL). A more detailed description of this format is
+given in :doc:`/yosys_internals/formats/rtlil_rep`.
+
+There is also a text representation of the RTLIL data structure that can be
+parsed using the RTLIL Frontend which is described in
+:doc:`/yosys_internals/formats/rtlil_text`.
+
+The design data may then be transformed using a series of passes that all
+operate on the RTLIL representation of the design.
+
+Finally the design in RTLIL representation is converted back to text by one of
+the backends, namely the Verilog Backend for generating Verilog netlists and the
+RTLIL Backend for writing the RTLIL data in the same format that is understood
+by the RTLIL Frontend.
+
+With the exception of the AST Frontend, which is called by the high-level HDL
+frontends and can't be called directly by the user, all program modules are
+called by the user (usually using a synthesis script that contains text commands
+for Yosys).
+
+By combining passes in different ways and/or adding additional passes to Yosys
+it is possible to adapt Yosys to a wide range of applications. For this to be
+possible it is key that (1) all passes operate on the same data structure
+(RTLIL) and (2) that this data structure is powerful enough to represent the
+design in different stages of the synthesis.
+
+.. figure:: /_images/internals/overview_flow.*
+	:class: width-helper invert-helper
+	:name: fig:Overview_flow
+
+	Yosys simplified data flow (ellipses: data structures, rectangles:
+	program modules)
diff --git a/yosys/docs/source/yosys_internals/flow/verilog_frontend.rst b/yosys/docs/source/yosys_internals/flow/verilog_frontend.rst
new file mode 100644
index 00000000000..f2eaeae97b3
--- /dev/null
+++ b/yosys/docs/source/yosys_internals/flow/verilog_frontend.rst
@@ -0,0 +1,656 @@
+.. _chapter:verilog:
+
+The Verilog and AST frontends
+=============================
+
+This chapter provides an overview of the implementation of the Yosys Verilog and
+AST frontends. The Verilog frontend reads Verilog-2005 code and creates an
+abstract syntax tree (AST) representation of the input. This AST representation
+is then passed to the AST frontend that converts it to RTLIL data, as
+illustrated in :numref:`Fig. %s <fig:Verilog_flow>`.
+
+.. figure:: /_images/internals/verilog_flow.*
+	:class: width-helper invert-helper
+	:name: fig:Verilog_flow
+
+	Simplified Verilog to RTLIL data flow
+
+Transforming Verilog to AST
+---------------------------
+
+The Verilog frontend converts the Verilog sources to an internal AST
+representation that closely resembles the structure of the original Verilog
+code. The Verilog frontend consists of three components, the Preprocessor, the
+Lexer and the Parser.
+
+The source code to the Verilog frontend can be found in
+:file:`frontends/verilog/` in the Yosys source tree.
+
+The Verilog preprocessor
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+The Verilog preprocessor scans over the Verilog source code and interprets some
+of the Verilog compiler directives such as :literal:`\`include`,
+:literal:`\`define` and :literal:`\`ifdef`.
+
+It is implemented as a C++ function that is passed a file descriptor as input
+and returns the pre-processed Verilog code as a ``std::string``.
+
+The source code to the Verilog Preprocessor can be found in
+:file:`frontends/verilog/preproc.cc` in the Yosys source tree.
+
+The Verilog lexer
+~~~~~~~~~~~~~~~~~
+
+The Verilog Lexer is written using the lexer generator flex. Its source code can
+be found in :file:`frontends/verilog/verilog_lexer.l` in the Yosys source tree.
+The lexer does little more than identifying all keywords and literals recognised
+by the Yosys Verilog frontend.
+
+The lexer keeps track of the current location in the Verilog source code using
+some global variables. These variables are used by the constructor of AST nodes
+to annotate each node with the source code location it originated from.
+
+Finally the lexer identifies and handles special comments such as "``// synopsys
+translate_off``" and "``// synopsys full_case``". (It is recommended to use
+:literal:`\`ifdef` constructs instead of the Synsopsys translate_on/off comments
+and attributes such as ``(* full_case *)`` over "``// synopsys full_case``"
+whenever possible.)
+
+The Verilog parser
+~~~~~~~~~~~~~~~~~~
+
+The Verilog Parser is written using the parser generator bison. Its source code
+can be found in :file:`frontends/verilog/verilog_parser.y` in the Yosys source
+tree.
+
+It generates an AST using the ``AST::AstNode`` data structure defined in
+:file:`frontends/ast/ast.h`. An ``AST::AstNode`` object has the following
+properties:
+
+.. list-table:: AST node types with their corresponding Verilog constructs.
+    :name: tab:Verilog_AstNodeType
+    :widths: 50 50
+
+    * - AST Node Type
+      - Corresponding Verilog Construct
+    * - AST_NONE
+      - This Node type should never be used.
+    * - AST_DESIGN
+      - This node type is used for the top node of the AST tree. It has no
+        corresponding Verilog construct.
+    * - AST_MODULE, AST_TASK, AST_FUNCTION
+      - ``module``, ``task`` and ``function``
+    * - AST_WIRE
+      - ``input``, ``output``, ``wire``, ``reg`` and ``integer``
+    * - AST_MEMORY
+      - Verilog Arrays
+    * - AST_AUTOWIRE
+      - Created by the simplifier when an undeclared signal name is used.
+    * - AST_PARAMETER, AST_LOCALPARAM
+      - ``parameter`` and ``localparam``
+    * - AST_PARASET
+      - Parameter set in cell instantiation
+    * - AST_ARGUMENT
+      - Port connection in cell instantiation
+    * - AST_RANGE
+      - Bit-Index in a signal or element index in array
+    * - AST_CONSTANT
+      - A literal value
+    * - AST_CELLTYPE
+      - The type of cell in cell instantiation
+    * - AST_IDENTIFIER
+      - An Identifier (signal name in expression or cell/task/etc. name in other
+        contexts)
+    * - AST_PREFIX
+      - Construct an identifier in the form <prefix>[<index>].<suffix> (used
+        only in advanced generate constructs)
+    * - AST_FCALL, AST_TCALL
+      - Call to function or task
+    * - AST_TO_SIGNED, AST_TO_UNSIGNED
+      - The ``$signed()`` and ``$unsigned()`` functions
+    * - AST_CONCAT, AST_REPLICATE
+      - The ``{...}`` and ``{...{...}}`` operators
+    * - AST_BIT_NOT, AST_BIT_AND, AST_BIT_OR, AST_BIT_XOR, AST_BIT_XNOR
+      - The bitwise operators ``~``, ``&``, ``|``, ``^`` and ``~^``
+    * - AST_REDUCE_AND, AST_REDUCE_OR, AST_REDUCE_XOR, AST_REDUCE_XNOR
+      - The unary reduction operators ``~``, ``&``, ``|``, ``^`` and ``~^``
+    * - AST_REDUCE_BOOL
+      - Conversion from multi-bit value to boolean value (equivalent to
+        AST_REDUCE_OR)
+    * - AST_SHIFT_LEFT, AST_SHIFT_RIGHT, AST_SHIFT_SLEFT, AST_SHIFT_SRIGHT
+      - The shift operators ``<<``, ``>>``, ``<<<`` and ``>>>``
+    * - AST_LT, AST_LE, AST_EQ, AST_NE, AST_GE, AST_GT
+      - The relational operators ``<``, ``<=``, ``==``, ``!=``, ``>=`` and ``>``
+    * - AST_ADD, AST_SUB, AST_MUL, AST_DIV, AST_MOD, AST_POW
+      - The binary operators ``+``, ``-``, ``*``, ``/``, ``%`` and ``**``
+    * - AST_POS, AST_NEG
+      - The prefix operators ``+`` and ``-``
+    * - AST_LOGIC_AND, AST_LOGIC_OR, AST_LOGIC_NOT
+      - The logic operators ``&&``, ``||`` and ``!``
+    * - AST_TERNARY
+      - The ternary ``?:``-operator
+    * - AST_MEMRD AST_MEMWR
+      - Read and write memories. These nodes are generated by the AST simplifier
+        for writes/reads to/from Verilog arrays.
+    * - AST_ASSIGN
+      - An ``assign`` statement
+    * - AST_CELL
+      - A cell instantiation
+    * - AST_PRIMITIVE
+      - A primitive cell (``and``, ``nand``, ``or``, etc.)
+    * - AST_ALWAYS, AST_INITIAL
+      - Verilog ``always``- and ``initial``-blocks
+    * - AST_BLOCK
+      - A ``begin``-``end``-block
+    * - AST_ASSIGN_EQ. AST_ASSIGN_LE
+      - Blocking (``=``) and nonblocking (``<=``) assignments within an
+        ``always``- or ``initial``-block
+    * - AST_CASE. AST_COND, AST_DEFAULT
+      - The ``case`` (``if``) statements, conditions within a case and the
+        default case respectively
+    * - AST_FOR
+      - A ``for``-loop with an ``always``- or ``initial``-block
+    * - AST_GENVAR, AST_GENBLOCK, AST_GENFOR, AST_GENIF
+      - The ``genvar`` and ``generate`` keywords and ``for`` and ``if`` within a
+        generate block.
+    * - AST_POSEDGE, AST_NEGEDGE, AST_EDGE
+      - Event conditions for ``always`` blocks.
+
+-  | The node type
+   | This enum (``AST::AstNodeType``) specifies the role of the node.
+     :numref:`Table %s <tab:Verilog_AstNodeType>` contains a list of all node
+     types.
+
+-  | The child nodes
+   | This is a list of pointers to all children in the abstract syntax tree.
+
+-  | Attributes
+   | As almost every AST node might have Verilog attributes assigned to it, the
+     ``AST::AstNode`` has direct support for attributes. Note that the attribute
+     values are again AST nodes.
+
+-  | Node content
+   | Each node might have additional content data. A series of member variables
+     exist to hold such data. For example the member ``std::string str`` can
+     hold a string value and is used e.g. in the ``AST_IDENTIFIER`` node type to
+     store the identifier name.
+
+-  | Source code location
+   | Each ``AST::AstNode`` is automatically annotated with the current source
+     code location by the ``AST::AstNode`` constructor. It is stored in the
+     ``std::string filename`` and ``int linenum`` member variables.
+
+The ``AST::AstNode`` constructor can be called with up to two child nodes that
+are automatically added to the list of child nodes for the new object. This
+simplifies the creation of AST nodes for simple expressions a bit. For example
+the bison code for parsing multiplications:
+
+.. code:: none
+   	:number-lines:
+
+	basic_expr '*' attr basic_expr {
+		$$ = new AstNode(AST_MUL, $1, $4);
+		append_attr($$, $3);
+	} |
+
+The generated AST data structure is then passed directly to the AST frontend
+that performs the actual conversion to RTLIL.
+
+Note that the Yosys command ``read_verilog`` provides the options ``-yydebug``
+and ``-dump_ast`` that can be used to print the parse tree or abstract syntax
+tree respectively.
+
+Transforming AST to RTLIL
+-------------------------
+
+The AST Frontend converts a set of modules in AST representation to modules in
+RTLIL representation and adds them to the current design. This is done in two
+steps: simplification and RTLIL generation.
+
+The source code to the AST frontend can be found in ``frontends/ast/`` in the
+Yosys source tree.
+
+AST simplification
+~~~~~~~~~~~~~~~~~~
+
+A full-featured AST is too complex to be transformed into RTLIL directly.
+Therefore it must first be brought into a simpler form. This is done by calling
+the ``AST::AstNode::simplify()`` method of all ``AST_MODULE`` nodes in the AST.
+This initiates a recursive process that performs the following transformations
+on the AST data structure:
+
+-  Inline all task and function calls.
+
+-  Evaluate all ``generate``-statements and unroll all ``for``-loops.
+
+-  Perform const folding where it is necessary (e.g. in the value part of
+   ``AST_PARAMETER``, ``AST_LOCALPARAM``, ``AST_PARASET`` and ``AST_RANGE``
+   nodes).
+
+-  Replace ``AST_PRIMITIVE`` nodes with appropriate ``AST_ASSIGN`` nodes.
+
+-  Replace dynamic bit ranges in the left-hand-side of assignments with
+   ``AST_CASE`` nodes with ``AST_COND`` children for each possible case.
+
+-  Detect array access patterns that are too complicated for the
+   ``RTLIL::Memory`` abstraction and replace them with a set of signals and
+   cases for all reads and/or writes.
+
+-  Otherwise replace array accesses with ``AST_MEMRD`` and ``AST_MEMWR`` nodes.
+
+In addition to these transformations, the simplifier also annotates the
+AST with additional information that is needed for the RTLIL generator,
+namely:
+
+-  All ranges (width of signals and bit selections) are not only const
+   folded but (when a constant value is found) are also written to
+   member variables in the AST_RANGE node.
+
+-  All identifiers are resolved and all ``AST_IDENTIFIER`` nodes are annotated
+   with a pointer to the AST node that contains the declaration of the
+   identifier. If no declaration has been found, an ``AST_AUTOWIRE`` node is
+   created and used for the annotation.
+
+This produces an AST that is fairly easy to convert to the RTLIL format.
+
+Generating RTLIL
+~~~~~~~~~~~~~~~~
+
+After AST simplification, the ``AST::AstNode::genRTLIL()`` method of each
+``AST_MODULE`` node in the AST is called. This initiates a recursive process
+that generates equivalent RTLIL data for the AST data.
+
+The ``AST::AstNode::genRTLIL()`` method returns an ``RTLIL::SigSpec`` structure.
+For nodes that represent expressions (operators, constants, signals, etc.), the
+cells needed to implement the calculation described by the expression are
+created and the resulting signal is returned. That way it is easy to generate
+the circuits for large expressions using depth-first recursion. For nodes that
+do not represent an expression (such as ``AST_CELL``), the corresponding circuit
+is generated and an empty ``RTLIL::SigSpec`` is returned.
+
+Synthesizing Verilog always blocks
+--------------------------------------
+
+For behavioural Verilog code (code utilizing ``always``- and ``initial``-blocks)
+it is necessary to also generate ``RTLIL::Process`` objects. This is done in the
+following way:
+
+Whenever ``AST::AstNode::genRTLIL()`` encounters an ``always``- or
+``initial``-block, it creates an instance of ``AST_INTERNAL::ProcessGenerator``.
+This object then generates the ``RTLIL::Process`` object for the block. It also
+calls ``AST::AstNode::genRTLIL()`` for all right-hand-side expressions contained
+within the block.
+
+First the ``AST_INTERNAL::ProcessGenerator`` creates a list of all signals
+assigned within the block. It then creates a set of temporary signals using the
+naming scheme ``$ <number> \ <original_name>`` for each of the assigned signals.
+
+Then an ``RTLIL::Process`` is created that assigns all intermediate values for
+each left-hand-side signal to the temporary signal in its
+``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree.
+
+Finally a ``RTLIL::SyncRule`` is created for the ``RTLIL::Process`` that assigns
+the temporary signals for the final values to the actual signals.
+
+A process may also contain memory writes. A ``RTLIL::MemWriteAction`` is created
+for each of them.
+
+Calls to ``AST::AstNode::genRTLIL()`` are generated for right hand sides as
+needed. When blocking assignments are used, ``AST::AstNode::genRTLIL()`` is
+configured using global variables to use the temporary signals that hold the
+correct intermediate values whenever one of the previously assigned signals is
+used in an expression.
+
+Unfortunately the generation of a correct
+``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule`` tree for behavioural code is a
+non-trivial task. The AST frontend solves the problem using the approach
+described on the following pages. The following example illustrates what the
+algorithm is supposed to do. Consider the following Verilog code:
+
+.. code:: verilog
+   :number-lines:
+
+   always @(posedge clock) begin
+       out1 = in1;
+       if (in2)
+           out1 = !out1;
+       out2 <= out1;
+       if (in3)
+           out2 <= out2;
+       if (in4)
+           if (in5)
+               out3 <= in6;
+           else
+               out3 <= in7;
+       out1 = out1 ^ out2;
+   end
+
+This is translated by the Verilog and AST frontends into the following RTLIL
+code (attributes, cell parameters and wire declarations not included):
+
+.. code:: RTLIL
+   :number-lines:
+
+   cell $logic_not $logic_not$<input>:4$2
+     connect \A \in1
+     connect \Y $logic_not$<input>:4$2_Y
+   end
+   cell $xor $xor$<input>:13$3
+     connect \A $1\out1[0:0]
+     connect \B \out2
+     connect \Y $xor$<input>:13$3_Y
+   end
+   process $proc$<input>:1$1
+     assign $0\out3[0:0] \out3
+     assign $0\out2[0:0] $1\out1[0:0]
+     assign $0\out1[0:0] $xor$<input>:13$3_Y
+     switch \in2
+       case 1'1
+         assign $1\out1[0:0] $logic_not$<input>:4$2_Y
+       case
+         assign $1\out1[0:0] \in1
+     end
+     switch \in3
+       case 1'1
+         assign $0\out2[0:0] \out2
+       case
+     end
+     switch \in4
+       case 1'1
+         switch \in5
+           case 1'1
+             assign $0\out3[0:0] \in6
+           case
+             assign $0\out3[0:0] \in7
+         end
+       case
+     end
+     sync posedge \clock
+       update \out1 $0\out1[0:0]
+       update \out2 $0\out2[0:0]
+       update \out3 $0\out3[0:0]
+   end
+
+Note that the two operators are translated into separate cells outside the
+generated process. The signal ``out1`` is assigned using blocking assignments
+and therefore ``out1`` has been replaced with a different signal in all
+expressions after the initial assignment. The signal ``out2`` is assigned using
+nonblocking assignments and therefore is not substituted on the right-hand-side
+expressions.
+
+The ``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule`` tree must be interpreted the
+following way:
+
+-  On each case level (the body of the process is the root case), first the
+   actions on this level are evaluated and then the switches within the case are
+   evaluated. (Note that the last assignment on line 13 of the Verilog code has
+   been moved to the beginning of the RTLIL process to line 13 of the RTLIL
+   listing.)
+
+   I.e. the special cases deeper in the switch hierarchy override the defaults
+   on the upper levels. The assignments in lines 12 and 22 of the RTLIL code
+   serve as an example for this.
+
+   Note that in contrast to this, the order within the ``RTLIL::SwitchRule``
+   objects within a ``RTLIL::CaseRule`` is preserved with respect to the
+   original AST and Verilog code.
+
+-  The whole ``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule`` tree describes an
+   asynchronous circuit. I.e. the decision tree formed by the switches can be
+   seen independently for each assigned signal. Whenever one assigned signal
+   changes, all signals that depend on the changed signals are to be updated.
+   For example the assignments in lines 16 and 18 in the RTLIL code in fact
+   influence the assignment in line 12, even though they are in the "wrong
+   order".
+
+The only synchronous part of the process is in the ``RTLIL::SyncRule`` object
+generated at line 35 in the RTLIL code. The sync rule is the only part of the
+process where the original signals are assigned. The synchronization event from
+the original Verilog code has been translated into the synchronization type
+(posedge) and signal (``\clock``) for the ``RTLIL::SyncRule`` object. In the
+case of this simple example the ``RTLIL::SyncRule`` object is later simply
+transformed into a set of d-type flip-flops and the
+``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule`` tree to a decision tree using
+multiplexers.
+
+In more complex examples (e.g. asynchronous resets) the part of the
+``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule`` tree that describes the asynchronous
+reset must first be transformed to the correct ``RTLIL::SyncRule`` objects. This
+is done by the ``proc_arst`` pass.
+
+The ProcessGenerator algorithm
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The ``AST_INTERNAL::ProcessGenerator`` uses the following internal state
+variables:
+
+-  | ``subst_rvalue_from`` and ``subst_rvalue_to``
+   | These two variables hold the replacement pattern that should be used by
+     ``AST::AstNode::genRTLIL()`` for signals with blocking assignments. After
+    initialization of ``AST_INTERNAL::ProcessGenerator`` these two variables are
+    empty.
+
+-  | ``subst_lvalue_from`` and ``subst_lvalue_to`` 
+   | These two variables contain the mapping from left-hand-side signals (``\
+     <name>``) to the current temporary signal for the same thing (initially
+     ``$0\ <name>``).
+
+-  | ``current_case`` 
+   | A pointer to a ``RTLIL::CaseRule`` object. Initially this is the root case
+     of the generated ``RTLIL::Process``.
+
+As the algorithm runs these variables are continuously modified as well as
+pushed to the stack and later restored to their earlier values by popping from
+the stack.
+
+On startup the ProcessGenerator generates a new ``RTLIL::Process`` object with
+an empty root case and initializes its state variables as described above. Then
+the ``RTLIL::SyncRule`` objects are created using the synchronization events
+from the AST_ALWAYS node and the initial values of ``subst_lvalue_from`` and
+``subst_lvalue_to``. Then the AST for this process is evaluated recursively.
+
+During this recursive evaluation, three different relevant types of AST nodes
+can be discovered: ``AST_ASSIGN_LE`` (nonblocking assignments),
+``AST_ASSIGN_EQ`` (blocking assignments) and ``AST_CASE`` (``if`` or ``case``
+statement).
+
+Handling of nonblocking assignments
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+When an ``AST_ASSIGN_LE`` node is discovered, the following actions are
+performed by the ProcessGenerator:
+
+-  The left-hand-side is evaluated using ``AST::AstNode::genRTLIL()`` and mapped
+   to a temporary signal name using ``subst_lvalue_from`` and
+   ``subst_lvalue_to``.
+
+-  The right-hand-side is evaluated using ``AST::AstNode::genRTLIL()``. For this
+   call, the values of ``subst_rvalue_from`` and ``subst_rvalue_to`` are used to
+   map blocking-assigned signals correctly.
+
+-  Remove all assignments to the same left-hand-side as this assignment from the
+   ``current_case`` and all cases within it.
+
+-  Add the new assignment to the ``current_case``.
+
+Handling of blocking assignments
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+When an ``AST_ASSIGN_EQ`` node is discovered, the following actions are
+performed by the ProcessGenerator:
+
+-  Perform all the steps that would be performed for a nonblocking assignment
+   (see above).
+
+-  Remove the found left-hand-side (before lvalue mapping) from
+   ``subst_rvalue_from`` and also remove the respective bits from
+   ``subst_rvalue_to``.
+
+-  Append the found left-hand-side (before lvalue mapping) to
+   ``subst_rvalue_from`` and append the found right-hand-side to
+   ``subst_rvalue_to``.
+
+Handling of cases and if-statements
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+When an ``AST_CASE`` node is discovered, the following actions are performed by
+the ProcessGenerator:
+
+-  The values of ``subst_rvalue_from``, ``subst_rvalue_to``,
+   ``subst_lvalue_from`` and ``subst_lvalue_to`` are pushed to the stack.
+
+-  A new ``RTLIL::SwitchRule`` object is generated, the selection expression is
+   evaluated using ``AST::AstNode::genRTLIL()`` (with the use of
+   ``subst_rvalue_from`` and ``subst_rvalue_to``) and added to the
+   ``RTLIL::SwitchRule`` object and the object is added to the ``current_case``.
+
+-  All lvalues assigned to within the ``AST_CASE`` node using blocking
+   assignments are collected and saved in the local variable
+   ``this_case_eq_lvalue``.
+
+-  New temporary signals are generated for all signals in
+   ``this_case_eq_lvalue`` and stored in ``this_case_eq_ltemp``.
+
+-  The signals in ``this_case_eq_lvalue`` are mapped using ``subst_rvalue_from``
+   and ``subst_rvalue_to`` and the resulting set of signals is stored in
+   ``this_case_eq_rvalue``.
+
+Then the following steps are performed for each ``AST_COND`` node within the
+``AST_CASE`` node:
+
+-  Set ``subst_rvalue_from``, ``subst_rvalue_to``, ``subst_lvalue_from`` and
+   ``subst_lvalue_to`` to the values that have been pushed to the stack.
+
+-  Remove ``this_case_eq_lvalue`` from
+   ``subst_lvalue_from``/``subst_lvalue_to``.
+
+-  Append ``this_case_eq_lvalue`` to ``subst_lvalue_from`` and append
+   ``this_case_eq_ltemp`` to ``subst_lvalue_to``.
+
+-  Push the value of ``current_case``.
+
+-  Create a new ``RTLIL::CaseRule``. Set ``current_case`` to the new object and
+   add the new object to the ``RTLIL::SwitchRule`` created above.
+
+-  Add an assignment from ``this_case_eq_rvalue`` to ``this_case_eq_ltemp`` to
+   the new ``current_case``.
+
+-  Evaluate the compare value for this case using
+   ``AST::AstNode::genRTLIL()`` (with the use of ``subst_rvalue_from``
+   and ``subst_rvalue_to``) modify the new ``current_case`` accordingly.
+
+-  Recursion into the children of the ``AST_COND`` node.
+
+-  Restore ``current_case`` by popping the old value from the stack.
+
+Finally the following steps are performed:
+
+-  The values of ``subst_rvalue_from``, ``subst_rvalue_to``,
+   ``subst_lvalue_from`` and ``subst_lvalue_to`` are popped from the stack.
+
+-  The signals from ``this_case_eq_lvalue`` are removed from the
+   ``subst_rvalue_from``/``subst_rvalue_to``-pair.
+
+-  The value of ``this_case_eq_lvalue`` is appended to ``subst_rvalue_from`` and
+   the value of ``this_case_eq_ltemp`` is appended to ``subst_rvalue_to``.
+
+-  Map the signals in ``this_case_eq_lvalue`` using
+   ``subst_lvalue_from``/``subst_lvalue_to``.
+
+-  Remove all assignments to signals in ``this_case_eq_lvalue`` in
+   ``current_case`` and all cases within it.
+
+-  Add an assignment from ``this_case_eq_ltemp`` to ``this_case_eq_lvalue`` to
+   ``current_case``.
+
+Further analysis of the algorithm for cases and if-statements
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+With respect to nonblocking assignments the algorithm is easy: later assignments
+invalidate earlier assignments. For each signal assigned using nonblocking
+assignments exactly one temporary variable is generated (with the ``$0``-prefix)
+and this variable is used for all assignments of the variable.
+
+Note how all the ``_eq_``-variables become empty when no blocking assignments
+are used and many of the steps in the algorithm can then be ignored as a result
+of this.
+
+For a variable with blocking assignments the algorithm shows the following
+behaviour: First a new temporary variable is created. This new temporary
+variable is then registered as the assignment target for all assignments for
+this variable within the cases for this ``AST_CASE`` node. Then for each case
+the new temporary variable is first assigned the old temporary variable. This
+assignment is overwritten if the variable is actually assigned in this case and
+is kept as a default value otherwise.
+
+This yields an ``RTLIL::CaseRule`` that assigns the new temporary variable in
+all branches. So when all cases have been processed a final assignment is added
+to the containing block that assigns the new temporary variable to the old one.
+Note how this step always overrides a previous assignment to the old temporary
+variable. Other than nonblocking assignments, the old assignment could still
+have an effect somewhere in the design, as there have been calls to
+``AST::AstNode::genRTLIL()`` with a
+``subst_rvalue_from``/\ ``subst_rvalue_to``-tuple that contained the
+right-hand-side of the old assignment.
+
+The proc pass
+~~~~~~~~~~~~~
+
+The ProcessGenerator converts a behavioural model in AST representation to a
+behavioural model in ``RTLIL::Process`` representation. The actual conversion
+from a behavioural model to an RTL representation is performed by the
+:cmd:ref:`proc` pass and the passes it launches:
+
+-  | :cmd:ref:`proc_clean` and :cmd:ref:`proc_rmdead` 
+   | These two passes just clean up the ``RTLIL::Process`` structure. The
+     :cmd:ref:`proc_clean` pass removes empty parts (eg. empty assignments) from
+     the process and :cmd:ref:`proc_rmdead` detects and removes unreachable
+     branches from the process's decision trees.
+
+-  | :cmd:ref:`proc_arst` 
+   | This pass detects processes that describe d-type flip-flops with
+     asynchronous resets and rewrites the process to better reflect what they
+     are modelling: Before this pass, an asynchronous reset has two
+     edge-sensitive sync rules and one top-level ``RTLIL::SwitchRule`` for the
+     reset path. After this pass the sync rule for the reset is level-sensitive
+     and the top-level ``RTLIL::SwitchRule`` has been removed.
+
+-  | :cmd:ref:`proc_mux` 
+   | This pass converts the ``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule``-tree to a
+     tree of multiplexers per written signal. After this, the ``RTLIL::Process``
+     structure only contains the ``RTLIL::SyncRule`` s that describe the output
+     registers.
+
+-  | :cmd:ref:`proc_dff`
+   | This pass replaces the ``RTLIL::SyncRule``\ s to d-type flip-flops (with
+     asynchronous resets if necessary).
+
+-  | :cmd:ref:`proc_dff`
+   | This pass replaces the ``RTLIL::MemWriteAction``\ s with ``$memwr`` cells.
+
+-  | :cmd:ref:`proc_clean`
+   | A final call to :cmd:ref:`proc_clean` removes the now empty
+     ``RTLIL::Process`` objects.
+
+Performing these last processing steps in passes instead of in the Verilog
+frontend has two important benefits:
+
+First it improves the transparency of the process. Everything that happens in a
+separate pass is easier to debug, as the RTLIL data structures can be easily
+investigated before and after each of the steps.
+
+Second it improves flexibility. This scheme can easily be extended to support
+other types of storage-elements, such as sr-latches or d-latches, without having
+to extend the actual Verilog frontend.
+
+.. todo:: Synthesizing Verilog arrays
+
+  Add some information on the generation of ``$memrd`` and ``$memwr`` cells and
+  how they are processed in the memory pass.
+
+
+.. todo:: Synthesizing parametric designs
+
+  Add some information on the ``RTLIL::Module::derive()`` method and how it is
+  used to synthesize parametric modules via the hierarchy pass.
diff --git a/yosys/docs/source/CHAPTER_CellLib.rst b/yosys/docs/source/yosys_internals/formats/cell_library.rst
similarity index 77%
rename from yosys/docs/source/CHAPTER_CellLib.rst
rename to yosys/docs/source/yosys_internals/formats/cell_library.rst
index c8904086879..2e30ee25c5d 100644
--- a/yosys/docs/source/CHAPTER_CellLib.rst
+++ b/yosys/docs/source/yosys_internals/formats/cell_library.rst
@@ -6,9 +6,14 @@
 Internal cell library
 =====================
 
-Most of the passes in Yosys operate on netlists, i.e. they only care about the
-RTLIL::Wire and RTLIL::Cell objects in an RTLIL::Module. This chapter discusses
-the cell types used by Yosys to represent a behavioural design internally.
+.. todo:: less academic, also check formatting consistency
+
+Most of the passes in Yosys operate on netlists, i.e. they only care about the
+``RTLIL::Wire`` and ``RTLIL::Cell`` objects in an ``RTLIL::Module``. This
+chapter discusses the cell types used by Yosys to represent a behavioural design
+internally.
+
+.. TODO:: is this chapter split preserved
 
 This chapter is split in two parts. In the first part the internal RTL cells are
 covered. These cells are used to represent the design on a coarse grain level.
@@ -31,7 +36,7 @@ parameters in sync with the size of the signals connected to the inputs and
 outputs.
 
 Simulation models for the RTL cells can be found in the file
-``techlibs/common/simlib.v`` in the Yosys source tree.
+:file:`techlibs/common/simlib.v` in the Yosys source tree.
 
 Unary operators
 ~~~~~~~~~~~~~~~
@@ -40,8 +45,8 @@ All unary RTL cells have one input port ``\A`` and one output port ``\Y``. They
 also have the following parameters:
 
 ``\A_SIGNED``
-	Set to a non-zero value if the input ``\A`` is signed and therefore
-	should be sign-extended when needed.
+	Set to a non-zero value if the input ``\A`` is signed and therefore should be
+	sign-extended when needed.
 
 ``\A_WIDTH``
 	The width of the input port ``\A``.
@@ -108,7 +113,7 @@ All binary RTL cells have two input ports ``\A`` and ``\B`` and one output port
 	:name: tab:CellLib_binary
 
 	======================= ============= ======================= =========
-	Verilog 	        Cell Type     Verilog                 Cell Type
+	Verilog                 Cell Type     Verilog                 Cell Type
 	======================= ============= ======================= =========
 	:verilog:`Y = A  & B`   $and          :verilog:`Y = A <  B`   $lt
 	:verilog:`Y = A  | B`   $or           :verilog:`Y = A <= B`   $le
@@ -120,9 +125,9 @@ All binary RTL cells have two input ports ``\A`` and ``\B`` and one output port
 	:verilog:`Y = A >>> B`  $sshr         :verilog:`Y = A  - B`   $sub
 	:verilog:`Y = A && B`   $logic_and    :verilog:`Y = A  * B`   $mul
 	:verilog:`Y = A || B`   $logic_or     :verilog:`Y = A  / B`   $div
-	:verilog:`Y = A === B`  $eqx          :verilog:`Y = A  % B`   $mod 
+	:verilog:`Y = A === B`  $eqx          :verilog:`Y = A  % B`   $mod
 	:verilog:`Y = A !== B`  $nex          ``N/A``                 $divfloor
-	:verilog:`Y = A ** B`   $pow          ``N/A``                 $modfoor
+	:verilog:`Y = A ** B`   $pow          ``N/A``                 $modfloor
 	======================= ============= ======================= =========
 
 The ``$shl`` and ``$shr`` cells implement logical shifts, whereas the ``$sshl``
@@ -139,7 +144,7 @@ positions are filled with undef (x) bits, and corresponds to the Verilog indexed
 part-select expression.
 
 For the binary cells that output a logical value (``$logic_and``, ``$logic_or``,
-``$eqx``, ``$nex``, ``$lt``, ``$le``, ``$eq``, ``$ne``, ``$ge``, ``$gt)``, when
+``$eqx``, ``$nex``, ``$lt``, ``$le``, ``$eq``, ``$ne``, ``$ge``, ``$gt``), when
 the ``\Y_WIDTH`` parameter is greater than 1, the output is zero-extended, and
 only the least significant bit varies.
 
@@ -195,7 +200,7 @@ from ``\S`` is set the output is undefined. Cells of this type are used to model
 by an optimization).
 
 The ``$tribuf`` cell is used to implement tristate logic. Cells of this type
-have a ``\B`` parameter and inputs ``\A`` and ``\EN`` and an output ``\Y``. The
+have a ``\WIDTH`` parameter and inputs ``\A`` and ``\EN`` and an output ``\Y``. The
 ``\A`` input and ``\Y`` output are ``\WIDTH`` bits wide, and the ``\EN`` input
 is one bit wide. When ``\EN`` is 0, the output is not driven. When ``\EN`` is 1,
 the value from ``\A`` input is sent to the ``\Y`` output. Therefore, the
@@ -205,7 +210,7 @@ Behavioural code with cascaded if-then-else- and case-statements usually results
 in trees of multiplexer cells. Many passes (from various optimizations to FSM
 extraction) heavily depend on these multiplexer trees to understand dependencies
 between signals. Therefore optimizations should not break these multiplexer
-trees (e.g. by replacing a multiplexer between a calculated signal and a
+trees (e.g. by replacing a multiplexer between a calculated signal and a
 constant zero with an ``$and`` gate).
 
 Registers
@@ -253,8 +258,8 @@ additional two parameters:
 ``\ARST_VALUE``
    	The state of ``\Q`` will be set to this value when the reset is active.
 
-Usually these cells are generated by the ``proc`` pass using the information in
-the designs RTLIL::Process objects.
+Usually these cells are generated by the :cmd:ref:`proc` pass using the
+information in the designs RTLIL::Process objects.
 
 D-type flip-flops with synchronous reset are represented by ``$sdff`` cells. As
 the ``$dff`` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they
@@ -268,8 +273,8 @@ additional two parameters:
 ``\SRST_VALUE``
 	The state of ``\Q`` will be set to this value when the reset is active.
 
-Note that the ``$adff`` and ``$sdff`` cells can only be used when the reset value is
-constant.
+Note that the ``$adff`` and ``$sdff`` cells can only be used when the reset
+value is constant.
 
 D-type flip-flops with asynchronous load are represented by ``$aldff`` cells. As
 the ``$dff`` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they
@@ -332,11 +337,11 @@ cells.
 Memories
 ~~~~~~~~
 
-Memories are either represented using RTLIL::Memory objects, ``$memrd_v2``,
+Memories are either represented using ``RTLIL::Memory`` objects, ``$memrd_v2``,
 ``$memwr_v2``, and ``$meminit_v2`` cells, or by ``$mem_v2`` cells alone.
 
-In the first alternative the RTLIL::Memory objects hold the general metadata for
-the memory (bit width, size in number of words, etc.) and for each port a
+In the first alternative the ``RTLIL::Memory`` objects hold the general metadata
+for the memory (bit width, size in number of words, etc.) and for each port a
 ``$memrd_v2`` (read port) or ``$memwr_v2`` (write port) cell is created. Having
 individual cells for read and write ports has the advantage that they can be
 consolidated using resource sharing passes. In some cases this drastically
@@ -351,7 +356,7 @@ address input ``\ADDR``, a data output ``\DATA``, an asynchronous reset input
 parameters:
 
 ``\MEMID``
-	The name of the RTLIL::Memory object that is associated with this read
+	The name of the ``RTLIL::Memory`` object that is associated with this read
 	port.
 
 ``\ABITS``
@@ -411,7 +416,7 @@ The ``$memwr_v2`` cells have a clock input ``\CLK``, an enable input ``\EN``
 ``\DATA``. They also have the following parameters:
 
 ``\MEMID``
-	The name of the RTLIL::Memory object that is associated with this write
+	The name of the ``RTLIL::Memory`` object that is associated with this write
 	port.
 
 ``\ABITS``
@@ -431,16 +436,17 @@ The ``$memwr_v2`` cells have a clock input ``\CLK``, an enable input ``\EN``
 	``1'b1`` and on the negative edge if this parameter is ``1'b0``.
 
 ``\PORTID``
-	An identifier for this write port, used to index write port bit mask parameters.
+	An identifier for this write port, used to index write port bit mask
+	parameters.
 
 ``\PRIORITY_MASK``
-	This parameter is a bitmask of write ports that this write port has
-	priority over in case of writing to the same address.  The bits of this
-	parameter are indexed by the other write port's ``\PORTID`` parameter.
-	Write ports can only have priority over write ports with lower port ID.
-	When two ports write to the same address and neither has priority over
-	the other, the result is undefined.  Priority can only be set between
-	two synchronous ports sharing the same clock domain.
+	This parameter is a bitmask of write ports that this write port has priority
+	over in case of writing to the same address.  The bits of this parameter are
+	indexed by the other write port's ``\PORTID`` parameter. Write ports can
+	only have priority over write ports with lower port ID. When two ports write
+	to the same address and neither has priority over the other, the result is
+	undefined.  Priority can only be set between two synchronous ports sharing
+	the same clock domain.
 
 The ``$meminit_v2`` cells have an address input ``\ADDR``, a data input
 ``\DATA``, with the width of the ``\DATA`` port equal to ``\WIDTH`` parameter
@@ -449,7 +455,7 @@ to ``\WIDTH`` parameter. All three of the inputs must resolve to a constant for
 synthesis to succeed.
 
 ``\MEMID``
-	The name of the RTLIL::Memory object that is associated with this
+	The name of the ``RTLIL::Memory`` object that is associated with this
 	initialization cell.
 
 ``\ABITS``
@@ -465,19 +471,19 @@ synthesis to succeed.
 	The cell with the higher integer value in this parameter wins an
 	initialization conflict.
 
-The HDL frontend models a memory using RTLIL::Memory objects and asynchronous
-``$memrd_v2`` and ``$memwr_v2`` cells. The ``memory`` pass (i.e.~its various
-sub-passes) migrates ``$dff`` cells into the ``$memrd_v2`` and ``$memwr_v2``
-cells making them synchronous, then converts them to a single ``$mem_v2`` cell
-and (optionally) maps this cell type to ``$dff`` cells for the individual words
-and multiplexer-based address decoders for the read and write interfaces. When
-the last step is disabled or not possible, a ``$mem_v2`` cell is left in the
-design.
+The HDL frontend models a memory using ``RTLIL::Memory`` objects and
+asynchronous ``$memrd_v2`` and ``$memwr_v2`` cells. The :cmd:ref:`memory` pass
+(i.e. its various sub-passes) migrates ``$dff`` cells into the ``$memrd_v2`` and
+``$memwr_v2`` cells making them synchronous, then converts them to a single
+``$mem_v2`` cell and (optionally) maps this cell type to ``$dff`` cells for the
+individual words and multiplexer-based address decoders for the read and write
+interfaces. When the last step is disabled or not possible, a ``$mem_v2`` cell
+is left in the design.
 
 The ``$mem_v2`` cell provides the following parameters:
 
 ``\MEMID``
-	The name of the original RTLIL::Memory object that became this
+	The name of the original ``RTLIL::Memory`` object that became this
 	``$mem_v2`` cell.
 
 ``\SIZE``
@@ -598,21 +604,107 @@ The ``$mem_v2`` cell has the following ports:
 	This input is ``\WR_PORTS*\WIDTH`` bits wide, containing all data
 	signals for the write ports.
 
-The ``memory_collect`` pass can be used to convert discrete ``$memrd_v2``,
-``$memwr_v2``, and ``$meminit_v2`` cells belonging to the same memory to a
-single ``$mem_v2`` cell, whereas the ``memory_unpack`` pass performs the inverse
-operation. The ``memory_dff`` pass can combine asynchronous memory ports that
-are fed by or feeding registers into synchronous memory ports. The
-``memory_bram`` pass can be used to recognize ``$mem_v2`` cells that can be
-implemented with a block RAM resource on an FPGA. The ``memory_map`` pass can be
-used to implement ``$mem_v2`` cells as basic logic: word-wide DFFs and address
-decoders.
+The :cmd:ref:`memory_collect` pass can be used to convert discrete
+``$memrd_v2``, ``$memwr_v2``, and ``$meminit_v2`` cells belonging to the same
+memory to a single ``$mem_v2`` cell, whereas the :cmd:ref:`memory_unpack` pass
+performs the inverse operation. The :cmd:ref:`memory_dff` pass can combine
+asynchronous memory ports that are fed by or feeding registers into synchronous
+memory ports. The :cmd:ref:`memory_bram` pass can be used to recognize
+``$mem_v2`` cells that can be implemented with a block RAM resource on an FPGA.
+The :cmd:ref:`memory_map` pass can be used to implement ``$mem_v2`` cells as
+basic logic: word-wide DFFs and address decoders.
 
 Finite state machines
 ~~~~~~~~~~~~~~~~~~~~~
 
 Add a brief description of the ``$fsm`` cell type.
 
+Coarse arithmetics
+~~~~~~~~~~~~~~~~~~~~~
+
+The ``$macc`` cell type represents a generalized multiply and accumulate operation. The cell is purely combinational. It outputs the result of summing up a sequence of products and other injected summands.
+
+.. code-block::
+
+	Y = 0 +- a0factor1 * a0factor2 +- a1factor1 * a1factor2 +- ...
+	     + B[0] + B[1] + ...
+
+The A port consists of concatenated pairs of multiplier inputs ("factors").
+A zero length factor2 acts as a constant 1, turning factor1 into a simple summand.
+
+In this pseudocode, ``u(foo)`` means an unsigned int that's foo bits long.
+
+.. code-block::
+
+	struct A {
+		u(CONFIG.mul_info[0].factor1_len) a0factor1;
+		u(CONFIG.mul_info[0].factor2_len) a0factor2;
+		u(CONFIG.mul_info[1].factor1_len) a1factor1;
+		u(CONFIG.mul_info[1].factor2_len) a1factor2;
+		...
+	};
+
+The cell's ``CONFIG`` parameter determines the layout of cell port ``A``.
+The CONFIG parameter carries the following information:
+
+.. code-block::
+
+	struct CONFIG {
+		u4 num_bits;
+		struct mul_info {
+			bool is_signed;
+			bool is_subtract;
+			u(num_bits) factor1_len;
+			u(num_bits) factor2_len;
+		}[num_ports];
+	};
+
+B is an array of concatenated 1-bit-wide unsigned integers to also be summed up.
+
+Arbitrary logic functions
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The ``$lut`` cell type implements a single-output LUT (lookup table).
+It implements an arbitrary logic function with its ``\LUT`` parameter to map
+input port ``\A`` to values of ``\Y`` output port values.
+In psuedocode: ``Y = \LUT[A]``.
+``\A`` has width set by parameter ``\WIDTH`` and ``\Y`` has a width of 1.
+Every logic function with a single bit output has a unique ``$lut``
+representation.
+
+The ``$sop`` cell type implements a sum-of-products expression, also known
+as disjunctive normal form (DNF). It implements an arbitrary logic function.
+Its structure mimics a programmable logic array (PLA).
+Output port ``\Y`` is the sum of products of the bits of the input port ``\A``
+as defined by parameter ``\TABLE``. ``\A`` is ``\WIDTH`` bits wide.
+The number of products in the sum is set by parameter ``\DEPTH``, and each
+product has two bits for each input bit - for the presence of the
+unnegated and negated version of said input bit in the product.
+Therefore the ``\TABLE`` parameter holds ``2 * \WIDTH * \DEPTH`` bits.
+
+For example:
+
+Let ``\WIDTH`` be 3. We would like to represent ``\Y =~\A[0] + \A[1]~\A[2]``.
+There are 2 products to be summed, so ``\DEPTH`` shall be 2.
+
+.. code-block::
+
+    ~A[2]-----+
+     A[2]----+|
+    ~A[1]---+||
+     A[1]--+|||
+    ~A[0]-+||||
+     A[0]+||||| 
+         |||||| product formula
+         010000 ~\A[0]
+         001001 \A[1]~\A[2]
+
+So the value of ``\TABLE`` will become ``010000001001``.
+
+Any logic function with a single bit output can be represented with
+``$sop`` but may have variously minimized or ordered summands represented
+in the ``\TABLE`` values.
+
 Specify rules
 ~~~~~~~~~~~~~
 
@@ -621,12 +713,141 @@ Add information about ``$specify2``, ``$specify3``, and ``$specrule`` cells.
 Formal verification cells
 ~~~~~~~~~~~~~~~~~~~~~~~~~
 
-Add information about ``$assert``, ``$assume``, ``$live``, ``$fair``,
+Add information about ``$check``, ``$assert``, ``$assume``, ``$live``, ``$fair``,
 ``$cover``, ``$equiv``, ``$initstate``, ``$anyconst``, ``$anyseq``,
 ``$anyinit``, ``$allconst``, ``$allseq`` cells.
 
 Add information about ``$ff`` and ``$_FF_`` cells.
 
+Debugging cells
+~~~~~~~~~~~~~~~
+
+The ``$print`` cell is used to log the values of signals, akin to (and
+translatable to) the ``$display`` and ``$write`` family of tasks in Verilog.  It
+has the following parameters:
+
+``\FORMAT``
+	The internal format string.  The syntax is described below.
+
+``\ARGS_WIDTH``
+	The width (in bits) of the signal on the ``\ARGS`` port.
+
+``\TRG_ENABLE``
+	True if triggered on specific signals defined in ``\TRG``; false if
+	triggered whenever ``\ARGS`` or ``\EN`` change and ``\EN`` is 1.
+
+If ``\TRG_ENABLE`` is true, the following parameters also apply:
+
+``\TRG_WIDTH``
+	The number of bits in the ``\TRG`` port.
+
+``\TRG_POLARITY``
+	For each bit in ``\TRG``, 1 if that signal is positive-edge triggered, 0 if
+	negative-edge triggered.
+
+``\PRIORITY``
+	When multiple ``$print`` or ``$$check`` cells fire on the same trigger, they\
+	execute in descending priority order.
+
+Ports:
+
+``\TRG``
+	The signals that control when this ``$print`` cell is triggered.
+	If the width of this port is zero and ``\TRG_ENABLE`` is true, the cell is
+	triggered during initial evaluation (time zero) only.
+
+``\EN``
+	Enable signal for the whole cell.
+
+``\ARGS``
+	The values to be displayed, in format string order.
+
+Format string syntax
+^^^^^^^^^^^^^^^^^^^^
+
+The format string syntax resembles Python f-strings.  Regular text is passed
+through unchanged until a format specifier is reached, starting with a ``{``.
+
+Format specifiers have the following syntax.  Unless noted, all items are
+required:
+
+``{``
+	Denotes the start of the format specifier.
+
+size
+	Signal size in bits; this many bits are consumed from the ``\ARGS`` port by
+	this specifier.
+
+``:``
+	Separates the size from the remaining items.
+
+justify
+	``>`` for right-justified, ``<`` for left-justified.
+
+padding
+	``0`` for zero-padding, or a space for space-padding.
+
+width\ *?*
+	(optional) The number of characters wide to pad to.
+
+base
+	* ``b`` for base-2 integers (binary)
+	* ``o`` for base-8 integers	(octal)
+	* ``d`` for base-10 integers (decimal)
+	* ``h`` for base-16	integers (hexadecimal)
+	* ``c`` for ASCII characters/strings
+	* ``t`` and ``r`` for simulation time (corresponding to :verilog:`$time` and :verilog:`$realtime`)
+
+For integers, this item may follow:
+
+``+``\ *?*
+	(optional, decimals only) Include a leading plus for non-negative numbers.
+	This can assist with symmetry with negatives in tabulated output.
+
+signedness
+	``u`` for unsigned, ``s`` for signed.  This distinction is only respected
+	when rendering decimals.
+
+ASCII characters/strings have no special options, but the signal size must be
+divisible by 8.
+
+For simulation time, the signal size must be zero.
+
+Finally:
+
+``}``
+	Denotes the end of the format specifier.
+
+Some example format specifiers:
+
++ ``{8:>02hu}`` - 8-bit unsigned integer rendered as hexadecimal,
+  right-justified, zero-padded to 2 characters wide.
++ ``{32:< 15d+s}`` - 32-bit signed integer rendered as decimal, left-justified,
+  space-padded to 15 characters wide, positive values prefixed with ``+``.
++ ``{16:< 10hu}`` - 16-bit unsigned integer rendered as hexadecimal,
+  left-justified, space-padded to 10 characters wide.
++ ``{0:>010t}`` - simulation time, right-justified, zero-padded to 10 characters
+  wide.
+
+To include literal ``{`` and ``}`` characters in your format string, use ``{{``
+and ``}}`` respectively.
+
+It is an error for a format string to consume more or less bits from ``\ARGS``
+than the port width.
+
+Values are never truncated, regardless of the specified width.
+
+Note that further restrictions on allowable combinations of options may apply
+depending on the backend used.
+
+For example, Verilog does not have a format specifier that allows zero-padding a
+string (i.e. more than 1 ASCII character), though zero-padding a single
+character is permitted.
+
+Thus, while the RTLIL format specifier ``{8:>02c}`` translates to ``%02c``,
+``{16:>02c}`` cannot be represented in Verilog and will fail to emit.  In this
+case, ``{16:> 02c}`` must be used, which translates to ``%2s``.
+
 .. _sec:celllib_gates:
 
 Gates
@@ -814,17 +1035,17 @@ techlibs/common/simcells.v in the Yosys source tree.
 	============== ============== =========
 
 
-Tables \ :numref:`%s <tab:CellLib_gates>`, :numref:`%s
-<tab:CellLib_gates_dffe>`, :numref:`%s <tab:CellLib_gates_adff>`, :numref:`%s
-<tab:CellLib_gates_adffe>`, :numref:`%s <tab:CellLib_gates_dffsr>`, :numref:`%s
-<tab:CellLib_gates_dffsre>`, :numref:`%s <tab:CellLib_gates_adlatch>`,
-:numref:`%s <tab:CellLib_gates_dlatchsr>` and :numref:`%s
-<tab:CellLib_gates_sr>` list all cell types used for gate level logic. The cell
-types ``$_BUF_``, ``$_NOT_``, ``$_AND_``, ``$_NAND_``, ``$_ANDNOT_``, ``$_OR_``,
-``$_NOR_``, ``$_ORNOT_``, ``$_XOR_``, ``$_XNOR_``, ``$_AOI3_``, ``$_OAI3_``,
-``$_AOI4_``, ``$_OAI4_``, ``$_MUX_``, ``$_MUX4_``, ``$_MUX8_``, ``$_MUX16_`` and
-``$_NMUX_`` are used to model combinatorial logic. The cell type ``$_TBUF_`` is
-used to model tristate logic.
+Tables :numref:`%s <tab:CellLib_gates>`, :numref:`%s <tab:CellLib_gates_dffe>`,
+:numref:`%s <tab:CellLib_gates_adff>`, :numref:`%s <tab:CellLib_gates_adffe>`,
+:numref:`%s <tab:CellLib_gates_dffsr>`, :numref:`%s <tab:CellLib_gates_dffsre>`,
+:numref:`%s <tab:CellLib_gates_adlatch>`, :numref:`%s
+<tab:CellLib_gates_dlatchsr>` and :numref:`%s <tab:CellLib_gates_sr>` list all
+cell types used for gate level logic. The cell types ``$_BUF_``, ``$_NOT_``,
+``$_AND_``, ``$_NAND_``, ``$_ANDNOT_``, ``$_OR_``, ``$_NOR_``, ``$_ORNOT_``,
+``$_XOR_``, ``$_XNOR_``, ``$_AOI3_``, ``$_OAI3_``, ``$_AOI4_``, ``$_OAI4_``,
+``$_MUX_``, ``$_MUX4_``, ``$_MUX8_``, ``$_MUX16_`` and ``$_NMUX_`` are used to
+model combinatorial logic. The cell type ``$_TBUF_`` is used to model tristate
+logic.
 
 The ``$_MUX4_``, ``$_MUX8_`` and ``$_MUX16_`` cells are used to model wide
 muxes, and correspond to the following Verilog code:
@@ -1013,8 +1234,8 @@ mapped to physical flip-flop cells from a Liberty file using the dfflibmap pass.
 The combinatorial logic cells can be mapped to physical cells from a Liberty
 file via ABC using the abc pass.
 
-Add information about ``$slice`` and ``$concat`` cells.
+.. todo:: Add information about ``$slice`` and ``$concat`` cells.
 
-Add information about ``$lut`` and ``$sop`` cells.
+.. todo:: Add information about ``$alu``, ``$fa``, and ``$lcu`` cells.
 
-Add information about ``$alu``, ``$macc``, ``$fa``, and ``$lcu`` cells.
+.. todo:: Add information about ``$demux`` cell.
\ No newline at end of file
diff --git a/yosys/docs/source/yosys_internals/formats/index.rst b/yosys/docs/source/yosys_internals/formats/index.rst
new file mode 100644
index 00000000000..c187a8238a8
--- /dev/null
+++ b/yosys/docs/source/yosys_internals/formats/index.rst
@@ -0,0 +1,13 @@
+Internal formats
+================
+
+.. todo:: brief overview for the internal formats index
+
+.. toctree:: 
+	:maxdepth: 3
+
+	overview
+	rtlil_rep
+	rtlil_text
+	cell_library
+
diff --git a/yosys/docs/source/yosys_internals/formats/overview.rst b/yosys/docs/source/yosys_internals/formats/overview.rst
new file mode 100644
index 00000000000..cbf5369bc06
--- /dev/null
+++ b/yosys/docs/source/yosys_internals/formats/overview.rst
@@ -0,0 +1,53 @@
+Format overview
+===============
+
+Yosys uses two different internal formats. The first is used to store an
+abstract syntax tree (AST) of a Verilog input file. This format is simply called
+AST and is generated by the Verilog Frontend. This data structure is consumed by
+a subsystem called AST Frontend [1]_. This AST Frontend then generates a design
+in Yosys' main internal format, the
+Register-Transfer-Level-Intermediate-Language (RTLIL) representation. It does
+that by first performing a number of simplifications within the AST
+representation and then generating RTLIL from the simplified AST data structure.
+
+The RTLIL representation is used by all passes as input and outputs. This has
+the following advantages over using different representational formats between
+different passes:
+
+-  The passes can be rearranged in a different order and passes can be removed
+   or inserted.
+
+-  Passes can simply pass-thru the parts of the design they don't change without
+   the need to convert between formats. In fact Yosys passes output the same
+   data structure they received as input and performs all changes in place.
+
+-  All passes use the same interface, thus reducing the effort required to
+   understand a pass when reading the Yosys source code, e.g. when adding
+   additional features.
+
+The RTLIL representation is basically a netlist representation with the
+following additional features:
+
+-  An internal cell library with fixed-function cells to represent RTL datapath
+   and register cells as well as logical gate-level cells (single-bit gates and
+   registers).
+
+-  Support for multi-bit values that can use individual bits from wires as well
+   as constant bits to represent coarse-grain netlists.
+
+-  Support for basic behavioural constructs (if-then-else structures and
+   multi-case switches with a sensitivity list for updating the outputs).
+
+-  Support for multi-port memories.
+
+The use of RTLIL also has the disadvantage of having a very powerful format
+between all passes, even when doing gate-level synthesis where the more advanced
+features are not needed. In order to reduce complexity for passes that operate
+on a low-level representation, these passes check the features used in the input
+RTLIL and fail to run when unsupported high-level constructs are used. In such
+cases a pass that transforms the higher-level constructs to lower-level
+constructs must be called from the synthesis script first.
+
+.. [1]
+   In Yosys the term pass is only used to refer to commands that operate on the
+   RTLIL data structure.
\ No newline at end of file
diff --git a/yosys/docs/source/yosys_internals/formats/rtlil_rep.rst b/yosys/docs/source/yosys_internals/formats/rtlil_rep.rst
new file mode 100644
index 00000000000..2737cd4bd46
--- /dev/null
+++ b/yosys/docs/source/yosys_internals/formats/rtlil_rep.rst
@@ -0,0 +1,416 @@
+The RTL Intermediate Language (RTLIL)
+=====================================
+
+All frontends, passes and backends in Yosys operate on a design in RTLIL
+representation. The only exception are the high-level frontends that use the AST
+representation as an intermediate step before generating RTLIL data.
+
+In order to avoid reinventing names for the RTLIL classes, they are simply
+referred to by their full C++ name, i.e. including the ``RTLIL::`` namespace
+prefix, in this document.
+
+:numref:`Figure %s <fig:Overview_RTLIL>` shows a simplified Entity-Relationship
+Diagram (ER Diagram) of RTLIL. In :math:`1:N` relationships the arrow points
+from the :math:`N` side to the :math:`1`. For example one ``RTLIL::Design``
+contains :math:`N` (zero to many) instances of ``RTLIL::Module`` . A two-pointed
+arrow indicates a :math:`1:1` relationship.
+
+The ``RTLIL::Design`` is the root object of the RTLIL data structure. There is
+always one "current design" in memory which passes operate on, frontends add
+data to and backends convert to exportable formats. But in some cases passes
+internally generate additional ``RTLIL::Design`` objects. For example when a
+pass is reading an auxiliary Verilog file such as a cell library, it might
+create an additional ``RTLIL::Design`` object and call the Verilog frontend with
+this other object to parse the cell library.
+
+.. figure:: /_images/internals/overview_rtlil.*
+	:class: width-helper invert-helper
+	:name: fig:Overview_RTLIL
+
+	Simplified RTLIL Entity-Relationship Diagram
+
+There is only one active ``RTLIL::Design`` object that is used by all frontends,
+passes and backends called by the user, e.g. using a synthesis script. The
+``RTLIL::Design`` then contains zero to many ``RTLIL::Module`` objects. This
+corresponds to modules in Verilog or entities in VHDL. Each module in turn
+contains objects from three different categories:
+
+-  ``RTLIL::Cell`` and ``RTLIL::Wire`` objects represent classical netlist data.
+
+-  ``RTLIL::Process`` objects represent the decision trees (if-then-else statements,
+   etc.) and synchronization declarations (clock signals and sensitivity) from
+   Verilog always and VHDL process blocks.
+
+-  ``RTLIL::Memory`` objects represent addressable memories (arrays).
+
+Usually the output of the synthesis procedure is a netlist, i.e. all
+``RTLIL::Process`` and ``RTLIL::Memory`` objects must be replaced by
+``RTLIL::Cell`` and ``RTLIL::Wire`` objects by synthesis passes.
+
+All features of the HDL that cannot be mapped directly to these RTLIL classes
+must be transformed to an RTLIL-compatible representation by the HDL frontend.
+This includes Verilog-features such as generate-blocks, loops and parameters.
+
+The following sections contain a more detailed description of the different
+parts of RTLIL and rationale behind some of the design decisions.
+
+RTLIL identifiers
+-----------------
+
+All identifiers in RTLIL (such as module names, port names, signal names, cell
+types, etc.) follow the following naming convention: they must either start with
+a backslash (``\``) or a dollar sign (``$``).
+
+Identifiers starting with a backslash are public visible identifiers. Usually
+they originate from one of the HDL input files. For example the signal name
+``\sig42`` is most likely a signal that was declared using the name ``sig42`` in
+an HDL input file. On the other hand the signal name ``$sig42`` is an
+auto-generated signal name. The backends convert all identifiers that start with
+a dollar sign to identifiers that do not collide with identifiers that start
+with a backslash.
+
+This has three advantages:
+
+-  First, it is impossible that an auto-generated identifier collides with an
+   identifier that was provided by the user.
+
+-  Second, the information about which identifiers were originally provided by
+   the user is always available which can help guide some optimizations. For
+   example, :cmd:ref:`opt_clean` tries to preserve signals with a user-provided
+   name but doesn't hesitate to delete signals that have auto-generated names
+   when they just duplicate other signals.  Note that this can be overridden
+   with the `-purge` option to also delete internal nets with user-provided
+   names.
+
+-  Third, the delicate job of finding suitable auto-generated public visible
+   names is deferred to one central location. Internally auto-generated names
+   that may hold important information for Yosys developers can be used without
+   disturbing external tools. For example the Verilog backend assigns names in
+   the form ``_123_``.
+
+Whitespace and control characters (any character with an ASCII code 32 or less)
+are not allowed in RTLIL identifiers; most frontends and backends cannot support
+these characters in identifiers.
+
+In order to avoid programming errors, the RTLIL data structures check if all
+identifiers start with either a backslash or a dollar sign, and contain no
+whitespace or control characters. Violating these rules results in a runtime
+error.
+
+All RTLIL identifiers are case sensitive.
+
+Some transformations, such as flattening, may have to change identifiers
+provided by the user to avoid name collisions. When that happens, attribute
+``hdlname`` is attached to the object with the changed identifier. This
+attribute contains one name (if emitted directly by the frontend, or is a result
+of disambiguation) or multiple names separated by spaces (if a result of
+flattening). All names specified in the ``hdlname`` attribute are public and do
+not include the leading ``\``.
+
+RTLIL::Design and RTLIL::Module
+-------------------------------
+
+The ``RTLIL::Design`` object is basically just a container for ``RTLIL::Module``
+objects. In addition to a list of ``RTLIL::Module`` objects the
+``RTLIL::Design`` also keeps a list of selected objects, i.e. the objects that
+passes should operate on. In most cases the whole design is selected and
+therefore passes operate on the whole design. But this mechanism can be useful
+for more complex synthesis jobs in which only parts of the design should be
+affected by certain passes.
+
+Besides the objects shown in the :ref:`ER diagram <fig:Overview_RTLIL>` above,
+an ``RTLIL::Module`` object contains the following additional properties:
+
+-  The module name
+-  A list of attributes
+-  A list of connections between wires
+-  An optional frontend callback used to derive parametrized variations of the
+   module
+
+The attributes can be Verilog attributes imported by the Verilog frontend or
+attributes assigned by passes. They can be used to store additional metadata
+about modules or just mark them to be used by certain part of the synthesis
+script but not by others.
+
+Verilog and VHDL both support parametric modules (known as "generic entities" in
+VHDL). The RTLIL format does not support parametric modules itself. Instead each
+module contains a callback function into the AST frontend to generate a
+parametrized variation of the ``RTLIL::Module`` as needed. This callback then
+returns the auto-generated name of the parametrized variation of the module. (A
+hash over the parameters and the module name is used to prohibit the same
+parametrized variation from being generated twice. For modules with only a few
+parameters, a name directly containing all parameters is generated instead of a
+hash string.)
+
+.. _sec:rtlil_cell_wire:
+
+RTLIL::Cell and RTLIL::Wire
+---------------------------
+
+A module contains zero to many ``RTLIL::Cell`` and ``RTLIL::Wire`` objects.
+Objects of these types are used to model netlists. Usually the goal of all
+synthesis efforts is to convert all modules to a state where the functionality
+of the module is implemented only by cells from a given cell library and wires
+to connect these cells with each other. Note that module ports are just wires
+with a special property.
+
+An ``RTLIL::Wire`` object has the following properties:
+
+-  The wire name
+-  A list of attributes
+-  A width (buses are just wires with a width more than 1)
+-  Bus direction (MSB to LSB or vice versa)
+-  Lowest valid bit index (LSB or MSB depending on bus direction)
+-  If the wire is a port: port number and direction (input/output/inout)
+
+As with modules, the attributes can be Verilog attributes imported by the
+Verilog frontend or attributes assigned by passes.
+
+In Yosys, busses (signal vectors) are represented using a single wire object
+with a width more than 1. So Yosys does not convert signal vectors to individual
+signals. This makes some aspects of RTLIL more complex but enables Yosys to be
+used for coarse grain synthesis where the cells of the target architecture
+operate on entire signal vectors instead of single bit wires.
+
+In Verilog and VHDL, busses may have arbitrary bounds, and LSB can have either
+the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSB;
+however, information from the HDL frontend is preserved so that the bus will be
+correctly indexed in error messages, backend output, constraint files, etc.
+
+An ``RTLIL::Cell`` object has the following properties:
+
+-  The cell name and type
+-  A list of attributes
+-  A list of parameters (for parametric cells)
+-  Cell ports and the connections of ports to wires and constants
+
+The connections of ports to wires are coded by assigning an ``RTLIL::SigSpec``
+to each cell port. The ``RTLIL::SigSpec`` data type is described in the next
+section.
+
+.. _sec:rtlil_sigspec:
+
+RTLIL::SigSpec
+--------------
+
+A "signal" is everything that can be applied to a cell port. I.e.
+
+-  | Any constant value of arbitrary bit-width
+   | 1em For example: ``1337, 16'b0000010100111001, 1'b1, 1'bx``
+
+-  | All bits of a wire or a selection of bits from a wire
+   | 1em For example: ``mywire, mywire[24], mywire[15:8]``
+
+-  | Concatenations of the above
+   | 1em For example: ``{16'd1337, mywire[15:8]}``
+
+The ``RTLIL::SigSpec`` data type is used to represent signals. The ``RTLIL::Cell``
+object contains one ``RTLIL::SigSpec`` for each cell port.
+
+In addition, connections between wires are represented using a pair of
+``RTLIL::SigSpec`` objects. Such pairs are needed in different locations.
+Therefore the type name ``RTLIL::SigSig`` was defined for such a pair.
+
+.. _sec:rtlil_process:
+
+RTLIL::Process
+--------------
+
+When a high-level HDL frontend processes behavioural code it splits it up into
+data path logic (e.g. the expression ``a + b`` is replaced by the output of an
+adder that takes a and b as inputs) and an ``RTLIL::Process`` that models the
+control logic of the behavioural code. Let's consider a simple example:
+
+.. code:: verilog
+   :number-lines:
+
+   module ff_with_en_and_async_reset(clock, reset, enable, d, q);
+   input clock, reset, enable, d;
+   output reg q;
+   always @(posedge clock, posedge reset)
+       if (reset)
+           q <= 0;
+       else if (enable)
+           q <= d;
+   endmodule
+
+In this example there is no data path and therefore the ``RTLIL::Module`` generated
+by the frontend only contains a few ``RTLIL::Wire`` objects and an ``RTLIL::Process`` .
+The ``RTLIL::Process`` in RTLIL syntax:
+
+.. code:: RTLIL
+   :number-lines:
+
+   process $proc$ff_with_en_and_async_reset.v:4$1
+       assign $0\q[0:0] \q
+       switch \reset
+           case 1'1
+               assign $0\q[0:0] 1'0
+           case
+               switch \enable
+                   case 1'1
+                       assign $0\q[0:0] \d
+                   case
+               end
+       end
+       sync posedge \clock
+           update \q $0\q[0:0]
+       sync posedge \reset
+           update \q $0\q[0:0]
+   end
+
+This ``RTLIL::Process`` contains two ``RTLIL::SyncRule`` objects, two
+``RTLIL::SwitchRule`` objects and five ``RTLIL::CaseRule`` objects. The wire
+``$0\q[0:0]`` is an automatically created wire that holds the next value of
+``\q``. The lines 2..12 describe how ``$0\q[0:0]`` should be calculated. The
+lines 13..16 describe how the value of ``$0\q[0:0]`` is used to update ``\q``.
+
+An ``RTLIL::Process`` is a container for zero or more ``RTLIL::SyncRule``
+objects and exactly one ``RTLIL::CaseRule`` object, which is called the root
+case.
+
+An ``RTLIL::SyncRule`` object contains an (optional) synchronization condition
+(signal and edge-type), zero or more assignments (``RTLIL::SigSig``), and zero
+or more memory writes (``RTLIL::MemWriteAction``). The always synchronization
+condition is used to break combinatorial loops when a latch should be inferred
+instead.
+
+An ``RTLIL::CaseRule`` is a container for zero or more assignments
+(``RTLIL::SigSig``) and zero or more ``RTLIL::SwitchRule`` objects. An
+``RTLIL::SwitchRule`` objects is a container for zero or more
+``RTLIL::CaseRule`` objects.
+
+In the above example the lines 2..12 are the root case. Here ``$0\q[0:0]`` is
+first assigned the old value ``\q`` as default value (line 2). The root case
+also contains an ``RTLIL::SwitchRule`` object (lines 3..12). Such an object is
+very similar to the C switch statement as it uses a control signal (``\reset``
+in this case) to determine which of its cases should be active. The
+``RTLIL::SwitchRule`` object then contains one ``RTLIL::CaseRule`` object per
+case. In this example there is a case [1]_ for ``\reset == 1`` that causes
+``$0\q[0:0]`` to be set (lines 4 and 5) and a default case that in turn contains
+a switch that sets ``$0\q[0:0]`` to the value of ``\d`` if ``\enable`` is active
+(lines 6..11).
+
+A case can specify zero or more compare values that will determine whether it
+matches. Each of the compare values must be the exact same width as the control
+signal. When more than one compare value is specified, the case matches if any
+of them matches the control signal; when zero compare values are specified, the
+case always matches (i.e. it is the default case).
+
+A switch prioritizes cases from first to last: multiple cases can match, but
+only the first matched case becomes active. This normally synthesizes to a
+priority encoder. The parallel_case attribute allows passes to assume that no
+more than one case will match, and full_case attribute allows passes to assume
+that exactly one case will match; if these invariants are ever dynamically
+violated, the behavior is undefined. These attributes are useful when an
+invariant invisible to the synthesizer causes the control signal to never take
+certain bit patterns.
+
+The lines 13..16 then cause ``\q`` to be updated whenever there is a positive
+clock edge on ``\clock`` or ``\reset``.
+
+In order to generate such a representation, the language frontend must be able
+to handle blocking and nonblocking assignments correctly. However, the language
+frontend does not need to identify the correct type of storage element for the
+output signal or generate multiplexers for the decision tree. This is done by
+passes that work on the RTLIL representation. Therefore it is relatively easy to
+substitute these steps with other algorithms that target different target
+architectures or perform optimizations or other transformations on the decision
+trees before further processing them.
+
+One of the first actions performed on a design in RTLIL representation in most
+synthesis scripts is identifying asynchronous resets. This is usually done using
+the :cmd:ref:`proc_arst` pass. This pass transforms the above example to the
+following ``RTLIL::Process``:
+
+.. code:: RTLIL
+   :number-lines:
+
+   process $proc$ff_with_en_and_async_reset.v:4$1
+       assign $0\q[0:0] \q
+       switch \enable
+           case 1'1
+               assign $0\q[0:0] \d
+           case
+       end
+       sync posedge \clock
+           update \q $0\q[0:0]
+       sync high \reset
+           update \q 1'0
+   end
+
+This pass has transformed the outer ``RTLIL::SwitchRule`` into a modified
+``RTLIL::SyncRule`` object for the ``\reset`` signal. Further processing converts the
+``RTLIL::Process`` into e.g. a d-type flip-flop with asynchronous reset and a
+multiplexer for the enable signal:
+
+.. code:: RTLIL
+   :number-lines:
+
+   cell $adff $procdff$6
+       parameter \ARST_POLARITY 1'1
+       parameter \ARST_VALUE 1'0
+       parameter \CLK_POLARITY 1'1
+       parameter \WIDTH 1
+       connect \ARST \reset
+       connect \CLK \clock
+       connect \D $0\q[0:0]
+       connect \Q \q
+   end
+   cell $mux $procmux$3
+       parameter \WIDTH 1
+       connect \A \q
+       connect \B \d
+       connect \S \enable
+       connect \Y $0\q[0:0]
+   end
+
+Different combinations of passes may yield different results. Note that
+``$adff`` and ``$mux`` are internal cell types that still need to be mapped to
+cell types from the target cell library.
+
+Some passes refuse to operate on modules that still contain ``RTLIL::Process`` 
+objects as the presence of these objects in a module increases the complexity.
+Therefore the passes to translate processes to a netlist of cells are usually
+called early in a synthesis script. The proc pass calls a series of other passes
+that together perform this conversion in a way that is suitable for most
+synthesis tasks.
+
+.. _sec:rtlil_memory:
+
+RTLIL::Memory
+-------------
+
+For every array (memory) in the HDL code an ``RTLIL::Memory`` object is created.
+A memory object has the following properties:
+
+-  The memory name
+-  A list of attributes
+-  The width of an addressable word
+-  The size of the memory in number of words
+
+All read accesses to the memory are transformed to ``$memrd`` cells and all
+write accesses to ``$memwr`` cells by the language frontend. These cells consist
+of independent read- and write-ports to the memory. Memory initialization is
+transformed to ``$meminit`` cells by the language frontend. The ``\MEMID``
+parameter on these cells is used to link them together and to the
+``RTLIL::Memory`` object they belong to.
+
+The rationale behind using separate cells for the individual ports versus
+creating a large multiport memory cell right in the language frontend is that
+the separate ``$memrd`` and ``$memwr`` cells can be consolidated using resource
+sharing. As resource sharing is a non-trivial optimization problem where
+different synthesis tasks can have different requirements it lends itself to do
+the optimisation in separate passes and merge the ``RTLIL::Memory`` objects and
+``$memrd`` and ``$memwr`` cells to multiport memory blocks after resource
+sharing is completed.
+
+The memory pass performs this conversion and can (depending on the options
+passed to it) transform the memories directly to d-type flip-flops and address
+logic or yield multiport memory blocks (represented using ``$mem`` cells).
+
+See :ref:`sec:memcells` for details about the memory cell types.
+
+.. [1]
+   The syntax ``1'1`` in the RTLIL code specifies a constant with a length of
+   one bit (the first ``1``), and this bit is a one (the second ``1``).
diff --git a/yosys/docs/source/appendix/CHAPTER_TextRtlil.rst b/yosys/docs/source/yosys_internals/formats/rtlil_text.rst
similarity index 92%
rename from yosys/docs/source/appendix/CHAPTER_TextRtlil.rst
rename to yosys/docs/source/yosys_internals/formats/rtlil_text.rst
index dc3d72230b9..8b5c1068120 100644
--- a/yosys/docs/source/appendix/CHAPTER_TextRtlil.rst
+++ b/yosys/docs/source/yosys_internals/formats/rtlil_text.rst
@@ -1,7 +1,7 @@
 .. _chapter:textrtlil:
 
 RTLIL text representation
-=========================
+-------------------------
 
 This appendix documents the text representation of RTLIL in extended Backus-Naur
 form (EBNF).
@@ -17,10 +17,10 @@ Finally, note that all statements (rules ending in ``-stmt``) terminate in an
 end-of-line. Because of this, a statement cannot be broken into multiple lines.
 
 Lexical elements
-----------------
+~~~~~~~~~~~~~~~~
 
 Characters
-~~~~~~~~~~
+^^^^^^^^^^
 
 An RTLIL file is a stream of bytes. Strictly speaking, a "character" in an RTLIL
 file is a single byte. The lexer treats multi-byte encoded characters as
@@ -37,7 +37,7 @@ An ``eol`` is one or more consecutive ASCII newlines (10) and carriage returns
 (13).
 
 Identifiers
-~~~~~~~~~~~
+^^^^^^^^^^^
 
 There are two types of identifiers in RTLIL:
 
@@ -51,7 +51,7 @@ There are two types of identifiers in RTLIL:
     <autogen-id>    ::= $ <nonws>+
 
 Values
-~~~~~~
+^^^^^^
 
 A *value* consists of a width in bits and a bit representation, most
 significant bit first. Bits may be any of:
@@ -76,7 +76,7 @@ error.
     <integer>       ::= -? <decimal-digit>+
 
 Strings
-~~~~~~~
+^^^^^^^
 
 A string is a series of characters delimited by double-quote characters. Within
 a string, any character except ASCII NUL (0) may be used. In addition, certain
@@ -94,13 +94,13 @@ character. Thus:
 -  ``\r``: An 'r' character
 
 Comments
-~~~~~~~~
+^^^^^^^^
 
 A comment starts with a ``#`` character and proceeds to the end of the line. All
 comments are ignored.
 
 File
-----
+~~~~
 
 A file consists of an optional autoindex statement followed by zero or more
 modules.
@@ -110,7 +110,7 @@ modules.
     <file> ::= <autoidx-stmt>? <module>*
 
 Autoindex statements
-~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^
 
 The autoindex statement sets the global autoindex value used by Yosys when it
 needs to generate a unique name, e.g. ``flattenN``. The N part is filled with
@@ -123,7 +123,7 @@ would have different properties than just running a pass on a warm design.
     <autoidx-stmt> ::= autoidx <integer> <eol>
 
 Modules
-~~~~~~~
+^^^^^^^
 
 Declares a module, with zero or more attributes, consisting of zero or more
 wires, memories, cells, processes, and connections.
@@ -142,7 +142,7 @@ wires, memories, cells, processes, and connections.
     <module-end-stmt>   ::= end <eol>
 
 Attribute statements
-~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^
 
 Declares an attribute with the given identifier and value.
 
@@ -151,7 +151,7 @@ Declares an attribute with the given identifier and value.
     <attr-stmt> ::= attribute <id> <constant> <eol>
 
 Signal specifications
-~~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^^
 
 A signal is anything that can be applied to a cell port, i.e. a constant value,
 all bits or a selection of bits from a wire, or concatenations of those.
@@ -161,8 +161,7 @@ all bits or a selection of bits from a wire, or concatenations of those.
 ``32'11111111111111111111111111111111``, while a constant of :math:`1` is the
 same as ``32'1``.
 
-See :numref:`Sec. %s <sec:rtlil_sigspec>` for an overview of signal
-specifications.
+See :ref:`sec:rtlil_sigspec` for an overview of signal specifications.
 
 .. code:: BNF
 
@@ -172,7 +171,7 @@ specifications.
                |  { <sigspec>* }
 
 Connections
-~~~~~~~~~~~
+^^^^^^^^^^^
 
 Declares a connection between the given signals.
 
@@ -181,12 +180,12 @@ Declares a connection between the given signals.
     <conn-stmt> ::= connect <sigspec> <sigspec> <eol>
 
 Wires
-~~~~~
+^^^^^
 
 Declares a wire, with zero or more attributes, with the given identifier and
 options in the enclosing module.
 
-See :numref:`Sec. %s <sec:rtlil_cell_wire>` for an overview of wires.
+See :ref:`sec:rtlil_cell_wire` for an overview of wires.
 
 .. code:: BNF
 
@@ -202,13 +201,13 @@ See :numref:`Sec. %s <sec:rtlil_cell_wire>` for an overview of wires.
                      |  signed
 
 Memories
-~~~~~~~~
+^^^^^^^^
 
 Declares a memory, with zero or more attributes, with the given identifier and
 options in the enclosing module.
 
-See :numref:`Sec. %s <sec:rtlil_memory>` for an overview of memory cells, and
-:numref:`Sec. %s <sec:memcells>` for details about memory cell types.
+See :ref:`sec:rtlil_memory` for an overview of memory cells, and
+:ref:`sec:memcells` for details about memory cell types.
 
 .. code:: BNF
 
@@ -219,13 +218,13 @@ See :numref:`Sec. %s <sec:rtlil_memory>` for an overview of memory cells, and
                      |  offset <integer>
 
 Cells
-~~~~~
+^^^^^
 
 Declares a cell, with zero or more attributes, with the given identifier and
 type in the enclosing module.
 
-Cells perform functions on input signals. See :numref:`Chap. %s
-<chapter:celllib>` for a detailed list of cell types.
+Cells perform functions on input signals. See
+:doc:`/yosys_internals/formats/cell_library` for a detailed list of cell types.
 
 .. code:: BNF
 
@@ -239,13 +238,13 @@ Cells perform functions on input signals. See :numref:`Chap. %s
 
 
 Processes
-~~~~~~~~~
+^^^^^^^^^
 
 Declares a process, with zero or more attributes, with the given identifier in
 the enclosing module. The body of a process consists of zero or more
 assignments, exactly one switch, and zero or more syncs.
 
-See :numref:`Sec. %s <sec:rtlil_process>` for an overview of processes.
+See :ref:`sec:rtlil_process` for an overview of processes.
 
 .. code:: BNF
 
@@ -258,7 +257,7 @@ See :numref:`Sec. %s <sec:rtlil_process>` for an overview of processes.
     <proc-end-stmt> ::= end <eol>
 
 Switches
-~~~~~~~~
+^^^^^^^^
 
 Switches test a signal for equality against a list of cases. Each case specifies
 a comma-separated list of signals to check against. If there are no signals in
@@ -277,7 +276,7 @@ attributes.
     <switch-end-stmt>   ::= end <eol>
 
 Syncs
-~~~~~
+^^^^^
 
 Syncs update signals with other signals when an event happens. Such an event may
 be:
diff --git a/yosys/docs/source/yosys_internals/index.rst b/yosys/docs/source/yosys_internals/index.rst
new file mode 100644
index 00000000000..b04f136995d
--- /dev/null
+++ b/yosys/docs/source/yosys_internals/index.rst
@@ -0,0 +1,40 @@
+.. _chapter:overview:
+
+Yosys internals
+===============
+
+.. todo:: less academic
+
+Yosys is an extensible open source hardware synthesis tool. It is aimed at
+designers who are looking for an easily accessible, universal, and
+vendor-independent synthesis tool, as well as scientists who do research in
+electronic design automation (EDA) and are looking for an open synthesis
+framework that can be used to test algorithms on complex real-world designs.
+
+Yosys can synthesize a large subset of Verilog 2005 and has been tested with a
+wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the
+`openMSP430 CPU`_, the `OpenCores I2C master`_, and the `k68 CPU`_.
+
+.. todo:: add RISC-V core example
+
+.. _OpenRISC 1200 CPU: https://github.com/openrisc/or1200
+
+.. _openMSP430 CPU: http://opencores.org/projects/openmsp430
+
+.. _OpenCores I2C master: http://opencores.org/projects/i2c
+
+.. _k68 CPU: http://opencores.org/projects/k68
+
+Yosys is written in C++, targeting C++11 at minimum. This chapter describes some
+of the fundamental Yosys data structures. For the sake of simplicity the C++
+type names used in the Yosys implementation are used in this chapter, even
+though the chapter only explains the conceptual idea behind it and can be used
+as reference to implement a similar system in any language.
+
+.. toctree::
+   :maxdepth: 3
+
+   flow/index
+   formats/index
+   extending_yosys/index
+   techmap
diff --git a/yosys/docs/source/yosys_internals/techmap.rst b/yosys/docs/source/yosys_internals/techmap.rst
new file mode 100644
index 00000000000..00fce26bd4f
--- /dev/null
+++ b/yosys/docs/source/yosys_internals/techmap.rst
@@ -0,0 +1,191 @@
+Techmap by example
+------------------
+
+As a quick recap, the :cmd:ref:`techmap` command replaces cells in the design
+with implementations given as Verilog code (called "map files"). It can replace
+Yosys' internal cell types (such as ``$or``) as well as user-defined cell types.
+
+- Verilog parameters are used extensively to customize the internal cell types.
+- Additional special parameters are used by techmap to communicate meta-data to
+  the map files.
+- Special wires are used to instruct techmap how to handle a module in the map
+  file.
+- Generate blocks and recursion are powerful tools for writing map files.
+
+Code examples used in this document are included in the Yosys code base under
+|code_examples/techmap|_.
+
+.. |code_examples/techmap| replace:: :file:`docs/source/code_examples/techmap`
+.. _code_examples/techmap: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/techmap
+
+
+Mapping OR3X1
+~~~~~~~~~~~~~
+
+.. todo:: add/expand supporting text
+
+.. note::
+
+    This is a simple example for demonstration only.  Techmap shouldn't be used
+    to implement basic logic optimization.
+
+.. literalinclude:: /code_examples/techmap/red_or3x1_map.v
+   :language: verilog
+   :caption: :file:`red_or3x1_map.v`
+
+.. figure:: /_images/code_examples/techmap/red_or3x1.*
+    :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/techmap/red_or3x1_test.ys
+   :language: yoscrypt
+   :caption: :file:`red_or3x1_test.ys`
+
+.. literalinclude:: /code_examples/techmap/red_or3x1_test.v
+   :language: verilog
+   :caption: :file:`red_or3x1_test.v`
+
+Conditional techmap
+~~~~~~~~~~~~~~~~~~~
+
+- In some cases only cells with certain properties should be substituted.
+- The special wire ``_TECHMAP_FAIL_`` can be used to disable a module in the map
+  file for a certain set of parameters.
+- The wire ``_TECHMAP_FAIL_`` must be set to a constant value. If it is non-zero
+  then the module is disabled for this set of parameters.
+- Example use-cases:
+
+    - coarse-grain cell types that only operate on certain bit widths
+    - memory resources for different memory geometries (width, depth, ports,
+      etc.)
+
+Example:
+
+.. figure:: /_images/code_examples/techmap/sym_mul.*
+    :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/techmap/sym_mul_map.v
+   :language: verilog
+   :caption: :file:`sym_mul_map.v`
+
+.. literalinclude:: /code_examples/techmap/sym_mul_test.v
+   :language: verilog
+   :caption: :file:`sym_mul_test.v`
+
+.. literalinclude:: /code_examples/techmap/sym_mul_test.ys
+   :language: yoscrypt
+   :caption: :file:`sym_mul_test.ys`
+
+
+Scripting in map modules
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+- The special wires ``_TECHMAP_DO_*`` can be used to run Yosys scripts in the
+  context of the replacement module.
+- The wire that comes first in alphabetical oder is interpreted as string (must
+  be connected to constants) that is executed as script. Then the wire is
+  removed. Repeat.
+- You can even call techmap recursively!
+- Example use-cases:
+
+    - Using always blocks in map module: call :cmd:ref:`proc`
+    - Perform expensive optimizations (such as :cmd:ref:`freduce`) on cells
+      where this is known to work well.
+    - Interacting with custom commands.
+
+.. note:: PROTIP:
+
+    Commands such as :cmd:ref:`shell`, ``show -pause``, and :cmd:ref:`dump` can
+    be used in the ``_TECHMAP_DO_*`` scripts for debugging map modules.
+
+Example:
+
+.. figure:: /_images/code_examples/techmap/mymul.*
+    :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/techmap/mymul_map.v
+   :language: verilog
+   :caption: :file:`mymul_map.v`
+
+.. literalinclude:: /code_examples/techmap/mymul_test.v
+   :language: verilog
+   :caption: :file:`mymul_test.v`
+
+.. literalinclude:: /code_examples/techmap/mymul_test.ys
+   :language: yoscrypt
+   :caption: :file:`mymul_test.ys`
+
+Handling constant inputs
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+- The special parameters ``_TECHMAP_CONSTMSK_<port-name>_`` and
+  ``_TECHMAP_CONSTVAL_<port-name>_`` can be used to handle constant input values
+  to cells.
+- The former contains 1-bits for all constant input bits on the port.
+- The latter contains the constant bits or undef (x) for non-constant bits.
+- Example use-cases:
+
+    - Converting arithmetic (for example multiply to shift).
+    - Identify constant addresses or enable bits in memory interfaces.
+
+Example:
+
+.. figure:: /_images/code_examples/techmap/mulshift.*
+    :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/techmap/mulshift_map.v
+   :language: verilog
+   :caption: :file:`mulshift_map.v`
+
+.. literalinclude:: /code_examples/techmap/mulshift_test.v
+   :language: verilog
+   :caption: :file:`mulshift_test.v`
+
+.. literalinclude:: /code_examples/techmap/mulshift_test.ys
+   :language: yoscrypt
+   :caption: :file:`mulshift_test.ys`
+
+Handling shorted inputs
+~~~~~~~~~~~~~~~~~~~~~~~
+
+- The special parameters ``_TECHMAP_BITS_CONNMAP_`` and
+  ``_TECHMAP_CONNMAP_<port-name>_`` can be used to handle shorted inputs.
+- Each bit of the port correlates to an ``_TECHMAP_BITS_CONNMAP_`` bits wide
+  number in ``_TECHMAP_CONNMAP_<port-name>_``.
+- Each unique signal bit is assigned its own number. Identical fields in the
+  ``_TECHMAP_CONNMAP_<port-name>_`` parameters mean shorted signal bits.
+- The numbers 0-3 are reserved for ``0``, ``1``, ``x``, and ``z`` respectively.
+- Example use-cases:
+
+    - Detecting shared clock or control signals in memory interfaces.
+    - In some cases this can be used for for optimization.
+
+Example:
+
+.. figure:: /_images/code_examples/techmap/addshift.*
+    :class: width-helper invert-helper
+
+.. literalinclude:: /code_examples/techmap/addshift_map.v
+   :language: verilog
+   :caption: :file:`addshift_map.v`
+
+.. literalinclude:: /code_examples/techmap/addshift_test.v
+   :language: verilog
+   :caption: :file:`addshift_test.v`
+
+.. literalinclude:: /code_examples/techmap/addshift_test.ys
+   :language: yoscrypt
+   :caption: :file:`addshift_test.ys`
+
+Notes on using techmap
+~~~~~~~~~~~~~~~~~~~~~~
+
+- Don't use positional cell parameters in map modules.
+- You can use the ``$__``-prefix for internal cell types to avoid collisions
+  with the user-namespace. But always use two underscores or the internal
+  consistency checker will trigger on these cells.
+- Techmap has two major use cases:
+
+    - Creating good logic-level representation of arithmetic functions. This
+      also means using dedicated hardware resources such as half- and full-adder
+      cells in ASICS or dedicated carry logic in FPGAs.
+    - Mapping of coarse-grain resources such as block memory or DSP cells.
diff --git a/yosys/docs/static/custom.css b/yosys/docs/static/custom.css
deleted file mode 100644
index 40a8c178f10..00000000000
--- a/yosys/docs/static/custom.css
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/yosys/docs/static/yosyshq.css b/yosys/docs/static/yosyshq.css
deleted file mode 100644
index 0be7f77281d..00000000000
--- a/yosys/docs/static/yosyshq.css
+++ /dev/null
@@ -1,78 +0,0 @@
-h1, h3, p.topic-title, .content li.toctree-l1 > a {
-    color: #d6368f !important;
-}
-
-h2, p.admonition-title, dt, .content li.toctree-l2 > a {
-    color: #4b72b8;
-}
-
-a {
-    color: #8857a3;
-}
-
-a.current, a:hover, a.external {
-    color: #d6368f !important;
-}
-
-a.external:hover {
-    text-decoration: underline;
-}
-
-p {
-    text-align: justify;
-}
-
-.vp-sidebar a {
-    color: #d6368f;
-}
-
-.vp-sidebar li li a {
-    color: #4b72b8;
-}
-
-.vp-sidebar li li li a {
-    color: #2c3e50;
-    font-weight: 400;
-}
-
-.vp-sidebar h3 {
-    padding-left: 1.5rem !important;
-}
-
-.vp-sidebar ul a {
-    padding-left: 1.5rem !important;
-}
-
-.vp-sidebar ul ul a {
-    padding-left: 3rem !important;
-}
-
-.vp-sidebar ul ul ul a {
-    padding-left: 4.5rem !important;
-}
-
-.vp-sidebar .toctree-l1.current a {
-    border-left: 0.5rem solid #6ecbd7;
-}
-
-.vp-sidebar .toctree-l1 a.current {
-    border-left: 0.5rem solid #8857a3;
-}
-
-.injected .rst-current-version, .injected dt {
-    color: #6ecbd7 !important;
-}
-
-.cmdref .highlight-yoscrypt .highlight pre {
-	padding: 0%;
-	margin: 0%;
-}
-
-.cmdref .highlight-none .highlight pre {
-	padding-top: 0%;
-	margin-top: 0%;
-}
-
-.width-helper {
-	max-width: 100%;
-}
diff --git a/yosys/docs/tests/macro_commands.py b/yosys/docs/tests/macro_commands.py
new file mode 100755
index 00000000000..7ceb092d867
--- /dev/null
+++ b/yosys/docs/tests/macro_commands.py
@@ -0,0 +1,101 @@
+#!/usr/bin/env python3
+
+import logging
+from pathlib import Path
+import re
+import subprocess
+import sys
+
+# basic logging setup
+logging.basicConfig(level=logging.INFO)
+
+# expects __file__ = yosys/docs/tests/macro_commands.py
+TESTS_DIR = Path(__file__).parent.absolute()
+ROOT_DIR = TESTS_DIR.parent.parent
+logging.log(logging.INFO, f"Using {ROOT_DIR} as root directory")
+THIS_FILE = (TESTS_DIR / "macro_commands.py").relative_to(ROOT_DIR)
+MACRO_SOURCE = TESTS_DIR.parent / "source" / "code_examples" / "macro_commands"
+assert MACRO_SOURCE.exists(), f"can't find macro_commands in {MACRO_SOURCE}"
+
+YOSYS = ROOT_DIR / "yosys"
+assert YOSYS.exists(), f"can't find yosys executable in {YOSYS}"
+
+raise_error = False
+# get all macro commands being used
+for macro in MACRO_SOURCE.glob("*.ys"):
+    # log current test
+    relative_path = macro.relative_to(ROOT_DIR)
+    logging.log(logging.INFO, f"Checking {relative_path}")
+    # files in macros_commands should be named {command}.ys
+    command = macro.stem
+    # run `yosys -h {command}` to capture current sub-commands
+    proc = subprocess.run([YOSYS, "-QTh", command], capture_output=True, text=True)
+    with open(macro) as f:
+        # {command.ys} starts with two commented lines, the first is the text
+        # immediately prior to the macro body.  The second is the text
+        # immediately after.
+        start = f.readline()
+        end = f.readline()
+        file_content = f.readlines()
+    expected_content = []
+    for line in file_content:
+        line = line.split("#")[0].strip()
+        if line:
+            expected_content.append(line)
+    # parse {command.ys}
+    if "#start:" not in start or "#end:" not in end:
+        logging.error(f"Missing start and/or end string in {relative_path}, see {THIS_FILE}")
+        raise_error = True
+        continue
+    start = start.replace("#start:", "").strip()
+    end = end.replace("#end:", "").strip()
+    # attempt to find macro body in help output
+    match = re.fullmatch(f".*{start}(.*){end}.*", proc.stdout, re.DOTALL)
+    if not match:
+        logging.error(f"Couldn't find {start!r} and/or {end!r} in `yosys -h {command}` output")
+        raise_error = True
+        continue
+    match_content = match.group(1).strip().splitlines()
+    actual_content = []
+    for line in match_content:
+        if line:
+            actual_content.append(line)
+    # iterate over and compare expected v actual
+    for (expected, actual) in zip(expected_content, actual_content):
+        expected = expected.strip()
+        actual = actual.strip()
+        # raw match
+        if expected == actual:
+            continue
+
+        # rip apart formatting to match line parts
+        pattern = r"(?P<cmd>\S+)(?P<pass> \[.*\])?(?P<opt>.*?)(?P<cond>\s+\(.*\))?"
+        try:
+            expected_dict = re.fullmatch(pattern, expected).groupdict()
+        except AttributeError:
+            logging.error(f"Bad formatting in {relative_path}: {expected!r}")
+            raise_error = True
+            continue
+
+        try:
+            actual_dict = re.fullmatch(pattern, actual).groupdict()
+        except AttributeError:
+            logging.error(f"Unexpected formatting in `yosys -h {command}` output, {actual!r}")
+            raise_error = True
+            continue
+
+        does_match = expected_dict["cmd"] == actual_dict["cmd"]
+
+        #todo: check expected_dict["pass"] is a subset of actual_dict["pass"]
+        # only check opt and cond match if they're in {command}.ys
+        match_keys = ["opt", "cond"]
+        for key in match_keys:
+            if expected_dict[key] and expected_dict[key] != actual_dict[key]:
+                does_match = False
+
+        # raise error on mismatch        
+        if not does_match:
+            logging.error(f"Expected {expected!r}, got {actual!r}")
+            raise_error = True
+
+sys.exit(raise_error)
diff --git a/yosys/docs/util/__init__.py b/yosys/docs/util/__init__.py
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/yosys/docs/util/cmdref.py b/yosys/docs/util/cmdref.py
new file mode 100644
index 00000000000..ec146e23173
--- /dev/null
+++ b/yosys/docs/util/cmdref.py
@@ -0,0 +1,246 @@
+# based on https://github.com/ofosos/sphinxrecipes/blob/master/sphinxrecipes/sphinxrecipes.py
+# license:
+# Copyright 2019 Mark Meyer
+# 
+# Permission is hereby granted, free of charge, to any person obtaining
+# a copy of this software and associated documentation files (the
+# "Software"), to deal in the Software without restriction, including
+# without limitation the rights to use, copy, modify, merge, publish,
+# distribute, sublicense, and/or sell copies of the Software, and to
+# permit persons to whom the Software is furnished to do so, subject to
+# the following conditions:
+# 
+# The above copyright notice and this permission notice shall be
+# included in all copies or substantial portions of the Software.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+# LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+# OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+# WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+import docutils
+from docutils import nodes
+import sphinx
+from docutils.parsers import rst
+from docutils.parsers.rst import directives
+from sphinx.domains import Domain, Index
+from sphinx.domains.std import StandardDomain
+from sphinx.roles import XRefRole
+from sphinx.directives import ObjectDescription
+from sphinx.util.nodes import make_refnode
+from sphinx import addnodes
+
+class CommandNode(ObjectDescription):
+    """A custom node that describes a command."""
+  
+    required_arguments = 1
+
+    option_spec = {
+        'title': directives.unchanged_required,
+        'tags': directives.unchanged
+    }
+
+    def handle_signature(self, sig, signode: addnodes.desc_signature):
+        signode += addnodes.desc_addname(text="yosys> help ")
+        signode += addnodes.desc_name(text=sig)
+        return sig
+
+    def add_target_and_index(self, name_cls, sig, signode):
+        signode['ids'].append('cmd' + '-' + sig)
+        if 'noindex' not in self.options:
+            name = "{}.{}.{}".format('cmd', type(self).__name__, sig)
+            tagmap = self.env.domaindata['cmd']['obj2tag']
+            tagmap[name] = list(self.options.get('tags', '').split(' '))
+            title = self.options.get('title')
+            titlemap = self.env.domaindata['cmd']['obj2title']
+            titlemap[name] = title
+            objs = self.env.domaindata['cmd']['objects']
+            objs.append((name,
+                         sig,
+                         title,
+                         self.env.docname,
+                         'cmd' + '-' + sig,
+                         0))
+
+class TagIndex(Index):
+    """A custom directive that creates an tag matrix."""
+    
+    name = 'tag'
+    localname = 'Tag Index'
+    shortname = 'Tag'
+    
+    def __init__(self, *args, **kwargs):
+        super(TagIndex, self).__init__(*args, **kwargs)
+
+    def generate(self, docnames=None):
+        """Return entries for the index given by *name*.  If *docnames* is
+        given, restrict to entries referring to these docnames.
+        The return value is a tuple of ``(content, collapse)``, where
+        * collapse* is a boolean that determines if sub-entries should
+        start collapsed (for output formats that support collapsing
+        sub-entries).
+        *content* is a sequence of ``(letter, entries)`` tuples, where *letter*
+        is the "heading" for the given *entries*, usually the starting letter.
+        *entries* is a sequence of single entries, where a single entry is a
+        sequence ``[name, subtype, docname, anchor, extra, qualifier, descr]``.
+        The items in this sequence have the following meaning:
+        - `name` -- the name of the index entry to be displayed
+        - `subtype` -- sub-entry related type:
+          0 -- normal entry
+          1 -- entry with sub-entries
+          2 -- sub-entry
+        - `docname` -- docname where the entry is located
+        - `anchor` -- anchor for the entry within `docname`
+        - `extra` -- extra info for the entry
+        - `qualifier` -- qualifier for the description
+        - `descr` -- description for the entry
+        Qualifier and description are not rendered e.g. in LaTeX output.
+        """
+
+        content = {}
+
+        objs = {name: (dispname, typ, docname, anchor)
+                for name, dispname, typ, docname, anchor, prio
+                in self.domain.get_objects()}
+        
+        tmap = {}
+        tags = self.domain.data['obj2tag']
+        for name, tags in tags.items():
+            for tag in tags:
+                tmap.setdefault(tag,[])
+                tmap[tag].append(name)
+            
+        for tag in tmap.keys():
+            lis = content.setdefault(tag, [])
+            objlis = tmap[tag]
+            for objname in objlis:
+                dispname, typ, docname, anchor = objs[objname]
+                lis.append((
+                    dispname, 0, docname,
+                    anchor,
+                    docname, '', typ
+                ))
+        re = [(k, v) for k, v in sorted(content.items())]
+
+        return (re, True)
+
+
+class CommandIndex(Index):    
+    name = 'cmd'
+    localname = 'Command Reference'
+    shortname = 'Command'
+    
+    def __init__(self, *args, **kwargs):
+        super(CommandIndex, self).__init__(*args, **kwargs)
+
+    def generate(self, docnames=None):
+        """Return entries for the index given by *name*.  If *docnames* is
+        given, restrict to entries referring to these docnames.
+        The return value is a tuple of ``(content, collapse)``, where
+        * collapse* is a boolean that determines if sub-entries should
+        start collapsed (for output formats that support collapsing
+        sub-entries).
+        *content* is a sequence of ``(letter, entries)`` tuples, where *letter*
+        is the "heading" for the given *entries*, usually the starting letter.
+        *entries* is a sequence of single entries, where a single entry is a
+        sequence ``[name, subtype, docname, anchor, extra, qualifier, descr]``.
+        The items in this sequence have the following meaning:
+        - `name` -- the name of the index entry to be displayed
+        - `subtype` -- sub-entry related type:
+          0 -- normal entry
+          1 -- entry with sub-entries
+          2 -- sub-entry
+        - `docname` -- docname where the entry is located
+        - `anchor` -- anchor for the entry within `docname`
+        - `extra` -- extra info for the entry
+        - `qualifier` -- qualifier for the description
+        - `descr` -- description for the entry
+        Qualifier and description are not rendered e.g. in LaTeX output.
+        """
+
+        content = {}
+        items = ((name, dispname, typ, docname, anchor)
+                 for name, dispname, typ, docname, anchor, prio
+                 in self.domain.get_objects())
+        items = sorted(items, key=lambda item: item[0])
+        for name, dispname, typ, docname, anchor in items:
+            lis = content.setdefault('Command', [])
+            lis.append((
+                dispname, 0, docname,
+                anchor,
+                '', '', typ
+            ))
+        re = [(k, v) for k, v in sorted(content.items())]
+
+        return (re, True)
+
+
+class CommandDomain(Domain):
+    name = 'cmd'
+    label = 'Command Sample'
+
+    roles = {
+        'ref': XRefRole()
+    }
+
+    directives = {
+        'def': CommandNode,
+    }
+
+    indices = {
+        CommandIndex,
+        TagIndex
+    }
+
+    initial_data = {
+        'objects': [],      # object list
+        'obj2tag': {},      # name -> tags
+        'obj2title': {},    # name -> title
+    }
+
+    def get_full_qualified_name(self, node):
+        """Return full qualified name for a given node"""
+        return "{}.{}.{}".format('cmd',
+                                 type(node).__name__,
+                                 node.arguments[0])
+
+    def get_objects(self):
+        for obj in self.data['objects']:
+            yield(obj)
+
+    def resolve_xref(self, env, fromdocname, builder, typ,
+                     target, node, contnode):
+        
+        match = [(docname, anchor, name)
+                 for name, sig, typ, docname, anchor, prio
+                 in self.get_objects() if sig == target]
+
+        if match:
+            todocname = match[0][0]
+            targ = match[0][1]
+            qual_name = match[0][2]
+            title = self.data['obj2title'].get(qual_name, targ)
+            
+            return make_refnode(builder,fromdocname,todocname,
+                                targ, contnode, title)
+        else:
+            print(f"Missing ref for {target} in {fromdocname} ")
+            return None
+
+def setup(app):
+    app.add_domain(CommandDomain)
+
+    StandardDomain.initial_data['labels']['commandindex'] =\
+        ('cmd-cmd', '', 'Command Reference')
+    StandardDomain.initial_data['labels']['tagindex'] =\
+        ('cmd-tag', '', 'Tag Index')
+
+    StandardDomain.initial_data['anonlabels']['commandindex'] =\
+        ('cmd-cmd', '')
+    StandardDomain.initial_data['anonlabels']['tagindex'] =\
+        ('cmd-tag', '')
+    
+    return {'version': '0.1'}
diff --git a/yosys/examples/cxx-api/scopeinfo_example.cc b/yosys/examples/cxx-api/scopeinfo_example.cc
new file mode 100644
index 00000000000..f163dff9eee
--- /dev/null
+++ b/yosys/examples/cxx-api/scopeinfo_example.cc
@@ -0,0 +1,144 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// build: yosys-config --build scopeinfo_example.so scopeinfo_example.cc
+// use: yosys -m scopeinfo_example.so
+
+#include "backends/rtlil/rtlil_backend.h"
+#include "kernel/scopeinfo.h"
+#include "kernel/yosys.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct ScopeinfoExamplePass : public Pass {
+	ScopeinfoExamplePass() : Pass("scopeinfo_example", "dump scopeinfo") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    scopeinfo_example [options] [selection]\n");
+		log("\n");
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing SCOPEINFO_EXAMPLE pass.\n");
+
+		bool do_wires = false;
+		bool do_common = false;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-wires") {
+				do_wires = true;
+				continue;
+			}
+			if (args[argidx] == "-common") {
+				do_common = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+
+		if (do_wires) {
+			for (auto module : design->selected_modules()) {
+				log("Source hierarchy for all selected wires within %s:\n", log_id(module));
+				ModuleHdlnameIndex index(module);
+
+				index.index_scopeinfo_cells();
+
+				for (auto wire : module->selected_wires()) {
+					if (!wire->name.isPublic())
+						continue;
+
+					auto wire_scope = index.containing_scope(wire);
+
+					if (!wire_scope.first.valid()) {
+						log_warning("Couldn't find containing scope for %s in index\n", log_id(wire));
+						continue;
+					}
+
+					log("%s %s\n", wire_scope.first.path_str().c_str(), log_id(wire_scope.second));
+					for (auto src : index.sources(wire))
+						log(" - %s\n", src.c_str());
+				}
+			}
+		}
+
+		if (do_common) {
+			for (auto module : design->selected_modules()) {
+				std::vector<Wire *> wires = module->selected_wires();
+
+				// Shuffle wires so this example produces more interesting outputs
+				std::sort(wires.begin(), wires.end(), [](Wire *a, Wire *b) {
+					return mkhash_xorshift(a->name.hash() * 0x2c9277b5) < mkhash_xorshift(b->name.hash() * 0x2c9277b5);
+				});
+
+				ModuleHdlnameIndex index(module);
+
+				index.index_scopeinfo_cells();
+
+				for (auto wire_i = wires.begin(), wire_end = wires.end(); wire_i != wire_end; ++wire_i) {
+					if (!(*wire_i)->name.isPublic())
+						continue;
+
+					std::pair<ModuleHdlnameIndex::Cursor, IdString> scope_i = index.containing_scope(*wire_i);
+					if (!scope_i.first.valid())
+						continue;
+
+					int limit = 0;
+
+					for (auto wire_j = wire_i + 1; wire_j != wire_end; ++wire_j) {
+						if (!(*wire_j)->name.isPublic())
+							continue;
+
+						std::pair<ModuleHdlnameIndex::Cursor, IdString> scope_j = index.containing_scope(*wire_j);
+						if (!scope_j.first.valid())
+							continue;
+
+						// Skip wires in the same hierarchy level
+						if (scope_i.first == scope_j.first)
+							continue;
+
+
+						ModuleHdlnameIndex::Cursor common = scope_i.first.common_ancestor(scope_j.first);
+
+						// Try to show at least some non-root common ancestors
+						if (common.is_root() && limit > 5)
+							continue;
+
+						log("common_ancestor(%s %s%s%s, %s %s%s%s) = %s %s\n",
+							log_id(module), scope_i.first.path_str().c_str(), scope_i.first.is_root() ? "" : " ", log_id(scope_i.second),
+							log_id(module), scope_j.first.path_str().c_str(), scope_j.first.is_root() ? "" : " ", log_id(scope_j.second),
+							log_id(module), common.path_str().c_str()
+						);
+
+						if (++limit == 10)
+							break;
+					}
+				}
+			}
+		}
+	}
+} ScopeinfoExamplePass;
+
+PRIVATE_NAMESPACE_END
diff --git a/yosys/examples/python-api/pass.py b/yosys/examples/python-api/pass.py
index d67cf4a23c5..dbef0a13fb9 100755
--- a/yosys/examples/python-api/pass.py
+++ b/yosys/examples/python-api/pass.py
@@ -1,6 +1,6 @@
 #!/usr/bin/python3
 
-from pyosys import libyosys as ys
+import libyosys as ys
 
 import matplotlib.pyplot as plt
 import numpy as np
diff --git a/yosys/flake.lock b/yosys/flake.lock
new file mode 100644
index 00000000000..2545f4ce057
--- /dev/null
+++ b/yosys/flake.lock
@@ -0,0 +1,61 @@
+{
+  "nodes": {
+    "flake-utils": {
+      "inputs": {
+        "systems": "systems"
+      },
+      "locked": {
+        "lastModified": 1705309234,
+        "narHash": "sha256-uNRRNRKmJyCRC/8y1RqBkqWBLM034y4qN7EprSdmgyA=",
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "rev": "1ef2e671c3b0c19053962c07dbda38332dcebf26",
+        "type": "github"
+      },
+      "original": {
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "type": "github"
+      }
+    },
+    "nixpkgs": {
+      "locked": {
+        "lastModified": 1708807242,
+        "narHash": "sha256-sRTRkhMD4delO/hPxxi+XwLqPn8BuUq6nnj4JqLwOu0=",
+        "owner": "NixOS",
+        "repo": "nixpkgs",
+        "rev": "73de017ef2d18a04ac4bfd0c02650007ccb31c2a",
+        "type": "github"
+      },
+      "original": {
+        "owner": "NixOS",
+        "ref": "nixos-unstable",
+        "repo": "nixpkgs",
+        "type": "github"
+      }
+    },
+    "root": {
+      "inputs": {
+        "flake-utils": "flake-utils",
+        "nixpkgs": "nixpkgs"
+      }
+    },
+    "systems": {
+      "locked": {
+        "lastModified": 1681028828,
+        "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=",
+        "owner": "nix-systems",
+        "repo": "default",
+        "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nix-systems",
+        "repo": "default",
+        "type": "github"
+      }
+    }
+  },
+  "root": "root",
+  "version": 7
+}
diff --git a/yosys/flake.nix b/yosys/flake.nix
new file mode 100644
index 00000000000..1e202324647
--- /dev/null
+++ b/yosys/flake.nix
@@ -0,0 +1,48 @@
+{
+  description = "A nix flake for the Yosys synthesis suite";
+
+  inputs = {
+    nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable";
+    flake-utils.url = "github:numtide/flake-utils";
+  };
+
+  outputs = { self, nixpkgs, flake-utils }:
+    flake-utils.lib.eachDefaultSystem (system:
+      let
+        pkgs = import nixpkgs {
+          inherit system;
+        };
+        # TODO: don't override src when ./abc is empty
+        # which happens when the command used is `nix build` and not `nix build ?submodules=1`
+        abc-verifier = pkgs.abc-verifier.overrideAttrs(x: y: {src = ./abc;});
+        yosys = pkgs.clangStdenv.mkDerivation {
+          name = "yosys";
+          src = ./. ;
+          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git pkg-configUpstream ];
+          checkInputs = with pkgs; [ gtest ];
+          propagatedBuildInputs = [ abc-verifier ];
+          preConfigure = "make config-clang";
+          checkTarget = "test";
+          installPhase = ''
+            make install PREFIX=$out ABCEXTERNAL=yosys-abc
+            ln -s ${abc-verifier}/bin/abc $out/bin/yosys-abc
+          '';
+					buildPhase = ''
+            make -j$(nproc) ABCEXTERNAL=yosys-abc
+          '';
+          meta = with pkgs.lib; {
+            description = "Yosys Open SYnthesis Suite";
+            homepage = "https://yosyshq.net/yosys/";
+            license = licenses.isc;
+            maintainers = with maintainers; [ ];
+          };
+        };
+      in {
+        packages.default = yosys;
+        defaultPackage = yosys;
+        devShell = pkgs.mkShell {
+          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier ];
+        };
+      }
+    );
+}
diff --git a/yosys/frontends/aiger/aigerparse.cc b/yosys/frontends/aiger/aigerparse.cc
index cb19b8413a5..0178514e1cd 100644
--- a/yosys/frontends/aiger/aigerparse.cc
+++ b/yosys/frontends/aiger/aigerparse.cc
@@ -590,6 +590,7 @@ void AigerReader::parse_aiger_ascii()
 	for (unsigned i = 0; i < O; ++i, ++line_count) {
 		if (!(f >> l1))
 			log_error("Line %u cannot be interpreted as an output!\n", line_count);
+		std::getline(f, line); // Ignore up to start of next line
 
 		log_debug2("%d is an output\n", l1);
 		RTLIL::Wire *wire = module->addWire(stringf("$o%0*d", digits, i));
@@ -597,20 +598,18 @@ void AigerReader::parse_aiger_ascii()
 		module->connect(wire, createWireIfNotExists(module, l1));
 		outputs.push_back(wire);
 	}
-	//std::getline(f, line); // Ignore up to start of next line
 
 	// Parse bad properties
 	for (unsigned i = 0; i < B; ++i, ++line_count) {
 		if (!(f >> l1))
 			log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
+		std::getline(f, line); // Ignore up to start of next line
 
 		log_debug2("%d is a bad state property\n", l1);
 		RTLIL::Wire *wire = createWireIfNotExists(module, l1);
 		wire->port_output = true;
 		bad_properties.push_back(wire);
 	}
-	//if (B > 0)
-	//	std::getline(f, line); // Ignore up to start of next line
 
 	// TODO: Parse invariant constraints
 	for (unsigned i = 0; i < C; ++i, ++line_count)
@@ -628,6 +627,7 @@ void AigerReader::parse_aiger_ascii()
 	for (unsigned i = 0; i < A; ++i) {
 		if (!(f >> l1 >> l2 >> l3))
 			log_error("Line %u cannot be interpreted as an AND!\n", line_count);
+		std::getline(f, line); // Ignore up to start of next line
 
 		log_debug2("%d %d %d is an AND\n", l1, l2, l3);
 		log_assert(!(l1 & 1));
@@ -636,7 +636,6 @@ void AigerReader::parse_aiger_ascii()
 		RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
 		module->addAndGate("$and" + o_wire->name.str(), i1_wire, i2_wire, o_wire);
 	}
-	std::getline(f, line); // Ignore up to start of next line
 }
 
 static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
@@ -715,6 +714,7 @@ void AigerReader::parse_aiger_binary()
 	for (unsigned i = 0; i < O; ++i, ++line_count) {
 		if (!(f >> l1))
 			log_error("Line %u cannot be interpreted as an output!\n", line_count);
+		std::getline(f, line); // Ignore up to start of next line
 
 		log_debug2("%d is an output\n", l1);
 		RTLIL::Wire *wire = module->addWire(stringf("$o%0*d", digits, i));
@@ -722,20 +722,18 @@ void AigerReader::parse_aiger_binary()
 		module->connect(wire, createWireIfNotExists(module, l1));
 		outputs.push_back(wire);
 	}
-	std::getline(f, line); // Ignore up to start of next line
 
 	// Parse bad properties
 	for (unsigned i = 0; i < B; ++i, ++line_count) {
 		if (!(f >> l1))
 			log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
+		std::getline(f, line); // Ignore up to start of next line
 
 		log_debug2("%d is a bad state property\n", l1);
 		RTLIL::Wire *wire = createWireIfNotExists(module, l1);
 		wire->port_output = true;
 		bad_properties.push_back(wire);
 	}
-	if (B > 0)
-		std::getline(f, line); // Ignore up to start of next line
 
 	// TODO: Parse invariant constraints
 	for (unsigned i = 0; i < C; ++i, ++line_count)
diff --git a/yosys/frontends/ast/ast.cc b/yosys/frontends/ast/ast.cc
index a027295e979..996f6715d05 100644
--- a/yosys/frontends/ast/ast.cc
+++ b/yosys/frontends/ast/ast.cc
@@ -45,7 +45,7 @@ namespace AST {
 
 // instantiate global variables (private API)
 namespace AST_INTERNAL {
-	bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
+	bool flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
 	bool flag_nomem2reg, flag_mem2reg, flag_noblackbox, flag_lib, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_autowire;
 	AstNode *current_ast, *current_ast_mod;
 	std::map<std::string, AstNode*> current_scope;
@@ -224,11 +224,16 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
 	port_id = 0;
 	range_left = -1;
 	range_right = 0;
+	unpacked_dimensions = 0;
 	integer = 0;
 	realvalue = 0;
 	id2ast = NULL;
 	basic_prep = false;
 	lookahead = false;
+	in_lvalue_from_above = false;
+	in_param_from_above = false;
+	in_lvalue = false;
+	in_param = false;
 
 	if (child1)
 		children.push_back(child1);
@@ -238,6 +243,8 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
 		children.push_back(child3);
 	if (child4)
 		children.push_back(child4);
+
+	fixup_hierarchy_flags();
 }
 
 // create a (deep recursive) copy of a node
@@ -249,6 +256,10 @@ AstNode *AstNode::clone() const
 		it = it->clone();
 	for (auto &it : that->attributes)
 		it.second = it.second->clone();
+
+	that->set_in_lvalue_flag(false);
+	that->set_in_param_flag(false);
+	that->fixup_hierarchy_flags(); // fixup to set flags on cloned children
 	return that;
 }
 
@@ -256,10 +267,13 @@ AstNode *AstNode::clone() const
 void AstNode::cloneInto(AstNode *other) const
 {
 	AstNode *tmp = clone();
+	tmp->in_lvalue_from_above = other->in_lvalue_from_above;
+	tmp->in_param_from_above = other->in_param_from_above;
 	other->delete_children();
 	*other = *tmp;
 	tmp->children.clear();
 	tmp->attributes.clear();
+	other->fixup_hierarchy_flags();
 	delete tmp;
 }
 
@@ -336,21 +350,23 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
 		fprintf(f, " int=%u", (int)integer);
 	if (realvalue != 0)
 		fprintf(f, " real=%e", realvalue);
-	if (!multirange_dimensions.empty()) {
-		fprintf(f, " multirange=[");
-		for (int v : multirange_dimensions)
-			fprintf(f, " %d", v);
-		fprintf(f, " ]");
-	}
-	if (!multirange_swapped.empty()) {
-		fprintf(f, " multirange_swapped=[");
-		for (bool v : multirange_swapped)
-			fprintf(f, " %d", v);
-		fprintf(f, " ]");
+	if (!dimensions.empty()) {
+		fprintf(f, " dimensions=");
+		for (auto &dim : dimensions) {
+			int left = dim.range_right + dim.range_width - 1;
+			int right = dim.range_right;
+			if (dim.range_swapped)
+				std::swap(left, right);
+			fprintf(f, "[%d:%d]", left, right);
+		}
 	}
 	if (is_enum) {
 		fprintf(f, " type=enum");
 	}
+	if (in_lvalue)
+		fprintf(f, " in_lvalue");
+	if (in_param)
+		fprintf(f, " in_param");
 	fprintf(f, "\n");
 
 	for (auto &it : attributes) {
@@ -472,6 +488,20 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
 		fprintf(f, ";\n");
 		break;
 
+	if (0) { case AST_MEMRD:   txt = "@memrd@";  }
+	if (0) { case AST_MEMINIT: txt = "@meminit@";  }
+	if (0) { case AST_MEMWR:   txt = "@memwr@";  }
+		fprintf(f, "%s%s", indent.c_str(), txt.c_str());
+		for (auto child : children) {
+			fprintf(f, first ? "(" : ", ");
+			child->dumpVlog(f, "");
+			first = false;
+		}
+		fprintf(f, ")");
+		if (type != AST_MEMRD)
+			fprintf(f, ";\n");
+		break;
+
 	case AST_RANGE:
 		if (range_valid) {
 			if (range_swapped)
@@ -488,6 +518,11 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
 		}
 		break;
 
+	case AST_MULTIRANGE:
+		for (auto child : children)
+			child->dumpVlog(f, "");
+		break;
+
 	case AST_ALWAYS:
 		fprintf(f, "%s" "always @", indent.c_str());
 		for (auto child : children) {
@@ -525,7 +560,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
 
 	case AST_IDENTIFIER:
 		{
-			AST::AstNode *member_node = AST::get_struct_member(this);
+			AstNode *member_node = get_struct_member();
 			if (member_node)
 				fprintf(f, "%s[%d:%d]", id2vl(str).c_str(), member_node->range_left, member_node->range_right);
 			else
@@ -535,6 +570,12 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
 			child->dumpVlog(f, "");
 		break;
 
+	case AST_STRUCT:
+	case AST_UNION:
+	case AST_STRUCT_ITEM:
+		fprintf(f, "%s", id2vl(str).c_str());
+		break;
+
 	case AST_CONSTANT:
 		if (!str.empty())
 			fprintf(f, "\"%s\"", str.c_str());
@@ -641,11 +682,20 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
 	if (0) { case AST_NEG:         txt = "-";  }
 	if (0) { case AST_LOGIC_NOT:   txt = "!";  }
 	if (0) { case AST_SELFSZ:      txt = "@selfsz@";  }
+	if (0) { case AST_TO_SIGNED:   txt = "signed'";  }
+	if (0) { case AST_TO_UNSIGNED: txt = "unsigned'";  }
 		fprintf(f, "%s(", txt.c_str());
 		children[0]->dumpVlog(f, "");
 		fprintf(f, ")");
 		break;
 
+	case AST_CAST_SIZE:
+		children[0]->dumpVlog(f, "");
+		fprintf(f, "'(");
+		children[1]->dumpVlog(f, "");
+		fprintf(f, ")");
+		break;
+
 	if (0) { case AST_BIT_AND:      txt = "&";   }
 	if (0) { case AST_BIT_OR:       txt = "|";   }
 	if (0) { case AST_BIT_XOR:      txt = "^";   }
@@ -824,6 +874,25 @@ AstNode *AstNode::mkconst_str(const std::string &str)
 	return node;
 }
 
+// create a temporary register
+AstNode *AstNode::mktemp_logic(const std::string &name, AstNode *mod, bool nosync, int range_left, int range_right, bool is_signed)
+{
+	AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(range_left, true), mkconst_int(range_right, true)));
+	wire->str = stringf("%s%s:%d$%d", name.c_str(), RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
+	if (nosync)
+		wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
+	wire->is_signed = is_signed;
+	wire->is_logic = true;
+	mod->children.push_back(wire);
+	while (wire->simplify(true, 1, -1, false)) { }
+
+	AstNode *ident = new AstNode(AST_IDENTIFIER);
+	ident->str = wire->str;
+	ident->id2ast = wire;
+
+	return ident;
+}
+
 bool AstNode::bits_only_01() const
 {
 	for (auto bit : bits)
@@ -1061,7 +1130,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
 		// simplify this module or interface using the current design as context
 		// for lookup up ports and wires within cells
 		set_simplify_design_context(design);
-		while (ast->simplify(!flag_noopt, false, 0, -1, false, false)) { }
+		while (ast->simplify(!flag_noopt, 0, -1, false)) { }
 		set_simplify_design_context(nullptr);
 
 		if (flag_dump_ast2) {
@@ -1091,7 +1160,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
 					ast->attributes.erase(ID::whitebox);
 				}
 				AstNode *n = ast->attributes.at(ID::lib_whitebox);
-				ast->attributes[ID::whitebox] = n;
+				ast->set_attribute(ID::whitebox, n);
 				ast->attributes.erase(ID::lib_whitebox);
 			}
 		}
@@ -1150,7 +1219,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
 			ast->children.swap(new_children);
 
 			if (ast->attributes.count(ID::blackbox) == 0) {
-				ast->attributes[ID::blackbox] = AstNode::mkconst_int(1, false);
+				ast->set_attribute(ID::blackbox, AstNode::mkconst_int(1, false));
 			}
 		}
 
@@ -1275,11 +1344,12 @@ static void rename_in_package_stmts(AstNode *pkg)
 }
 
 // create AstModule instances for all modules in the AST tree and add them to 'design'
-void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,
+void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,
 		bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire)
 {
 	current_ast = ast;
 	current_ast_mod = nullptr;
+	flag_nodisplay = nodisplay;
 	flag_dump_ast1 = dump_ast1;
 	flag_dump_ast2 = dump_ast2;
 	flag_no_dump_ptr = no_dump_ptr;
@@ -1298,6 +1368,8 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 	flag_pwires = pwires;
 	flag_autowire = autowire;
 
+	ast->fixup_hierarchy_flags(true);
+
 	log_assert(current_ast->type == AST_DESIGN);
 	for (AstNode *child : current_ast->children)
 	{
@@ -1361,7 +1433,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 		}
 		else if (child->type == AST_PACKAGE) {
 			// process enum/other declarations
-			child->simplify(true, false, 1, -1, false, false);
+			child->simplify(true, 1, -1, false);
 			rename_in_package_stmts(child);
 			design->verilog_packages.push_back(child->clone());
 			current_scope.clear();
@@ -1748,7 +1820,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
 
 	AstNode *new_ast = ast->clone();
 	if (!new_ast->attributes.count(ID::hdlname))
-		new_ast->attributes[ID::hdlname] = AstNode::mkconst_str(stripped_name);
+		new_ast->set_attribute(ID::hdlname, AstNode::mkconst_str(stripped_name.substr(1)));
 
 	para_counter = 0;
 	for (auto child : new_ast->children) {
@@ -1795,6 +1867,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
 			new_ast->children.push_back(defparam);
 		}
 
+	new_ast->fixup_hierarchy_flags(true);
 	(*new_ast_out) = new_ast;
 	return modname;
 }
diff --git a/yosys/frontends/ast/ast.h b/yosys/frontends/ast/ast.h
index 8893d5e010c..59a393e080e 100644
--- a/yosys/frontends/ast/ast.h
+++ b/yosys/frontends/ast/ast.h
@@ -17,12 +17,7 @@
  *
  *  ---
  *
- *  This is the AST frontend library.
- *
- *  The AST frontend library is not a frontend on it's own but provides a
- *  generic abstract syntax tree (AST) abstraction for HDL code and can be
- *  used by HDL frontends. See "ast.h" for an overview of the API and the
- *  Verilog frontend for an usage example.
+ *  This is support code for the Verilog frontend at frontends/verilog
  *
  */
 
@@ -30,6 +25,7 @@
 #define AST_H
 
 #include "kernel/rtlil.h"
+#include "kernel/fmt.h"
 #include <stdint.h>
 #include <set>
 
@@ -201,9 +197,17 @@ namespace AST
 		// set for IDs typed to an enumeration, not used
 		bool is_enum;
 
-		// if this is a multirange memory then this vector contains offset and length of each dimension
-		std::vector<int> multirange_dimensions;
-		std::vector<bool> multirange_swapped; // true if range is swapped
+		// Declared range for array dimension.
+		struct dimension_t {
+			int range_right;     // lsb in [msb:lsb]
+			int range_width;     // msb - lsb + 1
+			bool range_swapped;  // if the declared msb < lsb, msb and lsb above are swapped
+		};
+		// Packed and unpacked dimensions for arrays.
+		// Unpacked dimensions go first, to follow the order of indexing.
+		std::vector<dimension_t> dimensions;
+		// Number of unpacked dimensions.
+		int unpacked_dimensions;
 
 		// this is set by simplify and used during RTLIL generation
 		AstNode *id2ast;
@@ -220,6 +224,13 @@ namespace AST
 		std::string filename;
 		AstSrcLocType location;
 
+		// are we embedded in an lvalue, param?
+		// (see fixup_hierarchy_flags)
+		bool in_lvalue;
+		bool in_param;
+		bool in_lvalue_from_above;
+		bool in_param_from_above;
+
 		// creating and deleting nodes
 		AstNode(AstNodeType type = AST_NONE, AstNode *child1 = nullptr, AstNode *child2 = nullptr, AstNode *child3 = nullptr, AstNode *child4 = nullptr);
 		AstNode *clone() const;
@@ -250,7 +261,7 @@ namespace AST
 
 		// simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.
 		// it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
-		bool simplify(bool const_fold, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param);
+		bool simplify(bool const_fold, int stage, int width_hint, bool sign_hint);
 		void replace_result_wire_name_in_function(const std::string &from, const std::string &to);
 		AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init);
 		void expand_genblock(const std::string &prefix);
@@ -277,7 +288,9 @@ namespace AST
 		bool replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall, bool must_succeed);
 		AstNode *eval_const_function(AstNode *fcall, bool must_succeed);
 		bool is_simple_const_expr();
-		std::string process_format_str(const std::string &sformat, int next_arg, int stage, int width_hint, bool sign_hint);
+
+		// helper for parsing format strings
+		Fmt processFormat(int stage, bool sformat_like, int default_base = 10, size_t first_arg_at = 0, bool may_fail = false);
 
 		bool is_recursive_function() const;
 		std::pair<AstNode*, AstNode*> get_tern_choice();
@@ -311,6 +324,9 @@ namespace AST
 		static AstNode *mkconst_str(const std::vector<RTLIL::State> &v);
 		static AstNode *mkconst_str(const std::string &str);
 
+		// helper function to create an AST node for a temporary register
+		AstNode *mktemp_logic(const std::string &name, AstNode *mod, bool nosync, int range_left, int range_right, bool is_signed);
+
 		// helper function for creating sign-extended const objects
 		RTLIL::Const bitsAsConst(int width, bool is_signed);
 		RTLIL::Const bitsAsConst(int width = -1);
@@ -340,12 +356,34 @@ namespace AST
 		// to evaluate widths of dynamic ranges)
 		AstNode *clone_at_zero();
 
+		void set_attribute(RTLIL::IdString key, AstNode *node)
+		{
+			attributes[key] = node;
+			node->set_in_param_flag(true);
+		}
+
+		// helper to set in_lvalue/in_param flags from the hierarchy context (the actual flag
+		// can be overridden based on the intrinsic properties of this node, i.e. based on its type)
+		void set_in_lvalue_flag(bool flag, bool no_descend = false);
+		void set_in_param_flag(bool flag, bool no_descend = false);
+
+		// fix up the hierarchy flags (in_lvalue/in_param) of this node and its children
+		//
+		// to keep the flags in sync, fixup_hierarchy_flags(true) needs to be called once after
+		// parsing the AST to walk the full tree, then plain fixup_hierarchy_flags() performs
+		// localized fixups after modifying children/attributes of a particular node
+		void fixup_hierarchy_flags(bool force_descend = false);
+
+		// helpers for indexing
+		AstNode *make_index_range(AstNode *node, bool unpacked_range = false);
+		AstNode *get_struct_member() const;
+
 		// helper to print errors from simplify/genrtlil code
 		[[noreturn]] void input_error(const char *format, ...) const YS_ATTRIBUTE(format(printf, 2, 3));
 	};
 
 	// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
-	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit,
+	void process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit,
 			bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire);
 
 	// parametric modules are supported directly by the AST library
@@ -385,10 +423,6 @@ namespace AST
 	// Helper for setting the src attribute.
 	void set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast);
 
-	// struct helper exposed from simplify for genrtlil
-	AstNode *make_struct_member_range(AstNode *node, AstNode *member_node);
-	AstNode *get_struct_member(const AstNode *node);
-
 	// generate standard $paramod... derived module name; parameters should be
 	// in the order they are declared in the instantiated module
 	std::string derived_module_name(std::string stripped_name, const std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> &parameters);
@@ -401,7 +435,7 @@ namespace AST
 namespace AST_INTERNAL
 {
 	// internal state variables
-	extern bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
+	extern bool flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
 	extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_pwires, flag_autowire;
 	extern AST::AstNode *current_ast, *current_ast_mod;
 	extern std::map<std::string, AST::AstNode*> current_scope;
diff --git a/yosys/frontends/ast/genrtlil.cc b/yosys/frontends/ast/genrtlil.cc
index 3aa19b70687..3d47bd3c0f1 100644
--- a/yosys/frontends/ast/genrtlil.cc
+++ b/yosys/frontends/ast/genrtlil.cc
@@ -163,6 +163,28 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
 	return wire;
 }
 
+static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,
+		const AstNode *node, const char *to_add_kind)
+{
+	auto already_exists = [&](const RTLIL::AttrObject *existing, const char *existing_kind) {
+		std::string src = existing->get_string_attribute(ID::src);
+		std::string location_str = "earlier";
+		if (!src.empty())
+			location_str = "at " + src;
+		node->input_error("Cannot add %s `%s' because a %s with the same name was already created %s!\n",
+						  to_add_kind, id.c_str(), existing_kind, location_str.c_str());
+	};
+
+	if (const RTLIL::Wire *wire = module->wire(id))
+		already_exists(wire, "signal");
+	if (const RTLIL::Cell *cell = module->cell(id))
+		already_exists(cell, "cell");
+	if (module->processes.count(id))
+		already_exists(module->processes.at(id), "process");
+	if (module->memories.count(id))
+		already_exists(module->memories.at(id), "memory");
+}
+
 // helper class for rewriting simple lookahead references in AST always blocks
 struct AST_INTERNAL::LookaheadRewriter
 {
@@ -176,10 +198,11 @@ struct AST_INTERNAL::LookaheadRewriter
 				AstNode *wire = new AstNode(AST_WIRE);
 				for (auto c : node->id2ast->children)
 					wire->children.push_back(c->clone());
+				wire->fixup_hierarchy_flags();
 				wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++);
-				wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
+				wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
 				wire->is_logic = true;
-				while (wire->simplify(true, false, 1, -1, false, false)) { }
+				while (wire->simplify(true, 1, -1, false)) { }
 				current_ast_mod->children.push_back(wire);
 				lookaheadids[node->str] = make_pair(node->id2ast, wire);
 				wire->genRTLIL();
@@ -315,7 +338,10 @@ struct AST_INTERNAL::ProcessGenerator
 	// Buffer for generating the init action
 	RTLIL::SigSpec init_lvalue, init_rvalue;
 
-	ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg)
+	// The most recently assigned $print or $check cell \PRIORITY.
+	int last_effect_priority;
+
+	ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg), last_effect_priority(0)
 	{
 		// rewrite lookahead references
 		LookaheadRewriter la_rewriter(always);
@@ -693,8 +719,149 @@ struct AST_INTERNAL::ProcessGenerator
 			ast->input_error("Found parameter declaration in block without label!\n");
 			break;
 
-		case AST_NONE:
 		case AST_TCALL:
+			if (ast->str == "$display" || ast->str == "$displayb" || ast->str == "$displayh" || ast->str == "$displayo" ||
+		  ast->str == "$write"   || ast->str == "$writeb"   || ast->str == "$writeh"   || ast->str == "$writeo") {
+				std::stringstream sstr;
+				sstr << ast->str << "$" << ast->filename << ":" << ast->location.first_line << "$" << (autoidx++);
+
+				Wire *en = current_module->addWire(sstr.str() + "_EN", 1);
+				set_src_attr(en, ast);
+				proc->root_case.actions.push_back(SigSig(en, false));
+				current_case->actions.push_back(SigSig(en, true));
+
+				RTLIL::SigSpec triggers;
+				RTLIL::Const polarity;
+				for (auto sync : proc->syncs) {
+					if (sync->type == RTLIL::STp) {
+						triggers.append(sync->signal);
+						polarity.bits.push_back(RTLIL::S1);
+					} else if (sync->type == RTLIL::STn) {
+						triggers.append(sync->signal);
+						polarity.bits.push_back(RTLIL::S0);
+					}
+				}
+
+				RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($print));
+				set_src_attr(cell, ast);
+				cell->setParam(ID::TRG_WIDTH, triggers.size());
+				cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty());
+				cell->setParam(ID::TRG_POLARITY, polarity);
+				cell->setParam(ID::PRIORITY, --last_effect_priority);
+				cell->setPort(ID::TRG, triggers);
+				cell->setPort(ID::EN, en);
+
+				int default_base = 10;
+				if (ast->str.back() == 'b')
+					default_base = 2;
+				else if (ast->str.back() == 'o')
+					default_base = 8;
+				else if (ast->str.back() == 'h')
+					default_base = 16;
+
+				std::vector<VerilogFmtArg> args;
+				for (auto node : ast->children) {
+					int width;
+					bool is_signed;
+					node->detectSignWidth(width, is_signed, nullptr);
+
+					VerilogFmtArg arg = {};
+					arg.filename = node->filename;
+					arg.first_line = node->location.first_line;
+					if (node->type == AST_CONSTANT && node->is_string) {
+						arg.type = VerilogFmtArg::STRING;
+						arg.str = node->bitsAsConst().decode_string();
+						// and in case this will be used as an argument...
+						arg.sig = node->bitsAsConst();
+						arg.signed_ = false;
+					} else if (node->type == AST_IDENTIFIER && node->str == "$time") {
+						arg.type = VerilogFmtArg::TIME;
+					} else if (node->type == AST_IDENTIFIER && node->str == "$realtime") {
+						arg.type = VerilogFmtArg::TIME;
+						arg.realtime = true;
+					} else {
+						arg.type = VerilogFmtArg::INTEGER;
+						arg.sig = node->genWidthRTLIL(-1, false, &subst_rvalue_map.stdmap());
+						arg.signed_ = is_signed;
+					}
+					args.push_back(arg);
+				}
+
+				Fmt fmt;
+				fmt.parse_verilog(args, /*sformat_like=*/false, default_base, /*task_name=*/ast->str, current_module->name);
+				if (ast->str.substr(0, 8) == "$display")
+					fmt.append_literal("\n");
+				fmt.emit_rtlil(cell);
+			} else if (!ast->str.empty()) {
+				log_file_error(ast->filename, ast->location.first_line, "Found unsupported invocation of system task `%s'!\n", ast->str.c_str());
+			}
+			break;
+
+		// generate $check cells
+		case AST_ASSERT:
+		case AST_ASSUME:
+		case AST_LIVE:
+		case AST_FAIR:
+		case AST_COVER:
+			{
+				std::string flavor, desc;
+				if (ast->type == AST_ASSERT) { flavor = "assert"; desc = "assert ()"; }
+				if (ast->type == AST_ASSUME) { flavor = "assume"; desc = "assume ()"; }
+				if (ast->type == AST_LIVE) { flavor = "live"; desc = "assert (eventually)"; }
+				if (ast->type == AST_FAIR) { flavor = "fair"; desc = "assume (eventually)"; }
+				if (ast->type == AST_COVER) { flavor = "cover"; desc = "cover ()"; }
+
+				IdString cellname;
+				if (ast->str.empty())
+					cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(ast->filename).c_str(), ast->location.first_line, autoidx++);
+				else
+					cellname = ast->str;
+				check_unique_id(current_module, cellname, ast, "procedural assertion");
+
+				RTLIL::SigSpec check = ast->children[0]->genWidthRTLIL(-1, false, &subst_rvalue_map.stdmap());
+				if (GetSize(check) != 1)
+					check = current_module->ReduceBool(NEW_ID, check);
+
+				Wire *en = current_module->addWire(cellname.str() + "_EN", 1);
+				set_src_attr(en, ast);
+				proc->root_case.actions.push_back(SigSig(en, false));
+				current_case->actions.push_back(SigSig(en, true));
+
+				RTLIL::SigSpec triggers;
+				RTLIL::Const polarity;
+				for (auto sync : proc->syncs) {
+					if (sync->type == RTLIL::STp) {
+						triggers.append(sync->signal);
+						polarity.bits.push_back(RTLIL::S1);
+					} else if (sync->type == RTLIL::STn) {
+						triggers.append(sync->signal);
+						polarity.bits.push_back(RTLIL::S0);
+					}
+				}
+
+				RTLIL::Cell *cell = current_module->addCell(cellname, ID($check));
+				set_src_attr(cell, ast);
+				for (auto &attr : ast->attributes) {
+					if (attr.second->type != AST_CONSTANT)
+						log_file_error(ast->filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
+					cell->attributes[attr.first] = attr.second->asAttrConst();
+				}
+				cell->setParam(ID::FLAVOR, flavor);
+				cell->setParam(ID::TRG_WIDTH, triggers.size());
+				cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty());
+				cell->setParam(ID::TRG_POLARITY, polarity);
+				cell->setParam(ID::PRIORITY, --last_effect_priority);
+				cell->setPort(ID::TRG, triggers);
+				cell->setPort(ID::EN, en);
+				cell->setPort(ID::A, check);
+
+				// No message is emitted to ensure Verilog code roundtrips correctly.
+				Fmt fmt;
+				fmt.emit_rtlil(cell);
+				break;
+			}
+
+		case AST_NONE:
 		case AST_FOR:
 			break;
 
@@ -845,7 +1012,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 				this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
 			} else {
 				if (id_ast->children[0]->type != AST_CONSTANT)
-					while (id_ast->simplify(true, false, 1, -1, false, true)) { }
+					while (id_ast->simplify(true, 1, -1, false)) { }
 				if (id_ast->children[0]->type == AST_CONSTANT)
 					this_width = id_ast->children[0]->bits.size();
 				else
@@ -878,7 +1045,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 			if (children.size() > 1)
 				range = children[1];
 		} else if (id_ast->type == AST_STRUCT_ITEM || id_ast->type == AST_STRUCT || id_ast->type == AST_UNION) {
-			AstNode *tmp_range = make_struct_member_range(this, id_ast);
+			AstNode *tmp_range = make_index_range(id_ast);
 			this_width = tmp_range->range_left - tmp_range->range_right + 1;
 			delete tmp_range;
 		} else
@@ -889,8 +1056,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 			else if (!range->range_valid) {
 				AstNode *left_at_zero_ast = children[0]->children[0]->clone_at_zero();
 				AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone_at_zero() : left_at_zero_ast->clone();
-				while (left_at_zero_ast->simplify(true, false, 1, -1, false, false)) { }
-				while (right_at_zero_ast->simplify(true, false, 1, -1, false, false)) { }
+				while (left_at_zero_ast->simplify(true, 1, -1, false)) { }
+				while (right_at_zero_ast->simplify(true, 1, -1, false)) { }
 				if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
 					input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
 				this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
@@ -906,7 +1073,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 		break;
 
 	case AST_TO_BITS:
-		while (children[0]->simplify(true, false, 1, -1, false, false) == true) { }
+		while (children[0]->simplify(true, 1, -1, false) == true) { }
 		if (children[0]->type != AST_CONSTANT)
 			input_error("Left operand of tobits expression is not constant!\n");
 		children[1]->detectSignWidthWorker(sub_width_hint, sign_hint);
@@ -928,7 +1095,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 		break;
 
 	case AST_CAST_SIZE:
-		while (children.at(0)->simplify(true, false, 1, -1, false, false)) { }
+		while (children.at(0)->simplify(true, 1, -1, false)) { }
 		if (children.at(0)->type != AST_CONSTANT)
 			input_error("Static cast with non constant expression!\n");
 		children.at(1)->detectSignWidthWorker(width_hint, sign_hint);
@@ -950,7 +1117,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 		break;
 
 	case AST_REPLICATE:
-		while (children[0]->simplify(true, false, 1, -1, false, true) == true) { }
+		while (children[0]->simplify(true, 1, -1, false) == true) { }
 		if (children[0]->type != AST_CONSTANT)
 			input_error("Left operand of replicate expression is not constant!\n");
 		children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
@@ -1062,7 +1229,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 	case AST_PREFIX:
 		// Prefix nodes always resolve to identifiers in generate loops, so we
 		// can simply perform the resolution to determine the sign and width.
-		simplify(true, false, 1, -1, false, false);
+		simplify(true, 1, -1, false);
 		log_assert(type == AST_IDENTIFIER);
 		detectSignWidthWorker(width_hint, sign_hint, found_real);
 		break;
@@ -1070,7 +1237,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 	case AST_FCALL:
 		if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {
 			if (GetSize(children) == 1) {
-				while (children[0]->simplify(true, false, 1, -1, false, true) == true) { }
+				while (children[0]->simplify(true, 1, -1, false) == true) { }
 				if (children[0]->type != AST_CONSTANT)
 					input_error("System function %s called with non-const argument!\n",
 							RTLIL::unescape_id(str).c_str());
@@ -1117,8 +1284,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 				log_assert(range->type == AST_RANGE && range->children.size() == 2);
 				AstNode *left = range->children.at(0)->clone();
 				AstNode *right = range->children.at(1)->clone();
-				while (left->simplify(true, false, 1, -1, false, true)) { }
-				while (right->simplify(true, false, 1, -1, false, true)) { }
+				left->set_in_param_flag(true);
+				right->set_in_param_flag(true);
+				while (left->simplify(true, 1, -1, false)) { }
+				while (right->simplify(true, 1, -1, false)) { }
 				if (left->type != AST_CONSTANT || right->type != AST_CONSTANT)
 					input_error("Function %s has non-constant width!",
 							RTLIL::unescape_id(str).c_str());
@@ -1158,28 +1327,6 @@ void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real
 					width_hint, kWidthLimit);
 }
 
-static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,
-		const AstNode *node, const char *to_add_kind)
-{
-	auto already_exists = [&](const RTLIL::AttrObject *existing, const char *existing_kind) {
-		std::string src = existing->get_string_attribute(ID::src);
-		std::string location_str = "earlier";
-		if (!src.empty())
-			location_str = "at " + src;
-		node->input_error("Cannot add %s `%s' because a %s with the same name was already created %s!\n",
-						  to_add_kind, id.c_str(), existing_kind, location_str.c_str());
-	};
-
-	if (const RTLIL::Wire *wire = module->wire(id))
-		already_exists(wire, "signal");
-	if (const RTLIL::Cell *cell = module->cell(id))
-		already_exists(cell, "cell");
-	if (module->processes.count(id))
-		already_exists(module->processes.at(id), "process");
-	if (module->memories.count(id))
-		already_exists(module->memories.at(id), "memory");
-}
-
 // create RTLIL from an AST node
 // all generated cells, wires and processes are added to the module pointed to by 'current_module'
 // when the AST node is an expression (AST_ADD, AST_BIT_XOR, etc.), the result signal is returned.
@@ -1437,7 +1584,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			chunk.width = wire->width;
 			chunk.offset = 0;
 
-			if ((member_node = get_struct_member(this))) {
+			if ((member_node = get_struct_member())) {
 				// Clamp wire chunk to range of member within struct/union.
 				chunk.width = member_node->range_left - member_node->range_right + 1;
 				chunk.offset = member_node->range_right;
@@ -1462,8 +1609,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				if (!children[0]->range_valid) {
 					AstNode *left_at_zero_ast = children[0]->children[0]->clone_at_zero();
 					AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone_at_zero() : left_at_zero_ast->clone();
-					while (left_at_zero_ast->simplify(true, false, 1, -1, false, false)) { }
-					while (right_at_zero_ast->simplify(true, false, 1, -1, false, false)) { }
+					while (left_at_zero_ast->simplify(true, 1, -1, false)) { }
+					while (right_at_zero_ast->simplify(true, 1, -1, false)) { }
 					if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
 						input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
 					int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
@@ -1471,7 +1618,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 							children[0]->children[1]->clone() : children[0]->children[0]->clone());
 					fake_ast->children[0]->delete_children();
 					if (member_node)
-						fake_ast->children[0]->attributes[ID::wiretype] = member_node->clone();
+						fake_ast->children[0]->set_attribute(ID::wiretype, member_node->clone());
 
 					int fake_ast_width = 0;
 					bool fake_ast_sign = true;
@@ -1656,7 +1803,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			if (width_hint < 0)
 				detectSignWidth(width_hint, sign_hint);
 			RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
-			RTLIL::SigSpec right = children[1]->genRTLIL();
+			// for $shift and $shiftx, the second operand can be negative
+			RTLIL::SigSpec right = children[1]->genRTLIL(-1, type == AST_SHIFT || type == AST_SHIFTX);
 			int width = width_hint > 0 ? width_hint : left.size();
 			is_signed = children[0]->is_signed;
 			return binop2rtlil(this, type_name, width, left, right);
@@ -1860,48 +2008,50 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		}
 		break;
 
-	// generate $assert cells
+	// generate $check cells
 	case AST_ASSERT:
 	case AST_ASSUME:
 	case AST_LIVE:
 	case AST_FAIR:
 	case AST_COVER:
 		{
-			IdString celltype;
-			if (type == AST_ASSERT) celltype = ID($assert);
-			if (type == AST_ASSUME) celltype = ID($assume);
-			if (type == AST_LIVE) celltype = ID($live);
-			if (type == AST_FAIR) celltype = ID($fair);
-			if (type == AST_COVER) celltype = ID($cover);
-
-			log_assert(children.size() == 2);
-
-			RTLIL::SigSpec check = children[0]->genRTLIL();
-			if (GetSize(check) != 1)
-				check = current_module->ReduceBool(NEW_ID, check);
-
-			RTLIL::SigSpec en = children[1]->genRTLIL();
-			if (GetSize(en) != 1)
-				en = current_module->ReduceBool(NEW_ID, en);
+			std::string flavor, desc;
+			if (type == AST_ASSERT) { flavor = "assert"; desc = "assert property ()"; }
+			if (type == AST_ASSUME) { flavor = "assume"; desc = "assume property ()"; }
+			if (type == AST_LIVE) { flavor = "live"; desc = "assert property (eventually)"; }
+			if (type == AST_FAIR) { flavor = "fair"; desc = "assume property (eventually)"; }
+			if (type == AST_COVER) { flavor = "cover"; desc = "cover property ()"; }
 
 			IdString cellname;
 			if (str.empty())
-				cellname = stringf("%s$%s:%d$%d", celltype.c_str(), RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
+				cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
 			else
 				cellname = str;
-
 			check_unique_id(current_module, cellname, this, "procedural assertion");
-			RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
-			set_src_attr(cell, this);
 
+			RTLIL::SigSpec check = children[0]->genRTLIL();
+			if (GetSize(check) != 1)
+				check = current_module->ReduceBool(NEW_ID, check);
+
+			RTLIL::Cell *cell = current_module->addCell(cellname, ID($check));
+			set_src_attr(cell, this);
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
 					input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
 				cell->attributes[attr.first] = attr.second->asAttrConst();
 			}
-
+			cell->setParam(ID(FLAVOR), flavor);
+			cell->parameters[ID::TRG_WIDTH] = 0;
+			cell->parameters[ID::TRG_ENABLE] = 0;
+			cell->parameters[ID::TRG_POLARITY] = 0;
+			cell->parameters[ID::PRIORITY] = 0;
+			cell->setPort(ID::TRG, RTLIL::SigSpec());
+			cell->setPort(ID::EN, RTLIL::S1);
 			cell->setPort(ID::A, check);
-			cell->setPort(ID::EN, en);
+
+			// No message is emitted to ensure Verilog code roundtrips correctly.
+			Fmt fmt;
+			fmt.emit_rtlil(cell);
 		}
 		break;
 
@@ -2074,7 +2224,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				else
 					input_error("FATAL.\n");
 			} else {
-				input_error("Unknown elabortoon system task '%s'.\n", str.c_str());
+				input_error("Unknown elaboration system task '%s'.\n", str.c_str());
 			}
 		} break;
 
diff --git a/yosys/frontends/ast/simplify.cc b/yosys/frontends/ast/simplify.cc
index 64191cd7ebf..3d8478ef160 100644
--- a/yosys/frontends/ast/simplify.cc
+++ b/yosys/frontends/ast/simplify.cc
@@ -35,149 +35,153 @@
 #include <stdarg.h>
 #include <stdlib.h>
 #include <math.h>
+// For std::gcd in C++17
+// #include <numeric>
 
 YOSYS_NAMESPACE_BEGIN
 
 using namespace AST;
 using namespace AST_INTERNAL;
 
-// Process a format string and arguments for $display, $write, $sprintf, etc
-
-std::string AstNode::process_format_str(const std::string &sformat, int next_arg, int stage, int width_hint, bool sign_hint) {
-	// Other arguments are placeholders. Process the string as we go through it
-	std::string sout;
-	for (size_t i = 0; i < sformat.length(); i++)
-	{
-		// format specifier
-		if (sformat[i] == '%')
-		{
-			// If there's no next character, that's a problem
-			if (i+1 >= sformat.length())
-				input_error("System task `%s' called with `%%' at end of string.\n", str.c_str());
-
-			char cformat = sformat[++i];
-
-			// %% is special, does not need a matching argument
-			if (cformat == '%')
-			{
-				sout += '%';
-				continue;
-			}
-
-			bool got_len = false;
-			bool got_zlen = false;
-			int len_value = 0;
-
-			while ('0' <= cformat && cformat <= '9')
-			{
-				if (!got_len && cformat == '0')
-					got_zlen = true;
-
-				got_len = true;
-				len_value = 10*len_value + (cformat - '0');
+// gcd computed by Euclidian division.
+// To be replaced by C++17 std::gcd
+template<class I> I gcd(I a, I b) {
+	while (b != 0) {
+		I tmp = b;
+		b = a%b;
+		a = tmp;
+	}
+	return std::abs(a);
+}
 
-				cformat = sformat[++i];
-			}
+void AstNode::set_in_lvalue_flag(bool flag, bool no_descend)
+{
+	if (flag != in_lvalue_from_above) {
+		in_lvalue_from_above = flag;
+		if (!no_descend)
+			fixup_hierarchy_flags();
+	}
+}
 
-			// Simplify the argument
-			AstNode *node_arg = nullptr;
+void AstNode::set_in_param_flag(bool flag, bool no_descend)
+{
+	if (flag != in_param_from_above) {
+		in_param_from_above = flag;
+		if (!no_descend)
+			fixup_hierarchy_flags();
+	}
+}
 
-			// Everything from here on depends on the format specifier
-			switch (cformat)
-			{
-				case 's':
-				case 'S':
-				case 'd':
-				case 'D':
-					if (got_len && len_value != 0)
-						goto unsupported_format;
-					YS_FALLTHROUGH
-				case 'x':
-				case 'X':
-					if (next_arg >= GetSize(children))
-						input_error("Missing argument for %%%c format specifier in system task `%s'.\n",
-								cformat, str.c_str());
-
-					node_arg = children[next_arg++];
-					while (node_arg->simplify(true, false, stage, width_hint, sign_hint, false)) { }
-					if (node_arg->type != AST_CONSTANT)
-						input_error("Failed to evaluate system task `%s' with non-constant argument.\n", str.c_str());
-					break;
+void AstNode::fixup_hierarchy_flags(bool force_descend)
+{
+	// With forced descend, we disable the implicit
+	// descend from within the set_* functions, instead
+	// we do an explicit descend at the end of this function
 
-				case 'm':
-				case 'M':
-					if (got_len)
-						goto unsupported_format;
-					break;
+	in_param = in_param_from_above;
 
-				case 'l':
-				case 'L':
-					if (got_len)
-						goto unsupported_format;
-					break;
+	switch (type) {
+	case AST_PARAMETER:
+	case AST_LOCALPARAM:
+	case AST_DEFPARAM:
+	case AST_PARASET:
+	case AST_PREFIX:
+		in_param = true;
+		for (auto child : children)
+			child->set_in_param_flag(true, force_descend);
+		break;
 
-				default:
-				unsupported_format:
-					input_error("System task `%s' called with invalid/unsupported format specifier.\n", str.c_str());
-					break;
-			}
+	case AST_REPLICATE:
+	case AST_WIRE:
+	case AST_GENIF:
+	case AST_GENCASE:
+		for (auto child : children)
+			child->set_in_param_flag(in_param, force_descend);
+		if (children.size() >= 1)
+			children[0]->set_in_param_flag(true, force_descend);
+		break;
 
-			switch (cformat)
-			{
-				case 's':
-				case 'S':
-					sout += node_arg->bitsAsConst().decode_string();
-					break;
+	case AST_GENFOR:
+	case AST_FOR:
+		for (auto child : children)
+			child->set_in_param_flag(in_param, force_descend);
+		if (children.size() >= 2)
+			children[1]->set_in_param_flag(true, force_descend);
+		break;
 
-				case 'd':
-				case 'D':
-					sout += stringf("%d", node_arg->bitsAsConst().as_int());
-					break;
+	default:
+		in_param = in_param_from_above;
+		for (auto child : children)
+			child->set_in_param_flag(in_param, force_descend);
+	}
 
-				case 'x':
-				case 'X':
-					{
-						Const val = node_arg->bitsAsConst();
+	for (auto attr : attributes)
+		attr.second->set_in_param_flag(true, force_descend);
 
-						while (GetSize(val) % 4 != 0)
-							val.bits.push_back(State::S0);
+	in_lvalue = in_lvalue_from_above;
 
-						int len = GetSize(val) / 4;
-						for (int i = len; i < len_value; i++)
-							sout += got_zlen ? '0' : ' ';
+	switch (type) {
+	case AST_ASSIGN:
+	case AST_ASSIGN_EQ:
+	case AST_ASSIGN_LE:
+		if (children.size() >= 1)
+			children[0]->set_in_lvalue_flag(true, force_descend);
+		if (children.size() >= 2)
+			children[1]->set_in_lvalue_flag(in_lvalue, force_descend);
+		break;
 
-						for (int i = len-1; i >= 0; i--) {
-							Const digit = val.extract(4*i, 4);
-							if (digit.is_fully_def())
-								sout += stringf(cformat == 'x' ? "%x" : "%X", digit.as_int());
-							else
-								sout += cformat == 'x' ? "x" : "X";
-						}
-					}
-					break;
+	default:
+		for (auto child : children)
+			child->set_in_lvalue_flag(in_lvalue, force_descend);
+	}
 
-				case 'm':
-				case 'M':
-					sout += log_id(current_module->name);
-					break;
+	if (force_descend) {
+		for (auto child : children)
+			child->fixup_hierarchy_flags(true);
+		for (auto attr : attributes)
+			attr.second->fixup_hierarchy_flags(true);
+	}
+}
 
-				case 'l':
-				case 'L':
-					sout += log_id(current_module->name);
-					break;
+// Process a format string and arguments for $display, $write, $sprintf, etc
 
-				default:
-					log_abort();
-			}
+Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_t first_arg_at, bool may_fail) {
+	std::vector<VerilogFmtArg> args;
+	for (size_t index = first_arg_at; index < children.size(); index++) {
+		AstNode *node_arg = children[index];
+		while (node_arg->simplify(true, stage, -1, false)) { }
+
+		VerilogFmtArg arg = {};
+		arg.filename = filename;
+		arg.first_line = location.first_line;
+		if (node_arg->type == AST_CONSTANT && node_arg->is_string) {
+			arg.type = VerilogFmtArg::STRING;
+			arg.str = node_arg->bitsAsConst().decode_string();
+			// and in case this will be used as an argument...
+			arg.sig = node_arg->bitsAsConst();
+			arg.signed_ = false;
+		} else if (node_arg->type == AST_IDENTIFIER && node_arg->str == "$time") {
+			arg.type = VerilogFmtArg::TIME;
+		} else if (node_arg->type == AST_IDENTIFIER && node_arg->str == "$realtime") {
+			arg.type = VerilogFmtArg::TIME;
+			arg.realtime = true;
+		} else if (node_arg->type == AST_CONSTANT) {
+			arg.type = VerilogFmtArg::INTEGER;
+			arg.sig = node_arg->bitsAsConst();
+			arg.signed_ = node_arg->is_signed;
+		} else if (may_fail) {
+			log_file_info(filename, location.first_line, "Skipping system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1);
+			return Fmt();
+		} else {
+			log_file_error(filename, location.first_line, "Failed to evaluate system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1);
 		}
-
-		// not a format specifier
-		else
-			sout += sformat[i];
+		args.push_back(arg);
 	}
-	return sout;
-}
 
+	Fmt fmt;
+	fmt.parse_verilog(args, sformat_like, default_base, /*task_name=*/str, current_module->name);
+	return fmt;
+}
 
 void AstNode::annotateTypedEnums(AstNode *template_node)
 {
@@ -192,7 +196,7 @@ void AstNode::annotateTypedEnums(AstNode *template_node)
 		log_assert(current_scope.count(enum_type) == 1);
 		AstNode *enum_node = current_scope.at(enum_type);
 		log_assert(enum_node->type == AST_ENUM);
-		while (enum_node->simplify(true, false, 1, -1, false, true)) { }
+		while (enum_node->simplify(true, 1, -1, false)) { }
 		//get width from 1st enum item:
 		log_assert(enum_node->children.size() >= 1);
 		AstNode *enum_item0 = enum_node->children[0];
@@ -216,8 +220,8 @@ void AstNode::annotateTypedEnums(AstNode *template_node)
 				log_assert(enum_item->children[1]->type == AST_RANGE);
 				is_signed = enum_item->children[1]->is_signed;
 			} else {
-				log_error("enum_item children size==%lu, expected 1 or 2 for %s (%s)\n",
-						  enum_item->children.size(),
+				log_error("enum_item children size==%zu, expected 1 or 2 for %s (%s)\n",
+						  (size_t) enum_item->children.size(),
 						  enum_item->str.c_str(), enum_node->str.c_str()
 				);
 			}
@@ -233,22 +237,11 @@ void AstNode::annotateTypedEnums(AstNode *template_node)
 			RTLIL::Const val = enum_item->children[0]->bitsAsConst(width, is_signed);
 			enum_item_str.append(val.as_string());
 			//set attribute for available val to enum item name mappings
-			attributes[enum_item_str.c_str()] = mkconst_str(enum_item->str);
+			set_attribute(enum_item_str.c_str(), mkconst_str(enum_item->str));
 		}
 	}
 }
 
-static bool name_has_dot(const std::string &name, std::string &struct_name)
-{
-	// check if plausible struct member name \sss.mmm
-	std::string::size_type pos;
-	if (name.substr(0, 1) == "\\" && (pos = name.find('.', 0)) != std::string::npos) {
-		struct_name = name.substr(0, pos);
-		return true;
-	}
-	return false;
-}
-
 static AstNode *make_range(int left, int right, bool is_signed = false)
 {
 	// generate a pre-validated range node for a fixed signal range.
@@ -266,33 +259,22 @@ static int range_width(AstNode *node, AstNode *rnode)
 {
 	log_assert(rnode->type==AST_RANGE);
 	if (!rnode->range_valid) {
-		node->input_error("Size must be constant in packed struct/union member %s\n", node->str.c_str());
-
+		node->input_error("Non-constant range in declaration of %s\n", node->str.c_str());
 	}
 	// note: range swapping has already been checked for
 	return rnode->range_left - rnode->range_right + 1;
 }
 
-[[noreturn]] static void struct_array_packing_error(AstNode *node)
+static int add_dimension(AstNode *node, AstNode *rnode)
 {
-	node->input_error("Unpacked array in packed struct/union member %s\n", node->str.c_str());
+	int width = range_width(node, rnode);
+	node->dimensions.push_back({ rnode->range_right, width, rnode->range_swapped });
+	return width;
 }
 
-static void save_struct_range_dimensions(AstNode *node, AstNode *rnode)
-{
-	node->multirange_dimensions.push_back(rnode->range_right);
-	node->multirange_dimensions.push_back(range_width(node, rnode));
-	node->multirange_swapped.push_back(rnode->range_swapped);
-}
-
-static int get_struct_range_offset(AstNode *node, int dimension)
-{
-	return node->multirange_dimensions[2*dimension];
-}
-
-static int get_struct_range_width(AstNode *node, int dimension)
+[[noreturn]] static void struct_array_packing_error(AstNode *node)
 {
-	return node->multirange_dimensions[2*dimension + 1];
+	node->input_error("Unpacked array in packed struct/union member %s\n", node->str.c_str());
 }
 
 static int size_packed_struct(AstNode *snode, int base_offset)
@@ -310,10 +292,6 @@ static int size_packed_struct(AstNode *snode, int base_offset)
 		if (node->type == AST_STRUCT || node->type == AST_UNION) {
 			// embedded struct or union
 			width = size_packed_struct(node, base_offset + offset);
-			// set range of struct
-			node->range_right = base_offset + offset;
-			node->range_left = base_offset + offset + width - 1;
-			node->range_valid = true;
 		}
 		else {
 			log_assert(node->type == AST_STRUCT_ITEM);
@@ -325,18 +303,16 @@ static int size_packed_struct(AstNode *snode, int base_offset)
 					// and integer data types are allowed in packed structs / unions in SystemVerilog.
 					if (node->children[1]->type == AST_RANGE) {
 						// Unpacked array, e.g. bit [63:0] a [0:3]
+						// Pretend it's declared as a packed array, e.g. bit [0:3][63:0] a
 						auto rnode = node->children[1];
 						if (rnode->children.size() == 1) {
 							// C-style array size, e.g. bit [63:0] a [4]
-							node->multirange_dimensions.push_back(0);
-							node->multirange_dimensions.push_back(rnode->range_left);
-							node->multirange_swapped.push_back(true);
+							node->dimensions.push_back({ 0, rnode->range_left, true });
 							width *= rnode->range_left;
 						} else {
-							save_struct_range_dimensions(node, rnode);
-							width *= range_width(node, rnode);
+							width *= add_dimension(node, rnode);
 						}
-						save_struct_range_dimensions(node, node->children[0]);
+						add_dimension(node, node->children[0]);
 					}
 					else {
 						// The Yosys extension for unpacked arrays in packed structs / unions
@@ -345,7 +321,7 @@ static int size_packed_struct(AstNode *snode, int base_offset)
 					}
 				} else {
 					// Vector
-					save_struct_range_dimensions(node, node->children[0]);
+					add_dimension(node, node->children[0]);
 				}
 				// range nodes are now redundant
 				for (AstNode *child : node->children)
@@ -361,8 +337,7 @@ static int size_packed_struct(AstNode *snode, int base_offset)
 				}
 				width = 1;
 				for (auto rnode : node->children[0]->children) {
-					save_struct_range_dimensions(node, rnode);
-					width *= range_width(node, rnode);
+					width *= add_dimension(node, rnode);
 				}
 				// range nodes are now redundant
 				for (AstNode *child : node->children)
@@ -372,6 +347,7 @@ static int size_packed_struct(AstNode *snode, int base_offset)
 			else if (node->range_left < 0) {
 				// 1 bit signal: bit, logic or reg
 				width = 1;
+				node->dimensions.push_back({ 0, width, false });
 			}
 			else {
 				// already resolved and compacted
@@ -402,12 +378,15 @@ static int size_packed_struct(AstNode *snode, int base_offset)
 			offset += width;
 		}
 	}
-	return (is_union ? packed_width : offset);
-}
 
-[[noreturn]] static void struct_op_error(AstNode *node)
-{
-	node->input_error("Unsupported operation for struct/union member %s\n", node->str.c_str()+1);
+	int width = is_union ? packed_width : offset;
+
+	snode->range_right = base_offset;
+	snode->range_left = base_offset + width - 1;
+	snode->range_valid = true;
+	snode->dimensions.push_back({ 0, width, false });
+
+	return width;
 }
 
 static AstNode *node_int(int ival)
@@ -420,113 +399,123 @@ static AstNode *multiply_by_const(AstNode *expr_node, int stride)
 	return new AstNode(AST_MUL, expr_node, node_int(stride));
 }
 
-static AstNode *normalize_struct_index(AstNode *expr, AstNode *member_node, int dimension)
+static AstNode *normalize_index(AstNode *expr, AstNode *decl_node, int dimension)
 {
 	expr = expr->clone();
 
-	int offset = get_struct_range_offset(member_node, dimension);
+	int offset = decl_node->dimensions[dimension].range_right;
 	if (offset) {
 		expr = new AstNode(AST_SUB, expr, node_int(offset));
 	}
 
-	if (member_node->multirange_swapped[dimension]) {
-		// The dimension has swapped range; swap index into the struct accordingly.
-		int msb = get_struct_range_width(member_node, dimension) - 1;
-		expr = new AstNode(AST_SUB, node_int(msb), expr);
+	// Packed dimensions are normally indexed by lsb, while unpacked dimensions are normally indexed by msb.
+	if ((dimension < decl_node->unpacked_dimensions) ^ decl_node->dimensions[dimension].range_swapped) {
+		// Swap the index if the dimension is declared the "wrong" way.
+		int left = decl_node->dimensions[dimension].range_width - 1;
+		expr = new AstNode(AST_SUB, node_int(left), expr);
 	}
 
 	return expr;
 }
 
-static AstNode *struct_index_lsb_offset(AstNode *lsb_offset, AstNode *rnode, AstNode *member_node, int dimension, int &stride)
+static AstNode *index_offset(AstNode *offset, AstNode *rnode, AstNode *decl_node, int dimension, int &stride)
 {
-	stride /= get_struct_range_width(member_node, dimension);
-	auto right = normalize_struct_index(rnode->children.back(), member_node, dimension);
-	auto offset = stride > 1 ? multiply_by_const(right, stride) : right;
-	return lsb_offset ? new AstNode(AST_ADD, lsb_offset, offset) : offset;
+	stride /= decl_node->dimensions[dimension].range_width;
+	auto right = normalize_index(rnode->children.back(), decl_node, dimension);
+	auto add_offset = stride > 1 ? multiply_by_const(right, stride) : right;
+	return offset ? new AstNode(AST_ADD, offset, add_offset) : add_offset;
 }
 
-static AstNode *struct_index_msb_offset(AstNode *lsb_offset, AstNode *rnode, AstNode *member_node, int dimension, int stride)
+static AstNode *index_msb_offset(AstNode *lsb_offset, AstNode *rnode, AstNode *decl_node, int dimension, int stride)
 {
 	log_assert(rnode->children.size() <= 2);
 
 	// Offset to add to LSB
-	AstNode *offset;
+	AstNode *add_offset;
 	if (rnode->children.size() == 1) {
 		// Index, e.g. s.a[i]
-		offset = node_int(stride - 1);
+		add_offset = node_int(stride - 1);
 	}
 	else {
 		// rnode->children.size() == 2
 		// Slice, e.g. s.a[i:j]
-		auto left = normalize_struct_index(rnode->children[0], member_node, dimension);
-		auto right = normalize_struct_index(rnode->children[1], member_node, dimension);
-		offset = new AstNode(AST_SUB, left, right);
+		auto left = normalize_index(rnode->children[0], decl_node, dimension);
+		auto right = normalize_index(rnode->children[1], decl_node, dimension);
+		add_offset = new AstNode(AST_SUB, left, right);
 		if (stride > 1) {
 			// offset = (msb - lsb + 1)*stride - 1
-			auto slice_width = new AstNode(AST_ADD, offset, node_int(1));
-			offset = new AstNode(AST_SUB, multiply_by_const(slice_width, stride), node_int(1));
+			auto slice_width = new AstNode(AST_ADD, add_offset, node_int(1));
+			add_offset = new AstNode(AST_SUB, multiply_by_const(slice_width, stride), node_int(1));
 		}
 	}
 
-	return new AstNode(AST_ADD, lsb_offset, offset);
+	return new AstNode(AST_ADD, lsb_offset, add_offset);
 }
 
 
-AstNode *AST::make_struct_member_range(AstNode *node, AstNode *member_node)
+AstNode *AstNode::make_index_range(AstNode *decl_node, bool unpacked_range)
 {
 	// Work out the range in the packed array that corresponds to a struct member
 	// taking into account any range operations applicable to the current node
 	// such as array indexing or slicing
-	int range_left = member_node->range_left;
-	int range_right = member_node->range_right;
-	if (node->children.empty()) {
+	if (children.empty()) {
 		// no range operations apply, return the whole width
-		return make_range(range_left - range_right, 0);
+		return make_range(decl_node->range_left - decl_node->range_right, 0);
 	}
 
-	if (node->children.size() != 1) {
-		struct_op_error(node);
-	}
+	log_assert(children.size() == 1);
 
 	// Range operations
-	auto rnode = node->children[0];
-	AstNode *lsb_offset = NULL;
-	int stride = range_left - range_right + 1;
-	size_t i = 0;
+	AstNode *rnode = children[0];
+	AstNode *offset = NULL;
+	int dim = unpacked_range ? 0 : decl_node->unpacked_dimensions;
+	int max_dim = unpacked_range ? decl_node->unpacked_dimensions : GetSize(decl_node->dimensions);
+
+	int stride = 1;
+	for (int i = dim; i < max_dim; i++) {
+		stride *= decl_node->dimensions[i].range_width;
+	}
 
 	// Calculate LSB offset for the final index / slice
 	if (rnode->type == AST_RANGE) {
-		lsb_offset = struct_index_lsb_offset(lsb_offset, rnode, member_node, i, stride);
+		offset = index_offset(offset, rnode, decl_node, dim, stride);
 	}
 	else if (rnode->type == AST_MULTIRANGE) {
 		// Add offset for each dimension
-		auto mrnode = rnode;
-		for (i = 0; i < mrnode->children.size(); i++) {
-			rnode = mrnode->children[i];
-			lsb_offset = struct_index_lsb_offset(lsb_offset, rnode, member_node, i, stride);
+		AstNode *mrnode = rnode;
+		int stop_dim = std::min(GetSize(mrnode->children), max_dim);
+		for (; dim < stop_dim; dim++) {
+			rnode = mrnode->children[dim];
+			offset = index_offset(offset, rnode, decl_node, dim, stride);
 		}
-		i--;  // Step back to the final index / slice
+		dim--;  // Step back to the final index / slice
 	}
 	else {
-		struct_op_error(node);
+		input_error("Unsupported range operation for %s\n", str.c_str());
 	}
 
-	// Calculate MSB offset for the final index / slice
-	auto msb_offset = struct_index_msb_offset(lsb_offset->clone(), rnode, member_node, i, stride);
+	AstNode *index_range = new AstNode(AST_RANGE);
+
+	if (!unpacked_range && (stride > 1 || GetSize(rnode->children) == 2)) {
+		// Calculate MSB offset for the final index / slice of packed dimensions.
+		AstNode *msb_offset = index_msb_offset(offset->clone(), rnode, decl_node, dim, stride);
+		index_range->children.push_back(msb_offset);
+	}
 
-	return new AstNode(AST_RANGE, msb_offset, lsb_offset);
+	index_range->children.push_back(offset);
+
+	return index_range;
 }
 
-AstNode *AST::get_struct_member(const AstNode *node)
+AstNode *AstNode::get_struct_member() const
 {
-	AST::AstNode *member_node;
-	if (node->attributes.count(ID::wiretype) && (member_node = node->attributes.at(ID::wiretype)) &&
+	AstNode *member_node;
+	if (attributes.count(ID::wiretype) && (member_node = attributes.at(ID::wiretype)) &&
 	    (member_node->type == AST_STRUCT_ITEM || member_node->type == AST_STRUCT || member_node->type == AST_UNION))
 	{
 		return member_node;
 	}
-	return NULL;
+	return nullptr;
 }
 
 static void add_members_to_scope(AstNode *snode, std::string name)
@@ -544,31 +533,19 @@ static void add_members_to_scope(AstNode *snode, std::string name)
 	}
 }
 
-static int get_max_offset(AstNode *node)
-{
-	// get the width from the MS member in the struct
-	// as members are laid out from left to right in the packed wire
-	log_assert(node->type==AST_STRUCT || node->type==AST_UNION);
-	while (node->type != AST_STRUCT_ITEM) {
-		node = node->children[0];
-	}
-	return node->range_left;
-}
-
 static AstNode *make_packed_struct(AstNode *template_node, std::string &name, decltype(AstNode::attributes) &attributes)
 {
 	// create a wire for the packed struct
-	auto wnode = new AstNode(AST_WIRE);
+	auto wnode = new AstNode(AST_WIRE, make_range(template_node->range_left, 0));
 	wnode->str = name;
 	wnode->is_logic = true;
 	wnode->range_valid = true;
 	wnode->is_signed = template_node->is_signed;
 	for (auto &pair : attributes) {
-		wnode->attributes[pair.first] = pair.second->clone();
+		wnode->set_attribute(pair.first, pair.second->clone());
 	}
-	int offset = get_max_offset(template_node);
-	auto range = make_range(offset, 0);
-	wnode->children.push_back(range);
+	// resolve packed dimension
+	while (wnode->simplify(true, 1, -1, false)) {}
 	// make sure this node is the one in scope for this name
 	current_scope[name] = wnode;
 	// add all the struct members to scope under the wire's name
@@ -576,6 +553,22 @@ static AstNode *make_packed_struct(AstNode *template_node, std::string &name, de
 	return wnode;
 }
 
+static void prepend_ranges(AstNode *&range, AstNode *range_add)
+{
+	// Convert range to multirange.
+	if (range->type == AST_RANGE)
+		range = new AstNode(AST_MULTIRANGE, range);
+
+	// Add range or ranges.
+	if (range_add->type == AST_RANGE)
+		range->children.insert(range->children.begin(), range_add->clone());
+	else {
+		int i = 0;
+		for (auto child : range_add->children)
+			range->children.insert(range->children.begin() + i++, child->clone());
+	}
+}
+
 // check if a node or its children contains an assignment to the given variable
 static bool node_contains_assignment_to(const AstNode* node, const AstNode* var)
 {
@@ -628,7 +621,7 @@ const RTLIL::Module* AstNode::lookup_cell_module()
 
 	auto reprocess_after = [this] (const std::string &modname) {
 		if (!attributes.count(ID::reprocess_after))
-			attributes[ID::reprocess_after] = AstNode::mkconst_str(modname);
+			set_attribute(ID::reprocess_after, AstNode::mkconst_str(modname));
 	};
 
 	const AstNode *celltype = nullptr;
@@ -793,7 +786,7 @@ AstNode *AstNode::clone_at_zero()
 				pointee->type != AST_MEMORY)
 			break;
 
-		YS_FALLTHROUGH;
+		YS_FALLTHROUGH
 	case AST_MEMRD:
 		detectSignWidth(width_hint, sign_hint);
 		return mkconst_int(0, sign_hint, width_hint);
@@ -808,6 +801,11 @@ AstNode *AstNode::clone_at_zero()
 		it = it->clone_at_zero();
 	for (auto &it : that->attributes)
 		it.second = it.second->clone();
+
+	that->set_in_lvalue_flag(false);
+	that->set_in_param_flag(false);
+	that->fixup_hierarchy_flags();
+
 	return that;
 }
 
@@ -823,8 +821,8 @@ static bool try_determine_range_width(AstNode *range, int &result_width)
 	AstNode *left_at_zero_ast = range->children[0]->clone_at_zero();
 	AstNode *right_at_zero_ast = range->children[1]->clone_at_zero();
 
-	while (left_at_zero_ast->simplify(true, false, 1, -1, false, false)) {}
-	while (right_at_zero_ast->simplify(true, false, 1, -1, false, false)) {}
+	while (left_at_zero_ast->simplify(true, 1, -1, false)) {}
+	while (right_at_zero_ast->simplify(true, 1, -1, false)) {}
 
 	bool ok = false;
 	if (left_at_zero_ast->type == AST_CONSTANT
@@ -846,8 +844,7 @@ static void mark_auto_nosync(AstNode *block, const AstNode *wire)
 {
 	log_assert(block->type == AST_BLOCK);
 	log_assert(wire->type == AST_WIRE);
-	block->attributes[auto_nosync_prefix + wire->str] = AstNode::mkconst_int(1,
-			false);
+	block->set_attribute(auto_nosync_prefix + wire->str, AstNode::mkconst_int(1, false));
 }
 
 // block names can be prefixed with an explicit scope during elaboration
@@ -888,7 +885,7 @@ static void check_auto_nosync(AstNode *node)
 		// mark the wire with `nosync`
 		AstNode *wire = it->second;
 		log_assert(wire->type == AST_WIRE);
-		wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
+		wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
 	}
 
 	// remove the attributes we've "consumed"
@@ -909,7 +906,7 @@ static void check_auto_nosync(AstNode *node)
 //
 // this function also does all name resolving and sets the id2ast member of all
 // nodes that link to a different node using names and lexical scoping.
-bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param)
+bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hint)
 {
 	static int recursion_counter = 0;
 	static bool deep_recursion_warning = false;
@@ -927,8 +924,8 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 #if 0
 	log("-------------\n");
 	log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, filename.c_str(), location.first_line, type2str(type).c_str(), this);
-	log("const_fold=%d, in_lvalue=%d, stage=%d, width_hint=%d, sign_hint=%d, in_param=%d\n",
-			int(const_fold), int(in_lvalue), int(stage), int(width_hint), int(sign_hint), int(in_param));
+	log("const_fold=%d, stage=%d, width_hint=%d, sign_hint=%d\n",
+			int(const_fold), int(stage), int(width_hint), int(sign_hint));
 	// dumpAst(NULL, "> ");
 #endif
 
@@ -937,7 +934,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		log_assert(type == AST_MODULE || type == AST_INTERFACE);
 
 		deep_recursion_warning = true;
-		while (simplify(const_fold, in_lvalue, 1, width_hint, sign_hint, in_param)) { }
+		while (simplify(const_fold, 1, width_hint, sign_hint)) { }
 
 		if (!flag_nomem2reg && !get_bool_attribute(ID::nomem2reg))
 		{
@@ -1016,11 +1013,11 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 					reg->is_signed = node->is_signed;
 					for (auto &it : node->attributes)
 						if (it.first != ID::mem2reg)
-							reg->attributes.emplace(it.first, it.second->clone());
+							reg->set_attribute(it.first, it.second->clone());
 					reg->filename = node->filename;
 					reg->location = node->location;
 					children.push_back(reg);
-					while (reg->simplify(true, false, 1, -1, false, false)) { }
+					while (reg->simplify(true, 1, -1, false)) { }
 				}
 			}
 
@@ -1034,7 +1031,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 				delete node;
 		}
 
-		while (simplify(const_fold, in_lvalue, 2, width_hint, sign_hint, in_param)) { }
+		while (simplify(const_fold, 2, width_hint, sign_hint)) { }
 		recursion_counter--;
 		return false;
 	}
@@ -1057,35 +1054,37 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		str = std::string();
 	}
 
-	if ((type == AST_TCALL) && (str == "$display" || str == "$write") && (!current_always || current_always->type != AST_INITIAL)) {
-		log_file_warning(filename, location.first_line, "System task `%s' outside initial block is unsupported.\n", str.c_str());
-		delete_children();
-		str = std::string();
-	}
-
-	// print messages if this a call to $display() or $write()
-	// This code implements only a small subset of Verilog-2005 $display() format specifiers,
-	// but should be good enough for most uses
-	if ((type == AST_TCALL) && ((str == "$display") || (str == "$write")))
+	if ((type == AST_TCALL) &&
+	    (str == "$display" || str == "$displayb" || str == "$displayh" || str == "$displayo" ||
+	     str == "$write"   || str == "$writeb"   || str == "$writeh"   || str == "$writeo"))
 	{
-		int nargs = GetSize(children);
-		if (nargs < 1)
-			input_error("System task `%s' got %d arguments, expected >= 1.\n",
-					str.c_str(), int(children.size()));
-
-		// First argument is the format string
-		AstNode *node_string = children[0];
-		while (node_string->simplify(true, false, stage, width_hint, sign_hint, false)) { }
-		if (node_string->type != AST_CONSTANT)
-			input_error("Failed to evaluate system task `%s' with non-constant 1st argument.\n", str.c_str());
-		std::string sformat = node_string->bitsAsConst().decode_string();
-		std::string sout = process_format_str(sformat, 1, stage, width_hint, sign_hint);
-		// Finally, print the message (only include a \n for $display, not for $write)
-		log("%s", sout.c_str());
-		if (str == "$display")
-			log("\n");
-		delete_children();
-		str = std::string();
+		if (!current_always) {
+			log_file_warning(filename, location.first_line, "System task `%s' outside initial or always block is unsupported.\n", str.c_str());
+			delete_children();
+			str = std::string();
+		} else {
+			// simplify the expressions and convert them to a special cell later in genrtlil
+			for (auto node : children)
+				while (node->simplify(true, stage, -1, false)) {}
+
+			if (current_always->type == AST_INITIAL && !flag_nodisplay && stage == 2) {
+				int default_base = 10;
+				if (str.back() == 'b')
+					default_base = 2;
+				else if (str.back() == 'o')
+					default_base = 8;
+				else if (str.back() == 'h')
+					default_base = 16;
+
+				// when $display()/$write() functions are used in an initial block, print them during synthesis
+				Fmt fmt = processFormat(stage, /*sformat_like=*/false, default_base, /*first_arg_at=*/0, /*may_fail=*/true);
+				if (str.substr(0, 8) == "$display")
+					fmt.append_literal("\n");
+				log("%s", fmt.render().c_str());
+			}
+
+			return false;
+		}
 	}
 
 	// activate const folding if this is anything that must be evaluated statically (ranges, parameters, attributes, etc.)
@@ -1094,10 +1093,6 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 	if (type == AST_IDENTIFIER && current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM || current_scope[str]->type == AST_ENUM_ITEM))
 		const_fold = true;
 
-	// in certain cases a function must be evaluated constant. this is what in_param controls.
-	if (type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_DEFPARAM || type == AST_PARASET || type == AST_PREFIX)
-		in_param = true;
-
 	std::map<std::string, AstNode*> backup_scope;
 
 	// create name resolution entries for all objects with names
@@ -1117,7 +1112,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 						if (!c->is_simple_const_expr()) {
 							if (attributes.count(ID::dynports))
 								delete attributes.at(ID::dynports);
-							attributes[ID::dynports] = AstNode::mkconst_int(1, true);
+							set_attribute(ID::dynports, AstNode::mkconst_int(1, true));
 						}
 					}
 				}
@@ -1166,7 +1161,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 					for (auto &it : node->attributes) {
 						if (first_node->attributes.count(it.first) > 0)
 							delete first_node->attributes[it.first];
-						first_node->attributes[it.first] = it.second->clone();
+						first_node->set_attribute(it.first, it.second->clone());
 					}
 					children.erase(children.begin()+(i--));
 					did_something = true;
@@ -1200,12 +1195,12 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		for (size_t i = 0; i < children.size(); i++) {
 			AstNode *node = children[i];
 			if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY || node->type == AST_TYPEDEF)
-				while (node->simplify(true, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM))
+				while (node->simplify(true, 1, -1, false))
 					did_something = true;
 			if (node->type == AST_ENUM) {
 				for (auto enode : node->children){
 					log_assert(enode->type==AST_ENUM_ITEM);
-					while (node->simplify(true, false, 1, -1, false, in_param))
+					while (node->simplify(true, 1, -1, false))
 						did_something = true;
 				}
 			}
@@ -1270,7 +1265,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		for (AstNode *child : children) {
 			// simplify any parameters to constants
 			if (child->type == AST_PARASET)
-				while (child->simplify(true, false, 1, -1, false, true)) { }
+				while (child->simplify(true, 1, -1, false)) { }
 
 			// look for patterns which _may_ indicate ambiguity requiring
 			// resolution of the underlying module
@@ -1363,6 +1358,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 					asgn->children.push_back(arg);
 					asgn->children.push_back(ident);
 				}
+				asgn->fixup_hierarchy_flags();
 			}
 
 
@@ -1384,9 +1380,9 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 	case AST_ASSIGN_EQ:
 	case AST_ASSIGN_LE:
 	case AST_ASSIGN:
-		while (!children[0]->basic_prep && children[0]->simplify(false, true, stage, -1, false, in_param) == true)
+		while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false) == true)
 			did_something = true;
-		while (!children[1]->basic_prep && children[1]->simplify(false, false, stage, -1, false, in_param) == true)
+		while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false) == true)
 			did_something = true;
 		children[0]->detectSignWidth(backup_width_hint, backup_sign_hint);
 		children[1]->detectSignWidth(width_hint, sign_hint);
@@ -1422,7 +1418,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		if (!basic_prep) {
 			for (auto *node : children) {
 				// resolve any ranges
-				while (!node->basic_prep && node->simplify(true, false, stage, -1, false, false)) {
+				while (!node->basic_prep && node->simplify(true, stage, -1, false)) {
 					did_something = true;
 				}
 			}
@@ -1442,57 +1438,16 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 
 	case AST_STRUCT_ITEM:
 		if (is_custom_type) {
-			log_assert(children.size() == 1);
+			log_assert(children.size() >= 1);
 			log_assert(children[0]->type == AST_WIRETYPE);
-			auto type_name = children[0]->str;
-			if (!current_scope.count(type_name)) {
-				log_file_error(filename, location.first_line, "Unknown identifier `%s' used as type name\n", type_name.c_str());
-			}
-			AstNode *resolved_type_node = current_scope.at(type_name);
-			if (resolved_type_node->type != AST_TYPEDEF)
-				log_file_error(filename, location.first_line, "`%s' does not name a type\n", type_name.c_str());
-			log_assert(resolved_type_node->children.size() == 1);
-			AstNode *template_node = resolved_type_node->children[0];
 
-			// Ensure typedef itself is fully simplified
-			while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) {};
-
-			// Remove type reference
-			delete children[0];
-			children.pop_back();
-
-			switch (template_node->type) {
-			case AST_WIRE:
+			// Pretend it's just a wire in order to resolve the type.
+			type = AST_WIRE;
+			while (is_custom_type && simplify(const_fold, stage, width_hint, sign_hint)) {};
+			if (type == AST_WIRE)
 				type = AST_STRUCT_ITEM;
-				break;
-			case AST_STRUCT:
-			case AST_UNION:
-				type = template_node->type;
-				break;
-			default:
-				log_file_error(filename, location.first_line, "Invalid type for struct member: %s", type2str(template_node->type).c_str());
-			}
-
-			is_reg = template_node->is_reg;
-			is_logic = template_node->is_logic;
-			is_signed = template_node->is_signed;
-			is_string = template_node->is_string;
-			is_custom_type = template_node->is_custom_type;
-
-			range_valid = template_node->range_valid;
-			range_swapped = template_node->range_swapped;
-			range_left = template_node->range_left;
-			range_right = template_node->range_right;
-
-			attributes[ID::wiretype] = mkconst_str(resolved_type_node->str);
-
-			// Copy clones of children from template
-			for (auto template_child : template_node->children) {
-				children.push_back(template_child->clone());
-			}
 
 			did_something = true;
-
 		}
 		log_assert(!is_custom_type);
 		break;
@@ -1501,7 +1456,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		//log("\nENUM %s: %d child %d\n", str.c_str(), basic_prep, children[0]->basic_prep);
 		if (!basic_prep) {
 			for (auto item_node : children) {
-				while (!item_node->basic_prep && item_node->simplify(false, false, stage, -1, false, in_param))
+				while (!item_node->basic_prep && item_node->simplify(false, stage, -1, false))
 					did_something = true;
 			}
 			// allocate values (called more than once)
@@ -1516,16 +1471,16 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		if (children[0]->type == AST_IDENTIFIER && current_scope.count(children[0]->str) > 0) {
 			auto item_node = current_scope[children[0]->str];
 			if (item_node->type == AST_STRUCT || item_node->type == AST_UNION) {
-				attributes[ID::wiretype] = item_node->clone();
+				set_attribute(ID::wiretype, item_node->clone());
 				size_packed_struct(attributes[ID::wiretype], 0);
 				add_members_to_scope(attributes[ID::wiretype], str);
 			}
 		}
-		while (!children[0]->basic_prep && children[0]->simplify(false, false, stage, -1, false, true) == true)
+		while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false) == true)
 			did_something = true;
 		children[0]->detectSignWidth(width_hint, sign_hint);
 		if (children.size() > 1 && children[1]->type == AST_RANGE) {
-			while (!children[1]->basic_prep && children[1]->simplify(false, false, stage, -1, false, true) == true)
+			while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false) == true)
 				did_something = true;
 			if (!children[1]->range_valid)
 				input_error("Non-constant width range on parameter decl.\n");
@@ -1533,11 +1488,11 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		}
 		break;
 	case AST_ENUM_ITEM:
-		while (!children[0]->basic_prep && children[0]->simplify(false, false, stage, -1, false, in_param))
+		while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false))
 			did_something = true;
 		children[0]->detectSignWidth(width_hint, sign_hint);
 		if (children.size() > 1 && children[1]->type == AST_RANGE) {
-			while (!children[1]->basic_prep && children[1]->simplify(false, false, stage, -1, false, in_param))
+			while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false))
 				did_something = true;
 			if (!children[1]->range_valid)
 				input_error("Non-constant width range on enum item decl.\n");
@@ -1596,7 +1551,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		width_hint = -1;
 		sign_hint = true;
 		for (auto child : children) {
-			while (!child->basic_prep && child->simplify(false, in_lvalue, stage, -1, false, in_param) == true)
+			while (!child->basic_prep && child->simplify(false, stage, -1, false) == true)
 				did_something = true;
 			child->detectSignWidthWorker(width_hint, sign_hint);
 		}
@@ -1631,10 +1586,10 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 
 	if (detect_width_simple && width_hint < 0) {
 		if (type == AST_REPLICATE)
-			while (children[0]->simplify(true, in_lvalue, stage, -1, false, true) == true)
+			while (children[0]->simplify(true, stage, -1, false) == true)
 				did_something = true;
 		for (auto child : children)
-			while (!child->basic_prep && child->simplify(false, in_lvalue, stage, -1, false, in_param) == true)
+			while (!child->basic_prep && child->simplify(false, stage, -1, false) == true)
 				did_something = true;
 		detectSignWidth(width_hint, sign_hint);
 	}
@@ -1644,18 +1599,18 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 
 	if (type == AST_TERNARY) {
 		if (width_hint < 0) {
-			while (!children[0]->basic_prep && children[0]->simplify(true, in_lvalue, stage, -1, false, in_param))
+			while (!children[0]->basic_prep && children[0]->simplify(true, stage, -1, false))
 				did_something = true;
 
 			bool backup_unevaluated_tern_branch = unevaluated_tern_branch;
 			AstNode *chosen = get_tern_choice().first;
 
 			unevaluated_tern_branch = backup_unevaluated_tern_branch || chosen == children[2];
-			while (!children[1]->basic_prep && children[1]->simplify(false, in_lvalue, stage, -1, false, in_param))
+			while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false))
 				did_something = true;
 
 			unevaluated_tern_branch = backup_unevaluated_tern_branch || chosen == children[1];
-			while (!children[2]->basic_prep && children[2]->simplify(false, in_lvalue, stage, -1, false, in_param))
+			while (!children[2]->basic_prep && children[2]->simplify(false, stage, -1, false))
 				did_something = true;
 
 			unevaluated_tern_branch = backup_unevaluated_tern_branch;
@@ -1687,7 +1642,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 	if (const_fold && type == AST_CASE)
 	{
 		detectSignWidth(width_hint, sign_hint);
-		while (children[0]->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) { }
+		while (children[0]->simplify(const_fold, stage, width_hint, sign_hint)) { }
 		if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) {
 			children[0]->is_signed = sign_hint;
 			RTLIL::Const case_expr = children[0]->bitsAsConst(width_hint, sign_hint);
@@ -1701,7 +1656,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 						goto keep_const_cond;
 					if (v->type == AST_BLOCK)
 						continue;
-					while (v->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) { }
+					while (v->simplify(const_fold, stage, width_hint, sign_hint)) { }
 					if (v->type == AST_CONSTANT && v->bits_only_01()) {
 						RTLIL::Const case_item_expr = v->bitsAsConst(width_hint, sign_hint);
 						RTLIL::Const match = const_eq(case_expr, case_item_expr, sign_hint, sign_hint, 1);
@@ -1758,20 +1713,13 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 			unevaluated_tern_branch = chosen && chosen != children[i];
 		}
 		while (did_something_here && i < children.size()) {
-			bool const_fold_here = const_fold, in_lvalue_here = in_lvalue;
+			bool const_fold_here = const_fold;
 			int width_hint_here = width_hint;
 			bool sign_hint_here = sign_hint;
-			bool in_param_here = in_param;
 			if (i == 0 && (type == AST_REPLICATE || type == AST_WIRE))
-				const_fold_here = true, in_param_here = true;
-			if (i == 0 && (type == AST_GENIF || type == AST_GENCASE))
-				in_param_here = true;
-			if (i == 1 && (type == AST_FOR || type == AST_GENFOR))
-				in_param_here = true;
+				const_fold_here = true;
 			if (type == AST_PARAMETER || type == AST_LOCALPARAM)
 				const_fold_here = true;
-			if (i == 0 && (type == AST_ASSIGN || type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE))
-				in_lvalue_here = true;
 			if (type == AST_BLOCK) {
 				current_block = this;
 				current_block_child = children[i];
@@ -1786,7 +1734,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 				width_hint_here = -1, sign_hint_here = false;
 			if (children_are_self_determined)
 				width_hint_here = -1, sign_hint_here = false;
-			did_something_here = children[i]->simplify(const_fold_here, in_lvalue_here, stage, width_hint_here, sign_hint_here, in_param_here);
+			did_something_here = children[i]->simplify(const_fold_here, stage, width_hint_here, sign_hint_here);
 			if (did_something_here)
 				did_something = true;
 		}
@@ -1806,7 +1754,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		}
 	}
 	for (auto &attr : attributes) {
-		while (attr.second->simplify(true, false, stage, -1, false, true))
+		while (attr.second->simplify(true, stage, -1, false))
 			did_something = true;
 	}
 	if (type == AST_CASE && stage == 2) {
@@ -1884,7 +1832,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		log_assert(children.size() == 1);
 		auto type_node = children[0];
 		log_assert(type_node->type == AST_WIRE || type_node->type == AST_MEMORY || type_node->type == AST_STRUCT || type_node->type == AST_UNION);
-		while (type_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) {
+		while (type_node->simplify(const_fold, stage, width_hint, sign_hint)) {
 			did_something = true;
 		}
 		log_assert(!type_node->is_custom_type);
@@ -1905,13 +1853,15 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 			log_assert(resolved_type_node->children.size() == 1);
 			AstNode *template_node = resolved_type_node->children[0];
 
-			// Ensure typedef itself is fully simplified
-			while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) {};
+			// Resolve the typedef from the bottom up, recursing within the current
+			// block of code. Defer further simplification until the complete type is
+			// resolved.
+			while (template_node->is_custom_type && template_node->simplify(const_fold, stage, width_hint, sign_hint)) {};
 
 			if (!str.empty() && str[0] == '\\' && (template_node->type == AST_STRUCT || template_node->type == AST_UNION)) {
 				// replace instance with wire representing the packed structure
 				newNode = make_packed_struct(template_node, str, attributes);
-				newNode->attributes[ID::wiretype] = mkconst_str(resolved_type_node->str);
+				newNode->set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str));
 				// add original input/output attribute to resolved wire
 				newNode->is_input = this->is_input;
 				newNode->is_output = this->is_output;
@@ -1919,88 +1869,71 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 				goto apply_newNode;
 			}
 
-			// Remove type reference
-			delete children[0];
-			children.erase(children.begin());
-
-			if (type == AST_WIRE)
-				type = template_node->type;
-			is_reg = template_node->is_reg;
-			is_logic = template_node->is_logic;
-			is_signed = template_node->is_signed;
-			is_string = template_node->is_string;
-			is_custom_type = template_node->is_custom_type;
+			// Prepare replacement node.
+			newNode = template_node->clone();
+			newNode->str = str;
+			newNode->set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str));
+			newNode->is_input = is_input;
+			newNode->is_output = is_output;
+			newNode->is_wand = is_wand;
+			newNode->is_wor = is_wor;
+			for (auto &pair : attributes)
+				newNode->set_attribute(pair.first, pair.second->clone());
 
-			range_valid = template_node->range_valid;
-			range_swapped = template_node->range_swapped;
-			range_left = template_node->range_left;
-			range_right = template_node->range_right;
+			// if an enum then add attributes to support simulator tracing
+			newNode->annotateTypedEnums(template_node);
 
-			attributes[ID::wiretype] = mkconst_str(resolved_type_node->str);
+			bool add_packed_dimensions = (type == AST_WIRE && GetSize(children) > 1) || (type == AST_MEMORY && GetSize(children) > 2);
 
-			// if an enum then add attributes to support simulator tracing
-			annotateTypedEnums(template_node);
+			// Cannot add packed dimensions if unpacked dimensions are already specified.
+			if (add_packed_dimensions && newNode->type == AST_MEMORY)
+				input_error("Cannot extend unpacked type `%s' with packed dimensions\n", type_name.c_str());
 
-			// Insert clones children from template at beginning
-			for (int i  = 0; i < GetSize(template_node->children); i++)
-				children.insert(children.begin() + i, template_node->children[i]->clone());
+			// Add packed dimensions.
+			if (add_packed_dimensions) {
+				AstNode *packed = children[1];
+				if (newNode->children.empty())
+					newNode->children.insert(newNode->children.begin(), packed->clone());
+				else
+					prepend_ranges(newNode->children[0], packed);
+			}
 
-			if (type == AST_MEMORY && GetSize(children) == 1) {
-				// Single-bit memories must have [0:0] range
-				AstNode *rng = make_range(0, 0);
-				children.insert(children.begin(), rng);
+			// Add unpacked dimensions.
+			if (type == AST_MEMORY) {
+				AstNode *unpacked = children.back();
+				if (GetSize(newNode->children) < 2)
+					newNode->children.push_back(unpacked->clone());
+				else
+					prepend_ranges(newNode->children[1], unpacked);
+				newNode->type = type;
 			}
-			did_something = true;
+
+			// Prepare to generate dimensions metadata for the resolved type.
+			newNode->dimensions.clear();
+			newNode->unpacked_dimensions = 0;
+
+			goto apply_newNode;
 		}
-		log_assert(!is_custom_type);
 	}
 
 	// resolve types of parameters
 	if (type == AST_LOCALPARAM || type == AST_PARAMETER) {
 		if (is_custom_type) {
-			log_assert(children.size() == 2);
+			log_assert(children.size() >= 2);
 			log_assert(children[1]->type == AST_WIRETYPE);
-			auto type_name = children[1]->str;
-			if (!current_scope.count(type_name)) {
-				input_error("Unknown identifier `%s' used as type name\n", type_name.c_str());
-			}
-			AstNode *resolved_type_node = current_scope.at(type_name);
-			if (resolved_type_node->type != AST_TYPEDEF)
-				input_error("`%s' does not name a type\n", type_name.c_str());
-			log_assert(resolved_type_node->children.size() == 1);
-			AstNode *template_node = resolved_type_node->children[0];
-
-			// Ensure typedef itself is fully simplified
-			while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) {};
 
-			if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) {
-				// replace with wire representing the packed structure
-				newNode = make_packed_struct(template_node, str, attributes);
-				newNode->attributes[ID::wiretype] = mkconst_str(resolved_type_node->str);
-				newNode->type = type;
-				current_scope[str] = this;
-				// copy param value, it needs to be 1st value
-				delete children[1];
-				children.pop_back();
-				newNode->children.insert(newNode->children.begin(), children[0]->clone());
-				goto apply_newNode;
-			}
-			delete children[1];
-			children.pop_back();
+			// Pretend it's just a wire in order to resolve the type in the code block above.
+			AstNodeType param_type = type;
+			type = AST_WIRE;
+			AstNode *expr = children[0];
+			children.erase(children.begin());
+			while (is_custom_type && simplify(const_fold, stage, width_hint, sign_hint)) {};
+			type = param_type;
+			children.insert(children.begin(), expr);
 
-			if (template_node->type == AST_MEMORY)
+			if (children[1]->type == AST_MEMORY)
 				input_error("unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str());
-			is_signed = template_node->is_signed;
-			is_string = template_node->is_string;
-			is_custom_type = template_node->is_custom_type;
-
-			range_valid = template_node->range_valid;
-			range_swapped = template_node->range_swapped;
-			range_left = template_node->range_left;
-			range_right = template_node->range_right;
-			attributes[ID::wiretype] = mkconst_str(resolved_type_node->str);
-			for (auto template_child : template_node->children)
-				children.push_back(template_child->clone());
+			fixup_hierarchy_flags();
 			did_something = true;
 		}
 		log_assert(!is_custom_type);
@@ -2013,7 +1946,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 			input_error("Index in generate block prefix syntax is not constant!\n");
 		}
 		if (children[1]->type == AST_PREFIX)
-			children[1]->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param);
+			children[1]->simplify(const_fold, stage, width_hint, sign_hint);
 		log_assert(children[1]->type == AST_IDENTIFIER);
 		newNode = children[1]->clone();
 		const char *second_part = children[1]->str.c_str();
@@ -2057,9 +1990,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		if (old_range_valid != range_valid)
 			did_something = true;
 		if (range_valid && range_right > range_left) {
-			int tmp = range_right;
-			range_right = range_left;
-			range_left = tmp;
+			std::swap(range_left, range_right);
 			range_swapped = true;
 		}
 	}
@@ -2104,56 +2035,83 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		}
 	}
 
-	// resolve multiranges on memory decl
-	if (type == AST_MEMORY && children.size() > 1 && children[1]->type == AST_MULTIRANGE)
-	{
-		int total_size = 1;
-		multirange_dimensions.clear();
-		multirange_swapped.clear();
-		for (auto range : children[1]->children) {
-			if (!range->range_valid)
-				input_error("Non-constant range on memory decl.\n");
-			multirange_dimensions.push_back(min(range->range_left, range->range_right));
-			multirange_dimensions.push_back(max(range->range_left, range->range_right) - min(range->range_left, range->range_right) + 1);
-			multirange_swapped.push_back(range->range_swapped);
-			total_size *= multirange_dimensions.back();
+	// Resolve packed and unpacked ranges in declarations.
+	if ((type == AST_WIRE || type == AST_MEMORY) && dimensions.empty()) {
+		if (!children.empty()) {
+			// Unpacked ranges first, then packed ranges.
+			for (int i = std::min(GetSize(children), 2) - 1; i >= 0; i--) {
+				if (children[i]->type == AST_MULTIRANGE) {
+					int width = 1;
+					for (auto range : children[i]->children) {
+						width *= add_dimension(this, range);
+						if (i) unpacked_dimensions++;
+					}
+					delete children[i];
+					int left = width - 1, right = 0;
+					if (i)
+						std::swap(left, right);
+					children[i] = new AstNode(AST_RANGE, mkconst_int(left, true), mkconst_int(right, true));
+					fixup_hierarchy_flags();
+					did_something = true;
+				} else if (children[i]->type == AST_RANGE) {
+					add_dimension(this, children[i]);
+					if (i) unpacked_dimensions++;
+				}
+			}
+		} else {
+			// 1 bit signal: bit, logic or reg
+			dimensions.push_back({ 0, 1, false });
 		}
-		delete children[1];
-		children[1] = new AstNode(AST_RANGE, AstNode::mkconst_int(0, true), AstNode::mkconst_int(total_size-1, true));
-		did_something = true;
 	}
 
-	// resolve multiranges on memory access
-	if (type == AST_IDENTIFIER && id2ast && id2ast->type == AST_MEMORY && children.size() > 0 && children[0]->type == AST_MULTIRANGE)
+	// Resolve multidimensional array access.
+	if (type == AST_IDENTIFIER && !basic_prep && id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_MEMORY) &&
+	    children.size() > 0 && (children[0]->type == AST_RANGE || children[0]->type == AST_MULTIRANGE))
 	{
-		AstNode *index_expr = nullptr;
-
-		integer = children[0]->children.size(); // save original number of dimensions for $size() etc.
-		for (int i = 0; 2*i < GetSize(id2ast->multirange_dimensions); i++)
-		{
-			if (GetSize(children[0]->children) <= i)
-				input_error("Insufficient number of array indices for %s.\n", log_id(str));
-
-			AstNode *new_index_expr = children[0]->children[i]->children.at(0)->clone();
-
-			if (id2ast->multirange_dimensions[2*i])
-				new_index_expr = new AstNode(AST_SUB, new_index_expr, AstNode::mkconst_int(id2ast->multirange_dimensions[2*i], true));
+		int dims_sel = children[0]->type == AST_MULTIRANGE ? children[0]->children.size() : 1;
+		// Save original number of dimensions for $size() etc.
+		integer = dims_sel;
+
+		// Split access into unpacked and packed parts.
+		AstNode *unpacked_range = nullptr;
+		AstNode *packed_range = nullptr;
+
+		if (id2ast->unpacked_dimensions) {
+			if (id2ast->unpacked_dimensions > 1) {
+				// Flattened range for access to unpacked dimensions.
+				unpacked_range = make_index_range(id2ast, true);
+			} else {
+				// Index into one-dimensional unpacked part; unlink simple range node.
+				AstNode *&range = children[0]->type == AST_MULTIRANGE ? children[0]->children[0] : children[0];
+				unpacked_range = range;
+				range = nullptr;
+			}
+		}
 
-			if (i == 0)
-				index_expr = new_index_expr;
-			else
-				index_expr = new AstNode(AST_ADD, new AstNode(AST_MUL, index_expr, AstNode::mkconst_int(id2ast->multirange_dimensions[2*i+1], true)), new_index_expr);
+		if (dims_sel > id2ast->unpacked_dimensions) {
+			if (GetSize(id2ast->dimensions) - id2ast->unpacked_dimensions > 1) {
+				// Flattened range for access to packed dimensions.
+				packed_range = make_index_range(id2ast, false);
+			} else {
+				// Index into one-dimensional packed part; unlink simple range node.
+				AstNode *&range = children[0]->type == AST_MULTIRANGE ? children[0]->children[dims_sel - 1] : children[0];
+				packed_range = range;
+				range = nullptr;
+			}
 		}
 
-		for (int i = GetSize(id2ast->multirange_dimensions)/2; i < GetSize(children[0]->children); i++)
-			children.push_back(children[0]->children[i]->clone());
+		for (auto &it : children)
+			delete it;
+		children.clear();
 
-		delete children[0];
-		if (index_expr == nullptr)
-			children.erase(children.begin());
-		else
-			children[0] = new AstNode(AST_RANGE, index_expr);
+		if (unpacked_range)
+			children.push_back(unpacked_range);
 
+		if (packed_range)
+			children.push_back(packed_range);
+
+		fixup_hierarchy_flags();
+		basic_prep = true;
 		did_something = true;
 	}
 
@@ -2169,6 +2127,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 						children[0]->realvalue, log_signal(constvalue));
 				delete children[0];
 				children[0] = mkconst_bits(constvalue.bits, sign_hint);
+				fixup_hierarchy_flags();
 				did_something = true;
 			}
 			if (children[0]->type == AST_CONSTANT) {
@@ -2178,6 +2137,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 					AstNode *old_child_0 = children[0];
 					children[0] = mkconst_bits(sig.as_const().bits, is_signed);
 					delete old_child_0;
+					fixup_hierarchy_flags();
 				}
 				children[0]->is_signed = is_signed;
 			}
@@ -2191,24 +2151,38 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 			delete children[0];
 			children[0] = new AstNode(AST_REALVALUE);
 			children[0]->realvalue = as_realvalue;
+			fixup_hierarchy_flags();
 			did_something = true;
 		}
 	}
 
 	if (type == AST_IDENTIFIER && !basic_prep) {
 		// check if a plausible struct member sss.mmmm
-		std::string sname;
-		if (name_has_dot(str, sname)) {
-			if (current_scope.count(str) > 0) {
-				auto item_node = current_scope[str];
-				if (item_node->type == AST_STRUCT_ITEM || item_node->type == AST_STRUCT || item_node->type == AST_UNION) {
+		if (!str.empty() && str[0] == '\\' && current_scope.count(str)) {
+			auto item_node = current_scope[str];
+			if (item_node->type == AST_STRUCT_ITEM || item_node->type == AST_STRUCT || item_node->type == AST_UNION) {
+				// Traverse any hierarchical path until the full name for the referenced struct/union is found.
+				std::string sname;
+				bool found_sname = false;
+				for (std::string::size_type pos = 0; (pos = str.find('.', pos)) != std::string::npos; pos++) {
+					sname = str.substr(0, pos);
+					if (current_scope.count(sname)) {
+						auto stype = current_scope[sname]->type;
+						if (stype == AST_WIRE || stype == AST_PARAMETER || stype == AST_LOCALPARAM) {
+							found_sname = true;
+							break;
+						}
+					}
+				}
+
+				if (found_sname) {
 					// structure member, rewrite this node to reference the packed struct wire
-					auto range = make_struct_member_range(this, item_node);
+					auto range = make_index_range(item_node);
 					newNode = new AstNode(AST_IDENTIFIER, range);
 					newNode->str = sname;
 					// save type and original number of dimensions for $size() etc.
-					newNode->attributes[ID::wiretype] = item_node->clone();
-					if (!item_node->multirange_dimensions.empty() && children.size() > 0) {
+					newNode->set_attribute(ID::wiretype, item_node->clone());
+					if (!item_node->dimensions.empty() && children.size() > 0) {
 						if (children[0]->type == AST_RANGE)
 							newNode->integer = 1;
 						else if (children[0]->type == AST_MULTIRANGE)
@@ -2301,9 +2275,9 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true)));
 		wire->str = wire_id;
 		if (current_block)
-			wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
+			wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
 		current_ast_mod->children.push_back(wire);
-		while (wire->simplify(true, false, 1, -1, false, false)) { }
+		while (wire->simplify(true, 1, -1, false)) { }
 
 		AstNode *data = clone();
 		delete data->children[1];
@@ -2345,7 +2319,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		AstNode *body = children[1];
 
 		// eval count expression
-		while (count->simplify(true, false, stage, 32, true, false)) { }
+		while (count->simplify(true, stage, 32, true)) { }
 
 		if (count->type != AST_CONSTANT)
 			input_error("Repeat loops outside must have constant repeat counts!\n");
@@ -2401,7 +2375,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 			int expr_width_hint = -1;
 			bool expr_sign_hint = true;
 			varbuf->detectSignWidth(expr_width_hint, expr_sign_hint);
-			while (varbuf->simplify(true, false, stage, 32, true, false)) { }
+			while (varbuf->simplify(true, stage, 32, true)) { }
 		}
 
 		if (varbuf->type != AST_CONSTANT)
@@ -2442,7 +2416,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 				int expr_width_hint = -1;
 				bool expr_sign_hint = true;
 				buf->detectSignWidth(expr_width_hint, expr_sign_hint);
-				while (buf->simplify(true, false, stage, expr_width_hint, expr_sign_hint, false)) { }
+				while (buf->simplify(true, stage, expr_width_hint, expr_sign_hint)) { }
 			}
 
 			if (buf->type != AST_CONSTANT)
@@ -2477,7 +2451,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 
 			if (type == AST_GENFOR) {
 				for (size_t i = 0; i < buf->children.size(); i++) {
-					buf->children[i]->simplify(const_fold, false, stage, -1, false, false);
+					buf->children[i]->simplify(const_fold, stage, -1, false);
 					current_ast_mod->children.push_back(buf->children[i]);
 				}
 			} else {
@@ -2489,11 +2463,12 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 
 			// eval 3rd expression
 			buf = next_ast->children[1]->clone();
+			buf->set_in_param_flag(true);
 			{
 				int expr_width_hint = -1;
 				bool expr_sign_hint = true;
 				buf->detectSignWidth(expr_width_hint, expr_sign_hint);
-				while (buf->simplify(true, false, stage, expr_width_hint, expr_sign_hint, true)) { }
+				while (buf->simplify(true, stage, expr_width_hint, expr_sign_hint)) { }
 			}
 
 			if (buf->type != AST_CONSTANT)
@@ -2545,7 +2520,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		std::vector<AstNode*> new_children;
 		for (size_t i = 0; i < children.size(); i++)
 			if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF) {
-				children[i]->simplify(false, false, stage, -1, false, false);
+				children[i]->simplify(false, stage, -1, false);
 				current_ast_mod->children.push_back(children[i]);
 				current_scope[children[i]->str] = children[i];
 			} else
@@ -2564,7 +2539,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		}
 
 		for (size_t i = 0; i < children.size(); i++) {
-			children[i]->simplify(const_fold, false, stage, -1, false, false);
+			children[i]->simplify(const_fold, stage, -1, false);
 			current_ast_mod->children.push_back(children[i]);
 		}
 
@@ -2576,7 +2551,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 	if (type == AST_GENIF && children.size() != 0)
 	{
 		AstNode *buf = children[0]->clone();
-		while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { }
+		while (buf->simplify(true, stage, width_hint, sign_hint)) { }
 		if (buf->type != AST_CONSTANT) {
 			// for (auto f : log_files)
 			// 	dumpAst(f, "verilog-ast> ");
@@ -2600,7 +2575,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 			}
 
 			for (size_t i = 0; i < buf->children.size(); i++) {
-				buf->children[i]->simplify(const_fold, false, stage, -1, false, false);
+				buf->children[i]->simplify(const_fold, stage, -1, false);
 				current_ast_mod->children.push_back(buf->children[i]);
 			}
 
@@ -2616,7 +2591,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 	if (type == AST_GENCASE && children.size() != 0)
 	{
 		AstNode *buf = children[0]->clone();
-		while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { }
+		while (buf->simplify(true, stage, width_hint, sign_hint)) { }
 		if (buf->type != AST_CONSTANT) {
 			// for (auto f : log_files)
 			// 	dumpAst(f, "verilog-ast> ");
@@ -2650,7 +2625,8 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 					continue;
 
 				buf = child->clone();
-				while (buf->simplify(true, false, stage, width_hint, sign_hint, true)) { }
+				buf->set_in_param_flag(true);
+				while (buf->simplify(true, stage, width_hint, sign_hint)) { }
 				if (buf->type != AST_CONSTANT) {
 					// for (auto f : log_files)
 					// 	dumpAst(f, "verilog-ast> ");
@@ -2678,7 +2654,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 			}
 
 			for (size_t i = 0; i < buf->children.size(); i++) {
-				buf->children[i]->simplify(const_fold, false, stage, -1, false, false);
+				buf->children[i]->simplify(const_fold, stage, -1, false);
 				current_ast_mod->children.push_back(buf->children[i]);
 			}
 
@@ -2756,6 +2732,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 			children.push_back(children_list.at(0));
 			children.back()->was_checked = true;
 			children.push_back(node);
+			fixup_hierarchy_flags();
 			did_something = true;
 		}
 		else if (str == "buf" || str == "not")
@@ -2806,6 +2783,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 			children.push_back(children_list[0]);
 			children.back()->was_checked = true;
 			children.push_back(node);
+			fixup_hierarchy_flags();
 			did_something = true;
 		}
 	}
@@ -2824,27 +2802,12 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		if (!children[0]->id2ast->range_valid)
 			goto skip_dynamic_range_lvalue_expansion;
 
-		int source_width = children[0]->id2ast->range_left - children[0]->id2ast->range_right + 1;
-		int source_offset = children[0]->id2ast->range_right;
+		AST::AstNode *member_node = children[0]->get_struct_member();
+		int wire_width = member_node ?
+			member_node->range_left - member_node->range_right + 1 :
+			children[0]->id2ast->range_left - children[0]->id2ast->range_right + 1;
+		int wire_offset = children[0]->id2ast->range_right;
 		int result_width = 1;
-		int stride = 1;
-		AST::AstNode *member_node = get_struct_member(children[0]);
-		if (member_node) {
-			// Clamp chunk to range of member within struct/union.
-			log_assert(!source_offset && !children[0]->id2ast->range_swapped);
-			source_width = member_node->range_left - member_node->range_right + 1;
-
-			// When the (* nowrshmsk *) attribute is set, a CASE block is generated below
-			// to select the indexed bit slice. When a multirange array is indexed, the
-			// start of each possible slice is separated by the bit stride of the last
-			// index dimension, and we can optimize the CASE block accordingly.
-			// The dimension of the original array expression is saved in the 'integer' field.
-			int dims = children[0]->integer;
-			stride = source_width;
-			for (int dim = 0; dim < dims; dim++) {
-				stride /= get_struct_range_width(member_node, dim);
-			}
-		}
 
 		AstNode *shift_expr = NULL;
 		AstNode *range = children[0]->children[0];
@@ -2857,230 +2820,197 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin
 		else
 			shift_expr = range->children[0]->clone();
 
-		bool use_case_method = false;
-
-		if (children[0]->id2ast->attributes.count(ID::nowrshmsk)) {
-			AstNode *node = children[0]->id2ast->attributes.at(ID::nowrshmsk);
-			while (node->simplify(true, false, stage, -1, false, false)) { }
-			if (node->type != AST_CONSTANT)
-				input_error("Non-constant value for `nowrshmsk' attribute on `%s'!\n", children[0]->id2ast->str.c_str());
-			if (node->asAttrConst().as_bool())
-				use_case_method = true;
-		}
+		bool use_case_method = children[0]->id2ast->get_bool_attribute(ID::nowrshmsk);
 
 		if (!use_case_method && current_always->detect_latch(children[0]->str))
 			use_case_method = true;
 
-		if (use_case_method)
-		{
+		if (use_case_method) {
 			// big case block
 
+			int stride = 1;
+			long long bitno_div = stride;
+
+			int case_width_hint;
+			bool case_sign_hint;
+			shift_expr->detectSignWidth(case_width_hint, case_sign_hint);
+			int max_width = case_width_hint;
+
+			if (member_node) {  // Member in packed struct/union
+				// Clamp chunk to range of member within struct/union.
+				log_assert(!wire_offset && !children[0]->id2ast->range_swapped);
+
+				// When the (* nowrshmsk *) attribute is set, a CASE block is generated below
+				// to select the indexed bit slice. When a multirange array is indexed, the
+				// start of each possible slice is separated by the bit stride of the last
+				// index dimension, and we can optimize the CASE block accordingly.
+				// The dimension of the original array expression is saved in the 'integer' field.
+				int dims = children[0]->integer;
+				stride = wire_width;
+				for (int dim = 0; dim < dims; dim++) {
+					stride /= member_node->dimensions[dim].range_width;
+				}
+				bitno_div = stride;
+			} else {
+				// Extract (index)*(width) from non_opt_range pattern ((@selfsz@((index)*(width)))+(0)).
+				AstNode *lsb_expr =
+					shift_expr->type == AST_ADD && shift_expr->children[0]->type == AST_SELFSZ &&
+					shift_expr->children[1]->type == AST_CONSTANT && shift_expr->children[1]->integer == 0 ?
+					shift_expr->children[0]->children[0] :
+					shift_expr;
+
+				// Extract stride from indexing of two-dimensional packed arrays and
+				// variable slices on the form dst[i*stride +: width] = src.
+				if (lsb_expr->type == AST_MUL &&
+				    (lsb_expr->children[0]->type == AST_CONSTANT ||
+				     lsb_expr->children[1]->type == AST_CONSTANT))
+				{
+					int stride_ix = lsb_expr->children[1]->type == AST_CONSTANT;
+					stride = (int)lsb_expr->children[stride_ix]->integer;
+					bitno_div = stride != 0 ? stride : 1;
+
+					// Check whether i*stride can overflow.
+					int i_width;
+					bool i_sign;
+					lsb_expr->children[1 - stride_ix]->detectSignWidth(i_width, i_sign);
+					int stride_width;
+					bool stride_sign;
+					lsb_expr->children[stride_ix]->detectSignWidth(stride_width, stride_sign);
+					max_width = std::max(i_width, stride_width);
+					// Stride width calculated from actual stride value.
+					stride_width = std::ceil(std::log2(std::abs(stride)));
+
+					if (i_width + stride_width > max_width) {
+						// For (truncated) i*stride to be within the range of dst, the following must hold:
+						//   i*stride ≡ bitno (mod shift_mod), i.e.
+						//   i*stride = k*shift_mod + bitno
+						//
+						// The Diophantine equation on the form ax + by = c:
+						//   stride*i - shift_mod*k = bitno
+						// has solutions iff c is a multiple of d = gcd(a, b), i.e.
+						//   bitno mod gcd(stride, shift_mod) = 0
+						//
+						// long long is at least 64 bits in C++11
+						long long shift_mod = 1ll << (max_width - case_sign_hint);
+						// std::gcd requires C++17
+						// bitno_div = std::gcd(stride, shift_mod);
+						bitno_div = gcd((long long)stride, shift_mod);
+					}
+				}
+			}
+
+			// long long is at least 64 bits in C++11
+			long long max_offset = (1ll << (max_width - case_sign_hint)) - 1;
+			long long min_offset = case_sign_hint ? -(1ll << (max_width - 1)) : 0;
+
+			// A temporary register holds the result of the (possibly complex) rvalue expression,
+			// avoiding repetition in each AST_COND below.
+			int rvalue_width;
+			bool rvalue_sign;
+			children[1]->detectSignWidth(rvalue_width, rvalue_sign);
+			AstNode *rvalue = mktemp_logic("$bitselwrite$rvalue$", current_ast_mod, true, rvalue_width - 1, 0, rvalue_sign);
+			AstNode *caseNode = new AstNode(AST_CASE, shift_expr);
+			newNode = new AstNode(AST_BLOCK,
+					      new AstNode(AST_ASSIGN_EQ, rvalue, children[1]->clone()),
+					      caseNode);
+
 			did_something = true;
-			newNode = new AstNode(AST_CASE, shift_expr);
-			for (int i = 0; i < source_width; i += stride) {
-				int start_bit = source_offset + i;
-				int end_bit = std::min(start_bit+result_width,source_width) - 1;
-				AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit, true));
+			for (int i = 1 - result_width; i < wire_width; i++) {
+				// Out of range indexes are handled in genrtlil.cc
+				int start_bit = wire_offset + i;
+				int end_bit = start_bit + result_width - 1;
+				// Check whether the current index can be generated by shift_expr.
+				if (start_bit < min_offset || start_bit > max_offset)
+					continue;
+				if (start_bit%bitno_div != 0 || (stride == 0 && start_bit != 0))
+					continue;
+
+				AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit, case_sign_hint, max_width));
 				AstNode *lvalue = children[0]->clone();
 				lvalue->delete_children();
 				if (member_node)
-					lvalue->attributes[ID::wiretype] = member_node->clone();
+					lvalue->set_attribute(ID::wiretype, member_node->clone());
 				lvalue->children.push_back(new AstNode(AST_RANGE,
 						mkconst_int(end_bit, true), mkconst_int(start_bit, true)));
-				cond->children.push_back(new AstNode(AST_BLOCK, new AstNode(type, lvalue, children[1]->clone())));
-				newNode->children.push_back(cond);
+				cond->children.push_back(new AstNode(AST_BLOCK, new AstNode(type, lvalue, rvalue->clone())));
+				caseNode->children.push_back(cond);
 			}
-		}
-		else
-		{
-			// mask and shift operations, disabled for now
-
-			AstNode *wire_mask = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
-			wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
-			wire_mask->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
-			wire_mask->is_logic = true;
-			while (wire_mask->simplify(true, false, 1, -1, false, false)) { }
-			current_ast_mod->children.push_back(wire_mask);
-
-			AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
-			wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
-			wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
-			wire_data->is_logic = true;
-			while (wire_data->simplify(true, false, 1, -1, false, false)) { }
-			current_ast_mod->children.push_back(wire_data);
-
-			int shamt_width_hint = -1;
-			bool shamt_sign_hint = true;
-			shift_expr->detectSignWidth(shamt_width_hint, shamt_sign_hint);
-
-			AstNode *wire_sel = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(shamt_width_hint-1, true), mkconst_int(0, true)));
-			wire_sel->str = stringf("$bitselwrite$sel$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
-			wire_sel->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
-			wire_sel->is_logic = true;
-			wire_sel->is_signed = shamt_sign_hint;
-			while (wire_sel->simplify(true, false, 1, -1, false, false)) { }
-			current_ast_mod->children.push_back(wire_sel);
-
-			did_something = true;
-			newNode = new AstNode(AST_BLOCK);
+		} else {
+			// mask and shift operations
+			// dst = (dst & ~(width'1 << lsb)) | unsigned'(width'(src)) << lsb)
 
 			AstNode *lvalue = children[0]->clone();
 			lvalue->delete_children();
 			if (member_node)
-				lvalue->attributes[ID::wiretype] = member_node->clone();
-
-			AstNode *ref_mask = new AstNode(AST_IDENTIFIER);
-			ref_mask->str = wire_mask->str;
-			ref_mask->id2ast = wire_mask;
-			ref_mask->was_checked = true;
-
-			AstNode *ref_data = new AstNode(AST_IDENTIFIER);
-			ref_data->str = wire_data->str;
-			ref_data->id2ast = wire_data;
-			ref_data->was_checked = true;
-
-			AstNode *ref_sel = new AstNode(AST_IDENTIFIER);
-			ref_sel->str = wire_sel->str;
-			ref_sel->id2ast = wire_sel;
-			ref_sel->was_checked = true;
+				lvalue->set_attribute(ID::wiretype, member_node->clone());
 
 			AstNode *old_data = lvalue->clone();
 			if (type == AST_ASSIGN_LE)
 				old_data->lookahead = true;
 
-			AstNode *s = new AstNode(AST_ASSIGN_EQ, ref_sel->clone(), shift_expr);
-			newNode->children.push_back(s);
+			int shift_width_hint;
+			bool shift_sign_hint;
+			shift_expr->detectSignWidth(shift_width_hint, shift_sign_hint);
 
-			AstNode *shamt = ref_sel;
+			// All operations are carried out in a new block.
+			newNode = new AstNode(AST_BLOCK);
+
+			// Temporary register holding the result of the bit- or part-select position expression.
+			AstNode *pos = mktemp_logic("$bitselwrite$pos$", current_ast_mod, true, shift_width_hint - 1, 0, shift_sign_hint);
+			newNode->children.push_back(new AstNode(AST_ASSIGN_EQ, pos, shift_expr));
 
-			// convert to signed while preserving the sign and value
-			shamt = new AstNode(AST_CAST_SIZE, mkconst_int(shamt_width_hint + 1, true), shamt);
-			shamt = new AstNode(AST_TO_SIGNED, shamt);
+			// Calculate lsb from position.
+			AstNode *shift_val = pos->clone();
+
+			// If the expression is signed, we must add an extra bit for possible negation of the most negative number.
+			// If the expression is unsigned, we must add an extra bit for sign.
+			shift_val = new AstNode(AST_CAST_SIZE, mkconst_int(shift_width_hint + 1, true), shift_val);
+			if (!shift_sign_hint)
+				shift_val = new AstNode(AST_TO_SIGNED, shift_val);
 
 			// offset the shift amount by the lower bound of the dimension
-			int start_bit = source_offset;
-			shamt = new AstNode(AST_SUB, shamt, mkconst_int(start_bit, true));
+			if (wire_offset != 0)
+				shift_val = new AstNode(AST_SUB, shift_val, mkconst_int(wire_offset, true));
 
 			// reflect the shift amount if the dimension is swapped
 			if (children[0]->id2ast->range_swapped)
-				shamt = new AstNode(AST_SUB, mkconst_int(source_width - result_width, true), shamt);
+				shift_val = new AstNode(AST_SUB, mkconst_int(wire_width - result_width, true), shift_val);
 
 			// AST_SHIFT uses negative amounts for shifting left
-			shamt = new AstNode(AST_NEG, shamt);
-
-			AstNode *t;
+			shift_val = new AstNode(AST_NEG, shift_val);
 
-			t = mkconst_bits(std::vector<RTLIL::State>(result_width, State::S1), false);
-			t = new AstNode(AST_SHIFT, t, shamt->clone());
-			t = new AstNode(AST_ASSIGN_EQ, ref_mask->clone(), t);
-			newNode->children.push_back(t);
-
-			t = new AstNode(AST_BIT_AND, mkconst_bits(std::vector<RTLIL::State>(result_width, State::S1), false), children[1]->clone());
-			t = new AstNode(AST_SHIFT, t, shamt);
-			t = new AstNode(AST_ASSIGN_EQ, ref_data->clone(), t);
-			newNode->children.push_back(t);
-
-			t = new AstNode(AST_BIT_AND, old_data, new AstNode(AST_BIT_NOT, ref_mask));
-			t = new AstNode(AST_BIT_OR, t, ref_data);
-			t = new AstNode(type, lvalue, t);
-			newNode->children.push_back(t);
+			// dst = (dst & ~(width'1 << lsb)) | unsigned'(width'(src)) << lsb)
+			did_something = true;
+			AstNode *bitmask = mkconst_bits(std::vector<RTLIL::State>(result_width, State::S1), false);
+			newNode->children.push_back(
+				new AstNode(type,
+					    lvalue,
+					    new AstNode(AST_BIT_OR,
+							new AstNode(AST_BIT_AND,
+								    old_data,
+								    new AstNode(AST_BIT_NOT,
+										new AstNode(AST_SHIFT,
+											    bitmask,
+											    shift_val->clone()))),
+							new AstNode(AST_SHIFT,
+								    new AstNode(AST_TO_UNSIGNED,
+										new AstNode(AST_CAST_SIZE,
+											    mkconst_int(result_width, true),
+											    children[1]->clone())),
+								    shift_val))));
+
+			newNode->fixup_hierarchy_flags(true);
 		}
 
 		goto apply_newNode;
 	}
 skip_dynamic_range_lvalue_expansion:;
 
-	if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && current_block != NULL)
-	{
-		std::stringstream sstr;
-		sstr << "$formal$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
-		std::string id_check = sstr.str() + "_CHECK", id_en = sstr.str() + "_EN";
-
-		AstNode *wire_check = new AstNode(AST_WIRE);
-		wire_check->str = id_check;
-		wire_check->was_checked = true;
-		current_ast_mod->children.push_back(wire_check);
-		current_scope[wire_check->str] = wire_check;
-		while (wire_check->simplify(true, false, 1, -1, false, false)) { }
-
-		AstNode *wire_en = new AstNode(AST_WIRE);
-		wire_en->str = id_en;
-		wire_en->was_checked = true;
-		current_ast_mod->children.push_back(wire_en);
-		if (current_always_clocked) {
-			current_ast_mod->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)))));
-			current_ast_mod->children.back()->children[0]->children[0]->children[0]->str = id_en;
-			current_ast_mod->children.back()->children[0]->children[0]->children[0]->was_checked = true;
-		}
-		current_scope[wire_en->str] = wire_en;
-		while (wire_en->simplify(true, false, 1, -1, false, false)) { }
-
-		AstNode *check_defval;
-		if (type == AST_LIVE || type == AST_FAIR) {
-			check_defval = new AstNode(AST_REDUCE_BOOL, children[0]->clone());
-		} else {
-			std::vector<RTLIL::State> x_bit;
-			x_bit.push_back(RTLIL::State::Sx);
-			check_defval = mkconst_bits(x_bit, false);
-		}
-
-		AstNode *assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), check_defval);
-		assign_check->children[0]->str = id_check;
-		assign_check->children[0]->was_checked = true;
-
-		AstNode *assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, 1));
-		assign_en->children[0]->str = id_en;
-		assign_en->children[0]->was_checked = true;
-
-		AstNode *default_signals = new AstNode(AST_BLOCK);
-		default_signals->children.push_back(assign_check);
-		default_signals->children.push_back(assign_en);
-		current_top_block->children.insert(current_top_block->children.begin(), default_signals);
-
-		if (type == AST_LIVE || type == AST_FAIR) {
-			assign_check = nullptr;
-		} else {
-			assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_REDUCE_BOOL, children[0]->clone()));
-			assign_check->children[0]->str = id_check;
-			assign_check->children[0]->was_checked = true;
-		}
-
-		if (current_always == nullptr || current_always->type != AST_INITIAL) {
-			assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(1, false, 1));
-		} else {
-			assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_FCALL));
-			assign_en->children[1]->str = "\\$initstate";
-		}
-		assign_en->children[0]->str = id_en;
-		assign_en->children[0]->was_checked = true;
-
-		newNode = new AstNode(AST_BLOCK);
-		if (assign_check != nullptr)
-			newNode->children.push_back(assign_check);
-		newNode->children.push_back(assign_en);
-
-		AstNode *assertnode = new AstNode(type);
-		assertnode->location = location;
-		assertnode->str = str;
-		assertnode->children.push_back(new AstNode(AST_IDENTIFIER));
-		assertnode->children.push_back(new AstNode(AST_IDENTIFIER));
-		assertnode->children[0]->str = id_check;
-		assertnode->children[1]->str = id_en;
-		assertnode->attributes.swap(attributes);
-		current_ast_mod->children.push_back(assertnode);
-
-		goto apply_newNode;
-	}
-
-	if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && children.size() == 1)
-	{
-		children.push_back(mkconst_int(1, false, 1));
-		did_something = true;
-	}
-
 	// found right-hand side identifier for memory -> replace with memory read port
 	if (stage > 1 && type == AST_IDENTIFIER && id2ast != NULL && id2ast->type == AST_MEMORY && !in_lvalue &&
 			children.size() == 1 && children[0]->type == AST_RANGE && children[0]->children.size() == 1) {
+		if (integer < (unsigned)id2ast->unpacked_dimensions)
+			input_error("Insufficient number of array indices for %s.\n", log_id(str));
 		newNode = new AstNode(AST_MEMRD, children[0]->children[0]->clone());
 		newNode->str = str;
 		newNode->id2ast = id2ast;
@@ -3105,8 +3035,8 @@ skip_dynamic_range_lvalue_expansion:;
 			wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
 			current_ast_mod->children.push_back(wire_tmp);
 			current_scope[wire_tmp->str] = wire_tmp;
-			wire_tmp->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
-			while (wire_tmp->simplify(true, false, 1, -1, false, false)) { }
+			wire_tmp->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
+			while (wire_tmp->simplify(true, 1, -1, false)) { }
 			wire_tmp->is_logic = true;
 
 			AstNode *wire_tmp_id = new AstNode(AST_IDENTIFIER);
@@ -3139,6 +3069,9 @@ skip_dynamic_range_lvalue_expansion:;
 			children[0]->id2ast->children[0]->range_valid && children[0]->id2ast->children[1]->range_valid &&
 			(children[0]->children.size() == 1 || children[0]->children.size() == 2) && children[0]->children[0]->type == AST_RANGE)
 	{
+		if (children[0]->integer < (unsigned)children[0]->id2ast->unpacked_dimensions)
+			input_error("Insufficient number of array indices for %s.\n", log_id(str));
+
 		std::stringstream sstr;
 		sstr << "$memwr$" << children[0]->str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
 		std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN";
@@ -3176,7 +3109,7 @@ skip_dynamic_range_lvalue_expansion:;
 			wire_addr->was_checked = true;
 			current_ast_mod->children.push_back(wire_addr);
 			current_scope[wire_addr->str] = wire_addr;
-			while (wire_addr->simplify(true, false, 1, -1, false, false)) { }
+			while (wire_addr->simplify(true, 1, -1, false)) { }
 
 			AstNode *assign_addr = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false));
 			assign_addr->children[0]->str = id_addr;
@@ -3202,7 +3135,7 @@ skip_dynamic_range_lvalue_expansion:;
 			wire_data->is_signed = mem_signed;
 			current_ast_mod->children.push_back(wire_data);
 			current_scope[wire_data->str] = wire_data;
-			while (wire_data->simplify(true, false, 1, -1, false, false)) { }
+			while (wire_data->simplify(true, 1, -1, false)) { }
 
 			AstNode *assign_data = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false));
 			assign_data->children[0]->str = id_data;
@@ -3218,7 +3151,7 @@ skip_dynamic_range_lvalue_expansion:;
 		wire_en->was_checked = true;
 		current_ast_mod->children.push_back(wire_en);
 		current_scope[wire_en->str] = wire_en;
-		while (wire_en->simplify(true, false, 1, -1, false, false)) { }
+		while (wire_en->simplify(true, 1, -1, false)) { }
 
 		AstNode *assign_en_first = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width));
 		assign_en_first->children[0]->str = id_en;
@@ -3346,7 +3279,7 @@ skip_dynamic_range_lvalue_expansion:;
 				AstNode *wire = new AstNode(AST_WIRE);
 				wire->str = stringf("$initstate$%d_wire", myidx);
 				current_ast_mod->children.push_back(wire);
-				while (wire->simplify(true, false, 1, -1, false, false)) { }
+				while (wire->simplify(true, 1, -1, false)) { }
 
 				AstNode *cell = new AstNode(AST_CELL, new AstNode(AST_CELLTYPE), new AstNode(AST_ARGUMENT, new AstNode(AST_IDENTIFIER)));
 				cell->str = stringf("$initstate$%d", myidx);
@@ -3355,7 +3288,7 @@ skip_dynamic_range_lvalue_expansion:;
 				cell->children[1]->children[0]->str = wire->str;
 				cell->children[1]->children[0]->id2ast = wire;
 				current_ast_mod->children.push_back(cell);
-				while (cell->simplify(true, false, 1, -1, false, false)) { }
+				while (cell->simplify(true, 1, -1, false)) { }
 
 				newNode = new AstNode(AST_IDENTIFIER);
 				newNode->str = wire->str;
@@ -3381,7 +3314,7 @@ skip_dynamic_range_lvalue_expansion:;
 				if (GetSize(children) == 2)
 				{
 					AstNode *buf = children[1]->clone();
-					while (buf->simplify(true, false, stage, -1, false, false)) { }
+					while (buf->simplify(true, stage, -1, false)) { }
 					if (buf->type != AST_CONSTANT)
 						input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
 
@@ -3416,7 +3349,7 @@ skip_dynamic_range_lvalue_expansion:;
 
 					current_ast_mod->children.push_back(reg);
 
-					while (reg->simplify(true, false, 1, -1, false, false)) { }
+					while (reg->simplify(true, 1, -1, false)) { }
 
 					AstNode *regid = new AstNode(AST_IDENTIFIER);
 					regid->str = reg->str;
@@ -3492,7 +3425,7 @@ skip_dynamic_range_lvalue_expansion:;
 							RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				AstNode *buf = children[0]->clone();
-				while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { }
+				while (buf->simplify(true, stage, width_hint, sign_hint)) { }
 				if (buf->type != AST_CONSTANT)
 					input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
 
@@ -3510,10 +3443,11 @@ skip_dynamic_range_lvalue_expansion:;
 				goto apply_newNode;
 			}
 
-			if (str == "\\$size" || str == "\\$bits" || str == "\\$high" || str == "\\$low" || str == "\\$left" || str == "\\$right")
+			if (str == "\\$dimensions" || str == "\\$unpacked_dimensions" ||
+			    str == "\\$increment" || str == "\\$size" || str == "\\$bits" || str == "\\$high" || str == "\\$low" || str == "\\$left" || str == "\\$right")
 			{
 				int dim = 1;
-				if (str == "\\$bits") {
+				if (str == "\\$dimensions" || str == "\\$unpacked_dimensions" || str == "\\$bits") {
 					if (children.size() != 1)
 						input_error("System function %s got %d arguments, expected 1.\n",
 								RTLIL::unescape_id(str).c_str(), int(children.size()));
@@ -3524,7 +3458,7 @@ skip_dynamic_range_lvalue_expansion:;
 					if (children.size() == 2) {
 						AstNode *buf = children[1]->clone();
 						// Evaluate constant expression
-						while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { }
+						while (buf->simplify(true, stage, width_hint, sign_hint)) { }
 						dim = buf->asInt(false);
 						delete buf;
 					}
@@ -3532,10 +3466,9 @@ skip_dynamic_range_lvalue_expansion:;
 				AstNode *buf = children[0]->clone();
 				int mem_depth = 1;
 				int result, high = 0, low = 0, left = 0, right = 0, width = 1; // defaults for a simple wire
+				int expr_dimensions = 0, expr_unpacked_dimensions = 0;
 				AstNode *id_ast = NULL;
 
-				// Is this needed?
-				//while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { }
 				buf->detectSignWidth(width_hint, sign_hint);
 
 				if (buf->type == AST_IDENTIFIER) {
@@ -3545,107 +3478,46 @@ skip_dynamic_range_lvalue_expansion:;
 					if (!id_ast)
 						input_error("Failed to resolve identifier %s for width detection!\n", buf->str.c_str());
 
-					// Check for item in packed struct / union
-					AST::AstNode *item_node = get_struct_member(buf);
-					if (id_ast->type == AST_WIRE && item_node) {
+					if (id_ast->type == AST_WIRE || id_ast->type == AST_MEMORY) {
+						// Check for item in packed struct / union
+						AstNode *item_node = buf->get_struct_member();
+						if (item_node)
+							id_ast = item_node;
+
 						// The dimension of the original array expression is saved in the 'integer' field
 						dim += buf->integer;
-						if (item_node->multirange_dimensions.empty()) {
-							if (dim != 1)
-								input_error("Dimension %d out of range in `%s', as it only has one dimension!\n", dim, item_node->str.c_str());
-							left  = high = item_node->range_left;
-							right = low  = item_node->range_right;
-						} else {
-							int dims = GetSize(item_node->multirange_dimensions)/2;
-							if (dim < 1 || dim > dims)
-								input_error("Dimension %d out of range in `%s', as it only has dimensions 1..%d!\n", dim, item_node->str.c_str(), dims);
-							right = low  = get_struct_range_offset(item_node, dim - 1);
-							left  = high = low + get_struct_range_width(item_node, dim - 1) - 1;
-							if (item_node->multirange_swapped[dim - 1]) {
-								std::swap(left, right);
-							}
-							for (int i = dim; i < dims; i++) {
-							    mem_depth *= get_struct_range_width(item_node, i);
-							}
-						}
-					}
-					// Otherwise, we have 4 cases:
-					// wire x;                ==> AST_WIRE, no AST_RANGE children
-					// wire [1:0]x;           ==> AST_WIRE, AST_RANGE children
-					// wire [1:0]x[1:0];      ==> AST_MEMORY, two AST_RANGE children (1st for packed, 2nd for unpacked)
-					// wire [1:0]x[1:0][1:0]; ==> AST_MEMORY, one AST_RANGE child (0) for packed, then AST_MULTIRANGE child (1) for unpacked
-					// (updated: actually by the time we are here, AST_MULTIRANGE is converted into one big AST_RANGE)
-					// case 0 handled by default
-					else if ((id_ast->type == AST_WIRE || id_ast->type == AST_MEMORY) && id_ast->children.size() > 0) {
-						// handle packed array left/right for case 1, and cases 2/3 when requesting the last dimension (packed side)
-						AstNode *wire_range = id_ast->children[0];
-						left = wire_range->children[0]->integer;
-						right = wire_range->children[1]->integer;
-						high = max(left, right);
-						low  = min(left, right);
-					}
-					if (id_ast->type == AST_MEMORY) {
-						// a slice of our identifier means we advance to the next dimension, e.g. $size(a[3])
-						if (buf->children.size() > 0) {
-							// something is hanging below this identifier
-							if (buf->children[0]->type == AST_RANGE && buf->integer == 0)
-								// if integer == 0, this node was originally created as AST_RANGE so it's dimension is 1
-								dim++;
-							// more than one range, e.g. $size(a[3][2])
-							else // created an AST_MULTIRANGE, converted to AST_RANGE, but original dimension saved in 'integer' field
-								dim += buf->integer; // increment by multirange size
-						}
 
-						// We got here only if the argument is a memory
-						// Otherwise $size() and $bits() return the expression width
-						AstNode *mem_range = id_ast->children[1];
-						if (str == "\\$bits") {
-							if (mem_range->type == AST_RANGE) {
-								if (!mem_range->range_valid)
-									input_error("Failed to detect width of memory access `%s'!\n", buf->str.c_str());
-								mem_depth = mem_range->range_left - mem_range->range_right + 1;
-							} else
-								input_error("Unknown memory depth AST type in `%s'!\n", buf->str.c_str());
-						} else {
-							// $size(), $left(), $right(), $high(), $low()
-							int dims = 1;
-							if (mem_range->type == AST_RANGE) {
-								if (id_ast->multirange_dimensions.empty()) {
-									if (!mem_range->range_valid)
-										input_error("Failed to detect width of memory access `%s'!\n", buf->str.c_str());
-									if (dim == 1) {
-										left  = mem_range->range_right;
-										right = mem_range->range_left;
-										high = max(left, right);
-										low  = min(left, right);
-									}
-								} else {
-									dims = GetSize(id_ast->multirange_dimensions)/2;
-									if (dim <= dims) {
-										width_hint = id_ast->multirange_dimensions[2*dim-1];
-										high = id_ast->multirange_dimensions[2*dim-2] + id_ast->multirange_dimensions[2*dim-1] - 1;
-										low  = id_ast->multirange_dimensions[2*dim-2];
-										if (id_ast->multirange_swapped[dim-1]) {
-											left = low;
-											right = high;
-										} else {
-											right = low;
-											left = high;
-										}
-									} else if ((dim > dims+1) || (dim < 0))
-										input_error("Dimension %d out of range in `%s', as it only has dimensions 1..%d!\n", dim, buf->str.c_str(), dims+1);
-								}
-							} else {
-								input_error("Unknown memory depth AST type in `%s'!\n", buf->str.c_str());
-							}
+						int dims = GetSize(id_ast->dimensions);
+						// TODO: IEEE Std 1800-2017 20.7: "If the first argument to an array query function would cause $dimensions to return 0
+						// or if the second argument is out of range, then 'x shall be returned."
+						if (dim < 1 || dim > dims)
+							input_error("Dimension %d out of range in `%s', as it only has %d dimensions!\n", dim, id_ast->str.c_str(), dims);
+
+						expr_dimensions = dims - dim + 1;
+						expr_unpacked_dimensions = std::max(id_ast->unpacked_dimensions - dim + 1, 0);
+
+						right = low  = id_ast->dimensions[dim - 1].range_right;
+						left  = high = low + id_ast->dimensions[dim - 1].range_width - 1;
+						if (id_ast->dimensions[dim - 1].range_swapped) {
+							std::swap(left, right);
+						}
+						for (int i = dim; i < dims; i++) {
+							mem_depth *= id_ast->dimensions[i].range_width;
 						}
 					}
 					width = high - low + 1;
 				} else {
 					width = width_hint;
+					right = low  = 0;
+					left  = high = width - 1;
+					expr_dimensions = 1;
 				}
 				delete buf;
-				if (str == "\\$high")
+				if (str == "\\$dimensions")
+					result = expr_dimensions;
+				else if (str == "\\$unpacked_dimensions")
+					result = expr_unpacked_dimensions;
+				else if (str == "\\$high")
 					result = high;
 				else if (str == "\\$low")
 					result = low;
@@ -3653,6 +3525,8 @@ skip_dynamic_range_lvalue_expansion:;
 					result = left;
 				else if (str == "\\$right")
 					result = right;
+				else if (str == "\\$increment")
+					result = left >= right ? 1 : -1;
 				else if (str == "\\$size")
 					result = width;
 				else { // str == "\\$bits"
@@ -3682,7 +3556,7 @@ skip_dynamic_range_lvalue_expansion:;
 				}
 
 				if (children.size() >= 1) {
-					while (children[0]->simplify(true, false, stage, width_hint, sign_hint, false)) { }
+					while (children[0]->simplify(true, stage, width_hint, sign_hint)) { }
 					if (!children[0]->isConst())
 						input_error("Failed to evaluate system function `%s' with non-constant argument.\n",
 								RTLIL::unescape_id(str).c_str());
@@ -3693,7 +3567,7 @@ skip_dynamic_range_lvalue_expansion:;
 				}
 
 				if (children.size() >= 2) {
-					while (children[1]->simplify(true, false, stage, width_hint, sign_hint, false)) { }
+					while (children[1]->simplify(true, stage, width_hint, sign_hint)) { }
 					if (!children[1]->isConst())
 						input_error("Failed to evaluate system function `%s' with non-constant argument.\n",
 								RTLIL::unescape_id(str).c_str());
@@ -3735,13 +3609,8 @@ skip_dynamic_range_lvalue_expansion:;
 			}
 
 			if (str == "\\$sformatf") {
-				AstNode *node_string = children[0];
-				while (node_string->simplify(true, false, stage, width_hint, sign_hint, false)) { }
-				if (node_string->type != AST_CONSTANT)
-					input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str());
-				std::string sformat = node_string->bitsAsConst().decode_string();
-				std::string sout = process_format_str(sformat, 1, stage, width_hint, sign_hint);
-				newNode = AstNode::mkconst_str(sout);
+				Fmt fmt = processFormat(stage, /*sformat_like=*/true);
+				newNode = AstNode::mkconst_str(fmt.render());
 				goto apply_newNode;
 			}
 
@@ -3755,7 +3624,7 @@ skip_dynamic_range_lvalue_expansion:;
 				// Determine which bits to count
 				for (size_t i = 1; i < children.size(); i++) {
 					AstNode *node = children[i];
-					while (node->simplify(true, false, stage, -1, false, false)) { }
+					while (node->simplify(true, stage, -1, false)) { }
 					if (node->type != AST_CONSTANT)
 						input_error("Failed to evaluate system function `%s' with non-constant control bit argument.\n", str.c_str());
 					if (node->bits.size() != 1)
@@ -3850,7 +3719,7 @@ skip_dynamic_range_lvalue_expansion:;
 
 					argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str));
 					args.push_back(children.at(i-2)->clone());
-					while (args.back()->simplify(true, false, stage, -1, false, true)) { }
+					while (args.back()->simplify(true, stage, -1, false)) { }
 
 					if (args.back()->type != AST_CONSTANT && args.back()->type != AST_REALVALUE)
 						input_error("Failed to evaluate DPI function with non-constant argument.\n");
@@ -3887,12 +3756,12 @@ skip_dynamic_range_lvalue_expansion:;
 							RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				AstNode *node_filename = children[0]->clone();
-				while (node_filename->simplify(true, false, stage, width_hint, sign_hint, false)) { }
+				while (node_filename->simplify(true, stage, width_hint, sign_hint)) { }
 				if (node_filename->type != AST_CONSTANT)
 					input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str());
 
 				AstNode *node_memory = children[1]->clone();
-				while (node_memory->simplify(true, false, stage, width_hint, sign_hint, false)) { }
+				while (node_memory->simplify(true, stage, width_hint, sign_hint)) { }
 				if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY)
 					input_error("Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str());
 
@@ -3900,7 +3769,7 @@ skip_dynamic_range_lvalue_expansion:;
 
 				if (GetSize(children) > 2) {
 					AstNode *node_addr = children[2]->clone();
-					while (node_addr->simplify(true, false, stage, width_hint, sign_hint, false)) { }
+					while (node_addr->simplify(true, stage, width_hint, sign_hint)) { }
 					if (node_addr->type != AST_CONSTANT)
 						input_error("Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str());
 					start_addr = int(node_addr->asInt(false));
@@ -3908,7 +3777,7 @@ skip_dynamic_range_lvalue_expansion:;
 
 				if (GetSize(children) > 3) {
 					AstNode *node_addr = children[3]->clone();
-					while (node_addr->simplify(true, false, stage, width_hint, sign_hint, false)) { }
+					while (node_addr->simplify(true, stage, width_hint, sign_hint)) { }
 					if (node_addr->type != AST_CONSTANT)
 						input_error("Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str());
 					finish_addr = int(node_addr->asInt(false));
@@ -3960,13 +3829,14 @@ skip_dynamic_range_lvalue_expansion:;
 			bool require_const_eval = decl->has_const_only_constructs();
 			bool all_args_const = true;
 			for (auto child : children) {
-				while (child->simplify(true, false, 1, -1, false, true)) { }
+				while (child->simplify(true, 1, -1, false)) { }
 				if (child->type != AST_CONSTANT && child->type != AST_REALVALUE)
 					all_args_const = false;
 			}
 
 			if (all_args_const) {
 				AstNode *func_workspace = decl->clone();
+				func_workspace->set_in_param_flag(true);
 				func_workspace->str = prefix_id(prefix, "$result");
 				newNode = func_workspace->eval_const_function(this, in_param || require_const_eval);
 				delete func_workspace;
@@ -4004,7 +3874,7 @@ skip_dynamic_range_lvalue_expansion:;
 
 			current_scope[wire->str] = wire;
 			current_ast_mod->children.push_back(wire);
-			while (wire->simplify(true, false, 1, -1, false, false)) { }
+			while (wire->simplify(true, 1, -1, false)) { }
 
 			AstNode *lvalue = new AstNode(AST_IDENTIFIER);
 			lvalue->str = wire->str;
@@ -4050,7 +3920,7 @@ skip_dynamic_range_lvalue_expansion:;
 					wire->is_input = false;
 					wire->is_output = false;
 					current_ast_mod->children.push_back(wire);
-					while (wire->simplify(true, false, 1, -1, false, false)) { }
+					while (wire->simplify(true, 1, -1, false)) { }
 
 					AstNode *wire_id = new AstNode(AST_IDENTIFIER);
 					wire_id->str = wire->str;
@@ -4093,7 +3963,7 @@ skip_dynamic_range_lvalue_expansion:;
 						for (auto c : child->children)
 							wire->children.push_back(c->clone());
 					} else if (!child->children.empty()) {
-						while (child->simplify(true, false, stage, -1, false, false)) { }
+						while (child->simplify(true, stage, -1, false)) { }
 						if (GetSize(child->children) == GetSize(wire->children) - contains_value) {
 							for (int i = 0; i < GetSize(child->children); i++)
 								if (*child->children.at(i) != *wire->children.at(i + contains_value))
@@ -4111,9 +3981,9 @@ skip_dynamic_range_lvalue_expansion:;
 					wire->is_input = false;
 					wire->is_output = false;
 					wire->is_reg = true;
-					wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
+					wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
 					if (child->type == AST_ENUM_ITEM)
-						wire->attributes[ID::enum_base_type] = child->attributes[ID::enum_base_type];
+						wire->set_attribute(ID::enum_base_type, child->attributes[ID::enum_base_type]);
 
 					wire_cache[child->str] = wire;
 
@@ -4121,7 +3991,7 @@ skip_dynamic_range_lvalue_expansion:;
 					current_ast_mod->children.push_back(wire);
 				}
 
-				while (wire->simplify(true, false, 1, -1, false, false)) { }
+				while (wire->simplify(true, 1, -1, false)) { }
 
 				if ((child->is_input || child->is_output) && arg_count < children.size())
 				{
@@ -4152,8 +4022,9 @@ skip_dynamic_range_lvalue_expansion:;
 								range->children.push_back(mkconst_int(0, true));
 							}
 						}
+						wire->fixup_hierarchy_flags();
 						// updates the sizing
-						while (wire->simplify(true, false, 1, -1, false, false)) { }
+						while (wire->simplify(true, 1, -1, false)) { }
 						delete arg;
 						continue;
 					}
@@ -4222,7 +4093,7 @@ replace_fcall_later:;
 							tmp_range_left = (param_width + 2*param_offset) - children[0]->range_right - 1;
 							tmp_range_right = (param_width + 2*param_offset) - children[0]->range_left - 1;
 						}
-						AST::AstNode *member_node = get_struct_member(this);
+						AstNode *member_node = get_struct_member();
 						int chunk_offset = member_node ? member_node->range_right : 0;
 						log_assert(!(chunk_offset && param_upto));
 						for (int i = tmp_range_right; i <= tmp_range_left; i++) {
@@ -4471,6 +4342,7 @@ replace_fcall_later:;
 		newNode->filename = filename;
 		newNode->location = location;
 		newNode->cloneInto(this);
+		fixup_hierarchy_flags();
 		delete newNode;
 		did_something = true;
 	}
@@ -4686,6 +4558,8 @@ void AstNode::expand_genblock(const std::string &prefix)
 		switch (child->type) {
 		case AST_WIRE:
 		case AST_MEMORY:
+		case AST_STRUCT:
+		case AST_UNION:
 		case AST_PARAMETER:
 		case AST_LOCALPARAM:
 		case AST_FUNCTION:
@@ -4859,6 +4733,9 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
 	{
 		AstNode *mem = id2ast;
 
+		if (integer < (unsigned)mem->unpacked_dimensions)
+			input_error("Insufficient number of array indices for %s.\n", log_id(str));
+
 		// flag if used after blocking assignment (in same proc)
 		if ((proc_flags[mem] & AstNode::MEM2REG_FL_EQ1) && !(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_EQ2)) {
 			mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
@@ -5061,18 +4938,18 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 		wire_addr->str = id_addr;
 		wire_addr->is_reg = true;
 		wire_addr->was_checked = true;
-		wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
+		wire_addr->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
 		mod->children.push_back(wire_addr);
-		while (wire_addr->simplify(true, false, 1, -1, false, false)) { }
+		while (wire_addr->simplify(true, 1, -1, false)) { }
 
 		AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
 		wire_data->str = id_data;
 		wire_data->is_reg = true;
 		wire_data->was_checked = true;
 		wire_data->is_signed = mem_signed;
-		wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
+		wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
 		mod->children.push_back(wire_data);
-		while (wire_data->simplify(true, false, 1, -1, false, false)) { }
+		while (wire_data->simplify(true, 1, -1, false)) { }
 
 		log_assert(block != NULL);
 		size_t assign_idx = 0;
@@ -5099,6 +4976,10 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 			cond_node->children[1]->children.push_back(assign_reg);
 			case_node->children.push_back(cond_node);
 		}
+
+		// fixup on the full hierarchy below case_node
+		case_node->fixup_hierarchy_flags(true);
+
 		block->children.insert(block->children.begin()+assign_idx+2, case_node);
 
 		children[0]->delete_children();
@@ -5108,6 +4989,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 		type = AST_ASSIGN_EQ;
 		children[0]->was_checked = true;
 
+		fixup_hierarchy_flags();
 		did_something = true;
 	}
 
@@ -5137,7 +5019,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 				int width;
 				if (bit_part_sel)
 				{
-					bit_part_sel->dumpAst(nullptr, "? ");
+					// bit_part_sel->dumpAst(nullptr, "? ");
 					if (bit_part_sel->children.size() == 1)
 						width = 0;
 					else
@@ -5178,9 +5060,9 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 			wire_addr->is_reg = true;
 			wire_addr->was_checked = true;
 			if (block)
-				wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
+				wire_addr->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
 			mod->children.push_back(wire_addr);
-			while (wire_addr->simplify(true, false, 1, -1, false, false)) { }
+			while (wire_addr->simplify(true, 1, -1, false)) { }
 
 			AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
 			wire_data->str = id_data;
@@ -5188,9 +5070,9 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 			wire_data->was_checked = true;
 			wire_data->is_signed = mem_signed;
 			if (block)
-				wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
+				wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
 			mod->children.push_back(wire_data);
-			while (wire_data->simplify(true, false, 1, -1, false, false)) { }
+			while (wire_data->simplify(true, 1, -1, false)) { }
 
 			AstNode *assign_addr = new AstNode(block ? AST_ASSIGN_EQ : AST_ASSIGN, new AstNode(AST_IDENTIFIER), children[0]->children[0]->clone());
 			assign_addr->children[0]->str = id_addr;
@@ -5222,6 +5104,9 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 			cond_node->children[1]->children.push_back(assign_reg);
 			case_node->children.push_back(cond_node);
 
+			// fixup on the full hierarchy below case_node
+			case_node->fixup_hierarchy_flags(true);
+
 			if (block)
 			{
 				size_t assign_idx = 0;
@@ -5233,10 +5118,10 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 			}
 			else
 			{
-				AstNode *proc = new AstNode(AST_ALWAYS, new AstNode(AST_BLOCK));
-				proc->children[0]->children.push_back(case_node);
+				AstNode *proc = new AstNode(AST_ALWAYS, new AstNode(AST_BLOCK, case_node));
 				mod->children.push_back(proc);
 				mod->children.push_back(assign_addr);
+				mod->fixup_hierarchy_flags();
 			}
 
 			delete_children();
@@ -5245,8 +5130,10 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 			str = id_data;
 		}
 
-		if (bit_part_sel)
+		if (bit_part_sel) {
 			children.push_back(bit_part_sel);
+			fixup_hierarchy_flags();
+		}
 
 		did_something = true;
 	}
@@ -5368,7 +5255,7 @@ bool AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &varia
 			}
 			if (!children.at(0)->replace_variables(variables, fcall, must_succeed))
 				return false;
-			while (simplify(true, false, 1, -1, false, true)) { }
+			while (simplify(true, 1, -1, false)) { }
 			if (!children.at(0)->range_valid) {
 				if (!must_succeed)
 					return false;
@@ -5409,6 +5296,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
 	{
 		block->children.push_back(child->clone());
 	}
+	block->set_in_param_flag(true);
 
 	while (!block->children.empty())
 	{
@@ -5423,7 +5311,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
 
 		if (stmt->type == AST_WIRE)
 		{
-			while (stmt->simplify(true, false, 1, -1, false, true)) { }
+			while (stmt->simplify(true, 1, -1, false)) { }
 			if (!stmt->range_valid) {
 				if (!must_succeed)
 					goto finished;
@@ -5467,7 +5355,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
 
 		if (stmt->type == AST_LOCALPARAM)
 		{
-			while (stmt->simplify(true, false, 1, -1, false, true)) { }
+			while (stmt->simplify(true, 1, -1, false)) { }
 
 			current_scope[stmt->str] = stmt;
 
@@ -5484,7 +5372,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
 					goto finished;
 			if (!stmt->children.at(1)->replace_variables(variables, fcall, must_succeed))
 				goto finished;
-			while (stmt->simplify(true, false, 1, -1, false, true)) { }
+			while (stmt->simplify(true, 1, -1, false)) { }
 
 			if (stmt->type != AST_ASSIGN_EQ)
 				continue;
@@ -5551,7 +5439,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
 			AstNode *cond = stmt->children.at(0)->clone();
 			if (!cond->replace_variables(variables, fcall, must_succeed))
 				goto finished;
-			while (cond->simplify(true, false, 1, -1, false, true)) { }
+			cond->set_in_param_flag(true);
+			while (cond->simplify(true, 1, -1, false)) { }
 
 			if (cond->type != AST_CONSTANT) {
 				if (!must_succeed)
@@ -5576,7 +5465,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
 			AstNode *num = stmt->children.at(0)->clone();
 			if (!num->replace_variables(variables, fcall, must_succeed))
 				goto finished;
-			while (num->simplify(true, false, 1, -1, false, true)) { }
+			num->set_in_param_flag(true);
+			while (num->simplify(true, 1, -1, false)) { }
 
 			if (num->type != AST_CONSTANT) {
 				if (!must_succeed)
@@ -5599,7 +5489,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
 			AstNode *expr = stmt->children.at(0)->clone();
 			if (!expr->replace_variables(variables, fcall, must_succeed))
 				goto finished;
-			while (expr->simplify(true, false, 1, -1, false, true)) { }
+			expr->set_in_param_flag(true);
+			while (expr->simplify(true, 1, -1, false)) { }
 
 			AstNode *sel_case = NULL;
 			for (size_t i = 1; i < stmt->children.size(); i++)
@@ -5619,7 +5510,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
 						goto finished;
 
 					cond = new AstNode(AST_EQ, expr->clone(), cond);
-					while (cond->simplify(true, false, 1, -1, false, true)) { }
+					cond->set_in_param_flag(true);
+					while (cond->simplify(true, 1, -1, false)) { }
 
 					if (cond->type != AST_CONSTANT) {
 						if (!must_succeed)
@@ -5654,6 +5546,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
 			block->children.erase(block->children.begin());
 			block->children.insert(block->children.begin(), stmt->children.begin(), stmt->children.end());
 			stmt->children.clear();
+			block->fixup_hierarchy_flags();
 			delete stmt;
 			continue;
 		}
@@ -5688,7 +5581,7 @@ void AstNode::allocateDefaultEnumValues()
 	int last_enum_int = -1;
 	for (auto node : children) {
 		log_assert(node->type==AST_ENUM_ITEM);
-		node->attributes[ID::enum_base_type] = mkconst_str(str);
+		node->set_attribute(ID::enum_base_type, mkconst_str(str));
 		for (size_t i = 0; i < node->children.size(); i++) {
 			switch (node->children[i]->type) {
 			case AST_NONE:
@@ -5769,7 +5662,7 @@ std::string AstNode::try_pop_module_prefix() const
 		if (current_scope.count(new_str)) {
 			std::string prefix = str.substr(0, pos);
 			auto it = current_scope_ast->attributes.find(ID::hdlname);
-			if ((it != current_scope_ast->attributes.end() && it->second->str == prefix)
+			if ((it != current_scope_ast->attributes.end() && it->second->str == prefix.substr(1))
 					|| prefix == current_scope_ast->str)
 				return new_str;
 		}
diff --git a/yosys/frontends/blif/blifparse.cc b/yosys/frontends/blif/blifparse.cc
index ebbe082a2e8..731656866ea 100644
--- a/yosys/frontends/blif/blifparse.cc
+++ b/yosys/frontends/blif/blifparse.cc
@@ -256,6 +256,16 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 				continue;
 			}
 
+			if (!strcmp(cmd, ".area") || !strcmp(cmd, ".delay") || !strcmp(cmd, ".wire_load_slope") || !strcmp(cmd, ".wire") ||
+			    !strcmp(cmd, ".input_arrival") || !strcmp(cmd, ".default_input_arrival") || !strcmp(cmd, ".output_required") ||
+			    !strcmp(cmd, ".default_output_required") || !strcmp(cmd, ".input_drive") || !strcmp(cmd, ".default_input_drive") ||
+			    !strcmp(cmd, ".max_input_load") || !strcmp(cmd, ".default_max_input_load") || !strcmp(cmd, ".output_load") ||
+			    !strcmp(cmd, ".default_output_load"))
+			{
+				log_warning("Blif delay constraints (%s) are not supported.", cmd);
+				continue;
+			}
+
 			if (!strcmp(cmd, ".inputs") || !strcmp(cmd, ".outputs"))
 			{
 				char *p;
diff --git a/yosys/frontends/liberty/liberty.cc b/yosys/frontends/liberty/liberty.cc
index cadbcaee69f..86bb4c7dcd4 100644
--- a/yosys/frontends/liberty/liberty.cc
+++ b/yosys/frontends/liberty/liberty.cc
@@ -214,6 +214,18 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
 	return stack.back().sig;
 }
 
+static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func, const char *three_state_expr)
+{
+	RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);
+
+	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf));
+	cell->setParam(ID::WIDTH, GetSize(func));
+	cell->setPort(ID::A, func);
+	cell->setPort(ID::EN, create_inv_cell(module, three_state));
+	cell->setPort(ID::Y, module->addWire(NEW_ID));
+	return cell->getPort(ID::Y);
+}
+
 static void create_ff(RTLIL::Module *module, LibertyAst *node)
 {
 	RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
@@ -695,18 +707,24 @@ struct LibertyFrontend : public Frontend {
 					LibertyAst *func = node->find("function");
 					if (func == NULL)
 					{
-						if (!flag_ignore_miss_func)
-						{
-							log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
-						} else {
-							log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name));
-							delete module;
-							goto skip_cell;
+						if (dir->value != "inout") { // allow inout with missing function, can be used for power pins
+							if (!flag_ignore_miss_func)
+							{
+								log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
+							} else {
+								log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name));
+								delete module;
+								goto skip_cell;
+							}
+						}
+					} else {
+						RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
+						LibertyAst *three_state = node->find("three_state");
+						if (three_state) {
+							out_sig = create_tristate(module, out_sig, three_state->value.c_str());
 						}
+						module->connect(RTLIL::SigSig(wire, out_sig));
 					}
-
-					RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
-					module->connect(RTLIL::SigSig(wire, out_sig));
 				}
 			}
 
diff --git a/yosys/frontends/verific/Makefile.inc b/yosys/frontends/verific/Makefile.inc
index c82428613af..0766240a4a4 100644
--- a/yosys/frontends/verific/Makefile.inc
+++ b/yosys/frontends/verific/Makefile.inc
@@ -10,10 +10,11 @@ EXTRA_TARGETS += share/verific
 share/verific:
 	$(P) rm -rf share/verific.new
 	$(Q) mkdir -p share/verific.new
-ifneq ($(DISABLE_VERIFIC_VHDL),1)
+ifeq ($(ENABLE_VERIFIC_VHDL),1)
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008
+	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2019/. share/verific.new/vhdl_vdbs_2019
 endif
 	$(Q) chmod -R a+rX share/verific.new
 	$(Q) mv share/verific.new share/verific
diff --git a/yosys/frontends/verific/verific.cc b/yosys/frontends/verific/verific.cc
index b0d789d8fa3..56e94489cba 100644
--- a/yosys/frontends/verific/verific.cc
+++ b/yosys/frontends/verific/verific.cc
@@ -42,16 +42,24 @@ USING_YOSYS_NAMESPACE
 #pragma clang diagnostic ignored "-Woverloaded-virtual"
 #endif
 
-#include "veri_file.h"
+#include "Array.h"
+#include "RuntimeFlags.h"
+#ifdef VERIFIC_HIER_TREE_SUPPORT
 #include "hier_tree.h"
+#endif
+
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+#include "veri_file.h"
 #include "VeriModule.h"
 #include "VeriWrite.h"
 #include "VeriLibrary.h"
 #include "VeriExpression.h"
+#endif
 
 #ifdef VERIFIC_VHDL_SUPPORT
 #include "vhdl_file.h"
 #include "VhdlUnits.h"
+#include "NameSpace.h"
 #endif
 
 #ifdef VERIFIC_EDIF_SUPPORT
@@ -71,11 +79,15 @@ USING_YOSYS_NAMESPACE
 #endif
 
 #ifndef YOSYSHQ_VERIFIC_API_VERSION
-#  error "Only YosysHQ flavored Verific is supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific."
+#warning "Only YosysHQ flavored Verific is fully supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific."
+#else
+#if YOSYSHQ_VERIFIC_API_VERSION < 20230901
+#  error "Please update your version of YosysHQ flavored Verific."
+#endif
 #endif
 
-#if YOSYSHQ_VERIFIC_API_VERSION < 20210801
-#  error "Please update your version of YosysHQ flavored Verific."
+#if !defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT)
+#error "At least one of HDL languages must be enabled."
 #endif
 
 #ifdef __clang__
@@ -96,7 +108,9 @@ bool verific_import_pending;
 string verific_error_msg;
 int verific_sva_fsm_limit;
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 vector<string> verific_incdirs, verific_libdirs, verific_libexts;
+#endif
 
 void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args)
 {
@@ -114,7 +128,15 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil
 
 	if (log_verific_callback) {
 		string full_message = stringf("%s%s\n", message_prefix.c_str(), message.c_str());
-		log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), LineFile::GetLineNo(linefile), full_message.c_str());
+#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS 
+		log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), 
+			linefile ? linefile->GetLeftLine() : 0, linefile ? linefile->GetLeftCol() : 0, 
+			linefile ? linefile->GetRightLine() : 0, linefile ? linefile->GetRightCol() : 0, full_message.c_str());
+#else
+		log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), 
+			linefile ? LineFile::GetLineNo(linefile) : 0, 0, 
+			linefile ? LineFile::GetLineNo(linefile) : 0, 0, full_message.c_str());
+#endif
 	} else {
 		if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR)
 			log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str());
@@ -125,7 +147,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil
 		verific_error_msg = message;
 }
 
-void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg))
+void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg))
 {
 	Message::SetConsoleOutput(0);
 	Message::RegisterCallBackMsg(msg_func);
@@ -142,6 +164,7 @@ string get_full_netlist_name(Netlist *nl)
 	return nl->CellBaseName();
 }
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 class YosysStreamCallBackHandler : public VerificStreamCallBackHandler
 {
 public:
@@ -171,6 +194,7 @@ class YosysStreamCallBackHandler : public VerificStreamCallBackHandler
 };
 
 YosysStreamCallBackHandler verific_read_cb;
+#endif
 
 // ==================================================================
 
@@ -211,23 +235,120 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
 	return s;
 }
 
-// When used as attributes or parameter values Verific constants come already processed.
-// - Real string values are already under quotes
-// - Numeric values with specified width are always converted to binary
-// - Rest of user defined values are handled as 32bit integers
-// - There could be some internal values that are strings without quotes
-//   so we check if value is all digits or not
-//
-// Note: For signed values, verific uses <len>'sb<bits> and decimal values can
-// also be negative.
-static const RTLIL::Const verific_const(const char *value, bool allow_string = true, bool output_signed = false)
+RTLIL::Const mkconst_str(const std::string &str)
+{
+	RTLIL::Const val;
+	std::vector<RTLIL::State> data;
+	data.reserve(str.size() * 8);
+	for (size_t i = 0; i < str.size(); i++) {
+		unsigned char ch = str[str.size() - i - 1];
+		for (int j = 0; j < 8; j++) {
+			data.push_back((ch & 1) ? State::S1 : State::S0);
+			ch = ch >> 1;
+		}
+	}
+	val.bits = data;
+	val.flags |= RTLIL::CONST_FLAG_STRING;
+	return val;
+}
+
+static const RTLIL::Const extract_vhdl_boolean(std::string &val)
+{
+	if (val == "false")
+		return RTLIL::Const::from_string("0");
+	if (val == "true")
+		return RTLIL::Const::from_string("1");
+	log_error("Expecting VHDL boolean value.\n");
+}
+
+static const RTLIL::Const extract_vhdl_bit(std::string &val, std::string &typ)
+{
+	if (val.size()==3 && val[0]=='\'' && val.back()=='\'')
+		return  RTLIL::Const::from_string(val.substr(1,val.size()-2));
+	log_error("Error parsing VHDL %s.\n", typ.c_str());
+}
+
+static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string &typ)
+{
+	if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
+		RTLIL::Const c = RTLIL::Const::from_string(val.substr(1,val.size()-2));
+		if (typ == "signed")
+			c.flags |= RTLIL::CONST_FLAG_SIGNED;
+		return c;
+	}
+	log_error("Error parsing VHDL %s.\n", typ.c_str());
+}
+
+static const RTLIL::Const extract_vhdl_integer(std::string &val)
 {
-	size_t found;
+	char *end;
+	return RTLIL::Const((int)std::strtol(val.c_str(), &end, 10), 32);
+}
+
+static const RTLIL::Const extract_vhdl_char(std::string &val)
+{
+	if (val.size()==3 && val[0]=='\"' && val.back()=='\"')
+		return RTLIL::Const((int)val[1], 32);
+	log_error("Error parsing VHDL character.\n");
+}
+
+static const RTLIL::Const extract_real_value(std::string &val)
+{
+	RTLIL::Const c = mkconst_str(val);
+	c.flags |= RTLIL::CONST_FLAG_REAL;
+	return c;
+}
+
+static const RTLIL::Const extract_vhdl_string(std::string &val)
+{
+	if (!(val.size()>1 && val[0]=='\"' && val.back()=='\"'))
+		log_error("Error parsing VHDL string.\n");
+	return RTLIL::Const(val.substr(1,val.size()-2));
+}
+
+static const  RTLIL::Const extract_vhdl_const(const char *value, bool output_signed)
+{
+	RTLIL::Const c;
 	char *end;
 	int decimal;
 	bool is_signed = false;
+	std::string val = std::string(value);
+
+	if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
+		std::string data = val.substr(1,val.size()-2);
+		bool isBinary = std::all_of(data.begin(), data.end(), [](char c) {return c=='1' || c=='0'; });
+		if (isBinary)
+			c = RTLIL::Const::from_string(data);
+		else 
+			c = RTLIL::Const(data);
+	} else if (val.size()==3 && val[0]=='\'' && val.back()=='\'') {
+		c = RTLIL::Const::from_string(val.substr(1,val.size()-2));
+	} else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) &&
+			((decimal = std::strtol(value, &end, 10)), !end[0])) {
+		is_signed = output_signed;
+		c = RTLIL::Const((int)decimal, 32);
+	} else if (val == "false") {
+		c = RTLIL::Const::from_string("0");
+	} else if (val == "true") {
+		c = RTLIL::Const::from_string("1");
+	} else {
+		c = mkconst_str(val);
+		log_warning("encoding value '%s' as string.\n", value);
+	}
+	if (is_signed)
+		c.flags |= RTLIL::CONST_FLAG_SIGNED;
+	return c;
+}
+
+static const  RTLIL::Const extract_verilog_const(const char *value, bool allow_string, bool output_signed)
+{
 	RTLIL::Const c;
+	char *end;
+	int decimal;
+	bool is_signed = false;
+	size_t found;
 	std::string val = std::string(value);
+
 	if (allow_string && val.size()>1 && val[0]=='\"' && val.back()=='\"') {
 		c = RTLIL::Const(val.substr(1,val.size()-2));
 	} else if ((found = val.find("'sb")) != std::string::npos) {
@@ -242,27 +363,86 @@ static const RTLIL::Const verific_const(const char *value, bool allow_string = t
 	} else if (allow_string) {
 		c = RTLIL::Const(val);
 	} else {
-		log_error("expected numeric constant but found '%s'", value);
+		c = mkconst_str(val);
+		log_warning("encoding value '%s' as string.\n", value);
 	}
-
 	if (is_signed)
 		c.flags |= RTLIL::CONST_FLAG_SIGNED;
-
 	return c;
 }
 
+// When used as attributes or parameter values Verific constants come already processed.
+// - Real string values are already under quotes
+// - Numeric values with specified width are always converted to binary
+// - Rest of user defined values are handled as 32bit integers
+// - There could be some internal values that are strings without quotes
+//   so we check if value is all digits or not
+//
+// Note: For signed values, verific uses <len>'sb<bits> and decimal values can
+// also be negative.
+static const RTLIL::Const verific_const(const char* type_name, const char *value, DesignObj *obj, bool allow_string = true, bool output_signed = false)
+{
+	std::string val = std::string(value);
+	// VHDL
+	if (obj->IsFromVhdl()) {
+		if (type_name) {
+			std::string typ = std::string(type_name);
+			transform(typ.begin(), typ.end(), typ.begin(), ::tolower);
+			if (typ ==  "integer" ||  typ == "natural" || typ=="positive") return extract_vhdl_integer(val);
+			else if (typ =="boolean") return extract_vhdl_boolean(val);
+			else if (typ == "bit" || typ =="std_logic" || typ == "std_ulogic") return extract_vhdl_bit(val,typ);
+			else if (typ == "character") return extract_vhdl_char(val);
+			else if (typ == "bit_vector" || typ == "std_logic_vector" || typ == "std_ulogic_vector" ||
+					 typ == "unsigned" || typ == "signed") return extract_vhdl_bit_vector(val,typ);
+			else if (typ == "real") return extract_real_value(val);
+			else if (typ == "string") return extract_vhdl_string(val);
+			else {
+				if (val.size()>1 && val[0]=='\"' && val.back()=='\"')
+					return RTLIL::Const(val.substr(1,val.size()-2));
+				else if (val.size()==3 && val[0]=='\'' && val.back()=='\'')
+					return RTLIL::Const(val.substr(1,val.size()-2));
+				else
+					return RTLIL::Const(val);
+			}
+		} else extract_vhdl_const(value, output_signed);
+	}
+	// SystemVerilog
+	if (type_name && strcmp(type_name, "real")==0) {
+		return extract_real_value(val);
+	} else 
+		return extract_verilog_const(value, allow_string, output_signed);
+}
+
+#ifdef YOSYSHQ_VERIFIC_API_VERSION
+static const std::string verific_unescape(const char *value)
+{
+	std::string val = std::string(value);
+	if (val.size()>1 && val[0]=='\"' && val.back()=='\"')
+		return val.substr(1,val.size()-2);
+	return value;
+}
+#endif
+
 void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl)
 {
+	if (!obj)
+		return;
+
 	MapIter mi;
 	Att *attr;
 
+#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS 
+	if (obj->Linefile())
+		attributes[ID::src] = stringf("%s:%d.%d-%d.%d", LineFile::GetFileName(obj->Linefile()), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol());
+#else
 	if (obj->Linefile())
 		attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
+#endif
 
 	FOREACH_ATTRIBUTE(obj, mi, attr) {
 		if (attr->Key()[0] == ' ' || attr->Value() == nullptr)
 			continue;
-		attributes[RTLIL::escape_id(attr->Key())] = verific_const(attr->Value());
+		attributes[RTLIL::escape_id(attr->Key())] = verific_const(nullptr, attr->Value(), obj);
 	}
 
 	if (nl) {
@@ -284,7 +464,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
 		const char *k, *v;
 		FOREACH_MAP_ITEM(type_range->GetEnumIdMap(), mi, &k, &v) {
 			if (nl->IsFromVerilog()) {
-				auto const value = verific_const(v, false);
+				auto const value = verific_const(type_name, v, nl, false);
 
 				attributes.emplace(stringf("\\enum_value_%s", value.as_string().c_str()), RTLIL::escape_id(k));
 			}
@@ -329,36 +509,46 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
 	}
 }
 
+RTLIL::SigBit VerificImporter::netToSigBit(Verific::Net *net) {
+	if (net && net->IsGnd())
+		return RTLIL::State::S0;
+	else if (net && net->IsPwr())
+		return RTLIL::State::S1;
+	else if (net && net->IsX())
+		return RTLIL::State::Sx;
+	else if (net)
+		return net_map_at(net);
+	else
+		return RTLIL::State::Sz;
+}
+
 RTLIL::SigSpec VerificImporter::operatorInput(Instance *inst)
 {
 	RTLIL::SigSpec sig;
-	for (int i = int(inst->InputSize())-1; i >= 0; i--)
-		if (inst->GetInputBit(i))
-			sig.append(net_map_at(inst->GetInputBit(i)));
-		else
-			sig.append(RTLIL::State::Sz);
+	for (int i = int(inst->InputSize())-1; i >= 0; i--) {
+		Net *net = inst->GetInputBit(i);
+		sig.append(netToSigBit(net));
+	}
 	return sig;
 }
 
 RTLIL::SigSpec VerificImporter::operatorInput1(Instance *inst)
 {
 	RTLIL::SigSpec sig;
-	for (int i = int(inst->Input1Size())-1; i >= 0; i--)
-		if (inst->GetInput1Bit(i))
-			sig.append(net_map_at(inst->GetInput1Bit(i)));
-		else
-			sig.append(RTLIL::State::Sz);
+	for (int i = int(inst->Input1Size())-1; i >= 0; i--) {
+		Net *net = inst->GetInput1Bit(i);
+		sig.append(netToSigBit(net));
+	}
 	return sig;
 }
 
 RTLIL::SigSpec VerificImporter::operatorInput2(Instance *inst)
 {
 	RTLIL::SigSpec sig;
-	for (int i = int(inst->Input2Size())-1; i >= 0; i--)
-		if (inst->GetInput2Bit(i))
-			sig.append(net_map_at(inst->GetInput2Bit(i)));
-		else
-			sig.append(RTLIL::State::Sz);
+	for (int i = int(inst->Input2Size())-1; i >= 0; i--) {
+		Net *net = inst->GetInput2Bit(i);
+		sig.append(netToSigBit(net));
+	}
 	return sig;
 }
 
@@ -1103,6 +1293,45 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		return true;
 	}
 
+#ifdef YOSYSHQ_VERIFIC_API_VERSION
+	if (inst->Type() == OPER_YOSYSHQ_SET_TAG)
+	{
+		RTLIL::SigSpec sig_expr = operatorInport(inst, "expr");
+		RTLIL::SigSpec sig_set_mask = operatorInport(inst, "set_mask");
+		RTLIL::SigSpec sig_clr_mask = operatorInport(inst, "clr_mask");
+		RTLIL::SigSpec sig_o = operatorOutput(inst);
+		std::string tag = inst->GetAtt("tag") ? verific_unescape(inst->GetAttValue("tag")) : "";
+		module->connect(sig_o, module->SetTag(new_verific_id(inst), tag, sig_expr, sig_set_mask, sig_clr_mask));
+		return true;
+	}
+	if (inst->Type() == OPER_YOSYSHQ_GET_TAG)
+	{
+		std::string tag = inst->GetAtt("tag") ? verific_unescape(inst->GetAttValue("tag")) : "";
+		module->connect(operatorOutput(inst),module->GetTag(new_verific_id(inst), tag, operatorInput(inst)));
+		return true;
+	}
+	if (inst->Type() == OPER_YOSYSHQ_OVERWRITE_TAG)
+	{
+		RTLIL::SigSpec sig_signal = operatorInport(inst, "signal");
+		RTLIL::SigSpec sig_set_mask = operatorInport(inst, "set_mask");
+		RTLIL::SigSpec sig_clr_mask = operatorInport(inst, "clr_mask");
+		std::string tag = inst->GetAtt("tag") ? verific_unescape(inst->GetAttValue("tag")) : "";
+		module->addOverwriteTag(new_verific_id(inst), tag, sig_signal, sig_set_mask, sig_clr_mask);
+		return true;
+	}
+	if (inst->Type() == OPER_YOSYSHQ_ORIGINAL_TAG)
+	{
+		std::string tag = inst->GetAtt("tag") ? verific_unescape(inst->GetAttValue("tag")) : "";
+		module->connect(operatorOutput(inst),module->OriginalTag(new_verific_id(inst), tag, operatorInput(inst)));
+		return true;
+	}
+	if (inst->Type() == OPER_YOSYSHQ_FUTURE_FF)
+	{
+		module->connect(operatorOutput(inst),module->FutureFF(new_verific_id(inst), operatorInput(inst)));
+		return true;
+	}
+#endif
+
 	#undef IN
 	#undef IN1
 	#undef IN2
@@ -1230,9 +1459,26 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		log("Importing module %s.\n", RTLIL::id2cstr(module->name));
 	}
 	import_attributes(module->attributes, nl, nl);
+	module->set_string_attribute(ID::hdlname, nl->CellBaseName());
+	module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name());
+#ifdef VERIFIC_VHDL_SUPPORT
+	if (nl->IsFromVhdl()) {
+		NameSpace name_space(0);
+		char *architecture_name = name_space.ReName(nl->Name()) ;
+		module->set_string_attribute(ID(architecture), (architecture_name) ? architecture_name : nl->Name());
+	}
+#endif	
+	const char *param_name ;
+	const char *param_value ;
+	MapIter mi;
+	FOREACH_PARAMETER_OF_NETLIST(nl, mi, param_name, param_value) {
+		module->avail_parameters(RTLIL::escape_id(param_name));
+		const TypeRange *tr = nl->GetTypeRange(param_name) ;
+		module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(tr->GetTypeName(), param_value, nl);
+	}
 
 	SetIter si;
-	MapIter mi, mi2;
+	MapIter mi2;
 	Port *port;
 	PortBus *portbus;
 	Net *net;
@@ -1284,7 +1530,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
 		wire->upto = portbus->IsUp();
 		import_attributes(wire->attributes, portbus, nl);
-
+		SetIter si ;
+		Port *port ;
+		FOREACH_PORT_OF_PORTBUS(portbus, si, port) {
+			import_attributes(wire->attributes, port->GetNet(), nl);
+			break;
+		}
 		bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN;
 		if (portbus_input)
 			wire->port_input = true;
@@ -1583,10 +1834,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 	for (auto net : anyseq_nets)
 		module->connect(net_map_at(net), module->Anyseq(new_verific_id(net)));
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	pool<Instance*, hash_ptr_ops> sva_asserts;
 	pool<Instance*, hash_ptr_ops> sva_assumes;
 	pool<Instance*, hash_ptr_ops> sva_covers;
 	pool<Instance*, hash_ptr_ops> sva_triggers;
+#endif
 
 	pool<RTLIL::Cell*> past_ffs;
 
@@ -1703,6 +1956,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 				continue;
 		}
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		if (inst->Type() == PRIM_SVA_ASSERT || inst->Type() == PRIM_SVA_IMMEDIATE_ASSERT)
 			sva_asserts.insert(inst);
 
@@ -1845,7 +2099,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 			if (!mode_keep)
 				continue;
 		}
+#endif
 
+#ifdef YOSYSHQ_VERIFIC_API_VERSION
 		if (inst->Type() == PRIM_YOSYSHQ_INITSTATE)
 		{
 			if (verific_verbose)
@@ -1857,6 +2113,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 			if (!mode_keep)
 				continue;
 		}
+#endif
 
 		if (!mode_keep && verific_sva_prims.count(inst->Type())) {
 			if (verific_verbose)
@@ -1909,6 +2166,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		}
 
 		RTLIL::Cell *cell = module->addCell(inst_name, inst_type);
+		import_attributes(cell->attributes, inst);
 
 		if (inst->IsPrimitive() && mode_keep)
 			cell->attributes[ID::keep] = 1;
@@ -1922,7 +2180,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		const char *param_value ;
 		if (is_blackbox(inst->View())) {
 			FOREACH_PARAMETER_OF_INST(inst, mi2, param_name, param_value) {
-				cell->setParam(RTLIL::escape_id(param_name), verific_const(param_value));
+				const TypeRange *tr = inst->View()->GetTypeRange(param_name) ;
+				cell->setParam(RTLIL::escape_id(param_name), verific_const(tr->GetTypeName(), param_value, inst->View()));
 			}
 		}
 
@@ -1933,8 +2192,16 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 			int port_offset = 0;
 			if (pr->GetPort()->Bus()) {
 				port_name = pr->GetPort()->Bus()->Name();
-				port_offset = pr->GetPort()->Bus()->IndexOf(pr->GetPort()) -
-						min(pr->GetPort()->Bus()->LeftIndex(), pr->GetPort()->Bus()->RightIndex());
+				int msb_index = pr->GetPort()->Bus()->LeftIndex();
+				int lsb_index = pr->GetPort()->Bus()->RightIndex();
+				int index_of_port = pr->GetPort()->Bus()->IndexOf(pr->GetPort());
+				port_offset =  index_of_port - min(msb_index, lsb_index);
+				// In cases where the msb order is flipped we need to make sure
+				// that the indicies match LSB = 0 order to match the std::vector
+				// to SigSpec LSB = 0 precondition.
+				if (lsb_index > msb_index) {
+					port_offset = abs(port_offset - (lsb_index - min(msb_index, lsb_index)));
+				}
 			}
 			IdString port_name_id = RTLIL::escape_id(port_name);
 			auto &sigvec = cell_port_conns[port_name_id];
@@ -1956,6 +2223,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		}
 	}
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	if (!mode_nosva)
 	{
 		for (auto inst : sva_asserts) {
@@ -1975,6 +2243,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 
 		merge_past_ffs(past_ffs);
 	}
+#endif
 
 	if (!mode_fullinit)
 	{
@@ -2026,7 +2295,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 
 // ==================================================================
 
-VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_at_only)
+VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_at_only YS_MAYBE_UNUSED)
 {
 	module = importer->module;
 
@@ -2035,11 +2304,12 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a
 
 	Instance *inst = net->Driver();
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	// Detect condition expression in sva_at_only mode
 	if (sva_at_only)
 	do {
 		Instance *inst_mux = net->Driver();
-		if (inst_mux->Type() != PRIM_MUX)
+		if (inst_mux == nullptr || inst_mux->Type() != PRIM_MUX)
 			break;
 
 		bool pwr1 = inst_mux->GetInput1()->IsPwr();
@@ -2083,7 +2353,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a
 		net = inst->GetInput();
 		inst = net->Driver();;
 	}
-
+#endif
 	if (inst != nullptr && inst->Type() == PRIM_INV)
 	{
 		net = inst->GetInput();
@@ -2129,6 +2399,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a
 		inst = net->Driver();;
 	} while (0);
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	// Detect condition expression
 	do {
 		if (body_net == nullptr)
@@ -2153,6 +2424,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a
 		cond_net = inst_mux->GetControl();
 		cond_pol = pwr1;
 	} while (0);
+#endif
 
 	clock_net = net;
 	clock_sig = importer->net_map_at(clock_net);
@@ -2424,114 +2696,226 @@ struct VerificExtNets
 	}
 };
 
-std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top)
+void import_all(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED)
 {
-	verific_sva_fsm_limit = 16;
-
-	std::map<std::string,Netlist*> nl_todo, nl_done;
+#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
+	VerificExtensions::ElaborateAndRewrite(work, parameters);
+	verific_error_msg.clear();
+#endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+	if (!ppfile.empty())
+		veri_file::PrettyPrint(ppfile.c_str(), nullptr, work);
+#endif
 
-	VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1);
-	Array *netlists = NULL;
-	Array veri_libs, vhdl_libs;
+	Array vhdl_libs;
 #ifdef VERIFIC_VHDL_SUPPORT
-	VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1);
+	VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work, 1);
 	if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
 #endif
+	Array veri_libs;
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+	VeriLibrary *veri_lib = veri_file::GetLibrary(work, 1);
 	if (veri_lib) veri_libs.InsertLast(veri_lib);
+#endif
 
-	Map verific_params(STRING_HASH);
-	for (const auto &i : parameters)
-		verific_params.Insert(i.first.c_str(), i.second.c_str());
+#ifdef VERIFIC_HIER_TREE_SUPPORT
+	if (show_message)
+		log("Running hier_tree::ElaborateAll().\n");
+	Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, parameters);
+	Netlist *nl;
+	int i;
 
-#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-	VerificExtensions::ElaborateAndRewrite("work", &verific_params);
-	verific_error_msg.clear();
+	FOREACH_ARRAY_ITEM(netlists, i, nl)
+		nl_todo->emplace(nl->CellBaseName(), nl);
+	delete netlists;
+#else
+	if (parameters->Size())
+		log_warning("Please note that parameters are not propagated during import.\n");
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+	if (show_message)
+		log("Running veri_file::ElaborateAll().\n");
+	veri_file::ElaborateAll(work);
 #endif
-
-	if (top.empty()) {
-		netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
+#ifdef VERIFIC_VHDL_SUPPORT
+	if (show_message)
+		log("Running vhdl_file::ElaborateAll().\n");
+	vhdl_file::ElaborateAll(work);
+#endif
+	MapIter mi ;
+	Verific::Cell *c ;
+	MapIter it ;
+	Library *l ;
+	FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) {
+		if (l == Library::Primitives() || l == Library::Operators()) continue;
+		FOREACH_CELL_OF_LIBRARY(l,mi,c) {
+			MapIter ni ;
+			Netlist *nl;
+			FOREACH_NETLIST_OF_CELL(c, ni, nl) {
+				if (nl)
+					nl_todo->emplace(nl->CellBaseName(), nl);
+			}
+		}
 	}
-	else {
-		Array veri_modules, vhdl_units;
+#endif
+}
+
+std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED, std::vector<std::string> &tops)
+{
+	std::set<std::string> top_mod_names;
+	Array *netlists = nullptr;
+
+#ifdef VERIFIC_VHDL_SUPPORT
+	VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work, 1);
+#endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+	VeriLibrary* veri_lib = veri_file::GetLibrary(work, 1);
+#endif
 
-		if (veri_lib) {
-			VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1);
+#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
+	for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
+#endif
+	{
+		Array vhdl_units;
+		Array veri_modules;
+		for (std::string n : tops)
+		{
+			const char *name = n.c_str();
+			top_mod_names.insert(name);
+
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+			VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
 			if (veri_module) {
-				veri_modules.InsertLast(veri_module);
 				if (veri_module->IsConfiguration()) {
+					if (show_message)
+						log("Adding Verilog configuration '%s' to elaboration queue.\n", name);
+					veri_modules.InsertLast(veri_module);
+					top_mod_names.erase(name);
 					VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
-					VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast();
-					VeriLibrary *lib = veri_module->GetLibrary() ;
-					if (module_name && module_name->IsHierName()) {
-						VeriName *prefix = module_name->GetPrefix() ;
-						const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
-						if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
+					VeriName *module_name;
+					int i;
+					FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) {
+						VeriLibrary *lib = veri_module->GetLibrary() ;
+						if (module_name && module_name->IsHierName()) {
+							VeriName *prefix = module_name->GetPrefix() ;
+							const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
+							if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ;
+						}
+						if (lib && module_name)
+							top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName());
 					}
-					if (lib && module_name)
-						top = lib->GetModule(module_name->GetName(), 1)->GetName();
+				} else {
+					if (show_message)
+						log("Adding Verilog module '%s' to elaboration queue.\n", name);
+					veri_modules.InsertLast(veri_module);
 				}
+			continue;
 			}
-
-			// Also elaborate all root modules since they may contain bind statements
-			MapIter mi;
-			FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
-				if (!veri_module->IsRootModule()) continue;
-				veri_modules.InsertLast(veri_module);
+#endif
+#ifdef VERIFIC_VHDL_SUPPORT
+			VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr;
+			if (vhdl_unit) {
+				if (show_message)
+					log("Adding VHDL unit '%s' to elaboration queue.\n", name);
+				vhdl_units.InsertLast(vhdl_unit);
+				continue;
 			}
+#endif
+			log_error("Can't find module/unit '%s'.\n", name);
 		}
 
-#ifdef VERIFIC_VHDL_SUPPORT
-		if (vhdl_lib) {
-			VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str());
-			if (vhdl_unit)
-				vhdl_units.InsertLast(vhdl_unit);
+#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
+		if (static_elaborate) {
+			VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, parameters);
+			verific_error_msg.clear();
+#endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+			if (!ppfile.empty())
+				veri_file::PrettyPrint(ppfile.c_str(), nullptr, work);
+#endif
+#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
+			continue;
 		}
 #endif
-		netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+		const char *lib_name = nullptr;
+		SetIter si;
+		FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) {
+			VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0);
+			if (veri_lib) {
+				// Also elaborate all root modules since they may contain bind statements
+				MapIter mi;
+				VeriModule *veri_module;
+				FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
+					if (!veri_module->IsRootModule()) continue;
+					veri_modules.InsertLast(veri_module);
+				}
+			}
+		}
+#endif
+#ifdef VERIFIC_HIER_TREE_SUPPORT
+		if (show_message)
+			log("Running hier_tree::Elaborate().\n");
+		netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, parameters);
+#else
+#if defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && !defined(VERIFIC_VHDL_SUPPORT)
+		if (show_message)
+			log("Running veri_file::ElaborateMultipleTop().\n");
+		// SystemVerilog support only
+		netlists = veri_file::ElaborateMultipleTop(&veri_modules, parameters);
+#elif defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT)
+		if (show_message)
+			log("Running vhdl_file::Elaborate().\n");
+		// VHDL support	only
+		netlists = new Array(top_mod_names.size());
+		for (auto &name : top_mod_names) {
+			vhdl_file::Elaborate(name.c_str(), work, 0, parameters);
+			netlists->InsertLast(Netlist::PresentDesign());
+		}
+#elif defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && defined(VERIFIC_VHDL_SUPPORT)
+		// Both SystemVerilog and VHDL support
+		if (veri_modules.Size()>0) {
+			if (show_message)
+				log("Running veri_file::ElaborateMultipleTop().\n");
+			netlists = veri_file::ElaborateMultipleTop(&veri_modules, parameters);
+		} else
+			netlists = new Array(1);
+		if (vhdl_units.Size()>0) {
+			if (show_message)
+				log("Running vhdl_file::Elaborate().\n");
+			for (auto &name : top_mod_names) {
+				vhdl_file::Elaborate(name.c_str(), work, 0, parameters);
+				netlists->InsertLast(Netlist::PresentDesign());
+			}
+		}
+#else
+#endif
+#endif
 	}
-
 	Netlist *nl;
 	int i;
-	std::string cell_name = top;
 
 	FOREACH_ARRAY_ITEM(netlists, i, nl) {
 		if (!nl) continue;
-		if (!top.empty() && nl->CellBaseName() != top)
+		if (!top_mod_names.count(nl->CellBaseName()))
 			continue;
 		nl->AddAtt(new Att(" \\top", NULL));
-		nl_todo.emplace(nl->CellBaseName(), nl);
-		cell_name = nl->Owner()->Name();
+		nl_todo->emplace(nl->CellBaseName(), nl);
 	}
-	if (top.empty()) cell_name = top;
-
 	delete netlists;
+	return top_mod_names;
+}
 
-	if (!verific_error_msg.empty())
-		log_error("%s\n", verific_error_msg.c_str());
-
-	for (auto nl : nl_todo)
-		nl.second->ChangePortBusStructures(1 /* hierarchical */);
-
-	VerificExtNets worker;
-	for (auto nl : nl_todo)
-		worker.run(nl.second);
-
-	while (!nl_todo.empty()) {
-		auto it = nl_todo.begin();
-		Netlist *nl = it->second;
-		if (nl_done.count(it->first) == 0) {
-			VerificImporter importer(false, false, false, false, false, false, false);
-			nl_done[it->first] = it->second;
-			importer.import_netlist(design, nl, nl_todo, nl->Owner()->Name() == cell_name);
-		}
-		nl_todo.erase(it);
-	}
-
+void verific_cleanup()
+{
 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
 	VerificExtensions::Reset();
 #endif
+#ifdef VERIFIC_HIER_TREE_SUPPORT
 	hier_tree::DeleteHierarchicalTree();
+#endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	veri_file::Reset();
+#endif
 #ifdef VERIFIC_VHDL_SUPPORT
 	vhdl_file::Reset();
 #endif
@@ -2545,11 +2929,59 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 	Message::Reset();
 	RuntimeFlags::DeleteAllFlags();
 	LineFile::DeleteAllLineFiles();
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	verific_incdirs.clear();
 	verific_libdirs.clear();
 	verific_libexts.clear();
+#endif
 	verific_import_pending = false;
+}
+
+std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top)
+{
+	verific_sva_fsm_limit = 16;
+
+	std::map<std::string,Netlist*> nl_todo, nl_done;
+
+	Map verific_params(STRING_HASH);
+	for (const auto &i : parameters)
+		verific_params.Insert(i.first.c_str(), i.second.c_str());
 
+	std::set<std::string> top_mod_names;
+	if (top.empty()) {
+		import_all("work", &nl_todo, &verific_params, false, "");
+	} else {
+		std::vector<std::string> tops;
+		tops.push_back(top);
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+		veri_file::RemoveAllLOptions();
+		veri_file::AddLOption("work");
+#endif
+		top_mod_names = import_tops("work", &nl_todo, &verific_params, false, "", tops) ;
+	}
+
+	if (!verific_error_msg.empty())
+		log_error("%s\n", verific_error_msg.c_str());
+
+	for (auto nl : nl_todo)
+		nl.second->ChangePortBusStructures(1 /* hierarchical */);
+
+	VerificExtNets worker;
+	for (auto nl : nl_todo)
+		worker.run(nl.second);
+
+	while (!nl_todo.empty()) {
+		auto it = nl_todo.begin();
+		Netlist *nl = it->second;
+		if (nl_done.count(it->first) == 0) {
+			VerificImporter importer(false, false, false, false, false, false, false);
+			nl_done[it->first] = it->second;
+			importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->CellBaseName()));
+		}
+		nl_todo.erase(it);
+	}
+
+	verific_cleanup();
 	if (!verific_error_msg.empty())
 		log_error("%s\n", verific_error_msg.c_str());
 	return top;
@@ -2578,6 +3010,7 @@ struct VerificPass : public Pass {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		log("    verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..\n");
 		log("\n");
 		log("Load the specified Verilog/SystemVerilog files into Verific.\n");
@@ -2596,8 +3029,9 @@ struct VerificPass : public Pass {
 		log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
 		log("\n");
 		log("\n");
+#endif
 #ifdef VERIFIC_VHDL_SUPPORT
-		log("    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
+		log("    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl2019|-vhdl} <vhdl-file>..\n");
 		log("\n");
 		log("Load the specified VHDL files into Verific.\n");
 		log("\n");
@@ -2622,6 +3056,7 @@ struct VerificPass : public Pass {
 		log("\n");
 		log("\n");
 #endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		log("    verific {-f|-F} [-vlog95|-vlog2k|-sv2005|-sv2009|\n");
 		log("                     -sv2012|-sv|-formal] <command-file>\n");
 		log("\n");
@@ -2655,6 +3090,7 @@ struct VerificPass : public Pass {
 		log("        -sverilog\n");
 		log("\n");
 		log("\n");
+#endif
 		log("    verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>\n");
 		log("\n");
 		log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
@@ -2667,6 +3103,7 @@ struct VerificPass : public Pass {
 		log("(-L may be used more than once)\n");
 		log("\n");
 		log("\n");
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		log("    verific -vlog-incdir <directory>..\n");
 		log("\n");
 		log("Add Verilog include directories.\n");
@@ -2693,6 +3130,7 @@ struct VerificPass : public Pass {
 		log("Remove Verilog defines previously set with -vlog-define.\n");
 		log("\n");
 		log("\n");
+#endif
 		log("    verific -set-error <msg_id>..\n");
 		log("    verific -set-warning <msg_id>..\n");
 		log("    verific -set-info <msg_id>..\n");
@@ -2724,9 +3162,14 @@ struct VerificPass : public Pass {
 		log("  -extnets\n");
 		log("    Resolve references to external nets by adding module ports as needed.\n");
 		log("\n");
+		log("  -no-split-complex-ports\n");
+		log("    Complex ports (structs or arrays) are not split and remain packed as a single port.\n");
+		log("\n");
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		log("  -autocover\n");
 		log("    Generate automatic cover statements for all asserts\n");
 		log("\n");
+#endif
 		log("  -fullinit\n");
 		log("    Keep all register initializations, even those for non-FF registers.\n");
 		log("\n");
@@ -2759,12 +3202,14 @@ struct VerificPass : public Pass {
 		log("  -V\n");
 		log("    Import Verific netlist as-is without translating to Yosys cell types. \n");
 		log("\n");
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		log("  -nosva\n");
 		log("    Ignore SVA properties, do not infer checker logic.\n");
 		log("\n");
 		log("  -L <int>\n");
 		log("    Maximum number of ctrl bits for SVA checker FSMs (default=16).\n");
 		log("\n");
+#endif
 		log("  -n\n");
 		log("    Keep all Verific names on instances and nets. By default only\n");
 		log("    user-declared names are preserved.\n");
@@ -2888,7 +3333,7 @@ struct VerificPass : public Pass {
 #endif
 
 	msg_type_t prev_1063;
-
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 	void add_modules_to_map(Map &map, std::string work, bool flag_lib)
 	{
 		MapIter mi ;
@@ -2922,6 +3367,7 @@ struct VerificPass : public Pass {
 		if (Message::GetMessageType("VERI-1063")!=prev_1063)
 			Message::SetMessageType("VERI-1063", prev_1063);
 	}
+#endif
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
@@ -2951,10 +3397,14 @@ struct VerificPass : public Pass {
 			RuntimeFlags::SetVar("db_infer_wide_operators", 1);
 			RuntimeFlags::SetVar("db_infer_set_reset_registers", 0);
 
+			// Properly respect order of read and write for rams
+			RuntimeFlags::SetVar("db_change_inplace_ram_blocking_write_before_read", 1);
+
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
 			RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
 			RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
-
+#endif
 #ifdef VERIFIC_VHDL_SUPPORT
 			RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
 			RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
@@ -2967,6 +3417,7 @@ struct VerificPass : public Pass {
 			//RuntimeFlags::SetVar("vhdl_preserve_comments", 1);
 			RuntimeFlags::SetVar("vhdl_preserve_drivers", 1);
 #endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			RuntimeFlags::SetVar("veri_preserve_assignments", 1);
 			RuntimeFlags::SetVar("veri_preserve_comments", 1);
 			RuntimeFlags::SetVar("veri_preserve_drivers", 1);
@@ -2979,7 +3430,7 @@ struct VerificPass : public Pass {
 
 			// https://github.com/YosysHQ/yosys/issues/1055
 			RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ;
-
+#endif
 			RuntimeFlags::SetVar("verific_produce_verbose_syntax_error_message", 1);
 
 #ifndef DB_PRESERVE_INITIAL_VALUE
@@ -3008,8 +3459,10 @@ struct VerificPass : public Pass {
 		int argidx = 1;
 		std::string work = "work";
 		bool is_work_set = false;
+		(void)is_work_set;
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		veri_file::RegisterCallBackVerificStream(&verific_read_cb);
-
+#endif
 		if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" ||
 				args[argidx] == "-set-info" || args[argidx] == "-set-ignore"))
 		{
@@ -3043,6 +3496,7 @@ struct VerificPass : public Pass {
 			goto check_error;
 		}
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		if (GetSize(args) > argidx && args[argidx] == "-vlog-incdir") {
 			for (argidx++; argidx < GetSize(args); argidx++)
 				verific_incdirs.push_back(args[argidx]);
@@ -3085,18 +3539,38 @@ struct VerificPass : public Pass {
 		}
 
 		veri_file::RemoveAllLOptions();
-		veri_file::AddLOption("work");
+#endif
 		for (int i = argidx; i < GetSize(args); i++)
 		{
 			if (args[i] == "-work" && i+1 < GetSize(args)) {
+				work = args[++i];
+				is_work_set = true;
+				continue;
+			}
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+			if (args[i] == "-L" && i+1 < GetSize(args)) {
 				++i;
 				continue;
 			}
+#endif
+			break;
+		}
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+		veri_file::AddLOption(work.c_str());
+#endif
+		for (int i = argidx; i < GetSize(args); i++)
+		{
+			if (args[i] == "-work" && i+1 < GetSize(args)) {
+				++i;
+				continue;
+			}
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			if (args[i] == "-L" && i+1 < GetSize(args)) {
-				if (args[++i] == "work")
+				if (args[++i] == work)
 					veri_file::RemoveAllLOptions();
 				continue;
 			}
+#endif
 			break;
 		}
 		for (; argidx < GetSize(args); argidx++)
@@ -3106,13 +3580,16 @@ struct VerificPass : public Pass {
 				is_work_set = true;
 				continue;
 			}
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			if (args[argidx] == "-L" && argidx+1 < GetSize(args)) {
 				veri_file::AddLOption(args[++argidx].c_str());
 				continue;
 			}
+#endif
 			break;
 		}
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
 		{
 			unsigned verilog_mode = veri_file::UNDEFINED;
@@ -3239,18 +3716,27 @@ struct VerificPass : public Pass {
 					verific_error_msg.clear();
 					log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
 			}
+			char* fn;
+			int i = 0;
+
+			FOREACH_ARRAY_ITEM(&file_names, i, fn) {
+				free(fn);
+			}
 			set_modules_to_blackbox(map, work, flag_lib);
 			verific_import_pending = true;
 			goto check_error;
 		}
+#endif
 
 #ifdef VERIFIC_VHDL_SUPPORT
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl87") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
 			bool flag_lib = false;
-			for (argidx++; argidx < GetSize(args); argidx++) {
+			argidx++;
+			while (argidx < GetSize(args)) {
 				if (args[argidx] == "-lib") {
 					flag_lib = true;
+					argidx++;
 					continue;
 				}
 				if (args[argidx].compare(0, 1, "-") == 0) {
@@ -3271,9 +3757,11 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl93") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
 			bool flag_lib = false;
-			for (argidx++; argidx < GetSize(args); argidx++) {
+			argidx++;
+			while (argidx < GetSize(args)) {
 				if (args[argidx] == "-lib") {
 					flag_lib = true;
+					argidx++;
 					continue;
 				}
 				if (args[argidx].compare(0, 1, "-") == 0) {
@@ -3294,9 +3782,11 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
 			bool flag_lib = false;
-			for (argidx++; argidx < GetSize(args); argidx++) {
+			argidx++;
+			while (argidx < GetSize(args)) {
 				if (args[argidx] == "-lib") {
 					flag_lib = true;
+					argidx++;
 					continue;
 				}
 				if (args[argidx].compare(0, 1, "-") == 0) {
@@ -3314,12 +3804,39 @@ struct VerificPass : public Pass {
 			goto check_error;
 		}
 
+		if (GetSize(args) > argidx && (args[argidx] == "-vhdl2019")) {
+			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str());
+			bool flag_lib = false;
+			argidx++;
+			while (argidx < GetSize(args)) {
+				if (args[argidx] == "-lib") {
+					flag_lib = true;
+					argidx++;
+					continue;
+				}
+				if (args[argidx].compare(0, 1, "-") == 0) {
+					cmd_error(args, argidx, "unknown option");
+					goto check_error;
+				}
+				Map map(POINTER_HASH);
+				add_units_to_map(map, work, flag_lib);
+				std::string filename = frontent_rewrite(args, argidx, tmp_files);
+				if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2019))
+					log_cmd_error("Reading `%s' in VHDL_2019 mode failed.\n", filename.c_str());
+				set_units_to_blackbox(map, work, flag_lib);
+			}
+			verific_import_pending = true;
+			goto check_error;
+		}
+
 		if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
 			bool flag_lib = false;
-			for (argidx++; argidx < GetSize(args); argidx++) {
+			argidx++;
+			while (argidx < GetSize(args)) {
 				if (args[argidx] == "-lib") {
 					flag_lib = true;
+					argidx++;
 					continue;
 				}
 				if (args[argidx].compare(0, 1, "-") == 0) {
@@ -3428,8 +3945,10 @@ struct VerificPass : public Pass {
 #else
 				goto check_error;
 #endif
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			else
 				veri_file::PrettyPrint(filename, module, work.c_str());
+#endif
 			goto check_error;
 		}
 
@@ -3440,6 +3959,7 @@ struct VerificPass : public Pass {
 			bool mode_nosva = false, mode_names = false, mode_verific = false;
 			bool mode_autocover = false, mode_fullinit = false;
 			bool flatten = false, extnets = false, mode_cells = false;
+			bool split_complex_ports = true;
 			string dumpfile;
 			string ppfile;
 			Map parameters(STRING_HASH);
@@ -3457,6 +3977,10 @@ struct VerificPass : public Pass {
 					flatten = true;
 					continue;
 				}
+				if (args[argidx] == "-no-split-complex-ports") {
+					split_complex_ports = false;
+					continue;
+				}
 				if (args[argidx] == "-extnets") {
 					extnets = true;
 					continue;
@@ -3465,6 +3989,7 @@ struct VerificPass : public Pass {
 					mode_keep = true;
 					continue;
 				}
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 				if (args[argidx] == "-nosva") {
 					mode_nosva = true;
 					continue;
@@ -3473,14 +3998,15 @@ struct VerificPass : public Pass {
 					verific_sva_fsm_limit = atoi(args[++argidx].c_str());
 					continue;
 				}
-				if (args[argidx] == "-n") {
-					mode_names = true;
-					continue;
-				}
 				if (args[argidx] == "-autocover") {
 					mode_autocover = true;
 					continue;
 				}
+#endif
+				if (args[argidx] == "-n") {
+					mode_names = true;
+					continue;
+				}
 				if (args[argidx] == "-fullinit") {
 					mode_fullinit = true;
 					continue;
@@ -3526,111 +4052,19 @@ struct VerificPass : public Pass {
 
 			std::set<std::string> top_mod_names;
 
-#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-			VerificExtensions::ElaborateAndRewrite(work, &parameters);
-			verific_error_msg.clear();
-#endif
-			if (!ppfile.empty())
-				veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
-
 			if (mode_all)
 			{
-				log("Running hier_tree::ElaborateAll().\n");
-
-				VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
-
-				Array veri_libs, vhdl_libs;
-#ifdef VERIFIC_VHDL_SUPPORT
-				VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
-				if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
-#endif
-				if (veri_lib) veri_libs.InsertLast(veri_lib);
-
-				Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &parameters);
-				Netlist *nl;
-				int i;
-
-				FOREACH_ARRAY_ITEM(netlists, i, nl)
-					nl_todo.emplace(nl->CellBaseName(), nl);
-				delete netlists;
+				import_all(work.c_str(), &nl_todo, &parameters, true, ppfile);
 			}
 			else
 			{
 				if (argidx == GetSize(args))
 					cmd_error(args, argidx, "No top module specified.\n");
 
-				VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
-#ifdef VERIFIC_VHDL_SUPPORT
-				VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
-#endif
-
-				Array veri_modules, vhdl_units;
-				for (; argidx < GetSize(args); argidx++)
-				{
-					const char *name = args[argidx].c_str();
-					top_mod_names.insert(name);
-
-					VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
-					if (veri_module) {
-						if (veri_module->IsConfiguration()) {
-							log("Adding Verilog configuration '%s' to elaboration queue.\n", name);	
-							veri_modules.InsertLast(veri_module);
-
-							top_mod_names.erase(name);
-
-							VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
-							VeriName *module_name;
-							int i;
-							FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) {
-								VeriLibrary *lib = veri_module->GetLibrary() ;
-								if (module_name && module_name->IsHierName()) {
-									VeriName *prefix = module_name->GetPrefix() ;
-									const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
-									if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
-								}
-								if (lib && module_name)
-									top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName());
-							}
-						} else {
-							log("Adding Verilog module '%s' to elaboration queue.\n", name);
-							veri_modules.InsertLast(veri_module);
-						}
-						continue;
-					}
-#ifdef VERIFIC_VHDL_SUPPORT
-					VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr;
-					if (vhdl_unit) {
-						log("Adding VHDL unit '%s' to elaboration queue.\n", name);
-						vhdl_units.InsertLast(vhdl_unit);
-						continue;
-					}
-#endif
-					log_error("Can't find module/unit '%s'.\n", name);
-				}
-
-				if (veri_lib) {
-					// Also elaborate all root modules since they may contain bind statements
-					MapIter mi;
-					VeriModule *veri_module;
-					FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
-						if (!veri_module->IsRootModule()) continue;
-						veri_modules.InsertLast(veri_module);
-					}
-				}
-
-				log("Running hier_tree::Elaborate().\n");
-				Array *netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);
-				Netlist *nl;
-				int i;
-
-				FOREACH_ARRAY_ITEM(netlists, i, nl) {
-					if (!nl) continue;
-					if (!top_mod_names.count(nl->CellBaseName()))
-						continue;
-					nl->AddAtt(new Att(" \\top", NULL));
-					nl_todo.emplace(nl->CellBaseName(), nl);
-				}
-				delete netlists;
+				std::vector<std::string> tops;
+				for (int i = argidx; i < GetSize(args); i++)
+					tops.push_back(args[i].c_str());
+				top_mod_names = import_tops(work.c_str(), &nl_todo, &parameters, true, ppfile, tops) ;
 			}
 			if (mode_cells) {
 				log("Importing all cells.\n");
@@ -3669,14 +4103,17 @@ struct VerificPass : public Pass {
 					worker.run(nl.second);
 			}
 
-			for (auto nl : nl_todo)
-				nl.second->ChangePortBusStructures(1 /* hierarchical */);
+			if (split_complex_ports) {
+				for (auto nl : nl_todo)
+					nl.second->ChangePortBusStructures(1 /* hierarchical */);
+			}
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			if (!dumpfile.empty()) {
 				VeriWrite veri_writer;
 				veri_writer.WriteFile(dumpfile.c_str(), Netlist::PresentDesign());
 			}
-
+#endif
 			while (!nl_todo.empty()) {
 				auto it = nl_todo.begin();
 				Netlist *nl = it->second;
@@ -3684,33 +4121,12 @@ struct VerificPass : public Pass {
 					VerificImporter importer(mode_gates, mode_keep, mode_nosva,
 							mode_names, mode_verific, mode_autocover, mode_fullinit);
 					nl_done[it->first] = it->second;
-					importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->Owner()->Name()));
+					importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->CellBaseName()));
 				}
 				nl_todo.erase(it);
 			}
 
-#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-			VerificExtensions::Reset();
-#endif
-			hier_tree::DeleteHierarchicalTree();
-			veri_file::Reset();
-#ifdef VERIFIC_VHDL_SUPPORT
-			vhdl_file::Reset();
-#endif
-#ifdef VERIFIC_EDIF_SUPPORT
-			edif_file::Reset();
-#endif
-#ifdef VERIFIC_LIBERTY_SUPPORT
-			synlib_file::Reset();
-#endif
-			Libset::Reset();
-			Message::Reset();
-			RuntimeFlags::DeleteAllFlags();
-			LineFile::DeleteAllLineFiles();
-			verific_incdirs.clear();
-			verific_libdirs.clear();
-			verific_libexts.clear();
-			verific_import_pending = false;
+			verific_cleanup();
 			goto check_error;
 		}
 
@@ -3823,7 +4239,7 @@ struct ReadPass : public Pass {
 		log("\n");
 		log("\n");
 #ifdef VERIFIC_VHDL_SUPPORT
-		log("    read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
+		log("    read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl2019|-vhdl} <vhdl-file>..\n");
 		log("\n");
 		log("Load the specified VHDL files. (Requires Verific.)\n");
 		log("\n");
@@ -3927,7 +4343,7 @@ struct ReadPass : public Pass {
 		}
 
 #ifdef VERIFIC_VHDL_SUPPORT
-		if (args[1] == "-vhdl87" || args[1] == "-vhdl93" || args[1] == "-vhdl2k" || args[1] == "-vhdl2008" || args[1] == "-vhdl") {
+		if (args[1] == "-vhdl87" || args[1] == "-vhdl93" || args[1] == "-vhdl2k" || args[1] == "-vhdl2008" || args[1] == "-vhdl2019" || args[1] == "-vhdl") {
 			if (use_verific) {
 				args[0] = "verific";
 				Pass::call(design, args);
diff --git a/yosys/frontends/verific/verific.h b/yosys/frontends/verific/verific.h
index 44485751c7e..0b9616e1944 100644
--- a/yosys/frontends/verific/verific.h
+++ b/yosys/frontends/verific/verific.h
@@ -83,6 +83,7 @@ struct VerificImporter
 	RTLIL::IdString new_verific_id(Verific::DesignObj *obj);
 	void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj, Verific::Netlist  *nl = nullptr);
 
+	RTLIL::SigBit netToSigBit(Verific::Net *net);
 	RTLIL::SigSpec operatorInput(Verific::Instance *inst);
 	RTLIL::SigSpec operatorInput1(Verific::Instance *inst);
 	RTLIL::SigSpec operatorInput2(Verific::Instance *inst);
diff --git a/yosys/frontends/verific/verificsva.cc b/yosys/frontends/verific/verificsva.cc
index 222c7d2e917..b219c01652b 100644
--- a/yosys/frontends/verific/verificsva.cc
+++ b/yosys/frontends/verific/verificsva.cc
@@ -80,6 +80,7 @@ USING_YOSYS_NAMESPACE
 using namespace Verific;
 #endif
 
+#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 PRIVATE_NAMESPACE_BEGIN
 
 // Non-deterministic FSM
@@ -1878,5 +1879,8 @@ bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net)
 	worker.importer = importer;
 	return worker.net_to_ast_driver(net) != nullptr;
 }
-
+#else
+YOSYS_NAMESPACE_BEGIN
+pool<int> verific_sva_prims = {};
+#endif
 YOSYS_NAMESPACE_END
diff --git a/yosys/frontends/verilog/verilog_frontend.cc b/yosys/frontends/verilog/verilog_frontend.cc
index 9b277c6b977..d363d71fb9a 100644
--- a/yosys/frontends/verilog/verilog_frontend.cc
+++ b/yosys/frontends/verilog/verilog_frontend.cc
@@ -100,6 +100,10 @@ struct VerilogFrontend : public Frontend {
 		log("    -assert-assumes\n");
 		log("        treat all assume() statements like assert() statements\n");
 		log("\n");
+		log("    -nodisplay\n");
+		log("        suppress output from display system tasks ($display et. al).\n");
+		log("        This does not affect the output from a later 'sim' command.\n");
+		log("\n");
 		log("    -debug\n");
 		log("        alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug\n");
 		log("\n");
@@ -235,6 +239,7 @@ struct VerilogFrontend : public Frontend {
 	}
 	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		bool flag_nodisplay = false;
 		bool flag_dump_ast1 = false;
 		bool flag_dump_ast2 = false;
 		bool flag_no_dump_ptr = false;
@@ -265,8 +270,11 @@ struct VerilogFrontend : public Frontend {
 		frontend_verilog_yydebug = false;
 		sv_mode = false;
 		formal_mode = false;
+		noassert_mode = false;
+		noassume_mode = false;
 		norestrict_mode = false;
 		assume_asserts_mode = false;
+		assert_assumes_mode = false;
 		lib_mode = false;
 		specify_mode = false;
 		default_nettype_wire = true;
@@ -308,6 +316,10 @@ struct VerilogFrontend : public Frontend {
 				assert_assumes_mode = true;
 				continue;
 			}
+			if (arg == "-nodisplay") {
+				flag_nodisplay = true;
+				continue;
+			}
 			if (arg == "-debug") {
 				flag_dump_ast1 = true;
 				flag_dump_ast2 = true;
@@ -510,7 +522,7 @@ struct VerilogFrontend : public Frontend {
 		if (flag_nodpi)
 			error_on_dpi_function(current_ast);
 
-		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
+		AST::process(design, current_ast, flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
 				flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
 
 
diff --git a/yosys/frontends/verilog/verilog_lexer.l b/yosys/frontends/verilog/verilog_lexer.l
index 24998666828..8a37343022f 100644
--- a/yosys/frontends/verilog/verilog_lexer.l
+++ b/yosys/frontends/verilog/verilog_lexer.l
@@ -386,7 +386,7 @@ and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 {
 supply0 { return TOK_SUPPLY0; }
 supply1 { return TOK_SUPPLY1; }
 
-"$"(display|write|strobe|monitor|time|stop|finish|dumpfile|dumpvars|dumpon|dumpoff|dumpall) {
+"$"(display[bho]?|write[bho]?|strobe|monitor|time|realtime|stop|finish|dumpfile|dumpvars|dumpon|dumpoff|dumpall) {
 	yylval->string = new std::string(yytext);
 	return TOK_ID;
 }
diff --git a/yosys/frontends/verilog/verilog_parser.y b/yosys/frontends/verilog/verilog_parser.y
index 98bdbf9e5c5..15a04eb2885 100644
--- a/yosys/frontends/verilog/verilog_parser.y
+++ b/yosys/frontends/verilog/verilog_parser.y
@@ -197,9 +197,20 @@ static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
 			range_node = makeRange(type_node->range_left, type_node->range_right, false);
 		}
 	}
-	if (range_node && range_node->children.size() != 2) {
-		frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
+
+	if (range_node) {
+		bool valid = true;
+		if (range_node->type == AST_RANGE) {
+			valid = range_node->children.size() == 2;
+		} else {  // AST_MULTIRANGE
+			for (auto child : range_node->children) {
+				valid = valid && child->children.size() == 2;
+			}
+		}
+		if (!valid)
+			frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form [<expr>:<expr>]");
 	}
+
 	return range_node;
 }
 
@@ -292,6 +303,65 @@ static void rewriteGenForDeclInit(AstNode *loop)
 	substitute(incr);
 }
 
+static void ensureAsgnExprAllowed()
+{
+	if (!sv_mode)
+		frontend_verilog_yyerror("Assignments within expressions are only supported in SystemVerilog mode.");
+	if (ast_stack.back()->type != AST_BLOCK)
+		frontend_verilog_yyerror("Assignments within expressions are only permitted within procedures.");
+}
+
+// add a pre/post-increment/decrement statement
+static const AstNode *addIncOrDecStmt(dict<IdString, AstNode*> *stmt_attr, AstNode *lhs,
+				      dict<IdString, AstNode*> *op_attr, AST::AstNodeType op,
+				      YYLTYPE begin, YYLTYPE end)
+{
+	AstNode *one = AstNode::mkconst_int(1, true);
+	AstNode *rhs = new AstNode(op, lhs->clone(), one);
+	if (op_attr != nullptr)
+		append_attr(rhs, op_attr);
+	AstNode *stmt = new AstNode(AST_ASSIGN_EQ, lhs, rhs);
+	SET_AST_NODE_LOC(stmt, begin, end);
+	if (stmt_attr != nullptr)
+		append_attr(stmt, stmt_attr);
+	ast_stack.back()->children.push_back(stmt);
+	return stmt;
+}
+
+// create a pre/post-increment/decrement expression, and add the corresponding statement
+static AstNode *addIncOrDecExpr(AstNode *lhs, dict<IdString, AstNode*> *attr, AST::AstNodeType op, YYLTYPE begin, YYLTYPE end, bool undo)
+{
+	ensureAsgnExprAllowed();
+	const AstNode *stmt = addIncOrDecStmt(nullptr, lhs, attr, op, begin, end);
+	log_assert(stmt->type == AST_ASSIGN_EQ);
+	AstNode *expr = stmt->children[0]->clone();
+	if (undo) {
+		AstNode *minus_one = AstNode::mkconst_int(-1, true, 1);
+		expr = new AstNode(op, expr, minus_one);
+	}
+	SET_AST_NODE_LOC(expr, begin, end);
+	return expr;
+}
+
+// add a binary operator assignment statement, e.g., a += b
+static const AstNode *addAsgnBinopStmt(dict<IdString, AstNode*> *attr, AstNode *lhs, AST::AstNodeType op, AstNode *rhs, YYLTYPE begin, YYLTYPE end)
+{
+	SET_AST_NODE_LOC(rhs, end, end);
+	if (op == AST_SHIFT_LEFT || op == AST_SHIFT_RIGHT ||
+		op == AST_SHIFT_SLEFT || op == AST_SHIFT_SRIGHT) {
+		rhs = new AstNode(AST_TO_UNSIGNED, rhs);
+		SET_AST_NODE_LOC(rhs, end, end);
+	}
+	rhs = new AstNode(op, lhs->clone(), rhs);
+	AstNode *stmt = new AstNode(AST_ASSIGN_EQ, lhs, rhs);
+	SET_AST_NODE_LOC(rhs, begin, end);
+	SET_AST_NODE_LOC(stmt, begin, end);
+	ast_stack.back()->children.push_back(stmt);
+	if (attr != nullptr)
+		append_attr(stmt, attr);
+	return lhs;
+}
+
 %}
 
 %define api.prefix {frontend_verilog_yy}
@@ -358,7 +428,7 @@ static void rewriteGenForDeclInit(AstNode *loop)
 %type <integer> integer_atom_type integer_vector_type
 %type <al> attr case_attr
 %type <ast> struct_union
-%type <ast_node_type> asgn_binop
+%type <ast_node_type> asgn_binop inc_or_dec_op
 %type <ast> genvar_identifier
 
 %type <specify_target_ptr> specify_target
@@ -613,7 +683,7 @@ module_arg:
 		ast_stack.back()->children.push_back(astbuf2);
 		delete astbuf1; // really only needed if multiple instances of same type.
 	} module_arg_opt_assignment |
-	attr wire_type range TOK_ID {
+	attr wire_type range_or_multirange TOK_ID {
 		AstNode *node = $2;
 		node->str = *$4;
 		SET_AST_NODE_LOC(node, @4, @4);
@@ -1106,7 +1176,7 @@ task_func_args:
 	task_func_port | task_func_args ',' task_func_port;
 
 task_func_port:
-	attr wire_type range {
+	attr wire_type range_or_multirange {
 		bool prev_was_input = true;
 		bool prev_was_output = false;
 		if (albuf) {
@@ -1830,10 +1900,11 @@ struct_member_type: { astbuf1 = new AstNode(AST_STRUCT_ITEM); } member_type_toke
 	;
 
 member_type_token:
-	  member_type 
-	| hierarchical_type_id {
-			addWiretypeNode($1, astbuf1);
-		}
+	member_type range_or_multirange {
+		AstNode *range = checkRange(astbuf1, $2);
+		if (range)
+			astbuf1->children.push_back(range);
+	}
 	| {
 		delete astbuf1;
 	} struct_union {
@@ -1849,7 +1920,8 @@ member_type_token:
 	;
 
 member_type: type_atom type_signing
-	| type_vec type_signing range_or_multirange	{ if ($3) astbuf1->children.push_back($3); }
+	| type_vec type_signing
+	| hierarchical_type_id { addWiretypeNode($1, astbuf1); }
 	;
 
 struct_var_list: struct_var
@@ -1869,7 +1941,7 @@ struct_var: TOK_ID	{	auto *var_node = astbuf2->clone();
 /////////
 
 wire_decl:
-	attr wire_type range {
+	attr wire_type range_or_multirange {
 		albuf = $1;
 		astbuf1 = $2;
 		astbuf2 = checkRange(astbuf1, $3);
@@ -2045,14 +2117,14 @@ type_name: TOK_ID		// first time seen
 	 ;
 
 typedef_decl:
-	TOK_TYPEDEF typedef_base_type range type_name range_or_multirange ';' {
+	TOK_TYPEDEF typedef_base_type range_or_multirange type_name range_or_multirange ';' {
 		astbuf1 = $2;
 		astbuf2 = checkRange(astbuf1, $3);
 		if (astbuf2)
 			astbuf1->children.push_back(astbuf2);
 
 		if ($5 != NULL) {
-			if (!astbuf2) {
+			if (!astbuf2 && !astbuf1->is_custom_type) {
 				addRange(astbuf1, 0, 0, false);
 			}
 			rewriteAsMemoryNode(astbuf1, $5);
@@ -2425,7 +2497,7 @@ assert:
 			delete $5;
 		} else {
 			AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
-			SET_AST_NODE_LOC(node, @1, @6);
+			SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @6);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -2438,7 +2510,7 @@ assert:
 			delete $5;
 		} else {
 			AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
-			SET_AST_NODE_LOC(node, @1, @6);
+			SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @6);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -2451,7 +2523,7 @@ assert:
 			delete $6;
 		} else {
 			AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
-			SET_AST_NODE_LOC(node, @1, @7);
+			SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @7);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -2464,7 +2536,7 @@ assert:
 			delete $6;
 		} else {
 			AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
-			SET_AST_NODE_LOC(node, @1, @7);
+			SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @7);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -2474,7 +2546,7 @@ assert:
 	} |
 	opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
 		AstNode *node = new AstNode(AST_COVER, $5);
-		SET_AST_NODE_LOC(node, @1, @6);
+		SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @6);
 		if ($1 != nullptr) {
 			node->str = *$1;
 			delete $1;
@@ -2483,7 +2555,7 @@ assert:
 	} |
 	opt_sva_label TOK_COVER opt_property '(' ')' ';' {
 		AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
-		SET_AST_NODE_LOC(node, @1, @5);
+		SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @5);
 		if ($1 != nullptr) {
 			node->str = *$1;
 			delete $1;
@@ -2492,7 +2564,7 @@ assert:
 	} |
 	opt_sva_label TOK_COVER ';' {
 		AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
-		SET_AST_NODE_LOC(node, @1, @2);
+		SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @2);
 		if ($1 != nullptr) {
 			node->str = *$1;
 			delete $1;
@@ -2504,7 +2576,7 @@ assert:
 			delete $5;
 		} else {
 			AstNode *node = new AstNode(AST_ASSUME, $5);
-			SET_AST_NODE_LOC(node, @1, @6);
+			SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @6);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -2519,7 +2591,7 @@ assert:
 			delete $6;
 		} else {
 			AstNode *node = new AstNode(AST_FAIR, $6);
-			SET_AST_NODE_LOC(node, @1, @7);
+			SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @7);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -2610,17 +2682,11 @@ simple_behavioral_stmt:
 		SET_AST_NODE_LOC(node, @2, @5);
 		append_attr(node, $1);
 	} |
-	attr lvalue TOK_INCREMENT {
-		AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)));
-		ast_stack.back()->children.push_back(node);
-		SET_AST_NODE_LOC(node, @2, @3);
-		append_attr(node, $1);
+	attr lvalue attr inc_or_dec_op {
+		addIncOrDecStmt($1, $2, $3, $4, @1, @4);
 	} |
-	attr lvalue TOK_DECREMENT {
-		AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_SUB, $2->clone(), AstNode::mkconst_int(1, true)));
-		ast_stack.back()->children.push_back(node);
-		SET_AST_NODE_LOC(node, @2, @3);
-		append_attr(node, $1);
+	attr inc_or_dec_op attr lvalue {
+		addIncOrDecStmt($1, $4, $3, $2, @1, @4);
 	} |
 	attr lvalue OP_LE delay expr {
 		AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5);
@@ -2629,18 +2695,7 @@ simple_behavioral_stmt:
 		append_attr(node, $1);
 	} |
 	attr lvalue asgn_binop delay expr {
-		AstNode *expr_node = $5;
-		if ($3 == AST_SHIFT_LEFT || $3 == AST_SHIFT_RIGHT ||
-			$3 == AST_SHIFT_SLEFT || $3 == AST_SHIFT_SRIGHT) {
-			expr_node = new AstNode(AST_TO_UNSIGNED, expr_node);
-			SET_AST_NODE_LOC(expr_node, @5, @5);
-		}
-		AstNode *op_node = new AstNode($3, $2->clone(), expr_node);
-		AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, op_node);
-		SET_AST_NODE_LOC(op_node, @2, @5);
-		SET_AST_NODE_LOC(node, @2, @5);
-		ast_stack.back()->children.push_back(node);
-		append_attr(node, $1);
+		addAsgnBinopStmt($1, $2, $3, $5, @2, @5);
 	};
 
 asgn_binop:
@@ -2657,6 +2712,12 @@ asgn_binop:
 	TOK_SSHL_ASSIGN { $$ = AST_SHIFT_SLEFT; } |
 	TOK_SSHR_ASSIGN { $$ = AST_SHIFT_SRIGHT; } ;
 
+inc_or_dec_op:
+	// NOTE: These should only be permitted in SV mode, but Yosys has
+	// allowed them in all modes since support for them was added in 2017.
+	TOK_INCREMENT { $$ = AST_ADD; } |
+	TOK_DECREMENT { $$ = AST_SUB; } ;
+
 for_initialization:
 	TOK_ID '=' expr {
 		AstNode *ident = new AstNode(AST_IDENTIFIER);
@@ -2721,6 +2782,7 @@ behavioral_stmt:
 		ast_stack.push_back(node);
 		append_attr(node, $1);
 	} opt_arg_list ';'{
+		SET_AST_NODE_LOC(ast_stack.back(), @2, @5);
 		ast_stack.pop_back();
 	} |
 	attr TOK_MSG_TASKS {
@@ -2731,6 +2793,7 @@ behavioral_stmt:
 		ast_stack.push_back(node);
 		append_attr(node, $1);
 	} opt_arg_list ';'{
+		SET_AST_NODE_LOC(ast_stack.back(), @2, @5);
 		ast_stack.pop_back();
 	} |
 	attr TOK_BEGIN {
@@ -3147,6 +3210,14 @@ expr:
 		$$->children.push_back($6);
 		SET_AST_NODE_LOC($$, @1, @$);
 		append_attr($$, $3);
+	} |
+	inc_or_dec_op attr rvalue {
+		$$ = addIncOrDecExpr($3, $2, $1, @1, @3, false);
+	} |
+	// TODO: Attributes are allowed in the middle here, but they create some
+	// non-trivial conflicts that don't seem worth solving for now.
+	rvalue inc_or_dec_op {
+		$$ = addIncOrDecExpr($1, nullptr, $2, @1, @2, true);
 	};
 
 basic_expr:
@@ -3434,6 +3505,17 @@ basic_expr:
 			frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
 		$$ = new AstNode(AST_CAST_SIZE, $1, $4);
 		SET_AST_NODE_LOC($$, @1, @4);
+	} |
+	'(' expr '=' expr ')' {
+		ensureAsgnExprAllowed();
+		AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $4);
+		ast_stack.back()->children.push_back(node);
+		SET_AST_NODE_LOC(node, @2, @4);
+		$$ = $2->clone();
+	} |
+	'(' expr asgn_binop expr ')' {
+		ensureAsgnExprAllowed();
+		$$ = addAsgnBinopStmt(nullptr, $2, $3, $4, @2, @4)-> clone();
 	};
 
 concat_list:
diff --git a/yosys/guidelines/CodingStyle b/yosys/guidelines/CodingStyle
index ee1e1a2b6a1..8a3df2d62e8 100644
--- a/yosys/guidelines/CodingStyle
+++ b/yosys/guidelines/CodingStyle
@@ -19,7 +19,7 @@ Formatting of code
   blank lines.
 
 - Otherwise stick to the Linux Kernel Coding Style:
-    https://www.kernel.org/doc/Documentation/CodingStyle
+    https://www.kernel.org/doc/Documentation/process/coding-style.rst
 
 
 C++ Language
diff --git a/yosys/guidelines/GettingStarted b/yosys/guidelines/GettingStarted
index d27b285fce4..110f6318518 100644
--- a/yosys/guidelines/GettingStarted
+++ b/yosys/guidelines/GettingStarted
@@ -191,8 +191,8 @@ Example Code
 The following yosys commands are a good starting point if you are looking for examples
 of how to use the Yosys API:
 
-	docs/source/CHAPTER_Prog/stubnets.cc
-	manual/PRESENTATION_Prog/my_cmd.cc
+	docs/source/code_examples/stubnets/stubnets.cc
+	docs/resources/PRESENTATION_Prog/my_cmd.cc
 
 
 Script Passes
diff --git a/yosys/guidelines/Windows b/yosys/guidelines/Windows
index 2af0620fae9..c4548c37cc7 100644
--- a/yosys/guidelines/Windows
+++ b/yosys/guidelines/Windows
@@ -44,7 +44,7 @@ Visual Studio builds are not directly supported by build scripts, but they are s
 
 1. Easy way
 
-  - Go to https://github.com/YosysHQ/yosys/actions/workflows/vs.yml?query=branch%3Amaster
+  - Go to https://github.com/YosysHQ/yosys/actions/workflows/vs.yml?query=branch%3Amain
   - Click on the most recent completed run
   - In Artifacts region find vcxsrc and click on it to download
   - Unpack downloaded ZIP file
diff --git a/yosys/kernel/cellaigs.cc b/yosys/kernel/cellaigs.cc
index 332f821b76c..5dda4503fdd 100644
--- a/yosys/kernel/cellaigs.cc
+++ b/yosys/kernel/cellaigs.cc
@@ -385,17 +385,17 @@ Aig::Aig(Cell *cell)
 		goto optimize;
 	}
 
-	if (cell->type.in({ID($lt), ID($gt), ID($le), ID($ge)}))
+	if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge)))
 	{
 		int width = std::max(GetSize(cell->getPort(ID::A)),
 							 GetSize(cell->getPort(ID::B))) + 1;
 		vector<int> A = mk.inport_vec(ID::A, width);
 		vector<int> B = mk.inport_vec(ID::B, width);
 
-		if (cell->type.in({ID($gt), ID($ge)}))
+		if (cell->type.in(ID($gt), ID($ge)))
 			std::swap(A, B);
 
-		int carry = mk.bool_node(!cell->type.in({ID($le), ID($ge)}));
+		int carry = mk.bool_node(!cell->type.in(ID($le), ID($ge)));
 		for (auto &n : B)
 			n = mk.not_gate(n);
 		vector<int> Y = mk.adder(A, B, carry);
diff --git a/yosys/kernel/celledges.cc b/yosys/kernel/celledges.cc
index c43ba8db330..09cdfd55b96 100644
--- a/yosys/kernel/celledges.cc
+++ b/yosys/kernel/celledges.cc
@@ -172,6 +172,222 @@ void demux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 	}
 }
 
+void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+{
+	bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
+	bool is_b_signed = cell->getParam(ID::B_SIGNED).as_bool();
+	int a_width = GetSize(cell->getPort(ID::A));
+	int b_width = GetSize(cell->getPort(ID::B));
+	int y_width = GetSize(cell->getPort(ID::Y));
+
+	// Behavior of the different shift cells:
+	//
+	//  $shl, $sshl -- shifts left by the amount on B port, B always unsigned
+	//  $shr, $sshr -- ditto right
+	//  $shift, $shiftx -- shifts right by the amount on B port, B optionally signed
+	//
+	// Sign extension (if A signed):
+	//
+	//  $shl, $shr, $shift -- only sign-extends up to size of Y, then shifts in zeroes
+	//  $sshl, $sshr -- fully sign-extends
+	//  $shiftx -- no sign extension
+	//
+	// Because $shl, $sshl only shift left, and $shl sign-extens up to size of Y, they
+	// are effectively the same.
+
+	// the cap below makes sure we don't overflow in the arithmetic further down, though
+	// it makes the edge data invalid once a_width approaches the order of 2**30
+	// (that ever happening is considered improbable)
+	int b_width_capped = min(b_width, 30);
+
+	int b_high, b_low;
+	if (!is_b_signed) {
+		b_high = (1 << b_width_capped) - 1;
+		b_low = 0;
+	} else {
+		b_high = (1 << (b_width_capped - 1)) - 1;
+		b_low = -(1 << (b_width_capped - 1));
+	}
+
+	for (int i = 0; i < y_width; i++){
+		// highest position of Y that can change with the value of B
+		int b_range_upper = 0;
+		// 1 + highest position of A that can be moved to Y[i]
+		int a_range_upper;
+		// lowest position of A that can be moved to Y[i]
+		int a_range_lower;
+
+		if (cell->type.in(ID($shl), ID($sshl))) {
+			b_range_upper = a_width + b_high;
+			if (is_signed) b_range_upper -= 1;
+			a_range_lower = max(0, i - b_high);
+			a_range_upper = min(i+1, a_width);
+		} else if (cell->type.in(ID($shr), ID($sshr)) || (cell->type.in(ID($shift), ID($shiftx)) && !is_b_signed)) {
+			b_range_upper = a_width;
+			a_range_lower = min(i, a_width - 1);
+			a_range_upper = min(i+1 + b_high, a_width);
+		} else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed) {
+			// can go both ways depending on sign of B
+			// 2's complement range is different depending on direction
+			b_range_upper = a_width - b_low;
+			a_range_lower = max(0, i + b_low);
+			if (is_signed)
+				a_range_lower = min(a_range_lower, a_width - 1);
+			a_range_upper = min(i+1 + b_high, a_width);
+		} else {
+			log_assert(false && "unreachable");
+		}
+
+		if (i < b_range_upper) {
+			for (int k = a_range_lower; k < a_range_upper; k++)
+				db->add_edge(cell, ID::A, k, ID::Y, i, -1);
+		} else {
+			// only influence is through sign extension
+			if (is_signed)
+				db->add_edge(cell, ID::A, a_width - 1, ID::Y, i, -1);
+		}
+
+		for (int k = 0; k < b_width; k++) {
+			// left shifts
+			if (cell->type.in(ID($shl), ID($sshl))) {
+				if (a_width == 1 && is_signed) {
+					int skip = 1 << (k + 1);
+					int base = skip -1;
+					if (i % skip != base && i - a_width + 2 < 1 << b_width)
+						db->add_edge(cell, ID::B, k, ID::Y, i, -1);	
+				} else if (is_signed) {
+					if (i - a_width + 2 < 1 << b_width)
+						db->add_edge(cell, ID::B, k, ID::Y, i, -1);
+				} else {
+					if (i - a_width + 1 < 1 << b_width)
+						db->add_edge(cell, ID::B, k, ID::Y, i, -1);
+				}
+			// right shifts
+			} else if (cell->type.in(ID($shr), ID($sshr)) || (cell->type.in(ID($shift), ID($shiftx)) && !is_b_signed)) {
+				if (is_signed) {
+					bool shift_in_bulk = i < a_width - 1;
+					// can we jump into the zero-padding by toggling B[k]?
+					bool zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \
+									&& (((y_width - i) & ~(1 << k)) < (1 << b_width)));
+
+					if (shift_in_bulk || (cell->type.in(ID($shr), ID($shift), ID($shiftx)) && zpad_jump))
+						db->add_edge(cell, ID::B, k, ID::Y, i, -1);
+				} else {
+					if (i < a_width)
+						db->add_edge(cell, ID::B, k, ID::Y, i, -1);
+				}
+			// bidirectional shifts (positive B shifts right, negative left)
+			} else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed) {
+				if (is_signed) {
+					if (k != b_width - 1) {
+						bool r_shift_in_bulk = i < a_width - 1;
+						// assuming B is positive, can we jump into the upper zero-padding by toggling B[k]?
+						bool r_zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \
+											&& (((y_width - i) & ~(1 << k)) <= b_high));
+						// assuming B is negative, can we influence Y[i] by toggling B[k]?
+						bool l = a_width - 2 - i >= b_low;
+						if (a_width == 1) {
+							// in case of a_width==1 we go into more detailed reasoning
+							l = l && (~(i - a_width) & ((1 << (k + 1)) - 1)) != 0;
+						}
+						if (r_shift_in_bulk || r_zpad_jump || l)
+							db->add_edge(cell, ID::B, k, ID::Y, i, -1);
+					} else {
+						if (y_width - i <= b_high || a_width - 2 - i >= b_low)
+							db->add_edge(cell, ID::B, k, ID::Y, i, -1);
+					}
+				} else {
+					if (a_width - 1 - i >= b_low)
+						db->add_edge(cell, ID::B, k, ID::Y, i, -1);
+				}
+			} else {
+				log_assert(false && "unreachable");
+			}
+		}
+	}
+}
+
+void packed_mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+{
+	log_assert(cell->type == ID($mem_v2));
+	Const rd_clk_enable = cell->getParam(ID::RD_CLK_ENABLE);
+	int n_rd_ports = cell->getParam(ID::RD_PORTS).as_int();
+	int abits = cell->getParam(ID::ABITS).as_int();
+	int width = cell->getParam(ID::WIDTH).as_int();
+
+	for (int i = 0; i < n_rd_ports; i++) {
+		if (rd_clk_enable[i] != State::S0) {
+			for (int k = 0; k < width; k++)
+				db->add_edge(cell, ID::RD_ARST, i, ID::RD_DATA, i * width + k, -1);
+			continue;
+		}
+
+		for (int j = 0; j < abits; j++)
+			for (int k = 0; k < width; k++)
+				db->add_edge(cell, ID::RD_ADDR, i * abits + j,
+								   ID::RD_DATA, i * width + k, -1);
+	}
+}
+
+void memrd_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+{
+	log_assert(cell->type.in(ID($memrd), ID($memrd_v2)));
+	int abits = cell->getParam(ID::ABITS).as_int();
+	int width = cell->getParam(ID::WIDTH).as_int();
+
+	if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
+		if (cell->type == ID($memrd_v2)) {
+			for (int k = 0; k < width; k++)
+				db->add_edge(cell, ID::ARST, 0, ID::DATA, k, -1);
+		}
+		return;
+	}
+
+	for (int j = 0; j < abits; j++)
+		for (int k = 0; k < width; k++)
+			db->add_edge(cell, ID::ADDR, j, ID::DATA, k, -1);
+}
+
+void mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+{
+	if (cell->type == ID($mem_v2))
+		packed_mem_op(db, cell);
+	else if (cell->type.in(ID($memrd), ID($memrd_v2)))
+		memrd_op(db, cell);
+	else if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit)))
+		return; /* no edges here */
+	else
+		log_abort();
+}
+
+void ff_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+{
+	int width = cell->getPort(ID::Q).size();
+
+	if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
+		for (int k = 0; k < width; k++) {
+			db->add_edge(cell, ID::D, k, ID::Q, k, -1);
+			db->add_edge(cell, ID::EN, 0, ID::Q, k, -1);
+		}
+	}
+
+	if (cell->hasPort(ID::CLR))
+		for (int k = 0; k < width; k++)
+			db->add_edge(cell, ID::CLR, 0, ID::Q, k, -1);
+	if (cell->hasPort(ID::SET))
+		for (int k = 0; k < width; k++)
+			db->add_edge(cell, ID::SET, 0, ID::Q, k, -1);
+	if (cell->hasPort(ID::ALOAD))
+		for (int k = 0; k < width; k++)
+			db->add_edge(cell, ID::ALOAD, 0, ID::Q, k, -1);
+	if (cell->hasPort(ID::AD))
+		for (int k = 0; k < width; k++)
+			db->add_edge(cell, ID::AD, k, ID::Q, k, -1);
+	if (cell->hasPort(ID::ARST))
+		for (int k = 0; k < width; k++)
+			db->add_edge(cell, ID::ARST, 0, ID::Q, k, -1);
+}
+
 PRIVATE_NAMESPACE_END
 
 bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
@@ -201,11 +417,10 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
 		return true;
 	}
 
-	// FIXME:
-	// if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
-	// 	shift_op(this, cell);
-	// 	return true;
-	// }
+	if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
+		shift_op(this, cell);
+		return true;
+	}
 
 	if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
 		compare_op(this, cell);
@@ -227,8 +442,29 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
 		return true;
 	}
 
+	if (cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit))) {
+		mem_op(this, cell);
+		return true;
+	}
+
+	if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
+		ff_op(this, cell);
+		return true;
+	}
+
 	// FIXME: $mul $div $mod $divfloor $modfloor $slice $concat
 	// FIXME: $lut $sop $alu $lcu $macc $fa
+	// FIXME: $mul $div $mod $divfloor $modfloor $pow $slice $concat $bweqx
+	// FIXME: $lut $sop $alu $lcu $macc $fa $logic_and $logic_or $bwmux
+
+	// FIXME: $_BUF_ $_NOT_ $_AND_ $_NAND_ $_OR_ $_NOR_ $_XOR_ $_XNOR_ $_ANDNOT_ $_ORNOT_
+	// FIXME: $_MUX_ $_NMUX_ $_MUX4_ $_MUX8_ $_MUX16_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
+
+	// FIXME: $specify2 $specify3 $specrule ???
+	// FIXME: $equiv $set_tag $get_tag $overwrite_tag $original_tag
+
+	if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($initstate), ID($anyconst), ID($anyseq), ID($allconst), ID($allseq)))
+		return true; // no-op: these have either no inputs or no outputs
 
 	return false;
 }
diff --git a/yosys/kernel/celltypes.h b/yosys/kernel/celltypes.h
index 63e7408c142..fde6624e179 100644
--- a/yosys/kernel/celltypes.h
+++ b/yosys/kernel/celltypes.h
@@ -101,6 +101,14 @@ struct CellTypes
 		setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
 		setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);
 		setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
+		setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
+		setup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
+		setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});
+		setup_type(ID($get_tag), {ID::A}, {ID::Y});
+		setup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());
+		setup_type(ID($original_tag), {ID::A}, {ID::Y});
+		setup_type(ID($future_ff), {ID::A}, {ID::Y});
+		setup_type(ID($scopeinfo), {}, {});
 	}
 
 	void setup_internals_eval()
diff --git a/yosys/kernel/constids.inc b/yosys/kernel/constids.inc
index 39211d0c753..00db94af441 100644
--- a/yosys/kernel/constids.inc
+++ b/yosys/kernel/constids.inc
@@ -22,6 +22,8 @@ X(always_ff)
 X(always_latch)
 X(anyconst)
 X(anyseq)
+X(ARGS)
+X(ARGS_WIDTH)
 X(ARST)
 X(ARST_POLARITY)
 X(ARST_VALUE)
@@ -86,6 +88,8 @@ X(equiv_merged)
 X(equiv_region)
 X(extract_order)
 X(F)
+X(FLAVOR)
+X(FORMAT)
 X(force_downto)
 X(force_upto)
 X(fsm_encoding)
@@ -137,6 +141,7 @@ X(nomem2reg)
 X(nomeminit)
 X(nosync)
 X(nowrshmsk)
+X(no_ram)
 X(no_rw_check)
 X(O)
 X(OFFSET)
@@ -205,6 +210,7 @@ X(syn_romstyle)
 X(S_WIDTH)
 X(T)
 X(TABLE)
+X(TAG)
 X(techmap_autopurge)
 X(_TECHMAP_BITS_CONNMAP_)
 X(_TECHMAP_CELLNAME_)
@@ -216,6 +222,8 @@ X(_TECHMAP_REPLACE_)
 X(techmap_simplemap)
 X(_techmap_special_)
 X(techmap_wrap)
+X(_TECHMAP_PLACEHOLDER_)
+X(techmap_chtype)
 X(T_FALL_MAX)
 X(T_FALL_MIN)
 X(T_FALL_TYP)
@@ -233,6 +241,10 @@ X(TRANS_NUM)
 X(TRANSPARENCY_MASK)
 X(TRANSPARENT)
 X(TRANS_TABLE)
+X(TRG)
+X(TRG_ENABLE)
+X(TRG_POLARITY)
+X(TRG_WIDTH)
 X(T_RISE_MAX)
 X(T_RISE_MIN)
 X(T_RISE_TYP)
diff --git a/yosys/kernel/driver.cc b/yosys/kernel/driver.cc
index ef8e7792473..79dff7ddabe 100644
--- a/yosys/kernel/driver.cc
+++ b/yosys/kernel/driver.cc
@@ -51,40 +51,58 @@
 
 #if !defined(_WIN32) || defined(__MINGW32__)
 #  include <unistd.h>
-#else
+#endif
+
+USING_YOSYS_NAMESPACE
+
 char *optarg;
-int optind = 1, optcur = 1;
+int optind = 1, optcur = 1, optopt = 0;
 int getopt(int argc, char **argv, const char *optstring)
 {
-	if (optind >= argc || argv[optind][0] != '-')
+	if (optind >= argc)
 		return -1;
 
+	if (argv[optind][0] != '-' || argv[optind][1] == 0) {
+		optopt = 1;
+		optarg = argv[optind++];
+		return optopt;
+	}
+
 	bool takes_arg = false;
-	int opt = argv[optind][optcur];
+	optopt = argv[optind][optcur];
+
+	if (optopt == '-') {
+		++optind;
+		return -1;
+	}
+
 	for (int i = 0; optstring[i]; i++)
-		if (opt == optstring[i] && optstring[i + 1] == ':')
+		if (optopt == optstring[i] && optstring[i + 1] == ':')
 			takes_arg = true;
 
 	if (!takes_arg) {
 		if (argv[optind][++optcur] == 0)
 			optind++, optcur = 1;
-		return opt;
+		return optopt;
 	}
 
 	if (argv[optind][++optcur]) {
 		optarg = argv[optind++] + optcur;
 		optcur = 1;
-		return opt;
+		return optopt;
 	}
 
-	optarg = argv[++optind];
-	optind++, optcur = 1;
-	return opt;
-}
-#endif
+	if (++optind >= argc) {
+		fprintf(stderr, "%s: option '-%c' expects an argument\n", argv[0], optopt);
+		optopt = '?';
+		return optopt;
+	}
 
+	optarg = argv[optind];
+	optind++, optcur = 1;
 
-USING_YOSYS_NAMESPACE
+	return optopt;
+}
 
 #ifdef EMSCRIPTEN
 #  include <sys/stat.h>
@@ -215,6 +233,7 @@ int main(int argc, char **argv)
 	std::string backend_command = "auto";
 	std::vector<std::string> vlog_defines;
 	std::vector<std::string> passes_commands;
+	std::vector<std::string> frontend_files;
 	std::vector<std::string> plugin_filenames;
 	std::string output_filename = "";
 	std::string scriptfile = "";
@@ -231,14 +250,6 @@ int main(int argc, char **argv)
 	bool mode_v = false;
 	bool mode_q = false;
 
-#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE)
-	if (getenv("HOME") != NULL) {
-		yosys_history_file = stringf("%s/.yosys_history", getenv("HOME"));
-		read_history(yosys_history_file.c_str());
-		yosys_history_offset = where_history();
-	}
-#endif
-
 	if (argc == 2 && (!strcmp(argv[1], "-h") || !strcmp(argv[1], "-help") || !strcmp(argv[1], "--help")))
 	{
 		printf("\n");
@@ -345,7 +356,7 @@ int main(int argc, char **argv)
 		printf("    -V\n");
 		printf("        print version information and exit\n");
 		printf("\n");
-		printf("The option -S is an shortcut for calling the \"synth\" command, a default\n");
+		printf("The option -S is a shortcut for calling the \"synth\" command, a default\n");
 		printf("script for transforming the Verilog input to a gate-level netlist. For example:\n");
 		printf("\n");
 		printf("    yosys -o output.blif -S input.v\n");
@@ -509,6 +520,9 @@ int main(int argc, char **argv)
 		case 'C':
 			run_tcl_shell = true;
 			break;
+		case '\001':
+			frontend_files.push_back(optarg);
+			break;
 		default:
 			fprintf(stderr, "Run '%s -h' for help.\n", argv[0]);
 			exit(1);
@@ -523,6 +537,36 @@ int main(int argc, char **argv)
 	if (print_banner)
 		yosys_banner();
 
+#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE)
+	std::string state_dir;
+	#if defined(_WIN32)
+		if (getenv("HOMEDRIVE") != NULL && getenv("HOMEPATH") != NULL) {
+			state_dir = stringf("%s%s/.local/state", getenv("HOMEDRIVE"), getenv("HOMEPATH"));
+		} else {
+			log_debug("$HOMEDRIVE and/or $HOMEPATH is empty. No history file will be created.\n");
+		}
+	#else
+		if (getenv("XDG_STATE_HOME") == NULL || getenv("XDG_STATE_HOME")[0] == '\0') {
+			if (getenv("HOME") != NULL) {
+				state_dir = stringf("%s/.local/state", getenv("HOME"));
+			} else {
+				log_debug("$HOME is empty. No history file will be created.\n");
+			}
+		} else {
+			state_dir = stringf("%s", getenv("XDG_STATE_HOME"));
+		}
+	#endif
+
+	if (!state_dir.empty()) {
+		std::string yosys_dir = state_dir + "/yosys";
+		create_directory(yosys_dir);
+
+		yosys_history_file = yosys_dir + "/history";
+		read_history(yosys_history_file.c_str());
+		yosys_history_offset = where_history();
+	}
+#endif
+
 	if (print_stats)
 		log_hasher = new SHA1;
 
@@ -554,6 +598,8 @@ int main(int argc, char **argv)
 	for (auto &fn : plugin_filenames)
 		load_plugin(fn, {});
 
+	log_suppressed();
+
 	if (!vlog_defines.empty()) {
 		std::string vdef_cmd = "read -define";
 		for (auto vdef : vlog_defines)
@@ -561,17 +607,33 @@ int main(int argc, char **argv)
 		run_pass(vdef_cmd);
 	}
 
-	while (optind < argc)
-		if (run_frontend(argv[optind++], frontend_command))
+	if (scriptfile.empty() || !scriptfile_tcl) {
+		// Without a TCL script, arguments following '--' are also treated as frontend files
+		for (int i = optind; i < argc; ++i)
+			frontend_files.push_back(argv[i]);
+	}
+
+	for (auto it = frontend_files.begin(); it != frontend_files.end(); ++it) {
+		if (run_frontend((*it).c_str(), frontend_command))
 			run_shell = false;
+	}
 
 	if (!topmodule.empty())
 		run_pass("hierarchy -top " + topmodule);
-
 	if (!scriptfile.empty()) {
 		if (scriptfile_tcl) {
 #ifdef YOSYS_ENABLE_TCL
-			if (Tcl_EvalFile(yosys_get_tcl_interp(), scriptfile.c_str()) != TCL_OK)
+			int tcl_argc = argc - optind;
+			std::vector<Tcl_Obj*> script_args;
+			Tcl_Interp *interp = yosys_get_tcl_interp();
+			for (int i = optind; i < argc; ++i)
+				script_args.push_back(Tcl_NewStringObj(argv[i], strlen(argv[i])));
+
+			Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argc", 4), NULL, Tcl_NewIntObj(tcl_argc), 0);
+			Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argv", 4), NULL, Tcl_NewListObj(tcl_argc, script_args.data()), 0);
+			Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argv0", 5), NULL, Tcl_NewStringObj(scriptfile.c_str(), scriptfile.length()), 0);
+
+			if (Tcl_EvalFile(interp, scriptfile.c_str()) != TCL_OK)
 				log_error("TCL interpreter returned an error: %s\n", Tcl_GetStringResult(yosys_get_tcl_interp()));
 #else
 			log_error("Can't exectue TCL script: this version of yosys is not built with TCL support enabled.\n");
diff --git a/yosys/kernel/fmt.cc b/yosys/kernel/fmt.cc
new file mode 100644
index 00000000000..cbf2d12e9ac
--- /dev/null
+++ b/yosys/kernel/fmt.cc
@@ -0,0 +1,880 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2020  whitequark <whitequark@whitequark.org>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "libs/bigint/BigUnsigned.hh"
+#include "kernel/fmt.h"
+
+USING_YOSYS_NAMESPACE
+
+void Fmt::append_literal(const std::string &str) {
+	FmtPart part = {};
+	part.type = FmtPart::LITERAL;
+	part.str = str;
+	parts.push_back(part);
+}
+
+void Fmt::parse_rtlil(const RTLIL::Cell *cell) {
+	std::string fmt = cell->getParam(ID(FORMAT)).decode_string();
+	RTLIL::SigSpec args = cell->getPort(ID(ARGS));
+	parts.clear();
+
+	FmtPart part;
+	for (size_t i = 0; i < fmt.size(); i++) {
+		if (fmt.substr(i, 2) == "}}") {
+			part.str += '}';
+			++i;
+		} else if (fmt.substr(i, 2) == "{{") {
+			part.str += '{';
+			++i;
+		} else if (fmt[i] == '}') {
+			log_assert(false && "Unexpected '}' in format string");
+		} else if (fmt[i] == '{') {
+			if (!part.str.empty()) {
+				part.type = FmtPart::LITERAL;
+				parts.push_back(part);
+				part = {};
+			}
+
+			if (++i == fmt.size())
+				log_assert(false && "Unexpected end in format substitution");
+
+			size_t arg_size = 0;
+			for (; i < fmt.size(); i++) {
+				if (fmt[i] >= '0' && fmt[i] <= '9') {
+					arg_size *= 10;
+					arg_size += fmt[i] - '0';
+				} else if (fmt[i] == ':') {
+					++i;
+					break;
+				} else {
+					log_assert(false && "Unexpected character in format substitution");
+				}
+			}
+			if (i == fmt.size())
+				log_assert(false && "Unexpected end in format substitution");
+
+			if ((size_t)args.size() < arg_size)
+				log_assert(false && "Format part overruns arguments");
+			part.sig = args.extract(0, arg_size);
+			args.remove(0, arg_size);
+
+			if (fmt[i] == 'U') {
+				part.type = FmtPart::UNICHAR;
+				++i;
+				goto success;
+			}
+
+			if (fmt[i] == '>')
+				part.justify = FmtPart::RIGHT;
+			else if (fmt[i] == '<')
+				part.justify = FmtPart::LEFT;
+			else if (fmt[i] == '=')
+				part.justify = FmtPart::NUMERIC;
+			else
+				log_assert(false && "Unexpected justification in format substitution");
+			if (++i == fmt.size())
+				log_assert(false && "Unexpected end in format substitution");
+
+			part.padding = fmt[i];
+			if (++i == fmt.size())
+				log_assert(false && "Unexpected end in format substitution");
+
+			for (; i < fmt.size(); i++) {
+				if (fmt[i] >= '0' && fmt[i] <= '9') {
+					part.width *= 10;
+					part.width += fmt[i] - '0';
+					continue;
+				} else if (fmt[i] == 'b') {
+					part.type = FmtPart::INTEGER;
+					part.base = 2;
+				} else if (fmt[i] == 'o') {
+					part.type = FmtPart::INTEGER;
+					part.base = 8;
+				} else if (fmt[i] == 'd') {
+					part.type = FmtPart::INTEGER;
+					part.base = 10;
+				} else if (fmt[i] == 'h') {
+					part.type = FmtPart::INTEGER;
+					part.base = 16;
+				} else if (fmt[i] == 'H') {
+					part.type = FmtPart::INTEGER;
+					part.base = 16;
+					part.hex_upper = true;
+				} else if (fmt[i] == 'c') {
+					part.type = FmtPart::STRING;
+				} else if (fmt[i] == 't') {
+					part.type = FmtPart::VLOG_TIME;
+				} else if (fmt[i] == 'r') {
+					part.type = FmtPart::VLOG_TIME;
+					part.realtime = true;
+				} else {
+					log_assert(false && "Unexpected character in format substitution");
+				}
+				++i;
+				break;
+			}
+			if (i == fmt.size())
+				log_assert(false && "Unexpected end in format substitution");
+
+			if (part.type == FmtPart::INTEGER) {
+				if (fmt[i] == '-') {
+					part.sign = FmtPart::MINUS;
+					if (++i == fmt.size())
+						log_assert(false && "Unexpected end in format substitution");
+				} else if (fmt[i] == '+') {
+					part.sign = FmtPart::PLUS_MINUS;
+					if (++i == fmt.size())
+						log_assert(false && "Unexpected end in format substitution");
+				} else if (fmt[i] == ' ') {
+					part.sign = FmtPart::SPACE_MINUS;
+					if (++i == fmt.size())
+						log_assert(false && "Unexpected end in format substitution");
+				} else {
+					// also accept no sign character and treat like MINUS for compatibility
+				}
+
+				if (fmt[i] == '#') {
+					part.show_base = true;
+					++i;
+				}
+				if (fmt[i] == '_') {
+					part.group = true;
+					++i;
+				}
+
+				if (fmt[i] == 'u')
+					part.signed_ = false;
+				else if (fmt[i] == 's')
+					part.signed_ = true;
+				else
+					log_assert(false && "Unexpected character in format substitution");
+				if (++i == fmt.size())
+					log_assert(false && "Unexpected end in format substitution");
+			}
+
+		success:
+			if (fmt[i] != '}')
+				log_assert(false && "Expected '}' after format substitution");
+
+			parts.push_back(part);
+			part = {};
+		} else {
+			part.str += fmt[i];
+		}
+	}
+	if (!part.str.empty()) {
+		part.type = FmtPart::LITERAL;
+		parts.push_back(part);
+	}
+}
+
+void Fmt::emit_rtlil(RTLIL::Cell *cell) const {
+	std::string fmt;
+	RTLIL::SigSpec args;
+
+	for (auto &part : parts) {
+		switch (part.type) {
+			case FmtPart::LITERAL:
+				for (char c : part.str) {
+					if (c == '{')
+						fmt += "{{";
+					else if (c == '}')
+						fmt += "}}";
+					else
+						fmt += c;
+				}
+				break;
+
+			case FmtPart::UNICHAR:
+				log_assert(part.sig.size() <= 32);
+				fmt += "{U}";
+				break;
+
+			case FmtPart::VLOG_TIME:
+				log_assert(part.sig.size() == 0);
+				YS_FALLTHROUGH
+			case FmtPart::STRING:
+				log_assert(part.sig.size() % 8 == 0);
+				YS_FALLTHROUGH
+			case FmtPart::INTEGER:
+				args.append(part.sig);
+				fmt += '{';
+				fmt += std::to_string(part.sig.size());
+				fmt += ':';
+				if (part.justify == FmtPart::RIGHT)
+					fmt += '>';
+				else if (part.justify == FmtPart::LEFT)
+					fmt += '<';
+				else if (part.justify == FmtPart::NUMERIC)
+					fmt += '=';
+				else log_abort();
+				log_assert(part.width == 0 || part.padding != '\0');
+				fmt += part.padding != '\0' ? part.padding : ' ';
+				if (part.width > 0)
+					fmt += std::to_string(part.width);
+				if (part.type == FmtPart::INTEGER) {
+					switch (part.base) {
+						case  2: fmt += 'b'; break;
+						case  8: fmt += 'o'; break;
+						case 10: fmt += 'd'; break;
+						case 16: fmt += part.hex_upper ? 'H' : 'h'; break;
+						default: log_abort();
+					}
+					switch (part.sign) {
+						case FmtPart::MINUS:       fmt += '-'; break;
+						case FmtPart::PLUS_MINUS:  fmt += '+'; break;
+						case FmtPart::SPACE_MINUS: fmt += ' '; break;
+					}
+					fmt += part.show_base ? "#" : "";
+					fmt += part.group ? "_" : "";
+					fmt += part.signed_ ? 's' : 'u';
+				} else if (part.type == FmtPart::STRING) {
+					fmt += 'c';
+				} else if (part.type == FmtPart::VLOG_TIME) {
+					if (part.realtime)
+						fmt += 'r';
+					else
+						fmt += 't';
+				} else log_abort();
+				fmt += '}';
+				break;
+
+			default: log_abort();
+		}
+	}
+
+	cell->setParam(ID(FORMAT), fmt);
+	cell->setParam(ID(ARGS_WIDTH), args.size());
+	cell->setPort(ID(ARGS), args);
+}
+
+static size_t compute_required_decimal_places(size_t size, bool signed_)
+{
+	BigUnsigned max;
+	if (!signed_)
+		max.setBit(size, true);
+	else
+		max.setBit(size - 1, true);
+	size_t places = 0;
+	while (!max.isZero()) {
+		places++;
+		max /= 10;
+	}
+	if (signed_)
+		places++;
+	return places;
+}
+
+static size_t compute_required_nondecimal_places(size_t size, unsigned base)
+{
+	log_assert(base != 10);
+	BigUnsigned max;
+	max.setBit(size - 1, true);
+	size_t places = 0;
+	while (!max.isZero()) {
+		places++;
+		max /= base;
+	}
+	return places;
+}
+
+// Only called for integers, either when:
+//
+// (a) passed without a format string (e.g. "$display(a);"), or
+//
+// (b) the corresponding format specifier has no leading zero, e.g. "%b",
+// "%20h", "%-10d".
+//
+// In these cases, for binary/octal/hex, we always zero-pad to the size of the
+// signal; i.e. whether "%h" or "%10h" or "%-20h" is used, if the corresponding
+// signal is 32'h1234, "00001234" will always be a substring of the output.
+//
+// For case (a), we have no specified width, so there is nothing more to do.
+//
+// For case (b), because we are only called with no leading zero on the
+// specifier, any specified width beyond the signal size is therefore space
+// padding, whatever the justification.
+//
+// For decimal, we do no zero-padding, instead space-padding to the size
+// required for the signal's largest value.  This is per other Verilog
+// implementations, and intuitively makes sense as decimal representations lack
+// a discrete mapping of digits to bit groups.  Decimals may also show sign and
+// must accommodate this, whereas other representations do not.
+void Fmt::apply_verilog_automatic_sizing_and_add(FmtPart &part)
+{
+	if (part.base == 10) {
+		size_t places = compute_required_decimal_places(part.sig.size(), part.signed_);
+		part.padding = ' ';
+		part.width = std::max(part.width, places);
+		parts.push_back(part);
+		return;
+	}
+
+	part.padding = '0';
+
+	size_t places = compute_required_nondecimal_places(part.sig.size(), part.base);
+	if (part.width < places) {
+		part.justify = FmtPart::RIGHT;
+		part.width = places;
+		parts.push_back(part);
+	} else if (part.width == places) {
+		parts.push_back(part);
+	} else if (part.width > places) {
+		auto gap = std::string(part.width - places, ' ');
+		part.width = places;
+
+		if (part.justify == FmtPart::RIGHT) {
+			append_literal(gap);
+			parts.push_back(part);
+		} else {
+			part.justify = FmtPart::RIGHT;
+			parts.push_back(part);
+			append_literal(gap);
+		}
+	}
+}
+
+void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name)
+{
+	parts.clear();
+
+	auto arg = args.begin();
+	for (; arg != args.end(); ++arg) {
+		switch (arg->type) {
+			case VerilogFmtArg::INTEGER: {
+				FmtPart part = {};
+				part.type = FmtPart::INTEGER;
+				part.sig = arg->sig;
+				part.base = default_base;
+				part.signed_ = arg->signed_;
+				apply_verilog_automatic_sizing_and_add(part);
+				break;
+			}
+
+			case VerilogFmtArg::TIME: {
+				FmtPart part = {};
+				part.type = FmtPart::VLOG_TIME;
+				part.realtime = arg->realtime;
+				part.padding = ' ';
+				part.width = 20;
+				parts.push_back(part);
+				break;
+			}
+
+			case VerilogFmtArg::STRING: {
+				if (arg == args.begin() || !sformat_like) {
+					const auto fmtarg = arg;
+					const std::string &fmt = fmtarg->str;
+					FmtPart part = {};
+					for (size_t i = 0; i < fmt.size(); i++) {
+						if (fmt[i] != '%') {
+							part.str += fmt[i];
+						} else if (fmt.substr(i, 2) == "%%") {
+							i++;
+							part.str += '%';
+						} else if (fmt.substr(i, 2) == "%l" || fmt.substr(i, 2) == "%L") {
+							i++;
+							part.str += module_name.str();
+						} else if (fmt.substr(i, 2) == "%m" || fmt.substr(i, 2) == "%M") {
+							i++;
+							part.str += module_name.str();
+						} else {
+							if (!part.str.empty()) {
+								part.type = FmtPart::LITERAL;
+								parts.push_back(part);
+								part = {};
+							}
+							if (++i == fmt.size()) {
+								log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1);
+							}
+
+							if (++arg == args.end()) {
+								log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with fewer arguments than the format specifiers in argument %zu require.\n", task_name.c_str(), fmtarg - args.begin() + 1);
+							}
+							part.sig = arg->sig;
+							part.signed_ = arg->signed_;
+
+							for (; i < fmt.size(); i++) {
+								if (fmt[i] == '-') {
+									// left justify; not in IEEE 1800-2017 or verilator but iverilog has it
+									part.justify = FmtPart::LEFT;
+								} else if (fmt[i] == '+') {
+									// always show sign; not in IEEE 1800-2017 or verilator but iverilog has it
+									part.sign = FmtPart::PLUS_MINUS;
+								} else break;
+							}
+							if (i == fmt.size()) {
+								log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1);
+							}
+
+							bool has_leading_zero = false, has_width = false;
+							for (; i < fmt.size(); i++) {
+								if (fmt[i] >= '0' && fmt[i] <= '9') {
+									if (fmt[i] == '0' && !has_width) {
+										has_leading_zero = true;
+									} else {
+										has_width = true;
+										part.width *= 10;
+										part.width += fmt[i] - '0';
+									}
+									continue;
+								} else if (fmt[i] == 'b' || fmt[i] == 'B') {
+									part.type = FmtPart::INTEGER;
+									part.base =  2;
+								} else if (fmt[i] == 'o' || fmt[i] == 'O') {
+									part.type = FmtPart::INTEGER;
+									part.base =  8;
+								} else if (fmt[i] == 'd' || fmt[i] == 'D') {
+									part.type = FmtPart::INTEGER;
+									part.base = 10;
+								} else if (fmt[i] == 'h' || fmt[i] == 'H' ||
+								           fmt[i] == 'x' || fmt[i] == 'X') {
+									// hex digits always printed in lowercase for %h%x as well as %H%X
+									part.type = FmtPart::INTEGER;
+									part.base = 16;
+								} else if (fmt[i] == 'c' || fmt[i] == 'C') {
+									part.type = FmtPart::STRING;
+									part.sig.extend_u0(8);
+									// %10c and %010c not fully defined in IEEE 1800-2017 and do different things in iverilog
+								} else if (fmt[i] == 's' || fmt[i] == 'S') {
+									part.type = FmtPart::STRING;
+									if ((part.sig.size() % 8) != 0)
+										part.sig.extend_u0((part.sig.size() + 7) / 8 * 8);
+									// %10s and %010s not fully defined in IEEE 1800-2017 and do the same thing in iverilog
+									part.padding = ' ';
+								} else if (fmt[i] == 't' || fmt[i] == 'T') {
+									if (arg->type == VerilogFmtArg::TIME) {
+										part.type = FmtPart::VLOG_TIME;
+										part.realtime = arg->realtime;
+										if (!has_width && !has_leading_zero)
+											part.width = 20;
+									} else {
+										log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with format character `%c' in argument %zu, but the argument is not $time or $realtime.\n", task_name.c_str(), fmt[i], fmtarg - args.begin() + 1);
+									}
+								} else {
+									log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with unrecognized format character `%c' in argument %zu.\n", task_name.c_str(), fmt[i], fmtarg - args.begin() + 1);
+								}
+								break;
+							}
+							if (i == fmt.size()) {
+								log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1);
+							}
+
+							if (part.padding == '\0') {
+								if (has_leading_zero && part.justify == FmtPart::RIGHT) {
+									part.padding = '0';
+									part.justify = FmtPart::NUMERIC;
+								} else {
+									part.padding = ' ';
+								}
+							}
+
+							if (part.type == FmtPart::INTEGER && part.base != 10 && part.sign != FmtPart::MINUS)
+								log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with invalid format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1);
+
+							if (part.base != 10)
+								part.signed_ = false;
+							if (part.type == FmtPart::INTEGER && !has_leading_zero)
+								apply_verilog_automatic_sizing_and_add(part);
+							else
+								parts.push_back(part);
+							part = {};
+						}
+					}
+					if (!part.str.empty()) {
+						part.type = FmtPart::LITERAL;
+						parts.push_back(part);
+					}
+				} else {
+					FmtPart part = {};
+					part.type = FmtPart::LITERAL;
+					part.str = arg->str;
+					parts.push_back(part);
+				}
+				break;
+			}
+
+			default: log_abort();
+		}
+	}
+}
+
+std::vector<VerilogFmtArg> Fmt::emit_verilog() const
+{
+	std::vector<VerilogFmtArg> args;
+	VerilogFmtArg fmt = {};
+	fmt.type = VerilogFmtArg::STRING;
+
+	for (auto &part : parts) {
+		switch (part.type) {
+			case FmtPart::LITERAL:
+				for (char c : part.str) {
+					if (c == '%')
+						fmt.str += "%%";
+					else
+						fmt.str += c;
+				}
+				break;
+
+			case FmtPart::INTEGER: {
+				VerilogFmtArg arg = {};
+				arg.type = VerilogFmtArg::INTEGER;
+				arg.sig = part.sig;
+				arg.signed_ = part.signed_;
+				args.push_back(arg);
+
+				fmt.str += '%';
+				if (part.sign == FmtPart::PLUS_MINUS || part.sign == FmtPart::SPACE_MINUS)
+					fmt.str += '+'; // treat space/minus as plus/minus
+				if (part.justify == FmtPart::LEFT)
+					fmt.str += '-';
+				if (part.width == 0) {
+					fmt.str += '0';
+				} else if (part.width > 0) {
+					if (part.base != 10 || part.padding == '0')
+						fmt.str += '0';
+					fmt.str += std::to_string(part.width);
+				}
+				switch (part.base) {
+					case  2: fmt.str += 'b'; break;
+					case  8: fmt.str += 'o'; break;
+					case 10: fmt.str += 'd'; break;
+					case 16: fmt.str += 'h'; break; // treat uppercase hex as lowercase
+					default: log_abort();
+				}
+				break;
+			}
+
+			case FmtPart::STRING: {
+				VerilogFmtArg arg;
+				arg.type = VerilogFmtArg::INTEGER;
+				arg.sig = part.sig;
+				args.push_back(arg);
+
+				fmt.str += '%';
+				if (part.justify == FmtPart::LEFT)
+					fmt.str += '-';
+				if (part.sig.size() == 8) {
+					if (part.width > 0) {
+						if (part.padding == '0')
+							fmt.str += part.padding;
+						fmt.str += std::to_string(part.width);
+					}
+					fmt.str += 'c';
+				} else {
+					log_assert(part.sig.size() % 8 == 0);
+					if (part.width > 0) {
+						fmt.str += std::to_string(part.width);
+					}
+					fmt.str += 's';
+				}
+				break;
+			}
+
+			case FmtPart::UNICHAR: {
+				VerilogFmtArg arg;
+				arg.type = VerilogFmtArg::INTEGER;
+				arg.sig = part.sig.extract(0, 7); // only ASCII
+				args.push_back(arg);
+
+				fmt.str += "%c";
+				break;
+			}
+
+			case FmtPart::VLOG_TIME: {
+				VerilogFmtArg arg;
+				arg.type = VerilogFmtArg::TIME;
+				if (part.realtime)
+					arg.realtime = true;
+				args.push_back(arg);
+
+				fmt.str += '%';
+				log_assert(part.sign == FmtPart::MINUS || part.sign == FmtPart::PLUS_MINUS);
+				if (part.sign == FmtPart::PLUS_MINUS)
+					fmt.str += '+';
+				if (part.justify == FmtPart::LEFT)
+					fmt.str += '-';
+				if (part.padding == '0' && part.width > 0)
+					fmt.str += '0';
+				fmt.str += std::to_string(part.width);
+				fmt.str += 't';
+				break;
+			}
+
+			default: log_abort();
+		}
+	}
+
+	args.insert(args.begin(), fmt);
+	return args;
+}
+
+std::string escape_cxx_string(const std::string &input)
+{
+	std::string output = "\"";
+	for (auto c : input) {
+		if (::isprint(c)) {
+			if (c == '\\')
+				output.push_back('\\');
+			output.push_back(c);
+		} else {
+			char l = c & 0xf, h = (c >> 4) & 0xf;
+			output.append("\\x");
+			output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
+			output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
+		}
+	}
+	output.push_back('"');
+	if (output.find('\0') != std::string::npos) {
+		output.insert(0, "std::string {");
+		output.append(stringf(", %zu}", input.size()));
+	}
+	return output;
+}
+
+void Fmt::emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig, const std::string &context) const
+{
+	os << indent << "std::string buf;\n";
+	for (auto &part : parts) {
+		os << indent << "buf += fmt_part { ";
+		os << "fmt_part::";
+		switch (part.type) {
+			case FmtPart::LITERAL:   os << "LITERAL";   break;
+			case FmtPart::INTEGER:   os << "INTEGER";   break;
+			case FmtPart::STRING:    os << "STRING";    break;
+			case FmtPart::UNICHAR:   os << "UNICHAR";   break;
+			case FmtPart::VLOG_TIME: os << "VLOG_TIME"; break;
+		}
+		os << ", ";
+		os << escape_cxx_string(part.str) << ", ";
+		os << "fmt_part::";
+		switch (part.justify) {
+			case FmtPart::LEFT:    os << "LEFT";    break;
+			case FmtPart::RIGHT:   os << "RIGHT";   break;
+			case FmtPart::NUMERIC: os << "NUMERIC"; break;
+		}
+		os << ", ";
+		os << "(char)" << (int)part.padding << ", ";
+		os << part.width << ", ";
+		os << part.base << ", ";
+		os << part.signed_ << ", ";
+		os << "fmt_part::";
+		switch (part.sign) {
+			case FmtPart::MINUS:       os << "MINUS";       break;
+			case FmtPart::PLUS_MINUS:  os << "PLUS_MINUS";  break;
+			case FmtPart::SPACE_MINUS: os << "SPACE_MINUS"; break;
+		}
+		os << ", ";
+		os << part.hex_upper << ", ";
+		os << part.show_base << ", ";
+		os << part.group << ", ";
+		os << part.realtime;
+		os << " }.render(";
+		emit_sig(part.sig);
+		os << ", " << context << ");\n";
+	}
+	os << indent << "return buf;\n";
+}
+
+std::string Fmt::render() const
+{
+	std::string str;
+
+	for (auto &part : parts) {
+		switch (part.type) {
+			case FmtPart::LITERAL:
+				str += part.str;
+				break;
+
+			case FmtPart::UNICHAR: {
+				RTLIL::Const value = part.sig.as_const();
+				uint32_t codepoint = value.as_int();
+				if (codepoint >= 0x10000)
+					str += (char)(0xf0 |  (codepoint >> 18));
+				else if (codepoint >= 0x800)
+					str += (char)(0xe0 |  (codepoint >> 12));
+				else if (codepoint >= 0x80)
+					str += (char)(0xc0 |  (codepoint >>  6));
+				else
+					str += (char)codepoint;
+				if (codepoint >= 0x10000)
+					str += (char)(0x80 | ((codepoint >> 12) & 0x3f));
+				if (codepoint >= 0x800)
+					str += (char)(0x80 | ((codepoint >>  6) & 0x3f));
+				if (codepoint >= 0x80)
+					str += (char)(0x80 | ((codepoint >>  0) & 0x3f));
+				break;
+			}
+
+			case FmtPart::INTEGER:
+			case FmtPart::STRING:
+			case FmtPart::VLOG_TIME: {
+				std::string buf;
+				std::string prefix;
+				if (part.type == FmtPart::INTEGER) {
+					RTLIL::Const value = part.sig.as_const();
+					bool has_x = false, all_x = true, has_z = false, all_z = true;
+					for (State bit : value) {
+						if (bit == State::Sx)
+							has_x = true;
+						else
+							all_x = false;
+						if (bit == State::Sz)
+							has_z = true;
+						else
+							all_z = false;
+					}
+
+					if (!has_z && !has_x && part.signed_ && value[value.size() - 1]) {
+						prefix = "-";
+						value = RTLIL::const_neg(value, {}, part.signed_, {}, value.size() + 1);
+					} else {
+						switch (part.sign) {
+							case FmtPart::MINUS:       break;
+							case FmtPart::PLUS_MINUS:  prefix = "+"; break;
+							case FmtPart::SPACE_MINUS: prefix = " "; break;
+						}
+					}
+
+					if (part.base != 10) {
+						size_t minimum_size = 1;
+						for (size_t index = 0; index < (size_t)value.size(); index++)
+							if (value[index] != State::S0)
+								minimum_size = index + 1;
+						value = value.extract(0, minimum_size);
+					}
+
+					if (part.base == 2) {
+						if (part.show_base)
+							prefix += "0b";
+						for (size_t index = 0; index < (size_t)value.size(); index++) {
+							if (part.group && index > 0 && index % 4 == 0)
+								buf += '_';
+							RTLIL::State bit = value[index];
+							if (bit == State::Sx)
+								buf += 'x';
+							else if (bit == State::Sz)
+								buf += 'z';
+							else if (bit == State::S1)
+								buf += '1';
+							else /* if (bit == State::S0) */
+								buf += '0';
+						}
+					} else if (part.base == 8 || part.base == 16) {
+						if (part.show_base)
+							prefix += (part.base == 16) ? (part.hex_upper ? "0X" : "0x") : "0o";
+						size_t step = (part.base == 16) ? 4 : 3;
+						for (size_t index = 0; index < (size_t)value.size(); index += step) {
+							if (part.group && index > 0 && index % (4 * step) == 0)
+								buf += '_';
+							RTLIL::Const subvalue = value.extract(index, min(step, value.size() - index));
+							bool has_x = false, all_x = true, has_z = false, all_z = true;
+							for (State bit : subvalue) {
+								if (bit == State::Sx)
+									has_x = true;
+								else
+									all_x = false;
+								if (bit == State::Sz)
+									has_z = true;
+								else
+									all_z = false;
+							}
+							if (all_x)
+								buf += 'x';
+							else if (all_z)
+								buf += 'z';
+							else if (has_x)
+								buf += 'X';
+							else if (has_z)
+								buf += 'Z';
+							else
+								buf += (part.hex_upper ? "0123456789ABCDEF" : "0123456789abcdef")[subvalue.as_int()];
+						}
+					} else if (part.base == 10) {
+						if (part.show_base)
+							prefix += "0d";
+						if (all_x)
+							buf += 'x';
+						else if (all_z)
+							buf += 'z';
+						else if (has_x)
+							buf += 'X';
+						else if (has_z)
+							buf += 'Z';
+						else {
+							log_assert(value.is_fully_def());
+							if (value.is_fully_zero())
+								buf += '0';
+							size_t index = 0;
+							while (!value.is_fully_zero())	{
+								if (part.group && index > 0 && index % 3 == 0)
+									buf += '_';
+								buf += '0' + RTLIL::const_mod(value, 10, false, false, 4).as_int();
+								value = RTLIL::const_div(value, 10, false, false, value.size());
+								index++;
+							}
+						}
+					} else log_abort();
+					if (part.justify == FmtPart::NUMERIC && part.group && part.padding == '0') {
+						int group_size = part.base == 10 ? 3 : 4;
+						while (prefix.size() + buf.size() < part.width) {
+							if (buf.size() % (group_size + 1) == group_size)
+								buf += '_';
+							buf += '0';
+						}
+					}
+					std::reverse(buf.begin(), buf.end());
+				} else if (part.type == FmtPart::STRING) {
+					buf = part.sig.as_const().decode_string();
+				} else if (part.type == FmtPart::VLOG_TIME) {
+					// We only render() during initial, so time is always zero.
+					buf = "0";
+				}
+
+				log_assert(part.width == 0 || part.padding != '\0');
+				if (prefix.size() + buf.size() < part.width) {
+					size_t pad_width = part.width - prefix.size() - buf.size();
+					switch (part.justify) {
+						case FmtPart::LEFT:
+							str += prefix;
+							str += buf;
+							str += std::string(pad_width, part.padding);
+							break;
+						case FmtPart::RIGHT:
+							str += std::string(pad_width, part.padding);
+							str += prefix;
+							str += buf;
+							break;
+						case FmtPart::NUMERIC:
+							str += prefix;
+							str += std::string(pad_width, part.padding);
+							str += buf;
+							break;
+					}
+				} else {
+					str += prefix;
+					str += buf;
+				}
+				break;
+			}
+		}
+	}
+
+	return str;
+}
diff --git a/yosys/kernel/fmt.h b/yosys/kernel/fmt.h
new file mode 100644
index 00000000000..2d4b24979b2
--- /dev/null
+++ b/yosys/kernel/fmt.h
@@ -0,0 +1,116 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2020  whitequark <whitequark@whitequark.org>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef FMT_H
+#define FMT_H
+
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+// Verilog format argument, such as the arguments in:
+//   $display("foo %d bar %01x", 4'b0, $signed(2'b11))
+struct VerilogFmtArg {
+	enum {
+		STRING  = 0,
+		INTEGER = 1,
+		TIME    = 2,
+	} type;
+
+	// All types
+	std::string filename;
+	unsigned first_line;
+
+	// STRING type
+	std::string str;
+
+	// INTEGER type
+	RTLIL::SigSpec sig;
+	bool signed_ = false;
+
+	// TIME type
+	bool realtime = false;
+};
+
+// RTLIL format part, such as the substitutions in:
+//   "foo {4:> 4du} bar {2:<01hs}"
+// Must be kept in sync with `struct fmt_part` in backends/cxxrtl/runtime/cxxrtl/cxxrtl.h!
+struct FmtPart {
+	enum {
+		LITERAL  	= 0,
+		INTEGER 	= 1,
+		STRING    = 2,
+		UNICHAR   = 3,
+		VLOG_TIME = 4,
+	} type;
+
+	// LITERAL type
+	std::string str;
+
+	// INTEGER/STRING/UNICHAR types
+	RTLIL::SigSpec sig;
+
+	// INTEGER/STRING/VLOG_TIME types
+	enum {
+		RIGHT	= 0,
+		LEFT	= 1,
+		NUMERIC	= 2,
+	} justify = RIGHT;
+	char padding = '\0';
+	size_t width = 0;
+
+	// INTEGER type
+	unsigned base = 10;
+	bool signed_ = false;
+	enum {
+		MINUS		= 0,
+		PLUS_MINUS	= 1,
+		SPACE_MINUS	= 2,
+	} sign = MINUS;
+	bool hex_upper = false;
+	bool show_base = false;
+	bool group = false;
+
+	// VLOG_TIME type
+	bool realtime = false;
+};
+
+struct Fmt {
+public:
+	std::vector<FmtPart> parts;
+
+	void append_literal(const std::string &str);
+
+	void parse_rtlil(const RTLIL::Cell *cell);
+	void emit_rtlil(RTLIL::Cell *cell) const;
+
+	void parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name);
+	std::vector<VerilogFmtArg> emit_verilog() const;
+
+	void emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig, const std::string &context) const;
+
+	std::string render() const;
+
+private:
+	void apply_verilog_automatic_sizing_and_add(FmtPart &part);
+};
+
+YOSYS_NAMESPACE_END
+
+#endif
diff --git a/yosys/kernel/hashlib.h b/yosys/kernel/hashlib.h
index b3f99bf730f..e8ddddd3357 100644
--- a/yosys/kernel/hashlib.h
+++ b/yosys/kernel/hashlib.h
@@ -17,6 +17,8 @@
 #include <string>
 #include <vector>
 
+#include <stdint.h>
+
 namespace hashlib {
 
 const int hashtable_size_trigger = 2;
@@ -90,6 +92,12 @@ template<> struct hash_ops<uint32_t> : hash_int_ops
 		return a;
 	}
 };
+template<> struct hash_ops<uint64_t> : hash_int_ops
+{
+	static inline unsigned int hash(uint64_t a) {
+		return mkhash((unsigned int)(a), (unsigned int)(a >> 32));
+	}
+};
 
 template<> struct hash_ops<std::string> {
 	static inline bool cmp(const std::string &a, const std::string &b) {
@@ -365,7 +373,7 @@ class dict
 	}
 
 public:
-	class const_iterator : public std::iterator<std::forward_iterator_tag, std::pair<K, T>>
+	class const_iterator
 	{
 		friend class dict;
 	protected:
@@ -373,6 +381,11 @@ class dict
 		int index;
 		const_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { }
 	public:
+		typedef std::forward_iterator_tag iterator_category;
+		typedef std::pair<K, T> value_type;
+		typedef ptrdiff_t difference_type;
+		typedef std::pair<K, T>* pointer;
+		typedef std::pair<K, T>& reference;
 		const_iterator() { }
 		const_iterator operator++() { index--; return *this; }
 		const_iterator operator+=(int amt) { index -= amt; return *this; }
@@ -383,7 +396,7 @@ class dict
 		const std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }
 	};
 
-	class iterator : public std::iterator<std::forward_iterator_tag, std::pair<K, T>>
+	class iterator
 	{
 		friend class dict;
 	protected:
@@ -391,6 +404,11 @@ class dict
 		int index;
 		iterator(dict *ptr, int index) : ptr(ptr), index(index) { }
 	public:
+		typedef std::forward_iterator_tag iterator_category;
+		typedef std::pair<K, T> value_type;
+		typedef ptrdiff_t difference_type;
+		typedef std::pair<K, T>* pointer;
+		typedef std::pair<K, T>& reference;
 		iterator() { }
 		iterator operator++() { index--; return *this; }
 		iterator operator+=(int amt) { index -= amt; return *this; }
@@ -404,7 +422,7 @@ class dict
 		operator const_iterator() const { return const_iterator(ptr, index); }
 	};
 
-	dict()
+	constexpr dict()
 	{
 	}
 
@@ -794,7 +812,7 @@ class pool
 	}
 
 public:
-	class const_iterator : public std::iterator<std::forward_iterator_tag, K>
+	class const_iterator
 	{
 		friend class pool;
 	protected:
@@ -802,6 +820,11 @@ class pool
 		int index;
 		const_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { }
 	public:
+		typedef std::forward_iterator_tag iterator_category;
+		typedef K value_type;
+		typedef ptrdiff_t difference_type;
+		typedef K* pointer;
+		typedef K& reference;
 		const_iterator() { }
 		const_iterator operator++() { index--; return *this; }
 		bool operator==(const const_iterator &other) const { return index == other.index; }
@@ -810,7 +833,7 @@ class pool
 		const K *operator->() const { return &ptr->entries[index].udata; }
 	};
 
-	class iterator : public std::iterator<std::forward_iterator_tag, K>
+	class iterator
 	{
 		friend class pool;
 	protected:
@@ -818,6 +841,11 @@ class pool
 		int index;
 		iterator(pool *ptr, int index) : ptr(ptr), index(index) { }
 	public:
+		typedef std::forward_iterator_tag iterator_category;
+		typedef K value_type;
+		typedef ptrdiff_t difference_type;
+		typedef K* pointer;
+		typedef K& reference;
 		iterator() { }
 		iterator operator++() { index--; return *this; }
 		bool operator==(const iterator &other) const { return index == other.index; }
@@ -829,7 +857,7 @@ class pool
 		operator const_iterator() const { return const_iterator(ptr, index); }
 	};
 
-	pool()
+	constexpr pool()
 	{
 	}
 
@@ -988,7 +1016,7 @@ class pool
 		return !operator==(other);
 	}
 
-	bool hash() const {
+	unsigned int hash() const {
 		unsigned int hashval = mkhash_init;
 		for (auto &it : entries)
 			hashval ^= ops.hash(it.udata);
@@ -1015,7 +1043,7 @@ class idict
 	pool<K, OPS> database;
 
 public:
-	class const_iterator : public std::iterator<std::forward_iterator_tag, K>
+	class const_iterator
 	{
 		friend class idict;
 	protected:
@@ -1023,6 +1051,11 @@ class idict
 		int index;
 		const_iterator(const idict &container, int index) : container(container), index(index) { }
 	public:
+		typedef std::forward_iterator_tag iterator_category;
+		typedef K value_type;
+		typedef ptrdiff_t difference_type;
+		typedef K* pointer;
+		typedef K& reference;
 		const_iterator() { }
 		const_iterator operator++() { index++; return *this; }
 		bool operator==(const const_iterator &other) const { return index == other.index; }
@@ -1031,6 +1064,10 @@ class idict
 		const K *operator->() const { return &container[index]; }
 	};
 
+	constexpr idict()
+	{
+	}
+
 	int operator()(const K &key)
 	{
 		int hash = database.do_hash(key);
@@ -1101,6 +1138,10 @@ class mfp
 public:
 	typedef typename idict<K, 0, OPS>::const_iterator const_iterator;
 
+	constexpr mfp()
+	{
+	}
+
 	int operator()(const K &key) const
 	{
 		int i = database(key);
diff --git a/yosys/kernel/log.cc b/yosys/kernel/log.cc
index 73e7f16eca5..9a61e8f08b3 100644
--- a/yosys/kernel/log.cc
+++ b/yosys/kernel/log.cc
@@ -59,7 +59,7 @@ bool log_quiet_warnings = false;
 int log_verbose_level;
 string log_last_error;
 void (*log_error_atexit)() = NULL;
-void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg) = NULL;
+void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg) = NULL;
 
 int log_make_debug = 0;
 int log_force_debug = 0;
diff --git a/yosys/kernel/log.h b/yosys/kernel/log.h
index 78a2e434c7a..53aae58c6bc 100644
--- a/yosys/kernel/log.h
+++ b/yosys/kernel/log.h
@@ -17,11 +17,11 @@
  *
  */
 
-#include "kernel/yosys.h"
-
 #ifndef LOG_H
 #define LOG_H
 
+#include "kernel/yosys_common.h"
+
 #include <time.h>
 
 #include <regex>
@@ -131,8 +131,8 @@ void log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(for
 void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
 void log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
 
-void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg));
-extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg);
+void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg));
+extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg);
 
 // Log with filename to report a problem in a source file.
 void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));
@@ -449,4 +449,6 @@ void log_dump_args_worker(const char *p, T first, Args ... args)
 
 YOSYS_NAMESPACE_END
 
+#include "kernel/yosys.h"
+
 #endif
diff --git a/yosys/kernel/mem.cc b/yosys/kernel/mem.cc
index 628f6210499..01c866770f5 100644
--- a/yosys/kernel/mem.cc
+++ b/yosys/kernel/mem.cc
@@ -148,6 +148,9 @@ void Mem::emit() {
 			for (int j = 0; j < (1 << wr_ports[i].wide_log2); j++)
 				wr_port_xlat.push_back(i);
 		for (auto &port : rd_ports) {
+			for (auto attr: port.attributes)
+				if (!cell->has_attribute(attr.first))
+					cell->attributes.insert(attr);
 			if (port.cell) {
 				module->remove(port.cell);
 				port.cell = nullptr;
@@ -210,6 +213,9 @@ void Mem::emit() {
 		cell->setPort(ID::RD_ADDR, rd_addr);
 		cell->setPort(ID::RD_DATA, rd_data);
 		for (auto &port : wr_ports) {
+			for (auto attr: port.attributes)
+				if (!cell->has_attribute(attr.first))
+					cell->attributes.insert(attr);
 			if (port.cell) {
 				module->remove(port.cell);
 				port.cell = nullptr;
@@ -246,6 +252,9 @@ void Mem::emit() {
 		cell->setPort(ID::WR_ADDR, wr_addr);
 		cell->setPort(ID::WR_DATA, wr_data);
 		for (auto &init : inits) {
+			for (auto attr: init.attributes)
+				if (!cell->has_attribute(attr.first))
+					cell->attributes.insert(attr);
 			if (init.cell) {
 				module->remove(init.cell);
 				init.cell = nullptr;
@@ -1252,12 +1261,12 @@ void Mem::prepare_wr_merge(int idx1, int idx2, FfInitVals *initvals) {
 		// If transparent with only one, emulate it, and remove the collision-X
 		// flag that emulate_transparency will set (to align with the other port).
 		if (rport.transparency_mask[idx1]) {
-			emulate_transparency(i, idx1, initvals);
+			emulate_transparency(idx1, i, initvals);
 			rport.collision_x_mask[idx1] = false;
 			continue;
 		}
 		if (rport.transparency_mask[idx2]) {
-			emulate_transparency(i, idx2, initvals);
+			emulate_transparency(idx2, i, initvals);
 			rport.collision_x_mask[idx2] = false;
 			continue;
 		}
diff --git a/yosys/kernel/register.cc b/yosys/kernel/register.cc
index 9ffb17c1a97..80bc44901b2 100644
--- a/yosys/kernel/register.cc
+++ b/yosys/kernel/register.cc
@@ -108,9 +108,8 @@ Pass::Pass(std::string name, std::string short_help) : pass_name(name), short_he
 
 void Pass::run_register()
 {
-	if (pass_register.count(pass_name))
+	if (pass_register.count(pass_name) && !replace_existing_pass())
 		log_error("Unable to register pass '%s', pass already exists!\n", pass_name.c_str());
-
 	pass_register[pass_name] = this;
 }
 
@@ -447,13 +446,12 @@ Frontend::Frontend(std::string name, std::string short_help) :
 
 void Frontend::run_register()
 {
-	if (pass_register.count(pass_name))
+	if (pass_register.count(pass_name) && !replace_existing_pass())
 		log_error("Unable to register pass '%s', pass already exists!\n", pass_name.c_str());
 	pass_register[pass_name] = this;
 
-	if (frontend_register.count(frontend_name))
+	if (frontend_register.count(frontend_name) && !replace_existing_pass())
 		log_error("Unable to register frontend '%s', frontend already exists!\n", frontend_name.c_str());
-
 	frontend_register[frontend_name] = this;
 }
 
@@ -786,9 +784,8 @@ struct HelpPass : public Pass {
 		fprintf(f, ".. raw:: latex\n\n    \\begin{comment}\n\n");
 
 		// render html
-		fprintf(f, ":code:`yosys> help %s`\n", cmd.c_str());
-		fprintf(f, "--------------------------------------------------------------------------------\n\n");
-		fprintf(f, ".. container:: cmdref\n");
+		fprintf(f, ".. cmd:def:: %s\n", cmd.c_str());
+		fprintf(f, "    :title: %s\n\n", title.c_str());
 		std::stringstream ss;
 		std::string textcp = text;
 		ss << text;
@@ -994,4 +991,44 @@ struct MinisatSatSolver : public SatSolver {
 	}
 } MinisatSatSolver;
 
+struct LicensePass : public Pass {
+	LicensePass() : Pass("license", "print license terms") { }
+	void help() override
+	{
+		log("\n");
+		log("    license\n");
+		log("\n");
+		log("This command produces the following notice.\n");
+		notice();
+	}
+	void execute(std::vector<std::string>, RTLIL::Design*) override
+	{
+		notice();
+	}
+	void notice()
+	{
+		log("\n");
+		log(" /----------------------------------------------------------------------------\\\n");
+		log(" |                                                                            |\n");
+		log(" |  yosys -- Yosys Open SYnthesis Suite                                       |\n");
+		log(" |                                                                            |\n");
+		log(" |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |\n");
+		log(" |                                                                            |\n");
+		log(" |  Permission to use, copy, modify, and/or distribute this software for any  |\n");
+		log(" |  purpose with or without fee is hereby granted, provided that the above    |\n");
+		log(" |  copyright notice and this permission notice appear in all copies.         |\n");
+		log(" |                                                                            |\n");
+		log(" |  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |\n");
+		log(" |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |\n");
+		log(" |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |\n");
+		log(" |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |\n");
+		log(" |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |\n");
+		log(" |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |\n");
+		log(" |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |\n");
+		log(" |                                                                            |\n");
+		log(" \\----------------------------------------------------------------------------/\n");
+		log("\n");
+	}
+} LicensePass;
+
 YOSYS_NAMESPACE_END
diff --git a/yosys/kernel/register.h b/yosys/kernel/register.h
index 15750af2a40..25ea9f2321c 100644
--- a/yosys/kernel/register.h
+++ b/yosys/kernel/register.h
@@ -17,11 +17,12 @@
  *
  */
 
-#include "kernel/yosys.h"
-
 #ifndef REGISTER_H
 #define REGISTER_H
 
+#include "kernel/yosys_common.h"
+#include "kernel/yosys.h"
+
 YOSYS_NAMESPACE_BEGIN
 
 struct Pass
@@ -70,6 +71,7 @@ struct Pass
 
 	virtual void on_register();
 	virtual void on_shutdown();
+	virtual bool replace_existing_pass() const { return false; }
 };
 
 struct ScriptPass : Pass
diff --git a/yosys/kernel/rtlil.cc b/yosys/kernel/rtlil.cc
index 7011429ff5a..a6aebaa4258 100644
--- a/yosys/kernel/rtlil.cc
+++ b/yosys/kernel/rtlil.cc
@@ -313,18 +313,33 @@ RTLIL::Const RTLIL::Const::from_string(const std::string &str)
 
 std::string RTLIL::Const::decode_string() const
 {
-	std::string string;
-	string.reserve(GetSize(bits)/8);
-	for (int i = 0; i < GetSize(bits); i += 8) {
+	const int n = GetSize(bits);
+	const int n_over_8 = n / 8;
+	std::string s;
+	s.reserve(n_over_8);
+	int i = n_over_8 * 8;
+	if (i < n) {
 		char ch = 0;
-		for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
-			if (bits[i + j] == RTLIL::State::S1)
+		for (int j = 0; j < (n - i); j++) {
+			if (bits[i + j] == RTLIL::State::S1) {
 				ch |= 1 << j;
+			}
+		}
 		if (ch != 0)
-			string.append({ch});
+			s.append({ch});
 	}
-	std::reverse(string.begin(), string.end());
-	return string;
+	i -= 8;
+	for (; i >= 0; i -= 8) {
+		char ch = 0;
+		for (int j = 0; j < 8; j++) {
+			if (bits[i + j] == RTLIL::State::S1) {
+				ch |= 1 << j;
+			}
+		}
+		if (ch != 0)
+			s.append({ch});
+	}
+	return s;
 }
 
 bool RTLIL::Const::is_fully_zero() const
@@ -1053,6 +1068,12 @@ namespace {
 				error(__LINE__);
 		}
 
+		std::string param_string(const RTLIL::IdString &name)
+		{
+			param(name);
+			return cell->parameters.at(name).decode_string();
+		}
+
 		void port(const RTLIL::IdString& name, int width)
 		{
 			auto it = cell->connections_.find(name);
@@ -1720,6 +1741,43 @@ namespace {
 				return;
 			}
 
+			if (cell->type == ID($print)) {
+				param(ID(FORMAT));
+				param_bool(ID::TRG_ENABLE);
+				param(ID::TRG_POLARITY);
+				param(ID::PRIORITY);
+				port(ID::EN, 1);
+				port(ID::TRG, param(ID::TRG_WIDTH));
+				port(ID::ARGS, param(ID::ARGS_WIDTH));
+				check_expected();
+				return;
+			}
+
+			if (cell->type == ID($check)) {
+				std::string flavor = param_string(ID(FLAVOR));
+				if (!(flavor == "assert" || flavor == "assume" || flavor == "live" || flavor == "fair" || flavor == "cover"))
+					error(__LINE__);
+				param(ID(FORMAT));
+				param_bool(ID::TRG_ENABLE);
+				param(ID::TRG_POLARITY);
+				param(ID::PRIORITY);
+				port(ID::A, 1);
+				port(ID::EN, 1);
+				port(ID::TRG, param(ID::TRG_WIDTH));
+				port(ID::ARGS, param(ID::ARGS_WIDTH));
+				check_expected();
+				return;
+			}
+
+			if (cell->type == ID($scopeinfo)) {
+				param(ID::TYPE);
+				check_expected();
+				std::string scope_type = cell->getParam(ID::TYPE).decode_string();
+				if (scope_type != "module" && scope_type != "struct")
+					error(__LINE__);
+				return;
+			}
+
 			if (cell->type == ID($_BUF_))    { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
 			if (cell->type == ID($_NOT_))    { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
 			if (cell->type == ID($_AND_))    { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
@@ -1816,6 +1874,40 @@ namespace {
 					ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_)))
 				{ port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
 
+			if (cell->type.in(ID($set_tag))) {
+				param(ID::WIDTH);
+				param(ID::TAG);
+				port(ID::A, param(ID::WIDTH));
+				port(ID::SET, param(ID::WIDTH));
+				port(ID::CLR, param(ID::WIDTH));
+				port(ID::Y, param(ID::WIDTH));
+				check_expected();
+				return;
+			}
+			if (cell->type.in(ID($get_tag),ID($original_tag))) {
+				param(ID::WIDTH);
+				param(ID::TAG);
+				port(ID::A, param(ID::WIDTH));
+				port(ID::Y, param(ID::WIDTH));
+				check_expected();
+				return;
+			}
+			if (cell->type.in(ID($overwrite_tag))) {
+				param(ID::WIDTH);
+				param(ID::TAG);
+				port(ID::A, param(ID::WIDTH));
+				port(ID::SET, param(ID::WIDTH));
+				port(ID::CLR, param(ID::WIDTH));
+				check_expected();
+				return;
+			}
+			if (cell->type.in(ID($future_ff))) {
+				param(ID::WIDTH);
+				port(ID::A, param(ID::WIDTH));
+				port(ID::Y, param(ID::WIDTH));
+				check_expected();
+				return;
+			}
 			error(__LINE__);
 		}
 	};
@@ -2096,17 +2188,10 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
 		}
 
 		void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
-			log_assert(GetSize(lhs) == GetSize(rhs));
-			lhs.unpack();
-			rhs.unpack();
-			for (int i = 0; i < GetSize(lhs); i++) {
-				RTLIL::SigBit &lhs_bit = lhs.bits_[i];
-				RTLIL::SigBit &rhs_bit = rhs.bits_[i];
-				if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
-					lhs_bit = State::Sx;
-					rhs_bit = State::Sx;
-				}
-			}
+			// If a deleted wire occurs on the lhs or rhs we just remove that part
+			// of the assignment
+			lhs.remove2(*wires_p, &rhs);
+			rhs.remove2(*wires_p, &lhs);
 		}
 	};
 
@@ -2631,6 +2716,19 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &s
 	return cell;
 }
 
+RTLIL::Cell* RTLIL::Module::addFa(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src)
+{
+	RTLIL::Cell *cell = addCell(name, ID($fa));
+	cell->parameters[ID::WIDTH] = sig_a.size();
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::B, sig_b);
+	cell->setPort(ID::C, sig_c);
+	cell->setPort(ID::X, sig_x);
+	cell->setPort(ID::Y, sig_y);
+	cell->set_src_attribute(src);
+	return cell;
+}
+
 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
 {
 	RTLIL::Cell *cell = addCell(name, ID($slice));
@@ -3234,6 +3332,80 @@ RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string
 	return sig;
 }
 
+RTLIL::SigSpec RTLIL::Module::SetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src)
+{
+	RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size());
+	Cell *cell = addCell(name, ID($set_tag));
+	cell->parameters[ID::WIDTH] = sig_a.size();
+	cell->parameters[ID::TAG] = tag;
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::SET, sig_s);
+	cell->setPort(ID::CLR, sig_c);
+	cell->setPort(ID::Y, sig);
+	cell->set_src_attribute(src);
+	return sig;
+}
+
+RTLIL::Cell* RTLIL::Module::addSetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src)
+{
+	Cell *cell = addCell(name, ID($set_tag));
+	cell->parameters[ID::WIDTH] = sig_a.size();
+	cell->parameters[ID::TAG] = tag;
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::SET, sig_s);
+	cell->setPort(ID::CLR, sig_c);
+	cell->setPort(ID::Y, sig_y);
+	cell->set_src_attribute(src);
+	return cell;
+}
+
+RTLIL::SigSpec RTLIL::Module::GetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src)
+{
+	RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size());
+	Cell *cell = addCell(name, ID($get_tag));
+	cell->parameters[ID::WIDTH] = sig_a.size();
+	cell->parameters[ID::TAG] = tag;
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::Y, sig);
+	cell->set_src_attribute(src);
+	return sig;
+}
+
+RTLIL::Cell* RTLIL::Module::addOverwriteTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src)
+{
+	RTLIL::Cell *cell = addCell(name, ID($overwrite_tag));
+	cell->parameters[ID::WIDTH] = sig_a.size();
+	cell->parameters[ID::TAG] = tag;
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::SET, sig_s);
+	cell->setPort(ID::CLR, sig_c);
+	cell->set_src_attribute(src);
+	return cell;
+}
+
+RTLIL::SigSpec RTLIL::Module::OriginalTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src)
+{
+	RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size());
+	Cell *cell = addCell(name, ID($original_tag));
+	cell->parameters[ID::WIDTH] = sig_a.size();
+	cell->parameters[ID::TAG] = tag;
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::Y, sig);
+	cell->set_src_attribute(src);
+	return sig;
+}
+
+RTLIL::SigSpec RTLIL::Module::FutureFF(RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src)
+{
+	RTLIL::SigSpec sig = addWire(NEW_ID, sig_e.size());
+	Cell *cell = addCell(name, ID($future_ff));
+	cell->parameters[ID::WIDTH] = sig_e.size();
+	cell->setPort(ID::A, sig_e);
+	cell->setPort(ID::Y, sig);
+	cell->set_src_attribute(src);
+	return sig;
+}
+
 RTLIL::Wire::Wire()
 {
 	static unsigned int hashidx_count = 123456789;
@@ -3545,6 +3717,9 @@ RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
 
 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
 {
+	log_assert(offset >= 0);
+	log_assert(length >= 0);
+	log_assert(offset + length <= width);
 	RTLIL::SigChunk ret;
 	if (wire) {
 		ret.wire = wire;
@@ -3911,13 +4086,17 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
 	unpack();
 	other->unpack();
 
+	dict<RTLIL::SigBit, int> pattern_to_with;
 	for (int i = 0; i < GetSize(pattern.bits_); i++) {
 		if (pattern.bits_[i].wire != NULL) {
-			for (int j = 0; j < GetSize(bits_); j++) {
-				if (bits_[j] == pattern.bits_[i]) {
-					other->bits_[j] = with.bits_[i];
-				}
-			}
+			pattern_to_with.emplace(pattern.bits_[i], i);
+		}
+	}
+
+	for (int j = 0; j < GetSize(bits_); j++) {
+		auto it = pattern_to_with.find(bits_[j]);
+		if (it != pattern_to_with.end()) {
+			other->bits_[j] = with.bits_[it->second];
 		}
 	}
 
@@ -4086,6 +4265,34 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
 	check();
 }
 
+void RTLIL::SigSpec::remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other)
+{
+	if (other)
+		cover("kernel.rtlil.sigspec.remove_other");
+	else
+		cover("kernel.rtlil.sigspec.remove");
+
+	unpack();
+
+	if (other != NULL) {
+		log_assert(width_ == other->width_);
+		other->unpack();
+	}
+
+	for (int i = GetSize(bits_) - 1; i >= 0; i--) {
+		if (bits_[i].wire != NULL && pattern.count(bits_[i].wire)) {
+			bits_.erase(bits_.begin() + i);
+			width_--;
+			if (other != NULL) {
+				other->bits_.erase(other->bits_.begin() + i);
+				other->width_--;
+			}
+		}
+	}
+
+	check();
+}
+
 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
 {
 	if (other)
@@ -4225,9 +4432,39 @@ void RTLIL::SigSpec::remove(int offset, int length)
 
 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
 {
-	unpack();
+	log_assert(offset >= 0);
+	log_assert(length >= 0);
+	log_assert(offset + length <= width_);
+
 	cover("kernel.rtlil.sigspec.extract_pos");
-	return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
+
+	if (packed()) {
+		SigSpec extracted;
+		extracted.width_ = length;
+
+		auto it = chunks_.begin();
+		for (; offset; offset -= it->width, it++) {
+			if (offset < it->width) {
+				int chunk_length = min(it->width - offset, length);
+				extracted.chunks_.emplace_back(it->extract(offset, chunk_length));
+				length -= chunk_length;
+				it++;
+				break;
+			}
+		}
+		for (; length; length -= it->width, it++) {
+			if (length >= it->width) {
+				extracted.chunks_.emplace_back(*it);
+			} else {
+				extracted.chunks_.emplace_back(it->extract(0, length));
+				break;
+			}
+		}
+
+		return extracted;
+	} else {
+		return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
+	}
 }
 
 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
diff --git a/yosys/kernel/rtlil.h b/yosys/kernel/rtlil.h
index a69ce480baf..f9da2949508 100644
--- a/yosys/kernel/rtlil.h
+++ b/yosys/kernel/rtlil.h
@@ -17,11 +17,12 @@
  *
  */
 
-#include "kernel/yosys.h"
-
 #ifndef RTLIL_H
 #define RTLIL_H
 
+#include "kernel/yosys_common.h"
+#include "kernel/yosys.h"
+
 YOSYS_NAMESPACE_BEGIN
 
 namespace RTLIL
@@ -308,10 +309,14 @@ namespace RTLIL
 		bool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }
 
 		char operator[](size_t i) const {
-			const char *p = c_str();
+                        const char *p = c_str();
+#ifndef NDEBUG
 			for (; i != 0; i--, p++)
 				log_assert(*p != 0);
 			return *p;
+#else
+			return *(p + i);
+#endif
 		}
 
 		std::string substr(size_t pos = 0, size_t len = std::string::npos) const {
@@ -708,7 +713,7 @@ struct RTLIL::Const
 	inline unsigned int hash() const {
 		unsigned int h = mkhash_init;
 		for (auto b : bits)
-			mkhash(h, b);
+			h = mkhash(h, b);
 		return h;
 	}
 };
@@ -799,8 +804,14 @@ struct RTLIL::SigBit
 	unsigned int hash() const;
 };
 
-struct RTLIL::SigSpecIterator : public std::iterator<std::input_iterator_tag, RTLIL::SigSpec>
+struct RTLIL::SigSpecIterator
 {
+	typedef std::input_iterator_tag iterator_category;
+	typedef RTLIL::SigBit value_type;
+	typedef ptrdiff_t difference_type;
+	typedef RTLIL::SigBit* pointer;
+	typedef RTLIL::SigBit& reference;
+
 	RTLIL::SigSpec *sig_p;
 	int index;
 
@@ -810,8 +821,14 @@ struct RTLIL::SigSpecIterator : public std::iterator<std::input_iterator_tag, RT
 	inline void operator++() { index++; }
 };
 
-struct RTLIL::SigSpecConstIterator : public std::iterator<std::input_iterator_tag, RTLIL::SigSpec>
+struct RTLIL::SigSpecConstIterator
 {
+	typedef std::input_iterator_tag iterator_category;
+	typedef RTLIL::SigBit value_type;
+	typedef ptrdiff_t difference_type;
+	typedef RTLIL::SigBit* pointer;
+	typedef RTLIL::SigBit& reference;
+
 	const RTLIL::SigSpec *sig_p;
 	int index;
 
@@ -908,6 +925,7 @@ struct RTLIL::SigSpec
 	void remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;
 	void remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);
 	void remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);
+	void remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);
 
 	void remove(int offset, int length = 1);
 	void remove_const();
@@ -917,6 +935,9 @@ struct RTLIL::SigSpec
 	RTLIL::SigSpec extract(int offset, int length = 1) const;
 	RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }
 
+	RTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };
+	RTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };
+
 	void append(const RTLIL::SigSpec &signal);
 	inline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }
 	inline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }
@@ -1298,6 +1319,8 @@ struct RTLIL::Module : public RTLIL::AttrObject
 	RTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
 	RTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = "");
 
+	RTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = "");
+
 	RTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
 	RTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
 	RTLIL::Cell* addLogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
@@ -1465,6 +1488,13 @@ struct RTLIL::Module : public RTLIL::AttrObject
 	RTLIL::SigSpec Allseq    (RTLIL::IdString name, int width = 1, const std::string &src = "");
 	RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = "");
 
+	RTLIL::SigSpec SetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = "");
+	RTLIL::Cell*   addSetTag       (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = "");
+	RTLIL::SigSpec GetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = "");
+	RTLIL::Cell*   addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = "");
+	RTLIL::SigSpec OriginalTag     (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = "");
+	RTLIL::SigSpec FutureFF        (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = "");
+
 #ifdef WITH_PYTHON
 	static std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);
 #endif
diff --git a/yosys/kernel/satgen.cc b/yosys/kernel/satgen.cc
index 3a2fa473568..baaf22d1faf 100644
--- a/yosys/kernel/satgen.cc
+++ b/yosys/kernel/satgen.cc
@@ -1379,6 +1379,11 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
+	if (cell->type == ID($scopeinfo))
+	{
+		return true;
+	}
+
 	// Unsupported internal cell types: $pow $fsm $mem*
 	// .. and all sequential cells with asynchronous inputs
 	return false;
diff --git a/yosys/kernel/scopeinfo.cc b/yosys/kernel/scopeinfo.cc
new file mode 100644
index 00000000000..7ed9ebf33f7
--- /dev/null
+++ b/yosys/kernel/scopeinfo.cc
@@ -0,0 +1,129 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/scopeinfo.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+template <typename I, typename Filter> void ModuleHdlnameIndex::index_items(I begin, I end, Filter filter)
+{
+	for (; begin != end; ++begin) {
+		auto const &item = *begin;
+
+		if (!filter(item))
+			continue;
+		std::vector<IdString> path = parse_hdlname(item);
+		if (!path.empty())
+			lookup.emplace(item, tree.insert(path, item));
+	}
+}
+
+void ModuleHdlnameIndex::index()
+{
+	index_wires();
+	index_cells();
+}
+
+void ModuleHdlnameIndex::index_wires()
+{
+	auto wires = module->wires();
+	index_items(wires.begin(), wires.end(), [](Wire *) { return true; });
+}
+
+void ModuleHdlnameIndex::index_cells()
+{
+	auto cells = module->cells();
+	index_items(cells.begin(), cells.end(), [](Cell *) { return true; });
+}
+
+void ModuleHdlnameIndex::index_scopeinfo_cells()
+{
+	auto cells = module->cells();
+	index_items(cells.begin(), cells.end(), [](Cell *cell) { return cell->type == ID($scopeinfo); });
+}
+
+std::vector<std::string> ModuleHdlnameIndex::scope_sources(Cursor cursor)
+{
+	std::vector<std::string> result;
+
+	for (; !cursor.is_root(); cursor = cursor.parent()) {
+		if (!cursor.has_entry()) {
+			result.push_back("");
+			result.push_back("");
+			continue;
+		}
+		Cell *cell = cursor.entry().cell();
+		if (cell == nullptr || cell->type != ID($scopeinfo)) {
+			result.push_back("");
+			result.push_back("");
+			continue;
+		}
+		result.push_back(scopeinfo_get_attribute(cell, ScopeinfoAttrs::Module, ID::src).decode_string());
+		result.push_back(scopeinfo_get_attribute(cell, ScopeinfoAttrs::Cell, ID::src).decode_string());
+	}
+
+	result.push_back(module->get_src_attribute());
+
+	std::reverse(result.begin(), result.end());
+
+	return result;
+}
+
+static const char *attr_prefix(ScopeinfoAttrs attrs)
+{
+	switch (attrs) {
+	case ScopeinfoAttrs::Cell:
+		return "\\cell_";
+	case ScopeinfoAttrs::Module:
+		return "\\module_";
+	default:
+		log_abort();
+	}
+}
+
+bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id)
+{
+	log_assert(scopeinfo->type == ID($scopeinfo));
+	return scopeinfo->has_attribute(attr_prefix(attrs) + RTLIL::unescape_id(id));
+}
+
+RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id)
+{
+	log_assert(scopeinfo->type == ID($scopeinfo));
+	auto found = scopeinfo->attributes.find(attr_prefix(attrs) + RTLIL::unescape_id(id));
+	if (found == scopeinfo->attributes.end())
+		return RTLIL::Const();
+	return found->second;
+}
+
+dict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs)
+{
+	dict<RTLIL::IdString, RTLIL::Const> attributes;
+
+	const char *prefix = attr_prefix(attrs);
+	int prefix_len = strlen(prefix);
+
+	for (auto const &entry : scopeinfo->attributes)
+		if (entry.first.begins_with(prefix))
+			attributes.emplace(RTLIL::escape_id(entry.first.c_str() + prefix_len), entry.second);
+
+	return attributes;
+}
+
+YOSYS_NAMESPACE_END
diff --git a/yosys/kernel/scopeinfo.h b/yosys/kernel/scopeinfo.h
new file mode 100644
index 00000000000..71af70344ce
--- /dev/null
+++ b/yosys/kernel/scopeinfo.h
@@ -0,0 +1,432 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef SCOPEINFO_H
+#define SCOPEINFO_H
+
+#include <vector>
+#include <algorithm>
+
+#include "kernel/yosys.h"
+#include "kernel/celltypes.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+template<typename T>
+class IdTree
+{
+public:
+	struct Cursor;
+
+protected:
+	IdTree *parent = nullptr;
+	IdString scope_name;
+	int depth = 0;
+
+	pool<IdString> names;
+	dict<IdString, T> entries;
+public: // XXX
+	dict<IdString, std::unique_ptr<IdTree>> subtrees;
+
+	template<typename P, typename T_ref>
+	static Cursor do_insert(IdTree *tree, P begin, P end, T_ref &&value)
+	{
+		log_assert(begin != end && "path must be non-empty");
+		while (true) {
+			IdString name = *begin;
+			++begin;
+			log_assert(!name.empty());
+			tree->names.insert(name);
+			if (begin == end) {
+				tree->entries.emplace(name, std::forward<T_ref>(value));
+				return Cursor(tree, name);
+			}
+			auto &unique = tree->subtrees[name];
+			if (!unique) {
+				unique.reset(new IdTree);
+				unique->scope_name = name;
+				unique->parent = tree;
+				unique->depth = tree->depth + 1;
+			}
+			tree = unique.get();
+		}
+	}
+
+public:
+	IdTree() = default;
+	IdTree(const IdTree &) = delete;
+	IdTree(IdTree &&) = delete;
+
+	// A cursor remains valid as long as the (sub-)IdTree it points at is alive
+	struct Cursor
+	{
+		friend class IdTree;
+	protected:
+	public:
+		IdTree *target;
+		IdString scope_name;
+
+		Cursor() : target(nullptr) {}
+		Cursor(IdTree *target, IdString scope_name) : target(target), scope_name(scope_name) {
+			if (scope_name.empty())
+				log_assert(target->parent == nullptr);
+		}
+
+		Cursor do_first_child() {
+			IdTree *tree = nullptr;
+			if (scope_name.empty()) {
+				tree = target;
+			} else {
+				auto found = target->subtrees.find(scope_name);
+				if (found != target->subtrees.end()) {
+					tree = found->second.get();
+				} else {
+					return Cursor();
+				}
+			}
+			if (tree->names.empty()) {
+				return Cursor();
+			}
+			return Cursor(tree, *tree->names.begin());
+		}
+
+		Cursor do_next_sibling() {
+			if (scope_name.empty())
+				return Cursor();
+			auto found = target->names.find(scope_name);
+			if (found == target->names.end())
+				return Cursor();
+			++found;
+			if (found == target->names.end())
+				return Cursor();
+			return Cursor(target, *found);
+		}
+
+		Cursor do_parent() {
+			if (scope_name.empty())
+				return Cursor();
+			if (target->parent != nullptr)
+				return Cursor(target->parent, target->scope_name);
+			return Cursor(target, IdString());
+		}
+
+		Cursor do_next_preorder() {
+			Cursor current = *this;
+			Cursor next = current.do_first_child();
+			if (next.valid())
+				return next;
+			while (current.valid()) {
+				if (next.valid())
+					return next;
+				next = current.do_next_sibling();
+				if (next.valid())
+					return next;
+				current = current.do_parent();
+			}
+			return current;
+		}
+
+		Cursor do_child(IdString name) {
+			IdTree *tree = nullptr;
+			if (scope_name.empty()) {
+				tree = target;
+			} else {
+				auto found = target->subtrees.find(scope_name);
+				if (found != target->subtrees.end()) {
+					tree = found->second.get();
+				} else {
+					return Cursor();
+				}
+			}
+			auto found = tree->names.find(name);
+			if (found == tree->names.end()) {
+				return Cursor();
+			}
+			return Cursor(tree, *found);
+		}
+
+	public:
+		bool operator==(const Cursor &other) const {
+			return target == other.target && scope_name == other.scope_name;
+		}
+		bool operator!=(const Cursor &other) const {
+			return !(*this == other);
+		}
+
+		bool valid() const {
+			return target != nullptr;
+		}
+
+		int depth() const {
+			log_assert(valid());
+			return target->depth + !scope_name.empty();
+		}
+
+		bool is_root() const {
+			return target != nullptr && scope_name.empty();
+		}
+
+		bool has_entry() const {
+			log_assert(valid());
+			return !scope_name.empty() && target->entries.count(scope_name);
+		}
+
+		T &entry() {
+			log_assert(!scope_name.empty());
+			return target->entries.at(scope_name);
+		}
+
+		void assign_path_to(std::vector<IdString> &out_path) {
+			log_assert(valid());
+			out_path.clear();
+			if (scope_name.empty())
+				return;
+			out_path.push_back(scope_name);
+			IdTree *current = target;
+			while (current->parent) {
+				out_path.push_back(current->scope_name);
+				current = current->parent;
+			}
+			std::reverse(out_path.begin(), out_path.end());
+		}
+
+		std::vector<IdString> path() {
+			std::vector<IdString> result;
+			assign_path_to(result);
+			return result;
+		}
+
+		std::string path_str() {
+			std::string result;
+			for (const auto &item : path()) {
+				if (!result.empty())
+					result.push_back(' ');
+				result += RTLIL::unescape_id(item);
+			}
+			return result;
+		}
+
+		Cursor first_child() {
+			log_assert(valid());
+			return do_first_child();
+		}
+
+		Cursor next_preorder() {
+			log_assert(valid());
+			return do_next_preorder();
+		}
+
+		Cursor parent() {
+			log_assert(valid());
+			return do_parent();
+		}
+
+		Cursor child(IdString name) {
+			log_assert(valid());
+			return do_child(name);
+		}
+
+		Cursor common_ancestor(Cursor other) {
+			Cursor current = *this;
+
+			while (current != other) {
+				if (!current.valid() || !other.valid())
+					return Cursor();
+				int delta = current.depth() - other.depth();
+				if (delta >= 0)
+					current = current.do_parent();
+				if (delta <= 0)
+					other = other.do_parent();
+			}
+			return current;
+		}
+	};
+
+	template<typename P>
+	Cursor insert(P begin, P end, const T &value) {
+		return do_insert(this, begin, end, value);
+	}
+
+	template<typename P>
+	Cursor insert(P begin, P end, T &&value) {
+		return do_insert(this, begin, end, std::move(value));
+	}
+
+	template<typename P>
+	Cursor insert(const P &path, const T &value) {
+		return do_insert(this, path.begin(), path.end(), value);
+	}
+
+	template<typename P>
+	Cursor insert(const P &path, T &&value) {
+		return do_insert(this, path.begin(), path.end(), std::move(value));
+	}
+
+	Cursor cursor() {
+		return parent ? Cursor(this->parent, this->scope_name) : Cursor(this, IdString());
+	}
+
+	template<typename P>
+	Cursor cursor(P begin, P end) {
+		Cursor current = cursor();
+		for (; begin != end; ++begin) {
+			current = current.do_child(*begin);
+			if (!current.valid())
+				break;
+		}
+		return current;
+	}
+
+	template<typename P>
+	Cursor cursor(const P &path) {
+		return cursor(path.begin(), path.end());
+	}
+};
+
+
+struct ModuleItem {
+	enum class Type {
+		Wire,
+		Cell,
+	};
+	Type type;
+	void *ptr;
+
+	ModuleItem(Wire *wire) : type(Type::Wire), ptr(wire) {}
+	ModuleItem(Cell *cell) : type(Type::Cell), ptr(cell) {}
+
+	bool is_wire() const { return type == Type::Wire; }
+	bool is_cell() const { return type == Type::Cell; }
+
+	Wire *wire() const { return type == Type::Wire ? static_cast<Wire *>(ptr) : nullptr; }
+	Cell *cell() const { return type == Type::Cell ? static_cast<Cell *>(ptr) : nullptr; }
+
+	bool operator==(const ModuleItem &other) const { return ptr == other.ptr && type == other.type; }
+	unsigned int hash() const { return (uintptr_t)ptr; }
+};
+
+static inline void log_dump_val_worker(typename IdTree<ModuleItem>::Cursor cursor ) { log("%p %s", cursor.target, log_id(cursor.scope_name)); }
+
+template<typename T>
+static inline void log_dump_val_worker(const typename std::unique_ptr<T> &cursor ) { log("unique %p", cursor.get()); }
+
+template<typename O>
+std::vector<IdString> parse_hdlname(const O* object)
+{
+	std::vector<IdString> path;
+	if (!object->name.isPublic())
+		return path;
+	for (auto const &item : object->get_hdlname_attribute())
+		path.push_back("\\" + item);
+	if (path.empty())
+		path.push_back(object->name);
+	return path;
+}
+
+template<typename O>
+std::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)
+{
+	std::vector<IdString> path;
+	IdString trailing = object->name;
+	if (object->name.isPublic()) {
+		for (auto const &item : object->get_hdlname_attribute())
+			path.push_back("\\" + item);
+		if (!path.empty()) {
+			trailing = path.back();
+			path.pop_back();
+		}
+	} else {
+		for (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), " "))
+			path.push_back("\\" + item);
+
+	}
+	return {path, trailing};
+}
+
+struct ModuleHdlnameIndex {
+	typedef IdTree<ModuleItem>::Cursor Cursor;
+
+	RTLIL::Module *module;
+	IdTree<ModuleItem> tree;
+	dict<ModuleItem, Cursor> lookup;
+
+	ModuleHdlnameIndex(RTLIL::Module *module) : module(module) {}
+
+private:
+	template<typename I, typename Filter>
+	void index_items(I begin, I end, Filter filter);
+
+public:
+	// Index all wires and cells of the module
+	void index();
+
+	// Index all wires of the module
+	void index_wires();
+
+	// Index all cells of the module
+	void index_cells();
+
+	// Index only the $scopeinfo cells of the module.
+	// This is sufficient when using `containing_scope`.
+	void index_scopeinfo_cells();
+
+
+	// Return the cursor for the containing scope of some RTLIL object (Wire/Cell/...)
+	template<typename O>
+	std::pair<Cursor, IdString> containing_scope(O *object) {
+		auto pair = parse_scopename(object);
+		return {tree.cursor(pair.first), pair.second};
+	}
+
+	// Return a vector of source locations starting from the indexed module to
+	// the scope represented by the cursor. The vector alternates module and
+	// module item source locations, using empty strings for missing src
+	// attributes.
+	std::vector<std::string> scope_sources(Cursor cursor);
+
+	// Return a vector of source locations starting from the indexed module to
+	// the passed RTLIL object (Wire/Cell/...). The vector alternates module
+	// and module item source locations, using empty strings for missing src
+	// attributes.
+	template<typename O>
+	std::vector<std::string> sources(O *object) {
+		auto pair = parse_scopename(object);
+		std::vector<std::string> result = scope_sources(tree.cursor(pair.first));
+		result.push_back(object->get_src_attribute());
+		return result;
+	}
+};
+
+enum class ScopeinfoAttrs {
+	Module,
+	Cell,
+};
+
+// Check whether the flattened module or flattened cell corresponding to a $scopeinfo cell had a specific attribute.
+bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);
+
+// Get a specific attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.
+RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);
+
+// Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.
+dict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);
+
+YOSYS_NAMESPACE_END
+
+#endif
diff --git a/yosys/kernel/utils.h b/yosys/kernel/utils.h
index d37f045ff7c..3216c5eb5f0 100644
--- a/yosys/kernel/utils.h
+++ b/yosys/kernel/utils.h
@@ -128,41 +128,103 @@ struct stackmap
 // A simple class for topological sorting
 // ------------------------------------------------
 
-template<typename T, typename C = std::less<T>>
-struct TopoSort
+template <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> class TopoSort
 {
-	bool analyze_loops, found_loops;
-	std::map<T, std::set<T, C>, C> database;
-	std::set<std::set<T, C>> loops;
+      public:
+	// We use this ordering of the edges in the adjacency matrix for
+	// exact compatibility with an older implementation.
+	struct IndirectCmp {
+                IndirectCmp(const std::vector<T> &nodes) : node_cmp_(), nodes_(nodes) {}
+		bool operator()(int a, int b) const
+		{
+                        log_assert(static_cast<size_t>(a) < nodes_.size());
+			log_assert(static_cast<size_t>(b) < nodes_.size());
+			return node_cmp_(nodes_[a], nodes_[b]);
+		}
+		const C node_cmp_;
+		const std::vector<T> &nodes_;
+	};
+
+	bool analyze_loops;
+	std::map<T, int, C> node_to_index;
+	std::vector<std::set<int, IndirectCmp>> edges;
 	std::vector<T> sorted;
+	std::set<std::vector<T>> loops;
 
-	TopoSort()
+	TopoSort() : indirect_cmp(nodes)
 	{
 		analyze_loops = true;
 		found_loops = false;
 	}
 
-	void node(T n)
+	int node(T n)
 	{
-		if (database.count(n) == 0)
-			database[n] = std::set<T, C>();
+                auto rv = node_to_index.emplace(n, static_cast<int>(nodes.size()));
+                if (rv.second) {
+      	              nodes.push_back(n);
+		      edges.push_back(std::set<int, IndirectCmp>(indirect_cmp));
+		}
+		return rv.first->second;
 	}
 
-	void edge(T left, T right)
+	void edge(int l_index, int r_index) { edges[r_index].insert(l_index); }
+
+	void edge(T left, T right) { edge(node(left), node(right)); }
+
+	bool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); }
+
+	bool sort()
 	{
-		node(left);
-		database[right].insert(left);
+		log_assert(GetSize(node_to_index) == GetSize(edges));
+		log_assert(GetSize(nodes) == GetSize(edges));
+
+		loops.clear();
+		sorted.clear();
+		found_loops = false;
+
+		std::vector<bool> marked_cells(edges.size(), false);
+		std::vector<bool> active_cells(edges.size(), false);
+		std::vector<int> active_stack;
+		sorted.reserve(edges.size());
+
+		for (const auto &it : node_to_index)
+			sort_worker(it.second, marked_cells, active_cells, active_stack);
+
+		log_assert(GetSize(sorted) == GetSize(nodes));
+
+		return !found_loops;
 	}
 
-	void sort_worker(const T &n, std::set<T, C> &marked_cells, std::set<T, C> &active_cells, std::vector<T> &active_stack)
+	// Build the more expensive representation of edges for
+	// a few passes that use it directly.
+	std::map<T, std::set<T, C>, C> get_database()
 	{
-		if (active_cells.count(n)) {
+		std::map<T, std::set<T, C>, C> database;
+		for (size_t i = 0; i < nodes.size(); ++i) {
+			std::set<T, C> converted_edge_set;
+			for (int other_node : edges[i]) {
+				converted_edge_set.insert(nodes[other_node]);
+			}
+			database.emplace(nodes[i], converted_edge_set);
+		}
+		return database;
+	}
+
+      private:
+	bool found_loops;
+	std::vector<T> nodes;
+	const IndirectCmp indirect_cmp;
+
+	void sort_worker(const int root_index, std::vector<bool> &marked_cells, std::vector<bool> &active_cells, std::vector<int> &active_stack)
+	{
+		if (active_cells[root_index]) {
 			found_loops = true;
 			if (analyze_loops) {
-				std::set<T, C> loop;
-				for (int i = GetSize(active_stack)-1; i >= 0; i--) {
-					loop.insert(active_stack[i]);
-					if (active_stack[i] == n)
+				std::vector<T> loop;
+				for (int i = GetSize(active_stack) - 1; i >= 0; i--) {
+					const int index = active_stack[i];
+					loop.push_back(nodes[index]);
+					if (index == root_index)
 						break;
 				}
 				loops.insert(loop);
@@ -170,42 +232,24 @@ struct TopoSort
 			return;
 		}
 
-		if (marked_cells.count(n))
+		if (marked_cells[root_index])
 			return;
 
-		if (!database.at(n).empty())
-		{
+		if (!edges[root_index].empty()) {
 			if (analyze_loops)
-				active_stack.push_back(n);
-			active_cells.insert(n);
+				active_stack.push_back(root_index);
+			active_cells[root_index] = true;
 
-			for (auto &left_n : database.at(n))
+			for (int left_n : edges[root_index])
 				sort_worker(left_n, marked_cells, active_cells, active_stack);
 
 			if (analyze_loops)
 				active_stack.pop_back();
-			active_cells.erase(n);
+			active_cells[root_index] = false;
 		}
 
-		marked_cells.insert(n);
-		sorted.push_back(n);
-	}
-
-	bool sort()
-	{
-		loops.clear();
-		sorted.clear();
-		found_loops = false;
-
-		std::set<T, C> marked_cells;
-		std::set<T, C> active_cells;
-		std::vector<T> active_stack;
-
-		for (auto &it : database)
-			sort_worker(it.first, marked_cells, active_cells, active_stack);
-
-		log_assert(GetSize(sorted) == GetSize(database));
-		return !found_loops;
+		marked_cells[root_index] = true;
+		sorted.push_back(nodes[root_index]);
 	}
 };
 
diff --git a/yosys/kernel/yosys.cc b/yosys/kernel/yosys.cc
index bd8dded4b5f..57433d0d9c1 100644
--- a/yosys/kernel/yosys.cc
+++ b/yosys/kernel/yosys.cc
@@ -55,7 +55,7 @@
 #  include <glob.h>
 #endif
 
-#ifdef __FreeBSD__
+#if defined(__FreeBSD__) || defined(__NetBSD__)
 #  include <sys/sysctl.h>
 #endif
 
@@ -138,27 +138,11 @@ void yosys_banner()
 {
 	log("\n");
 	log(" /----------------------------------------------------------------------------\\\n");
-	log(" |                                                                            |\n");
 	log(" |  yosys -- Yosys Open SYnthesis Suite                                       |\n");
-	log(" |                                                                            |\n");
-	log(" |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |\n");
-	log(" |                                                                            |\n");
-	log(" |  Permission to use, copy, modify, and/or distribute this software for any  |\n");
-	log(" |  purpose with or without fee is hereby granted, provided that the above    |\n");
-	log(" |  copyright notice and this permission notice appear in all copies.         |\n");
-	log(" |                                                                            |\n");
-	log(" |  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |\n");
-	log(" |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |\n");
-	log(" |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |\n");
-	log(" |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |\n");
-	log(" |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |\n");
-	log(" |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |\n");
-	log(" |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |\n");
-	log(" |                                                                            |\n");
+	log(" |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |\n");
+	log(" |  Distributed under an ISC-like license, type \"license\" to see terms        |\n");
 	log(" \\----------------------------------------------------------------------------/\n");
-	log("\n");
 	log(" %s\n", yosys_version_str);
-	log("\n");
 }
 
 int ceil_log2(int x)
@@ -175,48 +159,6 @@ int ceil_log2(int x)
 #endif
 }
 
-std::string stringf(const char *fmt, ...)
-{
-	std::string string;
-	va_list ap;
-
-	va_start(ap, fmt);
-	string = vstringf(fmt, ap);
-	va_end(ap);
-
-	return string;
-}
-
-std::string vstringf(const char *fmt, va_list ap)
-{
-	std::string string;
-	char *str = NULL;
-
-#if defined(_WIN32 )|| defined(__CYGWIN__)
-	int sz = 64, rc;
-	while (1) {
-		va_list apc;
-		va_copy(apc, ap);
-		str = (char*)realloc(str, sz);
-		rc = vsnprintf(str, sz, fmt, apc);
-		va_end(apc);
-		if (rc >= 0 && rc < sz)
-			break;
-		sz *= 2;
-	}
-#else
-	if (vasprintf(&str, fmt, ap) < 0)
-		str = NULL;
-#endif
-
-	if (str != NULL) {
-		string = str;
-		free(str);
-	}
-
-	return string;
-}
-
 int readsome(std::istream &f, char *s, int n)
 {
 	int rc = int(f.readsome(s, n));
@@ -478,6 +420,25 @@ std::string make_temp_dir(std::string template_str)
 #endif
 }
 
+bool check_directory_exists(const std::string& dirname)
+{
+#if defined(_WIN32)
+	struct _stat info;
+	if (_stat(dirname.c_str(), &info) != 0)
+	{
+		return false;
+	}
+	return (info.st_mode & _S_IFDIR) != 0;
+#else
+	struct stat info;
+	if (stat(dirname.c_str(), &info) != 0)
+	{
+		return false;
+	}
+	return (info.st_mode & S_IFDIR) != 0;
+#endif
+}
+
 #ifdef _WIN32
 bool check_file_exists(std::string filename, bool)
 {
@@ -523,6 +484,48 @@ void remove_directory(std::string dirname)
 #endif
 }
 
+bool create_directory(const std::string& dirname)
+{
+#if defined(_WIN32)
+	int ret = _mkdir(dirname.c_str());
+#else
+	mode_t mode = 0755;
+	int ret = mkdir(dirname.c_str(), mode);
+#endif
+	if (ret == 0)
+		return true;
+
+	switch (errno)
+	{
+	case ENOENT:
+		// parent didn't exist, try to create it
+		{
+			std::string::size_type pos = dirname.find_last_of('/');
+			if (pos == std::string::npos)
+#if defined(_WIN32)
+				pos = dirname.find_last_of('\\');
+			if (pos == std::string::npos)
+#endif
+				return false;
+			if (!create_directory( dirname.substr(0, pos) ))
+				return false;
+		}
+		// now, try to create again
+#if defined(_WIN32)
+		return 0 == _mkdir(dirname.c_str());
+#else
+		return 0 == mkdir(dirname.c_str(), mode);
+#endif
+
+	case EEXIST:
+		// done!
+		return check_directory_exists(dirname);
+
+	default:
+		return false;
+	}
+}
+
 std::string escape_filename_spaces(const std::string& filename)
 {
 	std::string out;
@@ -823,10 +826,10 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a
 
 int yosys_tcl_iterp_init(Tcl_Interp *interp)
 {
-    if (Tcl_Init(interp)!=TCL_OK)
+	if (Tcl_Init(interp)!=TCL_OK)
 		log_warning("Tcl_Init() call failed - %s\n",Tcl_ErrnoMsg(Tcl_GetErrno()));
 	Tcl_CreateCommand(interp, "yosys", tcl_yosys_cmd, NULL, NULL);
-    return TCL_OK ;
+	return TCL_OK ;
 }
 
 void yosys_tcl_activate_repl()
@@ -898,10 +901,14 @@ std::string proc_self_dirname()
 		buflen--;
 	return std::string(path, buflen);
 }
-#elif defined(__FreeBSD__)
+#elif defined(__FreeBSD__) || defined(__NetBSD__)
 std::string proc_self_dirname()
 {
+#ifdef __NetBSD__
+	int mib[4] = {CTL_KERN, KERN_PROC_ARGS, getpid(), KERN_PROC_PATHNAME};
+#else
 	int mib[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PATHNAME, -1};
+#endif
 	size_t buflen;
 	char *buffer;
 	std::string path;
@@ -1395,8 +1402,12 @@ void shell(RTLIL::Design *design)
 		if ((command = fgets(command_buffer, 4096, stdin)) == NULL)
 			break;
 #endif
-		if (command[strspn(command, " \t\r\n")] == 0)
+		if (command[strspn(command, " \t\r\n")] == 0) {
+#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE)
+			free(command);
+#endif
 			continue;
+		}
 #if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE)
 		add_history(command);
 #endif
@@ -1418,10 +1429,17 @@ void shell(RTLIL::Design *design)
 			log_reset_stack();
 		}
 		design->check();
+#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE)
+		if (command)
+			free(command);
+#endif
 	}
 	if (command == NULL)
 		printf("exit\n");
-
+#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE)
+	else
+		free(command);
+#endif
 	recursion_counter--;
 	log_cmd_error_throw = false;
 }
diff --git a/yosys/kernel/yosys.h b/yosys/kernel/yosys.h
index 29415ff842e..5922d9ab752 100644
--- a/yosys/kernel/yosys.h
+++ b/yosys/kernel/yosys.h
@@ -39,263 +39,7 @@
 #ifndef YOSYS_H
 #define YOSYS_H
 
-#include <map>
-#include <set>
-#include <tuple>
-#include <vector>
-#include <string>
-#include <algorithm>
-#include <functional>
-#include <unordered_map>
-#include <unordered_set>
-#include <initializer_list>
-#include <stdexcept>
-#include <memory>
-#include <cmath>
-#include <cstddef>
-
-#include <sstream>
-#include <fstream>
-#include <istream>
-#include <ostream>
-#include <iostream>
-
-#include <stdarg.h>
-#include <stdlib.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <limits.h>
-
-#ifdef WITH_PYTHON
-#include <Python.h>
-#endif
-
-#ifndef _YOSYS_
-#  error It looks like you are trying to build Yosys without the config defines set. \
-         When building Yosys with a custom make system, make sure you set all the \
-         defines the Yosys Makefile would set for your build configuration.
-#endif
-
-#ifdef YOSYS_ENABLE_TCL
-#  include <tcl.h>
-#  ifdef YOSYS_MXE_HACKS
-extern Tcl_Command Tcl_CreateCommand(Tcl_Interp *interp, const char *cmdName, Tcl_CmdProc *proc, ClientData clientData, Tcl_CmdDeleteProc *deleteProc);
-extern Tcl_Interp *Tcl_CreateInterp(void);
-extern void Tcl_Preserve(ClientData data);
-extern void Tcl_Release(ClientData clientData);
-extern int Tcl_InterpDeleted(Tcl_Interp *interp);
-extern void Tcl_DeleteInterp(Tcl_Interp *interp);
-extern int Tcl_Eval(Tcl_Interp *interp, const char *script);
-extern int Tcl_EvalFile(Tcl_Interp *interp, const char *fileName);
-extern void Tcl_Finalize(void);
-extern int Tcl_GetCommandInfo(Tcl_Interp *interp, const char *cmdName, Tcl_CmdInfo *infoPtr);
-extern const char *Tcl_GetStringResult(Tcl_Interp *interp);
-extern Tcl_Obj *Tcl_NewStringObj(const char *bytes, int length);
-extern Tcl_Obj *Tcl_NewIntObj(int intValue);
-extern Tcl_Obj *Tcl_NewListObj(int objc, Tcl_Obj *const objv[]);
-extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *part2Ptr, Tcl_Obj *newValuePtr, int flags);
-#  endif
-#  undef CONST
-#  undef INLINE
-#endif
-
-#ifdef _WIN32
-#  undef NOMINMAX
-#  define NOMINMAX 1
-#  undef YY_NO_UNISTD_H
-#  define YY_NO_UNISTD_H 1
-
-#  include <windows.h>
-#  include <io.h>
-#  include <direct.h>
-
-#  define strtok_r strtok_s
-#  define strdup _strdup
-#  define snprintf _snprintf
-#  define getcwd _getcwd
-#  define mkdir _mkdir
-#  define popen _popen
-#  define pclose _pclose
-
-#  ifndef __MINGW32__
-#    define PATH_MAX MAX_PATH
-#    define isatty _isatty
-#    define fileno _fileno
-#  endif
-
-// The following defines conflict with our identifiers:
-#  undef CONST
-// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc
-#  undef TRANSPARENT
-#endif
-
-#ifndef PATH_MAX
-#  define PATH_MAX 4096
-#endif
-
-#define YOSYS_NAMESPACE          Yosys
-#define PRIVATE_NAMESPACE_BEGIN  namespace {
-#define PRIVATE_NAMESPACE_END    }
-#define YOSYS_NAMESPACE_BEGIN    namespace Yosys {
-#define YOSYS_NAMESPACE_END      }
-#define YOSYS_NAMESPACE_PREFIX   Yosys::
-#define USING_YOSYS_NAMESPACE    using namespace Yosys;
-
-#if defined(__GNUC__) || defined(__clang__)
-#  define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))
-#elif defined(_MSC_VER)
-#  define YS_ATTRIBUTE(...)
-#else
-#  define YS_ATTRIBUTE(...)
-#endif
-
-#if defined(__GNUC__) || defined(__clang__)
-#  define YS_MAYBE_UNUSED __attribute__((__unused__))
-#else
-#  define YS_MAYBE_UNUSED
-#endif
-
-#if __cplusplus >= 201703L
-#  define YS_FALLTHROUGH [[fallthrough]];
-#elif defined(__clang__)
-#  define YS_FALLTHROUGH [[clang::fallthrough]];
-#elif defined(__GNUC__)
-#  define YS_FALLTHROUGH [[gnu::fallthrough]];
-#else
-#  define YS_FALLTHROUGH
-#endif
-
-YOSYS_NAMESPACE_BEGIN
-
-// Note: All headers included in hashlib.h must be included
-// outside of YOSYS_NAMESPACE before this or bad things will happen.
-#ifdef HASHLIB_H
-#  undef HASHLIB_H
-#  include "kernel/hashlib.h"
-#else
-#  include "kernel/hashlib.h"
-#  undef HASHLIB_H
-#endif
-
-using std::vector;
-using std::string;
-using std::tuple;
-using std::pair;
-
-using std::make_tuple;
-using std::make_pair;
-using std::get;
-using std::min;
-using std::max;
-
-// A primitive shared string implementation that does not
-// move its .c_str() when the object is copied or moved.
-struct shared_str {
-	std::shared_ptr<string> content;
-	shared_str() { }
-	shared_str(string s) { content = std::shared_ptr<string>(new string(s)); }
-	shared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }
-	const char *c_str() const { return content->c_str(); }
-	const string &str() const { return *content; }
-	bool operator==(const shared_str &other) const { return *content == *other.content; }
-	unsigned int hash() const { return hashlib::hash_ops<std::string>::hash(*content); }
-};
-
-using hashlib::mkhash;
-using hashlib::mkhash_init;
-using hashlib::mkhash_add;
-using hashlib::mkhash_xorshift;
-using hashlib::hash_ops;
-using hashlib::hash_cstr_ops;
-using hashlib::hash_ptr_ops;
-using hashlib::hash_obj_ops;
-using hashlib::dict;
-using hashlib::idict;
-using hashlib::pool;
-using hashlib::mfp;
-
-namespace RTLIL {
-	struct IdString;
-	struct Const;
-	struct SigBit;
-	struct SigSpec;
-	struct Wire;
-	struct Cell;
-	struct Memory;
-	struct Process;
-	struct Module;
-	struct Design;
-	struct Monitor;
-	enum State : unsigned char;
-}
-
-namespace AST {
-	struct AstNode;
-}
-
-using RTLIL::IdString;
-using RTLIL::Const;
-using RTLIL::SigBit;
-using RTLIL::SigSpec;
-using RTLIL::Wire;
-using RTLIL::Cell;
-using RTLIL::Module;
-using RTLIL::Design;
-
-namespace hashlib {
-	template<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};
-	template<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};
-	template<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};
-	template<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};
-	template<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};
-	template<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};
-	template<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};
-	template<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};
-
-	template<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};
-	template<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};
-	template<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};
-	template<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};
-	template<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};
-	template<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};
-	template<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};
-	template<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};
-}
-
-void memhasher_on();
-void memhasher_off();
-void memhasher_do();
-
-extern bool memhasher_active;
-inline void memhasher() { if (memhasher_active) memhasher_do(); }
-
-void yosys_banner();
-int ceil_log2(int x) YS_ATTRIBUTE(const);
-std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));
-std::string vstringf(const char *fmt, va_list ap);
-int readsome(std::istream &f, char *s, int n);
-std::string next_token(std::string &text, const char *sep = " \t\r\n", bool long_strings = false);
-std::vector<std::string> split_tokens(const std::string &text, const char *sep = " \t\r\n");
-bool patmatch(const char *pattern, const char *string);
-#if !defined(YOSYS_DISABLE_SPAWN)
-int run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());
-#endif
-std::string get_base_tmpdir();
-std::string make_temp_file(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX");
-std::string make_temp_dir(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX");
-bool check_file_exists(std::string filename, bool is_exec = false);
-bool is_absolute_path(std::string filename);
-void remove_directory(std::string dirname);
-std::string escape_filename_spaces(const std::string& filename);
-
-template<typename T> int GetSize(const T &obj) { return obj.size(); }
-inline int GetSize(RTLIL::Wire *wire);
-
-extern int autoidx;
-extern int yosys_xtrace;
-
-YOSYS_NAMESPACE_END
+#include "kernel/yosys_common.h"
 
 #include "kernel/log.h"
 #include "kernel/rtlil.h"
@@ -303,14 +47,6 @@ YOSYS_NAMESPACE_END
 
 YOSYS_NAMESPACE_BEGIN
 
-using RTLIL::State;
-using RTLIL::SigChunk;
-using RTLIL::SigSig;
-
-namespace hashlib {
-	template<> struct hash_ops<RTLIL::State> : hash_ops<int> {};
-}
-
 void yosys_setup();
 
 #ifdef WITH_PYTHON
@@ -325,26 +61,6 @@ Tcl_Interp *yosys_get_tcl_interp();
 
 extern RTLIL::Design *yosys_design;
 
-RTLIL::IdString new_id(std::string file, int line, std::string func);
-RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);
-
-#define NEW_ID \
-	YOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)
-#define NEW_ID_SUFFIX(suffix) \
-	YOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)
-
-// Create a statically allocated IdString object, using for example ID::A or ID($add).
-//
-// Recipe for Converting old code that is using conversion of strings like ID::A and
-// "$add" for creating IdStrings: Run below SED command on the .cc file and then use for
-// example "meld foo.cc foo.cc.orig" to manually compile errors, if necessary.
-//
-//  sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' <filename>
-//
-#define ID(_id) ([]() { const char *p = "\\" #_id, *q = p[1] == '$' ? p+1 : p; \
-        static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })()
-namespace ID = RTLIL::ID;
-
 RTLIL::Design *yosys_get_design();
 std::string proc_self_dirname();
 std::string proc_share_dirname();
diff --git a/yosys/kernel/yosys_common.h b/yosys/kernel/yosys_common.h
new file mode 100644
index 00000000000..9f1bc2f58d7
--- /dev/null
+++ b/yosys/kernel/yosys_common.h
@@ -0,0 +1,379 @@
+/* -*- c++ -*-
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef YOSYS_COMMON_H
+#define YOSYS_COMMON_H
+
+#include <map>
+#include <set>
+#include <tuple>
+#include <vector>
+#include <string>
+#include <algorithm>
+#include <functional>
+#include <unordered_map>
+#include <unordered_set>
+#include <initializer_list>
+#include <stdexcept>
+#include <memory>
+#include <cmath>
+#include <cstddef>
+
+#include <sstream>
+#include <fstream>
+#include <istream>
+#include <ostream>
+#include <iostream>
+
+#include <stdarg.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <limits.h>
+#include <sys/stat.h>
+#include <errno.h>
+
+#ifdef WITH_PYTHON
+#include <Python.h>
+#endif
+
+#ifndef _YOSYS_
+#  error It looks like you are trying to build Yosys without the config defines set. \
+         When building Yosys with a custom make system, make sure you set all the \
+         defines the Yosys Makefile would set for your build configuration.
+#endif
+
+#ifdef YOSYS_ENABLE_TCL
+#  include <tcl.h>
+#  ifdef YOSYS_MXE_HACKS
+extern Tcl_Command Tcl_CreateCommand(Tcl_Interp *interp, const char *cmdName, Tcl_CmdProc *proc, ClientData clientData, Tcl_CmdDeleteProc *deleteProc);
+extern Tcl_Interp *Tcl_CreateInterp(void);
+extern void Tcl_Preserve(ClientData data);
+extern void Tcl_Release(ClientData clientData);
+extern int Tcl_InterpDeleted(Tcl_Interp *interp);
+extern void Tcl_DeleteInterp(Tcl_Interp *interp);
+extern int Tcl_Eval(Tcl_Interp *interp, const char *script);
+extern int Tcl_EvalFile(Tcl_Interp *interp, const char *fileName);
+extern void Tcl_Finalize(void);
+extern int Tcl_GetCommandInfo(Tcl_Interp *interp, const char *cmdName, Tcl_CmdInfo *infoPtr);
+extern const char *Tcl_GetStringResult(Tcl_Interp *interp);
+extern Tcl_Obj *Tcl_NewStringObj(const char *bytes, int length);
+extern Tcl_Obj *Tcl_NewIntObj(int intValue);
+extern Tcl_Obj *Tcl_NewListObj(int objc, Tcl_Obj *const objv[]);
+extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *part2Ptr, Tcl_Obj *newValuePtr, int flags);
+#  endif
+#  undef CONST
+#  undef INLINE
+#endif
+
+#ifdef _WIN32
+#  undef NOMINMAX
+#  define NOMINMAX 1
+#  undef YY_NO_UNISTD_H
+#  define YY_NO_UNISTD_H 1
+
+#  include <windows.h>
+#  include <io.h>
+#  include <direct.h>
+
+#  define strtok_r strtok_s
+#  define strdup _strdup
+#  define snprintf _snprintf
+#  define getcwd _getcwd
+#  define mkdir _mkdir
+#  define popen _popen
+#  define pclose _pclose
+
+#  ifndef __MINGW32__
+#    define PATH_MAX MAX_PATH
+#    define isatty _isatty
+#    define fileno _fileno
+#  endif
+
+// The following defines conflict with our identifiers:
+#  undef CONST
+// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc
+#  undef TRANSPARENT
+#endif
+
+#ifndef PATH_MAX
+#  define PATH_MAX 4096
+#endif
+
+
+#define YOSYS_NAMESPACE          Yosys
+#define PRIVATE_NAMESPACE_BEGIN  namespace {
+#define PRIVATE_NAMESPACE_END    }
+#define YOSYS_NAMESPACE_BEGIN    namespace Yosys {
+#define YOSYS_NAMESPACE_END      }
+#define YOSYS_NAMESPACE_PREFIX   Yosys::
+#define USING_YOSYS_NAMESPACE    using namespace Yosys;
+
+#if defined(__GNUC__) || defined(__clang__)
+#  define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))
+#elif defined(_MSC_VER)
+#  define YS_ATTRIBUTE(...)
+#else
+#  define YS_ATTRIBUTE(...)
+#endif
+
+#if defined(__GNUC__) || defined(__clang__)
+#  define YS_MAYBE_UNUSED __attribute__((__unused__))
+#else
+#  define YS_MAYBE_UNUSED
+#endif
+
+#if __cplusplus >= 201703L
+#  define YS_FALLTHROUGH [[fallthrough]];
+#elif defined(__clang__)
+#  define YS_FALLTHROUGH [[clang::fallthrough]];
+#elif defined(__GNUC__)
+#  define YS_FALLTHROUGH [[gnu::fallthrough]];
+#else
+#  define YS_FALLTHROUGH
+#endif
+
+
+YOSYS_NAMESPACE_BEGIN
+
+// Note: All headers included in hashlib.h must be included
+// outside of YOSYS_NAMESPACE before this or bad things will happen.
+#ifdef HASHLIB_H
+#  undef HASHLIB_H
+#  include "kernel/hashlib.h"
+#else
+#  include "kernel/hashlib.h"
+#  undef HASHLIB_H
+#endif
+
+
+using std::vector;
+using std::string;
+using std::tuple;
+using std::pair;
+
+using std::make_tuple;
+using std::make_pair;
+using std::get;
+using std::min;
+using std::max;
+
+// A primitive shared string implementation that does not
+// move its .c_str() when the object is copied or moved.
+struct shared_str {
+	std::shared_ptr<string> content;
+	shared_str() { }
+	shared_str(string s) { content = std::shared_ptr<string>(new string(s)); }
+	shared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }
+	const char *c_str() const { return content->c_str(); }
+	const string &str() const { return *content; }
+	bool operator==(const shared_str &other) const { return *content == *other.content; }
+	unsigned int hash() const { return hashlib::hash_ops<std::string>::hash(*content); }
+};
+
+using hashlib::mkhash;
+using hashlib::mkhash_init;
+using hashlib::mkhash_add;
+using hashlib::mkhash_xorshift;
+using hashlib::hash_ops;
+using hashlib::hash_cstr_ops;
+using hashlib::hash_ptr_ops;
+using hashlib::hash_obj_ops;
+using hashlib::dict;
+using hashlib::idict;
+using hashlib::pool;
+using hashlib::mfp;
+
+namespace RTLIL {
+	struct IdString;
+	struct Const;
+	struct SigBit;
+	struct SigSpec;
+	struct Wire;
+	struct Cell;
+	struct Memory;
+	struct Process;
+	struct Module;
+	struct Design;
+	struct Monitor;
+    struct Selection;
+	struct SigChunk;
+	enum State : unsigned char;
+
+	typedef std::pair<SigSpec, SigSpec> SigSig;
+
+    namespace ID {}
+}
+
+namespace AST {
+	struct AstNode;
+}
+
+using RTLIL::IdString;
+using RTLIL::Const;
+using RTLIL::SigBit;
+using RTLIL::SigSpec;
+using RTLIL::Wire;
+using RTLIL::Cell;
+using RTLIL::Module;
+using RTLIL::Design;
+
+using RTLIL::State;
+using RTLIL::SigChunk;
+using RTLIL::SigSig;
+
+namespace hashlib {
+	template<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};
+	template<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};
+	template<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};
+	template<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};
+	template<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};
+	template<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};
+	template<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};
+	template<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};
+
+	template<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};
+	template<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};
+	template<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};
+	template<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};
+	template<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};
+	template<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};
+	template<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};
+	template<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};
+}
+
+void memhasher_on();
+void memhasher_off();
+void memhasher_do();
+
+extern bool memhasher_active;
+inline void memhasher() { if (memhasher_active) memhasher_do(); }
+
+void yosys_banner();
+int ceil_log2(int x) YS_ATTRIBUTE(const);
+
+inline std::string vstringf(const char *fmt, va_list ap)
+{
+        // For the common case of strings shorter than 128, save a heap
+        // allocation by using a stack allocated buffer.
+        const int kBufSize = 128;
+        char buf[kBufSize];
+        buf[0] = '\0';
+        va_list apc;
+        va_copy(apc, ap);
+        int n = vsnprintf(buf, kBufSize, fmt, apc);
+        va_end(apc);
+        if (n < kBufSize)
+          return std::string(buf);
+
+        std::string string;
+        char *str = NULL;
+#if defined(_WIN32 )|| defined(__CYGWIN__)
+        int sz = 2 * kBufSize, rc;
+        while (1) {
+		va_copy(apc, ap);
+		str = (char*)realloc(str, sz);
+		rc = vsnprintf(str, sz, fmt, apc);
+		va_end(apc);
+		if (rc >= 0 && rc < sz)
+			break;
+		sz *= 2;
+	}
+	if (str != NULL) {
+		string = str;
+		free(str);
+	}
+	return string;
+#else
+        if (vasprintf(&str, fmt, ap) < 0)
+          str = NULL;
+        if (str != NULL) {
+          string = str;
+          free(str);
+        }
+	return string;
+#endif
+}
+
+std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));
+
+inline std::string stringf(const char *fmt, ...)
+{
+	std::string string;
+	va_list ap;
+
+	va_start(ap, fmt);
+	string = vstringf(fmt, ap);
+	va_end(ap);
+
+	return string;
+}
+
+int readsome(std::istream &f, char *s, int n);
+std::string next_token(std::string &text, const char *sep = " \t\r\n", bool long_strings = false);
+std::vector<std::string> split_tokens(const std::string &text, const char *sep = " \t\r\n");
+bool patmatch(const char *pattern, const char *string);
+#if !defined(YOSYS_DISABLE_SPAWN)
+int run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());
+#endif
+std::string get_base_tmpdir();
+std::string make_temp_file(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX");
+std::string make_temp_dir(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX");
+bool check_file_exists(std::string filename, bool is_exec = false);
+bool check_directory_exists(const std::string& dirname);
+bool is_absolute_path(std::string filename);
+void remove_directory(std::string dirname);
+bool create_directory(const std::string& dirname);
+std::string escape_filename_spaces(const std::string& filename);
+
+template<typename T> int GetSize(const T &obj) { return obj.size(); }
+inline int GetSize(RTLIL::Wire *wire);
+
+extern int autoidx;
+extern int yosys_xtrace;
+
+RTLIL::IdString new_id(std::string file, int line, std::string func);
+RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);
+
+#define NEW_ID \
+	YOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)
+#define NEW_ID_SUFFIX(suffix) \
+	YOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)
+
+// Create a statically allocated IdString object, using for example ID::A or ID($add).
+//
+// Recipe for Converting old code that is using conversion of strings like ID::A and
+// "$add" for creating IdStrings: Run below SED command on the .cc file and then use for
+// example "meld foo.cc foo.cc.orig" to manually compile errors, if necessary.
+//
+//  sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' <filename>
+//
+#define ID(_id) ([]() { const char *p = "\\" #_id, *q = p[1] == '$' ? p+1 : p; \
+        static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })()
+namespace ID = RTLIL::ID;
+
+namespace hashlib {
+	template<> struct hash_ops<RTLIL::State> : hash_ops<int> {};
+}
+
+
+YOSYS_NAMESPACE_END
+
+#endif
diff --git a/yosys/libs/bigint/run-testsuite b/yosys/libs/bigint/run-testsuite
index ff737291641..8436ebda057 100755
--- a/yosys/libs/bigint/run-testsuite
+++ b/yosys/libs/bigint/run-testsuite
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 bad=
 
diff --git a/yosys/libs/ezsat/Makefile b/yosys/libs/ezsat/Makefile
index b1f86416093..c41038dc938 100644
--- a/yosys/libs/ezsat/Makefile
+++ b/yosys/libs/ezsat/Makefile
@@ -1,9 +1,9 @@
 
 CC = clang
-CXX = clang
+CXX = clang++
 CXXFLAGS = -MD -Wall -Wextra -ggdb
 CXXFLAGS += -std=c++11 -O0
-LDLIBS = ../minisat/Options.cc ../minisat/SimpSolver.cc ../minisat/Solver.cc ../minisat/System.cc -lm -lstdc++
+LIBS = ../minisat/Options.cc ../minisat/SimpSolver.cc ../minisat/Solver.cc ../minisat/System.cc -lm -lstdc++
 
 
 all: demo_vec demo_bit demo_cmp testbench puzzle3d
@@ -27,4 +27,3 @@ clean:
 .PHONY: all test clean
 
 -include *.d
-
diff --git a/yosys/libs/fst/fstapi.cc b/yosys/libs/fst/fstapi.cc
index da0d959a0de..592b5cae6a7 100644
--- a/yosys/libs/fst/fstapi.cc
+++ b/yosys/libs/fst/fstapi.cc
@@ -348,17 +348,17 @@ static void *fstMmap2(size_t __len, int __fd, fst_off_t __off)
 #ifdef FST_DO_MISALIGNED_OPS
 #define fstGetUint32(x) (*(uint32_t *)(x))
 #else
-static uint32_t fstGetUint32(unsigned char *mem)
+static inline uint32_t fstGetUint32(unsigned char *mem)
 {
-    uint32_t u32;
-    unsigned char *buf = (unsigned char *)(&u32);
+    union {
+            uint8_t u8[sizeof(uint32_t)];
+            uint32_t u32;
+    } u;
 
-    buf[0] = mem[0];
-    buf[1] = mem[1];
-    buf[2] = mem[2];
-    buf[3] = mem[3];
+    for (size_t i=0; i < sizeof(u.u8); i++)
+            u.u8[i] = mem[i];
 
-    return (*(uint32_t *)buf);
+    return u.u32;
 }
 #endif
 
@@ -4334,7 +4334,7 @@ int fstReaderInit(struct fstReaderContext *xc)
                     hdr_incomplete = (xc->start_time == 0) && (xc->end_time == 0);
 
                     fstFread(&dcheck, 8, 1, xc->f);
-                    xc->double_endian_match = (dcheck == FST_DOUBLE_ENDTEST);
+                    xc->double_endian_match = (dcheck == (double)FST_DOUBLE_ENDTEST);
                     if (!xc->double_endian_match) {
                         union
                         {
diff --git a/yosys/libs/subcircuit/Makefile b/yosys/libs/subcircuit/Makefile
index f81085b5bc3..3d93ad0a2e4 100644
--- a/yosys/libs/subcircuit/Makefile
+++ b/yosys/libs/subcircuit/Makefile
@@ -5,9 +5,9 @@ CONFIG := clang-debug
 # CONFIG := release
 
 CC = clang
-CXX = clang
+CXX = clang++
 CXXFLAGS = -MD -Wall -Wextra -ggdb
-LDLIBS = -lstdc++
+LIBS = -lstdc++
 
 ifeq ($(CONFIG),clang-debug)
 CXXFLAGS += -std=c++11 -O0
@@ -15,19 +15,19 @@ endif
 
 ifeq ($(CONFIG),gcc-debug)
 CC = gcc
-CXX = gcc
+CXX = g++
 CXXFLAGS += -std=gnu++0x -O0
 endif
 
 ifeq ($(CONFIG),profile)
 CC = gcc
-CXX = gcc
+CXX = g++
 CXXFLAGS += -std=gnu++0x -Os -DNDEBUG
 endif
 
 ifeq ($(CONFIG),release)
 CC = gcc
-CXX = gcc
+CXX = g++
 CXXFLAGS += -std=gnu++0x -march=native -O3 -DNDEBUG
 endif
 
@@ -50,4 +50,3 @@ clean:
 .PHONY: all test clean
 
 -include *.d
-
diff --git a/yosys/manual/.gitignore b/yosys/manual/.gitignore
deleted file mode 100644
index 110f65b1900..00000000000
--- a/yosys/manual/.gitignore
+++ /dev/null
@@ -1,12 +0,0 @@
-*.aux
-*.bbl
-*.blg
-*.idx
-*.log
-*.out
-*.pdf
-*.toc
-*.snm
-*.nav
-*.vrb
-*.ok
diff --git a/yosys/manual/PRESENTATION_ExAdv.tex b/yosys/manual/PRESENTATION_ExAdv.tex
deleted file mode 100644
index 6a426ff2b1f..00000000000
--- a/yosys/manual/PRESENTATION_ExAdv.tex
+++ /dev/null
@@ -1,896 +0,0 @@
-
-\section{Yosys by example -- Advanced Synthesis}
-
-\begin{frame}
-\sectionpage
-\end{frame}
-
-\begin{frame}{Overview}
-This section contains 4 subsections:
-\begin{itemize}
-\item Using selections
-\item Advanced uses of techmap
-\item Coarse-grain synthesis
-\item Automatic design changes
-\end{itemize}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Using selections}
-
-\begin{frame}
-\subsectionpage
-\subsectionpagesuffix
-\end{frame}
-
-\subsubsection{Simple selections}
-
-\begin{frame}[fragile]{\subsubsecname}
-Most Yosys commands make use of the ``selection framework'' of Yosys. It can be used
-to apply commands only to part of the design. For example:
-
-\medskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-delete                # will delete the whole design, but
-
-delete foobar         # will only delete the module foobar.
-\end{lstlisting}
-
-\bigskip
-The {\tt select} command can be used to create a selection for subsequent
-commands. For example:
-
-\medskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-select foobar         # select the module foobar
-delete                # delete selected objects
-select -clear         # reset selection (select whole design)
-\end{lstlisting}
-\end{frame}
-
-\subsubsection{Selection by object name}
-
-\begin{frame}[fragile]{\subsubsecname}
-The easiest way to select objects is by object name. This is usually only done
-in synthesis scripts that are hand-tailored for a specific design.
-
-\bigskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-select foobar         # select module foobar
-select foo*           # select all modules whose names start with foo
-select foo*/bar*      # select all objects matching bar* from modules matching foo*
-select */clk          # select objects named clk from all modules
-\end{lstlisting}
-\end{frame}
-
-\subsubsection{Module and design context}
-
-\begin{frame}[fragile]{\subsubsecname}
-Commands can be executed in {\it module\/} or {\it design\/} context. Until now all
-commands have been executed in design context. The {\tt cd} command can be used
-to switch to module context.
-
-\bigskip
-In module context all commands only effect the active module. Objects in the module
-are selected without the {\tt <module\_name>/} prefix. For example:
-
-\bigskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-cd foo                # switch to module foo
-delete bar            # delete object foo/bar
-
-cd mycpu              # switch to module mycpu
-dump reg_*            # print details on all objects whose names start with reg_
-
-cd ..                 # switch back to design
-\end{lstlisting}
-
-\bigskip
-Note: Most synthesis scripts never switch to module context. But it is a very powerful
-tool for interactive design investigation.
-\end{frame}
-
-\subsubsection{Selecting by object property or type}
-
-\begin{frame}[fragile]{\subsubsecname}
-Special patterns can be used to select by object property or type. For example:
-
-\bigskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-select w:reg_*        # select all wires whose names start with reg_
-select a:foobar       # select all objects with the attribute foobar set
-select a:foobar=42    # select all objects with the attribute foobar set to 42
-select A:blabla       # select all modules with the attribute blabla set
-select foo/t:$add     # select all $add cells from the module foo
-\end{lstlisting}
-
-\bigskip
-A complete list of this pattern expressions can be found in the command
-reference to the {\tt select} command.
-\end{frame}
-
-\subsubsection{Combining selection}
-
-\begin{frame}[fragile]{\subsubsecname}
-When more than one selection expression is used in one statement, then they are
-pushed on a stack. The final elements on the stack are combined into a union:
-
-\medskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-select t:$dff r:WIDTH>1     # all cells of type $dff and/or with a parameter WIDTH > 1
-\end{lstlisting}
-
-\bigskip
-Special \%-commands can be used to combine the elements on the stack:
-
-\medskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-select t:$dff r:WIDTH>1 %i  # all cells of type $dff *AND* with a parameter WIDTH > 1
-\end{lstlisting}
-
-\medskip
-\begin{block}{Examples for {\tt \%}-codes (see {\tt help select} for full list)}
-{\tt \%u} \dotfill union of top two elements on stack -- pop 2, push 1 \\
-{\tt \%d} \dotfill difference of top two elements on stack -- pop 2, push 1 \\
-{\tt \%i} \dotfill intersection of top two elements on stack -- pop 2, push 1 \\
-{\tt \%n} \dotfill inverse of top element on stack -- pop 1, push 1 \\
-\end{block}
-\end{frame}
-
-\subsubsection{Expanding selections}
-
-\begin{frame}[fragile]{\subsubsecname}
-Selections of cells and wires can be expanded along connections using {\tt \%}-codes
-for selecting input cones ({\tt \%ci}), output cones ({\tt \%co}), or both ({\tt \%x}).
-
-\medskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-# select all wires that are inputs to $add cells
-select t:$add %ci w:* %i
-\end{lstlisting}
-
-\bigskip
-Additional constraints such as port names can be specified.
-
-\medskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-# select all wires that connect a "Q" output with a "D" input
-select c:* %co:+[Q] w:* %i c:* %ci:+[D] w:* %i %i
-
-# select the multiplexer tree that drives the signal 'state'
-select state %ci*:+$mux,$pmux[A,B,Y]
-\end{lstlisting}
-
-\bigskip
-See {\tt help select} for full documentation of this expressions.
-\end{frame}
-
-\subsubsection{Incremental selection}
-
-\begin{frame}[fragile]{\subsubsecname}
-Sometimes a selection can most easily be described by a series of add/delete operations.
-The commands {\tt select -add} and {\tt select -del} respectively add or remove objects
-from the current selection instead of overwriting it.
-
-\medskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-select -none            # start with an empty selection
-select -add reg_*       # select a bunch of objects
-select -del reg_42      # but not this one
-select -add state %ci   # and add mor stuff
-\end{lstlisting}
-
-\bigskip
-Within a select expression the token {\tt \%} can be used to push the previous selection
-on the stack.
-
-\medskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-select t:$add t:$sub    # select all $add and $sub cells
-select % %ci % %d       # select only the input wires to those cells
-\end{lstlisting}
-\end{frame}
-
-\subsubsection{Creating selection variables}
-
-\begin{frame}[fragile]{\subsubsecname}
-Selections can be stored under a name with the {\tt select -set <name>}
-command. The stored selections can be used in later select expressions
-using the syntax {\tt @<name>}.
-
-\medskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-select -set cone_a state_a %ci*:-$dff  # set @cone_a to the input cone of state_a
-select -set cone_b state_b %ci*:-$dff  # set @cone_b to the input cone of state_b
-select @cone_a @cone_b %i              # select the objects that are in both cones
-\end{lstlisting}
-
-\bigskip
-Remember that select expressions can also be used directly as arguments to most
-commands. Some commands also except a single select argument to some options.
-In those cases selection variables must be used to capture more complex selections.
-
-\medskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-dump @cone_a @cone_b
-
-select -set cone_ab @cone_a @cone_b %i
-show -color red @cone_ab -color magenta @cone_a -color blue @cone_b
-\end{lstlisting}
-\end{frame}
-
-\begin{frame}[fragile]{\subsubsecname{} -- Example}
-\begin{columns}
-\column[t]{4cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/select.v}
-\column[t]{7cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExAdv/select.ys}
-\end{columns}
-\hfil\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/select.pdf}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Advanced uses of techmap}
-
-\begin{frame}
-\subsectionpage
-\subsectionpagesuffix
-\end{frame}
-
-\subsubsection{Introduction to techmap}
-
-\begin{frame}{\subsubsecname}
-\begin{itemize}
-\item
-The {\tt techmap} command replaces cells in the design with implementations given
-as Verilog code (called ``map files''). It can replace Yosys' internal cell
-types (such as {\tt \$or}) as well as user-defined cell types.
-\medskip\item
-Verilog parameters are used extensively to customize the internal cell types.
-\medskip\item
-Additional special parameters are used by techmap to communicate meta-data to the
-map files.
-\medskip\item
-Special wires are used to instruct techmap how to handle a module in the map file.
-\medskip\item
-Generate blocks and recursion are powerful tools for writing map files.
-\end{itemize}
-\end{frame}
-
-\begin{frame}[t]{\subsubsecname{} -- Example 1/2}
-\vskip-0.2cm
-To map the Verilog OR-reduction operator to 3-input OR gates:
-\vskip-0.2cm
-\begin{columns}
-\column[t]{0.35\linewidth}
-\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=24]{PRESENTATION_ExAdv/red_or3x1_map.v}
-\column[t]{0.65\linewidth}
-\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=25]{PRESENTATION_ExAdv/red_or3x1_map.v}
-\end{columns}
-\end{frame}
-
-\begin{frame}[t]{\subsubsecname{} -- Example 2/2}
-\vbox to 0cm{
-\hfil\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/red_or3x1.pdf}
-\vss
-}
-\begin{columns}
-\column[t]{6cm}
-\column[t]{4cm}
-\vskip-0.6cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, firstline=4, lastline=4, frame=single]{PRESENTATION_ExAdv/red_or3x1_test.ys}
-\vskip-0.2cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/red_or3x1_test.v}
-\end{columns}
-\end{frame}
-
-\subsubsection{Conditional techmap}
-
-\begin{frame}{\subsubsecname}
-\begin{itemize}
-\item In some cases only cells with certain properties should be substituted.
-\medskip
-\item The special wire {\tt \_TECHMAP\_FAIL\_} can be used to disable a module
-in the map file for a certain set of parameters.
-\medskip
-\item The wire {\tt \_TECHMAP\_FAIL\_} must be set to a constant value. If it
-is non-zero then the module is disabled for this set of parameters.
-\medskip
-\item Example use-cases:
-\begin{itemize}
-\item coarse-grain cell types that only operate on certain bit widths
-\item memory resources for different memory geometries (width, depth, ports, etc.)
-\end{itemize}
-\end{itemize}
-\end{frame}
-
-\begin{frame}[t]{\subsubsecname{} -- Example}
-\vbox to 0cm{
-\vskip-0.5cm
-\hfill\includegraphics[width=6cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/sym_mul.pdf}
-\vss
-}
-\vskip-0.5cm
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/sym_mul_map.v}
-\begin{columns}
-\column[t]{6cm}
-\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/sym_mul_test.v}
-\column[t]{4cm}
-\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=4]{PRESENTATION_ExAdv/sym_mul_test.ys}
-\end{columns}
-\end{frame}
-
-\subsubsection{Scripting in map modules}
-
-\begin{frame}{\subsubsecname}
-\begin{itemize}
-\item The special wires {\tt \_TECHMAP\_DO\_*} can be used to run Yosys scripts
-in the context of the replacement module.
-\medskip
-\item The wire that comes first in alphabetical oder is interpreted as string (must
-be connected to constants) that is executed as script. Then the wire is removed. Repeat.
-\medskip
-\item You can even call techmap recursively!
-\medskip
-\item Example use-cases:
-\begin{itemize}
-\item Using always blocks in map module: call {\tt proc}
-\item Perform expensive optimizations (such as {\tt freduce}) on cells where
-this is known to work well.
-\item Interacting with custom commands.
-\end{itemize}
-\end{itemize}
-
-\scriptsize
-PROTIP: Commands such as {\tt shell}, {\tt show -pause}, and {\tt dump} can be use
-in the {\tt \_TECHMAP\_DO\_*} scripts for debugging map modules.
-\end{frame}
-
-\begin{frame}[t]{\subsubsecname{} -- Example}
-\vbox to 0cm{
-\vskip4.2cm
-\hskip0.5cm\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mymul.pdf}
-\vss
-}
-\vskip-0.6cm
-\begin{columns}
-\column[t]{6cm}
-\vskip-0.6cm
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mymul_map.v}
-\column[t]{4.2cm}
-\vskip-0.6cm
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mymul_test.v}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mymul_test.ys}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, frame=single, language=ys, firstline=7, lastline=12]{PRESENTATION_ExAdv/mymul_test.ys}
-\end{columns}
-\end{frame}
-
-\subsubsection{Handling constant inputs}
-
-\begin{frame}{\subsubsecname}
-\begin{itemize}
-\item The special parameters {\tt \_TECHMAP\_CONSTMSK\_\it <port-name>\tt \_} and
-{\tt \_TECHMAP\_CONSTVAL\_\it <port-name>\tt \_} can be used to handle constant
-input values to cells.
-\medskip
-\item The former contains 1-bits for all constant input bits on the port.
-\medskip
-\item The latter contains the constant bits or undef (x) for non-constant bits.
-\medskip
-\item Example use-cases:
-\begin{itemize}
-\item Converting arithmetic (for example multiply to shift)
-\item Identify constant addresses or enable bits in memory interfaces.
-\end{itemize}
-\end{itemize}
-\end{frame}
-
-\begin{frame}[t]{\subsubsecname{} -- Example}
-\vbox to 0cm{
-\vskip5.2cm
-\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mulshift.pdf}
-\vss
-}
-\vskip-0.6cm
-\begin{columns}
-\column[t]{6cm}
-\vskip-0.4cm
-\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mulshift_map.v}
-\column[t]{4.2cm}
-\vskip-0.6cm
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mulshift_test.v}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mulshift_test.ys}
-\end{columns}
-\end{frame}
-
-\subsubsection{Handling shorted inputs}
-
-\begin{frame}{\subsubsecname}
-\begin{itemize}
-\item The special parameters {\tt \_TECHMAP\_BITS\_CONNMAP\_} and
-{\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} can be used to handle shorted inputs.
-\medskip
-\item Each bit of the port correlates to an {\tt \_TECHMAP\_BITS\_CONNMAP\_} bits wide
-number in {\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_}.
-\medskip
-\item Each unique signal bit is assigned its own number. Identical fields in the {\tt
-\_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} parameters mean shorted signal bits.
-\medskip
-\item The numbers 0-3 are reserved for {\tt 0}, {\tt 1}, {\tt x}, and {\tt z} respectively.
-\medskip
-\item Example use-cases:
-\begin{itemize}
-\item Detecting shared clock or control signals in memory interfaces.
-\item In some cases this can be used for for optimization.
-\end{itemize}
-\end{itemize}
-\end{frame}
-
-\begin{frame}[t]{\subsubsecname{} -- Example}
-\vbox to 0cm{
-\vskip4.5cm
-\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/addshift.pdf}
-\vss
-}
-\vskip-0.6cm
-\begin{columns}
-\column[t]{6cm}
-\vskip-0.4cm
-\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/addshift_map.v}
-\column[t]{4.2cm}
-\vskip-0.6cm
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/addshift_test.v}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/addshift_test.ys}
-\end{columns}
-\end{frame}
-
-\subsubsection{Notes on using techmap}
-
-\begin{frame}{\subsubsecname}
-\begin{itemize}
-\item Don't use positional cell parameters in map modules.
-\medskip
-\item Don't try to implement basic logic optimization with techmap. \\
-{\small (So the OR-reduce using OR3X1 cells map was actually a bad example.)}
-\medskip
-\item You can use the {\tt \$\_\,\_}-prefix for internal cell types to avoid
-collisions with the user-namespace. But always use two underscores or the
-internal consistency checker will trigger on this cells.
-\medskip
-\item Techmap has two major use cases:
-\begin{itemize}
-\item Creating good logic-level representation of arithmetic functions. \\
-This also means using dedicated hardware resources such as half- and full-adder
-cells in ASICS or dedicated carry logic in FPGAs.
-\smallskip
-\item Mapping of coarse-grain resources such as block memory or DSP cells.
-\end{itemize}
-\end{itemize}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Coarse-grain synthesis}
-
-\begin{frame}
-\subsectionpage
-\subsectionpagesuffix
-\end{frame}
-
-\subsubsection{Intro to coarse-grain synthesis}
-
-\begin{frame}[fragile]{\subsubsecname}
-In coarse-grain synthesis the target architecture has cells of the same
-complexity or larger complexity than the internal RTL representation.
-
-For example:
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]
-	wire [15:0] a, b;
-	wire [31:0] c, y;
-	assign y = a * b + c;
-\end{lstlisting}
-
-This circuit contains two cells in the RTL representation: one multiplier and
-one adder. In some architectures this circuit can be implemented using
-a single circuit element, for example an FPGA DSP core. Coarse grain synthesis
-is this mapping of groups of circuit elements to larger components.
-
-\bigskip
-Fine-grain synthesis would be matching the circuit elements to smaller
-components, such as LUTs, gates, or half- and full-adders.
-\end{frame}
-
-\subsubsection{The extract pass}
-
-\begin{frame}{\subsubsecname}
-\begin{itemize}
-\item Like the {\tt techmap} pass, the {\tt extract} pass is called with
-a map file. It compares the circuits inside the modules of the map file
-with the design and looks for sub-circuits in the design that match any
-of the modules in the map file.
-\bigskip
-\item If a match is found, the {\tt extract} pass will replace the matching
-subcircuit with an instance of the module from the map file.
-\bigskip
-\item In a way the {\tt extract} pass is the inverse of the techmap pass.
-\end{itemize}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsubsecname{} -- Example 1/2}
-\vbox to 0cm{
-\vskip2cm
-\begin{tikzpicture}
-    \node at (0,0) {\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00a.pdf}};
-    \node at (3,-3) {\includegraphics[width=8cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00b.pdf}};
-    \draw[yshift=0.2cm,thick,-latex] (1,-1) -- (2,-2);
-\end{tikzpicture}
-\vss}
-\vskip-1.2cm
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test.v}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/macc_simple_xmap.v}
-\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys]
-read_verilog macc_simple_test.v
-hierarchy -check -top test
-
-extract -map macc_simple_xmap.v;;
-\end{lstlisting}
-\end{columns}
-\end{frame}
-
-\begin{frame}[fragile]{\subsubsecname{} -- Example 2/2}
-\hfil\begin{tabular}{cc}
-\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_01.v}}} &
-\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_02.v}}} \\
-$\downarrow$ & $\downarrow$ \\
-\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01a.pdf}} &
-\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02a.pdf}} \\
-$\downarrow$ & $\downarrow$ \\
-\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01b.pdf}} &
-\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02b.pdf}} \\
-\end{tabular}
-\end{frame}
-
-\subsubsection{The wrap-extract-unwrap method}
-
-\begin{frame}{\subsubsecname}
-\scriptsize
-Often a coarse-grain element has a constant bit-width, but can be used to
-implement operations with a smaller bit-width. For example, a 18x25-bit multiplier
-can also be used to implement 16x20-bit multiplication.
-
-\bigskip
-A way of mapping such elements in coarse grain synthesis is the wrap-extract-unwrap method:
-
-\begin{itemize}
-\item {\bf wrap} \\
-Identify candidate-cells in the circuit and wrap them in a cell with a constant
-wider bit-width using {\tt techmap}. The wrappers use the same parameters as the original cell, so
-the information about the original width of the ports is preserved. \\
-Then use the {\tt connwrappers} command to connect up the bit-extended in- and
-outputs of the wrapper cells.
-\item {\bf extract} \\
-Now all operations are encoded using the same bit-width as the coarse grain element. The {\tt
-extract} command can be used to replace circuits with cells of the target architecture.
-\item {\bf unwrap} \\
-The remaining wrapper cell can be unwrapped using {\tt techmap}.
-\end{itemize}
-
-\bigskip
-The following sides detail an example that shows how to map MACC operations of
-arbitrary size to MACC cells with a 18x25-bit multiplier and a 48-bit adder (such as
-the Xilinx DSP48 cells).
-\end{frame}
-
-\subsubsection{Example: DSP48\_MACC}
-
-\begin{frame}[t, fragile]{\subsubsecname{} -- 1/13}
-Preconditioning: {\tt macc\_xilinx\_swap\_map.v} \\
-Make sure {\tt A} is the smaller port on all multipliers
-
-\begin{columns}
-\column{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=15]{PRESENTATION_ExAdv/macc_xilinx_swap_map.v}
-\column{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=16]{PRESENTATION_ExAdv/macc_xilinx_swap_map.v}
-\end{columns}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsubsecname{} -- 2/13}
-Wrapping multipliers: {\tt macc\_xilinx\_wrap\_map.v}
-
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=23]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=24, lastline=46]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
-\end{columns}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsubsecname{} -- 3/13}
-Wrapping adders: {\tt macc\_xilinx\_wrap\_map.v}
-
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=48, lastline=67]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=68, lastline=89]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
-\end{columns}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsubsecname{} -- 4/13}
-Extract: {\tt macc\_xilinx\_xmap.v}
-
-\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=1,  lastline=17]{PRESENTATION_ExAdv/macc_xilinx_xmap.v}
-
-.. simply use the same wrapping commands on this module as on the design to create a template for the {\tt extract} command.
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsubsecname{} -- 5/13}
-Unwrapping multipliers: {\tt macc\_xilinx\_unwrap\_map.v}
-
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=1,  lastline=17]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=18, lastline=30]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
-\end{columns}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsubsecname{} -- 6/13}
-Unwrapping adders: {\tt macc\_xilinx\_unwrap\_map.v}
-
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=32, lastline=48]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=49, lastline=61]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
-\end{columns}
-\end{frame}
-
-\begin{frame}[fragile]{\subsubsecname{} -- 7/13}
-\hfil\begin{tabular}{cc}
-{\tt test1} & {\tt test2} \\
-\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=1, lastline=6, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} &
-\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=8, lastline=13, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} \\
-$\downarrow$ & $\downarrow$ \\
-\end{tabular}
-\vskip-0.5cm
-\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-                            read_verilog macc_xilinx_test.v
-                            hierarchy -check
-\end{lstlisting}
-\vskip-0.5cm
-\hfil\begin{tabular}{cc}
-$\downarrow$ & $\downarrow$ \\
-\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} &
-\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2a.pdf}} \\
-\end{tabular}
-\end{frame}
-
-\begin{frame}[fragile]{\subsubsecname{} -- 8/13}
-\hfil\begin{tabular}{cc}
-{\tt test1} & {\tt test2} \\
-\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} &
-\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2a.pdf}} \\
-$\downarrow$ & $\downarrow$ \\
-\end{tabular}
-\vskip-0.2cm
-\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-                         techmap -map macc_xilinx_swap_map.v ;;
-\end{lstlisting}
-\vskip-0.2cm
-\hfil\begin{tabular}{cc}
-$\downarrow$ & $\downarrow$ \\
-\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1b.pdf}} &
-\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2b.pdf}} \\
-\end{tabular}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsubsecname{} -- 9/13}
-Wrapping in {\tt test1}:
-\begin{columns}
-\column[t]{5cm}
-\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1b.pdf}}\vss}
-\column[t]{6cm}
-\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-techmap -map macc_xilinx_wrap_map.v
-
-connwrappers -unsigned $__mul_wrapper \
-                            Y Y_WIDTH \
-             -unsigned $__add_wrapper \
-                            Y Y_WIDTH ;;
-\end{lstlisting}
-\end{columns}
-
-\vskip1cm
-\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsubsecname{} -- 10/13}
-Wrapping in {\tt test2}:
-\begin{columns}
-\column[t]{5cm}
-\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2b.pdf}}\vss}
-\column[t]{6cm}
-\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-techmap -map macc_xilinx_wrap_map.v
-
-connwrappers -unsigned $__mul_wrapper \
-                            Y Y_WIDTH \
-             -unsigned $__add_wrapper \
-                            Y Y_WIDTH ;;
-\end{lstlisting}
-\end{columns}
-
-\vskip1cm
-\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsubsecname{} -- 11/13}
-Extract in {\tt test1}:
-\begin{columns}
-\column[t]{4.5cm}
-\vbox to 0cm{
-\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-design -push
-read_verilog macc_xilinx_xmap.v
-techmap -map macc_xilinx_swap_map.v
-techmap -map macc_xilinx_wrap_map.v;;
-design -save __macc_xilinx_xmap
-design -pop
-\end{lstlisting}
-\vss}
-\column[t]{5.5cm}
-\vskip-1cm
-\begin{lstlisting}[linewidth=5.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-extract -constports -ignore_parameters \
-        -map %__macc_xilinx_xmap       \
-        -swap $__add_wrapper A,B ;;
-\end{lstlisting}
-\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf}}\vss}
-\end{columns}
-
-\vskip2cm
-\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1d.pdf}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsubsecname{} -- 12/13}
-Extract in {\tt test2}:
-\begin{columns}
-\column[t]{4.5cm}
-\vbox to 0cm{
-\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-design -push
-read_verilog macc_xilinx_xmap.v
-techmap -map macc_xilinx_swap_map.v
-techmap -map macc_xilinx_wrap_map.v;;
-design -save __macc_xilinx_xmap
-design -pop
-\end{lstlisting}
-\vss}
-\column[t]{5.5cm}
-\vskip-1cm
-\begin{lstlisting}[linewidth=5.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-extract -constports -ignore_parameters \
-        -map %__macc_xilinx_xmap       \
-        -swap $__add_wrapper A,B ;;
-\end{lstlisting}
-\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf}}\vss}
-\end{columns}
-
-\vskip2cm
-\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsubsecname{} -- 13/13}
-Unwrap in {\tt test2}:
-
-\hfil\begin{tikzpicture}
-\node at (0,0) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}};
-\node at (0,-4) {\includegraphics[width=8cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2e.pdf}};
-\node at (1,-1.7) {\begin{lstlisting}[linewidth=5.5cm, frame=single, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-techmap -map macc_xilinx_unwrap_map.v ;;
-\end{lstlisting}};
-\draw[-latex] (4,-0.7) .. controls (5,-1.7) .. (4,-2.7);
-\end{tikzpicture}
-\end{frame}
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Automatic design changes}
-
-\begin{frame}
-\subsectionpage
-\subsectionpagesuffix
-\end{frame}
-
-\subsubsection{Changing the design from Yosys}
-
-\begin{frame}{\subsubsecname}
-Yosys commands can be used to change the design in memory. Examples of this are:
-
-\begin{itemize}
-\item {\bf Changes in design hierarchy} \\
-Commands such as {\tt flatten} and {\tt submod} can be used to change the design hierarchy, i.e.
-flatten the hierarchy or moving parts of a module to a submodule. This has applications in synthesis
-scripts as well as in reverse engineering and analysis.
-
-\item {\bf Behavioral changes} \\
-Commands such as {\tt techmap} can be used to make behavioral changes to the design, for example
-changing asynchronous resets to synchronous resets. This has applications in design space exploration
-(evaluation of various architectures for one circuit).
-\end{itemize}
-\end{frame}
-
-\subsubsection{Example: Async reset to sync reset}
-
-\begin{frame}[t, fragile]{\subsubsecname}
-The following techmap map file replaces all positive-edge async reset flip-flops with
-positive-edge sync reset flip-flops. The code is taken from the example Yosys script
-for ASIC synthesis of the Amber ARMv2 CPU.
-
-\begin{columns}
-\column[t]{6cm}
-\vbox to 0cm{
-\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
-(* techmap_celltype = "$adff" *)
-module adff2dff (CLK, ARST, D, Q);
-
-    parameter WIDTH = 1;
-    parameter CLK_POLARITY = 1;
-    parameter ARST_POLARITY = 1;
-    parameter ARST_VALUE = 0;
-
-    input CLK, ARST;
-    input [WIDTH-1:0] D;
-    output reg [WIDTH-1:0] Q;
-
-    wire [1023:0] _TECHMAP_DO_ = "proc";
-
-    wire _TECHMAP_FAIL_ = !CLK_POLARITY || !ARST_POLARITY;
-\end{lstlisting}
-\vss}
-\column[t]{4cm}
-\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
-// ..continued..
-
-
-    always @(posedge CLK)
-        if (ARST)
-            Q <= ARST_VALUE;
-        else
-             <= D;
-
-endmodule
-\end{lstlisting}
-\end{columns}
-
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Summary}
-
-\begin{frame}{\subsecname}
-\begin{itemize}
-\item A lot can be achieved in Yosys just with the standard set of commands.
-\item The commands {\tt techmap} and {\tt extract} can be used to prototype many complex synthesis tasks.
-\end{itemize}
-
-\bigskip
-\bigskip
-\begin{center}
-Questions?
-\end{center}
-
-\bigskip
-\bigskip
-\begin{center}
-\url{https://yosyshq.net/yosys/}
-\end{center}
-\end{frame}
-
diff --git a/yosys/manual/PRESENTATION_ExAdv/Makefile b/yosys/manual/PRESENTATION_ExAdv/Makefile
deleted file mode 100644
index 993a9d9e10c..00000000000
--- a/yosys/manual/PRESENTATION_ExAdv/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-
-all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
-		macc_simple_xmap.pdf macc_xilinx_xmap.pdf
-
-select.pdf: select.v select.ys
-	../../yosys select.ys
-
-red_or3x1.pdf: red_or3x1_*
-	../../yosys red_or3x1_test.ys
-
-sym_mul.pdf: sym_mul_*
-	../../yosys sym_mul_test.ys
-
-mymul.pdf: mymul_*
-	../../yosys mymul_test.ys
-
-mulshift.pdf: mulshift_*
-	../../yosys mulshift_test.ys
-
-addshift.pdf: addshift_*
-	../../yosys addshift_test.ys
-
-macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
-	../../yosys macc_simple_test.ys
-
-macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
-	../../yosys macc_xilinx_test.ys
-
diff --git a/yosys/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys b/yosys/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
deleted file mode 100644
index f3e8af4f046..00000000000
--- a/yosys/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
+++ /dev/null
@@ -1,43 +0,0 @@
-read_verilog macc_xilinx_test.v
-read_verilog -lib -icells macc_xilinx_unwrap_map.v
-read_verilog -lib -icells macc_xilinx_xmap.v
-hierarchy -check ;;
-
-show -prefix macc_xilinx_test1a -format pdf -notitle test1
-show -prefix macc_xilinx_test2a -format pdf -notitle test2
-
-techmap -map macc_xilinx_swap_map.v;;
-
-show -prefix macc_xilinx_test1b -format pdf -notitle test1
-show -prefix macc_xilinx_test2b -format pdf -notitle test2
-
-techmap -map macc_xilinx_wrap_map.v
-
-connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
-             -unsigned $__add_wrapper Y Y_WIDTH;;
-
-show -prefix macc_xilinx_test1c -format pdf -notitle test1
-show -prefix macc_xilinx_test2c -format pdf -notitle test2
-
-design -push
-read_verilog macc_xilinx_xmap.v
-techmap -map macc_xilinx_swap_map.v
-techmap -map macc_xilinx_wrap_map.v;;
-design -save __macc_xilinx_xmap
-design -pop
-
-extract -constports -ignore_parameters \
-        -map %__macc_xilinx_xmap       \
-        -swap $__add_wrapper A,B ;;
-
-show -prefix macc_xilinx_test1d -format pdf -notitle test1
-show -prefix macc_xilinx_test2d -format pdf -notitle test2
-
-techmap -map macc_xilinx_unwrap_map.v;;
-
-show -prefix macc_xilinx_test1e -format pdf -notitle test1
-show -prefix macc_xilinx_test2e -format pdf -notitle test2
-
-design -load __macc_xilinx_xmap
-show -prefix macc_xilinx_xmap -format pdf -notitle
-
diff --git a/yosys/manual/PRESENTATION_ExOth.tex b/yosys/manual/PRESENTATION_ExOth.tex
deleted file mode 100644
index 3f5113e3cf4..00000000000
--- a/yosys/manual/PRESENTATION_ExOth.tex
+++ /dev/null
@@ -1,227 +0,0 @@
-
-\section{Yosys by example -- Beyond Synthesis}
-
-\begin{frame}
-\sectionpage
-\end{frame}
-
-\begin{frame}{Overview}
-This section contains 2 subsections:
-\begin{itemize}
-\item Interactive Design Investigation
-\item Symbolic Model Checking
-\end{itemize}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Interactive Design Investigation}
-
-\begin{frame}
-\subsectionpage
-\subsectionpagesuffix
-\end{frame}
-
-\begin{frame}{\subsecname}
-Yosys can also be used to investigate designs (or netlists created
-from other tools).
-
-\begin{itemize}
-\item
-The selection mechanism (see slides ``Using Selections''), especially patterns such
-as {\tt \%ci} and {\tt \%co}, can be used to figure out how parts of the design
-are connected.
-
-\item
-Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used
-to transform the design into an equivalent design that is easier to analyse.
-
-\item
-Commands such as {\tt eval} and {\tt sat} can be used to investigate the
-behavior of the circuit.
-\end{itemize}
-\end{frame}
-
-\begin{frame}[t, fragile]{Example: Reorganizing a module}
-\begin{columns}
-\column[t]{4cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExOth/scrambler.v}
-\column[t]{7cm}
-\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]
-read_verilog scrambler.v
-
-hierarchy; proc;;
-
-cd scrambler
-submod -name xorshift32 \
-           xs %c %ci %D %c %ci:+[D] %D \
-           %ci*:-$dff xs %co %ci %d
-\end{lstlisting}
-\end{columns}
-
-\hfil\includegraphics[width=11cm,trim=0 0cm 0 1.5cm]{PRESENTATION_ExOth/scrambler_p01.pdf}
-
-\hfil\includegraphics[width=11cm,trim=0 0cm 0 2cm]{PRESENTATION_ExOth/scrambler_p02.pdf}
-\end{frame}
-
-\begin{frame}[t, fragile]{Example: Analysis of circuit behavior}
-\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-> read_verilog scrambler.v
-> hierarchy; proc;; cd scrambler
-> submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d
-
-> cd xorshift32
-> rename n2 in
-> rename n1 out
-
-> eval -set in 1 -show out
-Eval result: \out = 270369.
-
-> eval -set in 270369 -show out
-Eval result: \out = 67634689.
-
-> sat -set out 632435482
-Signal Name                 Dec        Hex                                   Bin
--------------------- ---------- ---------- -------------------------------------
-\in                   745495504   2c6f5bd0      00101100011011110101101111010000
-\out                  632435482   25b2331a      00100101101100100011001100011010
-\end{lstlisting}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Symbolic Model Checking}
-
-\begin{frame}
-\subsectionpage
-\subsectionpagesuffix
-\end{frame}
-
-\begin{frame}{\subsecname}
-Symbolic Model Checking (SMC) is used to formally prove that a circuit has
-(or has not) a given property.
-
-\bigskip
-One application is Formal Equivalence Checking: Proving that two circuits
-are identical. For example this is a very useful feature when debugging custom
-passes in Yosys.
-
-\bigskip
-Other applications include checking if a module conforms to interface
-standards.
-
-\bigskip
-The {\tt sat} command in Yosys can be used to perform Symbolic Model Checking.
-\end{frame}
-
-\begin{frame}[t]{Example: Formal Equivalence Checking (1/2)}
-Remember the following example?
-\vskip1em
-
-\vbox to 0cm{
-\vskip-0.3cm
-\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/techmap_01_map.v}
-}\vbox to 0cm{
-\vskip-0.5cm
-\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExSyn/techmap_01.v}
-\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/techmap_01.ys}}
-
-\vskip5cm\hskip5cm
-Lets see if it is correct..
-\end{frame}
-
-\begin{frame}[t, fragile]{Example: Formal Equivalence Checking (2/2)}
-\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]
-# read test design
-read_verilog techmap_01.v
-hierarchy -top test
-
-# create two version of the design: test_orig and test_mapped
-copy test test_orig
-rename test test_mapped
-
-# apply the techmap only to test_mapped
-techmap -map techmap_01_map.v test_mapped
-
-# create a miter circuit to test equivalence
-miter -equiv -make_assert -make_outputs test_orig test_mapped miter
-flatten miter
-
-# run equivalence check
-sat -verify -prove-asserts -show-inputs -show-outputs miter
-\end{lstlisting}
-
-\dots
-\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
-Solving problem with 945 variables and 2505 clauses..
-SAT proof finished - no model found: SUCCESS!
-\end{lstlisting}
-\end{frame}
-
-\begin{frame}[t, fragile]{Example: Symbolic Model Checking (1/2)}
-\small
-The following AXI4 Stream Master has a bug. But the bug is not exposed if the
-slave keeps {\tt tready} asserted all the time. (Something a test bench might do.)
-
-\medskip
-Symbolic Model Checking can be used to expose the bug and find a sequence
-of values for {\tt tready} that yield the incorrect behavior.
-
-\vskip-1em
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{5pt}{6pt}\selectfont, language=verilog]{PRESENTATION_ExOth/axis_master.v}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{5pt}{6pt}\selectfont, language=verilog]{PRESENTATION_ExOth/axis_test.v}
-\end{columns}
-\end{frame}
-
-\begin{frame}[t, fragile]{Example: Symbolic Model Checking (2/2)}
-\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]
-read_verilog -sv axis_master.v axis_test.v
-hierarchy -top axis_test
-
-proc; flatten;;
-sat -seq 50 -prove-asserts
-\end{lstlisting}
-
-\bigskip
-\dots with unmodified {\tt axis\_master.v}:
-\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
-Solving problem with 159344 variables and 442126 clauses..
-SAT proof finished - model found: FAIL!
-\end{lstlisting}
-
-\bigskip
-\dots with fixed {\tt axis\_master.v}:
-\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
-Solving problem with 159144 variables and 441626 clauses..
-SAT proof finished - no model found: SUCCESS!
-\end{lstlisting}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Summary}
-
-\begin{frame}{\subsecname}
-\begin{itemize}
-\item Yosys provides useful features beyond synthesis.
-\item The commands {\tt sat} and {\tt eval} can be used to analyse the behavior of a circuit.
-\item The {\tt sat} command can also be used for symbolic model checking.
-\item This can be useful for debugging and testing designs and Yosys extensions alike.
-\end{itemize}
-
-\bigskip
-\bigskip
-\begin{center}
-Questions?
-\end{center}
-
-\bigskip
-\bigskip
-\begin{center}
-\url{https://yosyshq.net/yosys/}
-\end{center}
-\end{frame}
-
diff --git a/yosys/manual/PRESENTATION_ExOth/.gitignore b/yosys/manual/PRESENTATION_ExOth/.gitignore
deleted file mode 100644
index cf658897d52..00000000000
--- a/yosys/manual/PRESENTATION_ExOth/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-*.dot
diff --git a/yosys/manual/PRESENTATION_ExOth/Makefile b/yosys/manual/PRESENTATION_ExOth/Makefile
deleted file mode 100644
index 4864d8d5203..00000000000
--- a/yosys/manual/PRESENTATION_ExOth/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-
-all: scrambler_p01.pdf scrambler_p02.pdf equiv.log axis_test.log
-
-scrambler_p01.pdf: scrambler.ys scrambler.v
-	../../yosys scrambler.ys
-
-scrambler_p02.pdf: scrambler_p01.pdf
-
-equiv.log: equiv.ys
-	../../yosys -l equiv.log_new equiv.ys
-	mv equiv.log_new equiv.log
-
-axis_test.log: axis_test.ys axis_master.v axis_test.v
-	../../yosys -l axis_test.log_new axis_test.ys
-	mv axis_test.log_new axis_test.log
-
diff --git a/yosys/manual/PRESENTATION_ExOth/equiv.ys b/yosys/manual/PRESENTATION_ExOth/equiv.ys
deleted file mode 100644
index 8db0a88a5fb..00000000000
--- a/yosys/manual/PRESENTATION_ExOth/equiv.ys
+++ /dev/null
@@ -1,17 +0,0 @@
-# read test design
-read_verilog ../PRESENTATION_ExSyn/techmap_01.v
-hierarchy -top test
-
-# create two version of the design: test_orig and test_mapped
-copy test test_orig
-rename test test_mapped
-
-# apply the techmap only to test_mapped
-techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped
-
-# create a miter circuit to test equivalence
-miter -equiv -make_assert -make_outputs test_orig test_mapped miter
-flatten miter
-
-# run equivalence check
-sat -verify -prove-asserts -show-inputs -show-outputs miter
diff --git a/yosys/manual/PRESENTATION_ExSyn.tex b/yosys/manual/PRESENTATION_ExSyn.tex
deleted file mode 100644
index d7cfdc6f2fc..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn.tex
+++ /dev/null
@@ -1,515 +0,0 @@
-
-\section{Yosys by example -- Synthesis}
-
-\begin{frame}
-\sectionpage
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Typical Phases of a Synthesis Flow}
-
-\begin{frame}{\subsecname}
-\begin{itemize}
-\item Reading and elaborating the design
-\item Higher-level synthesis and optimization
-\begin{itemize}
-\item Converting {\tt always}-blocks to logic and registers
-\item Perform coarse-grain optimizations (resource sharing, const folding, ...)
-\item Handling of memories and other coarse-grain blocks
-\item Extracting and optimizing finite state machines
-\end{itemize}
-\item Convert remaining logic to bit-level logic functions
-\item Perform optimizations on bit-level logic functions
-\item Map bit-level logic gates and registers to cell library
-\item Write results to output file
-\end{itemize}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Reading the design}
-
-\begin{frame}[fragile]{\subsecname}
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-read_verilog file1.v
-read_verilog -I include_dir -D enable_foo -D WIDTH=12 file2.v
-read_verilog -lib cell_library.v
-
-verilog_defaults -add -I include_dir
-read_verilog file3.v
-read_verilog file4.v
-verilog_defaults -clear
-
-verilog_defaults -push
-verilog_defaults -add -I include_dir
-read_verilog file5.v
-read_verilog file6.v
-verilog_defaults -pop
-\end{lstlisting}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Design elaboration}
-
-\begin{frame}[fragile]{\subsecname}
-During design elaboration Yosys figures out how the modules are hierarchically
-connected. It also re-runs the AST parts of the Verilog frontend to create
-all needed variations of parametric modules.
-
-\bigskip
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-# simplest form. at least this version should be used after reading all input files
-#
-hierarchy
-
-# recommended form. fails if parts of the design hierarchy are missing, removes
-# everything that is unreachable from the top module, and marks the top module.
-#
-hierarchy -check -top top_module
-\end{lstlisting}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{The {\tt proc} command}
-
-\begin{frame}[fragile]{\subsecname}
-The Verilog frontend converts {\tt always}-blocks to RTL netlists for the
-expressions and ``processes'' for the control- and memory elements.
-
-\medskip
-The {\tt proc} command transforms this ``processes'' to netlists of RTL
-multiplexer and register cells.
-
-\medskip
-The {\tt proc} command is actually a macro-command that calls the following
-other commands:
-
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-proc_clean      # remove empty branches and processes
-proc_rmdead     # remove unreachable branches
-proc_init       # special handling of "initial" blocks
-proc_arst       # identify modeling of async resets
-proc_mux        # convert decision trees to multiplexer networks
-proc_dff        # extract registers from processes
-proc_clean      # if all went fine, this should remove all the processes
-\end{lstlisting}
-
-\medskip
-Many commands can not operate on modules with ``processes'' in them. Usually
-a call to {\tt proc} is the first command in the actual synthesis procedure
-after design elaboration.
-\end{frame}
-
-\begin{frame}[fragile]{\subsecname{} -- Example 1/3}
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_01.v}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/proc_01.ys}
-\end{columns}
-\hfil\includegraphics[width=8cm,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/proc_01.pdf}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsecname{} -- Example 2/3}
-\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -2.5cm]{PRESENTATION_ExSyn/proc_02.pdf}\vss}
-\vskip-1cm
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_02.v}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/proc_02.ys}
-\end{columns}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsecname{} -- Example 3/3}
-\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -1.5cm]{PRESENTATION_ExSyn/proc_03.pdf}\vss}
-\vskip-1cm
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/proc_03.ys}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_03.v}
-\end{columns}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{The {\tt opt} command}
-
-\begin{frame}[fragile]{\subsecname}
-The {\tt opt} command implements a series of simple optimizations. It also
-is a macro command that calls other commands:
-
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-opt_expr                # const folding and simple expression rewriting
-opt_merge -nomux        # merging identical cells
-
-do
-    opt_muxtree         # remove never-active branches from multiplexer tree
-    opt_reduce          # consolidate trees of boolean ops to reduce functions
-    opt_merge           # merging identical cells
-    opt_rmdff           # remove/simplify registers with constant inputs
-    opt_clean           # remove unused objects (cells, wires) from design
-    opt_expr            # const folding and simple expression rewriting
-while [changed design]
-\end{lstlisting}
-
-The command {\tt clean} can be used as alias for {\tt opt\_clean}. And {\tt ;;}
-can be used as shortcut for {\tt clean}. For example:
-
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-proc; opt; memory; opt_expr;; fsm;;
-\end{lstlisting}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsecname{} -- Example 1/4}
-\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -0.5cm]{PRESENTATION_ExSyn/opt_01.pdf}\vss}
-\vskip-1cm
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/opt_01.ys}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_01.v}
-\end{columns}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsecname{} -- Example 2/4}
-\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm 0cm]{PRESENTATION_ExSyn/opt_02.pdf}\vss}
-\vskip-1cm
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/opt_02.ys}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_02.v}
-\end{columns}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsecname{} -- Example 3/4}
-\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -2cm]{PRESENTATION_ExSyn/opt_03.pdf}\vss}
-\vskip-1cm
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/opt_03.ys}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_03.v}
-\end{columns}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsecname{} -- Example 4/4}
-\vbox to 0cm{\hskip6cm\includegraphics[width=6cm,trim=0cm 0cm 0cm -3cm]{PRESENTATION_ExSyn/opt_04.pdf}\vss}
-\vskip-1cm
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_04.v}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/opt_04.ys}
-\end{columns}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{When to use {\tt opt} or {\tt clean}}
-
-\begin{frame}{\subsecname}
-Usually it does not hurt to call {\tt opt} after each regular command in the
-synthesis script. But it increases the synthesis time, so it is favourable
-to only call {\tt opt} when an improvement can be achieved.
-
-\bigskip
-The designs in {\tt yosys-bigsim} are a good playground for experimenting with
-the effects of calling {\tt opt} in various places of the flow.
-
-\bigskip
-It generally is a good idea to call {\tt opt} before inherently expensive
-commands such as {\tt sat} or {\tt freduce}, as the possible gain is much
-higher in this cases as the possible loss.
-
-\bigskip
-The {\tt clean} command on the other hand is very fast and many commands leave
-a mess (dangling signal wires, etc). For example, most commands do not remove
-any wires or cells. They just change the connections and depend on a later
-call to clean to get rid of the now unused objects. So the occasional {\tt ;;}
-is a good idea in every synthesis script.
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{The {\tt memory} command}
-
-\begin{frame}[fragile]{\subsecname}
-In the RTL netlist, memory reads and writes are individual cells. This makes
-consolidating the number of ports for a memory easier. The {\tt memory}
-transforms memories to an implementation. Per default that is logic for address
-decoders and registers. It also is a macro command that calls other commands:
-
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-# this merges registers into the memory read- and write cells.
-memory_dff
-
-# this collects all read and write cells for a memory and transforms them
-# into one multi-port memory cell.
-memory_collect
-
-# this takes the multi-port memory cell and transforms it to address decoder
-# logic and registers. This step is skipped if "memory" is called with -nomap.
-memory_map
-\end{lstlisting}
-
-\bigskip
-Usually it is preferred to use architecture-specific RAM resources for memory.
-For example:
-
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-memory -nomap; techmap -map my_memory_map.v; memory_map
-\end{lstlisting}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsecname{} -- Example 1/2}
-\vbox to 0cm{\includegraphics[width=0.7\linewidth,trim=0cm 0cm 0cm -10cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss}
-\vskip-1cm
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/memory_01.ys}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/memory_01.v}
-\end{columns}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsecname{} -- Example 2/2}
-\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -5cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss}
-\vskip-1cm
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/memory_02.v}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/memory_02.ys}
-\end{columns}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{The {\tt fsm} command}
-
-\begin{frame}[fragile]{\subsecname{}}
-The {\tt fsm} command identifies, extracts, optimizes (re-encodes), and
-re-synthesizes finite state machines. It again is a macro that calls
-a series of other commands:
-
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-fsm_detect          # unless got option -nodetect
-fsm_extract
-
-fsm_opt
-clean
-fsm_opt
-
-fsm_expand          # if got option -expand
-clean               # if got option -expand
-fsm_opt             # if got option -expand
-
-fsm_recode          # unless got option -norecode
-
-fsm_info
-
-fsm_export          # if got option -export
-fsm_map             # unless got option -nomap
-\end{lstlisting}
-\end{frame}
-
-\begin{frame}{\subsecname{} -- details}
-Some details on the most important commands from the {\tt fsm\_*} group:
-
-\bigskip
-The {\tt fsm\_detect} command identifies FSM state registers and marks them
-with the {\tt (* fsm\_encoding = "auto" *)} attribute, if they do not have the
-{\tt fsm\_encoding} set already. Mark registers with {\tt (* fsm\_encoding =
-"none" *)} to disable FSM optimization for a register.
-
-\bigskip
-The {\tt fsm\_extract} command replaces the entire FSM (logic and state
-registers) with a {\tt \$fsm} cell.
-
-\bigskip
-The commands {\tt fsm\_opt} and {\tt fsm\_recode} can be used to optimize the
-FSM.
-
-\bigskip
-Finally the {\tt fsm\_map} command can be used to convert the (optimized) {\tt
-\$fsm} cell back to logic and registers.
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{The {\tt techmap} command}
-
-\begin{frame}[t]{\subsecname}
-\vbox to 0cm{\includegraphics[width=12cm,trim=-15cm 0cm 0cm -20cm]{PRESENTATION_ExSyn/techmap_01.pdf}\vss}
-\vskip-0.8cm
-The {\tt techmap} command replaces cells with implementations given as
-verilog source. For example implementing a 32 bit adder using 16 bit adders:
-
-\vbox to 0cm{
-\vskip-0.3cm
-\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/techmap_01_map.v}
-}\vbox to 0cm{
-\vskip-0.5cm
-\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExSyn/techmap_01.v}
-\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/techmap_01.ys}
-}
-\end{frame}
-
-\begin{frame}[t]{\subsecname{} -- stdcell mapping}
-When {\tt techmap} is used without a map file, it uses a built-in map file
-to map all RTL cell types to a generic library of built-in logic gates and registers.
-
-\bigskip
-\begin{block}{The built-in logic gate types are:}
-{\tt \$\_NOT\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
-\end{block}
-
-\bigskip
-\begin{block}{The register types are:}
-{\tt \$\_SR\_NN\_ \$\_SR\_NP\_ \$\_SR\_PN\_ \$\_SR\_PP\_ \\
-\$\_DFF\_N\_ \$\_DFF\_P\_ \\
-\$\_DFF\_NN0\_ \$\_DFF\_NN1\_ \$\_DFF\_NP0\_ \$\_DFF\_NP1\_ \\
-\$\_DFF\_PN0\_ \$\_DFF\_PN1\_ \$\_DFF\_PP0\_ \$\_DFF\_PP1\_ \\
-\$\_DFFSR\_NNN\_ \$\_DFFSR\_NNP\_ \$\_DFFSR\_NPN\_ \$\_DFFSR\_NPP\_ \\
-\$\_DFFSR\_PNN\_ \$\_DFFSR\_PNP\_ \$\_DFFSR\_PPN\_ \$\_DFFSR\_PPP\_ \\
-\$\_DLATCH\_N\_ \$\_DLATCH\_P\_}
-\end{block}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{The {\tt abc} command}
-
-\begin{frame}{\subsecname}
-The {\tt abc} command provides an interface to ABC\footnote[frame]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}},
-an open source tool for low-level logic synthesis.
-
-\medskip
-The {\tt abc} command processes a netlist of internal gate types and can perform:
-\begin{itemize}
-\item logic minimization (optimization)
-\item mapping of logic to standard cell library (liberty format)
-\item mapping of logic to k-LUTs (for FPGA synthesis)
-\end{itemize}
-
-\medskip
-Optionally {\tt abc} can process registers from one clock domain and perform
-sequential optimization (such as register balancing).
-
-\medskip
-ABC is also controlled using scripts. An ABC script can be specified to use
-more advanced ABC features. It is also possible to write the design with
-{\tt write\_blif} and load the output file into ABC outside of Yosys.
-\end{frame}
-
-\begin{frame}[fragile]{\subsecname{} -- Example}
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/abc_01.v}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/abc_01.ys}
-\end{columns}
-\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/abc_01.pdf}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Other special-purpose mapping commands}
-
-\begin{frame}{\subsecname}
-\begin{block}{\tt dfflibmap}
-This command maps the internal register cell types to the register types
-described in a liberty file.
-\end{block}
-
-\bigskip
-\begin{block}{\tt hilomap}
-Some architectures require special driver cells for driving a constant hi or lo
-value. This command replaces simple constants with instances of such driver cells.
-\end{block}
-
-\bigskip
-\begin{block}{\tt iopadmap}
-Top-level input/outputs must usually be implemented using special I/O-pad cells.
-This command inserts this cells to the design.
-\end{block}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Example Synthesis Script}
-
-\begin{frame}[fragile]{\subsecname}
-\begin{columns}
-\column[t]{4cm}
-\begin{lstlisting}[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=ys]
-# read and elaborate design
-read_verilog cpu_top.v cpu_ctrl.v cpu_regs.v
-read_verilog -D WITH_MULT cpu_alu.v
-hierarchy -check -top cpu_top
-
-# high-level synthesis
-proc; opt; fsm;; memory -nomap; opt
-
-# substitute block rams
-techmap -map map_rams.v
-
-# map remaining memories
-memory_map
-
-# low-level synthesis
-techmap; opt; flatten;; abc -lut6
-techmap -map map_xl_cells.v
-
-# add clock buffers
-select -set xl_clocks t:FDRE %x:+FDRE[C] t:FDRE %d
-iopadmap -inpad BUFGP O:I @xl_clocks
-
-# add io buffers
-select -set xl_nonclocks w:* t:BUFGP %x:+BUFGP[I] %d
-iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl_nonclocks
-
-# write synthesis results
-write_edif synth.edif
-\end{lstlisting}
-\column[t]{6cm}
-\vskip1cm
-\begin{block}{Teaser / Outlook}
-\small\parbox{6cm}{
-The weird {\tt select} expressions at the end of this script are discussed in
-the next part (Section 3, ``Advanced Synthesis'') of this presentation.}
-\end{block}
-\end{columns}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Summary}
-
-\begin{frame}{\subsecname}
-\begin{itemize}
-\item Yosys provides commands for each phase of the synthesis.
-\item Each command solves a (more or less) simple problem.
-\item Complex commands are often only front-ends to simple commands.
-\item {\tt proc; opt; fsm; opt; memory; opt; techmap; opt; abc;;}
-\end{itemize}
-
-\bigskip
-\bigskip
-\begin{center}
-Questions?
-\end{center}
-
-\bigskip
-\bigskip
-\begin{center}
-\url{https://yosyshq.net/yosys/}
-\end{center}
-\end{frame}
-
diff --git a/yosys/manual/PRESENTATION_ExSyn/.gitignore b/yosys/manual/PRESENTATION_ExSyn/.gitignore
deleted file mode 100644
index cf658897d52..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-*.dot
diff --git a/yosys/manual/PRESENTATION_ExSyn/Makefile b/yosys/manual/PRESENTATION_ExSyn/Makefile
deleted file mode 100644
index c34eae3ffcf..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-
-TARGETS += proc_01 proc_02 proc_03
-TARGETS += opt_01 opt_02 opt_03 opt_04
-TARGETS += memory_01 memory_02
-TARGETS += techmap_01
-TARGETS += abc_01
-
-all: $(addsuffix .pdf,$(TARGETS))
-
-define make_pdf_template
-$(1).pdf: $(1)*.v $(1)*.ys
-	../../yosys -p 'script $(1).ys; show -notitle -prefix $(1) -format pdf'
-endef
-
-$(foreach trg,$(TARGETS),$(eval $(call make_pdf_template,$(trg))))
-
-clean:
-	rm -f $(addsuffix .pdf,$(TARGETS))
-	rm -f $(addsuffix .dot,$(TARGETS))
-
diff --git a/yosys/manual/PRESENTATION_ExSyn/abc_01.v b/yosys/manual/PRESENTATION_ExSyn/abc_01.v
deleted file mode 100644
index 3bc6863538d..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/abc_01.v
+++ /dev/null
@@ -1,10 +0,0 @@
-module test(input clk, a, b, c,
-            output reg y);
-
-	reg [2:0] q1, q2;
-	always @(posedge clk) begin
-		q1 <= { a, b, c };
-		q2 <= q1;
-		y <= ^q2;
-	end
-endmodule
diff --git a/yosys/manual/PRESENTATION_ExSyn/abc_01.ys b/yosys/manual/PRESENTATION_ExSyn/abc_01.ys
deleted file mode 100644
index bb0b3780ff3..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/abc_01.ys
+++ /dev/null
@@ -1,5 +0,0 @@
-read_verilog abc_01.v
-read_verilog -lib abc_01_cells.v
-hierarchy -check -top test
-proc; opt; techmap
-abc -dff -liberty abc_01_cells.lib;;
diff --git a/yosys/manual/PRESENTATION_ExSyn/abc_01_cells.lib b/yosys/manual/PRESENTATION_ExSyn/abc_01_cells.lib
deleted file mode 100644
index bf6b34788d0..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/abc_01_cells.lib
+++ /dev/null
@@ -1,54 +0,0 @@
-// test comment
-/* test comment */
-library(demo) {
-  cell(BUF) {
-    area: 6;
-    pin(A) { direction: input; }
-    pin(Y) { direction: output;
-              function: "A"; }
-  }
-  cell(NOT) {
-    area: 3;
-    pin(A) { direction: input; }
-    pin(Y) { direction: output;
-              function: "A'"; }
-  }
-  cell(NAND) {
-    area: 4;
-    pin(A) { direction: input; }
-    pin(B) { direction: input; }
-    pin(Y) { direction: output;
-             function: "(A*B)'"; }
-  }
-  cell(NOR) {
-    area: 4;
-    pin(A) { direction: input; }
-    pin(B) { direction: input; }
-    pin(Y) { direction: output;
-             function: "(A+B)'"; }
-  }
-  cell(DFF) {
-    area: 18;
-    ff(IQ, IQN) { clocked_on: C;
-                  next_state: D; }
-    pin(C) { direction: input;
-                 clock: true; }
-    pin(D) { direction: input; }
-    pin(Q) { direction: output;
-              function: "IQ"; }
-  }
-  cell(DFFSR) {
-    area: 18;
-    ff(IQ, IQN) { clocked_on: C;
-                  next_state: D;
-                      preset: S;
-                       clear: R; }
-    pin(C) { direction: input;
-                 clock: true; }
-    pin(D) { direction: input; }
-    pin(Q) { direction: output;
-              function: "IQ"; }
-    pin(S) { direction: input; }
-    pin(R) { direction: input; }
-  }
-}
diff --git a/yosys/manual/PRESENTATION_ExSyn/abc_01_cells.v b/yosys/manual/PRESENTATION_ExSyn/abc_01_cells.v
deleted file mode 100644
index 44409479895..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/abc_01_cells.v
+++ /dev/null
@@ -1,40 +0,0 @@
-
-module BUF(A, Y);
-input A;
-output Y = A;
-endmodule
-
-module NOT(A, Y);
-input A;
-output Y = ~A;
-endmodule
-
-module NAND(A, B, Y);
-input A, B;
-output Y = ~(A & B);
-endmodule
-
-module NOR(A, B, Y);
-input A, B;
-output Y = ~(A | B);
-endmodule
-
-module DFF(C, D, Q);
-input C, D;
-output reg Q;
-always @(posedge C)
-	Q <= D;
-endmodule
-
-module DFFSR(C, D, Q, S, R);
-input C, D, S, R;
-output reg Q;
-always @(posedge C, posedge S, posedge R)
-	if (S)
-		Q <= 1'b1;
-	else if (R)
-		Q <= 1'b0;
-	else
-		Q <= D;
-endmodule
-
diff --git a/yosys/manual/PRESENTATION_ExSyn/opt_01.v b/yosys/manual/PRESENTATION_ExSyn/opt_01.v
deleted file mode 100644
index 5d3c1ea49fc..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/opt_01.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input A, B, output Y);
-assign Y = A ? A ? B : 1'b1 : B;
-endmodule
diff --git a/yosys/manual/PRESENTATION_ExSyn/opt_01.ys b/yosys/manual/PRESENTATION_ExSyn/opt_01.ys
deleted file mode 100644
index 34ed123bee4..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/opt_01.ys
+++ /dev/null
@@ -1,3 +0,0 @@
-read_verilog opt_01.v
-hierarchy -check -top test
-opt
diff --git a/yosys/manual/PRESENTATION_ExSyn/opt_02.v b/yosys/manual/PRESENTATION_ExSyn/opt_02.v
deleted file mode 100644
index 762fc1a8993..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/opt_02.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module test(input A, output Y, Z);
-assign Y = A == A, Z = A != A;
-endmodule
diff --git a/yosys/manual/PRESENTATION_ExSyn/opt_02.ys b/yosys/manual/PRESENTATION_ExSyn/opt_02.ys
deleted file mode 100644
index fc92a636ed4..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/opt_02.ys
+++ /dev/null
@@ -1,3 +0,0 @@
-read_verilog opt_02.v
-hierarchy -check -top test
-opt
diff --git a/yosys/manual/PRESENTATION_ExSyn/opt_03.v b/yosys/manual/PRESENTATION_ExSyn/opt_03.v
deleted file mode 100644
index 134161bb80a..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/opt_03.v
+++ /dev/null
@@ -1,4 +0,0 @@
-module test(input  [3:0] A, B,
-            output [3:0] Y, Z);
-assign Y = A + B, Z = B + A;
-endmodule
diff --git a/yosys/manual/PRESENTATION_ExSyn/opt_03.ys b/yosys/manual/PRESENTATION_ExSyn/opt_03.ys
deleted file mode 100644
index 282f06ddecc..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/opt_03.ys
+++ /dev/null
@@ -1,3 +0,0 @@
-read_verilog opt_03.v
-hierarchy -check -top test
-opt
diff --git a/yosys/manual/PRESENTATION_ExSyn/opt_04.v b/yosys/manual/PRESENTATION_ExSyn/opt_04.v
deleted file mode 100644
index 2ed44763953..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/opt_04.v
+++ /dev/null
@@ -1,19 +0,0 @@
-module test(input CLK, ARST,
-            output [7:0] Q1, Q2, Q3);
-
-wire NO_CLK = 0;
-
-always @(posedge CLK, posedge ARST)
-	if (ARST)
-		Q1 <= 42;
-
-always @(posedge NO_CLK, posedge ARST)
-	if (ARST)
-		Q2 <= 42;
-	else
-		Q2 <= 23;
-
-always @(posedge CLK)
-	Q3 <= 42;
-
-endmodule
diff --git a/yosys/manual/PRESENTATION_ExSyn/opt_04.ys b/yosys/manual/PRESENTATION_ExSyn/opt_04.ys
deleted file mode 100644
index f5ddae29f20..00000000000
--- a/yosys/manual/PRESENTATION_ExSyn/opt_04.ys
+++ /dev/null
@@ -1,3 +0,0 @@
-read_verilog opt_04.v
-hierarchy -check -top test
-proc; opt
diff --git a/yosys/manual/PRESENTATION_Intro.tex b/yosys/manual/PRESENTATION_Intro.tex
deleted file mode 100644
index 1c3b79fa034..00000000000
--- a/yosys/manual/PRESENTATION_Intro.tex
+++ /dev/null
@@ -1,956 +0,0 @@
-
-\section{Introduction to Yosys}
-
-\begin{frame}
-\sectionpage
-\end{frame}
-
-\iffalse
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Representations of (digital) Circuits}
-
-\begin{frame}[t]{\subsecname}
-\begin{itemize}
-	\item Graphical
-		\begin{itemize}
-			\item \alert<1>{Schematic Diagram}
-			\item \alert<2>{Physical Layout}
-		\end{itemize}
-	\bigskip
-	\item Non-graphical
-		\begin{itemize}
-			\item \alert<3>{Netlists}
-			\item \alert<4>{Hardware Description Languages (HDLs)}
-		\end{itemize}
-\end{itemize}
-\bigskip
-\begin{block}{Definition:
-\only<1>{Schematic Diagram}%
-\only<2>{Physical Layout}%
-\only<3>{Netlists}%
-\only<4>{Hardware Description Languages (HDLs)}}
-\only<1>{
-	Graphical representation of the circuit topology. Circuit elements
-	are represented by symbols and electrical connections by lines. The geometric
-	layout is for readability only.
-}%
-\only<2>{
-	The actual physical geometry of the device (PCB or ASIC manufacturing masks).
-	This is the final product of the design process.
-}%
-\only<3>{
-	A list of circuit elements and a list of connections. This is the raw circuit
-	topology.
-}%
-\only<4>{
-	Computer languages (like programming languages) that can be used to describe
-	circuits. HDLs are much more powerful in describing huge circuits than
-	schematic diagrams.
-}%
-\end{block}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\fi
-
-\subsection{Levels of Abstraction for Digital Circuits}
-
-\begin{frame}[t]{\subsecname}
-\begin{itemize}
-	\item \alert<1>{System Level}
-	\item \alert<2>{High Level}
-	\item \alert<3>{Behavioral Level}
-	\item \alert<4>{Register-Transfer Level (RTL)}
-	\item \alert<5>{Logical Gate Level}
-	\item \alert<6>{Physical Gate Level}
-	\item \alert<7>{Switch Level}
-\end{itemize}
-\bigskip
-\begin{block}{Definition:
-\only<1>{System Level}%
-\only<2>{High Level}%
-\only<3>{Behavioral Level}%
-\only<4>{Register-Transfer Level (RTL)}%
-\only<5>{Logical Gate Level}%
-\only<6>{Physical Gate Level}%
-\only<7>{Switch Level}}
-\only<1>{
-	Overall view of the circuit. E.g. block-diagrams or instruction-set architecture descriptions.
-}%
-\only<2>{
-	Functional implementation of circuit in high-level programming language (C, C++, SystemC, Matlab, Python, etc.).
-}%
-\only<3>{
-	Cycle-accurate description of circuit in hardware description language (Verilog, VHDL, etc.).
-}%
-\only<4>{
-	List of registers (flip-flops) and logic functions that calculate the next state from the previous one. Usually
-	a netlist utilizing high-level cells such as adders, multipliers, multiplexer, etc.
-}%
-\only<5>{
-	Netlist of single-bit registers and basic logic gates (such as AND, OR,
-	NOT, etc.). Popular form: And-Inverter-Graphs (AIGs) with pairs of primary
-	inputs and outputs for each register bit.
-}%
-\only<6>{
-	Netlist of cells that actually are available on the target architecture
-	(such as CMOS gates in an ASIC or LUTs in an FPGA). Optimized for
-	area, power, and/or speed (static timing or number of logic levels).
-}%
-\only<7>{
-	Netlist of individual transistors.
-}%
-\end{block}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Digital Circuit Synthesis}
-
-\begin{frame}{\subsecname}
-	Synthesis Tools (such as Yosys) can transform HDL code to circuits:
-
-	\bigskip
-	\begin{center}
-	\begin{tikzpicture}[scale=0.8, every node/.style={transform shape}]
-			\tikzstyle{lvl} = [draw, fill=MyBlue, rectangle, minimum height=2em, minimum width=15em]
-			\node[lvl] (sys) {System Level};
-			\node[lvl] (hl) [below of=sys] {High Level};
-			\node[lvl] (beh) [below of=hl] {Behavioral Level};
-			\node[lvl] (rtl) [below of=beh] {Register-Transfer Level (RTL)};
-			\node[lvl] (lg) [below of=rtl] {Logical Gate Level};
-			\node[lvl] (pg) [below of=lg] {Physical Gate Level};
-			\node[lvl] (sw) [below of=pg] {Switch Level};
-
-			\draw[dotted] (sys.east)  -- ++(1,0) coordinate (sysx);
-			\draw[dotted] (hl.east)  -- ++(1,0) coordinate (hlx);
-			\draw[dotted] (beh.east) -- ++(1,0) coordinate (behx);
-			\draw[dotted] (rtl.east) -- ++(1,0) coordinate (rtlx);
-			\draw[dotted] (lg.east)  -- ++(1,0) coordinate (lgx);
-			\draw[dotted] (pg.east)  -- ++(1,0) coordinate (pgx);
-			\draw[dotted] (sw.east)  -- ++(1,0) coordinate (swx);
-
-			\draw[gray,|->] (sysx) -- node[right] {System Design} (hlx);
-			\draw[|->|] (hlx) -- node[right] {High Level Synthesis (HLS)} (behx);
-			\draw[->|] (behx) -- node[right] {Behavioral Synthesis} (rtlx);
-			\draw[->|] (rtlx) -- node[right] {RTL Synthesis} (lgx);
-			\draw[->|] (lgx) -- node[right] {Logic Synthesis} (pgx);
-			\draw[gray,->|] (pgx) -- node[right] {Cell Library} (swx);
-
-			\draw[dotted] (behx) -- ++(4,0) coordinate (a);
-			\draw[dotted] (pgx) -- ++(4,0) coordinate (b);
-			\draw[|->|] (a) -- node[right] {Yosys} (b);
-	\end{tikzpicture}
-	\end{center}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{What Yosys can and can't do}
-
-\begin{frame}{\subsecname}
-
-Things Yosys can do:
-\begin{itemize}
-\item Read and process (most of) modern Verilog-2005 code.
-\item Perform all kinds of operations on netlist (RTL, Logic, Gate).
-\item Perform logic optimizations and gate mapping with ABC\footnote[frame]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}}.
-\end{itemize}
-
-\bigskip
-Things Yosys can't do:
-\begin{itemize}
-\item Process high-level languages such as C/C++/SystemC.
-\item Create physical layouts (place\&route).
-\end{itemize}
-
-\bigskip
-A typical flow combines Yosys with with a low-level implementation tool, such
-as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC designs.
-
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Yosys Data- and Control-Flow}
-
-\begin{frame}{\subsecname}
-	A (usually short) synthesis script controls Yosys.
-
-	This scripts contain three types of commands:
-	\begin{itemize}
-	\item {\bf Frontends}, that read input files (usually Verilog).
-	\item {\bf Passes}, that perform transformations on the design in memory.
-	\item {\bf Backends}, that write the design in memory to a file (various formats are available: Verilog, BLIF, EDIF, SPICE, BTOR, \dots).
-	\end{itemize}
-
-	\bigskip
-	\begin{center}
-	\begin{tikzpicture}[scale=0.6, every node/.style={transform shape}]
-		\path (-1.5,3) coordinate (cursor);
-		\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
-		\draw[fill=orange!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Frontend} ++(1,3) coordinate (cursor);
-		\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
-		\draw[fill=green!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Pass} ++(1,3) coordinate (cursor);
-		\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
-		\draw[fill=green!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Pass} ++(1,3) coordinate (cursor);
-		\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
-		\draw[fill=green!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Pass} ++(1,3) coordinate (cursor);
-		\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
-		\draw[fill=orange!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Backend} ++(1,3) coordinate (cursor);
-		\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
-
-		\path (-3,-0.5) coordinate (cursor);
-		\draw (cursor) -- node[below] {HDL} ++(3,0) coordinate (cursor);
-		\draw[|-|] (cursor) -- node[below] {Internal Format (RTLIL)} ++(8,0) coordinate (cursor);
-		\draw (cursor) -- node[below] {Netlist} ++(3,0);
-
-		\path (-3,3.5) coordinate (cursor);
-		\draw[-] (cursor) -- node[above] {High-Level} ++(3,0) coordinate (cursor);
-		\draw[-] (cursor) -- ++(8,0) coordinate (cursor);
-		\draw[->] (cursor) -- node[above] {Low-Level} ++(3,0);
-	\end{tikzpicture}
-	\end{center}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Program Components and Data Formats}
-
-\begin{frame}{\subsecname}
-	\begin{center}
-	\begin{tikzpicture}[scale=0.6, every node/.style={transform shape}]
-		\tikzstyle{process} = [draw, fill=green!10, rectangle, minimum height=3em, minimum width=10em, node distance=15em]
-		\tikzstyle{data} = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=15em]
-		\node[process] (vlog) {Verilog Frontend};
-		\node[process, dashed, fill=green!5] (vhdl) [right of=vlog] {VHDL Frontend};
-		\node[process] (ilang) [right of=vhdl] {Other Frontends};
-		\node[data] (ast) [below of=vlog, node distance=5em, xshift=7.5em] {AST};
-		\node[process] (astfe) [below of=ast, node distance=5em] {AST Frontend};
-		\node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL};
-		\node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes};
-		\node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend};
-		\node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend};
-		\node[process, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends};
-
-		\draw[-latex] (vlog) -- (ast);
-		\draw[-latex] (vhdl) -- (ast);
-		\draw[-latex] (ast) -- (astfe);
-		\draw[-latex] (astfe) -- (rtlil);
-		\draw[-latex] (ilang) -- (rtlil);
-		\draw[latex-latex] (rtlil) -- (pass);
-		\draw[-latex] (rtlil) -- (vlbe);
-		\draw[-latex] (rtlil) -- (ilangbe);
-		\draw[-latex] (rtlil) -- (otherbe);
-	\end{tikzpicture}
-	\end{center}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Example Project}
-
-\begin{frame}[t]{\subsecname}
-The following slides cover an example project. This project contains three files:
-\begin{itemize}
-\item A simple ASIC synthesis script
-\item A digital design written in Verilog
-\item A simple CMOS cell library
-\end{itemize}
-\vfill
-Direct link to the files: \\ \footnotesize
-\url{https://github.com/YosysHQ/yosys/tree/master/manual/PRESENTATION_Intro}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\begin{frame}[t]{\subsecname{} -- Synthesis Script}
-
-\setbeamercolor{alerted text}{fg=white,bg=red}
-
-\begin{minipage}[t]{6cm}
-\tt\scriptsize
-{\color{YosysGreen}\# read design}\\
-\boxalert<1>{read\_verilog counter.v}\\
-\boxalert<2>{hierarchy -check -top counter}
-
-\medskip
-{\color{YosysGreen}\# the high-level stuff}\\
-\boxalert<3>{proc}; \boxalert<4>{opt}; \boxalert<5>{fsm}; \boxalert<6>{opt}; \boxalert<7>{memory}; \boxalert<8>{opt}
-
-\medskip
-{\color{YosysGreen}\# mapping to internal cell library}\\
-\boxalert<9>{techmap}; \boxalert<10>{opt}
-\end{minipage}
-\begin{minipage}[t]{5cm}
-\tt\scriptsize
-{\color{YosysGreen}\# mapping flip-flops to mycells.lib}\\
-\boxalert<11>{dfflibmap -liberty mycells.lib}
-
-\medskip
-{\color{YosysGreen}\# mapping logic to mycells.lib}\\
-\boxalert<12>{abc -liberty mycells.lib}
-
-\medskip
-{\color{YosysGreen}\# cleanup}\\
-\boxalert<13>{clean}
-
-\medskip
-{\color{YosysGreen}\# write synthesized design}\\
-\boxalert<14>{write\_verilog synth.v}
-\end{minipage}
-
-\vskip1cm
-
-\begin{block}{Command: \tt
-\only<1>{read\_verilog counter.v}%
-\only<2>{hierarchy -check -top counter}%
-\only<3>{proc}%
-\only<4>{opt}%
-\only<5>{fsm}%
-\only<6>{opt}%
-\only<7>{memory}%
-\only<8>{opt}%
-\only<9>{techmap}%
-\only<10>{opt}%
-\only<11>{dfflibmap -liberty mycells.lib}%
-\only<12>{abc -liberty mycells.lib}%
-\only<13>{clean}%
-\only<14>{write\_verilog synth.v}}
-\only<1>{
-	Read Verilog source file and convert to internal representation.
-}%
-\only<2>{
-	Elaborate the design hierarchy. Should always be the first
-	command after reading the design. Can re-run AST front-end.
-}%
-\only<3>{
-	Convert ``processes'' (the internal representation of behavioral
-	Verilog code) into multiplexers and registers.
-}%
-\only<4>{
-	Perform some basic optimizations and cleanups.
-}%
-\only<5>{
-	Analyze and optimize finite state machines.
-}%
-\only<6>{
-	Perform some basic optimizations and cleanups.
-}%
-\only<7>{
-	Analyze memories and create circuits to implement them.
-}%
-\only<8>{
-	Perform some basic optimizations and cleanups.
-}%
-\only<9>{
-	Map coarse-grain RTL cells (adders, etc.) to fine-grain
-	logic gates (AND, OR, NOT, etc.).
-}%
-\only<10>{
-	Perform some basic optimizations and cleanups.
-}%
-\only<11>{
-	Map registers to available hardware flip-flops.
-}%
-\only<12>{
-	Map logic to available hardware gates.
-}%
-\only<13>{
-	Clean up the design (just the last step of {\tt opt}).
-}%
-\only<14>{
-	Write final synthesis result to output file.
-}%
-\end{block}
-
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v}
-\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v}
-\end{frame}
-
-\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib}
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib}
-\end{columns}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Running the Synthesis Script}
-
-\begin{frame}[t, fragile]{\subsecname{} -- Step 1/4}
-\begin{verbatim}
-read_verilog counter.v
-hierarchy -check -top counter
-\end{verbatim}
-
-\vfill
-\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_00.pdf}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsecname{} -- Step 2/4}
-\begin{verbatim}
-proc; opt; fsm; opt; memory; opt
-\end{verbatim}
-
-\vfill
-\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_01.pdf}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsecname{} -- Step 3/4}
-\begin{verbatim}
-techmap; opt
-\end{verbatim}
-
-\vfill
-\includegraphics[width=\linewidth,trim=0 0cm 0 2cm]{PRESENTATION_Intro/counter_02.pdf}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsecname{} -- Step 4/4}
-\begin{verbatim}
-dfflibmap -liberty mycells.lib
-abc -liberty mycells.lib
-clean
-\end{verbatim}
-
-\vfill\hfil
-\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{The synth command}
-
-\begin{frame}[fragile]{\subsecname{}}
-Yosys contains a default (recommended example) synthesis script in form of the
-{\tt synth} command. The following commands are executed by this synthesis command:
-
-\begin{columns}
-\column[t]{5cm}
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-begin:
-    hierarchy -check [-top <top>]
-
-coarse:
-    proc
-    opt
-    wreduce
-    alumacc
-    share
-    opt
-    fsm
-    opt -fast
-    memory -nomap
-    opt_clean
-\end{lstlisting}
-\column[t]{5cm}
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-fine:
-    opt -fast -full
-    memory_map
-    opt -full
-    techmap
-    opt -fast
-
-abc:
-    abc -fast
-    opt -fast
-\end{lstlisting}
-\end{columns}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Yosys Commands}
-
-\begin{frame}[fragile]{\subsecname{} 1/3 \hspace{0pt plus 1 filll} (excerpt)}
-Command reference:
-\begin{itemize}
-\item Use ``{\tt help}'' for a command list and ``{\tt help \it command}'' for details.
-\item Or run ``{\tt yosys -H}'' or ``{\tt yosys -h \it command}''.
-\item Or go to \url{https://yosyshq.net/yosys/documentation.html}.
-\end{itemize}
-
-\bigskip
-Commands for design navigation and investigation:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-    cd                   # a shortcut for 'select -module <name>'
-    ls                   # list modules or objects in modules
-    dump                 # print parts of the design in RTLIL format
-    show                 # generate schematics using graphviz
-    select               # modify and view the list of selected objects
-\end{lstlisting}
-
-\bigskip
-Commands for executing scripts or entering interactive mode:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-    shell                # enter interactive command mode
-    history              # show last interactive commands
-    script               # execute commands from script file
-    tcl                  # execute a TCL script file
-\end{lstlisting}
-\end{frame}
-
-\begin{frame}[fragile]{\subsecname{} 2/3 \hspace{0pt plus 1 filll} (excerpt)}
-Commands for reading and elaborating the design:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-    read_rtlil           # read modules from RTLIL file
-    read_verilog         # read modules from Verilog file
-    hierarchy            # check, expand and clean up design hierarchy
-\end{lstlisting}
-
-\bigskip
-Commands for high-level synthesis:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-    proc                 # translate processes to netlists
-    fsm                  # extract and optimize finite state machines
-    memory               # translate memories to basic cells
-    opt                  # perform simple optimizations
-\end{lstlisting}
-
-\bigskip
-Commands for technology mapping:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-    techmap              # generic technology mapper
-    abc                  # use ABC for technology mapping
-    dfflibmap            # technology mapping of flip-flops
-    hilomap              # technology mapping of constant hi- and/or lo-drivers
-    iopadmap             # technology mapping of i/o pads (or buffers)
-    flatten              # flatten design
-\end{lstlisting}
-\end{frame}
-
-\begin{frame}[fragile]{\subsecname{} 3/3 \hspace{0pt plus 1 filll} (excerpt)}
-Commands for writing the results:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-    write_blif           # write design to BLIF file
-    write_btor           # write design to BTOR file
-    write_edif           # write design to EDIF netlist file
-    write_rtlil          # write design to RTLIL file
-    write_spice          # write design to SPICE netlist file
-    write_verilog        # write design to Verilog file
-\end{lstlisting}
-
-\bigskip
-Script-Commands for standard synthesis tasks:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-    synth                # generic synthesis script
-    synth_xilinx         # synthesis for Xilinx FPGAs
-\end{lstlisting}
-
-\bigskip
-Commands for model checking:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-    sat                  # solve a SAT problem in the circuit
-    miter                # automatically create a miter circuit
-    scc                  # detect strongly connected components (logic loops)
-\end{lstlisting}
-
-\bigskip
-... and many many more.
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{More Verilog Examples}
-
-\begin{frame}[fragile]{\subsecname{} 1/3}
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
-module detectprime(a, y);
-    input [4:0] a;
-    output y;
-
-    integer i, j;
-    reg [31:0] lut;
-
-    initial begin
-        for (i = 0; i < 32; i = i+1) begin
-            lut[i] = i > 1;
-            for (j = 2; j*j <= i; j = j+1)
-                if (i % j == 0)
-                    lut[i] = 0;
-        end
-    end
-
-    assign y = lut[a];
-endmodule
-\end{lstlisting}
-\end{frame}
-
-\begin{frame}[fragile]{\subsecname{} 2/3}
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
-module carryadd(a, b, y);
-    parameter WIDTH = 8;
-    input [WIDTH-1:0] a, b;
-    output [WIDTH-1:0] y;
-
-    genvar i;
-    generate
-        for (i = 0; i < WIDTH; i = i+1) begin:STAGE
-            wire IN1 = a[i], IN2 = b[i];
-            wire C, Y;
-            if (i == 0)
-                assign C = IN1 & IN2, Y = IN1 ^ IN2;
-            else
-                assign C = (IN1 & IN2) | ((IN1 | IN2) & STAGE[i-1].C),
-                       Y = IN1 ^ IN2 ^ STAGE[i-1].C;
-            assign y[i] = Y;
-        end
-    endgenerate
-endmodule
-\end{lstlisting}
-\end{frame}
-
-\begin{frame}[fragile]{\subsecname{} 3/3}
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{7pt}{8.5pt}\selectfont, language=Verilog]
-module cam(clk, wr_enable, wr_addr, wr_data, rd_data, rd_addr, rd_match);
-    parameter WIDTH = 8;
-    parameter DEPTH = 16;
-    localparam ADDR_BITS = $clog2(DEPTH-1);
-
-    input clk, wr_enable;
-    input [ADDR_BITS-1:0] wr_addr;
-    input [WIDTH-1:0] wr_data, rd_data;
-    output reg [ADDR_BITS-1:0] rd_addr;
-    output reg rd_match;
-
-    integer i;
-    reg [WIDTH-1:0] mem [0:DEPTH-1];
-
-    always @(posedge clk) begin
-        rd_addr <= 'bx;
-        rd_match <= 0;
-        for (i = 0; i < DEPTH; i = i+1)
-            if (mem[i] == rd_data) begin
-                rd_addr <= i;
-                rd_match <= 1;
-            end
-        if (wr_enable)
-            mem[wr_addr] <= wr_data;
-    end
-endmodule
-\end{lstlisting}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Currently unsupported Verilog-2005 language features}
-
-\begin{frame}{\subsecname}
-\begin{itemize}
-\item Tri-state logic
-\item The wor/wand wire types (maybe for 0.5)
-\item Latched logic (is synthesized as logic with feedback loops)
-\item Some non-synthesizable features that should be ignored in synthesis are not supported by the parser and cause a parser error (file a bug report if you encounter this problem)
-\end{itemize}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Verification of Yosys}
-
-\begin{frame}{\subsecname}
-Continuously checking the correctness of Yosys and making sure that new features
-do not break old ones is a high priority in Yosys.
-
-\bigskip
-Two external test suites have been built for Yosys: VlogHammer and yosys-bigsim
-(see next slides)
-
-\bigskip
-In addition to that, yosys comes with $\approx\!200$ test cases used in ``{\tt make test}''.
-
-\bigskip
-A debug build of Yosys also contains a lot of asserts and checks the integrity of
-the internal state after each command.
-\end{frame}
-
-\begin{frame}[fragile]{\subsecname{} -- VlogHammer}
-VlogHammer is a Verilog regression test suite developed to test the different
-subsystems in Yosys by comparing them to each other and to the output created
-by some other tools (Xilinx Vivado, Xilinx XST, Altera Quartus II, ...).
-
-\bigskip
-Yosys Subsystems tested: Verilog frontend, const folding, const eval, technology mapping,
-simulation models, SAT models.
-
-\bigskip
-Thousands of auto-generated test cases containing code such as:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
-assign y9 = $signed(((+$signed((^(6'd2 ** a2))))<$unsigned($unsigned(((+a3))))));
-assign y10 = (-((+((+{2{(~^p13)}})))^~(!{{b5,b1,a0},(a1&p12),(a4+a3)})));
-assign y11 = (~&(-{(-3'sd3),($unsigned($signed($unsigned({p0,b4,b1}))))}));
-\end{lstlisting}
-
-\bigskip
-Some bugs in Yosys where found and fixed thanks to VlogHammer. Over 50 bugs in
-the other tools used as external reference where found and reported so far.
-\end{frame}
-
-\begin{frame}{\subsecname{} -- yosys-bigsim}
-yosys-bigsim is a collection of real-world open-source Verilog designs and test
-benches. yosys-bigsim compares the testbench outputs of simulations of the original
-Verilog code and synthesis results.
-
-\bigskip
-The following designs are included in yosys-bigsim (excerpt):
-\begin{itemize}
-\item {\tt openmsp430} -- an MSP430 compatible 16 bit CPU
-\item {\tt aes\_5cycle\_2stage} -- an AES encryption core
-\item {\tt softusb\_navre} -- an AVR compatible 8 bit CPU
-\item {\tt amber23} -- an ARMv2 compatible 32 bit CPU
-\item {\tt lm32} -- another 32 bit CPU from Lattice Semiconductor
-\item {\tt verilog-pong} -- a hardware pong game with VGA output
-\item {\tt elliptic\_curve\_group} -- ECG point-add and point-scalar-mul core
-\item {\tt reed\_solomon\_decoder} -- a Reed-Solomon Error Correction Decoder
-\end{itemize}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Benefits of Open Source HDL Synthesis}
-
-\begin{frame}{\subsecname}
-\begin{itemize}
-\item Cost (also applies to ``free as in free beer'' solutions)
-\item Availability and Reproducibility
-\item Framework- and all-in-one-aspects
-\item Educational Tool
-\end{itemize}
-
-\bigskip
-
-Yosys is open source under the ISC license.
-\end{frame}
-
-\begin{frame}{\subsecname{} -- 1/3}
-\begin{itemize}
-\item Cost (also applies to ``free as in free beer'' solutions): \smallskip\par
-Today the cost for a mask set in $\unit[180]{nm}$ technology is far less than
-the cost for the design tools needed to design the mask layouts. Open Source
-ASIC flows are an important enabler for ASIC-level Open Source Hardware.
-
-\bigskip
-\item Availability and Reproducibility: \smallskip\par
-If you are a researcher who is publishing, you want to use tools that everyone
-else can also use. Even if most universities have access to all major
-commercial tools, you usually do not have easy access to the version that was
-used in a research project a couple of years ago. With Open Source tools you
-can even release the source code of the tool you have used alongside your data.
-\end{itemize}
-\end{frame}
-
-\begin{frame}{\subsecname{} -- 2/3}
-\begin{itemize}
-\item Framework: \smallskip\par
-Yosys is not only a tool. It is a framework that can be used as basis for other
-developments, so researchers and hackers alike do not need to re-invent the
-basic functionality. Extensibility was one of Yosys' design goals.
-
-\bigskip
-\item All-in-one: \smallskip\par
-Because of the framework characteristics of Yosys, an increasing number of features
-become available in one tool. Yosys not only can be used for circuit synthesis but
-also for formal equivalence checking, SAT solving, and for circuit analysis, to
-name just a few other application domains. With proprietary software one needs to
-learn a new tool for each of these applications.
-\end{itemize}
-\end{frame}
-
-\begin{frame}{\subsecname{} -- 3/3}
-\begin{itemize}
-\item Educational Tool: \smallskip\par
-Proprietary synthesis tools are at times very secretive about their inner
-workings. They often are ``black boxes''. Yosys is very open about its
-internals and it is easy to observe the different steps of synthesis.
-\end{itemize}
-
-\bigskip
-\begin{block}{Yosys is licensed under the ISC license:}
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-\end{block}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Typical Applications for Yosys}
-
-\begin{frame}{\subsecname}
-\begin{itemize}
-\item Synthesis of final production designs
-\item Pre-production synthesis (trial runs before investing in other tools)
-\item Conversion of full-featured Verilog to simple Verilog
-\item Conversion of Verilog to other formats (BLIF, BTOR, etc)
-\item Demonstrating synthesis algorithms (e.g. for educational purposes)
-\item Framework for experimenting with new algorithms
-\item Framework for building custom flows\footnote[frame]{Not limited to synthesis
-but also formal verification, reverse engineering, ...}
-\end{itemize}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Projects (that I know of) using Yosys}
-
-\begin{frame}{\subsecname{} -- (1/2)}
-\begin{itemize}
-\item Ongoing PhD project on coarse grain synthesis \\
-{\setlength{\parindent}{0.5cm}\footnotesize
-Johann Glaser and C. Wolf. Methodology and Example-Driven Interconnect
-Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable
-Architectures. In Jan Haase, editor, \it Models, Methods, and Tools for Complex
-Chip Design. Lecture Notes in Electrical Engineering. Volume 265, 2014, pp
-201-221. Springer, 2013.}
-
-\bigskip
-\item I know several people that use Yosys simply as Verilog frontend for other
-flows (using either the BLIF and BTOR backends).
-
-\bigskip
-\item I know some analog chip designers that use Yosys for small digital
-control logic because it is simpler than setting up a commercial flow.
-\end{itemize}
-\end{frame}
-
-\begin{frame}{\subsecname{} -- (2/2)}
-\begin{itemize}
-\item Efabless
-\begin{itemize}
-\smallskip \item Not much information on the website (\url{http://efabless.com}) yet.
-\smallskip \item Very cheap 180nm prototyping process (partnering with various fabs)
-\smallskip \item A semiconductor company, NOT an EDA company
-\smallskip \item Web-based design environment
-\smallskip \item HDL Synthesis using Yosys
-\smallskip \item Custom place\&route tool
-
-\bigskip
-\item efabless is building an Open Source IC as reference design. \\
-\hskip1cm (to be announced soon: \url{http://www.openic.io})
-\end{itemize}
-\end{itemize}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Supported Platforms}
-
-\begin{frame}{\subsecname}
-\begin{itemize}
-\item Main development OS: Kubuntu 14.04
-\item There is a PPA for ubuntu (not maintained by me)
-\item Any current Debian-based system should work out of the box
-\item When building on other Linux distributions:
-\begin{itemize}
-\item Needs compiler with some C++11 support
-\item See README file for build instructions
-\item Post to the subreddit if you get stuck
-\end{itemize}
-\item Ported to OS X (Darwin) and OpenBSD
-\item Native win32 build with VisualStudio
-\item Cross win32 build with MXE
-\end{itemize}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Other Open Source Tools}
-
-\begin{frame}{\subsecname}
-\begin{itemize}
-\item Icarus Verilog \\
-\smallskip\hskip1cm{}Verilog Simulation (and also a good syntax checker) \\
-\smallskip\hskip1cm{}\url{http://iverilog.icarus.com/}
-
-\bigskip
-\item Qflow (incl. TimberWolf, qrouter and Magic) \\
-\smallskip\hskip1cm{}A complete ASIC synthesis flow, using Yosys and ABC \\
-\smallskip\hskip1cm{}\url{http://opencircuitdesign.com/qflow/}
-
-\bigskip
-\item ABC \\
-\smallskip\hskip1cm{}Logic optimization, technology mapping, and more \\
-\smallskip\hskip1cm{}\url{http://www.eecs.berkeley.edu/~alanmi/abc/}
-\end{itemize}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Yosys needs you}
-
-\begin{frame}{\subsecname}
-\dots as an active user:
-\begin{itemize}
-\item Use Yosys for on your own projects
-\item .. even if you are not using it as final synthesis tool
-\item Join the discussion on the Subreddit
-\item Report bugs and send in feature requests
-\end{itemize}
-
-\bigskip
-\dots as a developer:
-\begin{itemize}
-\item Use Yosys as environment for your (research) work
-\item .. you might also want to look into ABC for logic-level stuff
-\item Fork the project on github or create loadable plugins
-\item We need a VHDL frontend or a good VHDL-to-Verilog converter
-\end{itemize}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Documentation, Downloads, Contacts}
-
-\begin{frame}{\subsecname}
-\begin{itemize}
-\item Website: \\
-\smallskip\hskip1cm\url{https://yosyshq.net/yosys/}
-
-\bigskip
-\item Manual, Command Reference, Application Notes: \\
-\smallskip\hskip1cm\url{https://yosyshq.net/yosys/documentation.html}
-
-\bigskip
-\item Instead of a mailing list we have a SubReddit: \\
-\smallskip\hskip1cm\url{http://www.reddit.com/r/yosys/}
-
-\bigskip
-\item Direct link to the source code: \\
-\smallskip\hskip1cm\url{https://github.com/YosysHQ/yosys}
-\end{itemize}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Summary}
-
-\begin{frame}{\subsecname}
-\begin{itemize}
-\item Yosys is a powerful tool and framework for Verilog synthesis.
-\item It uses a command-based interface and can be controlled by scripts.
-\item By combining existing commands and implementing new commands Yosys can
-be used in a wide range of application far beyond simple synthesis.
-\end{itemize}
-
-\bigskip
-\bigskip
-\begin{center}
-Questions?
-\end{center}
-
-\bigskip
-\bigskip
-\begin{center}
-\url{https://yosyshq.net/yosys/}
-\end{center}
-\end{frame}
-
diff --git a/yosys/manual/PRESENTATION_Intro/.gitignore b/yosys/manual/PRESENTATION_Intro/.gitignore
deleted file mode 100644
index d0c4618ac70..00000000000
--- a/yosys/manual/PRESENTATION_Intro/.gitignore
+++ /dev/null
@@ -1,4 +0,0 @@
-counter_00.dot
-counter_01.dot
-counter_02.dot
-counter_03.dot
diff --git a/yosys/manual/PRESENTATION_Intro/Makefile b/yosys/manual/PRESENTATION_Intro/Makefile
deleted file mode 100644
index abc354e4691..00000000000
--- a/yosys/manual/PRESENTATION_Intro/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-
-all: counter_00.pdf counter_01.pdf counter_02.pdf counter_03.pdf
-
-counter_00.pdf: counter.v counter.ys mycells.lib
-	../../yosys counter.ys
-
-counter_01.pdf: counter_00.pdf
-counter_02.pdf: counter_00.pdf
-counter_03.pdf: counter_00.pdf
-
diff --git a/yosys/manual/PRESENTATION_Intro/counter.ys b/yosys/manual/PRESENTATION_Intro/counter.ys
deleted file mode 100644
index cc4e7cd3199..00000000000
--- a/yosys/manual/PRESENTATION_Intro/counter.ys
+++ /dev/null
@@ -1,27 +0,0 @@
-# read design
-read_verilog counter.v
-hierarchy -check -top counter
-
-show -notitle -stretch -format pdf -prefix counter_00
-
-# the high-level stuff
-proc; opt; memory; opt; fsm; opt
-
-show -notitle -stretch -format pdf -prefix counter_01
-
-# mapping to internal cell library
-techmap; opt
-
-splitnets -ports;;
-show -notitle -stretch -format pdf -prefix counter_02
-
-# mapping flip-flops to mycells.lib
-dfflibmap -liberty mycells.lib
-
-# mapping logic to mycells.lib
-abc -liberty mycells.lib
-
-# cleanup
-clean
-
-show -notitle -stretch -lib mycells.v -format pdf -prefix counter_03
diff --git a/yosys/manual/PRESENTATION_Prog.tex b/yosys/manual/PRESENTATION_Prog.tex
deleted file mode 100644
index b0390cb9977..00000000000
--- a/yosys/manual/PRESENTATION_Prog.tex
+++ /dev/null
@@ -1,596 +0,0 @@
-
-\section{Writing Yosys extensions in C++}
-
-\begin{frame}
-\sectionpage
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Program Components and Data Formats}
-
-\begin{frame}{\subsecname}
-\begin{center}
-\begin{tikzpicture}[scale=0.6, every node/.style={transform shape}]
-	\tikzstyle{process} = [draw, fill=green!10, rectangle, minimum height=3em, minimum width=10em, node distance=15em]
-	\tikzstyle{data} = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=15em]
-	\node[process] (vlog) {Verilog Frontend};
-	\node[process, dashed, fill=green!5] (vhdl) [right of=vlog] {VHDL Frontend};
-	\node[process] (ilang) [right of=vhdl] {Other Frontends};
-	\node[data] (ast) [below of=vlog, node distance=5em, xshift=7.5em] {AST};
-	\node[process] (astfe) [below of=ast, node distance=5em] {AST Frontend};
-	\node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL};
-	\node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes};
-	\node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend};
-	\node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend};
-	\node[process, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends};
-
-	\draw[-latex] (vlog) -- (ast);
-	\draw[-latex] (vhdl) -- (ast);
-	\draw[-latex] (ast) -- (astfe);
-	\draw[-latex] (astfe) -- (rtlil);
-	\draw[-latex] (ilang) -- (rtlil);
-	\draw[latex-latex] (rtlil) -- (pass);
-	\draw[-latex] (rtlil) -- (vlbe);
-	\draw[-latex] (rtlil) -- (ilangbe);
-	\draw[-latex] (rtlil) -- (otherbe);
-\end{tikzpicture}
-\end{center}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Simplified RTLIL Entity-Relationship Diagram}
-
-\begin{frame}{\subsecname}
-Between passses and frontends/backends the design is stored in Yosys' internal
-RTLIL (RTL Intermediate Language) format. For writing Yosys extensions it is
-key to understand this format.
-
-\bigskip
-\begin{center}
-\begin{tikzpicture}[scale=0.6, every node/.style={transform shape}]
-	\tikzstyle{entity} = [draw, fill=gray!10, rectangle, minimum height=3em, minimum width=7em, node distance=5em, font={\ttfamily}]
-	\node[entity] (design) {RTLIL::Design};
-	\node[entity] (module) [right of=design, node distance=11em] {RTLIL::Module} edge [-latex] node[above] {\tiny 1 \hskip3em N} (design);
-
-	\node[entity] (process) [fill=green!10, right of=module, node distance=10em] {RTLIL::Process} (process.west) edge [-latex] (module);
-	\node[entity] (memory) [fill=red!10, below of=process] {RTLIL::Memory} edge [-latex] (module);
-	\node[entity] (wire) [fill=blue!10, above of=process] {RTLIL::Wire} (wire.west) edge [-latex] (module);
-	\node[entity] (cell) [fill=blue!10, above of=wire] {RTLIL::Cell} (cell.west) edge [-latex] (module);
-
-	\node[entity] (case) [fill=green!10, right of=process, node distance=10em] {RTLIL::CaseRule} edge [latex-latex] (process);
-	\node[entity] (sync) [fill=green!10, above of=case] {RTLIL::SyncRule} edge [-latex] (process);
-	\node[entity] (switch) [fill=green!10, below of=case] {RTLIL::SwitchRule} edge [-latex] (case);
-	\draw[latex-] (switch.east) -- ++(1em,0) |- (case.east);
-\end{tikzpicture}
-\end{center}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{RTLIL without memories and processes}
-
-\begin{frame}[fragile]{\subsecname}
-After the commands {\tt proc} and {\tt memory} (or {\tt memory -nomap}), we are
-left with a much simpler version of RTLIL:
-
-\begin{center}
-\begin{tikzpicture}[scale=0.6, every node/.style={transform shape}]
-	\tikzstyle{entity} = [draw, fill=gray!10, rectangle, minimum height=3em, minimum width=7em, node distance=5em, font={\ttfamily}]
-	\node[entity] (design) {RTLIL::Design};
-	\node[entity] (module) [right of=design, node distance=11em] {RTLIL::Module} edge [-latex] node[above] {\tiny 1 \hskip3em N} (design);
-
-	\node[entity] (wire) [fill=blue!10, right of=module, node distance=10em] {RTLIL::Wire} (wire.west) edge [-latex] (module);
-	\node[entity] (cell) [fill=blue!10, above of=wire] {RTLIL::Cell} (cell.west) edge [-latex] (module);
-\end{tikzpicture}
-\end{center}
-
-\bigskip
-Many commands simply choose to only work on this simpler version:
-\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
-for (RTLIL::Module *module : design->selected_modules() {
-    if (module->has_memories_warn() || module->has_processes_warn())
-        continue;
-    ....
-}
-\end{lstlisting}
-
-For simplicity we only discuss this version of RTLIL in this presentation.
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Using dump and show commands}
-
-\begin{frame}{\subsecname}
-\begin{itemize}
-\item The {\tt dump} command prints the design (or parts of it) in the text representation of RTLIL.
-
-\bigskip
-\item The {\tt show} command visualizes how the components in the design are connected.
-\end{itemize}
-
-\bigskip
-When trying to understand what a command does, create a small test case and
-look at the output of {\tt dump} and {\tt show} before and after the command
-has been executed.
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{The RTLIL Data Structures}
-
-\begin{frame}{\subsecname}
-The RTLIL data structures are simple structs utilizing {\tt pool<>} and
-{\tt dict<>} containers (drop-in replacements for {\tt
-std::unordered\_set<>} and {\tt std::unordered\_map<>}).
-
-\bigskip
-\begin{itemize}
-\item Most operations are performed directly on the RTLIL structs without
-setter or getter functions.
-
-\bigskip
-\item In debug builds a consistency checker is run over the in-memory design
-between commands to make sure that the RTLIL representation is intact.
-
-\bigskip
-\item Most RTLIL structs have helper methods that perform the most common operations.
-\end{itemize}
-
-\bigskip
-See {\tt yosys/kernel/rtlil.h} for details.
-\end{frame}
-
-\subsubsection{RTLIL::IdString}
-
-\begin{frame}{\subsubsecname}{}
-{\tt RTLIL::IdString} in many ways behave like a {\tt std::string}. It is used
-for names of RTLIL objects. Internally a RTLIL::IdString object is only a
-single integer.
-
-\medskip
-The first character of a {\tt RTLIL::IdString} specifies if the name is {\it public\/} or {\it private\/}:
-
-\medskip
-\begin{itemize}
-\item {\tt RTLIL::IdString[0] == '\textbackslash\textbackslash'}: \\
-This is a public name. Usually this means it is a name that was declared in a Verilog file.
-
-\bigskip
-\item {\tt RTLIL::IdString[0] == '\$'}: \\
-This is a private name. It was assigned by Yosys.
-\end{itemize}
-
-\bigskip
-Use the {\tt NEW\_ID} macro to create a new unique private name.
-\end{frame}
-
-\subsubsection{RTLIL::Design and RTLIL::Module}
-
-\begin{frame}[t, fragile]{\subsubsecname}
-The {\tt RTLIL::Design} and {\tt RTLIL::Module} structs are the top-level RTLIL
-data structures. Yosys always operates on one active design, but can hold many designs in memory.
-
-\bigskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-struct RTLIL::Design {
-    dict<RTLIL::IdString, RTLIL::Module*> modules_;
-    ...
-};
-
-struct RTLIL::Module {
-    RTLIL::IdString name;
-    dict<RTLIL::IdString, RTLIL::Wire*> wires_;
-    dict<RTLIL::IdString, RTLIL::Cell*> cells_;
-    std::vector<RTLIL::SigSig> connections_;
-    ...
-};
-\end{lstlisting}
-
-(Use the various accessor functions instead of directly working with the {\tt *\_} members.)
-\end{frame}
-
-\subsubsection{The RTLIL::Wire Structure}
-
-\begin{frame}[t, fragile]{\subsubsecname}
-Each wire in the design is represented by a {\tt RTLIL::Wire} struct:
-
-\medskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-struct RTLIL::Wire {
-    RTLIL::IdString name;
-    int width, start_offset, port_id;
-    bool port_input, port_output;
-    ...
-};
-\end{lstlisting}
-
-\medskip
-\hfil\begin{tabular}{p{3cm}l}
-{\tt width} \dotfill & The total number of bits. E.g. 10 for {\tt [9:0]}. \\
-{\tt start\_offset} \dotfill & The lowest bit index. E.g. 3 for {\tt [5:3]}. \\
-{\tt port\_id} \dotfill & Zero for non-ports. Positive index for ports. \\
-{\tt port\_input} \dotfill & True for {\tt input} and {\tt inout} ports. \\
-{\tt port\_output} \dotfill & True for {\tt output} and {\tt inout} ports. \\
-\end{tabular}
-\end{frame}
-
-\subsubsection{RTLIL::State and RTLIL::Const}
-
-\begin{frame}[t, fragile]{\subsubsecname}
-The {\tt RTLIL::State} enum represents a simple 1-bit logic level:
-
-\smallskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-enum RTLIL::State {
-    S0 = 0,
-    S1 = 1,
-    Sx = 2, // undefined value or conflict
-    Sz = 3, // high-impedance / not-connected
-    Sa = 4, // don't care (used only in cases)
-    Sm = 5  // marker (used internally by some passes)
-};
-\end{lstlisting}
-
-\bigskip
-The {\tt RTLIL::Const} struct represents a constant multi-bit value:
-
-\smallskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-struct RTLIL::Const {
-    std::vector<RTLIL::State> bits;
-    ...
-};
-\end{lstlisting}
-
-\bigskip
-Notice that Yosys is not using special {\tt VCC} or {\tt GND} driver cells to represent constants. Instead
-constants are part of the RTLIL representation itself.
-\end{frame}
-
-\subsubsection{The RTLIL::SigSpec Structure}
-
-\begin{frame}[t, fragile]{\subsubsecname}
-The {\tt RTLIL::SigSpec} struct represents a signal vector. Each bit can either be a bit from a wire
-or a constant value.
-
-\bigskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-struct RTLIL::SigBit
-{
-    RTLIL::Wire *wire;
-    union {
-        RTLIL::State data; // used if wire == NULL
-        int offset;        // used if wire != NULL
-    };
-    ...
-};
-
-struct RTLIL::SigSpec {
-    std::vector<RTLIL::SigBit> bits_; // LSB at index 0
-    ...
-};
-\end{lstlisting}
-
-\bigskip
-The {\tt RTLIL::SigSpec} struct has a ton of additional helper methods to compare, analyze, and
-manipulate instances of {\tt RTLIL::SigSpec}.
-\end{frame}
-
-\subsubsection{The RTLIL::Cell Structure}
-
-\begin{frame}[t, fragile]{\subsubsecname (1/2)}
-The {\tt RTLIL::Cell} struct represents an instance of a module or library cell.
-
-\smallskip
-The ports of the cell
-are associated with {\tt RTLIL::SigSpec} instances and the parameters are associated with {\tt RTLIL::Const}
-instances:
-
-\bigskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-struct RTLIL::Cell {
-    RTLIL::IdString name, type;
-    dict<RTLIL::IdString, RTLIL::SigSpec> connections_;
-    dict<RTLIL::IdString, RTLIL::Const> parameters;
-    ...
-};
-\end{lstlisting}
-
-\bigskip
-The {\tt type} may refer to another module in the same design, a cell name from a cell library, or a
-cell name from the internal cell library:
-
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont]
-$not $pos $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor
-$reduce_bool $shl $shr $sshl $sshr $lt $le $eq $ne $eqx $nex $ge $gt $add $sub $mul $div $mod
-$divfloor $modfloor $pow $logic_not $logic_and $logic_or $mux $pmux $slice $concat $lut $assert $sr $dff
-$dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_NOT_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_
-$_SR_NP_ $_SR_PN_ $_SR_PP_ $_DFF_N_ $_DFF_P_ $_DFF_NN0_ $_DFF_NN1_ $_DFF_NP0_ $_DFF_NP1_ $_DFF_PN0_
-$_DFF_PN1_ $_DFF_PP0_ $_DFF_PP1_ $_DFFSR_NNN_ $_DFFSR_NNP_ $_DFFSR_NPN_ $_DFFSR_NPP_ $_DFFSR_PNN_
-$_DFFSR_PNP_ $_DFFSR_PPN_ $_DFFSR_PPP_ $_DLATCH_N_ $_DLATCH_P_ $_DLATCHSR_NNN_ $_DLATCHSR_NNP_
-$_DLATCHSR_NPN_ $_DLATCHSR_NPP_ $_DLATCHSR_PNN_ $_DLATCHSR_PNP_ $_DLATCHSR_PPN_ $_DLATCHSR_PPP_
-\end{lstlisting}
-\end{frame}
-
-\begin{frame}[t, fragile]{\subsubsecname (2/2)}
-Simulation models (i.e. {\it documentation\/} :-) for the internal cell library:
-
-\smallskip
-\hskip2em {\tt yosys/techlibs/common/simlib.v} and \\
-\hskip2em {\tt yosys/techlibs/common/simcells.v}
-
-\bigskip
-The lower-case cell types (such as {\tt \$and}) are parameterized cells of variable
-width. This so-called {\it RTL Cells\/} are the cells described in {\tt simlib.v}.
-
-\bigskip
-The upper-case cell types (such as {\tt \$\_AND\_}) are single-bit cells that are not
-parameterized. This so-called {\it Internal Logic Gates} are the cells described
-in {\tt simcells.v}.
-
-\bigskip
-The consistency checker also checks the interfaces to the internal cell library.
-If you want to use private cell types for your own purposes, use the {\tt \$\_\_}-prefix
-to avoid name collisions.
-\end{frame}
-
-\subsubsection{Connecting wires or constant drivers}
-
-\begin{frame}[t, fragile]{\subsubsecname}
-Additional connections between wires or between wires and constants are modelled using
-{\tt RTLIL::Module::connections}:
-
-\bigskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-typedef std::pair<RTLIL::SigSpec, RTLIL::SigSpec> RTLIL::SigSig;
-
-struct RTLIL::Module {
-    ...
-    std::vector<RTLIL::SigSig> connections_;
-    ...
-};
-\end{lstlisting}
-
-\bigskip
-{\tt RTLIL::SigSig::first} is the driven signal and {\tt RTLIL::SigSig::second} is the driving signal.
-Example usage (setting wire {\tt foo} to value {\tt 42}):
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-module->connect(module->wire("\\foo"),
-                RTLIL::SigSpec(42, module->wire("\\foo")->width));
-\end{lstlisting}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Creating modules from scratch}
-
-\begin{frame}[t, fragile]{\subsecname}
-Let's create the following module using the RTLIL API:
-
-\smallskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
-module absval(input signed [3:0] a, output [3:0] y);
-    assign y = a[3] ? -a : a;
-endmodule
-\end{lstlisting}
-
-\smallskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-RTLIL::Module *module = new RTLIL::Module;
-module->name = "\\absval";
-
-RTLIL::Wire *a = module->addWire("\\a", 4);
-a->port_input = true;
-a->port_id = 1;
-
-RTLIL::Wire *y = module->addWire("\\y", 4);
-y->port_output = true;
-y->port_id = 2;
-
-RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4);
-module->addNeg(NEW_ID, a, a_inv, true);
-module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 1, 3), y);
-
-module->fixup_ports();
-\end{lstlisting}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Modifying modules}
-
-\begin{frame}{\subsecname}
-Most commands modify existing modules, not create new ones.
-
-When modifying existing modules, stick to the following DOs and DON'Ts:
-
-\begin{itemize}
-\item Do not remove wires. Simply disconnect them and let a successive {\tt clean} command worry about removing it.
-
-\item Use {\tt module->fixup\_ports()} after changing the {\tt port\_*} properties of wires.
-
-\item You can safely remove cells or change the {\tt connections} property of a cell, but be careful when
-changing the size of the {\tt SigSpec} connected to a cell port.
-
-\item Use the {\tt SigMap} helper class (see next slide) when you need a unique handle for each signal bit.
-\end{itemize}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Using the SigMap helper class}
-
-\begin{frame}[t, fragile]{\subsecname}
-Consider the following module:
-
-\smallskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
-module test(input a, output x, y);
-    assign x = a, y = a;
-endmodule
-\end{lstlisting}
-
-In this case {\tt a}, {\tt x}, and {\tt y} are all different names for the same signal. However:
-
-\smallskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-RTLIL::SigSpec a(module->wire("\\a")), x(module->wire("\\x")),
-                                       y(module->wire("\\y"));
-log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
-\end{lstlisting}
-
-The {\tt SigMap} helper class can be used to map all such aliasing signals to a
-unique signal from the group (usually the wire that is directly driven by a cell or port).
-
-\smallskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-SigMap sigmap(module);
-log("%d %d %d\n", sigmap(a) == sigmap(x), sigmap(x) == sigmap(y),
-                  sigmap(y) == sigmap(a)); // will print "1 1 1"
-\end{lstlisting}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Printing log messages}
-
-\begin{frame}[t, fragile]{\subsecname}
-The {\tt log()} function is a {\tt printf()}-like function that can be used to create log messages.
-
-\medskip
-Use {\tt log\_signal()} to create a C-string for a SigSpec object\footnote[frame]{The pointer returned
-by {\tt log\_signal()} is automatically freed by the log framework at a later time.}:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-log("Mapped signal x: %s\n", log_signal(sigmap(x)));
-\end{lstlisting}
-
-\medskip
-Use {\tt log\_id()} to create a C-string for an {\tt RTLIL::IdString}:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-log("Name of this module: %s\n", log_id(module->name));
-\end{lstlisting}
-
-\medskip
-Use {\tt log\_header()} and {\tt log\_push()}/{\tt log\_pop()} to structure log messages:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-log_header(design, "Doing important stuff!\n");
-log_push();
-for (int i = 0; i < 10; i++)
-    log("Log message #%d.\n", i);
-log_pop();
-\end{lstlisting}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Error handling}
-
-\begin{frame}[t, fragile]{\subsecname}
-Use {\tt log\_error()} to report a non-recoverable error:
-
-\medskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-if (design->modules.count(module->name) != 0)
-    log_error("A module with the name %s already exists!\n",
-            RTLIL::id2cstr(module->name));
-\end{lstlisting}
-
-\bigskip
-Use {\tt log\_cmd\_error()} to report a recoverable error:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-if (design->selection_stack.back().empty())
-    log_cmd_error("This command can't operator on an empty selection!\n");
-\end{lstlisting}
-
-\bigskip
-Use {\tt log\_assert()} and {\tt log\_abort()} instead of {\tt assert()} and {\tt abort()}.
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Creating a command}
-
-\begin{frame}[t, fragile]{\subsecname}
-Simply create a global instance of a class derived from {\tt Pass} to create
-a new yosys command:
-
-\bigskip
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-#include "kernel/yosys.h"
-USING_YOSYS_NAMESPACE
-
-struct MyPass : public Pass {
-    MyPass() : Pass("my_cmd", "just a simple test") { }
-    virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
-    {
-        log("Arguments to my_cmd:\n");
-        for (auto &arg : args)
-            log("  %s\n", arg.c_str());
-
-        log("Modules in current design:\n");
-        for (auto mod : design->modules())
-            log("  %s (%d wires, %d cells)\n", log_id(mod),
-                    GetSize(mod->wires()), GetSize(mod->cells()));
-    }
-} MyPass;
-\end{lstlisting}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Creating a plugin}
-
-\begin{frame}[fragile]{\subsecname}
-Yosys can be extended by adding additional C++ code to the Yosys code base, or
-by loading plugins into Yosys.
-
-\bigskip
-Use the following command to compile a Yosys plugin:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
-yosys-config --exec --cxx --cxxflags --ldflags \
-             -o my_cmd.so -shared my_cmd.cc --ldlibs
-\end{lstlisting}
-
-\bigskip
-Or shorter:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
-yosys-config --build my_cmd.so my_cmd.cc
-\end{lstlisting}
-
-\bigskip
-Load the plugin using the yosys {\tt -m} option:
-\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
-yosys -m ./my_cmd.so -p 'my_cmd foo bar'
-\end{lstlisting}
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Summary}
-
-\begin{frame}{\subsecname}
-\begin{itemize}
-\item Writing Yosys extensions is very straight-forward.
-\item \dots and even simpler if you don't need RTLIL::Memory or RTLIL::Process objects.
-
-\bigskip
-\item Writing synthesis software? Consider learning the Yosys API and make your work
-part of the Yosys framework.
-\end{itemize}
-
-\bigskip
-\bigskip
-\begin{center}
-Questions?
-\end{center}
-
-\bigskip
-\bigskip
-\begin{center}
-\url{https://yosyshq.net/yosys/}
-\end{center}
-\end{frame}
-
diff --git a/yosys/manual/PRESENTATION_Prog/Makefile b/yosys/manual/PRESENTATION_Prog/Makefile
deleted file mode 100644
index 2ac8e5bed9f..00000000000
--- a/yosys/manual/PRESENTATION_Prog/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-
-all: test0.log test1.log test2.log
-
-CXXFLAGS=$(shell ../../yosys-config --cxxflags)
-DATDIR=$(shell ../../yosys-config --datdir)
-
-my_cmd.so: my_cmd.cc
-	../../yosys-config --exec --cxx $(subst $(DATDIR),../../share,$(CXXFLAGS)) --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
-
-test0.log: my_cmd.so
-	../../yosys -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v
-	mv test0.log_new test0.log
-
-test1.log: my_cmd.so
-	../../yosys -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v
-	mv test1.log_new test1.log
-
-test2.log: my_cmd.so
-	../../yosys -Ql test2.log_new -m ./my_cmd.so -p 'hierarchy -top test; test2' sigmap_test.v
-	mv test2.log_new test2.log
-
diff --git a/yosys/manual/clean.sh b/yosys/manual/clean.sh
deleted file mode 100755
index addc34ed183..00000000000
--- a/yosys/manual/clean.sh
+++ /dev/null
@@ -1,2 +0,0 @@
-#!/bin/bash
-for f in $( find . -name .gitignore ); do sed -Ee "s,^,find ${f%.gitignore} -name ',; s,$,' | xargs rm -f,;" $f; done | bash -v
diff --git a/yosys/manual/presentation.sh b/yosys/manual/presentation.sh
deleted file mode 100755
index ca8a6c93c10..00000000000
--- a/yosys/manual/presentation.sh
+++ /dev/null
@@ -1,54 +0,0 @@
-#!/bin/bash
-
-fast_mode=false
-
-set -- $(getopt fu "$@")
-while [ $# -gt 0 ]; do
-	case "$1" in
-		-f)
-			fast_mode=true
-			;;
-		--)
-			shift
-			break
-			;;
-		-*)
-			echo "$0: error - unrecognized option $1" 1>&2
-			exit 1
-			;;
-		*)
-			break
-	esac
-	shift
-done
-
-PDFTEX_OPT="-shell-escape -halt-on-error"
-
-set -ex
-
-if ! $fast_mode; then
-	! md5sum *.aux *.snm *.nav *.toc > autoloop.old
-	make -C PRESENTATION_Intro
-	make -C PRESENTATION_ExSyn
-	make -C PRESENTATION_ExAdv
-	make -C PRESENTATION_ExOth
-	make -C PRESENTATION_Prog
-fi
-
-set -ex
-
-pdflatex $PDFTEX_OPT presentation.tex
-
-if ! $fast_mode; then
-	while
-		md5sum *.aux *.snm *.nav *.toc > autoloop.new
-		! cmp autoloop.old autoloop.new
-	do
-		cp autoloop.new autoloop.old
-		pdflatex $PDFTEX_OPT presentation.tex
-	done
-
-	rm -f autoloop.old
-	rm -f autoloop.new
-fi
-
diff --git a/yosys/manual/presentation.tex b/yosys/manual/presentation.tex
deleted file mode 100644
index 7aba33c8b31..00000000000
--- a/yosys/manual/presentation.tex
+++ /dev/null
@@ -1,162 +0,0 @@
-\documentclass{beamer}
-\hypersetup{bookmarksdepth=5}
-
-\usepackage[T1]{fontenc}   % required for luximono!
-\usepackage{lmodern}
-\usepackage[scaled=0.8]{luximono}  % typewriter font with bold face
-
-% To install the luximono font files:
-% getnonfreefonts-sys --all        or
-% getnonfreefonts-sys luximono
-%
-% when there are trouble you might need to:
-% - Create /etc/texmf/updmap.d/99local-luximono.cfg
-%   containing the single line: Map ul9.map
-% - Run update-updmap followed by mktexlsr and updmap-sys
-%
-% This commands must be executed as root with a root environment
-% (i.e. run "sudo su" and then execute the commands in the root
-% shell, don't just prefix the commands with "sudo").
-
-% formats the text according the set language
-\usepackage[english]{babel}
-\usepackage{amsmath}
-\usepackage{multirow}
-\usepackage{booktabs}
-\usepackage{listings}
-\usepackage{setspace}
-\usepackage{skull}
-\usepackage{units}
-
-\usepackage{tikz}
-\usetikzlibrary{calc}
-\usetikzlibrary{arrows}
-\usetikzlibrary{scopes}
-\usetikzlibrary{through}
-\usetikzlibrary{shapes.geometric}
-
-\lstset{basicstyle=\ttfamily}
-
-\def\B#1{{\tt\textbackslash{}#1}}
-\def\C#1{\lstinline[language=C++]{#1}}
-\def\V#1{\lstinline[language=Verilog]{#1}}
-
-\lstdefinelanguage{liberty}{
-	morecomment=[s]{/*}{*/},
-	morekeywords={library,cell,area,pin,direction,function,clocked_on,next_state,clock,ff},
-	morestring=[b]",
-}
-
-\lstdefinelanguage{rtlil}{
-	morecomment=[l]{\#},
-	morekeywords={module,attribute,parameter,wire,memory,auto,width,offset,size,input,output,inout,cell,connect,switch,case,assign,sync,low,high,posedge,negedge,edge,always,update,process,end},
-	morestring=[b]",
-}
-
-\lstdefinelanguage{ys}{
-	morecomment=[l]{\#},
-}
-
-\lstset{
-	commentstyle=\color{YosysGreen},
-}
-
-\newenvironment{boxalertenv}{\begin{altenv}%
-{\usebeamertemplate{alerted text begin}\usebeamercolor[fg]{alerted text}\usebeamerfont{alerted text}\setlength{\fboxsep}{1pt}\colorbox{bg}}
-{\usebeamertemplate{alerted text end}}{\color{.}}{}}{\end{altenv}}
-
-\newcommand<>{\boxalert}[1]{{%
-\begin{boxalertenv}#2{#1}\end{boxalertenv}%
-}}
-
-\newcommand{\subsectionpagesuffix}{
-\vfill\begin{centering}
-{\usebeamerfont{subsection name}\usebeamercolor[fg]{subsection name}of \sectionname~\insertsectionnumber}
-\vskip1em\par
-\setbeamercolor{graybox}{bg=gray}
-\begin{beamercolorbox}[sep=8pt,center]{graybox}
-\usebeamerfont{subsection title}\insertsection\par
-\end{beamercolorbox}
-\end{centering}}
-
-\title{Yosys Open SYnthesis Suite}
-\author{Claire Xenia Wolf}
-\institute{https://yosyshq.net/yosys/}
-
-\usetheme{Madrid}
-\usecolortheme{seagull}
-\beamertemplatenavigationsymbolsempty
-
-\definecolor{YosysGreen}{RGB}{85,136,102}
-\definecolor{MyBlue}{RGB}{85,130,180}
-
-\setbeamercolor{title}{fg=black,bg=YosysGreen!70}
-\setbeamercolor{titlelike}{fg=black,bg=YosysGreen!70}
-\setbeamercolor{frametitle}{fg=black,bg=YosysGreen!70}
-\setbeamercolor{block title}{fg=black,bg=YosysGreen!70}
-\setbeamercolor{item projected}{fg=black,bg=YosysGreen}
-
-\begin{document}
-
-\begin{frame}
-\titlepage
-\end{frame}
-
-\setcounter{section}{-3}
-
-\section{Abstract}
-\begin{frame}{Abstract}
-Yosys is the first full-featured open source software for Verilog HDL
-synthesis. It supports most of Verilog-2005 and is well tested with
-real-world designs from the ASIC and FPGA world.
-
-\bigskip
-Learn how to use Yosys to create your own custom synthesis flows and
-discover why open source HDL synthesis is important for researchers,
-hobbyists, educators and engineers alike.
-
-\bigskip
-This presentation covers basic concepts of Yosys, writing synthesis scripts
-for a wide range of applications, creating Yosys scripts for various
-non-synthesis applications (such as formal equivalence checking) and
-writing extensions to Yosys using the C++ API.
-\end{frame}
-
-\section{About me}
-\begin{frame}{About me}
-Hi! I'm Claire Xenia Wolf.
-
-\bigskip
-I like writing open source software. For example:
-\begin{itemize}
-\item Yosys
-\item OpenSCAD (now maintained by Marius Kintel)
-\item SPL (a not very popular scripting language)
-\item EmbedVM (a very simple compiler+vm for 8 bit micros)
-\item Lib(X)SVF (a library to play SVF/XSVF files over JTAG)
-\item ROCK Linux (discontinued since 2010)
-\end{itemize}
-\end{frame}
-
-\section{Outline}
-\begin{frame}{Outline}
-Yosys is an Open Source Verilog synthesis tool, and more.
-
-\bigskip
-Outline of this presentation:
-\begin{itemize}
-\item Introduction to the field and Yosys
-\item Yosys by example: synthesis
-\item Yosys by example: advanced synthesis
-\item Yosys by example: beyond synthesis
-\item Writing Yosys extensions in C++
-\end{itemize}
-\end{frame}
-
-\include{PRESENTATION_Intro}
-\include{PRESENTATION_ExSyn}
-\include{PRESENTATION_ExAdv}
-\include{PRESENTATION_ExOth}
-\include{PRESENTATION_Prog}
-
-\end{document}
diff --git a/yosys/misc/create_vcxsrc.sh b/yosys/misc/create_vcxsrc.sh
index 8b39d59e30e..eee215015b5 100644
--- a/yosys/misc/create_vcxsrc.sh
+++ b/yosys/misc/create_vcxsrc.sh
@@ -46,7 +46,7 @@ Open "Git Bash" in this directory and run:
 	mv yosys yosys.bak
 	git clone https://github.com/YosysHQ/yosys.git yosys
 	cd yosys
-	git checkout -B master $(git rev-parse HEAD | cut -c1-10)
+	git checkout -B main $(git rev-parse HEAD | cut -c1-10)
 	unzip ../genfiles.zip
 EOT
 
diff --git a/yosys/misc/jny.schema.json b/yosys/misc/jny.schema.json
index 0fff8ee57d8..278b1a55f63 100644
--- a/yosys/misc/jny.schema.json
+++ b/yosys/misc/jny.schema.json
@@ -1,6 +1,6 @@
 {
 	"$schema": "https://json-schema.org/draft/2020-12/schema",
-	"$id": "https://raw.githubusercontent.com/YosysHQ/yosys/master/misc/jny.schema.json",
+	"$id": "https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json",
 	"title": "Yosys JSON Netlist metadata",
 	"description": "Yosys JSON Netlist",
 	"type": "object",
diff --git a/yosys/misc/py_wrap_generator.py b/yosys/misc/py_wrap_generator.py
index 7fe78e03a58..a65d24d9218 100644
--- a/yosys/misc/py_wrap_generator.py
+++ b/yosys/misc/py_wrap_generator.py
@@ -1257,6 +1257,7 @@ def from_string(str_def, containing_file, class_, line_number, namespace):
 		func.is_static = False
 		func.is_inline = False
 		func.is_virtual = False
+		func.is_const = False
 		func.ret_attr_type = attr_types.default
 		func.is_operator = False
 		func.member_of = None
@@ -1334,6 +1335,11 @@ def from_string(str_def, containing_file, class_, line_number, namespace):
 		found = find_closing(str_def, "(", ")")
 		if found == -1:
 			return None
+
+		post_qualifiers = str_def[found + 1:].lstrip().replace("{", " {") + " "
+		if post_qualifiers.startswith("const "):
+			func.is_const = True
+
 		str_def = str_def[0:found]
 		if func.name in blacklist_methods:
 			return None
@@ -1379,6 +1385,12 @@ def mangled_name(self):
 	def gen_alias(self):
 		self.alias = self.mangled_name
 
+	def gen_post_qualifiers(self, derived=False):
+		if self.member_of != None and self.member_of.link_type == link_types.derive and self.is_virtual and derived:
+			# we drop the qualifiers when deriving callbacks to be implemented in Python
+			return ''
+		return ' const' if self.is_const else ''
+
 	def gen_decl(self):
 		if self.duplicate:
 			return ""
@@ -1392,7 +1404,7 @@ def gen_decl(self):
 			text += ", "
 		if len(self.args) > 0:
 			text = text[:-2]
-		text += ");\n"
+		text += f"){self.gen_post_qualifiers()};\n"
 		return text
 
 	def gen_decl_virtual(self):
@@ -1411,12 +1423,18 @@ def gen_decl_virtual(self):
 		if len(self.args) > 0:
 			text = text[:-2]
 		text += ")"
-		if len(self.args) == 0:
+		if len(self.args) == 0 and self.ret_type.name == "void":
 			text += "{}"
 		else:
 			text += "\n\t\t{"
 			for arg in self.args:
 				text += "\n\t\t\t(void)" + arg.gen_varname() + ";"
+			if self.ret_type.name == "void":
+				pass
+			elif self.ret_type.name == "bool":
+				text += "\n\t\t\treturn false;"
+			else:
+				raise NotImplementedError(self.ret_type.name)
 			text += "\n\t\t}\n"
 		text += "\n\t\tvirtual "
 		if self.is_static:
@@ -1427,7 +1445,7 @@ def gen_decl_virtual(self):
 			text += ", "
 		if len(self.args) > 0:
 			text = text[:-2]
-		text += ") override;\n"
+		text += f"){self.gen_post_qualifiers()} override;\n"
 		return text
 
 	def gen_decl_hash_py(self):
@@ -1452,7 +1470,7 @@ def gen_def(self):
 			text += ", "
 		if len(self.args) > 0:
 			text = text[:-2]
-		text +=")\n\t{"
+		text += f"){self.gen_post_qualifiers()}\n\t{{"
 		for arg in self.args:
 			text += arg.gen_translation()
 		text += "\n\t\t"
@@ -1507,16 +1525,17 @@ def gen_def_virtual(self):
 			text += ", "
 		if len(self.args) > 0:
 			text = text[:-2]
-		text += ")\n\t{"
+		text += f"){self.gen_post_qualifiers()}\n\t{{"
 		for arg in self.args:
 			text += arg.gen_translation_cpp()
-		text += "\n\t\t"
+		return_stmt = "return " if self.ret_type.name != "void" else ""
+		text += f"\n\t\t{return_stmt}"
 		if self.member_of == None:
 			text += "::" + self.namespace + "::" + self.alias + "("
 		elif self.is_static:
 			text += self.member_of.namespace + "::" + self.member_of.name + "::" + self.name + "("
 		else:
-			text += "py_" + self.alias + "("
+			text += f"const_cast<{self.member_of.name}*>(this)->py_" + self.alias + "("
 		for arg in self.args:
 			text += arg.gen_call_cpp() + ", "
 		if len(self.args) > 0:
@@ -1547,11 +1566,13 @@ def gen_default_impl(self):
 			call_string = call_string[0:-2]
 		call_string += ");"
 
+		return_stmt = "return " if self.ret_type.name != "void" else ""
+
 		text += ")\n\t\t{"
-		text += "\n\t\t\tif(boost::python::override py_" + self.alias + " = this->get_override(\"py_" + self.alias + "\"))"
-		text += "\n\t\t\t\t" + call_string
+		text += "\n\t\t\tif (boost::python::override py_" + self.alias + " = this->get_override(\"py_" + self.alias + "\"))"
+		text += f"\n\t\t\t\t{return_stmt}" + call_string
 		text += "\n\t\t\telse"
-		text += "\n\t\t\t\t" + self.member_of.name + "::" + call_string
+		text += f"\n\t\t\t\t{return_stmt}" + self.member_of.name + "::" + call_string
 		text += "\n\t\t}"
 
 		text += "\n\n\t\t" + self.ret_type.gen_text() + " default_py_" + self.alias + "("
@@ -1559,8 +1580,8 @@ def gen_default_impl(self):
 			text += arg.gen_listitem() + ", "
 		if len(self.args) > 0:
 			text = text[:-2]
-		text += ")\n\t\t{"
-		text += "\n\t\t\tthis->" + self.member_of.name + "::" + call_string
+		text += f")\n\t\t{{"
+		text += f"\n\t\t\t{return_stmt}this->" + self.member_of.name + "::" + call_string
 		text += "\n\t\t}"
 		return text
 
@@ -1584,9 +1605,9 @@ def gen_boost_py(self):
 			for a in self.args:
 				text += a.gen_listitem_hash() + ", "
 			if len(self.args) > 0:
-				text = text[0:-2] + ")>"
+				text = text[0:-2] + f"){self.gen_post_qualifiers(True)}>"
 			else:
-				text += "void)>"
+				text += f"void){self.gen_post_qualifiers(True)}>"
 
 		if self.is_operator:
 			text += "(\"" + wrappable_operators[self.name.replace("operator","")] + "\""
diff --git a/yosys/misc/yosys-config.in b/yosys/misc/yosys-config.in
old mode 100644
new mode 100755
index f0f0f755231..dd42b7c877b
--- a/yosys/misc/yosys-config.in
+++ b/yosys/misc/yosys-config.in
@@ -9,8 +9,10 @@ help() {
 		echo "Replacement args:"
 		echo "    --cxx         @CXX@"
 		echo "    --cxxflags    $( echo '@CXXFLAGS@' | fmt -w60 | sed ':a;N;$!ba;s/\n/ \\\n                      /g' )"
-		echo "    --ldflags     @LDFLAGS@"
-		echo "    --ldlibs      @LDLIBS@"
+		echo "    --linkflags   @LINKFLAGS@"
+		echo "    --ldflags     (alias of --linkflags)"
+		echo "    --libs        @LIBS@"
+		echo "    --ldlibs      (alias of --libs)"
 		echo "    --bindir      @BINDIR@"
 		echo "    --datdir      @DATDIR@"
 		echo ""
@@ -18,7 +20,7 @@ help() {
 		echo ""
 		echo "Use --exec to call a command instead of generating output. Example usage:"
 		echo ""
-		echo "  $0 --exec --cxx --cxxflags --ldflags -o plugin.so -shared plugin.cc --ldlibs"
+		echo "  $0 --exec --cxx --cxxflags --ldflags -o plugin.so -shared plugin.cc --libs"
 		echo ""
 		echo "The above command can be abbreviated as:"
 		echo ""
@@ -44,7 +46,7 @@ fi
 
 if [ "$1" == "--build" ]; then
 	modname="$2"; shift 2
-	set -- --exec --cxx --cxxflags --ldflags -o "$modname" -shared "$@" --ldlibs
+	set -- --exec --cxx --cxxflags --ldflags -o "$modname" -shared "$@" --libs
 fi
 
 prefix="--"
@@ -63,10 +65,14 @@ for opt; do
 			tokens=( "${tokens[@]}"  @CXX@       ) ;;
 		"$prefix"cxxflags)
 			tokens=( "${tokens[@]}"  @CXXFLAGS@  ) ;;
+		"$prefix"linkflags)
+			tokens=( "${tokens[@]}"  @LINKFLAGS@   ) ;;
+		"$prefix"libs)
+			tokens=( "${tokens[@]}"  @LIBS@    ) ;;
 		"$prefix"ldflags)
-			tokens=( "${tokens[@]}"  @LDFLAGS@   ) ;;
+			tokens=( "${tokens[@]}"  @LINKFLAGS@   ) ;;
 		"$prefix"ldlibs)
-			tokens=( "${tokens[@]}"  @LDLIBS@    ) ;;
+			tokens=( "${tokens[@]}"  @LIBS@    ) ;;
 		"$prefix"bindir)
 			tokens=( "${tokens[@]}" '@BINDIR@'   ) ;;
 		"$prefix"datdir)
@@ -104,4 +110,3 @@ fi
 
 echo "${tokens[@]}"
 exit 0
-
diff --git a/yosys/passes/cmds/Makefile.inc b/yosys/passes/cmds/Makefile.inc
index 29b3a1132ad..33e3ae1bc5a 100644
--- a/yosys/passes/cmds/Makefile.inc
+++ b/yosys/passes/cmds/Makefile.inc
@@ -46,3 +46,6 @@ OBJS += passes/cmds/printattrs.o
 OBJS += passes/cmds/sta.o
 OBJS += passes/cmds/clean_zerowidth.o
 OBJS += passes/cmds/xprop.o
+OBJS += passes/cmds/dft_tag.o
+OBJS += passes/cmds/future.o
+OBJS += passes/cmds/box_derive.o
diff --git a/yosys/passes/cmds/autoname.cc b/yosys/passes/cmds/autoname.cc
index 6019c61534f..737bd3e58be 100644
--- a/yosys/passes/cmds/autoname.cc
+++ b/yosys/passes/cmds/autoname.cc
@@ -24,8 +24,8 @@ PRIVATE_NAMESPACE_BEGIN
 
 int autoname_worker(Module *module, const dict<Wire*, int>& wire_score)
 {
-	dict<Cell*, pair<int, IdString>> proposed_cell_names;
-	dict<Wire*, pair<int, IdString>> proposed_wire_names;
+	dict<Cell*, pair<int, string>> proposed_cell_names;
+	dict<Wire*, pair<int, string>> proposed_wire_names;
 	int best_score = -1;
 
 	for (auto cell : module->selected_cells()) {
@@ -36,7 +36,7 @@ int autoname_worker(Module *module, const dict<Wire*, int>& wire_score)
 					if (bit.wire != nullptr && bit.wire->name[0] != '$') {
 						if (suffix.empty())
 							suffix = stringf("_%s_%s", log_id(cell->type), log_id(conn.first));
-						IdString new_name(bit.wire->name.str() + suffix);
+						string new_name(bit.wire->name.str() + suffix);
 						int score = wire_score.at(bit.wire);
 						if (cell->output(conn.first)) score = 0;
 						score = 10000*score + new_name.size();
@@ -54,7 +54,7 @@ int autoname_worker(Module *module, const dict<Wire*, int>& wire_score)
 					if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) {
 						if (suffix.empty())
 							suffix = stringf("_%s", log_id(conn.first));
-						IdString new_name(cell->name.str() + suffix);
+						string new_name(cell->name.str() + suffix);
 						int score = wire_score.at(bit.wire);
 						if (cell->output(conn.first)) score = 0;
 						score = 10000*score + new_name.size();
@@ -71,7 +71,7 @@ int autoname_worker(Module *module, const dict<Wire*, int>& wire_score)
 	for (auto &it : proposed_cell_names) {
 		if (best_score*2 < it.second.first)
 			continue;
-		IdString n = module->uniquify(it.second.second);
+		IdString n = module->uniquify(IdString(it.second.second));
 		log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
 		module->rename(it.first, n);
 	}
@@ -79,7 +79,7 @@ int autoname_worker(Module *module, const dict<Wire*, int>& wire_score)
 	for (auto &it : proposed_wire_names) {
 		if (best_score*2 < it.second.first)
 			continue;
-		IdString n = module->uniquify(it.second.second);
+		IdString n = module->uniquify(IdString(it.second.second));
 		log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
 		module->rename(it.first, n);
 	}
diff --git a/yosys/passes/cmds/box_derive.cc b/yosys/passes/cmds/box_derive.cc
new file mode 100644
index 00000000000..da698b04d37
--- /dev/null
+++ b/yosys/passes/cmds/box_derive.cc
@@ -0,0 +1,116 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Martin Povišer <povik@cutebit.org>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+#include "kernel/yosys.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct BoxDerivePass : Pass {
+	BoxDerivePass() : Pass("box_derive", "derive box modules") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    box_derive [-base <base_module>] [-naming_attr <attr>] [selection]\n");
+		log("\n");
+		log("As part of the assembly of the design hierarchy done by the 'hierarchy' command,\n");
+		log("specializations of parametric modules are derived on demand: for each choice of\n");
+		log("parameter values appearing in the design, a copy of the parametric module is\n");
+		log("derived which is specialized to that choice.\n");
+		log("\n");
+		log("This derivation process ignores blackboxes and whiteboxes (boxes). To supplement,\n");
+		log("this 'box_derive' command can be used to request the derivation of modules based\n");
+		log("on box instances appearing in the design, which is desirable in certain use\n");
+		log("cases. Only the selected cells are considered as the instances that steer the\n");
+		log("derivation process.\n");
+		log("\n");
+		log("    -base <base_module>\n");
+		log("        instead of deriving the module that directly corresponds to each box\n");
+		log("        instance, derive a specialization of <base_module> (this option applies\n");
+		log("        to all selected box cells)\n");
+		log("\n");
+		log("    -naming_attr <attr>\n");
+		log("        once a specialization is derived, use the value of the module attribute\n");
+		log("        <attr> for a name which should be used for the derived module (this\n");
+		log("        replaces the internal Yosys naming scheme in which the names of derived\n");
+		log("        modules start with '$paramod$')\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *d) override
+	{
+		log_header(d, "Executing BOX_DERIVE pass. (derive modules for boxes)\n");
+
+		size_t argidx;
+		IdString naming_attr;
+		IdString base_name;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-naming_attr" && argidx + 1 < args.size())
+				naming_attr = RTLIL::escape_id(args[++argidx]);
+			else if (args[argidx] == "-base" && argidx + 1 < args.size())
+				base_name = RTLIL::escape_id(args[++argidx]);
+			else
+				break;
+		}
+		extra_args(args, argidx, d);
+
+		Module *base_override = nullptr;
+		if (!base_name.empty()) {
+			base_override = d->module(base_name);
+			if (!base_override)
+				log_cmd_error("Base module %s not found.\n", log_id(base_name));
+		}
+
+		dict<std::pair<RTLIL::IdString, dict<RTLIL::IdString, RTLIL::Const>>, Module*> done;
+
+		for (auto module : d->selected_modules()) {
+			for (auto cell : module->selected_cells()) {
+				Module *inst_module = d->module(cell->type);
+				if (!inst_module || !inst_module->get_blackbox_attribute())
+					continue;
+
+				Module *base = inst_module;
+				if (base_override)
+					base = base_override;
+
+				auto index = std::make_pair(base->name, cell->parameters);
+
+				if (cell->parameters.empty() || done.count(index))
+					continue;
+
+				IdString derived_type = base->derive(d, cell->parameters);
+				Module *derived = d->module(derived_type);
+				log_assert(derived && "Failed to derive module\n");
+				log_debug("derived %s\n", derived_type.c_str());
+
+				if (!naming_attr.empty() && derived->has_attribute(naming_attr)) {
+					IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr));
+					if (!new_name.isPublic())
+						log_error("Derived module %s cannot be renamed to private name %s.\n",
+								  log_id(derived), log_id(new_name));
+					derived->attributes.erase(naming_attr);
+					d->rename(derived, new_name);
+				}
+
+				done[index] = derived;
+			}
+		}
+	}
+} BoxDerivePass;
+
+PRIVATE_NAMESPACE_END
diff --git a/yosys/passes/cmds/check.cc b/yosys/passes/cmds/check.cc
index d1c83f04d88..255c32fbad9 100644
--- a/yosys/passes/cmds/check.cc
+++ b/yosys/passes/cmds/check.cc
@@ -19,6 +19,7 @@
 
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
+#include "kernel/celledges.h"
 #include "kernel/celltypes.h"
 #include "kernel/utils.h"
 
@@ -102,10 +103,10 @@ struct CheckPass : public Pass {
 
 			SigMap sigmap(module);
 			dict<SigBit, vector<string>> wire_drivers;
+			dict<SigBit, Cell *> driver_cells;
 			dict<SigBit, int> wire_drivers_count;
 			pool<SigBit> used_wires;
-			TopoSort<string> topo;
-
+			TopoSort<std::pair<RTLIL::IdString, int>> topo;
 			for (auto &proc_it : module->processes)
 			{
 				std::vector<RTLIL::CaseRule*> all_cases = {&proc_it.second->root_case};
@@ -150,6 +151,50 @@ struct CheckPass : public Pass {
 				}
 			}
 
+			struct CircuitEdgesDatabase : AbstractCellEdgesDatabase {
+				TopoSort<std::pair<RTLIL::IdString, int>> &topo;
+				SigMap sigmap;
+
+				CircuitEdgesDatabase(TopoSort<std::pair<RTLIL::IdString, int>> &topo, SigMap &sigmap)
+					: topo(topo), sigmap(sigmap) {}
+
+				void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit,
+							  RTLIL::IdString to_port, int to_bit, int) override {
+					SigSpec from_portsig = cell->getPort(from_port);
+					SigSpec to_portsig = cell->getPort(to_port);
+					log_assert(from_bit >= 0 && from_bit < from_portsig.size());
+					log_assert(to_bit >= 0 && to_bit < to_portsig.size());
+					SigBit from = sigmap(from_portsig[from_bit]);
+					SigBit to = sigmap(to_portsig[to_bit]);
+
+					if (from.wire && to.wire)
+						topo.edge(std::make_pair(from.wire->name, from.offset), std::make_pair(to.wire->name, to.offset));
+				}
+
+				bool add_edges_from_cell(Cell *cell) {
+					if (AbstractCellEdgesDatabase::add_edges_from_cell(cell))
+						return true;
+
+					// We don't have accurate cell edges, do the fallback of all input-output pairs
+					for (auto &conn : cell->connections()) {
+						if (cell->input(conn.first))
+						for (auto bit : sigmap(conn.second))
+						if (bit.wire)
+							topo.edge(std::make_pair(bit.wire->name, bit.offset),
+									  std::make_pair(cell->name, -1));
+
+						if (cell->output(conn.first))
+						for (auto bit : sigmap(conn.second))
+						if (bit.wire)
+							topo.edge(std::make_pair(cell->name, -1),
+									  std::make_pair(bit.wire->name, bit.offset));
+					}
+					return true;
+				}
+			};
+
+			CircuitEdgesDatabase edges_db(topo, sigmap);
+
 			for (auto cell : module->cells())
 			{
 				if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
@@ -158,31 +203,30 @@ struct CheckPass : public Pass {
 					counter++;
 				cell_allowed:;
 				}
+
 				for (auto &conn : cell->connections()) {
+					bool input = cell->input(conn.first);
+					bool output = cell->output(conn.first);
+
 					SigSpec sig = sigmap(conn.second);
-					bool logic_cell = yosys_celltypes.cell_evaluable(cell->type);
-					if (cell->input(conn.first))
-						for (auto bit : sig)
-							if (bit.wire) {
-								if (logic_cell)
-									topo.edge(stringf("wire %s", log_signal(bit)),
-											stringf("cell %s (%s)", log_id(cell), log_id(cell->type)));
-								used_wires.insert(bit);
-							}
-					if (cell->output(conn.first))
-						for (int i = 0; i < GetSize(sig); i++) {
-							if (logic_cell)
-								topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)),
-										stringf("wire %s", log_signal(sig[i])));
-
-							if (sig[i].wire || !cell->input(conn.first))
-								wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)",
-										log_id(conn.first), i, log_id(cell), log_id(cell->type)));
-						}
-					if (!cell->input(conn.first) && cell->output(conn.first))
-						for (auto bit : sig)
-							if (bit.wire) wire_drivers_count[bit]++;
+					for (int i = 0; i < sig.size(); i++) {
+						SigBit bit = sig[i];
+
+						if (input && bit.wire)
+							used_wires.insert(bit);
+						if (output && !input && bit.wire)
+							wire_drivers_count[bit]++;
+						if (output && (bit.wire || !input))
+							wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", log_id(conn.first), i,
+																log_id(cell), log_id(cell->type)));
+						if (output)
+							driver_cells[bit] = cell;
+					}
 				}
+
+				if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \
+						|| RTLIL::builtin_ff_cell_types().count(cell->type))
+					edges_db.add_edges_from_cell(cell);
 			}
 
 			pool<SigBit> init_bits;
@@ -239,8 +283,72 @@ struct CheckPass : public Pass {
 			topo.sort();
 			for (auto &loop : topo.loops) {
 				string message = stringf("found logic loop in module %s:\n", log_id(module));
-				for (auto &str : loop)
-					message += stringf("    %s\n", str.c_str());
+
+				// `loop` only contains wire bits, or an occassional special helper node for cells for
+				// which we have done the edges fallback. The cell and its ports that led to an edge is
+				// an information we need to recover now. For that we need to have the previous wire bit
+				// of the loop at hand.
+				SigBit prev;
+				for (auto it = loop.rbegin(); it != loop.rend(); it++)
+				if (it->second != -1) { // skip the fallback helper nodes
+					prev = SigBit(module->wire(it->first), it->second);
+					break;
+				}
+				log_assert(prev != SigBit());
+
+				for (auto &pair : loop) {
+					if (pair.second == -1)
+						continue; // helper node for edges fallback, we can ignore it
+
+					struct MatchingEdgePrinter : AbstractCellEdgesDatabase {
+						std::string &message;
+						SigMap &sigmap;
+						SigBit from, to;
+						int nhits;
+						const int HITS_LIMIT = 3;
+
+						MatchingEdgePrinter(std::string &message, SigMap &sigmap, SigBit from, SigBit to)
+							: message(message), sigmap(sigmap), from(from), to(to), nhits(0) {}
+
+						void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit,
+									  RTLIL::IdString to_port, int to_bit, int) override {
+							SigBit edge_from = sigmap(cell->getPort(from_port))[from_bit];
+							SigBit edge_to = sigmap(cell->getPort(to_port))[to_bit];
+
+							if (edge_from == from && edge_to == to && nhits++ < HITS_LIMIT)
+								message += stringf("        %s[%d] --> %s[%d]\n", log_id(from_port), from_bit,
+												   log_id(to_port), to_bit);
+							if (nhits == HITS_LIMIT)
+								message += "        ...\n";
+						}
+					};
+
+					Wire *wire = module->wire(pair.first);
+					log_assert(wire);
+					SigBit bit(module->wire(pair.first), pair.second);
+					log_assert(driver_cells.count(bit));
+					Cell *driver = driver_cells.at(bit);
+
+					std::string driver_src;
+					if (driver->has_attribute(ID::src)) {
+						std::string src_attr = driver->get_src_attribute();
+						driver_src = stringf(" source: %s", src_attr.c_str());
+					}
+					message += stringf("    cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src.c_str());
+					MatchingEdgePrinter printer(message, sigmap, prev, bit);
+					printer.add_edges_from_cell(driver);
+
+					if (wire->name.isPublic()) {
+						std::string wire_src;
+						if (wire->has_attribute(ID::src)) {
+							std::string src_attr = wire->get_src_attribute();
+							wire_src = stringf(" source: %s", src_attr.c_str());
+						}
+						message += stringf("    wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src.c_str());						
+					}
+
+					prev = bit;
+				}
 				log_warning("%s", message.c_str());
 				counter++;
 			}
diff --git a/yosys/passes/cmds/chformal.cc b/yosys/passes/cmds/chformal.cc
index da97ff71d69..e027103bb03 100644
--- a/yosys/passes/cmds/chformal.cc
+++ b/yosys/passes/cmds/chformal.cc
@@ -23,6 +23,52 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+static RTLIL::IdString formal_flavor(RTLIL::Cell *cell)
+{
+	if (cell->type != ID($check))
+		return cell->type;
+
+	std::string flavor_param = cell->getParam(ID(FLAVOR)).decode_string();
+	if (flavor_param == "assert")
+		return ID($assert);
+	else if (flavor_param == "assume")
+		return ID($assume);
+	else if (flavor_param == "cover")
+		return ID($cover);
+	else if (flavor_param == "live")
+		return ID($live);
+	else if (flavor_param == "fair")
+		return ID($fair);
+	else
+		log_abort();
+}
+
+static void set_formal_flavor(RTLIL::Cell *cell, RTLIL::IdString flavor)
+{
+	if (cell->type != ID($check)) {
+		cell->type = flavor;
+		return;
+	}
+
+	if (flavor == ID($assert))
+		cell->setParam(ID(FLAVOR), std::string("assert"));
+	else if (flavor == ID($assume))
+		cell->setParam(ID(FLAVOR), std::string("assume"));
+	else if (flavor == ID($cover))
+		cell->setParam(ID(FLAVOR), std::string("cover"));
+	else if (flavor == ID($live))
+		cell->setParam(ID(FLAVOR), std::string("live"));
+	else if (flavor == ID($fair))
+		cell->setParam(ID(FLAVOR), std::string("fair"));
+	else
+		log_abort();
+}
+
+static bool is_triggered_check_cell(RTLIL::Cell * cell)
+{
+	return cell->type == ID($check) && cell->getParam(ID(TRG_ENABLE)).as_bool();
+}
+
 struct ChformalPass : public Pass {
 	ChformalPass() : Pass("chformal", "change formal constraints of the design") { }
 	void help() override
@@ -41,13 +87,18 @@ struct ChformalPass : public Pass {
 		log("    -fair         $fair cells, representing assume(s_eventually ...)\n");
 		log("    -cover        $cover cells, representing cover() statements\n");
 		log("\n");
+		log("    Additionally chformal will operate on $check cells corresponding to the\n");
+		log("    selected constraint types.\n");
+		log("\n");
 		log("Exactly one of the following modes must be specified:\n");
 		log("\n");
 		log("    -remove\n");
 		log("        remove the cells and thus constraints from the design\n");
 		log("\n");
 		log("    -early\n");
-		log("        bypass FFs that only delay the activation of a constraint\n");
+		log("        bypass FFs that only delay the activation of a constraint. When inputs\n");
+		log("        of the bypassed FFs do not remain stable between clock edges, this may\n");
+		log("        result in unexpected behavior.\n");
 		log("\n");
 		log("    -delay <N>\n");
 		log("        delay activation of the constraint by <N> clock cycles\n");
@@ -69,6 +120,11 @@ struct ChformalPass : public Pass {
 		log("    -fair2live\n");
 		log("        change the roles of cells as indicated. these options can be combined\n");
 		log("\n");
+		log("    -lower\n");
+		log("        convert each $check cell into an $assert, $assume, $live, $fair or\n");
+		log("        $cover cell. If the $check cell contains a message, also produce a\n");
+		log("        $print cell.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
@@ -146,6 +202,10 @@ struct ChformalPass : public Pass {
 				mode = 'c';
 				continue;
 			}
+			if (mode == 0 && args[argidx] == "-lower") {
+				mode = 'l';
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -166,7 +226,7 @@ struct ChformalPass : public Pass {
 			vector<Cell*> constr_cells;
 
 			for (auto cell : module->selected_cells())
-				if (constr_types.count(cell->type))
+				if (constr_types.count(formal_flavor(cell)))
 					constr_cells.push_back(cell);
 
 			if (mode == 'r')
@@ -216,6 +276,18 @@ struct ChformalPass : public Pass {
 				}
 
 				for (auto cell : constr_cells)
+				{
+					if (is_triggered_check_cell(cell)) {
+						if (cell->getParam(ID::TRG_WIDTH).as_int() != 1)
+							continue;
+						cell->setPort(ID::TRG, SigSpec());
+						cell->setParam(ID::TRG_ENABLE, false);
+						cell->setParam(ID::TRG_WIDTH, 0);
+						cell->setParam(ID::TRG_POLARITY, false);
+					}
+
+					IdString flavor = formal_flavor(cell);
+
 					while (true)
 					{
 						SigSpec A = sigmap(cell->getPort(ID::A));
@@ -225,8 +297,8 @@ struct ChformalPass : public Pass {
 							break;
 
 						if (!init_zero.count(EN)) {
-							if (cell->type == ID($cover)) break;
-							if (cell->type.in(ID($assert), ID($assume)) && !init_one.count(A)) break;
+							if (flavor == ID($cover)) break;
+							if (flavor.in(ID($assert), ID($assume)) && !init_one.count(A)) break;
 						}
 
 						const auto &A_map = ffmap.at(A);
@@ -238,25 +310,31 @@ struct ChformalPass : public Pass {
 						cell->setPort(ID::A, A_map.first);
 						cell->setPort(ID::EN, EN_map.first);
 					}
+				}
 			}
 			else
 			if (mode == 'd')
 			{
 				for (auto cell : constr_cells)
-				for (int i = 0; i < mode_arg; i++)
 				{
-					SigSpec orig_a = cell->getPort(ID::A);
-					SigSpec orig_en = cell->getPort(ID::EN);
+					if (is_triggered_check_cell(cell))
+						log_error("Cannot delay edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", log_id(cell));
 
-					Wire *new_a = module->addWire(NEW_ID);
-					Wire *new_en = module->addWire(NEW_ID);
-					new_en->attributes[ID::init] = State::S0;
+					for (int i = 0; i < mode_arg; i++)
+					{
+						SigSpec orig_a = cell->getPort(ID::A);
+						SigSpec orig_en = cell->getPort(ID::EN);
+
+						Wire *new_a = module->addWire(NEW_ID);
+						Wire *new_en = module->addWire(NEW_ID);
+						new_en->attributes[ID::init] = State::S0;
 
-					module->addFf(NEW_ID, orig_a, new_a);
-					module->addFf(NEW_ID, orig_en, new_en);
+						module->addFf(NEW_ID, orig_a, new_a);
+						module->addFf(NEW_ID, orig_en, new_en);
 
-					cell->setPort(ID::A, new_a);
-					cell->setPort(ID::EN, new_en);
+						cell->setPort(ID::A, new_a);
+						cell->setPort(ID::EN, new_en);
+					}
 				}
 			}
 			else
@@ -278,21 +356,76 @@ struct ChformalPass : public Pass {
 			if (mode =='p')
 			{
 				for (auto cell : constr_cells)
-					module->addCover(NEW_ID_SUFFIX("coverenable"),
-						cell->getPort(ID::EN), State::S1, cell->get_src_attribute());
+				{
+					if (cell->type == ID($check)) {
+						Cell *cover = module->addCell(NEW_ID_SUFFIX("coverenable"), ID($check));
+						cover->attributes = cell->attributes;
+						cover->parameters = cell->parameters;
+						cover->setParam(ID(FLAVOR), Const("cover"));
+
+						for (auto const &conn : cell->connections())
+							if (!conn.first.in(ID::A, ID::EN))
+								cover->setPort(conn.first, conn.second);
+						cover->setPort(ID::A, cell->getPort(ID::EN));
+						cover->setPort(ID::EN, State::S1);
+					} else {
+						module->addCover(NEW_ID_SUFFIX("coverenable"),
+							cell->getPort(ID::EN), State::S1, cell->get_src_attribute());
+					}
+				}
 			}
 			else
 			if (mode == 'c')
 			{
-				for (auto cell : constr_cells)
-					if (assert2assume && cell->type == ID($assert))
-						cell->type = ID($assume);
-					else if (assume2assert && cell->type == ID($assume))
-						cell->type = ID($assert);
-					else if (live2fair && cell->type == ID($live))
-						cell->type = ID($fair);
-					else if (fair2live && cell->type == ID($fair))
-						cell->type = ID($live);
+				for (auto cell : constr_cells) {
+					IdString flavor = formal_flavor(cell);
+					if (assert2assume && flavor == ID($assert))
+						set_formal_flavor(cell, ID($assume));
+					else if (assume2assert && flavor == ID($assume))
+						set_formal_flavor(cell, ID($assert));
+					else if (live2fair && flavor == ID($live))
+						set_formal_flavor(cell, ID($fair));
+					else if (fair2live && flavor == ID($fair))
+						set_formal_flavor(cell, ID($live));
+				}
+			}
+			else
+			if (mode == 'l')
+			{
+				for (auto cell : constr_cells) {
+					if (cell->type != ID($check))
+						continue;
+
+					if (is_triggered_check_cell(cell))
+						log_error("Cannot lower edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", log_id(cell));
+
+
+					Cell *plain_cell = module->addCell(NEW_ID, formal_flavor(cell));
+
+					plain_cell->attributes = cell->attributes;
+
+					SigBit sig_a = cell->getPort(ID::A);
+					SigBit sig_en = cell->getPort(ID::EN);
+
+					plain_cell->setPort(ID::A, sig_a);
+					plain_cell->setPort(ID::EN, sig_en);
+
+					if (plain_cell->type.in(ID($assert), ID($assume)))
+						sig_a = module->Not(NEW_ID, sig_a);
+
+					SigBit combined_en = module->And(NEW_ID, sig_a, sig_en);
+
+					module->swap_names(cell, plain_cell);
+
+					if (cell->getPort(ID::ARGS).empty()) {
+						module->remove(cell);
+					} else {
+						cell->type = ID($print);
+						cell->setPort(ID::EN, combined_en);
+						cell->unsetPort(ID::A);
+						cell->unsetParam(ID(FLAVOR));
+					}
+				}
 			}
 		}
 	}
diff --git a/yosys/passes/cmds/connect.cc b/yosys/passes/cmds/connect.cc
index 1bd52aab258..65292ef92e9 100644
--- a/yosys/passes/cmds/connect.cc
+++ b/yosys/passes/cmds/connect.cc
@@ -47,7 +47,7 @@ struct ConnectPass : public Pass {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr>\n");
+		log("    connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr> [selection]\n");
 		log("\n");
 		log("Create a connection. This is equivalent to adding the statement 'assign\n");
 		log("<lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing\n");
@@ -55,12 +55,12 @@ struct ConnectPass : public Pass {
 		log("the -nounset option.\n");
 		log("\n");
 		log("\n");
-		log("    connect [-nomap] -unset <expr>\n");
+		log("    connect [-nomap] -unset <expr> [selection]\n");
 		log("\n");
 		log("Unconnect all existing drivers for the specified expression.\n");
 		log("\n");
 		log("\n");
-		log("    connect [-nomap] [-assert] -port <cell> <port> <expr>\n");
+		log("    connect [-nomap] [-assert] -port <cell> <port> <expr> [selection]\n");
 		log("\n");
 		log("Connect the specified cell port to the specified cell port.\n");
 		log("\n");
@@ -80,17 +80,6 @@ struct ConnectPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		RTLIL::Module *module = nullptr;
-		for (auto mod : design->selected_modules()) {
-			if (module != nullptr)
-				log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name));
-			module = mod;
-		}
-		if (module == nullptr)
-			log_cmd_error("No modules selected.\n");
-		if (!module->processes.empty())
-			log_cmd_error("Found processes in selected module.\n");
-
 		bool flag_nounset = false, flag_nomap = false, flag_assert = false;
 		std::string set_lhs, set_rhs, unset_expr;
 		std::string port_cell, port_port, port_expr;
@@ -128,6 +117,18 @@ struct ConnectPass : public Pass {
 			}
 			break;
 		}
+		extra_args(args, argidx, design);
+
+		RTLIL::Module *module = nullptr;
+		for (auto mod : design->selected_modules()) {
+			if (module != nullptr)
+				log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name));
+			module = mod;
+		}
+		if (module == nullptr)
+			log_cmd_error("No modules selected.\n");
+		if (!module->processes.empty())
+			log_cmd_error("Found processes in selected module.\n");
 
 		SigMap sigmap;
 		if (!flag_nomap)
diff --git a/yosys/passes/cmds/dft_tag.cc b/yosys/passes/cmds/dft_tag.cc
new file mode 100644
index 00000000000..2b2340dab53
--- /dev/null
+++ b/yosys/passes/cmds/dft_tag.cc
@@ -0,0 +1,1015 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2022  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/celltypes.h"
+#include "kernel/ff.h"
+#include "kernel/modtools.h"
+#include "kernel/sigtools.h"
+#include "kernel/yosys.h"
+#include <deque>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct DftTagOptions {
+	bool tag_public = false;
+	bool overwrite_only = false;
+};
+
+struct DftTagWorker {
+	Module *module;
+	DftTagOptions options;
+	ModWalker modwalker;
+	SigMap &sigmap;
+	FfInitVals initvals;
+
+	struct tag_set {
+		int index = 0;
+
+		tag_set(int index = 0) : index(index) {}
+
+		bool operator<(const tag_set &other) const { return index < other.index; }
+		bool operator==(const tag_set &other) const { return index == other.index; }
+
+		unsigned int hash() const { return hash_ops<int>::hash(index); }
+
+		bool empty() const { return index == 0; }
+	};
+
+	idict<pool<IdString>> tag_sets;
+
+	pool<IdString> tmp_tag_set;
+	dict<std::pair<tag_set, tag_set>, tag_set> tag_set_union_cache;
+
+	dict<SigBit, tag_set> tagged_signals;
+
+	dict<IdString, pool<IdString>> tag_groups;
+	dict<IdString, IdString> group_of_tag;
+	pool<IdString> all_tags;
+
+	pool<Cell *> pending_cells;
+	std::deque<Cell *> pending_cell_queue;
+
+	dict<std::pair<IdString, SigBit>, SigBit> tag_signals;
+
+	// Uses SigSpec instead of SigBit so we can use coarse grained cells to combine the individual tags
+	dict<std::pair<IdString, SigSpec>, SigSpec> tag_group_signals;
+
+	pool<Cell *> warned_cells;
+
+	DftTagWorker(Module *module, DftTagOptions options) :
+		module(module), options(options), modwalker(module->design), sigmap(modwalker.sigmap)
+	{
+		modwalker.setup(module);
+		initvals.set(&modwalker.sigmap, module);
+		tag_sets(tmp_tag_set);
+	}
+
+	void resolve_overwrites()
+	{
+		std::vector<Cell *> overwrite_cells;
+		std::vector<Cell *> original_cells;
+
+		bool design_changed = false;
+
+		for (auto cell : module->cells()) {
+			if (cell->type == ID($overwrite_tag))
+				overwrite_cells.push_back(cell);
+
+			if (cell->type == ID($original_tag))
+				original_cells.push_back(cell);
+		}
+
+		for (auto cell : overwrite_cells) {
+			log_debug("Applying $overwrite_tag %s for signal %s\n", log_id(cell->name), log_signal(cell->getPort(ID::A)));
+			SigSpec orig_signal = cell->getPort(ID::A);
+			SigSpec interposed_signal = divert_users(orig_signal);
+			auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal);
+			modwalker.add_cell(set_tag_cell); // Make sure the next $overwrite_tag sees the new connections
+			design_changed = true;
+		}
+
+		for (auto cell : overwrite_cells) {
+			module->remove(cell);
+		}
+		for (auto cell : original_cells) {
+			cell->type = ID($get_tag);
+		}
+
+		if (design_changed)
+			modwalker.setup(module);
+	}
+
+	SigSpec divert_users(SigSpec signal)
+	{
+		SigSpec signal_mapped = sigmap(signal);
+		signal_mapped.sort_and_unify();
+		if (GetSize(signal_mapped) < GetSize(signal))
+			log_warning("Detected $overwrite_tag on signal %s which contains repeated bits, this can result in unexpected behavior.\n", log_signal(signal));
+		SigSpec new_wire = module->addWire(NEW_ID, GetSize(signal));
+		for (int i = 0; i < GetSize(new_wire); ++i)
+			divert_users(signal[i], new_wire[i]);
+		return new_wire;
+	}
+
+	void divert_users(SigBit driver_bit, SigBit interposed_bit)
+	{
+		dict<std::pair<Cell *, IdString>, SigSpec> updated_ports;
+		// TODO also check module outputs
+		auto found = modwalker.signal_consumers.find(driver_bit);
+		if (found == modwalker.signal_consumers.end())
+			return;
+		for (auto &consumer : found->second) {
+			if (consumer.cell->type.in(ID($original_tag)))
+				continue;
+			if (sigmap(consumer.cell->getPort(consumer.port)[consumer.offset]) != driver_bit)
+				continue;
+			std::pair<Cell *, IdString> key = {consumer.cell, consumer.port};
+			auto found_port = updated_ports.find(key);
+			if (found_port == updated_ports.end()) {
+				updated_ports.emplace(key, consumer.cell->getPort(consumer.port));
+			}
+			updated_ports[key][consumer.offset] = interposed_bit;
+		}
+		for (auto &update : updated_ports) {
+			update.first.first->setPort(update.first.second, update.second);
+			modwalker.add_cell(update.first.first); // Make sure the next $overwrite_tag sees the new connections
+		}
+	}
+
+	const pool<IdString> &tag_pool(tag_set set) { return tag_sets[set.index]; }
+
+	tag_set singleton(IdString tag)
+	{
+		tmp_tag_set.clear();
+		tmp_tag_set.emplace(tag);
+		return tag_sets(tmp_tag_set);
+	}
+
+	tag_set merge(tag_set a, tag_set b)
+	{
+		if (b < a)
+			std::swap(a, b);
+		if (a.empty() || a == b)
+			return b;
+		auto found = tag_set_union_cache.find(std::make_pair(a, b));
+		if (found == tag_set_union_cache.end()) {
+			tmp_tag_set.clear();
+			auto &a_tags = tag_pool(a);
+			auto &b_tags = tag_pool(b);
+			tmp_tag_set.insert(a_tags.begin(), a_tags.end());
+			tmp_tag_set.insert(b_tags.begin(), b_tags.end());
+			tag_set result = tag_sets(tmp_tag_set);
+			tag_set_union_cache.emplace(std::make_pair(a, b), result);
+			return result;
+		}
+		return found->second;
+	}
+
+	tag_set tags(SigBit bit)
+	{
+		sigmap.apply(bit);
+		auto found = tagged_signals.find(bit);
+		if (found != tagged_signals.end())
+			return found->second;
+		return tag_set();
+	}
+
+	tag_set tags(SigSpec sig)
+	{
+		tag_set result;
+		for (auto bit : sig)
+			result = merge(result, tags(bit));
+		return result;
+	}
+
+	tag_set tags(Cell *cell)
+	{
+		tag_set result;
+		for (auto &conn : cell->connections()) {
+			if (cell->input(conn.first))
+				result = merge(result, tags(conn.second));
+		}
+		return result;
+	}
+
+	void add_tags(SigBit bit, tag_set new_tags)
+	{
+		sigmap.apply(bit);
+		auto &tags = tagged_signals[bit];
+		tag_set merged_tags = merge(tags, new_tags);
+		if (merged_tags == tags)
+			return;
+		tags = merged_tags;
+		auto it = modwalker.signal_consumers.find(bit);
+		if (it == modwalker.signal_consumers.end())
+			return;
+		for (auto &consumer : it->second)
+			if (pending_cells.insert(consumer.cell).second)
+				pending_cell_queue.push_back(consumer.cell);
+	}
+
+	void add_tags(SigSpec sig, tag_set new_tags)
+	{
+		for (auto bit : sigmap(sig))
+			add_tags(bit, new_tags);
+	}
+
+	void add_tags(Cell *cell, tag_set new_tags)
+	{
+		for (auto &conn : cell->connections())
+			if (cell->output(conn.first))
+				add_tags(conn.second, new_tags);
+	}
+
+	void forward_tags(SigSpec dst, SigSpec src)
+	{
+		log_assert(GetSize(dst) == GetSize(src));
+		for (int i = 0; i < GetSize(dst); i++)
+			add_tags(dst[i], tags(src[i]));
+	}
+
+	void propagate_tags()
+	{
+		for (auto cell : module->cells()) {
+			if (cell->type == ID($set_tag)) {
+				pending_cells.insert(cell);
+				pending_cell_queue.push_back(cell);
+			}
+		}
+
+		while (!pending_cell_queue.empty()) {
+			Cell *cell = pending_cell_queue.front();
+			pending_cell_queue.pop_front();
+			pending_cells.erase(cell);
+
+			propagate_tags(cell);
+		}
+	}
+
+	SigBit tag_signal(IdString tag, SigBit bit)
+	{
+		sigmap.apply(bit);
+		if (!bit.is_wire())
+			return State::S0; // Constant value - no tags
+
+		auto found = tag_signals.find(std::make_pair(tag, bit));
+		if (found != tag_signals.end())
+			return found->second;
+
+		if (!tag_pool(tags(bit)).count(tag))
+			return State::S0; // Statically known to not have this tag
+
+		// TODO handle module inputs
+		auto drivers = modwalker.signal_drivers.find(bit);
+		if (drivers == modwalker.signal_drivers.end() || drivers->second.empty())
+			return State::S0; // No driver - no tags
+
+		log_assert(drivers->second.size() == 1);
+		auto driver = *drivers->second.begin();
+
+		emit_tag_signals(tag, driver.cell);
+
+		found = tag_signals.find(std::make_pair(tag, bit));
+		log_assert(found != tag_signals.end());
+		return found->second;
+	}
+
+	SigSpec tag_signal(IdString tag, SigSpec sig)
+	{
+		SigSpec result;
+		for (auto bit : sig)
+			result.append(tag_signal(tag, bit));
+		return result;
+	}
+
+	SigSpec tag_group_signal(IdString tag_group, SigSpec sig)
+	{
+		sigmap.apply(sig);
+		if (sig.is_fully_const() || tag_groups.count(tag_group) == 0)
+			return Const(0, GetSize(sig));
+
+		auto found = tag_group_signals.find(std::make_pair(tag_group, sig));
+		if (found != tag_group_signals.end())
+			return found->second;
+
+		SigSpec combined;
+
+		for (auto &tag : tag_groups[tag_group]) {
+			auto tag_sig = tag_signal(tag, sig);
+
+			if (!GetSize(combined))
+				combined = tag_sig;
+			else
+				combined = autoOr(NEW_ID, combined, tag_sig);
+		}
+
+		if (!GetSize(combined))
+			combined = Const(0, GetSize(sig));
+
+		tag_group_signals.emplace(std::make_pair(tag_group, sig), combined);
+		return combined;
+	}
+
+	void emit_tag_signal(IdString tag, SigBit bit, SigBit tag_bit)
+	{
+		sigmap.apply(bit);
+		sigmap.apply(tag_bit);
+
+		if (!tag_pool(tags(bit)).count(tag))
+			return;
+
+		auto key = std::make_pair(tag, bit);
+		auto found = tag_signals.find(key);
+		if (found != tag_signals.end()) {
+			module->connect(found->second, tag_bit);
+			return;
+		}
+		tag_signals.emplace(key, tag_bit);
+	}
+
+	void emit_tag_signal(IdString tag, SigSpec sig, SigSpec tag_sig)
+	{
+		log_assert(GetSize(sig) == GetSize(tag_sig));
+		for (int i = 0; i < GetSize(sig); i++)
+			emit_tag_signal(tag, sig[i], tag_sig[i]);
+	}
+
+	void emit_tag_signals(IdString tag, Cell *cell)
+	{
+		if (!pending_cells.insert(cell).second) {
+			// We have a cycle, emit placeholder wires which will be connected
+			// when the outer call for this tag/cell returns
+			for (auto &conn : cell->connections())
+				if (cell->output(conn.first))
+					emit_tag_signal(tag, conn.second, module->addWire(NEW_ID, GetSize(conn.second)));
+
+			return;
+		}
+
+		process_cell(tag, cell);
+
+		pending_cells.erase(cell);
+	}
+
+	void propagate_tags(Cell *cell)
+	{
+		if (cell->type == ID($set_tag)) {
+			IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
+			if (all_tags.insert(tag).second) {
+				auto group_sep = tag.str().find(':');
+				IdString tag_group = group_sep != std::string::npos ? tag.str().substr(0, group_sep) : tag;
+				tag_groups[tag_group].insert(tag);
+				group_of_tag[tag] = tag_group;
+			}
+
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+			// TODO handle constant set/clr masks
+			add_tags(sig_y, singleton(tag));
+			forward_tags(sig_y, sig_a);
+			return;
+		}
+
+		if (cell->type == ID($get_tag)) {
+			return;
+		}
+
+		if (cell->type.in(ID($not), ID($pos))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A);
+			if (cell->type.in(ID($not), ID($or))) {
+				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
+			}
+			forward_tags(sig_y, sig_a);
+			return;
+		}
+
+		if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($bweqx))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A);
+			auto sig_b = cell->getPort(ID::B);
+			if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
+				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
+				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
+			}
+			forward_tags(sig_y, sig_a);
+			forward_tags(sig_y, sig_b);
+			return;
+		}
+
+		if (cell->type.in(ID($mux), ID($bwmux))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+			auto &sig_b = cell->getPort(ID::B);
+			auto sig_s = cell->getPort(ID::S);
+
+			if (cell->type == ID($mux))
+				sig_s = SigSpec(sig_s[0], GetSize(sig_y));
+
+			forward_tags(sig_y, sig_a);
+			forward_tags(sig_y, sig_b);
+			forward_tags(sig_y, sig_s);
+			return;
+		}
+
+		if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
+			FfData ff(&initvals, cell);
+
+			if (ff.has_clk || ff.has_gclk)
+				forward_tags(ff.sig_q, ff.sig_d);
+			return;
+		}
+
+		// Single output but, sensitive to all inputs
+		if (cell->type.in(
+			ID($le), ID($lt), ID($ge), ID($gt),
+			ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor),
+			ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and),
+			ID($eq), ID($ne)
+		)) {
+			auto &sig_y = cell->getPort(ID::Y);
+
+			add_tags(sig_y[0], tags(cell));
+			return;
+		}
+
+
+		// Fallback, propagate tags from all inputs to all outputs
+		add_tags(cell, tags(cell));
+
+		if (cell->type.in(
+			ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_),
+			ID($_XOR_), ID($_XNOR_), ID($_NOT_), ID($_BUF_), ID($_MUX_),
+
+			ID($assert), ID($assume)
+		)) {
+			return;
+		}
+
+		// This isn't a correctness concern (unless cell is a module generating
+		// tags), but we may end up generating a lot of extra logic when
+		// reaching this
+		if (!warned_cells.insert(cell).second)
+			return;
+		if (cell->type.isPublic())
+			log_warning("Unhandled cell %s (%s) during tag propagation\n", log_id(cell), log_id(cell->type));
+		else
+			log_debug("Unhandled cell %s (%s) during tag propagation\n", log_id(cell), log_id(cell->type));
+	}
+
+	void process_cell(IdString tag, Cell *cell)
+	{
+		if (cell->type == ID($set_tag)) {
+			IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
+
+			auto tag_sig_a = tag_signal(tag, cell->getPort(ID::A));
+			auto &sig_y = cell->getPort(ID::Y);
+
+			if (cell_tag == tag) {
+				auto &sig_set = cell->getPort(ID::SET);
+				auto &sig_clr = cell->getPort(ID::CLR);
+				tag_sig_a = autoAnd(NEW_ID, tag_sig_a, autoNot(NEW_ID, sig_clr));
+				tag_sig_a = autoOr(NEW_ID, tag_sig_a, sig_set);
+			}
+
+			emit_tag_signal(tag, sig_y, tag_sig_a);
+			return;
+		}
+
+		if (cell->type == ID($get_tag)) {
+			log_assert(false);
+		}
+
+		if (cell->type.in(ID($not), ID($pos), ID($_NOT_), ID($_BUF_))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A);
+			if (cell->type.in(ID($not), ID($or))) {
+				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
+			}
+			emit_tag_signal(tag, sig_y, tag_signal(tag, sig_a));
+			return;
+		}
+
+		if (cell->type.in(
+			ID($and), ID($or),
+			ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_)
+		)) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A);
+			auto sig_b = cell->getPort(ID::B);
+			if (cell->type.in(ID($and), ID($or))) {
+				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
+				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
+			}
+
+			bool inv_a = false;
+			bool inv_b = false;
+
+			if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
+				inv_a ^= true, inv_b ^= true;
+			if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
+				inv_b ^= true;
+
+			if (inv_a)
+				sig_a = autoNot(NEW_ID, sig_a);
+			if (inv_b)
+				sig_b = autoNot(NEW_ID, sig_b);
+
+			auto group_sig_a = tag_group_signal(tag, sig_a);
+			auto group_sig_b = tag_group_signal(tag, sig_b);
+
+			auto tag_sig_a = tag_signal(tag, sig_a);
+			auto tag_sig_b = tag_signal(tag, sig_b);
+
+
+			// Does this input allow propagating (doesn't fix output or same tag group)
+			sig_a = autoOr(NEW_ID, sig_a, group_sig_a);
+			sig_b = autoOr(NEW_ID, sig_b, group_sig_b);
+
+			// Mask input tags by whether the other side allows propagation
+			tag_sig_a = autoAnd(NEW_ID, tag_sig_a, sig_b);
+			tag_sig_b = autoAnd(NEW_ID, tag_sig_b, sig_a);
+
+
+			auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b);
+			emit_tag_signal(tag, sig_y, tag_sig);
+			return;
+		}
+
+		if (cell->type.in(ID($xor), ID($xnor), ID($bweqx), ID($_XOR_), ID($_XNOR_))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A);
+			auto sig_b = cell->getPort(ID::B);
+			if (cell->type.in(ID($xor), ID($xnor))) {
+				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
+				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
+			}
+
+			auto tag_sig_a = tag_signal(tag, sig_a);
+			auto tag_sig_b = tag_signal(tag, sig_b);
+
+			auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b);
+			emit_tag_signal(tag, sig_y, tag_sig);
+			return;
+		}
+
+
+		if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+			auto &sig_b = cell->getPort(ID::B);
+			auto sig_s = cell->getPort(ID::S);
+
+			if (cell->type == ID($mux))
+				sig_s = SigSpec(sig_s[0], GetSize(sig_y));
+
+			auto group_sig_a = tag_group_signal(tag, sig_a);
+			auto group_sig_b = tag_group_signal(tag, sig_b);
+			auto group_sig_s = tag_group_signal(tag, sig_s);
+
+			auto prop_s = autoOr(NEW_ID,
+					autoXor(NEW_ID, sig_a, sig_b),
+					autoOr(NEW_ID, group_sig_a, group_sig_b));
+
+			auto prop_a = autoOr(NEW_ID, autoNot(NEW_ID, sig_s), group_sig_s);
+			auto prop_b = autoOr(NEW_ID, sig_s, group_sig_s);
+
+			auto tag_sig_a = tag_signal(tag, sig_a);
+			auto tag_sig_b = tag_signal(tag, sig_b);
+			auto tag_sig_s = tag_signal(tag, sig_s);
+
+			tag_sig_a = autoAnd(NEW_ID, tag_sig_a, prop_a);
+			tag_sig_b = autoAnd(NEW_ID, tag_sig_b, prop_b);
+			tag_sig_s = autoAnd(NEW_ID, tag_sig_s, prop_s);
+
+			auto tag_sig = autoOr(NEW_ID, tag_sig_s,
+					autoOr(NEW_ID, tag_sig_a, tag_sig_b));
+			emit_tag_signal(tag, sig_y, tag_sig);
+			return;
+		}
+
+		if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A);
+			auto sig_b = cell->getPort(ID::B);
+			int width = std::max(GetSize(sig_a), GetSize(sig_b));
+			sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
+			sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
+
+			auto group_sig_a = tag_group_signal(tag, sig_a);
+			auto group_sig_b = tag_group_signal(tag, sig_b);
+
+			auto tag_sig_a = tag_signal(tag, sig_a);
+			auto tag_sig_b = tag_signal(tag, sig_b);
+
+			auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b);
+			// The output can only be affected by the tagged inputs if all group-untagged bits are equal
+
+			auto masked_a = autoOr(NEW_ID, sig_a, group_sig);
+			auto masked_b = autoOr(NEW_ID, sig_b, group_sig);
+
+			auto prop = autoEq(NEW_ID, masked_a, masked_b);
+
+			auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b}));
+			tag_sig.extend_u0(GetSize(sig_y), false);
+			emit_tag_signal(tag, sig_y, tag_sig);
+			return;
+		}
+
+
+		if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A);
+			auto sig_b = cell->getPort(ID::B);
+			int width = std::max(GetSize(sig_a), GetSize(sig_b));
+			sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
+			sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
+
+			if (cell->type.in(ID($gt), ID($le)))
+				std::swap(sig_a, sig_b);
+
+			auto group_sig_a = tag_group_signal(tag, sig_a);
+			auto group_sig_b = tag_group_signal(tag, sig_b);
+
+			auto tag_sig_a = tag_signal(tag, sig_a);
+			auto tag_sig_b = tag_signal(tag, sig_b);
+
+			auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b);
+			// The output can only be affected by the tagged inputs if the greatest possible sig_a is
+			// greater or equal to the least possible sig_b
+			auto masked_a = autoOr(NEW_ID, sig_a, group_sig);
+			auto masked_b = autoAnd(NEW_ID, sig_b, autoNot(NEW_ID, group_sig));
+
+			auto prop = autoGe(NEW_ID, masked_a, masked_b);
+
+			auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b}));
+			tag_sig.extend_u0(GetSize(sig_y), false);
+			emit_tag_signal(tag, sig_y, tag_sig);
+			return;
+		}
+
+		if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A);
+
+			auto group_sig_a = tag_group_signal(tag, sig_a);
+			auto tag_sig_a = tag_signal(tag, sig_a);
+
+			if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not)))
+				sig_a = autoNot(NEW_ID, sig_a);
+
+			auto filled = autoOr(NEW_ID, sig_a, group_sig_a);
+
+			auto prop = autoReduceAnd(NEW_ID, filled);
+			auto tagged = autoReduceOr(NEW_ID, tag_sig_a);
+			auto tag_sig = autoAnd(NEW_ID, prop, tagged);
+			tag_sig.extend_u0(GetSize(sig_y), false);
+			emit_tag_signal(tag, sig_y, tag_sig);
+			return;
+		}
+
+		if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
+			FfData ff(&initvals, cell);
+			// TODO handle some more variants
+			if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
+				if (ff.has_clk && !tags(ff.sig_clk).empty())
+					log_warning("Tags on CLK input ignored for %s (%s)\n", log_id(cell), log_id(cell->type));
+
+				int width = ff.width;
+
+				auto sig_q = ff.sig_q;
+				auto sig_d = ff.sig_d;
+
+				ff.name = NEW_ID;
+				ff.cell = nullptr;
+				ff.sig_d = tag_signal(tag, ff.sig_d);
+				ff.sig_q = module->addWire(NEW_ID, width);
+				ff.is_anyinit = false;
+				ff.val_init = Const(0, width);
+				ff.emit();
+
+				emit_tag_signal(tag, sig_q, ff.sig_q);
+				return;
+			} else {
+				log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", log_id(cell), log_id(cell->type));
+
+				// For unhandled FFs, the default propagation would cause combinational loops
+				emit_tag_signal(tag, ff.sig_q, Const(0, ff.width));
+				return;
+			}
+		}
+
+		// Fallback
+		SigSpec tag_input;
+
+		for (auto &conn : cell->connections()) {
+			if (cell->input(conn.first)) {
+				auto tag_sig = tag_signal(tag, conn.second);
+				tag_input.append(tag_sig);
+			}
+		}
+
+		SigBit any_tagged = autoReduceOr(NEW_ID, tag_input);
+
+		for (auto &conn : cell->connections()) {
+			if (cell->output(conn.first)) {
+				emit_tag_signal(tag, conn.second, SigSpec(any_tagged, GetSize(conn.second)));
+			}
+		}
+
+		// As fallback we propagate all tags from all inputs to all outputs,
+		// which is an over-approximation (unless the cell is a module that
+		// generates tags itself in which case it could be arbitrary).
+		if (warned_cells.insert(cell).second)
+			log_warning("Unhandled cell %s (%s) while emitting tag signals\n", log_id(cell), log_id(cell->type));
+	}
+
+	void emit_tags()
+	{
+		warned_cells.clear();
+		std::vector<Cell *> get_tag_cells;
+		for (auto cell : module->selected_cells())
+			if (cell->type == ID($get_tag))
+				get_tag_cells.push_back(cell);
+
+		for (auto cell : get_tag_cells) {
+			auto &sig_a = cell->getPort(ID::A);
+			IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
+
+			tag_signal(tag, sig_a);
+		}
+
+		if (options.tag_public)
+		{
+			std::vector<Wire *> public_wires;
+
+			for (auto wire : module->selected_wires())
+				if (wire->name.isPublic())
+					public_wires.push_back(wire);
+
+			for (auto wire : public_wires) {
+				for (auto tag : tag_pool(tags(SigSpec(wire)))) {
+					auto tag_sig = tag_signal(tag, SigSpec(wire));
+					if (tag_sig.is_fully_zero())
+						continue;
+
+					int index = 0;
+					auto name = module->uniquify(stringf("%s:%s", wire->name.c_str(), tag.c_str() + 1), index);
+					auto hdlname = wire->get_hdlname_attribute();
+
+					if (!hdlname.empty())
+						hdlname.back() += index ?
+								stringf(":%s_%d", tag.c_str() + 1, index) :
+								stringf(":%s", tag.c_str() + 1);
+
+					auto tag_wire = module->addWire(name, wire->width);
+
+					tag_wire->set_bool_attribute(ID::keep);
+					tag_wire->set_bool_attribute(ID(dft_tag));
+					if (!hdlname.empty())
+						tag_wire->set_hdlname_attribute(hdlname);
+
+					module->connect(tag_wire, tag_sig);
+				}
+			}
+		}
+	}
+
+	void replace_dft_cells()
+	{
+		std::vector<Cell *> get_tag_cells;
+		std::vector<Cell *> set_tag_cells;
+		for (auto cell : module->cells()) {
+			if (cell->type == ID($get_tag))
+				get_tag_cells.push_back(cell);
+
+			if (cell->type == ID($set_tag))
+				set_tag_cells.push_back(cell);
+
+			log_assert(!cell->type.in(ID($overwrite_tag), ID($original_tag)));
+		}
+
+		for (auto cell : set_tag_cells) {
+			auto &sig_a = cell->getPort(ID::A);
+			auto &sig_y = cell->getPort(ID::Y);
+			module->connect(sig_y, sig_a);
+			module->remove(cell);
+		}
+
+		for (auto cell : get_tag_cells) {
+			auto &sig_a = cell->getPort(ID::A);
+			auto &sig_y = cell->getPort(ID::Y);
+			IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
+
+			auto tag_sig = tag_signal(tag, sig_a);
+			module->connect(sig_y, tag_sig);
+			module->remove(cell);
+		}
+	}
+
+
+	SigSpec autoAnd(IdString name, const SigSpec &sig_a, const SigSpec &sig_b)
+	{
+		log_assert(GetSize(sig_a) == GetSize(sig_b));
+		if (sig_a.is_fully_zero() || sig_b.is_fully_ones() || sig_a == sig_b)
+			return sig_a;
+		if (sig_a.is_fully_ones() || sig_b.is_fully_zero())
+			return sig_b;
+
+		return module->And(name, sig_a, sig_b);
+	}
+
+	SigSpec autoOr(IdString name, const SigSpec &sig_a, const SigSpec &sig_b)
+	{
+		log_assert(GetSize(sig_a) == GetSize(sig_b));
+		if (sig_a.is_fully_ones() || sig_b.is_fully_zero() || sig_a == sig_b)
+			return sig_a;
+		if (sig_a.is_fully_zero() || sig_b.is_fully_ones())
+			return sig_b;
+
+		return module->Or(name, sig_a, sig_b);
+	}
+
+	SigSpec autoXor(IdString name, const SigSpec &sig_a, const SigSpec &sig_b)
+	{
+		log_assert(GetSize(sig_a) == GetSize(sig_b));
+		if (sig_a == sig_b)
+			return Const(State::S0, GetSize(sig_a));
+		if (sig_a.is_fully_zero())
+			return sig_b;
+		if (sig_b.is_fully_zero())
+			return sig_a;
+		if (sig_a.is_fully_ones())
+			return autoNot(name, sig_b);
+		if (sig_b.is_fully_ones())
+			return autoNot(name, sig_a);
+		return module->Xor(name, sig_a, sig_b);
+	}
+
+	SigSpec autoXnor(IdString name, const SigSpec &sig_a, const SigSpec &sig_b)
+	{
+		log_assert(GetSize(sig_a) == GetSize(sig_b));
+		if (sig_a == sig_b)
+			return Const(State::S1, GetSize(sig_a));
+		if (sig_a.is_fully_ones())
+			return sig_b;
+		if (sig_b.is_fully_ones())
+			return sig_a;
+		if (sig_a.is_fully_zero())
+			return autoNot(name, sig_b);
+		if (sig_b.is_fully_zero())
+			return autoNot(name, sig_a);
+		return module->Xnor(name, sig_a, sig_b);
+	}
+
+	SigSpec autoNot(IdString name, const SigSpec &sig_a)
+	{
+		if (sig_a.is_fully_const()) {
+			auto const_val = sig_a.as_const();
+			for (auto &bit : const_val.bits)
+				bit = bit == State::S0 ? State::S1 : bit == State::S1 ? State::S0 : bit;
+			return const_val;
+		}
+		return module->Not(name, sig_a);
+	}
+
+	SigSpec autoEq(IdString name, const SigSpec &sig_a, const SigSpec &sig_b)
+	{
+		log_assert(GetSize(sig_a) == GetSize(sig_b));
+		if (sig_a == sig_b)
+			return State::S1;
+		for (int i = 0; i < GetSize(sig_a); i++) {
+			auto bit_a = sig_a[i];
+			auto bit_b = sig_b[i];
+			if (bit_a.is_wire() || bit_b.is_wire())
+				continue;
+			if ((bit_a.data == State::S0 && bit_b.data == State::S1) ||
+					(bit_a.data == State::S1 && bit_b.data == State::S0))
+				return State::S0;
+		}
+
+		return module->Eq(name, sig_a, sig_b);
+	}
+
+	SigSpec autoGe(IdString name, const SigSpec &sig_a, const SigSpec &sig_b)
+	{
+		log_assert(GetSize(sig_a) == GetSize(sig_b));
+		if (sig_a == sig_b || sig_a.is_fully_ones())
+			return State::S1;
+		if (sig_b.is_fully_zero())
+			return State::S1;
+
+		return module->Ge(name, sig_a, sig_b);
+	}
+
+	SigSpec autoReduceAnd(IdString name, const SigSpec &sig_a)
+	{
+		if (GetSize(sig_a) == 0)
+			return State::S1;
+
+		if (GetSize(sig_a) == 1 || sig_a == SigSpec(sig_a[0], GetSize(sig_a)))
+			return sig_a[0];
+		for (auto bit : sig_a)
+			if (!bit.is_wire() && bit.data == State::S0)
+				return State::S0;
+		if (sig_a.is_fully_ones())
+			return State::S1;
+		return module->ReduceAnd(name, sig_a);
+	}
+
+	SigSpec autoReduceOr(IdString name, const SigSpec &sig_a)
+	{
+		if (GetSize(sig_a) == 0)
+			return State::S0;
+
+		if (GetSize(sig_a) == 1 || sig_a == SigSpec(sig_a[0], GetSize(sig_a)))
+			return sig_a[0];
+		for (auto bit : sig_a)
+			if (!bit.is_wire() && bit.data == State::S1)
+				return State::S1;
+		if (sig_a.is_fully_zero())
+			return State::S0;
+		return module->ReduceOr(name, sig_a);
+	}
+};
+
+struct DftTagPass : public Pass {
+	DftTagPass() : Pass("dft_tag", "create tagging logic for data flow tracking") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    dft_tag [options] [selection]\n");
+		log("\n");
+		log("This pass... TODO\n");
+		log("\n");
+		log("    -overwrite-only\n");
+		log("        Only process $overwrite_tag and $original_tag cells.\n");
+		log("    -tag-public\n");
+		log("        For each public wire that may carry tagged data, create a new public\n");
+		log("        wire (named <wirename>:<tagname>) that carries the tag bits. Note\n");
+		log("        that without this, tagging logic will only be emitted as required\n");
+		log("        for uses of $get_tag.\n");
+		log("\n");
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		DftTagOptions options;
+
+		log_header(design, "Executing DFT_TAG pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-tag-public") {
+				options.tag_public = true;
+				continue;
+			}
+			if (args[argidx] == "-overwrite-only") {
+				options.overwrite_only = true;
+				continue;
+			}
+			break;
+		}
+
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules()) {
+			DftTagWorker worker(module, options);
+
+			log_debug("Resolve overwrite_tag and original_tag.\n");
+			worker.resolve_overwrites();
+
+			if (options.overwrite_only)
+				continue;
+
+			log_debug("Propagate tagged signals.\n");
+			worker.propagate_tags();
+
+			log_debug("Emit tag signals and logic.\n");
+			worker.emit_tags();
+
+			log_debug("Replace dft cells.\n");
+			worker.replace_dft_cells();
+		}
+	}
+} DftTagPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/yosys/passes/cmds/future.cc b/yosys/passes/cmds/future.cc
new file mode 100644
index 00000000000..b03613c9bd2
--- /dev/null
+++ b/yosys/passes/cmds/future.cc
@@ -0,0 +1,140 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/celltypes.h"
+#include "kernel/ff.h"
+#include "kernel/ffinit.h"
+#include "kernel/modtools.h"
+#include "kernel/sigtools.h"
+#include "kernel/utils.h"
+#include "kernel/yosys.h"
+#include <deque>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct FutureOptions {
+};
+
+struct FutureWorker {
+	Module *module;
+	FutureOptions options;
+	ModWalker modwalker;
+	SigMap &sigmap;
+	FfInitVals initvals;
+
+	dict<SigBit, SigBit> future_ff_signals;
+
+	FutureWorker(Module *module, FutureOptions options) :
+		module(module), options(options), modwalker(module->design), sigmap(modwalker.sigmap)
+	{
+		modwalker.setup(module);
+		initvals.set(&modwalker.sigmap, module);
+
+		std::vector<Cell *> replaced_cells;
+		for (auto cell : module->selected_cells()) {
+			if (cell->type != ID($future_ff))
+				continue;
+
+			module->connect(cell->getPort(ID::Y), future_ff(cell->getPort(ID::A)));
+			replaced_cells.push_back(cell);
+		}
+
+		for (auto cell : replaced_cells) {
+			module->remove(cell);
+		}
+	}
+
+	SigSpec future_ff(SigSpec sig)
+	{
+		for (auto &bit : sig) {
+			bit = future_ff(bit);
+		}
+		return sig;
+	}
+
+	SigBit future_ff(SigBit bit)
+	{
+		if (!bit.is_wire())
+			return bit;
+
+		auto found = future_ff_signals.find(bit);
+		if (found != future_ff_signals.end())
+			return found->second;
+
+		auto found_driver = modwalker.signal_drivers.find(bit);
+		if (found_driver == modwalker.signal_drivers.end() || found_driver->second.size() < 1)
+			log_error("No driver for future_ff target signal %s found\n", log_signal(bit));
+		if (found_driver->second.size() > 1)
+			log_error("Found multiple drivers for future_ff target signal %s\n", log_signal(bit));
+		auto driver = *found_driver->second.begin();
+		if (!RTLIL::builtin_ff_cell_types().count(driver.cell->type) && driver.cell->type != ID($anyinit))
+			log_error("Driver for future_ff target signal %s has non-FF cell type %s\n", log_signal(bit), log_id(driver.cell->type));
+
+		FfData ff(&initvals, driver.cell);
+
+		if (!ff.has_clk && !ff.has_gclk)
+			log_error("Driver for future_ff target signal %s has cell type %s, which is not clocked\n", log_signal(bit),
+				  log_id(driver.cell->type));
+
+		ff.unmap_ce_srst();
+
+		// We insert all bits into the mapping, because unmap_ce_srst might
+		// have removed the cell which is still present in the modwalker data.
+		// By inserting all bits driven by th FF we ensure that we'll never use
+		// that stale modwalker data again.
+
+		for (int i = 0; i < ff.width; ++i) {
+			future_ff_signals.emplace(ff.sig_q[i], ff.sig_d[i]);
+		}
+
+		return future_ff_signals.at(bit);
+	}
+};
+
+struct FuturePass : public Pass {
+	FuturePass() : Pass("future", "resolve future sampled value functions") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    future [options] [selection]\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		FutureOptions options;
+
+		log_header(design, "Executing FUTURE pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+
+			break;
+		}
+
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules()) {
+			FutureWorker worker(module, options);
+		}
+	}
+} FuturePass;
+
+PRIVATE_NAMESPACE_END
diff --git a/yosys/passes/cmds/glift.cc b/yosys/passes/cmds/glift.cc
index 439ded07685..8553b02a541 100644
--- a/yosys/passes/cmds/glift.cc
+++ b/yosys/passes/cmds/glift.cc
@@ -582,7 +582,7 @@ struct GliftPass : public Pass {
 			for (auto cell : module->selected_cells()) {
 				RTLIL::Module *tpl = design->module(cell->type);
 				if (tpl != nullptr) {
-					if (topo_modules.database.count(tpl) == 0)
+					if (!topo_modules.has_node(tpl))
 						worklist.push_back(tpl);
 					topo_modules.edge(tpl, module);
 					non_top_modules.insert(cell->type);
diff --git a/yosys/passes/cmds/logcmd.cc b/yosys/passes/cmds/logcmd.cc
index 20cbd894345..3b82ac48c0c 100644
--- a/yosys/passes/cmds/logcmd.cc
+++ b/yosys/passes/cmds/logcmd.cc
@@ -31,7 +31,8 @@ struct LogPass : public Pass {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    log string\n");
+		log("    log [options] string\n");
+		log("    log [ -push | -pop ]\n");
 		log("\n");
 		log("Print the given string to the screen and/or the log file. This is useful for TCL\n");
 		log("scripts, because the TCL command \"puts\" only goes to stdout but not to\n");
@@ -52,14 +53,26 @@ struct LogPass : public Pass {
 		log("    -n\n");
 		log("        do not append a newline\n");
 		log("\n");
+		log("    -header\n");
+		log("        log a pass header\n");
+		log("\n");
+		log("    -push\n");
+		log("        push a new level on the pass counter\n");
+		log("\n");
+		log("    -pop\n");
+		log("        pop from the pass counter\n");
+		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design*) override
+	void execute(std::vector<std::string> args, RTLIL::Design* design) override
 	{
 		size_t argidx;
 		bool to_stdout = false;
 		bool to_stderr = false;
 		bool to_log    = true;
 		bool newline   = true;
+		bool header    = false;
+		bool push      = false;
+		bool pop       = false;
 		std::string text;
 
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -68,15 +81,30 @@ struct LogPass : public Pass {
 			else if (args[argidx] == "-stderr") to_stderr = true;
 			else if (args[argidx] == "-nolog")  to_log    = false;
 			else if (args[argidx] == "-n")      newline   = false;
+			else if (args[argidx] == "-header") header    = true;
+			else if (args[argidx] == "-push")   push      = true;
+			else if (args[argidx] == "-pop")    pop       = true;
 			else break;
 		}
+
+		if ((push || pop) && args.size() != 2)
+			log_cmd_error("Bad usage: 'log -push' or 'log -pop' must be used without other arguments.\n");
+
+		if (push) { log_push(); return; }
+		if (pop)  { log_pop(); return; }
+
 		for (; argidx < args.size(); argidx++)
 			text += args[argidx] + ' ';
 		if (!text.empty()) text.resize(text.size()-1);
 
-		if (to_stdout) fprintf(stdout, (newline ? "%s\n" : "%s"), text.c_str());
-		if (to_stderr) fprintf(stderr, (newline ? "%s\n" : "%s"), text.c_str());
-		if (to_log)    log    (        (newline ? "%s\n" : "%s"), text.c_str());
+		const char *fmtline = newline ? "%s\n" : "%s";
+
+		if (to_stdout) fprintf(stdout, fmtline, text.c_str());
+		if (to_stderr) fprintf(stderr, fmtline, text.c_str());
+		if (to_log) {
+			if (!header) log(fmtline, text.c_str());
+			else log_header(design, fmtline, text.c_str());
+		}
 	}
 } LogPass;
 
diff --git a/yosys/passes/cmds/plugin.cc b/yosys/passes/cmds/plugin.cc
index 08b4aa8c4ee..4ad7c165b1e 100644
--- a/yosys/passes/cmds/plugin.cc
+++ b/yosys/passes/cmds/plugin.cc
@@ -103,7 +103,6 @@ void load_plugin(std::string filename, std::vector<std::string> aliases)
 
 			loaded_plugins[orig_filename] = hdl;
 			Pass::init_register();
-
 		}
 	}
 
diff --git a/yosys/passes/cmds/rename.cc b/yosys/passes/cmds/rename.cc
index da4ba2f17e9..3f8d807b36d 100644
--- a/yosys/passes/cmds/rename.cc
+++ b/yosys/passes/cmds/rename.cc
@@ -134,7 +134,6 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
 				cell->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 });
 				renames.emplace_back(cell, new_id);
 			}
-			break;
 		}
 
 		if (cell->type.in(ID($anyconst), ID($anyseq), ID($anyinit), ID($allconst), ID($allseq))) {
@@ -165,6 +164,20 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
 				}
 			}
 		}
+
+
+		if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($live), ID($fair), ID($check))) {
+			has_witness_signals = true;
+			if (cell->name.isPublic())
+				continue;
+			std::string name = stringf("%s_%s", cell->type.c_str() + 1, cell->name.c_str() + 1);
+			for (auto &c : name)
+				if ((c < 'a' || c > 'z') && (c < 'A' || c > 'Z') && (c < '0' || c > '9') && c != '_')
+					c = '_';
+			auto new_id = module->uniquify("\\_witness_." + name);
+			renames.emplace_back(cell, new_id);
+			cell->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 });
+		}
 	}
 	for (auto rename : renames) {
 		module->rename(rename.first, rename.second);
diff --git a/yosys/passes/cmds/scc.cc b/yosys/passes/cmds/scc.cc
index 81881832cd7..197bd931966 100644
--- a/yosys/passes/cmds/scc.cc
+++ b/yosys/passes/cmds/scc.cc
@@ -27,7 +27,6 @@
 #include "kernel/log.h"
 #include <stdlib.h>
 #include <stdio.h>
-#include <set>
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -39,18 +38,18 @@ struct SccWorker
 	SigMap sigmap;
 	CellTypes ct, specifyCells;
 
-	std::set<RTLIL::Cell*> workQueue;
-	std::map<RTLIL::Cell*, std::set<RTLIL::Cell*>> cellToNextCell;
-	std::map<RTLIL::Cell*, RTLIL::SigSpec> cellToPrevSig, cellToNextSig;
+	pool<RTLIL::Cell*> workQueue;
+	dict<RTLIL::Cell*, pool<RTLIL::Cell*>> cellToNextCell;
+	dict<RTLIL::Cell*, RTLIL::SigSpec> cellToPrevSig, cellToNextSig;
 
-	std::map<RTLIL::Cell*, std::pair<int, int>> cellLabels;
-	std::map<RTLIL::Cell*, int> cellDepth;
-	std::set<RTLIL::Cell*> cellsOnStack;
+	dict<RTLIL::Cell*, std::pair<int, int>> cellLabels;
+	dict<RTLIL::Cell*, int> cellDepth;
+	pool<RTLIL::Cell*> cellsOnStack;
 	std::vector<RTLIL::Cell*> cellStack;
 	int labelCounter;
 
-	std::map<RTLIL::Cell*, int> cell2scc;
-	std::vector<std::set<RTLIL::Cell*>> sccList;
+	dict<RTLIL::Cell*, int> cell2scc;
+	std::vector<pool<RTLIL::Cell*>> sccList;
 
 	void run(RTLIL::Cell *cell, int depth, int maxDepth)
 	{
@@ -85,7 +84,7 @@ struct SccWorker
 			else
 			{
 				log("Found an SCC:");
-				std::set<RTLIL::Cell*> scc;
+				pool<RTLIL::Cell*> scc;
 				while (cellsOnStack.count(cell) > 0) {
 					RTLIL::Cell *c = cellStack.back();
 					cellStack.pop_back();
@@ -199,11 +198,11 @@ struct SccWorker
 
 		for (auto cell : workQueue)
 		{
-			cellToNextCell[cell] = sigToNextCells.find(cellToNextSig[cell]);
+			sigToNextCells.find(cellToNextSig[cell], cellToNextCell[cell]);
 
 			if (!nofeedbackMode && cellToNextCell[cell].count(cell)) {
 				log("Found an SCC:");
-				std::set<RTLIL::Cell*> scc;
+				pool<RTLIL::Cell*> scc;
 				log(" %s", RTLIL::id2cstr(cell->name));
 				cell2scc[cell] = sccList.size();
 				scc.insert(cell);
@@ -231,7 +230,7 @@ struct SccWorker
 	{
 		for (int i = 0; i < int(sccList.size()); i++)
 		{
-			std::set<RTLIL::Cell*> &cells = sccList[i];
+			pool<RTLIL::Cell*> &cells = sccList[i];
 			RTLIL::SigSpec prevsig, nextsig, sig;
 
 			for (auto cell : cells) {
@@ -295,7 +294,7 @@ struct SccPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		std::map<std::string, std::string> setAttr;
+		dict<std::string, std::string> setAttr;
 		bool allCellTypes = false;
 		bool selectMode = false;
 		bool nofeedbackMode = false;
diff --git a/yosys/passes/cmds/select.cc b/yosys/passes/cmds/select.cc
index 03d00816e1b..e455baf7c7f 100644
--- a/yosys/passes/cmds/select.cc
+++ b/yosys/passes/cmds/select.cc
@@ -1065,6 +1065,10 @@ struct SelectPass : public Pass {
 		log("        selection is non-empty. i.e. produce an error if no object or module\n");
 		log("        matching the selection is found.\n");
 		log("\n");
+		log("    -assert-mod-count N\n");
+		log("        do not modify the current selection. instead assert that the given\n");
+		log("        selection contains exactly N modules (partially or fully selected).\n");
+		log("\n");
 		log("    -assert-count N\n");
 		log("        do not modify the current selection. instead assert that the given\n");
 		log("        selection contains exactly N objects.\n");
@@ -1263,6 +1267,7 @@ struct SelectPass : public Pass {
 		bool got_module = false;
 		bool assert_none = false;
 		bool assert_any = false;
+		int assert_modcount = -1;
 		int assert_count = -1;
 		int assert_max = -1;
 		int assert_min = -1;
@@ -1291,6 +1296,10 @@ struct SelectPass : public Pass {
 				assert_any = true;
 				continue;
 			}
+			if (arg == "-assert-mod-count" && argidx+1 < args.size()) {
+				assert_modcount = atoi(args[++argidx].c_str());
+				continue;
+			}
 			if (arg == "-assert-count" && argidx+1 < args.size()) {
 				assert_count = atoi(args[++argidx].c_str());
 				continue;
@@ -1345,7 +1354,8 @@ struct SelectPass : public Pass {
 			}
 			if (arg.size() > 0 && arg[0] == '-')
 				log_cmd_error("Unknown option %s.\n", arg.c_str());
-			bool disable_empty_warning = count_mode || assert_none || assert_any || (assert_count != -1) || (assert_max != -1) || (assert_min != -1);
+			bool disable_empty_warning = count_mode || assert_none || assert_any || (assert_modcount != -1) ||
+											(assert_count != -1) || (assert_max != -1) || (assert_min != -1);
 			select_stmt(design, arg, disable_empty_warning);
 			sel_str += " " + arg;
 		}
@@ -1385,17 +1395,20 @@ struct SelectPass : public Pass {
 		if (none_mode && args.size() != 2)
 			log_cmd_error("Option -none can not be combined with any other options.\n");
 
-		if (add_mode + del_mode + assert_none + assert_any + (assert_count >= 0) + (assert_max >= 0) + (assert_min >= 0) > 1)
-			log_cmd_error("Options -add, -del, -assert-none, -assert-any, assert-count, -assert-max or -assert-min can not be combined.\n");
+		int common_flagset_tally = add_mode + del_mode + assert_none + assert_any + (assert_modcount >= 0) + (assert_count >= 0) + (assert_max >= 0) + (assert_min >= 0);
+		const char *common_flagset = "-add, -del, -assert-none, -assert-any, -assert-mod-count, -assert-count, -assert-max, or -assert-min";
 
-		if ((list_mode || !write_file.empty() || count_mode) && (add_mode || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
-			log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none, -assert-any, assert-count, -assert-max, or -assert-min.\n");
+		if (common_flagset_tally > 1)
+			log_cmd_error("Options %s can not be combined.\n", common_flagset);                
 
-		if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || !unset_name.empty() || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
-			log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -unset, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
+		if ((list_mode || !write_file.empty() || count_mode) && common_flagset_tally)
+			log_cmd_error("Options -list, -write and -count can not be combined with %s.\n", common_flagset);
 
-		if (!unset_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || !set_name.empty() || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
-			log_cmd_error("Option -unset can not be combined with -list, -write, -count, -add, -del, -set, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
+		if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || !unset_name.empty() || common_flagset_tally))
+			log_cmd_error("Option -set can not be combined with -list, -write, -count, -unset, %s.\n", common_flagset);
+
+		if (!unset_name.empty() && (list_mode || !write_file.empty() || count_mode || !set_name.empty() || common_flagset_tally))
+			log_cmd_error("Option -unset can not be combined with -list, -write, -count, -set, %s.\n", common_flagset);
 
 		if (work_stack.size() == 0 && got_module) {
 			RTLIL::Selection sel;
@@ -1514,15 +1527,16 @@ struct SelectPass : public Pass {
 			return;
 		}
 
-		if (assert_count >= 0 || assert_max >= 0 || assert_min >= 0)
+		if (assert_modcount >= 0 || assert_count >= 0 || assert_max >= 0 || assert_min >= 0)
 		{
-			int total_count = 0;
+			int module_count = 0, total_count = 0;
 			if (work_stack.size() == 0)
 				log_cmd_error("No selection to check.\n");
 			RTLIL::Selection *sel = &work_stack.back();
 			sel->optimize(design);
 			for (auto mod : design->modules())
 				if (sel->selected_module(mod->name)) {
+					module_count++;
 					for (auto wire : mod->wires())
 						if (sel->selected_member(mod->name, wire->name))
 							total_count++;
@@ -1536,6 +1550,11 @@ struct SelectPass : public Pass {
 						if (sel->selected_member(mod->name, it.first))
 							total_count++;
 				}
+			if (assert_modcount >= 0 && assert_modcount != module_count)
+			{
+				log_error("Assertion failed: selection contains %d modules instead of the asserted %d:%s\n",
+						module_count, assert_modcount, sel_str.c_str());
+			}
 			if (assert_count >= 0 && assert_count != total_count)
 			{
 				std::string desc = describe_selection_for_assert(design, sel);
diff --git a/yosys/passes/cmds/show.cc b/yosys/passes/cmds/show.cc
index 0dc5c452c09..82b5c6bcf35 100644
--- a/yosys/passes/cmds/show.cc
+++ b/yosys/passes/cmds/show.cc
@@ -65,6 +65,7 @@ struct ShowWorker
 	bool enumerateIds;
 	bool abbreviateIds;
 	bool notitle;
+	bool href;
 	int page_counter;
 
 	const std::vector<std::pair<std::string, RTLIL::Selection>> &color_selections;
@@ -432,9 +433,13 @@ struct ShowWorker
 			if (wire->port_input || wire->port_output)
 				shape = "octagon";
 			if (wire->name.isPublic()) {
-				fprintf(f, "n%d [ shape=%s, label=\"%s\", %s ];\n",
+				std::string src_href;
+				if (href && wire->attributes.count(ID::src) > 0)
+					src_href = stringf(", href=\"%s\" ", escape(wire->attributes.at(ID::src).decode_string()));
+				fprintf(f, "n%d [ shape=%s, label=\"%s\", %s%s];\n",
 						id2num(wire->name), shape, findLabel(wire->name.str()),
-						nextColor(RTLIL::SigSpec(wire), "color=\"black\", fontcolor=\"black\"").c_str());
+						nextColor(RTLIL::SigSpec(wire), "color=\"black\", fontcolor=\"black\"").c_str(),
+						src_href.c_str());
 				if (wire->port_input)
 					all_sources.insert(stringf("n%d", id2num(wire->name)));
 				else if (wire->port_output)
@@ -496,14 +501,18 @@ struct ShowWorker
 						conn.second, ct.cell_output(cell->type, conn.first));
 			}
 
+			std::string src_href;
+			if (href && cell->attributes.count(ID::src) > 0) {
+				src_href = stringf("%shref=\"%s\" ", (findColor(cell->name).empty() ? "" :" , "), escape(cell->attributes.at(ID::src).decode_string()));
+			}
 #ifdef CLUSTER_CELLS_AND_PORTBOXES
 			if (!code.empty())
-				fprintf(f, "subgraph cluster_c%d {\nc%d [ shape=record, label=\"%s\"%s ];\n%s}\n",
-						id2num(cell->name), id2num(cell->name), label_string.c_str(), color.c_str(), code.c_str());
+				fprintf(f, "subgraph cluster_c%d {\nc%d [ shape=record, label=\"%s\"%s%s ];\n%s}\n",
+						id2num(cell->name), id2num(cell->name), label_string.c_str(), color.c_str(), src_href.c_str(), code.c_str());
 			else
 #endif
-				fprintf(f, "c%d [ shape=record, label=\"%s\", %s ];\n%s",
-						id2num(cell->name), label_string.c_str(), findColor(cell->name).c_str(), code.c_str());
+				fprintf(f, "c%d [ shape=record, label=\"%s\", %s%s ];\n%s",
+						id2num(cell->name), label_string.c_str(), findColor(cell->name).c_str(), src_href.c_str(), code.c_str());
 		}
 
 		for (auto &it : module->processes)
@@ -539,7 +548,7 @@ struct ShowWorker
 			std::string proc_src = RTLIL::unescape_id(proc->name);
 			if (proc->attributes.count(ID::src) > 0)
 				proc_src = proc->attributes.at(ID::src).decode_string();
-			fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name.str()), proc_src.c_str());
+			fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\", %s];\n", pidx, findLabel(proc->name.str()), proc_src.c_str(), findColor(proc->name).c_str());
 		}
 
 		for (auto &conn : module->connections())
@@ -575,7 +584,7 @@ struct ShowWorker
 				} else {
 					net_conn_map[right_node].in.insert({stringf("x%d", single_idx_count), GetSize(conn.first)});
 					net_conn_map[left_node].out.insert({stringf("x%d", single_idx_count), GetSize(conn.first)});
-					fprintf(f, "x%d [shape=box, style=rounded, label=\"BUF\", %s];\n", single_idx_count++, findColor(conn).c_str());
+					fprintf(f, "x%d [shape=point, %s];\n", single_idx_count++, findColor(conn).c_str());
 				}
 			}
 		}
@@ -608,12 +617,12 @@ struct ShowWorker
 	}
 
 	ShowWorker(FILE *f, RTLIL::Design *design, std::vector<RTLIL::Design*> &libs, uint32_t colorSeed, bool genWidthLabels,
-			bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle,
+			bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, bool href,
 			const std::vector<std::pair<std::string, RTLIL::Selection>> &color_selections,
 			const std::vector<std::pair<std::string, RTLIL::Selection>> &label_selections, RTLIL::IdString colorattr) :
 			f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels),
 			genSignedLabels(genSignedLabels), stretchIO(stretchIO), enumerateIds(enumerateIds), abbreviateIds(abbreviateIds),
-			notitle(notitle), color_selections(color_selections), label_selections(label_selections), colorattr(colorattr)
+			notitle(notitle), href(href), color_selections(color_selections), label_selections(label_selections), colorattr(colorattr)
 	{
 		ct.setup_internals();
 		ct.setup_internals_mem();
@@ -726,6 +735,10 @@ struct ShowPass : public Pass {
 		log("        don't run viewer in the background, IE wait for the viewer tool to\n");
 		log("        exit before returning\n");
 		log("\n");
+		log("    -href\n");
+		log("        adds href attribute to all items representing cells and wires, using\n");
+		log("        src attribute of origin\n");
+		log("\n");
 		log("When no <format> is specified, 'dot' is used. When no <format> and <viewer> is\n");
 		log("specified, 'xdot' is used to display the schematic (POSIX systems only).\n");
 		log("\n");
@@ -763,6 +776,7 @@ struct ShowPass : public Pass {
 		bool flag_enum = false;
 		bool flag_abbreviate = true;
 		bool flag_notitle = false;
+		bool flag_href = false;
 		bool custom_prefix = false;
 		std::string background = "&";
 		RTLIL::IdString colorattr;
@@ -850,6 +864,10 @@ struct ShowPass : public Pass {
 				background= "";
 				continue;
 			}
+			if (arg == "-href") {
+				flag_href = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -894,7 +912,7 @@ struct ShowPass : public Pass {
 				delete lib;
 			log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str());
 		}
-		ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, color_selections, label_selections, colorattr);
+		ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, flag_href, color_selections, label_selections, colorattr);
 		fclose(f);
 
 		for (auto lib : libs)
diff --git a/yosys/passes/cmds/stat.cc b/yosys/passes/cmds/stat.cc
index f0021cf8769..c2bb72f3bb3 100644
--- a/yosys/passes/cmds/stat.cc
+++ b/yosys/passes/cmds/stat.cc
@@ -28,10 +28,16 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+struct cell_area_t {
+	double area;
+	bool is_sequential;
+};
+
 struct statdata_t
 {
 	#define STAT_INT_MEMBERS X(num_wires) X(num_wire_bits) X(num_pub_wires) X(num_pub_wire_bits) \
-			X(num_memories) X(num_memory_bits) X(num_cells) X(num_processes)
+			X(num_ports) X(num_port_bits) X(num_memories) X(num_memory_bits) X(num_cells) \
+			X(num_processes)
 
 	#define STAT_NUMERIC_MEMBERS STAT_INT_MEMBERS X(area)
 
@@ -39,6 +45,7 @@ struct statdata_t
 	STAT_INT_MEMBERS
 	#undef X
 	double area;
+	double sequential_area;
 	string tech;
 
 	std::map<RTLIL::IdString, int> techinfo;
@@ -74,7 +81,7 @@ struct statdata_t
 	#undef X
 	}
 
-	statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, double> &cell_area, string techname)
+	statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, cell_area_t> &cell_area, string techname)
 	{
 		tech = techname;
 
@@ -84,6 +91,11 @@ struct statdata_t
 
 		for (auto wire : mod->selected_wires())
 		{
+			if (wire->port_input || wire->port_output) {
+				num_ports++;
+				num_port_bits += wire->width;
+			}
+
 			if (wire->name.isPublic()) {
 				num_pub_wires++;
 				num_pub_wire_bits += wire->width;
@@ -132,10 +144,16 @@ struct statdata_t
 			}
 
 			if (!cell_area.empty()) {
-				if (cell_area.count(cell_type))
-					area += cell_area.at(cell_type);
-				else
+				if (cell_area.count(cell_type)) {
+					cell_area_t cell_data = cell_area.at(cell_type);
+					if (cell_data.is_sequential) {
+						sequential_area += cell_data.area;
+					}
+					area += cell_data.area;
+				}
+				else {
 					unknown_cell_area.insert(cell_type);
+				}
 			}
 
 			num_cells++;
@@ -227,6 +245,8 @@ struct statdata_t
 		log("   Number of wire bits:         %6u\n", num_wire_bits);
 		log("   Number of public wires:      %6u\n", num_pub_wires);
 		log("   Number of public wire bits:  %6u\n", num_pub_wire_bits);
+		log("   Number of ports:             %6u\n", num_ports);
+		log("   Number of port bits:         %6u\n", num_port_bits);
 		log("   Number of memories:          %6u\n", num_memories);
 		log("   Number of memory bits:       %6u\n", num_memory_bits);
 		log("   Number of processes:         %6u\n", num_processes);
@@ -244,6 +264,7 @@ struct statdata_t
 		if (area != 0) {
 			log("\n");
 			log("   Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area);
+			log("     of which used for sequential elements: %f (%.2f%%)\n", sequential_area, 100.0*sequential_area/area);
 		}
 
 		if (tech == "xilinx")
@@ -271,6 +292,8 @@ struct statdata_t
 		log("         \"num_wire_bits\":     %u,\n", num_wire_bits);
 		log("         \"num_pub_wires\":     %u,\n", num_pub_wires);
 		log("         \"num_pub_wire_bits\": %u,\n", num_pub_wire_bits);
+		log("         \"num_ports\":         %u,\n", num_ports);
+		log("         \"num_port_bits\":     %u,\n", num_port_bits);
 		log("         \"num_memories\":      %u,\n", num_memories);
 		log("         \"num_memory_bits\":   %u,\n", num_memory_bits);
 		log("         \"num_processes\":     %u,\n", num_processes);
@@ -325,7 +348,7 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
 	return mod_data;
 }
 
-void read_liberty_cellarea(dict<IdString, double> &cell_area, string liberty_file)
+void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string liberty_file)
 {
 	std::ifstream f;
 	f.open(liberty_file.c_str());
@@ -341,8 +364,9 @@ void read_liberty_cellarea(dict<IdString, double> &cell_area, string liberty_fil
 			continue;
 
 		LibertyAst *ar = cell->find("area");
+		bool is_flip_flop = cell->find("ff") != nullptr;
 		if (ar != nullptr && !ar->value.empty())
-			cell_area["\\" + cell->args[0]] = atof(ar->value.c_str());
+			cell_area["\\" + cell->args[0]] = {/*area=*/atof(ar->value.c_str()), is_flip_flop};
 	}
 }
 
@@ -366,7 +390,7 @@ struct StatPass : public Pass {
 		log("        use cell area information from the provided liberty file\n");
 		log("\n");
 		log("    -tech <technology>\n");
-		log("        print area estemate for the specified technology. Currently supported\n");
+		log("        print area estimate for the specified technology. Currently supported\n");
 		log("        values for <technology>: xilinx, cmos\n");
 		log("\n");
 		log("    -width\n");
@@ -383,7 +407,7 @@ struct StatPass : public Pass {
 		bool width_mode = false, json_mode = false;
 		RTLIL::Module *top_mod = nullptr;
 		std::map<RTLIL::IdString, statdata_t> mod_stat;
-		dict<IdString, double> cell_area;
+		dict<IdString, cell_area_t> cell_area;
 		string techname;
 
 		size_t argidx;
@@ -480,6 +504,8 @@ struct StatPass : public Pass {
 			design->scratchpad_set_int("stat.num_wire_bits", data.num_wire_bits);
 			design->scratchpad_set_int("stat.num_pub_wires", data.num_pub_wires);
 			design->scratchpad_set_int("stat.num_pub_wire_bits", data.num_pub_wire_bits);
+			design->scratchpad_set_int("stat.num_ports", data.num_ports);
+			design->scratchpad_set_int("stat.num_port_bits", data.num_port_bits);
 			design->scratchpad_set_int("stat.num_memories", data.num_memories);
 			design->scratchpad_set_int("stat.num_memory_bits", data.num_memory_bits);
 			design->scratchpad_set_int("stat.num_processes", data.num_processes);
diff --git a/yosys/passes/cmds/xprop.cc b/yosys/passes/cmds/xprop.cc
index 5e78ff9fce4..310d6d773d5 100644
--- a/yosys/passes/cmds/xprop.cc
+++ b/yosys/passes/cmds/xprop.cc
@@ -493,8 +493,9 @@ struct XpropWorker
 				auto sig_b = cell->getPort(ID::B);
 
 				auto name = cell->name;
+				auto type = cell->type;
 				module->remove(cell);
-				if (cell->type == ID($eqx))
+				if (type == ID($eqx))
 					module->addEq(name, sig_a, sig_b, sig_y);
 				else
 					module->addNe(name, sig_a, sig_b, sig_y);
@@ -534,7 +535,7 @@ struct XpropWorker
 			auto enc_b = encoded(sig_b);
 			auto enc_y = encoded(sig_y, true);
 
-			if (cell->type.in(ID($or), ID($_OR_)))
+			if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
 				enc_a.invert(), enc_b.invert(), enc_y.invert();
 			if (cell->type.in(ID($_NAND_), ID($_NOR_)))
 				enc_y.invert();
@@ -1027,12 +1028,25 @@ struct XpropWorker
 		for (auto wire : module->selected_wires()) {
 			if (wire->port_input || wire->port_output || !wire->name.isPublic())
 				continue;
-			auto name_d = module->uniquify(stringf("%s_d", wire->name.c_str()));
-			auto name_x = module->uniquify(stringf("%s_x", wire->name.c_str()));
+			int index_d = 0;
+			int index_x = 0;
+			auto name_d = module->uniquify(stringf("%s_d", wire->name.c_str()), index_d);
+			auto name_x = module->uniquify(stringf("%s_x", wire->name.c_str()), index_x);
+
+			auto hdlname = wire->get_hdlname_attribute();
 
 			auto wire_d = module->addWire(name_d, GetSize(wire));
 			auto wire_x = module->addWire(name_x, GetSize(wire));
 
+			if (!hdlname.empty()) {
+				auto hdlname_d = hdlname;
+				auto hdlname_x = hdlname;
+				hdlname_d.back() += index_d ? stringf("_d_%d", index_d) : "_d";
+				hdlname_x.back() += index_x ? stringf("_x_%d", index_x) : "_x";
+				wire_d->set_hdlname_attribute(hdlname_d);
+				wire_x->set_hdlname_attribute(hdlname_x);
+			}
+
 			auto enc = encoded(wire);
 			module->connect(wire_d, enc.is_1);
 			module->connect(wire_x, enc.is_x);
diff --git a/yosys/passes/equiv/equiv_simple.cc b/yosys/passes/equiv/equiv_simple.cc
index 7621341a7c3..59974a1e642 100644
--- a/yosys/passes/equiv/equiv_simple.cc
+++ b/yosys/passes/equiv/equiv_simple.cc
@@ -60,7 +60,7 @@ struct EquivSimpleWorker
 		for (auto &conn : cell->connections())
 			if (yosys_celltypes.cell_input(cell->type, conn.first))
 				for (auto bit : sigmap(conn.second)) {
-					if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) {
+					if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
 						if (!conn.first.in(ID::CLK, ID::C))
 							next_seed.insert(bit);
 					} else
@@ -133,11 +133,9 @@ struct EquivSimpleWorker
 
 			for (auto bit_a : seed_a)
 				find_input_cone(next_seed_a, full_cells_cone_a, full_bits_cone_a, no_stop_cells, no_stop_bits, nullptr, bit_a);
-			next_seed_a.clear();
 
 			for (auto bit_b : seed_b)
 				find_input_cone(next_seed_b, full_cells_cone_b, full_bits_cone_b, no_stop_cells, no_stop_bits, nullptr, bit_b);
-			next_seed_b.clear();
 
 			pool<Cell*> short_cells_cone_a, short_cells_cone_b;
 			pool<SigBit> short_bits_cone_a, short_bits_cone_b;
@@ -145,10 +143,12 @@ struct EquivSimpleWorker
 
 			if (short_cones)
 			{
+				next_seed_a.clear();
 				for (auto bit_a : seed_a)
 					find_input_cone(next_seed_a, short_cells_cone_a, short_bits_cone_a, full_cells_cone_b, full_bits_cone_b, &input_bits, bit_a);
 				next_seed_a.swap(seed_a);
 
+				next_seed_b.clear();
 				for (auto bit_b : seed_b)
 					find_input_cone(next_seed_b, short_cells_cone_b, short_bits_cone_b, full_cells_cone_a, full_bits_cone_a, &input_bits, bit_b);
 				next_seed_b.swap(seed_b);
@@ -339,6 +339,8 @@ struct EquivSimplePass : public Pass {
 		CellTypes ct;
 		ct.setup_internals();
 		ct.setup_stdcells();
+		ct.setup_internals_ff();
+		ct.setup_stdcells_mem();
 
 		for (auto module : design->selected_modules())
 		{
@@ -364,7 +366,7 @@ struct EquivSimplePass : public Pass {
 					unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module));
 
 			for (auto cell : module->cells()) {
-				if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_)))
+				if (!ct.cell_known(cell->type))
 					continue;
 				for (auto &conn : cell->connections())
 					if (yosys_celltypes.cell_output(cell->type, conn.first))
diff --git a/yosys/passes/hierarchy/hierarchy.cc b/yosys/passes/hierarchy/hierarchy.cc
index bf013750365..3ef04616fcb 100644
--- a/yosys/passes/hierarchy/hierarchy.cc
+++ b/yosys/passes/hierarchy/hierarchy.cc
@@ -47,7 +47,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
 	{
 		if (design->module(cell->type) != nullptr)
 			continue;
-		if (cell->type.begins_with("$__"))
+		if (cell->type.begins_with("$") && !cell->type.begins_with("$__"))
 			continue;
 		for (auto &pattern : celltypes)
 			if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str()))
@@ -655,12 +655,23 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
 	log("Removed %d unused modules.\n", del_counter);
 }
 
+bool set_keep_print(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
+{
+	if (cache.count(mod) == 0)
+		for (auto c : mod->cells()) {
+			RTLIL::Module *m = mod->design->module(c->type);
+			if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print))
+				return cache[mod] = true;
+		}
+	return cache[mod];
+}
+
 bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
 {
 	if (cache.count(mod) == 0)
 		for (auto c : mod->cells()) {
 			RTLIL::Module *m = mod->design->module(c->type);
-			if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
+			if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
 				return cache[mod] = true;
 		}
 	return cache[mod];
@@ -762,6 +773,11 @@ struct HierarchyPass : public Pass {
 		log("    -nodefaults\n");
 		log("        do not resolve input port default values\n");
 		log("\n");
+		log("    -nokeep_prints\n");
+		log("        per default this pass sets the \"keep\" attribute on all modules\n");
+		log("        that directly or indirectly display text on the terminal.\n");
+		log("        This option disables this behavior.\n");
+		log("\n");
 		log("    -nokeep_asserts\n");
 		log("        per default this pass sets the \"keep\" attribute on all modules\n");
 		log("        that directly or indirectly contain one or more formal properties.\n");
@@ -818,6 +834,7 @@ struct HierarchyPass : public Pass {
 		bool keep_positionals = false;
 		bool keep_portwidths = false;
 		bool nodefaults = false;
+		bool nokeep_prints = false;
 		bool nokeep_asserts = false;
 		std::vector<std::string> generate_cells;
 		std::vector<generate_port_decl_t> generate_ports;
@@ -893,6 +910,10 @@ struct HierarchyPass : public Pass {
 				nodefaults = true;
 				continue;
 			}
+			if (args[argidx] == "-nokeep_prints") {
+				nokeep_prints = true;
+				continue;
+			}
 			if (args[argidx] == "-nokeep_asserts") {
 				nokeep_asserts = true;
 				continue;
@@ -985,6 +1006,18 @@ struct HierarchyPass : public Pass {
 				if (mod->get_bool_attribute(ID::top))
 					top_mod = mod;
 
+		if (top_mod == nullptr)
+		{
+			std::vector<IdString> abstract_ids;
+			for (auto module : design->modules())
+				if (module->name.begins_with("$abstract"))
+					abstract_ids.push_back(module->name);
+			for (auto abstract_id : abstract_ids)
+				design->module(abstract_id)->derive(design, {});
+			for (auto abstract_id : abstract_ids)
+				design->remove(design->module(abstract_id));
+		}
+
 		if (top_mod == nullptr && auto_top_mode) {
 			log_header(design, "Finding top of design hierarchy..\n");
 			dict<Module*, int> db;
@@ -1091,6 +1124,15 @@ struct HierarchyPass : public Pass {
 			}
 		}
 
+		if (!nokeep_prints) {
+			std::map<RTLIL::Module*, bool> cache;
+			for (auto mod : design->modules())
+				if (set_keep_print(cache, mod)) {
+					log("Module %s directly or indirectly displays text -> setting \"keep\" attribute.\n", log_id(mod));
+					mod->set_bool_attribute(ID::keep);
+				}
+		}
+
 		if (!nokeep_asserts) {
 			std::map<RTLIL::Module*, bool> cache;
 			for (auto mod : design->modules())
diff --git a/yosys/passes/memory/memlib.md b/yosys/passes/memory/memlib.md
index fdc2d4bed27..855aa1345fb 100644
--- a/yosys/passes/memory/memlib.md
+++ b/yosys/passes/memory/memlib.md
@@ -267,7 +267,7 @@ The address is always `abits` wide.  If a non-narrowest width is used, the appro
 bits will be tied to 0.
 
 
-### Port `width` prooperty
+### Port `width` property
 
 If the RAM has `per_port` widths, the available width selection can be further described
 on per-port basis, by using one of the following properties:
diff --git a/yosys/passes/memory/memory_collect.cc b/yosys/passes/memory/memory_collect.cc
index bf3bb34f8b0..157042c9c2f 100644
--- a/yosys/passes/memory/memory_collect.cc
+++ b/yosys/passes/memory/memory_collect.cc
@@ -39,6 +39,9 @@ struct MemoryCollectPass : public Pass {
 		log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
 		extra_args(args, 1, design);
 		for (auto module : design->selected_modules()) {
+			if (module->has_processes_warn())
+				continue;
+
 			for (auto &mem : Mem::get_selected_memories(module)) {
 				if (!mem.packed) {
 					mem.packed = true;
diff --git a/yosys/passes/memory/memory_libmap.cc b/yosys/passes/memory/memory_libmap.cc
index 6e5a806fd0e..77a4eb81bbe 100644
--- a/yosys/passes/memory/memory_libmap.cc
+++ b/yosys/passes/memory/memory_libmap.cc
@@ -481,18 +481,58 @@ void MemMapping::dump_config(MemConfig &cfg) {
 	}
 }
 
+std::pair<bool, Const> search_for_attribute(Mem mem, IdString attr) {
+	// priority of attributes:
+	// 1. attributes on memory itself
+	// 2. attributes on a read or write port
+	// 3. attributes on data signal of a read or write port
+	// 4. attributes on address signal of a read or write port
+
+	if (mem.has_attribute(attr))
+		return std::make_pair(true, mem.attributes.at(attr));
+
+	for (auto &port: mem.rd_ports)
+		if (port.has_attribute(attr))
+			return std::make_pair(true, port.attributes.at(attr));
+	for (auto &port: mem.wr_ports)
+		if (port.has_attribute(attr))
+			return std::make_pair(true, port.attributes.at(attr));
+
+	for (auto &port: mem.rd_ports)
+		for (SigBit bit: port.data)
+			if (bit.is_wire() && bit.wire->has_attribute(attr))
+				return std::make_pair(true, bit.wire->attributes.at(attr));
+	for (auto &port: mem.wr_ports)
+		for (SigBit bit: port.data)
+			if (bit.is_wire() && bit.wire->has_attribute(attr))
+				return std::make_pair(true, bit.wire->attributes.at(attr));
+
+	for (auto &port: mem.rd_ports)
+		for (SigBit bit: port.addr)
+			if (bit.is_wire() && bit.wire->has_attribute(attr))
+				return std::make_pair(true, bit.wire->attributes.at(attr));
+	for (auto &port: mem.wr_ports)
+		for (SigBit bit: port.addr)
+			if (bit.is_wire() && bit.wire->has_attribute(attr))
+				return std::make_pair(true, bit.wire->attributes.at(attr));
+	
+	return std::make_pair(false, Const());
+}
+
 // Go through memory attributes to determine user-requested mapping style.
 void MemMapping::determine_style() {
 	kind = RamKind::Auto;
 	style = "";
-	if (mem.get_bool_attribute(ID::lram)) {
+	auto find_attr = search_for_attribute(mem, ID::lram);
+	if (find_attr.first && find_attr.second.as_bool()) {
 		kind = RamKind::Huge;
 		log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", log_id(mem.module->name), log_id(mem.memid));
 		return;
 	}
 	for (auto attr: {ID::ram_block, ID::rom_block, ID::ram_style, ID::rom_style, ID::ramstyle, ID::romstyle, ID::syn_ramstyle, ID::syn_romstyle}) {
-		if (mem.has_attribute(attr)) {
-			Const val = mem.attributes.at(attr);
+		find_attr = search_for_attribute(mem, attr);
+		if (find_attr.first) {
+			Const val = find_attr.second;
 			if (val == 1) {
 				kind = RamKind::NotLogic;
 				log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", log_id(attr), log_id(mem.module->name), log_id(mem.memid));
@@ -526,8 +566,11 @@ void MemMapping::determine_style() {
 			return;
 		}
 	}
-	if (mem.get_bool_attribute(ID::logic_block))
-		kind = RamKind::Logic;
+	for (auto attr: {ID::logic_block, ID::no_ram}){
+		find_attr = search_for_attribute(mem, attr);
+		if (find_attr.first && find_attr.second.as_bool())
+			kind = RamKind::Logic;
+	}
 }
 
 // Determine whether the memory can be mapped entirely to soft logic.
@@ -647,7 +690,7 @@ bool apply_clock(MemConfig &cfg, const PortVariant &def, SigBit clk, bool clk_po
 
 // Perform write port assignment, validating clock options as we go.
 void MemMapping::assign_wr_ports() {
-	log_reject(stringf("Assigning write ports... (candidate configs: %lu)", cfgs.size()));
+	log_reject(stringf("Assigning write ports... (candidate configs: %zu)", (size_t) cfgs.size()));
 	for (auto &port: mem.wr_ports) {
 		if (!port.clk_enable) {
 			// Async write ports not supported.
@@ -667,7 +710,7 @@ void MemMapping::assign_wr_ports() {
 				if (used >= GetSize(pg.names)) {
 					log_reject(*cfg.def, pg, "not enough unassigned ports remaining");
 					continue;
-					}
+				}
 				for (int pvi = 0; pvi < GetSize(pg.variants); pvi++) {
 					auto &def = pg.variants[pvi];
 					// Make sure the target is a write port.
@@ -696,7 +739,7 @@ void MemMapping::assign_wr_ports() {
 
 // Perform read port assignment, validating clock and rden options as we go.
 void MemMapping::assign_rd_ports() {
-	log_reject(stringf("Assigning read ports... (candidate configs: %lu)", cfgs.size()));
+	log_reject(stringf("Assigning read ports... (candidate configs: %zu)", (size_t) cfgs.size()));
 	for (int pidx = 0; pidx < GetSize(mem.rd_ports); pidx++) {
 		auto &port = mem.rd_ports[pidx];
 		MemConfigs new_cfgs;
@@ -857,7 +900,7 @@ void MemMapping::assign_rd_ports() {
 
 // Validate transparency restrictions, determine where to add soft transparency logic.
 void MemMapping::handle_trans() {
-	log_reject(stringf("Handling transparency... (candidate configs: %lu)", cfgs.size()));
+	log_reject(stringf("Handling transparency... (candidate configs: %zu)", (size_t) cfgs.size()));
 	if (mem.emulate_read_first_ok()) {
 		MemConfigs new_cfgs;
 		for (auto &cfg: cfgs) {
@@ -2114,7 +2157,7 @@ struct MemoryLibMapPass : public Pass {
 		log("    memory_libmap -lib <library_file> [-D <condition>] [selection]\n");
 		log("\n");
 		log("This pass takes a description of available RAM cell types and maps\n");
-		log("all selected memories to one of them, or leaves them  to be mapped to FFs.\n");
+		log("all selected memories to one of them, or leaves them to be mapped to FFs.\n");
 		log("\n");
 		log("  -lib <library_file>\n");
 		log("    Selects a library file containing RAM cell definitions. This option\n");
@@ -2186,6 +2229,9 @@ struct MemoryLibMapPass : public Pass {
 		Library lib = parse_library(lib_files, defines);
 
 		for (auto module : design->selected_modules()) {
+			if (module->has_processes_warn())
+				continue;
+
 			MapWorker worker(module);
 			auto mems = Mem::get_selected_memories(module);
 			for (auto &mem : mems)
diff --git a/yosys/passes/memory/memory_map.cc b/yosys/passes/memory/memory_map.cc
index e2f74c2e1a5..d1dd0fd882d 100644
--- a/yosys/passes/memory/memory_map.cc
+++ b/yosys/passes/memory/memory_map.cc
@@ -415,7 +415,7 @@ struct MemoryMapPass : public Pass {
 		log("        to any of the values.\n");
 		log("\n");
 		log("    -iattr\n");
-		log("        for -attr, ignore case of <value>.\n");
+		log("        for -attr, suppress case sensitivity in matching of <value>.\n");
 		log("\n");
 		log("    -rom-only\n");
 		log("        only perform conversion for ROMs (memories with no write ports).\n");
@@ -493,6 +493,9 @@ struct MemoryMapPass : public Pass {
 		extra_args(args, argidx, design);
 
 		for (auto mod : design->selected_modules()) {
+			if (mod->has_processes_warn())
+				continue;
+
 			MemoryMapWorker worker(design, mod);
 			worker.attr_icase = attr_icase;
 			worker.attributes = attributes;
diff --git a/yosys/passes/memory/memory_memx.cc b/yosys/passes/memory/memory_memx.cc
index 7edc26caaa2..22aebb43f1b 100644
--- a/yosys/passes/memory/memory_memx.cc
+++ b/yosys/passes/memory/memory_memx.cc
@@ -50,7 +50,7 @@ struct MemoryMemxPass : public Pass {
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
-		log_header(design, "Executing MEMORY_MEMX pass (converting $mem cells to logic and flip-flops).\n");
+		log_header(design, "Executing MEMORY_MEMX pass (emit soft logic for out-of-bounds handling).\n");
 		extra_args(args, 1, design);
 
 		for (auto module : design->selected_modules())
diff --git a/yosys/passes/memory/memory_narrow.cc b/yosys/passes/memory/memory_narrow.cc
index cf5e4346540..46c538bab1e 100644
--- a/yosys/passes/memory/memory_narrow.cc
+++ b/yosys/passes/memory/memory_narrow.cc
@@ -46,6 +46,9 @@ struct MemoryNarrowPass : public Pass {
 		extra_args(args, argidx, design);
 
 		for (auto module : design->selected_modules()) {
+			if (module->has_processes_warn())
+				continue;
+
 			for (auto &mem : Mem::get_selected_memories(module))
 			{
 				bool wide = false;
diff --git a/yosys/passes/memory/memory_share.cc b/yosys/passes/memory/memory_share.cc
index 8b2354ef861..e06989f4ab8 100644
--- a/yosys/passes/memory/memory_share.cc
+++ b/yosys/passes/memory/memory_share.cc
@@ -558,8 +558,12 @@ struct MemorySharePass : public Pass {
 		extra_args(args, argidx, design);
 		MemoryShareWorker msw(design, flag_widen, flag_sat);
 
-		for (auto module : design->selected_modules())
+		for (auto module : design->selected_modules()) {
+			if (module->has_processes_warn())
+				continue;
+
 			msw(module);
+		}
 	}
 } MemorySharePass;
 
diff --git a/yosys/passes/opt/opt_clean.cc b/yosys/passes/opt/opt_clean.cc
index cb2490dc72e..ba39b9c8086 100644
--- a/yosys/passes/opt/opt_clean.cc
+++ b/yosys/passes/opt/opt_clean.cc
@@ -35,10 +35,12 @@ struct keep_cache_t
 {
 	Design *design;
 	dict<Module*, bool> cache;
+	bool purge_mode = false;
 
-	void reset(Design *design = nullptr)
+	void reset(Design *design = nullptr, bool purge_mode = false)
 	{
 		this->design = design;
+		this->purge_mode = purge_mode;
 		cache.clear();
 	}
 
@@ -76,12 +78,21 @@ struct keep_cache_t
 		if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
 			return true;
 
+		if (cell->type.in(ID($overwrite_tag)))
+			return true;
+
 		if (!ignore_specify && cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
 			return true;
 
+		if (cell->type == ID($print) || cell->type == ID($check))
+			return true;
+
 		if (cell->has_keep_attr())
 			return true;
 
+		if (!purge_mode && cell->type == ID($scopeinfo))
+			return true;
+
 		if (cell->module && cell->module->design)
 			return query(cell->module->design->module(cell->type));
 
@@ -230,10 +241,13 @@ int count_nontrivial_wire_attrs(RTLIL::Wire *w)
 {
 	int count = w->attributes.size();
 	count -= w->attributes.count(ID::src);
+	count -= w->attributes.count(ID::hdlname);
+	count -= w->attributes.count(ID(scopename));
 	count -= w->attributes.count(ID::unused_bits);
 	return count;
 }
 
+// Should we pick `s2` over `s1` to represent a signal?
 bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPool &conns, pool<RTLIL::Wire*> &direct_wires)
 {
 	RTLIL::Wire *w1 = s1.wire;
@@ -286,9 +300,10 @@ bool check_public_name(RTLIL::IdString id)
 
 bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose)
 {
+	// `register_signals` and `connected_signals` will help us decide later on
+	// on picking representatives out of groups of connected signals
 	SigPool register_signals;
 	SigPool connected_signals;
-
 	if (!purge_mode)
 		for (auto &it : module->cells_) {
 			RTLIL::Cell *cell = it.second;
@@ -303,20 +318,27 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 		}
 
 	SigMap assign_map(module);
-	pool<RTLIL::SigSpec> direct_sigs;
+
+	// construct a pool of wires which are directly driven by a known celltype,
+	// this will influence our choice of representatives
 	pool<RTLIL::Wire*> direct_wires;
-	for (auto &it : module->cells_) {
-		RTLIL::Cell *cell = it.second;
-		if (ct_all.cell_known(cell->type))
-			for (auto &it2 : cell->connections())
-				if (ct_all.cell_output(cell->type, it2.first))
-					direct_sigs.insert(assign_map(it2.second));
-	}
-	for (auto &it : module->wires_) {
-		if (direct_sigs.count(assign_map(it.second)) || it.second->port_input)
-			direct_wires.insert(it.second);
+	{
+		pool<RTLIL::SigSpec> direct_sigs;
+		for (auto &it : module->cells_) {
+			RTLIL::Cell *cell = it.second;
+			if (ct_all.cell_known(cell->type))
+				for (auto &it2 : cell->connections())
+					if (ct_all.cell_output(cell->type, it2.first))
+						direct_sigs.insert(assign_map(it2.second));
+		}
+		for (auto &it : module->wires_) {
+			if (direct_sigs.count(assign_map(it.second)) || it.second->port_input)
+				direct_wires.insert(it.second);
+		}
 	}
 
+	// weight all options for representatives with `compare_signals`,
+	// the one that wins will be what `assign_map` maps to
 	for (auto &it : module->wires_) {
 		RTLIL::Wire *wire = it.second;
 		for (int i = 0; i < wire->width; i++) {
@@ -326,21 +348,30 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 		}
 	}
 
+	// we are removing all connections
 	module->connections_.clear();
 
+	// used signals sigmapped
 	SigPool used_signals;
+	// used signals pre-sigmapped
 	SigPool raw_used_signals;
+	// used signals sigmapped, ignoring drivers (we keep track of this to set `unused_bits`)
 	SigPool used_signals_nodrivers;
+
+	// gather the usage information for cells
 	for (auto &it : module->cells_) {
 		RTLIL::Cell *cell = it.second;
 		for (auto &it2 : cell->connections_) {
-			assign_map.apply(it2.second);
+			assign_map.apply(it2.second); // modify the cell connection in place
 			raw_used_signals.add(it2.second);
 			used_signals.add(it2.second);
 			if (!ct_all.cell_output(cell->type, it2.first))
 				used_signals_nodrivers.add(it2.second);
 		}
 	}
+
+	// gather the usage information for ports, wires with `keep`,
+	// also gather init bits
 	dict<RTLIL::SigBit, RTLIL::State> init_bits;
 	for (auto &it : module->wires_) {
 		RTLIL::Wire *wire = it.second;
@@ -368,6 +399,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 		}
 	}
 
+	// set init attributes on all wires of a connected group
 	for (auto wire : module->wires()) {
 		bool found = false;
 		Const val(State::Sx, wire->width);
@@ -382,6 +414,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 			wire->attributes[ID::init] = val;
 	}
 
+	// now decide for each wire if we should be deleting it
 	pool<RTLIL::Wire*> del_wires_queue;
 	for (auto wire : module->wires())
 	{
@@ -410,10 +443,6 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 		if (!raw_used_signals.check_any(s1)) {
 			// delete wires that aren't used by anything directly
 			goto delete_this_wire;
-		} else
-		if (!used_signals.check_any(s2)) {
-			// delete wires that aren't used by anything indirectly, even though other wires may alias it
-			goto delete_this_wire;
 		}
 
 		if (0)
@@ -632,7 +661,7 @@ struct OptCleanPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		keep_cache.reset(design);
+		keep_cache.reset(design, purge_mode);
 
 		ct_reg.setup_internals_mem();
 		ct_reg.setup_internals_anyinit();
diff --git a/yosys/passes/opt/opt_demorgan.cc b/yosys/passes/opt/opt_demorgan.cc
index 1464c4177cd..4db3a810105 100644
--- a/yosys/passes/opt/opt_demorgan.cc
+++ b/yosys/passes/opt/opt_demorgan.cc
@@ -183,7 +183,7 @@ struct OptDemorganPass : public Pass {
 	{
 		log_header(design, "Executing OPT_DEMORGAN pass (push inverters through $reduce_* cells).\n");
 
-		int argidx = 0;
+		int argidx = 1;
 		extra_args(args, argidx, design);
 
 		unsigned int cells_changed = 0;
diff --git a/yosys/passes/opt/opt_dff.cc b/yosys/passes/opt/opt_dff.cc
index f090d20b2e8..b77be45151b 100644
--- a/yosys/passes/opt/opt_dff.cc
+++ b/yosys/passes/opt/opt_dff.cc
@@ -353,7 +353,7 @@ struct OptDffWorker
 					// Try a more complex conversion to plain async reset.
 					State val_neutral = ff.pol_set ? State::S0 : State::S1;
 					Const val_arst;
-					SigSpec sig_arst;
+					SigBit sig_arst;
 					if (ff.sig_clr[0] == val_neutral)
 						sig_arst = ff.sig_set[0];
 					else
diff --git a/yosys/passes/opt/opt_expr.cc b/yosys/passes/opt/opt_expr.cc
index 46773a344b1..3eadd35c6af 100644
--- a/yosys/passes/opt/opt_expr.cc
+++ b/yosys/passes/opt/opt_expr.cc
@@ -424,13 +424,19 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						for (auto &bit : sig)
 							outbit_to_cell[bit].insert(cell);
 				}
-			cells.node(cell);
+                        cells.node(cell);
 		}
 
-	for (auto &it_right : cell_to_inbit)
-	for (auto &it_sigbit : it_right.second)
-	for (auto &it_left : outbit_to_cell[it_sigbit])
-		cells.edge(it_left, it_right.first);
+        // Build the graph for the topological sort.
+	for (auto &it_right : cell_to_inbit) {
+          const int r_index = cells.node(it_right.first);
+          for (auto &it_sigbit : it_right.second) {
+            for (auto &it_left : outbit_to_cell[it_sigbit]) {
+              const int l_index = cells.node(it_left);
+              cells.edge(l_index, r_index);
+            }
+          }
+        }
 
 	cells.sort();
 
diff --git a/yosys/passes/opt/opt_ffinv.cc b/yosys/passes/opt/opt_ffinv.cc
index 3f7b4bc4a71..d982ef2d239 100644
--- a/yosys/passes/opt/opt_ffinv.cc
+++ b/yosys/passes/opt/opt_ffinv.cc
@@ -38,6 +38,7 @@ struct OptFfInvWorker
 	// - ... which has no other users
 	// - all users of FF are LUTs
 	bool push_d_inv(FfData &ff) {
+		log_assert(ff.width == 1);
 		if (index.query_is_input(ff.sig_d))
 			return false;
 		if (index.query_is_output(ff.sig_d))
@@ -90,7 +91,7 @@ struct OptFfInvWorker
 				int flip_mask = 0;
 				SigSpec sig_a = lut->getPort(ID::A);
 				for (int i = 0; i < GetSize(sig_a); i++) {
-					if (index.sigmap(sig_a[i]) == index.sigmap(ff.sig_q)) {
+					if (index.sigmap(sig_a[i]) == index.sigmap(ff.sig_q[0])) {
 						flip_mask |= 1 << i;
 					}
 				}
diff --git a/yosys/passes/opt/opt_lut.cc b/yosys/passes/opt/opt_lut.cc
index 3b079d964f4..d0fc6078120 100644
--- a/yosys/passes/opt/opt_lut.cc
+++ b/yosys/passes/opt/opt_lut.cc
@@ -24,6 +24,10 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+// Type represents the following constraint: Preserve connections to dedicated
+// logic cell <cell_type> that has ports connected to LUT inputs. This includes
+// the case where both LUT and dedicated logic input are connected to the same
+// constant.
 struct dlogic_t {
 	IdString cell_type;
 	// LUT input idx -> hard cell's port name
@@ -163,7 +167,11 @@ struct OptLutWorker
 							legal = false;
 							break;
 						}
-						if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)))
+
+						if (lut_dlogic.second->getPort(dlogic_conn.second).size() != 1)
+							continue;
+
+						if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)[0]))
 						{
 							log_debug("  LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));
 							log_debug("    LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type.c_str(), dlogic_conn.second.c_str(), log_signal(lut_dlogic.second->getPort(dlogic_conn.second)));
@@ -310,7 +318,7 @@ struct OptLutWorker
 
 			auto lutA = worklist.pop();
 			SigSpec lutA_input = sigmap(lutA->getPort(ID::A));
-			SigSpec lutA_output = sigmap(lutA->getPort(ID::Y)[0]);
+			SigBit lutA_output = sigmap(lutA->getPort(ID::Y)[0]);
 			int lutA_width = lutA->getParam(ID::WIDTH).as_int();
 			int lutA_arity = luts_arity[lutA];
 			pool<int> &lutA_dlogic_inputs = luts_dlogic_inputs[lutA];
@@ -515,16 +523,6 @@ struct OptLutWorker
 	}
 };
 
-static void split(std::vector<std::string> &tokens, const std::string &text, char sep)
-{
-	size_t start = 0, end = 0;
-	while ((end = text.find(sep, start)) != std::string::npos) {
-		tokens.push_back(text.substr(start, end - start));
-		start = end + 1;
-	}
-	tokens.push_back(text.substr(start));
-}
-
 struct OptLutPass : public Pass {
 	OptLutPass() : Pass("opt_lut", "optimize LUT cells") { }
 	void help() override
@@ -535,11 +533,9 @@ struct OptLutPass : public Pass {
 		log("\n");
 		log("This pass combines cascaded $lut cells with unused inputs.\n");
 		log("\n");
-		log("    -dlogic <type>:<cell-port>=<LUT-input>[:<cell-port>=<LUT-input>...]\n");
-		log("        preserve connections to dedicated logic cell <type> that has ports\n");
-		log("        <cell-port> connected to LUT inputs <LUT-input>. this includes\n");
-		log("        the case where both LUT and dedicated logic input are connected to\n");
-		log("        the same constant.\n");
+		log("	-tech ice40\n");
+		log("        treat the design as a LUT-mapped circuit for the iCE40 architecture\n");
+		log("        and preserve connections to SB_CARRY as appropriate\n");
 		log("\n");
 		log("    -limit N\n");
 		log("        only perform the first N combines, then stop. useful for debugging.\n");
@@ -555,28 +551,28 @@ struct OptLutPass : public Pass {
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			if (args[argidx] == "-dlogic" && argidx+1 < args.size())
+			if (args[argidx] == "-tech" && argidx+1 < args.size())
 			{
-				std::vector<std::string> tokens;
-				split(tokens, args[++argidx], ':');
-				if (tokens.size() < 2)
-					log_cmd_error("The -dlogic option requires at least one connection.\n");
-				dlogic_t entry;
-				entry.cell_type = "\\" + tokens[0];
-				for (auto it = tokens.begin() + 1; it != tokens.end(); ++it) {
-					std::vector<std::string> conn_tokens;
-					split(conn_tokens, *it, '=');
-					if (conn_tokens.size() != 2)
-						log_cmd_error("Invalid format of -dlogic signal mapping.\n");
-					IdString logic_port = "\\" + conn_tokens[0];
-					int lut_input = atoi(conn_tokens[1].c_str());
-					entry.lut_input_port[lut_input] = logic_port;
-				}
-				dlogic.push_back(entry);
+				std::string tech = args[++argidx];
+				if (tech != "ice40")
+					log_cmd_error("Unsupported -tech argument: %s\n", tech.c_str());
+
+				dlogic = {{
+					ID(SB_CARRY),
+					dict<int, IdString>{
+						std::make_pair(1, ID(I0)),
+						std::make_pair(2, ID(I1)),
+						std::make_pair(3, ID(CI))
+					}
+				}, {
+					ID(SB_CARRY),
+					dict<int, IdString>{
+						std::make_pair(3, ID(CO))
+					}
+				}};
 				continue;
 			}
-			if (args[argidx] == "-limit" && argidx + 1 < args.size())
-			{
+			if (args[argidx] == "-limit" && argidx + 1 < args.size()) {
 				limit = atoi(args[++argidx].c_str());
 				continue;
 			}
diff --git a/yosys/passes/opt/opt_lut_ins.cc b/yosys/passes/opt/opt_lut_ins.cc
index 2f7c392b29a..652fce1e2d5 100644
--- a/yosys/passes/opt/opt_lut_ins.cc
+++ b/yosys/passes/opt/opt_lut_ins.cc
@@ -39,7 +39,7 @@ struct OptLutInsPass : public Pass {
 		log("\n");
 		log("    -tech <technology>\n");
 		log("        Instead of generic $lut cells, operate on LUT cells specific\n");
-		log("        to the given technology.  Valid values are: xilinx, ecp5, gowin.\n");
+		log("        to the given technology.  Valid values are: xilinx, lattice, gowin.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -58,7 +58,7 @@ struct OptLutInsPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		if (techname != "" && techname != "xilinx" && techname != "ecp5" && techname != "gowin")
+		if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "ecp5" && techname != "gowin")
 			log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());
 
 		for (auto module : design->selected_modules())
@@ -130,7 +130,7 @@ struct OptLutInsPass : public Pass {
 						output = cell->getPort(ID::O);
 					else
 						output = cell->getPort(ID::F);
-				} else if (techname == "ecp5") {
+				} else if (techname == "lattice" || techname == "ecp5") {
 					if (cell->type == ID(LUT4)) {
 						inputs = {
 							cell->getPort(ID::A),
@@ -181,7 +181,7 @@ struct OptLutInsPass : public Pass {
 				if (!doit)
 					continue;
 				log("  Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs));
-				if (techname == "ecp5") {
+				if (techname == "lattice" || techname == "ecp5") {
 					// Pad the LUT to 4 inputs, adding consts from the front.
 					int extra = 4 - GetSize(new_inputs);
 					log_assert(extra >= 0);
@@ -215,9 +215,9 @@ struct OptLutInsPass : public Pass {
 					}
 					new_lut[i] = lut[lidx];
 				}
-				// For ecp5, and gowin do not replace with a const driver — the nextpnr
+				// For lattice, and gowin do not replace with a const driver — the nextpnr
 				// packer requires a complete set of LUTs for wide LUT muxes.
-				if (new_inputs.empty() && techname != "ecp5" && techname != "gowin") {
+				if (new_inputs.empty() && techname != "lattice" && techname != "ecp5" && techname != "gowin") {
 					// const driver.
 					remove_cells.push_back(cell);
 					module->connect(output, new_lut[0]);
@@ -226,7 +226,7 @@ struct OptLutInsPass : public Pass {
 						cell->setParam(ID::LUT, new_lut);
 						cell->setParam(ID::WIDTH, GetSize(new_inputs));
 						cell->setPort(ID::A, new_inputs);
-					} else if (techname == "ecp5") {
+					} else if (techname == "lattice" || techname == "ecp5") {
 						log_assert(GetSize(new_inputs) == 4);
 						cell->setParam(ID::INIT, new_lut);
 						cell->setPort(ID::A, new_inputs[0]);
diff --git a/yosys/passes/opt/opt_mem.cc b/yosys/passes/opt/opt_mem.cc
index 885b6f97d83..9a2d8e6a56f 100644
--- a/yosys/passes/opt/opt_mem.cc
+++ b/yosys/passes/opt/opt_mem.cc
@@ -52,6 +52,9 @@ struct OptMemPass : public Pass {
 
 		int total_count = 0;
 		for (auto module : design->selected_modules()) {
+			if (module->has_processes_warn())
+				continue;
+
 			SigMap sigmap(module);
 			FfInitVals initvals(&sigmap, module);
 			for (auto &mem : Mem::get_selected_memories(module)) {
diff --git a/yosys/passes/opt/opt_merge.cc b/yosys/passes/opt/opt_merge.cc
index e9d98cd4304..eb3aa462e01 100644
--- a/yosys/passes/opt/opt_merge.cc
+++ b/yosys/passes/opt/opt_merge.cc
@@ -41,7 +41,6 @@ struct OptMergeWorker
 
 	CellTypes ct;
 	int total_count;
-	SHA1 checksum;
 
 	static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
 	{
@@ -78,7 +77,7 @@ struct OptMergeWorker
 		return str;
 	}
 
-	std::string hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
+        uint64_t hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
 	{
 		vector<string> hash_conn_strings;
 		std::string hash_string = cell->type.str() + "\n";
@@ -149,8 +148,7 @@ struct OptMergeWorker
 		for (auto it : hash_conn_strings)
 			hash_string += it;
 
-		checksum.update(hash_string);
-		return checksum.final();
+		return std::hash<std::string>{}(hash_string);
 	}
 
 	bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
@@ -268,13 +266,16 @@ struct OptMergeWorker
 			}
 
 			did_something = false;
-			dict<std::string, RTLIL::Cell*> sharemap;
+                        dict<uint64_t, RTLIL::Cell*> sharemap;
 			for (auto cell : cells)
 			{
 				if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known())
 					continue;
 
-				auto hash = hash_cell_parameters_and_connections(cell);
+				if (cell->type == ID($scopeinfo))
+					continue;
+
+				uint64_t hash = hash_cell_parameters_and_connections(cell);
 				auto r = sharemap.insert(std::make_pair(hash, cell));
 				if (!r.second) {
 					if (compare_cell_parameters_and_connections(cell, r.first->second)) {
diff --git a/yosys/passes/opt/share.cc b/yosys/passes/opt/share.cc
index abef719370b..586bd9dfe9d 100644
--- a/yosys/passes/opt/share.cc
+++ b/yosys/passes/opt/share.cc
@@ -1032,7 +1032,7 @@ struct ShareWorker
 		}
 
 		bool found_scc = !toposort.sort();
-		topo_cell_drivers = std::move(toposort.database);
+		topo_cell_drivers = toposort.get_database();
 
 		if (found_scc && toposort.analyze_loops)
 			for (auto &loop : toposort.loops) {
diff --git a/yosys/passes/pmgen/Makefile.inc b/yosys/passes/pmgen/Makefile.inc
index a7ef642825c..ed872b7212d 100644
--- a/yosys/passes/pmgen/Makefile.inc
+++ b/yosys/passes/pmgen/Makefile.inc
@@ -1,5 +1,5 @@
 %_pm.h: passes/pmgen/pmgen.py %.pmg
-	$(P) mkdir -p passes/pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^)
+	$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^)
 
 # --------------------------------------
 
@@ -42,7 +42,9 @@ GENFILES += passes/pmgen/peepopt_pm.h
 passes/pmgen/peepopt.o: passes/pmgen/peepopt_pm.h
 $(eval $(call add_extra_objs,passes/pmgen/peepopt_pm.h))
 
-PEEPOPT_PATTERN  = passes/pmgen/peepopt_shiftmul.pmg
+PEEPOPT_PATTERN  = passes/pmgen/peepopt_shiftmul_right.pmg
+PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftmul_left.pmg
+PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftadd.pmg
 PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg
 
 passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
diff --git a/yosys/passes/pmgen/README.md b/yosys/passes/pmgen/README.md
index 39560839f0f..3205be1b55e 100644
--- a/yosys/passes/pmgen/README.md
+++ b/yosys/passes/pmgen/README.md
@@ -212,7 +212,7 @@ second argument, and the matcher will iterate over those options:
         index <SigSpec> port(eq, BA) === bar
         set eq_ab AB
         set eq_ba BA
-    generate
+    endmatch
 
 Notice how `define` can be used to define additional local variables similar
 to the loop variables defined by `slice` and `choice`.
diff --git a/yosys/passes/pmgen/ice40_dsp.cc b/yosys/passes/pmgen/ice40_dsp.cc
index 24134b1fb1f..5720c9b1e7a 100644
--- a/yosys/passes/pmgen/ice40_dsp.cc
+++ b/yosys/passes/pmgen/ice40_dsp.cc
@@ -289,7 +289,7 @@ struct Ice40DspPass : public Pass {
 		log("\n");
 		log("Pack input registers (A, B, {C,D}; with optional hold), pipeline registers\n");
 		log("({F,J,K,G}, H), output registers (O -- full 32-bits or lower 16-bits only; with\n");
-		log("optional hold), and post-adder into into the SB_MAC16 resource.\n");
+		log("optional hold), and post-adder into the SB_MAC16 resource.\n");
 		log("\n");
 		log("Multiply-accumulate operations using the post-adder with feedback on the {C,D}\n");
 		log("input will be folded into the DSP. In this scenario only, resetting the\n");
diff --git a/yosys/passes/pmgen/ice40_dsp.pmg b/yosys/passes/pmgen/ice40_dsp.pmg
index 4de4791228e..9099dd3c470 100644
--- a/yosys/passes/pmgen/ice40_dsp.pmg
+++ b/yosys/passes/pmgen/ice40_dsp.pmg
@@ -346,7 +346,7 @@ endmatch
 code argQ argD
 {
 	if (clock != SigBit()) {
-		if (port(ff, \CLK) != clock)
+		if (port(ff, \CLK)[0] != clock)
 			reject;
 		if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
 			reject;
@@ -393,7 +393,7 @@ endmatch
 code argQ
 	if (ff) {
 		if (clock != SigBit()) {
-			if (port(ff, \CLK) != clock)
+			if (port(ff, \CLK)[0] != clock)
 				reject;
 			if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
 				reject;
diff --git a/yosys/passes/pmgen/peepopt.cc b/yosys/passes/pmgen/peepopt.cc
index 9a497c91441..edd3b18a815 100644
--- a/yosys/passes/pmgen/peepopt.cc
+++ b/yosys/passes/pmgen/peepopt.cc
@@ -24,11 +24,8 @@ USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 bool did_something;
-dict<SigBit, State> initbits;
-pool<SigBit> rminitbits;
 
 #include "passes/pmgen/peepopt_pm.h"
-#include "generate.h"
 
 struct PeepoptPass : public Pass {
 	PeepoptPass() : Pass("peepopt", "collection of peephole optimizers") { }
@@ -40,38 +37,32 @@ struct PeepoptPass : public Pass {
 		log("\n");
 		log("This pass applies a collection of peephole optimizers to the current design.\n");
 		log("\n");
+		log("This pass employs the following rules:\n");
+		log("\n");
+		log("   * muldiv - Replace (A*B)/B with A\n");
+		log("\n");
+		log("   * shiftmul - Replace A>>(B*C) with A'>>(B<<K) where C and K are constants\n");
+		log("                and A' is derived from A by appropriately inserting padding\n");
+		log("                into the signal. (right variant)\n");
+		log("\n");
+		log("                Analogously, replace A<<(B*C) with appropriate selection of\n");
+		log("                output bits from A<<(B<<K). (left variant)\n");
+		log("\n");
+		log("   * shiftadd - Replace A>>(B+D) with (A'>>D)>>(B) where D is constant and\n");
+		log("                A' is derived from A by padding or cutting inaccessible bits.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		std::string genmode;
-
 		log_header(design, "Executing PEEPOPT pass (run peephole optimizers).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			if (args[argidx] == "-generate" && argidx+1 < args.size()) {
-				genmode = args[++argidx];
-				continue;
-			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
-		if (!genmode.empty())
-		{
-			initbits.clear();
-			rminitbits.clear();
-
-			if (genmode == "shiftmul")
-				GENERATE_PATTERN(peepopt_pm, shiftmul);
-			else if (genmode == "muldiv")
-				GENERATE_PATTERN(peepopt_pm, muldiv);
-			else
-				log_abort();
-			return;
-		}
-
 		for (auto module : design->selected_modules())
 		{
 			did_something = true;
@@ -79,47 +70,15 @@ struct PeepoptPass : public Pass {
 			while (did_something)
 			{
 				did_something = false;
-				initbits.clear();
-				rminitbits.clear();
 
 				peepopt_pm pm(module);
 
-				for (auto w : module->wires()) {
-					auto it = w->attributes.find(ID::init);
-					if (it != w->attributes.end()) {
-						SigSpec sig = pm.sigmap(w);
-						Const val = it->second;
-						int len = std::min(GetSize(sig), GetSize(val));
-						for (int i = 0; i < len; i++) {
-							if (sig[i].wire == nullptr)
-								continue;
-							if (val[i] != State::S0 && val[i] != State::S1)
-								continue;
-							initbits[sig[i]] = val[i];
-						}
-					}
-				}
-
 				pm.setup(module->selected_cells());
 
-				pm.run_shiftmul();
+				pm.run_shiftadd();
+				pm.run_shiftmul_right();
+				pm.run_shiftmul_left();
 				pm.run_muldiv();
-
-				for (auto w : module->wires()) {
-					auto it = w->attributes.find(ID::init);
-					if (it != w->attributes.end()) {
-						SigSpec sig = pm.sigmap(w);
-						Const &val = it->second;
-						int len = std::min(GetSize(sig), GetSize(val));
-						for (int i = 0; i < len; i++) {
-							if (rminitbits.count(sig[i]))
-								val[i] = State::Sx;
-						}
-					}
-				}
-
-				initbits.clear();
-				rminitbits.clear();
 			}
 		}
 	}
diff --git a/yosys/passes/pmgen/peepopt_shiftadd.pmg b/yosys/passes/pmgen/peepopt_shiftadd.pmg
new file mode 100644
index 00000000000..e690ff65113
--- /dev/null
+++ b/yosys/passes/pmgen/peepopt_shiftadd.pmg
@@ -0,0 +1,133 @@
+pattern shiftadd
+//
+// Transforms add/sub+shift pairs that result from expressions such as data[s*W +C +:W2]
+// specifically something like: out[W2-1:0] = data >> (s*W +C)
+// will be transformed into: out[W2-1:0] = (data >> C) >> (s*W)
+// this can then be optimized using peepopt_shiftmul_right.pmg
+//
+
+match shift
+	select shift->type.in($shift, $shiftx, $shr)
+	filter !port(shift, \B).empty()
+endmatch
+
+// the right shift amount
+state <SigSpec> shift_amount
+// log2 scale factor in interpreting of shift_amount
+// due to zero padding on the shift cell's B port
+state <int> log2scale
+// zeros at the MSB position make it unsigned
+state <bool> msb_zeros
+
+code shift_amount log2scale msb_zeros
+	shift_amount = port(shift, \B);
+
+	log2scale = 0;
+	while (shift_amount[0] == State::S0) {
+		shift_amount.remove(0);
+		if (shift_amount.empty()) reject;
+		log2scale++;
+	}
+
+	msb_zeros = 0;
+	while (shift_amount.bits().back() == State::S0) {
+		msb_zeros = true;
+		shift_amount.remove(GetSize(shift_amount) - 1);
+		if (shift_amount.empty()) reject;
+	}
+endcode
+
+state <bool>    var_signed
+state <SigSpec> var_signal
+// offset: signed constant value c in data[var+c +:W1] (constant shift-right amount)
+state <int>     offset
+
+match add
+	// either data[var+c +:W1] or data[var-c +:W1]
+	select add->type.in($add, $sub)
+	index <SigSpec> port(add, \Y) === shift_amount
+
+	// one must be constant, the other is variable
+	choice <IdString> constport {\A, \B}
+	select !port(add, constport).empty()
+	select port(add, constport).is_fully_const()
+	define <IdString> varport (constport == \A ? \B : \A)
+
+	// if a value of var is able to wrap the output, the transformation might give wrong results
+	// an addition/substraction can at most flip one more bit than the largest operand (the carry bit)
+	// as long as the output can show this bit, no wrap should occur (assuming all signed-ness make sense)
+	select ( GetSize(port(add, \Y)) > max(GetSize(port(add, \A)), GetSize(port(add, \B))) )
+
+	define <bool> varport_A (varport == \A)
+	define <bool> is_sub add->type.in($sub)
+
+	define <bool> constport_signed param(add, !varport_A ? \A_SIGNED : \B_SIGNED).as_bool()
+	define <bool> varport_signed param(add, varport_A ? \A_SIGNED : \B_SIGNED).as_bool();
+	define <bool> offset_negative ((port(add, constport).bits().back() == State::S1) ^ (is_sub && varport_A))
+
+	// checking some value boundaries as well:
+	// data[...-c +:W1] is fine for +/-var (pad at LSB, all data still accessible)
+	// data[...+c +:W1] is only fine for +var(add) and var unsigned
+	// (+c cuts lower C bits, making them inaccessible, a signed var could try to access them)
+	// either its an add or the variable port is A (it must be positive)
+	select (add->type.in($add) || varport == \A)
+
+	// -> data[var+c +:W1] (with var signed) is illegal
+	filter !(!offset_negative && varport_signed)
+
+	// state-variables are assigned at the end only:
+	// shift the log2scale offset in-front of add to get true value: (var+c)<<N -> (var<<N)+(c<<N)
+	set offset ( (port(add, constport).as_int(constport_signed) << log2scale) * ( (is_sub && varport_A) ? -1 : 1 ) )
+
+	set var_signed varport_signed
+	set var_signal add->getPort(varport)
+endmatch
+
+code
+{
+	// positive constant offset with a signed variable (index) cannot be handled
+	// the above filter should get rid of this case but 'offset' is calculated differently
+	// due to limitations of state-variables in pmgen
+	// it should only differ if previous passes create invalid data
+	log_assert(!(offset>0 && var_signed));
+
+	did_something = true;
+	log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \
+			log_id(module), log_id(shift), log_id(add), offset);
+
+	SigSpec old_a = port(shift, \A), new_a;
+	if(offset<0) {
+		// data >> (...-c) transformed to {data, c'X} >> (...)
+		SigSpec padding( (shift->type.in($shiftx) ? State::Sx : State::S0), -offset );
+		new_a.append(padding);
+		new_a.append(old_a);
+	} else {
+		// data >> (...+c) transformed to data[MAX:c] >> (...)
+		if(offset < GetSize(old_a)) { // some signal bits left?
+			new_a.append(old_a.extract_end(offset));
+		} else {
+			// warn user in case data is empty (no bits left)
+			std::string location = shift->get_src_attribute();
+			if (location.empty())
+				location = shift->name.str();
+			if(shift->type.in($shiftx))
+				log_warning("at %s: result of indexed part-selection is always constant (selecting from '%s' with index '%s + %d')\n", \
+							location.c_str(), log_signal(old_a), log_signal(var_signal), offset);
+			else
+				log_warning("at %s: result of shift operation is always constant (shifting '%s' by '%s + %d'-bits)\n", \
+							location.c_str(), log_signal(old_a), log_signal(var_signal), offset);
+		}
+	}
+
+	SigSpec new_b = {var_signal, SigSpec(State::S0, log2scale)};
+	if (msb_zeros || !var_signed)
+		new_b.append(State::S0);
+
+	shift->setPort(\A, new_a);
+	shift->setParam(\A_WIDTH, GetSize(new_a));
+	shift->setPort(\B, new_b);
+	shift->setParam(\B_WIDTH, GetSize(new_b));
+	blacklist(add);
+	accept;
+}
+endcode
diff --git a/yosys/passes/pmgen/peepopt_shiftmul.pmg b/yosys/passes/pmgen/peepopt_shiftmul.pmg
deleted file mode 100644
index d71fbf74449..00000000000
--- a/yosys/passes/pmgen/peepopt_shiftmul.pmg
+++ /dev/null
@@ -1,92 +0,0 @@
-pattern shiftmul
-//
-// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
-//
-
-state <SigSpec> shamt
-
-match shift
-	select shift->type.in($shift, $shiftx, $shr)
-endmatch
-
-code shamt
-	shamt = port(shift, \B);
-	if (shamt.empty())
-		reject;
-	if (shamt[GetSize(shamt)-1] == State::S0) {
-		do {
-			shamt.remove(GetSize(shamt)-1);
-			if (shamt.empty())
-				reject;
-		} while (shamt[GetSize(shamt)-1] == State::S0);
-	} else
-	if (shift->type.in($shift, $shiftx) && param(shift, \B_SIGNED).as_bool()) {
-		reject;
-	}
-	if (GetSize(shamt) > 20)
-		reject;
-endcode
-
-match mul
-	select mul->type.in($mul)
-	select port(mul, \A).is_fully_const() || port(mul, \B).is_fully_const()
-	index <SigSpec> port(mul, \Y) === shamt
-	filter !param(mul, \A_SIGNED).as_bool()
-endmatch
-
-code
-{
-	IdString const_factor_port = port(mul, \A).is_fully_const() ? \A : \B;
-	Const const_factor_cnst = port(mul, const_factor_port).as_const();
-	int const_factor = const_factor_cnst.as_int();
-
-	if (GetSize(const_factor_cnst) == 0)
-		reject;
-
-	if (GetSize(const_factor_cnst) > 20)
-		reject;
-
-	if (GetSize(port(shift, \Y)) > const_factor)
-		reject;
-
-	int factor_bits = ceil_log2(const_factor);
-	SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);
-
-	if (GetSize(shamt) < factor_bits+GetSize(mul_din))
-		reject;
-
-	did_something = true;
-	log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
-
-	int new_const_factor = 1 << factor_bits;
-	SigSpec padding(State::Sx, new_const_factor-const_factor);
-	SigSpec old_a = port(shift, \A), new_a;
-	int trunc = 0;
-
-	if (GetSize(old_a) % const_factor != 0) {
-		trunc = const_factor - GetSize(old_a) % const_factor;
-		old_a.append(SigSpec(State::Sx, trunc));
-	}
-
-	for (int i = 0; i*const_factor < GetSize(old_a); i++) {
-		SigSpec slice = old_a.extract(i*const_factor, const_factor);
-		new_a.append(slice);
-		new_a.append(padding);
-	}
-
-	if (trunc > 0)
-		new_a.remove(GetSize(new_a)-trunc, trunc);
-
-	SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
-	if (param(shift, \B_SIGNED).as_bool())
-		new_b.append(State::S0);
-
-	shift->setPort(\A, new_a);
-	shift->setParam(\A_WIDTH, GetSize(new_a));
-	shift->setPort(\B, new_b);
-	shift->setParam(\B_WIDTH, GetSize(new_b));
-
-	blacklist(shift);
-	accept;
-}
-endcode
diff --git a/yosys/passes/pmgen/peepopt_shiftmul_left.pmg b/yosys/passes/pmgen/peepopt_shiftmul_left.pmg
new file mode 100644
index 00000000000..607f8368c53
--- /dev/null
+++ b/yosys/passes/pmgen/peepopt_shiftmul_left.pmg
@@ -0,0 +1,160 @@
+pattern shiftmul_left
+//
+// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
+//
+
+match shift
+	select shift->type.in($shift, $shiftx, $shl)
+	select shift->type.in($shl) || param(shift, \B_SIGNED).as_bool()
+	filter !port(shift, \B).empty()
+endmatch
+
+match neg
+	if shift->type.in($shift, $shiftx)
+	select neg->type == $neg
+	index <SigSpec> port(neg, \Y) === port(shift, \B)
+	filter !port(shift, \A).empty()
+endmatch
+
+// the left shift amount
+state <SigSpec> shift_amount
+// log2 scale factor in interpreting of shift_amount
+// due to zero padding on the shift cell's B port
+state <int> log2scale
+
+code shift_amount log2scale
+	if (neg) {
+		// case of `$shift`, `$shiftx`
+		shift_amount = port(neg, \A);
+		if (!param(neg, \A_SIGNED).as_bool())
+			shift_amount.append(State::S0);
+	} else {
+		// case of `$shl`
+		shift_amount = port(shift, \B);
+		if (!param(shift, \B_SIGNED).as_bool())
+			shift_amount.append(State::S0);
+	}
+
+	// at this point shift_amount is signed, make
+	// sure we can never go negative
+	if (shift_amount.bits().back() != State::S0)
+		reject;
+
+	while (shift_amount.bits().back() == State::S0) {
+		shift_amount.remove(GetSize(shift_amount) - 1);
+		if (shift_amount.empty()) reject;
+	}
+
+	log2scale = 0;
+	while (shift_amount[0] == State::S0) {
+		shift_amount.remove(0);
+		if (shift_amount.empty()) reject;
+		log2scale++;
+	}
+
+	if (GetSize(shift_amount) > 20)
+		reject;
+endcode
+
+state <SigSpec> mul_din
+state <Const> mul_const
+
+match mul
+	select mul->type.in($mul)
+	index <SigSpec> port(mul, \Y) === shift_amount
+	filter !param(mul, \A_SIGNED).as_bool()
+
+	choice <IdString> constport {\A, \B}
+	filter port(mul, constport).is_fully_const()
+
+	define <IdString> varport (constport == \A ? \B : \A)
+	set mul_const SigSpec({port(mul, constport), SigSpec(State::S0, log2scale)}).as_const()
+	// get mul_din unmapped (so no `port()` shorthand)
+	// because we will be using it to set the \A port
+	// on the shift cell, and we want to stay close
+	// to the original design
+	set mul_din mul->getPort(varport)
+endmatch
+
+code
+{
+	if (mul_const.empty() || GetSize(mul_const) > 20)
+		reject;
+
+	// make sure there's no overlap in the signal
+	// selections by the shiftmul pattern
+	if (GetSize(port(shift, \A)) > mul_const.as_int())
+		reject;
+
+	int factor_bits = ceil_log2(mul_const.as_int());
+	// make sure the multiplication never wraps around
+	if (GetSize(shift_amount) < factor_bits + GetSize(mul_din))
+		reject;
+
+	if (neg) {
+		// make sure the negation never wraps around
+		if (GetSize(port(shift, \B)) < factor_bits + GetSize(mul_din)
+										+ log2scale + 1)
+			reject;
+	}
+
+	did_something = true;
+	log("left shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
+
+	int const_factor = mul_const.as_int();
+	int new_const_factor = 1 << factor_bits;
+	SigSpec padding(State::Sm, new_const_factor-const_factor);
+	SigSpec old_y = port(shift, \Y), new_y;
+	int trunc = 0;
+
+	if (GetSize(old_y) % const_factor != 0) {
+		trunc = const_factor - GetSize(old_y) % const_factor;
+		old_y.append(SigSpec(State::Sm, trunc));
+	}
+
+	for (int i = 0; i*const_factor < GetSize(old_y); i++) {
+		SigSpec slice = old_y.extract(i*const_factor, const_factor);
+		new_y.append(slice);
+		new_y.append(padding);
+	}
+
+	if (trunc > 0)
+		new_y.remove(GetSize(new_y)-trunc, trunc);
+
+	{
+		// Now replace occurences of Sm in new_y with bits
+		// of a dummy wire
+		int padbits = 0;
+		for (auto bit : new_y)
+		if (bit == SigBit(State::Sm))
+			padbits++;
+
+		SigSpec padwire = module->addWire(NEW_ID, padbits);
+
+		for (int i = new_y.size() - 1; i >= 0; i--)
+		if (new_y[i] == SigBit(State::Sm)) {
+			new_y[i] = padwire.bits().back();
+			padwire.remove(padwire.size() - 1);
+		}
+	}
+
+	SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
+
+	shift->setPort(\Y, new_y);
+	shift->setParam(\Y_WIDTH, GetSize(new_y));
+	if (shift->type == $shl) {
+		if (param(shift, \B_SIGNED).as_bool())
+			new_b.append(State::S0);
+		shift->setPort(\B, new_b);
+		shift->setParam(\B_WIDTH, GetSize(new_b));
+	} else {
+		SigSpec b_neg = module->addWire(NEW_ID, GetSize(new_b) + 1);
+		module->addNeg(NEW_ID, new_b, b_neg);
+		shift->setPort(\B, b_neg);
+		shift->setParam(\B_WIDTH, GetSize(b_neg));
+	}
+
+	blacklist(shift);
+	accept;
+}
+endcode
diff --git a/yosys/passes/pmgen/peepopt_shiftmul_right.pmg b/yosys/passes/pmgen/peepopt_shiftmul_right.pmg
new file mode 100644
index 00000000000..108829d4f9d
--- /dev/null
+++ b/yosys/passes/pmgen/peepopt_shiftmul_right.pmg
@@ -0,0 +1,108 @@
+pattern shiftmul_right
+//
+// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
+//
+
+match shift
+	select shift->type.in($shift, $shiftx, $shr)
+	filter !port(shift, \B).empty()
+endmatch
+
+// the right shift amount
+state <SigSpec> shift_amount
+// log2 scale factor in interpreting of shift_amount
+// due to zero padding on the shift cell's B port
+state <int> log2scale
+
+code shift_amount log2scale
+	shift_amount = port(shift, \B);
+	if (shift->type.in($shr) || !param(shift, \B_SIGNED).as_bool())
+		shift_amount.append(State::S0);
+
+	// at this point shift_amount is signed, make
+	// sure we can never go negative
+	if (shift_amount.bits().back() != State::S0)
+		reject;
+
+	while (shift_amount.bits().back() == State::S0) {
+		shift_amount.remove(GetSize(shift_amount) - 1);
+		if (shift_amount.empty()) reject;
+	}
+
+	log2scale = 0;
+	while (shift_amount[0] == State::S0) {
+		shift_amount.remove(0);
+		if (shift_amount.empty()) reject;
+		log2scale++;
+	}
+
+	if (GetSize(shift_amount) > 20)
+		reject;
+endcode
+
+state <SigSpec> mul_din
+state <Const> mul_const
+
+match mul
+	select mul->type.in($mul)
+	index <SigSpec> port(mul, \Y) === shift_amount
+	filter !param(mul, \A_SIGNED).as_bool()
+
+	choice <IdString> constport {\A, \B}
+	filter port(mul, constport).is_fully_const()
+
+	define <IdString> varport (constport == \A ? \B : \A)
+	set mul_const SigSpec({port(mul, constport), SigSpec(State::S0, log2scale)}).as_const()
+	// get mul_din unmapped (so no `port()` shorthand)
+	// because we will be using it to set the \A port
+	// on the shift cell, and we want to stay close
+	// to the original design
+	set mul_din mul->getPort(varport)
+endmatch
+
+code
+{
+	if (mul_const.empty() || GetSize(mul_const) > 20)
+		reject;
+
+	// make sure there's no overlap in the signal
+	// selections by the shiftmul pattern
+	if (GetSize(port(shift, \Y)) > mul_const.as_int())
+		reject;
+
+	int factor_bits = ceil_log2(mul_const.as_int());
+	// make sure the multiplication never wraps around
+	if (GetSize(shift_amount) + log2scale < factor_bits + GetSize(mul_din))
+		reject;
+
+	did_something = true;
+	log("right shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
+
+	int const_factor = mul_const.as_int();
+	int new_const_factor = 1 << factor_bits;
+	SigSpec padding(State::Sx, new_const_factor-const_factor);
+	SigSpec old_a = port(shift, \A), new_a;
+
+	for (int i = 0; i*const_factor < GetSize(old_a); i++) {
+		if ((i+1)*const_factor < GetSize(old_a)) {
+			SigSpec slice = old_a.extract(i*const_factor, const_factor);
+			new_a.append(slice);
+			new_a.append(padding);
+		} else {
+			new_a.append(old_a.extract_end(i*const_factor));
+		}
+	}
+
+	SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
+	if (param(shift, \B_SIGNED).as_bool())
+		new_b.append(State::S0);
+
+	shift->setPort(\A, new_a);
+	shift->setParam(\A_WIDTH, GetSize(new_a));
+	shift->setPort(\B, new_b);
+	shift->setParam(\B_WIDTH, GetSize(new_b));
+
+	blacklist(shift);
+	accept;
+}
+endcode
diff --git a/yosys/passes/pmgen/xilinx_dsp.pmg b/yosys/passes/pmgen/xilinx_dsp.pmg
index 0cd23c09da0..817a15a1e8f 100644
--- a/yosys/passes/pmgen/xilinx_dsp.pmg
+++ b/yosys/passes/pmgen/xilinx_dsp.pmg
@@ -415,7 +415,7 @@ match ff
 	filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
 	filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
 
-	filter clock == SigBit() || port(ff, \CLK) == clock
+	filter clock == SigBit() || port(ff, \CLK)[0] == clock
 endmatch
 
 code argQ
@@ -465,7 +465,7 @@ match ff
 	filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
 	filter port(ff, \D).extract(offset, GetSize(argD)) == argD
 
-	filter clock == SigBit() || port(ff, \CLK) == clock
+	filter clock == SigBit() || port(ff, \CLK)[0] == clock
 endmatch
 
 code argQ
diff --git a/yosys/passes/pmgen/xilinx_dsp48a.pmg b/yosys/passes/pmgen/xilinx_dsp48a.pmg
index dce1b61b005..f3bd9bc9567 100644
--- a/yosys/passes/pmgen/xilinx_dsp48a.pmg
+++ b/yosys/passes/pmgen/xilinx_dsp48a.pmg
@@ -354,7 +354,7 @@ match ff
 	filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
 	filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
 
-	filter clock == SigBit() || port(ff, \CLK) == clock
+	filter clock == SigBit() || port(ff, \CLK)[0] == clock
 endmatch
 
 code argQ
@@ -404,7 +404,7 @@ match ff
 	filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
 	filter port(ff, \D).extract(offset, GetSize(argD)) == argD
 
-	filter clock == SigBit() || port(ff, \CLK) == clock
+	filter clock == SigBit() || port(ff, \CLK)[0] == clock
 endmatch
 
 code argQ
diff --git a/yosys/passes/pmgen/xilinx_dsp_CREG.pmg b/yosys/passes/pmgen/xilinx_dsp_CREG.pmg
index 95379771a2d..49e79dd8723 100644
--- a/yosys/passes/pmgen/xilinx_dsp_CREG.pmg
+++ b/yosys/passes/pmgen/xilinx_dsp_CREG.pmg
@@ -135,7 +135,7 @@ match ff
 	filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
 	filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
 
-	filter clock == SigBit() || port(ff, \CLK) == clock
+	filter clock == SigBit() || port(ff, \CLK)[0] == clock
 endmatch
 
 code argQ
diff --git a/yosys/passes/pmgen/xilinx_dsp_cascade.pmg b/yosys/passes/pmgen/xilinx_dsp_cascade.pmg
index 06601554c6b..29fc27dfed6 100644
--- a/yosys/passes/pmgen/xilinx_dsp_cascade.pmg
+++ b/yosys/passes/pmgen/xilinx_dsp_cascade.pmg
@@ -46,7 +46,7 @@ pattern xilinx_dsp_cascade
 udata <std::function<SigSpec(const SigSpec&)>> unextend
 udata <vector<std::tuple<Cell*,int,int,int>>> chain longest_chain
 state <Cell*> next
-state <SigSpec> clock
+state <SigBit> clock
 state <int> AREG BREG
 
 // Variables used for subpatterns
@@ -395,7 +395,7 @@ match ff
 	filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
 	filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
 
-	filter clock == SigBit() || port(ff, \CLK) == clock
+	filter clock == SigBit() || port(ff, \CLK)[0] == clock
 endmatch
 
 code argQ
diff --git a/yosys/passes/proc/proc_clean.cc b/yosys/passes/proc/proc_clean.cc
index 45872907bd8..95cb0e88ca9 100644
--- a/yosys/passes/proc/proc_clean.cc
+++ b/yosys/passes/proc/proc_clean.cc
@@ -31,7 +31,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth)
 {
-	if (sw->signal.size() > 0 && sw->signal.is_fully_const())
+	if (sw->signal.size() > 0 && sw->signal.is_fully_def())
 	{
 		int found_matching_case_idx = -1;
 		for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++)
@@ -41,7 +41,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
 				break;
 			for (int j = 0; j < int(cs->compare.size()); j++) {
 				RTLIL::SigSpec &val = cs->compare[j];
-				if (!val.is_fully_const())
+				if (!val.is_fully_def())
 					continue;
 				if (val == sw->signal) {
 					cs->compare.clear();
diff --git a/yosys/passes/proc/proc_dlatch.cc b/yosys/passes/proc/proc_dlatch.cc
index 8340e143197..5b392ce512b 100644
--- a/yosys/passes/proc/proc_dlatch.cc
+++ b/yosys/passes/proc/proc_dlatch.cc
@@ -46,7 +46,7 @@ struct proc_dlatch_db_t
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type.in(ID($mux), ID($pmux)))
+			if (cell->type.in(ID($mux), ID($pmux), ID($bwmux)))
 			{
 				auto sig_y = sigmap(cell->getPort(ID::Y));
 				for (int i = 0; i < GetSize(sig_y); i++)
@@ -186,6 +186,8 @@ struct proc_dlatch_db_t
 		Cell *cell = it->second.first;
 		int index = it->second.second;
 
+		log_assert(cell->type.in(ID($mux), ID($pmux), ID($bwmux)));
+		bool is_bwmux = (cell->type == ID($bwmux));
 		SigSpec sig_a = sigmap(cell->getPort(ID::A));
 		SigSpec sig_b = sigmap(cell->getPort(ID::B));
 		SigSpec sig_s = sigmap(cell->getPort(ID::S));
@@ -200,12 +202,16 @@ struct proc_dlatch_db_t
 				sig[index] = State::Sx;
 				cell->setPort(ID::A, sig);
 			}
-			for (int i = 0; i < GetSize(sig_s); i++)
-				n = make_inner(sig_s[i], State::S0, n);
+			if (!is_bwmux) {
+				for (int i = 0; i < GetSize(sig_s); i++)
+					n = make_inner(sig_s[i], State::S0, n);
+			} else {
+				n = make_inner(sig_s[index], State::S0, n);
+			}
 			children.insert(n);
 		}
 
-		for (int i = 0; i < GetSize(sig_s); i++) {
+		for (int i = 0; i < (is_bwmux ? 1 : GetSize(sig_s)); i++) {
 			n = find_mux_feedback(sig_b[i*width + index], needle, set_undef);
 			if (n != false_node) {
 				if (set_undef && sig_b[i*width + index] == needle) {
@@ -213,7 +219,7 @@ struct proc_dlatch_db_t
 					sig[i*width + index] = State::Sx;
 					cell->setPort(ID::B, sig);
 				}
-				children.insert(make_inner(sig_s[i], State::S1, n));
+				children.insert(make_inner(sig_s[is_bwmux ? index : i], State::S1, n));
 			}
 		}
 
diff --git a/yosys/passes/proc/proc_rom.cc b/yosys/passes/proc/proc_rom.cc
index b83466ce75a..ebc2377aafa 100644
--- a/yosys/passes/proc/proc_rom.cc
+++ b/yosys/passes/proc/proc_rom.cc
@@ -66,6 +66,11 @@ struct RomWorker
 			}
 		}
 
+		if (lhs.empty()) {
+			log_debug("rejecting switch: lhs empty\n");
+			return;
+		}
+
 		int swsigbits = 0;
 		for (int i = 0; i < GetSize(sw->signal); i++)
 			if (sw->signal[i] != State::S0)
diff --git a/yosys/passes/sat/async2sync.cc b/yosys/passes/sat/async2sync.cc
index 6fdf470b12b..93c7e96c809 100644
--- a/yosys/passes/sat/async2sync.cc
+++ b/yosys/passes/sat/async2sync.cc
@@ -41,31 +41,88 @@ struct Async2syncPass : public Pass {
 		log("reset value in the next cycle regardless of the data-in value at the time of\n");
 		log("the clock edge.\n");
 		log("\n");
+		log("    -nolower\n");
+		log("        Do not automatically run 'chformal -lower' to lower $check cells.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		// bool flag_noinit = false;
+		bool flag_nolower = false;
 
 		log_header(design, "Executing ASYNC2SYNC pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			// if (args[argidx] == "-noinit") {
-			// 	flag_noinit = true;
-			// 	continue;
-			// }
+			if (args[argidx] == "-nolower") {
+				flag_nolower = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
+		bool have_check_cells = false;
+
 		for (auto module : design->selected_modules())
 		{
 			SigMap sigmap(module);
 			FfInitVals initvals(&sigmap, module);
 
+			SigBit initstate;
+
 			for (auto cell : vector<Cell*>(module->selected_cells()))
 			{
+				if (cell->type.in(ID($print), ID($check)))
+				{
+					if (cell->type == ID($check))
+						have_check_cells = true;
+
+					bool trg_enable = cell->getParam(ID(TRG_ENABLE)).as_bool();
+					if (!trg_enable)
+						continue;
+
+					int trg_width = cell->getParam(ID(TRG_WIDTH)).as_int();
+
+					if (trg_width > 1)
+						log_error("$check cell %s with TRG_WIDTH > 1 is not support by async2sync, use clk2fflogic.\n", log_id(cell));
+
+					if (trg_width == 0) {
+						if (initstate == State::S0)
+							initstate = module->Initstate(NEW_ID);
+
+						SigBit sig_en = cell->getPort(ID::EN);
+						cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate));
+					} else {
+						SigBit sig_en = cell->getPort(ID::EN);
+						SigSpec sig_args = cell->getPort(ID::ARGS);
+						bool trg_polarity = cell->getParam(ID(TRG_POLARITY)).as_bool();
+						SigBit sig_trg = cell->getPort(ID::TRG);
+						Wire *sig_en_q = module->addWire(NEW_ID);
+						Wire *sig_args_q = module->addWire(NEW_ID, GetSize(sig_args));
+						sig_en_q->attributes.emplace(ID::init, State::S0);
+						module->addDff(NEW_ID, sig_trg, sig_en, sig_en_q, trg_polarity, cell->get_src_attribute());
+						module->addDff(NEW_ID, sig_trg, sig_args, sig_args_q, trg_polarity, cell->get_src_attribute());
+						cell->setPort(ID::EN, sig_en_q);
+						cell->setPort(ID::ARGS, sig_args_q);
+						if (cell->type == ID($check)) {
+							SigBit sig_a = cell->getPort(ID::A);
+							Wire *sig_a_q = module->addWire(NEW_ID);
+							sig_a_q->attributes.emplace(ID::init, State::S1);
+							module->addDff(NEW_ID, sig_trg, sig_a, sig_a_q, trg_polarity, cell->get_src_attribute());
+							cell->setPort(ID::A, sig_a_q);
+						}
+					}
+
+					cell->setPort(ID::TRG, SigSpec());
+
+					cell->setParam(ID::TRG_ENABLE, false);
+					cell->setParam(ID::TRG_WIDTH, 0);
+					cell->setParam(ID::TRG_POLARITY, false);
+					cell->set_bool_attribute(ID(trg_on_gclk));
+					continue;
+				}
+
 				if (!RTLIL::builtin_ff_cell_types().count(cell->type))
 					continue;
 
@@ -273,6 +330,12 @@ struct Async2syncPass : public Pass {
 				ff.emit();
 			}
 		}
+
+		if (have_check_cells && !flag_nolower) {
+			log_push();
+			Pass::call(design, "chformal -lower");
+			log_pop();
+		}
 	}
 } Async2syncPass;
 
diff --git a/yosys/passes/sat/clk2fflogic.cc b/yosys/passes/sat/clk2fflogic.cc
index 3dc96ecce2a..bcefa7d8f92 100644
--- a/yosys/passes/sat/clk2fflogic.cc
+++ b/yosys/passes/sat/clk2fflogic.cc
@@ -48,6 +48,9 @@ struct Clk2fflogicPass : public Pass {
 		log("reset value in the next cycle regardless of the data-in value at the time of\n");
 		log("the clock edge.\n");
 		log("\n");
+		log("    -nolower\n");
+		log("        Do not automatically run 'chformal -lower' to lower $check cells.\n");
+		log("\n");
 	}
 	// Active-high sampled and current value of a level-triggered control signal. Initial sampled values is low/non-asserted.
 	SampledSig sample_control(Module *module, SigSpec sig, bool polarity, bool is_fine) {
@@ -117,21 +120,23 @@ struct Clk2fflogicPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		// bool flag_noinit = false;
+		bool flag_nolower = false;
 
 		log_header(design, "Executing CLK2FFLOGIC pass (convert clocked FFs to generic $ff cells).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			// if (args[argidx] == "-noinit") {
-			// 	flag_noinit = true;
-			// 	continue;
-			// }
+			if (args[argidx] == "-nolower") {
+				flag_nolower = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
+		bool have_check_cells = false;
+
 		for (auto module : design->selected_modules())
 		{
 			SigMap sigmap(module);
@@ -194,79 +199,138 @@ struct Clk2fflogicPass : public Pass {
 				mem.emit();
 			}
 
+			SigBit initstate;
+
 			for (auto cell : vector<Cell*>(module->selected_cells()))
 			{
-				SigSpec qval;
-				if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
-					FfData ff(&initvals, cell);
+				if (cell->type.in(ID($print), ID($check)))
+				{
+					if (cell->type == ID($check))
+						have_check_cells = true;
 
-					if (ff.has_gclk) {
-						// Already a $ff or $_FF_ cell.
+					bool trg_enable = cell->getParam(ID(TRG_ENABLE)).as_bool();
+					if (!trg_enable)
 						continue;
-					}
 
-					if (ff.has_clk) {
-						log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
-								log_id(module), log_id(cell), log_id(cell->type),
-								log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
-					} else if (ff.has_aload) {
-						log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
-								log_id(module), log_id(cell), log_id(cell->type),
-								log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
+					int trg_width = cell->getParam(ID(TRG_WIDTH)).as_int();
+
+					if (trg_width == 0) {
+						if (initstate == State::S0)
+							initstate = module->Initstate(NEW_ID);
+
+						SigBit sig_en = cell->getPort(ID::EN);
+						cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate));
 					} else {
-						// $sr.
-						log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
-								log_id(module), log_id(cell), log_id(cell->type),
-								log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
+						SigBit sig_en = cell->getPort(ID::EN);
+						SigSpec sig_args = cell->getPort(ID::ARGS);
+						Const trg_polarity = cell->getParam(ID(TRG_POLARITY));
+						SigSpec sig_trg = cell->getPort(ID::TRG);
+
+						SigSpec sig_trg_sampled;
+
+						for (auto const &bit : sig_trg)
+							sig_trg_sampled.append(sample_control_edge(module, bit, trg_polarity[GetSize(sig_trg_sampled)] == State::S1, false));
+						SigSpec sig_args_sampled = sample_data(module, sig_args, Const(State::S0, GetSize(sig_args)), false, false).sampled;
+						SigBit sig_en_sampled = sample_data(module, sig_en, State::S0, false, false).sampled;
+
+						SigBit sig_trg_combined = module->ReduceOr(NEW_ID, sig_trg_sampled);
+
+						cell->setPort(ID::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined));
+						cell->setPort(ID::ARGS, sig_args_sampled);
+						if (cell->type == ID($check)) {
+							SigBit sig_a = cell->getPort(ID::A);
+							SigBit sig_a_sampled = sample_data(module, sig_a, State::S1, false, false).sampled;
+							cell->setPort(ID::A, sig_a_sampled);
+						}
 					}
 
-					ff.remove();
+					cell->setPort(ID::TRG, SigSpec());
 
-					if (ff.has_clk)
-						ff.unmap_ce_srst();
+					cell->setParam(ID::TRG_ENABLE, false);
+					cell->setParam(ID::TRG_WIDTH, 0);
+					cell->setParam(ID::TRG_POLARITY, false);
+					cell->set_bool_attribute(ID(trg_on_gclk));
 
-					auto next_q = sample_data(module, ff.sig_q, ff.val_init, ff.is_fine, true).sampled;
+					continue;
+				}
 
-					if (ff.has_clk) {
-						// The init value for the sampled d is never used, so we can set it to fixed zero, reducing uninit'd FFs
-						auto sampled_d = sample_data(module, ff.sig_d, RTLIL::Const(State::S0, ff.width), ff.is_fine);
-						auto clk_edge = sample_control_edge(module, ff.sig_clk, ff.pol_clk, ff.is_fine);
-						next_q = mux(module, next_q, sampled_d.sampled, clk_edge, ff.is_fine);
-					}
+				if (!RTLIL::builtin_ff_cell_types().count(cell->type))
+					continue;
 
-					SampledSig sampled_aload, sampled_ad, sampled_set, sampled_clr, sampled_arst;
-					// The check for a constant sig_aload is also done by opt_dff, but when using verific and running
-					// clk2fflogic before opt_dff (which does more and possibly unwanted optimizations) this check avoids
-					// generating a lot of extra logic.
-					bool has_nonconst_aload = ff.has_aload && ff.sig_aload != (ff.pol_aload ? State::S0 : State::S1);
-					if (has_nonconst_aload) {
-						sampled_aload = sample_control(module, ff.sig_aload, ff.pol_aload, ff.is_fine);
-						// The init value for the sampled ad is never used, so we can set it to fixed zero, reducing uninit'd FFs
-						sampled_ad = sample_data(module, ff.sig_ad, RTLIL::Const(State::S0, ff.width), ff.is_fine);
-					}
-					if (ff.has_sr) {
-						sampled_set = sample_control(module, ff.sig_set, ff.pol_set, ff.is_fine);
-						sampled_clr = sample_control(module, ff.sig_clr, ff.pol_clr, ff.is_fine);
-					}
-					if (ff.has_arst)
-						sampled_arst = sample_control(module, ff.sig_arst, ff.pol_arst, ff.is_fine);
-
-					// First perform updates using _only_ sampled values, then again using _only_ current values. Unlike the previous
-					// implementation, this approach correctly handles all the cases of multiple signals changing simultaneously.
-					for (int current = 0; current < 2; current++) {
-						if (has_nonconst_aload)
-							next_q = mux(module, next_q, sampled_ad[current], sampled_aload[current], ff.is_fine);
-						if (ff.has_sr)
-							next_q = bitwise_sr(module, next_q, sampled_set[current], sampled_clr[current], ff.is_fine);
-						if (ff.has_arst)
-							next_q = mux(module, next_q, ff.val_arst, sampled_arst[current], ff.is_fine);
-					}
+				FfData ff(&initvals, cell);
 
-					module->connect(ff.sig_q, next_q);
+				if (ff.has_gclk) {
+					// Already a $ff or $_FF_ cell.
+					continue;
 				}
+
+				if (ff.has_clk) {
+					log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
+							log_id(module), log_id(cell), log_id(cell->type),
+							log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
+				} else if (ff.has_aload) {
+					log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
+							log_id(module), log_id(cell), log_id(cell->type),
+							log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
+				} else {
+					// $sr.
+					log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
+							log_id(module), log_id(cell), log_id(cell->type),
+							log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
+				}
+
+				ff.remove();
+
+				if (ff.has_clk)
+					ff.unmap_ce_srst();
+
+				auto next_q = sample_data(module, ff.sig_q, ff.val_init, ff.is_fine, true).sampled;
+
+				if (ff.has_clk) {
+					// The init value for the sampled d is never used, so we can set it to fixed zero, reducing uninit'd FFs
+					auto sampled_d = sample_data(module, ff.sig_d, RTLIL::Const(State::S0, ff.width), ff.is_fine);
+					auto clk_edge = sample_control_edge(module, ff.sig_clk, ff.pol_clk, ff.is_fine);
+					next_q = mux(module, next_q, sampled_d.sampled, clk_edge, ff.is_fine);
+				}
+
+				SampledSig sampled_aload, sampled_ad, sampled_set, sampled_clr, sampled_arst;
+				// The check for a constant sig_aload is also done by opt_dff, but when using verific and running
+				// clk2fflogic before opt_dff (which does more and possibly unwanted optimizations) this check avoids
+				// generating a lot of extra logic.
+				bool has_nonconst_aload = ff.has_aload && ff.sig_aload != (ff.pol_aload ? State::S0 : State::S1);
+				if (has_nonconst_aload) {
+					sampled_aload = sample_control(module, ff.sig_aload, ff.pol_aload, ff.is_fine);
+					// The init value for the sampled ad is never used, so we can set it to fixed zero, reducing uninit'd FFs
+					sampled_ad = sample_data(module, ff.sig_ad, RTLIL::Const(State::S0, ff.width), ff.is_fine);
+				}
+				if (ff.has_sr) {
+					sampled_set = sample_control(module, ff.sig_set, ff.pol_set, ff.is_fine);
+					sampled_clr = sample_control(module, ff.sig_clr, ff.pol_clr, ff.is_fine);
+				}
+				if (ff.has_arst)
+					sampled_arst = sample_control(module, ff.sig_arst, ff.pol_arst, ff.is_fine);
+
+				// First perform updates using _only_ sampled values, then again using _only_ current values. Unlike the previous
+				// implementation, this approach correctly handles all the cases of multiple signals changing simultaneously.
+				for (int current = 0; current < 2; current++) {
+					if (has_nonconst_aload)
+						next_q = mux(module, next_q, sampled_ad[current], sampled_aload[current], ff.is_fine);
+					if (ff.has_sr)
+						next_q = bitwise_sr(module, next_q, sampled_set[current], sampled_clr[current], ff.is_fine);
+					if (ff.has_arst)
+						next_q = mux(module, next_q, ff.val_arst, sampled_arst[current], ff.is_fine);
+				}
+
+				module->connect(ff.sig_q, next_q);
+
 			}
 		}
 
+		if (have_check_cells && !flag_nolower) {
+			log_push();
+			Pass::call(design, "chformal -lower");
+			log_pop();
+		}
 	}
 } Clk2fflogicPass;
 
diff --git a/yosys/passes/sat/eval.cc b/yosys/passes/sat/eval.cc
index 05879426e63..acebea6c568 100644
--- a/yosys/passes/sat/eval.cc
+++ b/yosys/passes/sat/eval.cc
@@ -543,13 +543,13 @@ struct EvalPass : public Pass {
 
 				int pos = 0;
 				for (auto &c : tabsigs.chunks()) {
-					tab_line.push_back(log_signal(RTLIL::SigSpec(tabvals).extract(pos, c.width)));
+					tab_line.push_back(log_signal(RTLIL::SigSpec(tabvals).extract(pos, c.width), false));
 					pos += c.width;
 				}
 
 				pos = 0;
 				for (auto &c : signal.chunks()) {
-					tab_line.push_back(log_signal(value.extract(pos, c.width)));
+					tab_line.push_back(log_signal(value.extract(pos, c.width), false));
 					pos += c.width;
 				}
 
diff --git a/yosys/passes/sat/formalff.cc b/yosys/passes/sat/formalff.cc
index 264a9fb3be0..0eadb69e0eb 100644
--- a/yosys/passes/sat/formalff.cc
+++ b/yosys/passes/sat/formalff.cc
@@ -237,7 +237,7 @@ struct InitValWorker
 					return true;
 				if (ff.has_ce && initconst(ff.sig_ce.as_bit()) == (ff.pol_ce ? State::S0 : State::S1))
 					continue;
-				if (ff.has_srst && initconst(ff.sig_ce.as_bit()) == (ff.pol_srst ? State::S1 : State::S0))
+				if (ff.has_srst && initconst(ff.sig_srst.as_bit()) == (ff.pol_srst ? State::S1 : State::S0))
 					continue;
 
 				return true;
diff --git a/yosys/passes/sat/recover_names.cc b/yosys/passes/sat/recover_names.cc
index 2d7e7f01cfa..4870e2cac19 100644
--- a/yosys/passes/sat/recover_names.cc
+++ b/yosys/passes/sat/recover_names.cc
@@ -26,16 +26,10 @@
 
 #include <algorithm>
 #include <queue>
+#include <cinttypes>
 
 USING_YOSYS_NAMESPACE
 
-template<> struct hashlib::hash_ops<uint64_t> : hashlib::hash_int_ops
-{
-	static inline unsigned int hash(uint64_t a) {
-		return mkhash((unsigned int)(a), (unsigned int)(a >> 32));
-	}
-};
-
 PRIVATE_NAMESPACE_BEGIN
 
 // xorshift128 params
@@ -453,7 +447,7 @@ struct RecoverNamesWorker {
     pool<IdString> comb_whiteboxes, buffer_types;
 
     // class -> (gold, (gate, inverted))
-    dict<equiv_cls_t, std::pair<pool<IdBit>, dict<IdBit, bool>>> cls2bits; 
+    dict<equiv_cls_t, std::pair<pool<IdBit>, dict<IdBit, bool>>> cls2bits;
 
     void analyse_boxes()
     {
@@ -630,7 +624,7 @@ struct RecoverNamesWorker {
         	if (pop == 1 || pop == (8*sizeof(equiv_cls_t) - 1))
         		continue;
 
-        	log_debug("equivalence class: %016lx\n", cls.first);
+        	log_debug("equivalence class: %016" PRIx64 "\n", cls.first);
             const pool<IdBit> &gold_bits = cls2bits.at(cls.first).first;
             const pool<InvBit> &gate_bits = cls2bits.at(cls.first).second;
             if (gold_bits.empty() || gate_bits.empty())
diff --git a/yosys/passes/sat/sim.cc b/yosys/passes/sat/sim.cc
index 325e123201c..aeed16b9784 100644
--- a/yosys/passes/sat/sim.cc
+++ b/yosys/passes/sat/sim.cc
@@ -25,6 +25,7 @@
 #include "kernel/ff.h"
 #include "kernel/yw.h"
 #include "kernel/json.h"
+#include "kernel/fmt.h"
 
 #include <ctime>
 
@@ -87,6 +88,17 @@ struct TriggeredAssertion {
 	{ }
 };
 
+struct DisplayOutput {
+	int step;
+	SimInstance *instance;
+	Cell *cell;
+	std::string output;
+
+	DisplayOutput(int step, SimInstance *instance, Cell *cell, std::string output) :
+		step(step), instance(instance), cell(cell), output(output)
+	{ }
+};
+
 struct SimShared
 {
 	bool debug = false;
@@ -109,6 +121,9 @@ struct SimShared
 	int next_output_id = 0;
 	int step = 0;
 	std::vector<TriggeredAssertion> triggered_assertions;
+	std::vector<DisplayOutput> display_output;
+	bool serious_asserts = false;
+	bool initstate = true;
 };
 
 void zinit(State &v)
@@ -168,11 +183,39 @@ struct SimInstance
 		Const data;
 	};
 
+	struct print_state_t
+	{
+		bool initial_done;
+		Const past_trg;
+		Const past_en;
+		Const past_args;
+
+		Cell *cell;
+		Fmt fmt;
+
+		std::tuple<bool, SigSpec, Const, int, Cell*> _sort_label() const
+		{
+			return std::make_tuple(
+				cell->getParam(ID::TRG_ENABLE).as_bool(), // Group by trigger
+				cell->getPort(ID::TRG),
+				cell->getParam(ID::TRG_POLARITY),
+				-cell->getParam(ID::PRIORITY).as_int(), // Then sort by descending PRIORITY
+				cell
+			);
+		}
+
+		bool operator<(const print_state_t &other) const
+		{
+			return _sort_label() < other._sort_label();
+		}
+	};
+
 	dict<Cell*, ff_state_t> ff_database;
 	dict<IdString, mem_state_t> mem_database;
 	pool<Cell*> formal_database;
 	pool<Cell*> initstate_database;
 	dict<Cell*, IdString> mem_cells;
+	std::vector<print_state_t> print_database;
 
 	std::vector<Mem> memories;
 
@@ -189,9 +232,13 @@ struct SimInstance
 		log_assert(module);
 
 		if (module->get_blackbox_attribute(true))
-			log_error("Cannot simulate blackbox module %s (instanced at %s).\n",
+			log_error("Cannot simulate blackbox module %s (instantiated at %s).\n",
 					  log_id(module->name), hiername().c_str());
 
+		if (module->has_processes())
+			log_error("Found processes in simulation hierarchy (in module %s at %s). Run 'proc' first.\n",
+					  log_id(module), hiername().c_str());
+
 		if (parent) {
 			log_assert(parent->children.count(instance) == 0);
 			parent->children[instance] = this;
@@ -289,13 +336,27 @@ struct SimInstance
 				if (shared->fst)
 					fst_memories[name] = shared->fst->getMemoryHandles(scope + "." + RTLIL::unescape_id(name));
 			}
-			if (cell->type.in(ID($assert), ID($cover), ID($assume))) {
+
+			if (cell->type.in(ID($assert), ID($cover), ID($assume)))
 				formal_database.insert(cell);
-			}
+
 			if (cell->type == ID($initstate))
 				initstate_database.insert(cell);
+
+			if (cell->type == ID($print)) {
+				print_database.emplace_back();
+				auto &print = print_database.back();
+				print.cell = cell;
+				print.fmt.parse_rtlil(cell);
+				print.past_trg = Const(State::Sx, cell->getPort(ID::TRG).size());
+				print.past_args = Const(State::Sx, cell->getPort(ID::ARGS).size());
+				print.past_en = State::Sx;
+				print.initial_done = false;
+			}
 		}
 
+		std::sort(print_database.begin(), print_database.end());
+
 		if (shared->zinit)
 		{
 			for (auto &it : ff_database)
@@ -519,6 +580,9 @@ struct SimInstance
 			return;
 		}
 
+		if (cell->type == ID($print))
+			return;
+
 		log_error("Unsupported cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
 	}
 
@@ -533,7 +597,7 @@ struct SimInstance
 			Const data = Const(State::Sx, mem.width << port.wide_log2);
 
 			if (port.clk_enable)
-				log_error("Memory %s.%s has clocked read ports. Run 'memory' with -nordff.\n", log_id(module), log_id(mem.memid));
+				log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", log_id(module), log_id(mem.memid));
 
 			if (addr.is_fully_def()) {
 				int addr_int = addr.as_int();
@@ -725,7 +789,31 @@ struct SimInstance
 		return did_something;
 	}
 
-	void update_ph3(bool check_assertions)
+	static void log_source(RTLIL::AttrObject *src)
+	{
+		for (auto src : src->get_strpool_attribute(ID::src))
+			log("    %s\n", src.c_str());
+	}
+
+	void log_cell_w_hierarchy(std::string opening_verbiage, RTLIL::Cell *cell)
+	{
+		log_assert(cell->module == module);
+		bool has_src = cell->has_attribute(ID::src);
+		log("%s %s%s\n", opening_verbiage.c_str(),
+			log_id(cell), has_src ? " at" : "");
+		log_source(cell);
+
+		struct SimInstance *sim = this;
+		while (sim->instance) {
+			has_src = sim->instance->has_attribute(ID::src);
+			log("  in instance %s of module %s%s\n", log_id(sim->instance),
+				log_id(sim->instance->type), has_src ? " at" : "");
+			log_source(sim->instance);
+			sim = sim->parent;
+		}
+	}
+
+	void update_ph3(bool gclk_trigger)
 	{
 		for (auto &it : ff_database)
 		{
@@ -760,7 +848,63 @@ struct SimInstance
 			}
 		}
 
-		if (check_assertions)
+		// Do prints *before* assertions
+		for (auto &print : print_database) {
+			Cell *cell = print.cell;
+			bool triggered = false;
+
+			Const trg = get_state(cell->getPort(ID::TRG));
+			bool trg_en = cell->getParam(ID::TRG_ENABLE).as_bool();
+			Const en = get_state(cell->getPort(ID::EN));
+			Const args = get_state(cell->getPort(ID::ARGS));
+
+			bool sampled = trg_en && trg.size() > 0;
+
+			if (sampled ? print.past_en.as_bool() : en.as_bool()) {
+				if (sampled) {
+					sampled = true;
+					Const trg_pol = cell->getParam(ID::TRG_POLARITY);
+					for (int i = 0; i < trg.size(); i++) {
+						bool pol = trg_pol[i] == State::S1;
+						State curr = trg[i], past = print.past_trg[i];
+						if (pol && curr == State::S1 && past == State::S0)
+							triggered = true;
+						if (!pol && curr == State::S0 && past == State::S1)
+							triggered = true;
+					}
+				} else if (trg_en) {
+					// initial $print (TRG width = 0, TRG_ENABLE = true)
+					if (!print.initial_done && en != print.past_en)
+						triggered = true;
+				} else if (cell->get_bool_attribute(ID(trg_on_gclk))) {
+					// unified $print for cycle based FV semantics
+					triggered = gclk_trigger;
+				} else {
+					// always @(*) $print
+					if (args != print.past_args || en != print.past_en)
+						triggered = true;
+				}
+
+				if (triggered) {
+					int pos = 0;
+					for (auto &part : print.fmt.parts) {
+						part.sig = (sampled ? print.past_args : args).extract(pos, part.sig.size());
+						pos += part.sig.size();
+					}
+
+					std::string rendered = print.fmt.render();
+					log("%s", rendered.c_str());
+					shared->display_output.emplace_back(shared->step, this, cell, rendered);
+				}
+			}
+
+			print.past_trg = trg;
+			print.past_en = en;
+			print.past_args = args;
+			print.initial_done = true;
+		}
+
+		if (gclk_trigger)
 		{
 			for (auto cell : formal_database)
 			{
@@ -781,13 +925,18 @@ struct SimInstance
 				if (cell->type == ID($assume) && en == State::S1 && a != State::S1)
 					log("Assumption %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
 
-				if (cell->type == ID($assert) && en == State::S1 && a != State::S1)
-					log_warning("Assert %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
+				if (cell->type == ID($assert) && en == State::S1 && a != State::S1) {
+					log_cell_w_hierarchy("Failed assertion", cell);
+					if (shared->serious_asserts)
+						log_error("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
+					else
+						log_warning("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
+				}
 			}
 		}
 
 		for (auto it : children)
-			it.second->update_ph3(check_assertions);
+			it.second->update_ph3(gclk_trigger);
 	}
 
 	void set_initstate_outputs(State state)
@@ -1263,6 +1412,8 @@ struct SimWorker : SimShared
 		set_inports(clock, State::Sx);
 		set_inports(clockn, State::Sx);
 
+		top->set_initstate_outputs(initstate ? State::S1 : State::S0);
+
 		update(false);
 
 		register_output_step(0);
@@ -1279,6 +1430,9 @@ struct SimWorker : SimShared
 			update(true);
 			register_output_step(10*cycle + 5);
 
+			if (cycle == 0)
+				top->set_initstate_outputs(State::S0);
+
 			if (debug)
 				log("\n===== %d =====\n", 10*cycle + 10);
 			else if (verbose)
@@ -1860,7 +2014,7 @@ struct SimWorker : SimShared
 		if (yw.steps.empty()) {
 			log_warning("Yosys witness file `%s` contains no time steps\n", yw.filename.c_str());
 		} else {
-			top->set_initstate_outputs(State::S1);
+			top->set_initstate_outputs(initstate ? State::S1 : State::S0);
 			set_yw_state(yw, hierarchy, 0);
 			set_yw_clocks(yw, hierarchy, true);
 			initialize_stable_past();
@@ -1927,6 +2081,20 @@ struct SimWorker : SimShared
 			json.end_object();
 		}
 		json.end_array();
+		json.name("display_output");
+		json.begin_array();
+		for (auto &output : display_output) {
+			json.begin_object();
+			json.entry("step", output.step);
+			json.entry("path", output.instance->witness_full_path(output.cell));
+			auto src = output.cell->get_string_attribute(ID::src);
+			if (!src.empty()) {
+				json.entry("src", src);
+			}
+			json.entry("output", output.output);
+			json.end_object();
+		}
+		json.end_array();
 		json.end_object();
 	}
 
@@ -2453,6 +2621,9 @@ struct SimPass : public Pass {
 		log("    -n <integer>\n");
 		log("        number of clock cycles to simulate (default: 20)\n");
 		log("\n");
+		log("    -noinitstate\n");
+		log("        do not activate $initstate cells during the first cycle\n");
+		log("\n");
 		log("    -a\n");
 		log("        use all nets in VCD/FST operations, not just those with public names\n");
 		log("\n");
@@ -2497,6 +2668,10 @@ struct SimPass : public Pass {
 		log("    -sim-gate\n");
 		log("        co-simulation, x in FST can match any value in simulation\n");
 		log("\n");
+		log("    -assert\n");
+		log("        fail the simulation command if, in the course of simulating,\n");
+		log("        any of the asserts in the design fail\n");
+		log("\n");
 		log("    -q\n");
 		log("        disable per-cycle/sample log message\n");
 		log("\n");
@@ -2549,6 +2724,10 @@ struct SimPass : public Pass {
 				worker.cycles_set = true;
 				continue;
 			}
+			if (args[argidx] == "-noinitstate") {
+				worker.initstate = false;
+				continue;
+			}
 			if (args[argidx] == "-rstlen" && argidx+1 < args.size()) {
 				worker.rstlen = atoi(args[++argidx].c_str());
 				continue;
@@ -2651,6 +2830,10 @@ struct SimPass : public Pass {
 				worker.sim_mode = SimulationMode::gate;
 				continue;
 			}
+			if (args[argidx] == "-assert") {
+				worker.serious_asserts = true;
+				continue;
+			}
 			if (args[argidx] == "-x") {
 				worker.ignore_x = true;
 				continue;
diff --git a/yosys/passes/techmap/Makefile.inc b/yosys/passes/techmap/Makefile.inc
index 1b834fabc3b..74813bca93f 100644
--- a/yosys/passes/techmap/Makefile.inc
+++ b/yosys/passes/techmap/Makefile.inc
@@ -4,6 +4,7 @@ OBJS += passes/techmap/techmap.o
 OBJS += passes/techmap/simplemap.o
 OBJS += passes/techmap/dfflibmap.o
 OBJS += passes/techmap/maccmap.o
+OBJS += passes/techmap/booth.o
 OBJS += passes/techmap/libparse.o
 
 ifeq ($(ENABLE_ABC),1)
@@ -47,6 +48,7 @@ OBJS += passes/techmap/dfflegalize.o
 OBJS += passes/techmap/dffunmap.o
 OBJS += passes/techmap/flowmap.o
 OBJS += passes/techmap/extractinv.o
+OBJS += passes/techmap/cellmatch.o
 endif
 
 ifeq ($(DISABLE_SPAWN),0)
@@ -55,5 +57,5 @@ EXTRA_OBJS += passes/techmap/filterlib.o
 
 $(PROGRAM_PREFIX)yosys-filterlib$(EXE): passes/techmap/filterlib.o
 	$(Q) mkdir -p $(dir $@)
-	$(P) $(LD) -o $(PROGRAM_PREFIX)yosys-filterlib$(EXE) $(LDFLAGS) $^ $(LDLIBS)
+	$(P) $(CXX) -o $(PROGRAM_PREFIX)yosys-filterlib$(EXE) $(LINKFLAGS) $^ $(LIBS)
 endif
diff --git a/yosys/passes/techmap/abc.cc b/yosys/passes/techmap/abc.cc
index 364a8e54458..b33e1a17df4 100644
--- a/yosys/passes/techmap/abc.cc
+++ b/yosys/passes/techmap/abc.cc
@@ -127,10 +127,15 @@ bool clk_polarity, en_polarity, arst_polarity, srst_polarity;
 RTLIL::SigSpec clk_sig, en_sig, arst_sig, srst_sig;
 dict<int, std::string> pi_map, po_map;
 
+int undef_bits_lost;
+
 int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1)
 {
 	assign_map.apply(bit);
 
+	if (bit == State::Sx)
+		undef_bits_lost++;
+
 	if (signal_map.count(bit) == 0) {
 		gate_t gate;
 		gate.id = signal_list.size();
@@ -702,7 +707,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 		std::vector<std::string> &liberty_files, std::vector<std::string> &genlib_files, std::string constr_file,
 		bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target,
 		std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
-		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, bool abc_dress)
+		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, bool abc_dress, std::vector<std::string> &dont_use_cells)
 {
 	module = current_module;
 	map_autoidx = autoidx++;
@@ -795,8 +800,15 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name.c_str());
 
 	if (!liberty_files.empty() || !genlib_files.empty()) {
-		for (std::string liberty_file : liberty_files)
-			abc_script += stringf("read_lib -w \"%s\"; ", liberty_file.c_str());
+		std::string dont_use_args;
+		for (std::string dont_use_cell : dont_use_cells) {
+			dont_use_args += stringf("-X \"%s\" ", dont_use_cell.c_str());
+		}
+		bool first_lib = true;
+		for (std::string liberty_file : liberty_files) {
+			abc_script += stringf("read_lib %s %s -w \"%s\" ; ", dont_use_args.c_str(), first_lib ? "" : "-m", liberty_file.c_str());
+			first_lib = false;
+		}
 		for (std::string liberty_file : genlib_files)
 			abc_script += stringf("read_library \"%s\"; ", liberty_file.c_str());
 		if (!constr_file.empty())
@@ -880,10 +892,15 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 		}
 	}
 
+	undef_bits_lost = 0;
+
 	had_init = false;
 	for (auto c : cells)
 		extract_cell(c, keepff);
 
+	if (undef_bits_lost)
+		log("Replacing %d occurrences of constant undef bits with constant zero bits\n", undef_bits_lost);
+
 	for (auto wire : module->wires()) {
 		if (wire->port_id > 0 || wire->get_bool_attribute(ID::keep))
 			mark_port(wire);
@@ -1503,6 +1520,10 @@ struct AbcPass : public Pass {
 		log("        generate netlists for the specified cell library (using the liberty\n");
 		log("        file format).\n");
 		log("\n");
+		log("    -dont_use <cell_name>\n");
+		log("        generate netlists for the specified cell library (using the liberty\n");
+		log("        file format).\n");
+		log("\n");
 		log("    -genlib <file>\n");
 		log("        generate netlists for the specified cell library (using the SIS Genlib\n");
 		log("        file format).\n");
@@ -1639,7 +1660,7 @@ struct AbcPass : public Pass {
 
 		std::string exe_file = yosys_abc_executable;
 		std::string script_file, default_liberty_file, constr_file, clk_str;
-		std::vector<std::string> liberty_files, genlib_files;
+		std::vector<std::string> liberty_files, genlib_files, dont_use_cells;
 		std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
 		bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
 		bool show_tempdir = false, sop_mode = false;
@@ -1722,6 +1743,10 @@ struct AbcPass : public Pass {
 				liberty_files.push_back(args[++argidx]);
 				continue;
 			}
+			if (arg == "-dont_use" && argidx+1 < args.size()) {
+				dont_use_cells.push_back(args[++argidx]);
+				continue;
+			}
 			if (arg == "-genlib" && argidx+1 < args.size()) {
 				genlib_files.push_back(args[++argidx]);
 				continue;
@@ -2028,7 +2053,7 @@ struct AbcPass : public Pass {
 
 			if (!dff_mode || !clk_str.empty()) {
 				abc_module(design, mod, script_file, exe_file, liberty_files, genlib_files, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
-						delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress);
+						delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress, dont_use_cells);
 				continue;
 			}
 
@@ -2190,7 +2215,7 @@ struct AbcPass : public Pass {
 				srst_polarity = std::get<6>(it.first);
 				srst_sig = assign_map(std::get<7>(it.first));
 				abc_module(design, mod, script_file, exe_file, liberty_files, genlib_files, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
-						keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress);
+						keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress, dont_use_cells);
 				assign_map.set(mod);
 			}
 		}
diff --git a/yosys/passes/techmap/booth.cc b/yosys/passes/techmap/booth.cc
new file mode 100644
index 00000000000..09c20b50712
--- /dev/null
+++ b/yosys/passes/techmap/booth.cc
@@ -0,0 +1,1191 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2023  Andy Fox <andy@rushc.com> https://www.linkedin.com/in/awfox/
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+/*
+  Booth Pass
+  ----------
+
+  Replace $mul with booth encoded multipliers. Two different
+  architectures used for signed/unsigned.
+
+  References:
+  Signed architecture: A Low Power Radix-4 Booth Multipliers with Pre-Encoded Mechanism, IEEE Access
+  https://ieeexplore.ieee.org/document/9121226
+
+  Unsigned architecture: Gary Bewick, Fast Multiplication algorithms and implementation. Stanford PhD:
+  http://i.stanford.edu/pub/cstr/reports/csl/tr/94/617/CSL-TR-94-617.pdf
+
+  How to use:
+  Add booth pass  to your yosys script eg:
+
+  read_verilog smultiply5_rtl.v
+  opt
+  wreduce
+  opt
+  booth
+  alumacc
+  maccmap
+  opt
+  techmap -map ./techmap.v
+  dfflibmap -liberty NangateOpenCellLibrary_typical.lib
+  abc -liberty NangateOpenCellLibrary_typical.lib
+  stat -liberty NangateOpenCellLibrary_typical.lib
+  write_verilog -norename booth_final.v
+
+or in generic synthesis call with -booth argument:
+synth -top my_design -booth
+*/
+
+//FIXME: These debug prints are broken now, should be fixed or removed.
+//#define DEBUG_CPA
+
+#include "kernel/sigtools.h"
+#include "kernel/yosys.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct BoothPassWorker {
+
+	RTLIL::Module *module;
+	SigMap sigmap;
+	int booth_counter;
+	bool lowpower = false;
+	bool mapped_cpa = false;
+
+	BoothPassWorker(RTLIL::Module *module) : module(module), sigmap(module) { booth_counter = 0; }
+
+	// Booth unsigned decoder lsb
+	SigBit Bur4d_lsb(std::string name, SigBit lsb_i, SigBit one_i, SigBit s_i)
+	{
+		SigBit and_op = module->AndGate(NEW_ID_SUFFIX(name), lsb_i, one_i);
+		return module->XorGate(NEW_ID_SUFFIX(name), and_op, s_i);
+	}
+
+	// Booth unsigned radix4 decoder
+	SigBit Bur4d_n(std::string name, SigBit yn_i, SigBit ynm1_i, SigBit one_i, SigBit two_i, SigBit s_i)
+	{
+		// ppij = ((yn & one)   | (ynm1 & two)) ^ s;
+		SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), yn_i, one_i);
+		SigBit an2 = module->AndGate(NEW_ID_SUFFIX(name), ynm1_i, two_i);
+		SigBit or1 = module->OrGate(NEW_ID_SUFFIX(name), an1, an2);
+		return module->XorGate(NEW_ID_SUFFIX(name), s_i, or1);
+	}
+
+	// Booth unsigned radix4 decoder
+	SigBit Bur4d_msb(std::string name, SigBit msb_i, SigBit two_i, SigBit s_i)
+	{
+		// ppij = (msb & two)  ^ s;
+		SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), msb_i, two_i);
+		return module->XorGate(NEW_ID_SUFFIX(name), s_i, an1);
+	}
+
+	// half adder, used in CPA
+	void BuildHa(std::string name, SigBit a_i, SigBit b_i, SigBit &s_o, SigBit &c_o)
+	{
+		s_o = module->XorGate(NEW_ID_SUFFIX(name), a_i, b_i);
+		c_o = module->AndGate(NEW_ID_SUFFIX(name), a_i, b_i);
+	}
+
+	// Booth unsigned radix 4 encoder
+	void BuildBur4e(std::string name, SigBit y0_i, SigBit y1_i, SigBit y2_i,
+			SigBit &one_o, SigBit &two_o, SigBit &s_o, SigBit &sb_o)
+	{
+		one_o = module->XorGate(NEW_ID_SUFFIX(name), y0_i, y1_i);
+		s_o = y2_i;
+		sb_o = module->NotGate(NEW_ID_SUFFIX(name), y2_i);
+		SigBit y1_xnor_y2 = module->XnorGate(NEW_ID_SUFFIX(name), y1_i, y2_i);
+		two_o = module->NorGate(NEW_ID_SUFFIX(name), y1_xnor_y2, one_o);
+	}
+
+	void BuildBr4e(std::string name, SigBit y2_m1_i,
+		       SigBit y2_i, // y2i
+		       SigBit y2_p1_i,
+		       SigBit &negi_o, SigBit &twoi_n_o, SigBit &onei_n_o, SigBit &cori_o)
+	{
+		auto y2_p1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_p1_i);
+		auto y2_n = module->NotGate(NEW_ID_SUFFIX(name), y2_i);
+		auto y2_m1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_m1_i);
+
+		negi_o = y2_p1_i;
+
+		// twoi_n = ~(
+		//    (y2_p1_n & y2_i & y2_m1_i) |
+		//    (y2_p1 & y2_n & y2_m1_n)
+		// )
+		twoi_n_o = module->NorGate(NEW_ID_SUFFIX(name),
+			module->AndGate(NEW_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEW_ID_SUFFIX(name), y2_i, y2_m1_i)),
+			module->AndGate(NEW_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEW_ID_SUFFIX(name), y2_n, y2_m1_n))
+		);
+
+		// onei_n = ~(y2_m1_i ^ y2_i);
+		onei_n_o = module->XnorGate(NEW_ID_SUFFIX(name), y2_m1_i, y2_i);
+		// cori = (y2_m1_n | y2_n) & y2_p1_i;
+		cori_o = module->AndGate(NEW_ID_SUFFIX(name), module->OrGate(NEW_ID_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i);
+	}
+
+	//
+	// signed booth radix 4 decoder
+	//
+	void BuildBr4d(std::string name, SigBit nxj_m1_i, SigBit twoi_n_i, SigBit xj_i, SigBit negi_i, SigBit onei_n_i,
+		       SigBit &ppij_o, SigBit &nxj_o)
+	{
+		// nxj_in = xnor(xj,negi)
+		// nxj_o = xnj_in,
+		// ppij = ~( (nxj_m1_i | twoi_n_i) & (nxj_int | onei_n_i));
+		nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), xj_i, negi_i);
+		ppij_o = module->NandGate(NEW_ID_SUFFIX(name),
+			module->OrGate(NEW_ID_SUFFIX(name), nxj_m1_i, twoi_n_i),
+			module->OrGate(NEW_ID_SUFFIX(name), nxj_o, onei_n_i)
+		);
+	}
+
+	/*
+	  In signed case 1st two bits best realised
+	  using non-booth encoded logic. We can save a booth
+	  encoder for the first couple of bits.
+	*/
+	void BuildBoothQ1(std::string name, SigBit negi_i, SigBit cori_i, SigBit x0_i, SigBit x1_i, SigBit y0_i,
+			  SigBit y1_i,
+			  SigBit &nxj_o, SigBit &cor_o, SigBit &pp0_o, SigBit &pp1_o)
+	{
+		/*
+		  assign NXJO = ~(X1 ^ NEGI);
+		  assign PP0 = (X0 & Y0);
+		  //and terms for multiply
+		  wire pp1_1_int = X1 & Y0;
+		  wire pp1_2_int = X0 & Y1;
+		  //sum generation for pp[1]
+		  assign PP1 = pp1_1_int ^ pp1_2_int;
+		  //correction propagation
+		  assign CORO = (~PP1 & ~PP0)? CORI : 1'b0;
+		*/
+		nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), x1_i, negi_i);
+		pp0_o = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y0_i);
+		SigBit pp1_1_int = module->AndGate(NEW_ID_SUFFIX(name), x1_i, y0_i);
+		SigBit pp1_2_int = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y1_i);
+		pp1_o = module->XorGate(NEW_ID_SUFFIX(name), pp1_1_int, pp1_2_int);
+
+		SigBit pp1_nor_pp0 = module->NorGate(NEW_ID_SUFFIX(name), pp1_o, pp0_o);
+		cor_o = module->AndGate(NEW_ID_SUFFIX(name), pp1_nor_pp0, cori_i);
+	}
+
+	void BuildBitwiseFa(Module *mod, std::string name, const SigSpec &sig_a, const SigSpec &sig_b,
+			    const SigSpec &sig_c, const SigSpec &sig_x, const SigSpec &sig_y,
+			    const std::string &src = "")
+	{
+		// We can't emit a single wide full-adder cell here since
+		// there would typically be feedback loops involving the cells'
+		// input and output ports, and Yosys doesn't cope well with
+		// those
+		log_assert(sig_a.size() == sig_b.size());
+		log_assert(sig_a.size() == sig_c.size());
+		log_assert(sig_a.size() == sig_x.size());
+		log_assert(sig_a.size() == sig_y.size());
+
+		for (int i = 0; i < sig_a.size(); i++)
+			mod->addFa(stringf("%s[%d]", name.c_str(), i), sig_a[i], sig_b[i],
+				   sig_c[i], sig_x[i], sig_y[i], src);
+	}
+
+	void run()
+	{
+		for (auto cell : module->selected_cells()) {
+			if (cell->type != ID($mul))
+				continue;
+
+			SigSpec A = cell->getPort(ID::A);
+			SigSpec B = cell->getPort(ID::B);
+			SigSpec Y = cell->getPort(ID::Y);
+			int x_sz = GetSize(A), y_sz = GetSize(B), z_sz = GetSize(Y);
+
+			if (x_sz < 4 || y_sz < 4 || z_sz < 8) {
+				log_debug("Not mapping cell %s sized at %dx%x, %x: size below threshold\n",
+					  log_id(cell), x_sz, y_sz, z_sz);
+				continue;
+			}
+
+			log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool());
+			bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
+
+			log("Mapping cell %s to %s Booth multiplier\n", log_id(cell), is_signed ? "signed" : "unsigned");
+
+			// To simplify the generator size the arguments
+			// to be the same. Then allow logic synthesis to
+			// clean things up. Size to biggest
+
+			int x_sz_revised = x_sz;
+			int y_sz_revised = y_sz;
+
+			if (x_sz != y_sz) {
+				if (x_sz < y_sz) {
+					if (y_sz % 2 != 0) {
+						x_sz_revised = y_sz + 1;
+						y_sz_revised = y_sz + 1;
+					} else {
+						x_sz_revised = y_sz;
+					}		
+				} else {
+					if (x_sz % 2 != 0) {
+						y_sz_revised = x_sz + 1;
+						x_sz_revised = x_sz + 1;
+					} else {
+						y_sz_revised = x_sz;
+					}
+				}
+			} else {
+				if (x_sz % 2 != 0) {
+					y_sz_revised = y_sz + 1;
+					x_sz_revised = x_sz + 1;
+				}
+			}
+
+			log_assert((x_sz_revised == y_sz_revised) && (x_sz_revised % 2 == 0) && (y_sz_revised % 2 == 0));
+
+
+			A.extend_u0(x_sz_revised, is_signed);
+			B.extend_u0(y_sz_revised, is_signed);
+
+			// Make sure output domain is big enough to take
+			// all combinations.
+			// Later logic synthesis will kill unused
+			// portions of the output domain.
+
+			int required_op_size = x_sz_revised + y_sz_revised;
+
+			if (required_op_size != z_sz) {
+				SigSpec expanded_Y = module->addWire(NEW_ID, required_op_size);
+				SigSpec Y_driver = expanded_Y;
+				Y_driver.extend_u0(Y.size(), is_signed);
+				module->connect(Y, Y_driver);
+				Y = expanded_Y;
+			}
+			log_assert(GetSize(Y) == required_op_size);
+
+			if (!lowpower)
+				CreateBoothMult(module,
+					A, // multiplicand
+					B, // multiplier(scanned)
+					Y, // result
+					is_signed
+				);
+			else
+				CreateBoothLowpowerMult(module,
+					A, // multiplicand
+					B, // multiplier(scanned)
+					Y, // result
+					is_signed
+				);
+
+			module->remove(cell);
+			booth_counter++;
+		}
+	}
+
+	SigSig WallaceSum(int width, std::vector<SigSpec> summands)
+	{
+		for (auto &s : summands)
+			s.extend_u0(width);
+
+		while (summands.size() > 2) {
+			std::vector<SigSpec> new_summands;
+			int i;
+			for (i = 0; i < (int) summands.size() - 2; i += 3) {
+				SigSpec x = module->addWire(NEW_ID, width);
+				SigSpec y = module->addWire(NEW_ID, width);
+				BuildBitwiseFa(module, NEW_ID.str(), summands[i], summands[i + 1],
+					       summands[i + 2], x, y);
+				new_summands.push_back(y);
+				new_summands.push_back({x.extract(0, width - 1), State::S0});
+			}
+
+			new_summands.insert(new_summands.begin(), summands.begin() + i, summands.end());
+
+			std::swap(summands, new_summands);
+		}
+
+		if (!summands.size())
+			return SigSig(SigSpec(width, State::S0), SigSpec(width, State::S0));
+		else if (summands.size() == 1)
+			return SigSig(summands[0], SigSpec(width, State::S0));
+		else
+			return SigSig(summands[0], summands[1]);
+	}
+
+	/*
+	  Build Multiplier.
+	  -------------------------
+	  Uses a generic booth multiplier
+	*/
+
+	void CreateBoothMult(RTLIL::Module *module,
+			      SigSpec X, // multiplicand
+			      SigSpec Y, // multiplier
+			      SigSpec Z,
+			      bool is_signed)
+	{ // result
+		int z_sz = Z.size();
+
+		SigSpec one_int, two_int, s_int, sb_int;
+		int encoder_count = 0;
+
+		BuildBoothMultEncoders(Y, one_int, two_int, s_int, sb_int, module, encoder_count, is_signed);
+
+		// Build the decoder rows
+		// format of each Partial product to be passed to CSA
+		// tree builder:
+		//
+		// Bits to be added
+		// Shift
+		// Sign bit to be added
+		//
+		std::vector<std::tuple<SigSpec, int, SigBit>> ppij_int;
+
+		// Row 0: special case 1. Format S/.S.S.C.Data
+		SigSpec ppij_row_0;
+		BuildBoothMultDecoderRow0(module, X, s_int, sb_int, one_int, two_int, ppij_row_0, is_signed);
+
+		// data, shift, sign
+		ppij_int.push_back(std::make_tuple(ppij_row_0, 0, s_int[0]));
+
+		for (int i = 1; i < encoder_count; i++) {
+			// format 1,S.Data.shift = encoder_ix*2,sign = sb_int[i]
+			SigSpec ppij_row_n;
+
+			BuildBoothMultDecoderRowN(module,
+						   X, // multiplicand
+						   one_int[i], two_int[i], s_int[i], sb_int[i], ppij_row_n, i,
+						   is_signed
+			);
+			// data, shift, sign
+			ppij_int.push_back(std::make_tuple(ppij_row_n, i * 2, s_int[i]));
+		}
+
+
+		//  Debug dump out partial products
+		//  DebugDumpPP(ppij_int);
+
+		// Summation of Partial Products (Wallace Tree)
+		std::vector<SigSpec> aligned_pp;
+		aligned_pp.resize(encoder_count + 1); // make an entirely redundant row
+		// just for sign bit in lsb. (We then filter this out).
+
+		// resize all to be same size as z
+		for (int i = 0; i < encoder_count + 1; i++)
+			aligned_pp[i].extend_u0(z_sz);
+
+		AlignPP(z_sz, ppij_int, aligned_pp);
+
+		// Debug: dump out aligned partial products.
+		// Later on yosys will clean up unused constants
+		//  DebugDumpAlignPP(aligned_pp);
+
+		SigSig wtree_sum = WallaceSum(z_sz, aligned_pp);
+
+		// Debug code: Dump out the csa trees
+		// DumpCSATrees(debug_csa_trees);
+		// Build the CPA to do the final accumulation.
+		log_assert(wtree_sum.second[0] == State::S0);
+		if (mapped_cpa)
+			BuildCPA(module, wtree_sum.first, {State::S0, wtree_sum.second.extract_end(1)}, Z);
+		else
+			module->addAdd(NEW_ID, wtree_sum.first, {wtree_sum.second.extract_end(1), State::S0}, Z);
+	}
+
+	/*
+	  Build Row 0 of decoders
+	*/
+
+	void BuildBoothMultDecoderRow0(RTLIL::Module *module,
+					SigSpec X, // multiplicand
+					SigSpec s_int, SigSpec sb_int, SigSpec one_int,
+					SigSpec two_int, SigSpec &ppij_vec, bool is_signed)
+	{
+		(void)sb_int;
+		(void)module;
+		int x_sz = GetSize(X);
+		SigBit ppij;
+
+		// lsb
+		ppij_vec.append(Bur4d_lsb("row0_lsb_dec", X[0], one_int[0], s_int[0]));
+
+		// 1..xsize -1
+		for (int i = 1; i < x_sz; i++)
+			ppij_vec.append(Bur4d_n(stringf("row0_dec_%d", i), X[i], X[i - 1],
+						one_int[0], two_int[0], s_int[0]));
+
+
+		// The redundant bit. Duplicate decoding of last bit.
+		if (!is_signed) {
+			ppij_vec.append(Bur4d_msb("row0_dec_msb", X.msb(), two_int[0], s_int[0]));
+		} else {
+			ppij_vec.append(Bur4d_n("row0_dec_msb", X.msb(), X.msb(),
+										  one_int[0], two_int[0], s_int[0]));
+		}
+
+		// append the sign bits
+		if (is_signed) {
+			SigBit e = module->XorGate(NEW_ID, s_int[0], module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int[0], one_int[0])));
+			ppij_vec.append({module->NotGate(NEW_ID, e), e, e});
+		} else {
+			// append the sign bits
+			ppij_vec.append({module->NotGate(NEW_ID, s_int[0]), s_int[0], s_int[0]});
+		}
+	}
+
+	// Build a generic row of decoders.
+
+	void BuildBoothMultDecoderRowN(RTLIL::Module *module,
+					SigSpec X, // multiplicand
+					SigSpec one_int, SigSpec two_int, SigSpec s_int, SigSpec sb_int,
+					SigSpec &ppij_vec, int row_ix,
+					bool is_signed)
+	{
+		(void)module;
+		int x_sz = GetSize(X);
+
+		// lsb
+		ppij_vec.append(Bur4d_lsb(stringf("row_%d_lsb_dec", row_ix), X[0], one_int, s_int));
+
+		// core bits
+		for (int i = 1; i < x_sz; i++)
+			ppij_vec.append(Bur4d_n(stringf("row_%d_dec_%d", row_ix, i), X[i], X[i - 1],
+				     		one_int, two_int, s_int));
+
+		if (!is_signed) {			// redundant bit
+			ppij_vec.append(Bur4d_msb("row_dec_red", X[x_sz - 1], two_int, s_int));
+		} else {
+			ppij_vec.append(Bur4d_n(stringf("row_%d_dec_msb", row_ix), X[x_sz - 1], X[x_sz - 1],
+				     					one_int, two_int, s_int));
+		}
+
+		ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEW_ID, sb_int, module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int, one_int))));
+		ppij_vec.append(State::S1);
+	}
+
+	void DebugDumpAlignPP(std::vector<std::vector<RTLIL::Wire *>> &aligned_pp)
+	{
+		printf("Aligned & Padded Partial products\n");
+		int pp_ix = 0;
+		for (auto pp_row : aligned_pp) {
+			printf("PP_%d \t", pp_ix);
+			for (unsigned i = 0; i < pp_row.size(); i++)
+				printf("[%d] %s ", i, pp_row[i] == nullptr ? " 0 " : pp_row[i]->name.c_str());
+			printf("\n");
+			pp_ix++;
+		}
+	}
+
+	// Debug routines to inspect intermediate results
+	void DebugDumpPP(std::vector<std::tuple<std::vector<RTLIL::Wire *>, int, RTLIL::Wire *>> &ppij_int)
+	{
+		printf("Debug dump of partial products\n");
+		int pp_ix = 0;
+
+		for (auto pp : ppij_int) {
+			int shift = get<1>(pp);
+			RTLIL::Wire *sign_bit = get<2>(pp);
+
+			printf("PP %d\n", pp_ix);
+			printf("\tShift %d\n", shift);
+			printf("\tData (0 lsb)\n\t");
+			int ix = 0;
+
+			for (auto pp_wire : get<0>(pp)) {
+				RTLIL::IdString wire_name = pp_wire->name;
+
+				printf(" [%d]:%s ", ix, wire_name.c_str());
+				ix++;
+			}
+			printf("\n");
+			printf("\tSign bit to add in: %s\n", sign_bit->name.c_str());
+
+			pp_ix++;
+		}
+	}
+
+	void DumpCSATrees(std::vector<std::vector<RTLIL::Cell *>> &debug_csa_trees)
+	{
+		int i = 0;
+		for (auto csa_tree : debug_csa_trees) {
+			printf("CSA Tree column %d\n", i);
+			int ix = 0;
+			for (auto csa_elem : csa_tree) {
+				printf("\tCell %d  %s type %s\n", ix, csa_elem->name.c_str(), csa_elem->type.c_str());
+				if (csa_elem->getPort(ID::A) == State::S0)
+					printf("\tA set to constant 0\n");
+				else if (csa_elem->getPort(ID::A) == State::S1)
+					printf("\tA set to constant 1\n");
+				else
+					printf("\tA driven by %s\n", csa_elem->getPort(ID::A).as_wire()->name.c_str());
+
+				if (csa_elem->getPort(ID::B) == State::S0)
+					printf("\tB set to constant 0\n");
+				else if (csa_elem->getPort(ID::B) == State::S1)
+					printf("\tB set to constant 1\n");
+				else
+					printf("\tB driven by %s\n", csa_elem->getPort(ID::B).as_wire()->name.c_str());
+
+				if (csa_elem->getPort(ID::C) == State::S0)
+					printf("\tC set to constant 0\n");
+				else if (csa_elem->getPort(ID::C) == State::S1)
+					printf("\tC set to constant 1\n");
+				else
+					printf("\tC driven by %s\n", csa_elem->getPort(ID::C).as_wire()->name.c_str());
+
+				printf("Carry out: %s\n", csa_elem->getPort(ID::X).as_wire()->name.c_str());
+				printf("Sum out: %s\n", csa_elem->getPort(ID::Y).as_wire()->name.c_str());
+
+				ix++;
+			}
+			i++;
+		}
+	}
+
+	void BuildCSATree(RTLIL::Module *module, std::vector<SigSpec> &bits_to_reduce, SigSpec &s_vec,
+			  SigSpec &c_vec, std::vector<std::vector<RTLIL::Cell *>> &debug_csa_trees)
+	{
+
+		if (!(bits_to_reduce.size() > 0))
+			return;
+
+		int column_size = bits_to_reduce[0].size();
+		int row_size = bits_to_reduce.size();
+		SigSpec carry_bits_to_add_to_next_column;
+
+		for (int column_ix = 0; column_ix < column_size; column_ix++) {
+
+			// get the bits in this column.
+			SigSpec column_bits;
+			for (int row_ix = 0; row_ix < row_size; row_ix++) {
+				if (bits_to_reduce[row_ix][column_ix] != State::S0)
+					column_bits.append(bits_to_reduce[row_ix][column_ix]);
+			}
+			for (auto c : carry_bits_to_add_to_next_column) {
+#ifdef DEBUG_CSA
+				printf("\t Propagating column bit %s to column %d from column %d\n", c->name.c_str(), column_ix, column_ix - 1);
+#endif
+				column_bits.append(c);
+			}
+
+			carry_bits_to_add_to_next_column = {};
+
+#ifdef DEBUG_CSA
+			printf("Column %d Reducing %d bits\n", column_ix, column_bits.size());
+			for (auto b : column_bits) {
+				printf("\t %s\n", b->name.c_str());
+			}
+			printf("\n");
+#endif
+
+			SigBit s, c;
+#ifdef DEBUG_CSA
+			int csa_count_before = debug_csa_trees[column_ix].size();
+#endif
+
+			ReduceBits(module, column_ix, column_bits, s, c, carry_bits_to_add_to_next_column, debug_csa_trees);
+
+			s_vec.append(s);
+			c_vec.append(c);
+
+#ifdef DEBUG_CSA
+			int csa_count_after = debug_csa_trees[column_ix].size();
+
+			printf("Column %d Created %d csa tree elements\n", column_ix, csa_count_after - csa_count_before);
+#endif
+		}
+	}
+
+	/*
+	  Alignment:
+	  ---------
+
+	  Concept traverse from last row.
+	  Pad row by shift
+	  Add sign bit from prior row to 2 bits right of end of data.
+
+	  Example
+
+	  SCDDDDDDD- +S
+	  DDDDDDDD_
+
+	  ==>
+	  SCDDDDDDD-
+	  DDDDDDDD_S <-- prior rows sign bit added 2 columns to right on next row.
+
+	  Pad out rows with zeros and left the opt pass clean them up.
+
+	*/
+	void AlignPP(int z_sz, std::vector<std::tuple<SigSpec, int, SigBit>> &ppij_int,
+		     std::vector<SigSpec> &aligned_pp)
+	{
+		unsigned aligned_pp_ix = aligned_pp.size() - 1;
+
+		// default is zero for everything (so don't have to think to hard
+		// about padding).
+
+		for (unsigned i = 0; i < aligned_pp.size(); i++) {
+			for (int j = 0; j < z_sz; j++) {
+				aligned_pp[i][j] = State::S0;
+			}
+		}
+
+		// for very last row we just have the sign bit
+		// Note that the aligned_pp is one row bigger
+		// than the ppij_int. We put the sign bit
+		// in first column of the last partial product
+		// which is at index corresponding to size of multiplicand
+		{
+			int prior_row_idx = get<1>(ppij_int[aligned_pp_ix - 1]);
+			SigBit prior_row_sign = get<2>(ppij_int[aligned_pp_ix - 1]);
+			if (prior_row_idx < z_sz)
+				aligned_pp[aligned_pp_ix][prior_row_idx] = prior_row_sign;
+		}
+
+		for (int row_ix = aligned_pp_ix - 1; row_ix >= 0; row_ix--) {
+			int shift_amount = get<1>(ppij_int[row_ix]);
+
+			// copy in data
+			int copy_ix = shift_amount;
+			for (auto w : get<0>(ppij_int[row_ix])) {
+				if (copy_ix < aligned_pp[row_ix].size()) {
+					aligned_pp[row_ix][copy_ix] = w;
+				}
+				copy_ix++;
+			}
+
+			// copy in the sign bit from the prior row
+			if (row_ix > 0) {
+				// if sign bit on prior row, copy in
+				// the destination of the sign bit is the (row_ix -1)*2
+				// eg destination for sign bit for row 0 is 0.
+				// eg destination for sign bit for row 1 is 1
+				SigBit prior_row_sign = get<2>(ppij_int[row_ix - 1]);
+				copy_ix = (row_ix - 1) * 2;
+				aligned_pp[row_ix][copy_ix] = prior_row_sign;
+			}
+		}
+	}
+
+	/*
+	  Build a Carry Propagate Adder
+	  -----------------------------
+	  First build the sum and carry vectors to be added.
+	*/
+	void BuildCPA(RTLIL::Module *module, SigSpec s_vec, SigSpec c_vec, SigSpec result)
+	{
+		static int cpa_id;
+		cpa_id++;
+
+		log_assert(c_vec.size() == s_vec.size());
+		log_assert(result.size() == s_vec.size());
+
+		SigBit carry;
+		for (int n = 0; n < s_vec.size(); n++) {
+			std::string carry_name;
+
+			// Base Case: Bit 0 is sum 0
+			if (n == 0) {
+				module->addBufGate(NEW_ID_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]);
+
+#ifdef DEBUG_CPA
+				printf("CPA bit [%d] Cell %s IP 0 %s \n", n, buf->name.c_str(), s_vec[0]->name.c_str());
+#endif
+			}
+
+			//
+			// Base Case
+			// c,s = ha(s_vec[1],c_vec[0])
+			//
+			else if (n == 1) {
+				std::string ha_name = "cpa_" + std::to_string(cpa_id) + "_ha_" + std::to_string(n);
+				SigBit ha_op;
+				BuildHa(ha_name, s_vec[n], c_vec[n - 1], ha_op, carry);
+				module->connect(result[n], ha_op);
+
+#ifdef DEBUG_CPA
+				printf("CPA bit [%d] Cell %s IPs [%s] [%s] \n", n, ha_cell->name.c_str(), s_vec[n]->name.c_str(),
+				       c_vec[n - 1]->name.c_str());
+#endif
+
+			}
+			// End Case
+			else if (n == s_vec.size() - 1) {
+				// Make the carry results.. Two extra bits after fa.
+				SigBit carry_out = module->addWire(NEW_ID, 1);
+				module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
+					/* A */ s_vec[n],
+					/* B */ c_vec[n - 1],
+					/* C */ carry,
+					/* X */ carry_out,
+					/* Y */ result[n]
+				);
+				carry = carry_out;
+
+#ifdef DEBUG_CPA
+				printf("CPA bit [%d] Cell %s IPs [%s] [%s] [%s]\n", n, fa_cell->name.c_str(), s_vec[n]->name.c_str(),
+				       c_vec[n - 1]->name.c_str(), carry->name.c_str());
+#endif
+				if (n + 1 < GetSize(result)) {
+					// Now make a half adder: c_vec[n] = carry
+					std::string ha_name = "cpa_" + std::to_string(cpa_id) + "_ha_" + std::to_string(n);
+					SigBit ha_sum;
+					SigBit ha_carry;
+					BuildHa(ha_name, c_vec[n], carry, ha_sum, ha_carry);
+					if (n + 1 < GetSize(result))
+						module->connect(result[n + 1], ha_sum);
+					if (n + 2 < GetSize(result))
+						module->connect(result[n + 2], ha_carry);
+				}
+			}
+			// Step case
+			else {
+				SigBit carry_out = module->addWire(NEW_ID_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1);
+				module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
+					/* A */ s_vec[n],
+					/* B */ c_vec[n - 1],
+					/* C */ carry,
+					/* X */ carry_out,
+					/* Y */ result[n]
+				);
+				carry = carry_out;
+#ifdef DEBUG_CPA
+				printf("CPA bit [%d] Cell %s IPs [%s] [%s] [%s]\n", n, fa_cell->name.c_str(), s_vec[n]->name.c_str(),
+				       c_vec[n - 1]->name.c_str(), carry->name.c_str());
+#endif
+			}
+		}
+	}
+
+	// Sum the bits in the current column
+	// Pass the carry bits from each csa to the next
+	// column for summation.
+
+	void ReduceBits(RTLIL::Module *module, int column_ix, SigSpec column_bits, SigBit &s_result, SigBit &c_result,
+			SigSpec &carry_bits_to_sum, std::vector<std::vector<RTLIL::Cell *>> &debug_csa_trees)
+	{
+
+		int csa_ix = 0;
+		int column_size = column_bits.size();
+
+		if (column_size > 0) {
+			int var_ix = 0;
+			SigSpec first_csa_ips;
+			// get the first 3 inputs, if possible
+			for (var_ix = 0; var_ix < column_bits.size() && first_csa_ips.size() != 3; var_ix++) {
+				if (column_bits[var_ix] != State::S0)
+					first_csa_ips.append(column_bits[var_ix]);
+			}
+
+			if (first_csa_ips.size() > 0) {
+				// build the first csa
+				auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
+				auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
+
+				auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
+					/* A */ first_csa_ips[0],
+					/* B */ first_csa_ips.size() > 1 ? first_csa_ips[1] : State::S0,
+					/* C */ first_csa_ips.size() > 2 ? first_csa_ips[2] : State::S0,
+					/* X */ c_wire,
+					/* Y */ s_wire
+				);
+
+				s_result = s_wire;
+				c_result = c_wire;
+
+				debug_csa_trees[column_ix].push_back(csa);
+				csa_ix++;				
+
+				if (var_ix <= column_bits.size() - 1)
+					carry_bits_to_sum.append(c_wire);
+
+				// Now build the rest of the tree if we can
+				while (var_ix <= column_bits.size() - 1) {
+					SigSpec csa_ips;
+					// get the next two variables to sum
+					for (; var_ix <= column_bits.size() - 1 && csa_ips.size() < 2;) {
+						// skip any empty bits
+						if (column_bits[var_ix] != State::S0)
+							csa_ips.append(column_bits[var_ix]);
+						var_ix++;
+					}
+
+					if (csa_ips.size() > 0) {
+						auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
+						auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
+
+						auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
+							/* A */ s_result,
+							/* B */ csa_ips[0],
+							/* C */ csa_ips.size() > 1 ? csa_ips[1] : State::S0,
+							/* X */ c_wire,
+							/* Y */ s_wire
+						);
+
+						debug_csa_trees[column_ix].push_back(csa);
+						csa_ix++;
+
+						if (var_ix <= column_bits.size() - 1)
+							carry_bits_to_sum.append(c_wire);
+
+						s_result = s_wire;
+						c_result = c_wire;
+					}
+				}
+			}
+		}
+	}
+
+	void BuildBoothMultEncoders(SigSpec Y, SigSpec &one_int, SigSpec &two_int,
+				     SigSpec &s_int, SigSpec &sb_int, RTLIL::Module *module, int &encoder_ix, bool is_signed)
+	{
+		int y_sz = GetSize(Y);
+
+		for (int y_ix = 0; y_ix < (!is_signed ? y_sz : y_sz - 1);) {
+			std::string enc_name = stringf("bur_enc_%d", encoder_ix);
+
+			two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
+			one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
+			s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
+			sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
+
+			if (y_ix == 0) {
+				BuildBur4e(enc_name, State::S0, Y[y_ix],
+					   Y[y_ix + 1], one_int[encoder_ix], two_int[encoder_ix], s_int[encoder_ix],
+					   sb_int[encoder_ix]);
+
+				y_ix = y_ix + 1;
+				encoder_ix++;
+			} else {
+				//
+				// step case. If multiplier ends on a boundary
+				// then add an extra booth encoder bounded by
+				// zeroes to ensure unsigned works.
+				//
+				SigBit y0, y1, y2;
+
+				bool need_padded_cell = false;
+
+				if (y_ix > y_sz - 1) {
+					y0 = is_signed ? Y.msb() : State::S0;
+					need_padded_cell = false;
+				} else {
+					y0 = Y[y_ix];
+					y_ix++;
+				}
+
+				if (y_ix > y_sz - 1) {
+					need_padded_cell = false;
+					y1 = is_signed ? Y.msb() : State::S0;
+				} else {
+					y1 = Y[y_ix];
+					y_ix++;
+				}
+
+				if (y_ix > y_sz - 1) {
+					need_padded_cell = false;
+					y2 = is_signed ? Y.msb() : State::S0;
+				} else {
+					if (y_ix == y_sz - 1)
+						need_padded_cell = !is_signed;
+					else
+						need_padded_cell = false;
+					y2 = Y[y_ix];
+
+					BuildBur4e(enc_name, y0, y1, y2, one_int[encoder_ix], two_int[encoder_ix], s_int[encoder_ix],
+						   sb_int[encoder_ix]);
+				}
+
+				encoder_ix++;
+
+				if (need_padded_cell == true) {
+					// make extra encoder cell
+					// y_ix at y0, rest 0
+
+					std::string enc_name = stringf("br_enc_pad_%d", encoder_ix);
+
+					two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
+					one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
+					s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
+					sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
+
+					SigBit one_o_int, two_o_int, s_o_int, sb_o_int;
+					BuildBur4e(enc_name, Y[y_ix], State::S0,
+						   State::S0, one_o_int, two_o_int, s_o_int, sb_o_int);
+
+					module->connect(one_int[encoder_ix], one_o_int);
+					module->connect(two_int[encoder_ix], two_o_int);
+					module->connect(s_int[encoder_ix], s_o_int);
+					module->connect(sb_int[encoder_ix], sb_o_int);
+					y_ix++;
+					encoder_ix++;
+				}
+			}
+		}
+	}
+
+	/*
+	  Low-power Multiplier
+	*/
+	void CreateBoothLowpowerMult(RTLIL::Module *module, SigSpec X, SigSpec Y, SigSpec Z, bool is_signed)
+	{ // product
+		int x_sz = X.size(), y_sz = Y.size(), z_sz = Z.size();
+
+		if (!is_signed)
+			log_error("Low-power Booth architecture is only supported on signed multipliers.\n");
+
+		unsigned enc_count = (y_sz / 2) + (((y_sz % 2) != 0) ? 1 : 0);
+		int dec_count = x_sz + 1;
+
+		int fa_count = x_sz + 4;
+		int fa_row_count = enc_count - 1;
+
+		log_debug("Mapping %d x %d -> %d multiplier: %d encoders %d decoders\n", x_sz, y_sz, z_sz, enc_count, dec_count);
+
+		SigSpec negi_n_int, twoi_n_int, onei_n_int, cori_n_int;
+
+		negi_n_int.extend_u0(enc_count);
+		twoi_n_int.extend_u0(enc_count);
+		onei_n_int.extend_u0(enc_count);
+		cori_n_int.extend_u0(enc_count);
+
+		for (unsigned encoder_ix = 1; encoder_ix <= enc_count; encoder_ix++) {
+			std::string enc_name = stringf("enc_%d", encoder_ix);
+			negi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1);
+			twoi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1);
+			onei_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1);
+			cori_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1);
+
+			if (encoder_ix == 1) {
+				BuildBr4e(enc_name, State::S0, Y[0], Y[1],
+					  negi_n_int[encoder_ix - 1], twoi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1],
+					  cori_n_int[encoder_ix - 1]);
+
+			} else {
+				SigBit y1, y2, y3;
+
+				y1 = Y[(encoder_ix - 1) * 2 - 1];
+
+				if ((encoder_ix - 1) * 2 >= (unsigned)y_sz)
+					y2 = State::S0; // constant 0
+				else
+					y2 = Y[(encoder_ix - 1) * 2]; // 0
+
+				if (((encoder_ix - 1) * 2 + 1) >= (unsigned)y_sz)
+					y3 = State::S0; // constant 0
+				else
+					y3 = Y[(encoder_ix - 1) * 2 + 1]; //+1
+
+				BuildBr4e(enc_name, y1, y2, y3,
+					  negi_n_int[encoder_ix - 1], twoi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1],
+					  cori_n_int[encoder_ix - 1]);
+			}
+		}
+
+		// Decoders and PP generation
+		SigSpec PPij(State::S0, enc_count * dec_count);
+		SigSpec nxj(State::S0, enc_count * dec_count);
+
+		for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) {
+			for (int decoder_ix = 1; decoder_ix <= dec_count; decoder_ix++) {
+				PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1] =
+					module->addWire(NEW_ID_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1);
+
+				nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1] =
+					module->addWire(NEW_ID_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "",
+									      encoder_ix, decoder_ix)), 1);
+			}
+		}
+
+		//
+		// build decoder array
+		//
+		for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) {
+			// pre-decoder
+			std::string pre_dec_name = "pre_dec_" + std::to_string(encoder_ix) + "_";
+
+			if (encoder_ix == 1) {
+				// quadrant 1 optimization
+			} else {
+				module->addNotGate(NEW_ID_SUFFIX(stringf("pre_dec_%d", encoder_ix)),
+					negi_n_int[encoder_ix - 1],
+					nxj[(encoder_ix - 1) * dec_count]
+				);
+			}
+
+			for (int decoder_ix = 1; decoder_ix < dec_count; decoder_ix++) {
+				// range 1..8
+
+				// quadrant 1 optimization.
+				if ((decoder_ix == 1 || decoder_ix == 2) && encoder_ix == 1)
+					continue;
+
+				std::string dec_name = stringf("dec_%d_%d", encoder_ix, decoder_ix);
+				BuildBr4d(dec_name, nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1], twoi_n_int[encoder_ix - 1],
+					  X[decoder_ix - 1], negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1],
+					  PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1], nxj[((encoder_ix - 1) * dec_count) + decoder_ix]);
+			}
+
+			// duplicate end for sign fix
+			// applies to 9th decoder (xsz+1 decoder).
+			std::string dec_name = stringf("dec_%d_%d", encoder_ix, x_sz + 1);
+			SigBit unused_op;
+			BuildBr4d(dec_name, nxj[((encoder_ix - 1) * dec_count) + dec_count - 1], twoi_n_int[encoder_ix - 1],
+				  X[dec_count - 2], negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1],
+				  PPij[((encoder_ix - 1) * dec_count) + dec_count - 1], unused_op);
+		}
+
+		//
+		// instantiate the quadrant 1 cell. This is the upper right
+		// quadrant which can be realized using non-booth encoded logic.
+		//
+		SigBit pp0_o_int, pp1_o_int, nxj_o_int, q1_carry_out;
+
+		BuildBoothQ1("icb_booth_q1_",
+			     negi_n_int[0], // negi
+			     cori_n_int[0], // cori
+			     X[0], X[1], Y[0], Y[1],
+			     nxj_o_int, q1_carry_out, pp0_o_int, pp1_o_int);
+
+		module->connect(Z[0], pp0_o_int);
+		module->connect(Z[1], pp1_o_int);
+		module->connect(nxj[(0 * dec_count) + 2], nxj_o_int);
+
+		//
+		// sum up the partial products
+		//
+		int fa_row_ix = 0;
+		std::vector<SigSpec> fa_sum;
+		std::vector<SigSpec> fa_carry;
+
+		for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) {
+			fa_sum.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count));
+			fa_carry.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count));
+		}
+
+		// full adder creation
+		// base case: 1st row: Inputs from decoders
+		// 1st row exception: two localized inverters due to sign extension structure
+		SigBit d08_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]);
+		SigBit d18_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]);
+		BuildBitwiseFa(module, NEW_ID_SUFFIX("fa_row_0").str(),
+			/* A */ {State::S0, d08_inv, PPij[(0 * dec_count) + x_sz], PPij.extract((0 * dec_count) + 2, x_sz - 1)},
+			/* B */ {State::S1, d18_inv, PPij.extract((1 * dec_count), x_sz)},
+			/* C */ fa_carry[0].extract(1, x_sz + 2),
+			/* X */ fa_carry[0].extract(2, x_sz + 2),
+			/* Y */ fa_sum[0].extract(2, x_sz + 2)
+		);
+		module->connect(fa_carry[0][1], q1_carry_out);
+
+		// step case: 2nd and rest of rows. (fa_row_ix == 1...n)
+		// special because these are driven by a decoder and prior fa.
+		for (fa_row_ix = 1; fa_row_ix < fa_row_count; fa_row_ix++) {
+			// end two bits: sign extension
+			SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)),
+						       PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]);
+
+			BuildBitwiseFa(module, NEW_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(),
+				/* A */	{State::S0, fa_carry[fa_row_ix - 1][fa_count - 1], fa_sum[fa_row_ix - 1].extract(2, x_sz + 2)},
+				/* B */ {State::S1, d_inv, PPij.extract((fa_row_ix + 1) * dec_count, x_sz), State::S0, State::S0},
+
+				/* C */ {fa_carry[fa_row_ix].extract(0, x_sz + 3), cori_n_int[fa_row_ix]},
+				/* X */ fa_carry[fa_row_ix],
+				/* Y */ fa_sum[fa_row_ix]
+			);
+		}
+
+		// instantiate the cpa
+		SigSpec cpa_carry;
+		if (z_sz > fa_row_count * 2)
+			cpa_carry = module->addWire(NEW_ID_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2);
+
+		// The end case where we pass the last two summands
+		// from prior row directly to product output
+		// without using a cpa cell. This is always
+		// 0,1 index of prior fa row
+		for (int cpa_ix = 0; cpa_ix < fa_row_count * 2; cpa_ix += 2) {
+			int fa_row_ix = cpa_ix / 2;
+			module->connect(Z.extract(cpa_ix, 2), fa_sum[fa_row_ix].extract(0, 2));
+		}
+
+		for (int cpa_ix = fa_row_count * 2; cpa_ix < z_sz; cpa_ix++) {
+			int offset = fa_row_count * 2;
+			std::string cpa_name = stringf("cpa_%d", cpa_ix - offset);
+
+			SigBit ci = (cpa_ix == offset) ? cori_n_int[enc_count - 1] : cpa_carry[cpa_ix - offset - 1];
+			SigBit op;
+			BuildHa(cpa_name, fa_sum[fa_row_count - 1][cpa_ix - offset + 2], ci, op, cpa_carry[cpa_ix - offset]);
+			module->connect(Z[cpa_ix], op);
+		}
+	}
+};
+
+struct BoothPass : public Pass {
+	BoothPass() : Pass("booth", "map $mul cells to Booth multipliers") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    booth [selection]\n");
+		log("\n");
+		log("This pass replaces multiplier cells with a radix-4 Booth-encoded implementation.\n");
+		log("It operates on $mul cells whose width of operands is at least 4x4 and whose\n");
+		log("width of result is at least 8.\n");
+		log("\n");
+		log("    -lowpower\n");
+		log("        use an alternative low-power architecture for the generated multiplier\n");
+		log("        (signed multipliers only)\n");
+		log("\n");
+	}
+	void execute(vector<string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing BOOTH pass (map to Booth multipliers).\n");
+
+		size_t argidx;
+		bool mapped_cpa = false;
+		bool lowpower = false;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-mapped_cpa")
+				// Have an undocumented option which helps with multiplier
+				// verification using specialized tools (AMulet2 in particular)
+				mapped_cpa = true;
+			else if (args[argidx] == "-lowpower")
+				lowpower = true;
+			else
+				break;
+		}
+		extra_args(args, argidx, design);
+
+		int total = 0;
+
+		for (auto mod : design->selected_modules()) {
+			if (!mod->has_processes_warn()) {
+				BoothPassWorker worker(mod);
+				worker.mapped_cpa = mapped_cpa;
+				worker.lowpower = lowpower;
+				worker.run();
+				total += worker.booth_counter;
+			}
+		}
+
+		log("Mapped %d multipliers.\n", total);
+	}
+} MultPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/yosys/passes/techmap/cellmatch.cc b/yosys/passes/techmap/cellmatch.cc
new file mode 100644
index 00000000000..a21a4fbadc2
--- /dev/null
+++ b/yosys/passes/techmap/cellmatch.cc
@@ -0,0 +1,312 @@
+#include "kernel/celltypes.h"
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
+#include "kernel/sigtools.h"
+#include "kernel/consteval.h"
+#include "kernel/utils.h"
+
+#include <algorithm>
+
+USING_YOSYS_NAMESPACE
+YOSYS_NAMESPACE_BEGIN
+
+// return module's inputs in canonical order
+SigSpec module_inputs(Module *m)
+{
+	SigSpec ret;
+	for (auto port : m->ports) {
+		Wire *w = m->wire(port);
+		if (!w->port_input)
+			continue;
+		if (w->width != 1)
+			log_error("Unsupported wide port (%s) of non-unit width found in module %s.\n",
+					  log_id(w), log_id(m));
+		ret.append(w);
+	}
+	return ret;
+}
+
+// return module's outputs in canonical order
+SigSpec module_outputs(Module *m)
+{
+	SigSpec ret;
+	for (auto port : m->ports) {
+		Wire *w = m->wire(port);
+		if (!w->port_output)
+			continue;
+		if (w->width != 1)
+			log_error("Unsupported wide port (%s) of non-unit width found in module %s.\n",
+					  log_id(w), log_id(m));
+		ret.append(w);
+	}
+	return ret;
+}
+
+// Permute the inputs of a single-output k-LUT according to varmap
+uint64_t permute_lut(uint64_t lut, const std::vector<int> &varmap)
+{
+	int k = varmap.size();
+	uint64_t ret = 0;
+	// Index j iterates over all bits in lut.
+	// When (j & 1 << n) is true,
+	//  (lut & 1 << j) represents an output value where input var n is set.
+	// We use this fact to permute the LUT such that
+	// every variable n is remapped to varmap[n].
+	for (int j = 0; j < 1 << k; j++) {
+		int m = 0;
+		for (int l = 0; l < k; l++)
+		if (j & 1 << l)
+			m |= 1 << varmap[l];
+		if (lut & 1 << m)
+			ret |= 1 << j;
+	}
+	return ret;
+}
+
+// Find the LUT with the minimum integer representation
+// such that it is a permutation of the given lut.
+// The resulting LUT becomes the "fingerprint" of the "permutation class".
+// This function checks all possible input permutations.
+uint64_t p_class(int k, uint64_t lut)
+{
+	std::vector<int> map;
+	for (int j = 0; j < k; j++)
+		map.push_back(j);
+
+	uint64_t repr = ~(uint64_t) 0;
+	std::vector<int> repr_vars;
+	while (true) {
+		uint64_t perm = permute_lut(lut, map);
+		if (perm <= repr) {
+			repr = perm;
+			repr_vars = map;
+		}
+		if (!std::next_permutation(map.begin(), map.end()))
+			break;
+	}
+	return repr;
+}
+
+// Represent module m as N single-output k-LUTs
+// where k is the number of module inputs,
+//   and N is the number of module outputs.
+bool derive_module_luts(Module *m, std::vector<uint64_t> &luts)
+{
+	CellTypes ff_types;
+	ff_types.setup_stdcells_mem();
+	for (auto cell : m->cells()) {
+		if (ff_types.cell_known(cell->type)) {
+			log("Ignoring module '%s' which isn't purely combinational.\n", log_id(m));
+			return false;
+		}
+	}
+
+	SigSpec inputs = module_inputs(m);
+	SigSpec outputs = module_outputs(m);
+	int ninputs = inputs.size(), noutputs = outputs.size();
+
+	if (ninputs > 6) {
+		log_warning("Skipping module %s with more than 6 inputs bits.\n", log_id(m));
+		return false;
+	}
+
+	luts.clear();
+	luts.resize(noutputs);
+
+	ConstEval ceval(m);
+	for (int i = 0; i < 1 << ninputs; i++) {
+		ceval.clear();
+		for (int j = 0; j < ninputs; j++)
+			ceval.set(inputs[j], (i & (1 << j)) ? State::S1 : State::S0);
+		for (int j = 0; j < noutputs; j++) {
+			SigSpec bit = outputs[j];
+
+			if (!ceval.eval(bit)) {
+				log("Failed to evaluate output '%s' in module '%s'.\n",
+					log_signal(outputs[j]), log_id(m));
+				return false;
+			}
+
+			log_assert(ceval.eval(bit));
+
+			if (bit[0] == State::S1)
+				luts[j] |= 1 << i;
+		}
+	}
+
+	return true;
+}
+
+struct CellmatchPass : Pass {
+	CellmatchPass() : Pass("cellmatch", "match cells to their targets in cell library") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    cellmatch -lib <design> [module selection]\n");
+		log("\n");
+		log("This pass identifies functionally equivalent counterparts between each of the\n");
+		log("selected modules and a module from the secondary design <design>. For every such\n");
+		log("correspondence found, a techmap rule is generated for mapping instances of the\n");
+		log("former to instances of the latter. This techmap rule is saved in yet another\n");
+		log("design called '$cellmatch', which is created if non-existent.\n");
+		log("\n");
+		log("This pass restricts itself to combinational modules. Modules are functionally\n");
+		log("equivalent as long as their truth tables are identical upto a permutation of\n");
+		log("inputs and outputs. The supported number of inputs is limited to 6.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *d) override
+	{
+		log_header(d, "Executing CELLMATCH pass. (match cells)\n");
+
+		size_t argidx;
+		bool lut_attrs = false;
+		Design *lib = NULL;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-lut_attrs") {
+				// an undocumented debugging option
+				lut_attrs = true;
+			} else if (args[argidx] == "-lib" && argidx + 1 < args.size()) {
+				if (!saved_designs.count(args[++argidx]))
+					log_cmd_error("No design '%s' found!\n", args[argidx].c_str());
+				lib = saved_designs.at(args[argidx]);
+			} else {
+				break;
+			}
+		}
+		extra_args(args, argidx, d);
+
+		if (!lib && !lut_attrs)
+			log_cmd_error("Missing required -lib option.\n");
+
+		struct Target {
+			Module *module;
+			std::vector<uint64_t> luts;
+		};
+
+		dict<pool<uint64_t>, std::vector<Target>> targets;
+
+		if (lib)
+		for (auto m : lib->modules()) {
+			pool<uint64_t> p_classes;
+
+			// produce a fingerprint in p_classes
+			int ninputs = module_inputs(m).size();
+			std::vector<uint64_t> luts;
+			if (!derive_module_luts(m, luts))
+				continue;
+			for (auto lut : luts)
+				p_classes.insert(p_class(ninputs, lut));
+
+			log_debug("Registered %s\n", log_id(m));
+
+			// save as a viable target
+			targets[p_classes].push_back(Target{m, luts});
+		}
+
+		auto r = saved_designs.emplace("$cellmatch", nullptr);
+		if (r.second)
+			r.first->second = new Design;
+		Design *map_design = r.first->second;
+
+		for (auto m : d->selected_whole_modules_warn()) {
+			std::vector<uint64_t> luts;
+			if (!derive_module_luts(m, luts))
+				continue;
+
+			SigSpec inputs = module_inputs(m);
+			SigSpec outputs = module_outputs(m);
+
+			if (lut_attrs) {
+				int no = 0;
+				for (auto bit : outputs) {
+					log_assert(bit.is_wire());
+					bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]);
+					bit.wire->attributes[ID(lut)] = luts[no++];
+				}
+			}
+
+			// fingerprint
+			pool<uint64_t> p_classes;
+			for (auto lut : luts)
+				p_classes.insert(p_class(inputs.size(), lut));
+
+			for (auto target : targets[p_classes]) {
+				log_debug("Candidate %s for matching to %s\n", log_id(target.module), log_id(m));
+
+				SigSpec target_inputs = module_inputs(target.module);
+				SigSpec target_outputs = module_outputs(target.module);
+
+				if (target_inputs.size() != inputs.size())
+					continue;
+
+				if (target_outputs.size() != outputs.size())
+					continue;
+
+				std::vector<int> input_map;
+				for (int i = 0; i < inputs.size(); i++)
+					input_map.push_back(i);
+
+				bool found_match = false;
+				// For each input_map
+				while (!found_match) {
+					std::vector<int> output_map;
+					for (int i = 0; i < outputs.size(); i++)
+						output_map.push_back(i);
+
+					// For each output_map
+					while (!found_match) {
+						int out_no = 0;
+						bool match = true;
+						for (auto lut : luts) {
+							if (permute_lut(target.luts[output_map[out_no++]], input_map) != lut) {
+								match = false;
+								break;
+							}
+						}
+
+						if (match) {
+							log("Module %s matches %s\n", log_id(m), log_id(target.module));
+							// Add target.module to map_design ("$cellmatch")
+							// as a techmap rule to match m and replace it with target.module
+							Module *map = map_design->addModule(stringf("\\_60_%s_%s", log_id(m), log_id(target.module)));
+							Cell *cell = map->addCell(ID::_TECHMAP_REPLACE_, target.module->name);
+
+							map->attributes[ID(techmap_celltype)] = m->name.str();
+
+							for (int i = 0; i < outputs.size(); i++) {
+								log_assert(outputs[i].is_wire());
+								Wire *w = map->addWire(outputs[i].wire->name, 1);
+								w->port_id = outputs[i].wire->port_id;
+								w->port_output = true;
+								log_assert(target_outputs[output_map[i]].is_wire());
+								cell->setPort(target_outputs[output_map[i]].wire->name, w);
+							}
+
+							for (int i = 0; i < inputs.size(); i++) {
+								log_assert(inputs[i].is_wire());
+								Wire *w = map->addWire(inputs[i].wire->name, 1);
+								w->port_id = inputs[i].wire->port_id;
+								w->port_input = true;
+								log_assert(target_inputs[input_map[i]].is_wire());
+								cell->setPort(target_inputs[input_map[i]].wire->name, w);
+							}
+
+							map->fixup_ports();
+							found_match = true;
+						}
+
+						if (!std::next_permutation(output_map.begin(), output_map.end()))
+							break;
+					}
+
+					if (!std::next_permutation(input_map.begin(), input_map.end()))
+						break;
+				}
+			}
+		}
+	}
+} CellmatchPass;
+
+YOSYS_NAMESPACE_END
diff --git a/yosys/passes/techmap/dfflibmap.cc b/yosys/passes/techmap/dfflibmap.cc
index 12c3a95de89..78bfe1586ff 100644
--- a/yosys/passes/techmap/dfflibmap.cc
+++ b/yosys/passes/techmap/dfflibmap.cc
@@ -115,7 +115,7 @@ static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name,
 	return false;
 }
 
-static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval)
+static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, std::vector<std::string> &dont_use_cells)
 {
 	LibertyAst *best_cell = nullptr;
 	std::map<std::string, char> best_cell_ports;
@@ -135,6 +135,18 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has
 		if (dn != nullptr && dn->value == "true")
 			continue;
 
+		bool dont_use = false;
+		for (std::string &dont_use_cell : dont_use_cells)
+		{
+			if (patmatch(dont_use_cell.c_str(), cell->args[0].c_str()))
+			{
+				dont_use = true;
+				break;
+			}
+		}
+		if (dont_use)
+			continue;
+
 		LibertyAst *ff = cell->find("ff");
 		if (ff == nullptr)
 			continue;
@@ -227,7 +239,7 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has
 	}
 }
 
-static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol)
+static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol, std::vector<std::string> &dont_use_cells)
 {
 	LibertyAst *best_cell = nullptr;
 	std::map<std::string, char> best_cell_ports;
@@ -247,6 +259,18 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool
 		if (dn != nullptr && dn->value == "true")
 			continue;
 
+		bool dont_use = false;
+		for (std::string &dont_use_cell : dont_use_cells)
+		{
+			if (patmatch(dont_use_cell.c_str(), cell->args[0].c_str()))
+			{
+				dont_use = true;
+				break;
+			}
+		}
+		if (dont_use)
+			continue;
+
 		LibertyAst *ff = cell->find("ff");
 		if (ff == nullptr)
 			continue;
@@ -414,7 +438,7 @@ struct DfflibmapPass : public Pass {
 	void help() override
 	{
 		log("\n");
-		log("    dfflibmap [-prepare] [-map-only] [-info] -liberty <file> [selection]\n");
+		log("    dfflibmap [-prepare] [-map-only] [-info] [-dont_use <cell_name>] -liberty <file> [selection]\n");
 		log("\n");
 		log("Map internal flip-flop cells to the flip-flop cells in the technology\n");
 		log("library specified in the given liberty file.\n");
@@ -435,6 +459,11 @@ struct DfflibmapPass : public Pass {
 		log("that would be passed to the dfflegalize pass.  The design will not be\n");
 		log("changed.\n");
 		log("\n");
+		log("When called with -dont_use, this command will not map to the specified cell\n");
+		log("name as an alternative to setting the dont_use property in the Liberty file.\n");
+		log("This argument can be called multiple times with different cell names. This\n");
+		log("argument also supports simple glob patterns in the cell name.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
@@ -446,6 +475,8 @@ struct DfflibmapPass : public Pass {
 		bool map_only_mode = false;
 		bool info_mode = false;
 
+		std::vector<std::string> dont_use_cells;
+
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
@@ -467,6 +498,10 @@ struct DfflibmapPass : public Pass {
 				info_mode = true;
 				continue;
 			}
+			if (arg == "-dont_use" && argidx+1 < args.size()) {
+				dont_use_cells.push_back(args[++argidx]);
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -491,26 +526,26 @@ struct DfflibmapPass : public Pass {
 		LibertyParser libparser(f);
 		f.close();
 
-		find_cell(libparser.ast, ID($_DFF_N_), false, false, false, false);
-		find_cell(libparser.ast, ID($_DFF_P_), true, false, false, false);
-
-		find_cell(libparser.ast, ID($_DFF_NN0_), false, true, false, false);
-		find_cell(libparser.ast, ID($_DFF_NN1_), false, true, false, true);
-		find_cell(libparser.ast, ID($_DFF_NP0_), false, true, true, false);
-		find_cell(libparser.ast, ID($_DFF_NP1_), false, true, true, true);
-		find_cell(libparser.ast, ID($_DFF_PN0_), true, true, false, false);
-		find_cell(libparser.ast, ID($_DFF_PN1_), true, true, false, true);
-		find_cell(libparser.ast, ID($_DFF_PP0_), true, true, true, false);
-		find_cell(libparser.ast, ID($_DFF_PP1_), true, true, true, true);
-
-		find_cell_sr(libparser.ast, ID($_DFFSR_NNN_), false, false, false);
-		find_cell_sr(libparser.ast, ID($_DFFSR_NNP_), false, false, true);
-		find_cell_sr(libparser.ast, ID($_DFFSR_NPN_), false, true, false);
-		find_cell_sr(libparser.ast, ID($_DFFSR_NPP_), false, true, true);
-		find_cell_sr(libparser.ast, ID($_DFFSR_PNN_), true, false, false);
-		find_cell_sr(libparser.ast, ID($_DFFSR_PNP_), true, false, true);
-		find_cell_sr(libparser.ast, ID($_DFFSR_PPN_), true, true, false);
-		find_cell_sr(libparser.ast, ID($_DFFSR_PPP_), true, true, true);
+		find_cell(libparser.ast, ID($_DFF_N_), false, false, false, false, dont_use_cells);
+		find_cell(libparser.ast, ID($_DFF_P_), true, false, false, false, dont_use_cells);
+
+		find_cell(libparser.ast, ID($_DFF_NN0_), false, true, false, false, dont_use_cells);
+		find_cell(libparser.ast, ID($_DFF_NN1_), false, true, false, true, dont_use_cells);
+		find_cell(libparser.ast, ID($_DFF_NP0_), false, true, true, false, dont_use_cells);
+		find_cell(libparser.ast, ID($_DFF_NP1_), false, true, true, true, dont_use_cells);
+		find_cell(libparser.ast, ID($_DFF_PN0_), true, true, false, false, dont_use_cells);
+		find_cell(libparser.ast, ID($_DFF_PN1_), true, true, false, true, dont_use_cells);
+		find_cell(libparser.ast, ID($_DFF_PP0_), true, true, true, false, dont_use_cells);
+		find_cell(libparser.ast, ID($_DFF_PP1_), true, true, true, true, dont_use_cells);
+
+		find_cell_sr(libparser.ast, ID($_DFFSR_NNN_), false, false, false, dont_use_cells);
+		find_cell_sr(libparser.ast, ID($_DFFSR_NNP_), false, false, true, dont_use_cells);
+		find_cell_sr(libparser.ast, ID($_DFFSR_NPN_), false, true, false, dont_use_cells);
+		find_cell_sr(libparser.ast, ID($_DFFSR_NPP_), false, true, true, dont_use_cells);
+		find_cell_sr(libparser.ast, ID($_DFFSR_PNN_), true, false, false, dont_use_cells);
+		find_cell_sr(libparser.ast, ID($_DFFSR_PNP_), true, false, true, dont_use_cells);
+		find_cell_sr(libparser.ast, ID($_DFFSR_PPN_), true, true, false, dont_use_cells);
+		find_cell_sr(libparser.ast, ID($_DFFSR_PPP_), true, true, true, dont_use_cells);
 
 		log("  final dff cell mappings:\n");
 		logmap_all();
diff --git a/yosys/passes/techmap/extract_fa.cc b/yosys/passes/techmap/extract_fa.cc
index 117fdd54cf6..ec1979f3b6d 100644
--- a/yosys/passes/techmap/extract_fa.cc
+++ b/yosys/passes/techmap/extract_fa.cc
@@ -281,7 +281,7 @@ struct ExtractFaWorker
 	void assign_new_driver(SigBit bit, SigBit new_driver)
 	{
 		Cell *cell = driver.at(bit);
-		if (sigmap(cell->getPort(ID::Y)) == bit) {
+		if (sigmap(cell->getPort(ID::Y)) == SigSpec(bit)) {
 			cell->setPort(ID::Y, module->addWire(NEW_ID));
 			module->connect(bit, new_driver);
 		}
diff --git a/yosys/passes/techmap/flatten.cc b/yosys/passes/techmap/flatten.cc
index 7e6df5d2c1f..ea5855a09a2 100644
--- a/yosys/passes/techmap/flatten.cc
+++ b/yosys/passes/techmap/flatten.cc
@@ -46,24 +46,6 @@ IdString map_name(RTLIL::Cell *cell, T *object)
 	return cell->module->uniquify(concat_name(cell, object->name));
 }
 
-template<class T>
-void map_attributes(RTLIL::Cell *cell, T *object, IdString orig_object_name)
-{
-	if (object->has_attribute(ID::src))
-		object->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-
-	// Preserve original names via the hdlname attribute, but only for objects with a fully public name.
-	if (cell->name[0] == '\\' && (object->has_attribute(ID::hdlname) || orig_object_name[0] == '\\')) {
-		std::vector<std::string> hierarchy;
-		if (object->has_attribute(ID::hdlname))
-			hierarchy = object->get_hdlname_attribute();
-		else
-			hierarchy.push_back(orig_object_name.str().substr(1));
-		hierarchy.insert(hierarchy.begin(), cell->name.str().substr(1));
-		object->set_hdlname_attribute(hierarchy);
-	}
-}
-
 void map_sigspec(const dict<RTLIL::Wire*, RTLIL::Wire*> &map, RTLIL::SigSpec &sig, RTLIL::Module *into = nullptr)
 {
 	vector<SigChunk> chunks = sig;
@@ -76,6 +58,54 @@ void map_sigspec(const dict<RTLIL::Wire*, RTLIL::Wire*> &map, RTLIL::SigSpec &si
 struct FlattenWorker
 {
 	bool ignore_wb = false;
+	bool create_scopeinfo = true;
+	bool create_scopename = false;
+
+	template<class T>
+	void map_attributes(RTLIL::Cell *cell, T *object, IdString orig_object_name)
+	{
+		if (!create_scopeinfo && object->has_attribute(ID::src))
+			object->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+
+		// Preserve original names via the hdlname attribute, but only for objects with a fully public name.
+		// If the '-scopename' option is used, also preserve the containing scope of private objects if their scope is fully public.
+		if (cell->name[0] == '\\') {
+			if (object->has_attribute(ID::hdlname) || orig_object_name[0] == '\\') {
+				std::string new_hdlname;
+
+				if (cell->has_attribute(ID::hdlname)) {
+					new_hdlname = cell->get_string_attribute(ID(hdlname));
+				} else {
+					log_assert(!cell->name.empty());
+					new_hdlname = cell->name.c_str() + 1;
+				}
+				new_hdlname += ' ';
+
+				if (object->has_attribute(ID::hdlname)) {
+					new_hdlname += object->get_string_attribute(ID(hdlname));
+				} else {
+					log_assert(!orig_object_name.empty());
+					new_hdlname += orig_object_name.c_str() + 1;
+				}
+				object->set_string_attribute(ID(hdlname), new_hdlname);
+			} else if (object->has_attribute(ID(scopename))) {
+				std::string new_scopename;
+
+				if (cell->has_attribute(ID::hdlname)) {
+					new_scopename = cell->get_string_attribute(ID(hdlname));
+				} else {
+					log_assert(!cell->name.empty());
+					new_scopename = cell->name.c_str() + 1;
+				}
+				new_scopename += ' ';
+				new_scopename += object->get_string_attribute(ID(scopename));
+				object->set_string_attribute(ID(scopename), new_scopename);
+			} else if (create_scopename) {
+				log_assert(!cell->name.empty());
+				object->set_string_attribute(ID(scopename), cell->name.c_str() + 1);
+			}
+		}
+	}
 
 	void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, SigMap &sigmap, std::vector<RTLIL::Cell*> &new_cells)
 	{
@@ -220,7 +250,33 @@ struct FlattenWorker
 			sigmap.add(new_conn.first, new_conn.second);
 		}
 
+		RTLIL::Cell *scopeinfo = nullptr;
+		RTLIL::IdString cell_name = cell->name;
+
+		if (create_scopeinfo && cell_name.isPublic())
+		{
+			// The $scopeinfo's name will be changed below after removing the flattened cell
+			scopeinfo = module->addCell(NEW_ID, ID($scopeinfo));
+			scopeinfo->setParam(ID::TYPE, RTLIL::Const("module"));
+
+			for (auto const &attr : cell->attributes)
+			{
+				if (attr.first == ID::hdlname)
+					scopeinfo->attributes.insert(attr);
+				else
+					scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first).c_str()), attr.second);
+			}
+
+			for (auto const &attr : tpl->attributes)
+				scopeinfo->attributes.emplace(stringf("\\module_%s", RTLIL::unescape_id(attr.first).c_str()), attr.second);
+
+			scopeinfo->attributes.emplace(ID(module), RTLIL::unescape_id(tpl->name));
+		}
+
 		module->remove(cell);
+
+		if (scopeinfo != nullptr)
+			module->rename(scopeinfo, cell_name);
 	}
 
 	void flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool<RTLIL::Module*> &used_modules)
@@ -275,6 +331,20 @@ struct FlattenPass : public Pass {
 		log("    -wb\n");
 		log("        Ignore the 'whitebox' attribute on cell implementations.\n");
 		log("\n");
+		log("    -noscopeinfo\n");
+		log("        Do not create '$scopeinfo' cells that preserve attributes of cells and\n");
+		log("        modules that were removed during flattening. With this option, the\n");
+		log("        'src' attribute of a given cell is merged into all objects replacing\n");
+		log("        that cell, with multiple distinct 'src' locations separated by '|'.\n");
+		log("        Without this option these 'src' locations can be found via the\n");
+		log("        cell_src' and 'module_src' attribute of '$scopeinfo' cells.\n");
+		log("\n");
+		log("    -scopename\n");
+		log("        Create 'scopename' attributes for objects with a private name. This\n");
+		log("        attribute records the 'hdlname' of the enclosing scope. For objects\n");
+		log("        with a public name the enclosing scope can be found via their\n");
+		log("        'hdlname' attribute.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
@@ -289,6 +359,14 @@ struct FlattenPass : public Pass {
 				worker.ignore_wb = true;
 				continue;
 			}
+			if (args[argidx] == "-noscopeinfo") {
+				worker.create_scopeinfo = false;
+				continue;
+			}
+			if (args[argidx] == "-scopename") {
+				worker.create_scopename = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -312,7 +390,7 @@ struct FlattenPass : public Pass {
 			for (auto cell : module->selected_cells()) {
 				RTLIL::Module *tpl = design->module(cell->type);
 				if (tpl != nullptr) {
-					if (topo_modules.database.count(tpl) == 0)
+                                        if (!topo_modules.has_node(tpl))
 						worklist.insert(tpl);
 					topo_modules.edge(tpl, module);
 				}
diff --git a/yosys/passes/techmap/simplemap.cc b/yosys/passes/techmap/simplemap.cc
index 11692b715ea..7461460fed8 100644
--- a/yosys/passes/techmap/simplemap.cc
+++ b/yosys/passes/techmap/simplemap.cc
@@ -36,7 +36,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->attributes[ID::src] = cell->attributes[ID::src];
 		gate->setPort(ID::A, sig_a[i]);
 		gate->setPort(ID::Y, sig_y[i]);
 	}
@@ -73,7 +73,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->attributes[ID::src] = cell->attributes[ID::src];
 		gate->setPort(ID::A, sig_a[i]);
 		gate->setPort(ID::B, sig_b[i]);
 		gate->setPort(ID::Y, sig_y[i]);
@@ -124,7 +124,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 			}
 
 			RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-			gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+			gate->attributes[ID::src] = cell->attributes[ID::src];
 			gate->setPort(ID::A, sig_a[i]);
 			gate->setPort(ID::B, sig_a[i+1]);
 			gate->setPort(ID::Y, sig_t[i/2]);
@@ -137,7 +137,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 	if (cell->type == ID($reduce_xnor)) {
 		RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
 		RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->attributes[ID::src] = cell->attributes[ID::src];
 		gate->setPort(ID::A, sig_a);
 		gate->setPort(ID::Y, sig_t);
 		last_output_cell = gate;
@@ -165,7 +165,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
 			}
 
 			RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
-			gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+			gate->attributes[ID::src] = cell->attributes[ID::src];
 			gate->setPort(ID::A, sig[i]);
 			gate->setPort(ID::B, sig[i+1]);
 			gate->setPort(ID::Y, sig_t[i/2]);
@@ -194,7 +194,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 
 	RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
-	gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+	gate->attributes[ID::src] = cell->attributes[ID::src];
 	gate->setPort(ID::A, sig_a);
 	gate->setPort(ID::Y, sig_y);
 }
@@ -223,7 +223,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
 	log_assert(!gate_type.empty());
 
 	RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-	gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+	gate->attributes[ID::src] = cell->attributes[ID::src];
 	gate->setPort(ID::A, sig_a);
 	gate->setPort(ID::B, sig_b);
 	gate->setPort(ID::Y, sig_y);
@@ -239,20 +239,20 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
 	RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
-	xor_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+	xor_cell->attributes[ID::src] = cell->attributes[ID::src];
 	simplemap_bitop(module, xor_cell);
 	module->remove(xor_cell);
 
 	RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
 	RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
-	reduce_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+	reduce_cell->attributes[ID::src] = cell->attributes[ID::src];
 	simplemap_reduce(module, reduce_cell);
 	module->remove(reduce_cell);
 
 	if (!is_ne) {
 		RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
-		not_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-		simplemap_lognot(module, not_cell);
+		not_cell->attributes[ID::src] = cell->attributes[ID::src];
+                simplemap_lognot(module, not_cell);
 		module->remove(not_cell);
 	}
 }
@@ -265,7 +265,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->attributes[ID::src] = cell->attributes[ID::src];
 		gate->setPort(ID::A, sig_a[i]);
 		gate->setPort(ID::B, sig_b[i]);
 		gate->setPort(ID::S, cell->getPort(ID::S));
@@ -282,7 +282,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->attributes[ID::src] = cell->attributes[ID::src];
 		gate->setPort(ID::A, sig_a[i]);
 		gate->setPort(ID::B, sig_b[i]);
 		gate->setPort(ID::S, sig_s[i]);
@@ -298,7 +298,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->attributes[ID::src] = cell->attributes[ID::src];
 		gate->setPort(ID::A, sig_a[i]);
 		gate->setPort(ID::E, sig_e);
 		gate->setPort(ID::Y, sig_y[i]);
@@ -316,7 +316,7 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell)
 		for (int i = 0; i < GetSize(new_data); i += width) {
 			for (int k = 0; k < width; k++) {
 				RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
-				gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+				gate->attributes[ID::src] = cell->attributes[ID::src];
 				gate->setPort(ID::A, data[i*2+k]);
 				gate->setPort(ID::B, data[i*2+width+k]);
 				gate->setPort(ID::S, sel[idx]);
@@ -339,7 +339,7 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
 		SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
 		for (int i = 0; i < GetSize(lut_data); i += 2) {
 			RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
-			gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+			gate->attributes[ID::src] = cell->attributes[ID::src];
 			gate->setPort(ID::A, lut_data[i]);
 			gate->setPort(ID::B, lut_data[i+1]);
 			gate->setPort(ID::S, lut_ctrl[idx]);
diff --git a/yosys/passes/techmap/techmap.cc b/yosys/passes/techmap/techmap.cc
index 144f596c88c..64de3a1cac0 100644
--- a/yosys/passes/techmap/techmap.cc
+++ b/yosys/passes/techmap/techmap.cc
@@ -336,6 +336,11 @@ struct TechmapWorker
 
 			if (c->type.begins_with("\\$"))
 				c->type = c->type.substr(1);
+			
+			if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) {
+				c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype));
+				c->attributes.erase(ID::techmap_chtype);
+			}
 
 			vector<IdString> autopurge_ports;
 
@@ -1041,8 +1046,8 @@ struct TechmapPass : public Pass {
 		log("\n");
 		log("When a port on a module in the map file has the 'techmap_autopurge' attribute\n");
 		log("set, and that port is not connected in the instantiation that is mapped, then\n");
-		log("then a cell port connected only to such wires will be omitted in the mapped\n");
-		log("version of the circuit.\n");
+		log("a cell port connected only to such wires will be omitted in the mapped version\n");
+		log("of the circuit.\n");
 		log("\n");
 		log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
 		log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
@@ -1135,6 +1140,10 @@ struct TechmapPass : public Pass {
 		log("new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'\n");
 		log("prefix also substituted.\n");
 		log("\n");
+		log("A cell with the type _TECHMAP_PLACEHOLDER_ in the map file will have its type\n");
+		log("changed to the content of the techmap_chtype attribute. This allows for choosing\n");
+		log("the cell type dynamically.\n");
+		log("\n");
 		log("See 'help extract' for a pass that does the opposite thing.\n");
 		log("\n");
 		log("See 'help flatten' for a pass that does flatten the design (which is\n");
diff --git a/yosys/techlibs/achronix/synth_achronix.cc b/yosys/techlibs/achronix/synth_achronix.cc
index 9a0a7a3b57b..2b969182eaf 100644
--- a/yosys/techlibs/achronix/synth_achronix.cc
+++ b/yosys/techlibs/achronix/synth_achronix.cc
@@ -26,7 +26,7 @@ USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 struct SynthAchronixPass : public ScriptPass {
-  SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { }
+  SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Achronix Speedster22i FPGAs.") { }
 
   void help() override
   {
diff --git a/yosys/techlibs/anlogic/synth_anlogic.cc b/yosys/techlibs/anlogic/synth_anlogic.cc
index a3c1e0434f2..c72e7f2a183 100644
--- a/yosys/techlibs/anlogic/synth_anlogic.cc
+++ b/yosys/techlibs/anlogic/synth_anlogic.cc
@@ -169,12 +169,14 @@ struct SynthAnlogicPass : public ScriptPass
 		if (check_label("map_ram"))
 		{
 			std::string args = "";
-			if (nobram)
-				args += " -no-auto-block";
-			if (nolutram)
-				args += " -no-auto-distributed";
 			if (help_mode)
 				args += " [-no-auto-block] [-no-auto-distributed]";
+			else {
+				if (nobram)
+					args += " -no-auto-block";
+				if (nolutram)
+					args += " -no-auto-distributed";
+			}
 			run("memory_libmap -lib +/anlogic/lutrams.txt -lib +/anlogic/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
 			run("techmap -map +/anlogic/lutrams_map.v -map +/anlogic/brams_map.v");
 		}
diff --git a/yosys/techlibs/common/Makefile.inc b/yosys/techlibs/common/Makefile.inc
index 47f1ed60456..fa5c2a825de 100644
--- a/yosys/techlibs/common/Makefile.inc
+++ b/yosys/techlibs/common/Makefile.inc
@@ -34,3 +34,5 @@ $(eval $(call add_share_file,share,techlibs/common/abc9_model.v))
 $(eval $(call add_share_file,share,techlibs/common/abc9_map.v))
 $(eval $(call add_share_file,share,techlibs/common/abc9_unmap.v))
 $(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v))
+$(eval $(call add_share_file,share,techlibs/common/cmp2softlogic.v))
+$(eval $(call add_share_file,share/choices,techlibs/common/choices/kogge-stone.v))
diff --git a/yosys/techlibs/common/choices/kogge-stone.v b/yosys/techlibs/common/choices/kogge-stone.v
new file mode 100644
index 00000000000..ad2e2b16954
--- /dev/null
+++ b/yosys/techlibs/common/choices/kogge-stone.v
@@ -0,0 +1,54 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Martin Povišer <povik@cutebit.org>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+(* techmap_celltype = "$lcu" *)
+module _80_lcu_kogge_stone (P, G, CI, CO);
+	parameter WIDTH = 2;
+
+	(* force_downto *)
+	input [WIDTH-1:0] P, G;
+	input CI;
+
+	(* force_downto *)
+	output [WIDTH-1:0] CO;
+
+	integer i, j;
+	(* force_downto *)
+	reg [WIDTH-1:0] p, g;
+
+	wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
+
+	always @* begin
+		p = P;
+		g = G;
+
+		// in almost all cases CI will be constant zero
+		g[0] = g[0] | (p[0] & CI);
+
+		for (i = 0; i < $clog2(WIDTH); i = i + 1) begin
+			// iterate in reverse so we don't confuse a result from this stage and the previous
+			for (j = WIDTH - 1; j >= 2**i; j = j - 1) begin
+				g[j] = g[j] | p[j] & g[j - 2**i];
+				p[j] = p[j] & p[j - 2**i];
+			end
+		end
+	end
+
+	assign CO = g;
+endmodule
diff --git a/yosys/techlibs/common/cmp2softlogic.v b/yosys/techlibs/common/cmp2softlogic.v
new file mode 100644
index 00000000000..e480b4eee99
--- /dev/null
+++ b/yosys/techlibs/common/cmp2softlogic.v
@@ -0,0 +1,117 @@
+module constgtge(C, A, B, Y);
+parameter A_WIDTH = 0;
+parameter B_WIDTH = 0;
+
+(* force_downto *)
+input [A_WIDTH-1:0] A;
+(* force_downto *)
+input [B_WIDTH-1:0] B;
+output Y;
+input C;
+
+wire [A_WIDTH:0] ch;
+genvar n;
+generate
+	if (B_WIDTH > A_WIDTH) begin
+		// Fail
+	end else begin
+		assign ch[0] = C;
+		for (n = 0; n < A_WIDTH; n = n + 1) begin
+			if (n < B_WIDTH) begin
+				assign ch[n + 1] = B[n] ? (ch[n] && A[n]) : (ch[n] || A[n]);
+			end else begin
+				assign ch[n + 1] = ch[n] || A[n];
+			end
+		end
+		assign Y = ch[A_WIDTH];
+	end
+endgenerate
+endmodule
+
+module constltle(C, A, B, Y);
+parameter A_WIDTH = 0;
+parameter B_WIDTH = 0;
+
+(* force_downto *)
+input [A_WIDTH-1:0] A;
+(* force_downto *)
+input [B_WIDTH-1:0] B;
+output Y;
+input C;
+
+wire [A_WIDTH:0] ch;
+genvar n;
+generate
+	if (B_WIDTH > A_WIDTH) begin
+		// Fail
+	end else begin
+		assign ch[0] = C;
+		for (n = 0; n < A_WIDTH; n = n + 1) begin
+			if (n < B_WIDTH) begin
+				assign ch[n + 1] = !B[n] ? (ch[n] && !A[n]) : (ch[n] || !A[n]);
+			end else begin
+				assign ch[n + 1] = ch[n] && !A[n];
+			end
+		end
+		assign Y = ch[A_WIDTH];
+	end
+endgenerate
+endmodule
+
+(* techmap_celltype = "$ge $gt $le $lt" *)
+module _map_const_cmp_(A, B, Y);
+parameter A_WIDTH = 0;
+parameter B_WIDTH = 0;
+parameter Y_WIDTH = 0;
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+
+(* force_downto *)
+input [A_WIDTH-1:0] A;
+(* force_downto *)
+input [B_WIDTH-1:0] B;
+(* force_downto *)
+output [Y_WIDTH-1:0] Y;
+
+parameter _TECHMAP_CELLTYPE_ = "";
+
+parameter _TECHMAP_CONSTMSK_A_ = 0;
+parameter _TECHMAP_CONSTVAL_A_ = 0;
+parameter _TECHMAP_CONSTMSK_B_ = 0;
+parameter _TECHMAP_CONSTVAL_B_ = 0;
+
+wire [1023:0] _TECHMAP_DO_ = "opt -fast;";
+
+wire [A_WIDTH:0] ch;
+
+genvar n;
+generate
+	if (Y_WIDTH != 1 || A_SIGNED || B_SIGNED)
+		wire _TECHMAP_FAIL_ = 1;
+	else if (&_TECHMAP_CONSTMSK_A_) begin
+		if (A_WIDTH > B_WIDTH)
+			wire _TECHMAP_FAIL_ = 1;
+		else if (_TECHMAP_CELLTYPE_ == "$lt" || _TECHMAP_CELLTYPE_ == "$le")
+			constgtge #(.A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH))
+				_TECHMAP_REPLACE_(.A(B), .B(A), .Y(Y),
+					.C(_TECHMAP_CELLTYPE_ == "$lt"));
+		else
+			constltle #(.A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH))
+				_TECHMAP_REPLACE_(.A(B), .B(A), .Y(Y),
+					.C(_TECHMAP_CELLTYPE_ == "$gt"));
+	end else if (&_TECHMAP_CONSTMSK_B_) begin
+		if (B_WIDTH > A_WIDTH)
+			wire _TECHMAP_FAIL_ = 1;
+		else if (_TECHMAP_CELLTYPE_ == "$lt" || _TECHMAP_CELLTYPE_ == "$le")
+			constltle #(.A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH))
+				_TECHMAP_REPLACE_(.A(A), .B(B), .Y(Y),
+					.C(_TECHMAP_CELLTYPE_ == "$le"));
+		else
+			constgtge #(.A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH))
+				_TECHMAP_REPLACE_(.A(A), .B(B), .Y(Y),
+					.C(_TECHMAP_CELLTYPE_ == "$ge"));
+	end else
+		wire _TECHMAP_FAIL_ = 1;
+endgenerate
+
+endmodule
diff --git a/yosys/techlibs/common/prep.cc b/yosys/techlibs/common/prep.cc
index c354956bcf4..e9176304d48 100644
--- a/yosys/techlibs/common/prep.cc
+++ b/yosys/techlibs/common/prep.cc
@@ -189,6 +189,7 @@ struct PrepPass : public ScriptPass
 				run(ifxmode ? "proc -ifx" : "proc");
 			if (help_mode || flatten)
 				run("flatten", "(if -flatten)");
+			run("future");
 			run(nokeepdc ? "opt_expr" : "opt_expr -keepdc");
 			run("opt_clean");
 			run("check");
diff --git a/yosys/techlibs/common/simlib.v b/yosys/techlibs/common/simlib.v
index 9cb68e7252f..7dc03da6d2d 100644
--- a/yosys/techlibs/common/simlib.v
+++ b/yosys/techlibs/common/simlib.v
@@ -902,18 +902,34 @@ endgenerate
 endmodule
 
 // --------------------------------------------------------
-
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $macc (A, B, Y)
+//-
+//- Multiply and accumulate.
+//- A building block for summing any number of negated and unnegated signals
+//- and arithmetic products of pairs of signals. Cell port A concatenates pairs
+//- of signals to be multiplied together. When the second signal in a pair is zero
+//- length, a constant 1 is used instead as the second factor. Cell port B
+//- concatenates 1-bit-wide signals to also be summed, such as "carry in" in adders.
+//- Typically created by the `alumacc` pass, which transforms $add and $mul
+//- into $macc cells.
 module \$macc (A, B, Y);
 
 parameter A_WIDTH = 0;
 parameter B_WIDTH = 0;
 parameter Y_WIDTH = 0;
+// CONFIG determines the layout of A, as explained below
 parameter CONFIG = 4'b0000;
 parameter CONFIG_WIDTH = 4;
 
-input [A_WIDTH-1:0] A;
-input [B_WIDTH-1:0] B;
-output reg [Y_WIDTH-1:0] Y;
+// In the terms used for this cell, there's mixed meanings for the term "port". To disambiguate:
+// A cell port is for example the A input (it is constructed in C++ as cell->setPort(ID::A, ...))
+// Multiplier ports are pairs of multiplier inputs ("factors").
+// If the second signal in such a pair is zero length, no multiplication is necessary, and the first signal is just added to the sum.
+input [A_WIDTH-1:0] A; // Cell port A is the concatenation of all arithmetic ports
+input [B_WIDTH-1:0] B; // Cell port B is the concatenation of single-bit unsigned signals to be also added to the sum
+output reg [Y_WIDTH-1:0] Y; // Output sum
 
 // Xilinx XSIM does not like $clog2() below..
 function integer my_clog2;
@@ -929,10 +945,42 @@ function integer my_clog2;
 	end
 endfunction
 
+// Bits that a factor's length field in CONFIG per factor in cell port A
 localparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;
+// Number of multiplier ports
 localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
+// Minium bit width of an induction variable to iterate over all bits of cell port A
 localparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;
 
+// In this pseudocode, u(foo) means an unsigned int that's foo bits long.
+// The CONFIG parameter carries the following information:
+//	struct CONFIG {
+//		u4 num_bits;
+//		struct port_field {
+//			bool is_signed;
+//			bool is_subtract;
+//			u(num_bits) factor1_len;
+//			u(num_bits) factor2_len;
+//		}[num_ports];
+//	};
+
+// The A cell port carries the following information:
+//	struct A {
+//		u(CONFIG.port_field[0].factor1_len) port0factor1;
+//		u(CONFIG.port_field[0].factor2_len) port0factor2;
+//		u(CONFIG.port_field[1].factor1_len) port1factor1;
+//		u(CONFIG.port_field[1].factor2_len) port1factor2;
+//		...
+//	};
+// and log(sizeof(A)) is num_abits.
+// No factor1 may have a zero length.
+// A factor2 having a zero length implies factor2 is replaced with a constant 1.
+
+// Additionally, B is an array of 1-bit-wide unsigned integers to also be summed up.
+// Finally, we have:
+// Y = port0factor1 * port0factor2 + port1factor1 * port1factor2 + ...
+//     * B[0] + B[1] + ...
+
 function [2*num_ports*num_abits-1:0] get_port_offsets;
 	input [CONFIG_WIDTH-1:0] cfg;
 	integer i, cursor;
@@ -1799,6 +1847,46 @@ end
 
 endmodule
 
+// --------------------------------------------------------
+
+module \$print (EN, TRG, ARGS);
+
+parameter PRIORITY = 0;
+
+parameter FORMAT = "";
+parameter ARGS_WIDTH = 0;
+
+parameter TRG_ENABLE = 1;
+parameter TRG_WIDTH = 0;
+parameter TRG_POLARITY = 0;
+
+input EN;
+input [TRG_WIDTH-1:0] TRG;
+input [ARGS_WIDTH-1:0] ARGS;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$check (A, EN, TRG, ARGS);
+
+parameter FLAVOR = "";
+parameter PRIORITY = 0;
+
+parameter FORMAT = "";
+parameter ARGS_WIDTH = 0;
+
+parameter TRG_ENABLE = 1;
+parameter TRG_WIDTH = 0;
+parameter TRG_POLARITY = 0;
+
+input A;
+input EN;
+input [TRG_WIDTH-1:0] TRG;
+input [ARGS_WIDTH-1:0] ARGS;
+
+endmodule
+
 // --------------------------------------------------------
 `ifndef SIMLIB_NOSR
 
@@ -2653,3 +2741,80 @@ endmodule
 `endif
 
 // --------------------------------------------------------
+
+module \$set_tag (A, SET, CLR, Y);
+
+parameter TAG = "";
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A;
+input [WIDTH-1:0] SET;
+input [WIDTH-1:0] CLR;
+output [WIDTH-1:0] Y;
+
+assign Y = A;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$get_tag (A, Y);
+
+parameter TAG = "";
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A;
+output [WIDTH-1:0] Y;
+
+assign Y = A;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$overwrite_tag (A, SET, CLR);
+
+parameter TAG = "";
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A;
+input [WIDTH-1:0] SET;
+input [WIDTH-1:0] CLR;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$original_tag (A, Y);
+
+parameter TAG = "";
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A;
+output [WIDTH-1:0] Y;
+
+assign Y = A;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$future_ff (A, Y);
+
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A;
+output [WIDTH-1:0] Y;
+
+assign Y = A;
+
+endmodule
+
+// --------------------------------------------------------
+
+(* noblackbox *)
+module \$scopeinfo ();
+
+parameter TYPE = "";
+
+endmodule
diff --git a/yosys/techlibs/common/synth.cc b/yosys/techlibs/common/synth.cc
index 63395c36802..74a484d59ae 100644
--- a/yosys/techlibs/common/synth.cc
+++ b/yosys/techlibs/common/synth.cc
@@ -17,17 +17,16 @@
  *
  */
 
-#include "kernel/register.h"
 #include "kernel/celltypes.h"
-#include "kernel/rtlil.h"
 #include "kernel/log.h"
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-struct SynthPass : public ScriptPass
-{
-	SynthPass() : ScriptPass("synth", "generic synthesis script") { }
+struct SynthPass : public ScriptPass {
+	SynthPass() : ScriptPass("synth", "generic synthesis script") {}
 
 	void help() override
 	{
@@ -60,6 +59,9 @@ struct SynthPass : public ScriptPass
 		log("    -noabc\n");
 		log("        do not run abc (as if yosys was compiled without ABC support)\n");
 		log("\n");
+		log("    -booth\n");
+		log("        run the booth pass to map $mul to Booth encoded multipliers\n");
+		log("\n");
 		log("    -noalumacc\n");
 		log("        do not run 'alumacc' pass. i.e. keep arithmetic operators in\n");
 		log("        their direct form ($add, $sub, etc.).\n");
@@ -86,6 +88,10 @@ struct SynthPass : public ScriptPass
 		log("        read/write collision\" (same result as setting the no_rw_check\n");
 		log("        attribute on all memories).\n");
 		log("\n");
+		log("    -extra-map filename\n");
+		log("        source extra rules from the given file to complement the default\n");
+		log("        mapping library in the `techmap` step. this option can be\n");
+		log("        repeated.\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
@@ -93,8 +99,9 @@ struct SynthPass : public ScriptPass
 	}
 
 	string top_module, fsm_opts, memory_opts, abc;
-	bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap;
+	bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth;
 	int lut;
+	std::vector<std::string> techmap_maps;
 
 	void clear_flags() override
 	{
@@ -110,7 +117,9 @@ struct SynthPass : public ScriptPass
 		noabc = false;
 		noshare = false;
 		flowmap = false;
+		booth = false;
 		abc = "abc";
+		techmap_maps.clear();
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -119,24 +128,23 @@ struct SynthPass : public ScriptPass
 		clear_flags();
 
 		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			if (args[argidx] == "-top" && argidx+1 < args.size()) {
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-top" && argidx + 1 < args.size()) {
 				top_module = args[++argidx];
 				continue;
 			}
-			if (args[argidx] == "-encfile" && argidx+1 < args.size()) {
+			if (args[argidx] == "-encfile" && argidx + 1 < args.size()) {
 				fsm_opts = " -encfile " + args[++argidx];
 				continue;
 			}
-			if (args[argidx] == "-run" && argidx+1 < args.size()) {
-				size_t pos = args[argidx+1].find(':');
+			if (args[argidx] == "-run" && argidx + 1 < args.size()) {
+				size_t pos = args[argidx + 1].find(':');
 				if (pos == std::string::npos) {
 					run_from = args[++argidx];
 					run_to = args[argidx];
 				} else {
 					run_from = args[++argidx].substr(0, pos);
-					run_to = args[argidx].substr(pos+1);
+					run_to = args[argidx].substr(pos + 1);
 				}
 				continue;
 			}
@@ -148,7 +156,7 @@ struct SynthPass : public ScriptPass
 				flatten = true;
 				continue;
 			}
-			if (args[argidx] == "-lut") {
+			if (args[argidx] == "-lut" && argidx + 1 < args.size()) {
 				lut = atoi(args[++argidx].c_str());
 				continue;
 			}
@@ -164,6 +172,11 @@ struct SynthPass : public ScriptPass
 				noalumacc = true;
 				continue;
 			}
+			if (args[argidx] == "-booth") {
+				booth = true;
+				continue;
+			}
+
 			if (args[argidx] == "-nordff") {
 				memory_opts += " -nordff";
 				continue;
@@ -184,6 +197,10 @@ struct SynthPass : public ScriptPass
 				memory_opts += " -no-rw-check";
 				continue;
 			}
+			if (args[argidx] == "-extra-map" && argidx + 1 < args.size()) {
+				techmap_maps.push_back(args[++argidx]);
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -206,8 +223,7 @@ struct SynthPass : public ScriptPass
 
 	void script() override
 	{
-		if (check_label("begin"))
-		{
+		if (check_label("begin")) {
 			if (help_mode) {
 				run("hierarchy -check [-top <top> | -auto-top]");
 			} else {
@@ -221,16 +237,15 @@ struct SynthPass : public ScriptPass
 			}
 		}
 
-		if (check_label("coarse"))
-		{
+		if (check_label("coarse")) {
 			run("proc");
-			if (help_mode || flatten)
+			if (flatten || help_mode)
 				run("flatten", "  (if -flatten)");
 			run("opt_expr");
 			run("opt_clean");
 			run("check");
 			run("opt -nodffe -nosdff");
-			if (!nofsm)
+			if (!nofsm || help_mode)
 				run("fsm" + fsm_opts, "      (unless -nofsm)");
 			run("opt");
 			run("wreduce");
@@ -240,6 +255,8 @@ struct SynthPass : public ScriptPass
 				run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)");
 			else if (lut)
 				run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut));
+			if (booth || help_mode)
+				run("booth", "    (if -booth)");
 			if (!noalumacc)
 				run("alumacc", "  (unless -noalumacc)");
 			if (!noshare)
@@ -249,50 +266,50 @@ struct SynthPass : public ScriptPass
 			run("opt_clean");
 		}
 
-		if (check_label("fine"))
-		{
+		if (check_label("fine")) {
 			run("opt -fast -full");
 			run("memory_map");
 			run("opt -full");
-			run("techmap");
-			if (help_mode)
-			{
+			if (help_mode) {
+				run("techmap", "                  (unless -extra-map)");	
+				run("techmap -map +/techmap.v -map <inject>", "  (if -extra-map)");
+			} else {
+				std::string techmap_opts;
+				if (!techmap_maps.empty())
+					techmap_opts += " -map +/techmap.v";
+				for (auto fn : techmap_maps)
+					techmap_opts += stringf(" -map %s", fn.c_str());
+				run("techmap" + techmap_opts);
+			}
+			if (help_mode) {
 				run("techmap -map +/gate2lut.v", "(if -noabc and -lut)");
 				run("clean; opt_lut", "           (if -noabc and -lut)");
 				run("flowmap -maxlut K", "        (if -flowmap and -lut)");
-			}
-			else if (noabc && lut)
-			{
+			} else if (noabc && lut) {
 				run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut));
 				run("clean; opt_lut");
-			}
-			else if (flowmap)
-			{
+			} else if (flowmap) {
 				run(stringf("flowmap -maxlut %d", lut));
 			}
 			run("opt -fast");
 
-			if (!noabc && !flowmap) {
-		#ifdef YOSYS_ENABLE_ABC
-				if (help_mode)
-				{
+			if ((!noabc && !flowmap) || help_mode) {
+#ifdef YOSYS_ENABLE_ABC
+				if (help_mode) {
 					run(abc + " -fast", "       (unless -noabc, unless -lut)");
 					run(abc + " -fast -lut k", "(unless -noabc, if -lut)");
-				}
-				else
-				{
+				} else {
 					if (lut)
 						run(stringf("%s -fast -lut %d", abc.c_str(), lut));
 					else
 						run(abc + " -fast");
 				}
 				run("opt -fast", "       (unless -noabc)");
-		#endif
+#endif
 			}
 		}
 
-		if (check_label("check"))
-		{
+		if (check_label("check")) {
 			run("hierarchy -check");
 			run("stat");
 			run("check");
diff --git a/yosys/techlibs/common/techmap.v b/yosys/techlibs/common/techmap.v
index 7fb8173b069..68b276588b5 100644
--- a/yosys/techlibs/common/techmap.v
+++ b/yosys/techlibs/common/techmap.v
@@ -207,7 +207,7 @@ module _90_fa (A, B, C, X, Y);
 endmodule
 
 (* techmap_celltype = "$lcu" *)
-module _90_lcu (P, G, CI, CO);
+module _90_lcu_brent_kung (P, G, CI, CO);
 	parameter WIDTH = 2;
 
 	(* force_downto *)
diff --git a/yosys/techlibs/ecp5/Makefile.inc b/yosys/techlibs/ecp5/Makefile.inc
index f9fa79ab9ad..a1c9bfc5233 100644
--- a/yosys/techlibs/ecp5/Makefile.inc
+++ b/yosys/techlibs/ecp5/Makefile.inc
@@ -1,5 +1,5 @@
 
-OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o
+OBJS += techlibs/ecp5/synth_ecp5.o
 
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh))
diff --git a/yosys/techlibs/ecp5/synth_ecp5.cc b/yosys/techlibs/ecp5/synth_ecp5.cc
index 82e23486844..6e518f5d183 100644
--- a/yosys/techlibs/ecp5/synth_ecp5.cc
+++ b/yosys/techlibs/ecp5/synth_ecp5.cc
@@ -93,8 +93,8 @@ struct SynthEcp5Pass : public ScriptPass
 		log("    -abc2\n");
 		log("        run two passes of 'abc' for slightly improved logic density\n");
 		log("\n");
-		log("    -abc9\n");
-		log("        use new ABC9 flow (EXPERIMENTAL)\n");
+		log("    -noabc9\n");
+		log("        disable use of new ABC9 flow\n");
 		log("\n");
 		log("    -vpr\n");
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
@@ -137,7 +137,7 @@ struct SynthEcp5Pass : public ScriptPass
 		retime = false;
 		abc2 = false;
 		vpr = false;
-		abc9 = false;
+		abc9 = true;
 		iopad = false;
 		nodsp = false;
 		no_rw_check = false;
@@ -224,7 +224,11 @@ struct SynthEcp5Pass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-abc9") {
-				abc9 = true;
+				// removed, ABC9 is on by default.
+				continue;
+			}
+			if (args[argidx] == "-noabc9") {
+				abc9 = false;
 				continue;
 			}
 			if (args[argidx] == "-iopad") {
@@ -304,12 +308,14 @@ struct SynthEcp5Pass : public ScriptPass
 		if (check_label("map_ram"))
 		{
 			std::string args = "";
-			if (nobram)
-				args += " -no-auto-block";
-			if (nolutram)
-				args += " -no-auto-distributed";
 			if (help_mode)
 				args += " [-no-auto-block] [-no-auto-distributed]";
+			else {
+				if (nobram)
+					args += " -no-auto-block";
+				if (nolutram)
+					args += " -no-auto-distributed";
+			}
 			run("memory_libmap -lib +/ecp5/lutrams.txt -lib +/ecp5/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
 			run("techmap -map +/ecp5/lutrams_map.v -map +/ecp5/brams_map.v");
 		}
@@ -359,7 +365,7 @@ struct SynthEcp5Pass : public ScriptPass
 			run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
 			run("opt_expr -undriven -mux_undef");
 			run("simplemap");
-			run("ecp5_gsr");
+			run("lattice_gsr");
 			run("attrmvcp -copy -attr syn_useioff");
 			run("opt_clean");
 		}
@@ -404,7 +410,7 @@ struct SynthEcp5Pass : public ScriptPass
 				run("techmap -map +/ecp5/cells_map.v", "(skip if -vpr)");
 			else if (!vpr)
 				run("techmap -map +/ecp5/cells_map.v");
-			run("opt_lut_ins -tech ecp5");
+			run("opt_lut_ins -tech lattice");
 			run("clean");
 		}
 
diff --git a/yosys/techlibs/efinix/cells_sim.v b/yosys/techlibs/efinix/cells_sim.v
index 22c7bc776da..26e45464613 100644
--- a/yosys/techlibs/efinix/cells_sim.v
+++ b/yosys/techlibs/efinix/cells_sim.v
@@ -113,7 +113,31 @@ module EFX_GBUFCE(
    
 endmodule
 
-module EFX_RAM_5K(
+module EFX_RAM_5K
+# (
+   parameter READ_WIDTH = 20,
+   parameter WRITE_WIDTH = 20,
+   localparam READ_ADDR_WIDTH = 
+			    (READ_WIDTH == 16) ? 8 :  // 256x16
+			    (READ_WIDTH == 8)  ? 9 :  // 512x8
+			    (READ_WIDTH == 4)  ? 10 : // 1024x4
+			    (READ_WIDTH == 2)  ? 11 : // 2048x2
+			    (READ_WIDTH == 1)  ? 12 : // 4096x1
+			    (READ_WIDTH == 20) ? 8 :  // 256x20
+			    (READ_WIDTH == 10) ? 9 :  // 512x10
+			    (READ_WIDTH == 5)  ? 10 : -1, // 1024x5
+   
+   localparam WRITE_ADDR_WIDTH = 
+			    (WRITE_WIDTH == 16) ? 8 :  // 256x16
+			    (WRITE_WIDTH == 8)  ? 9 :  // 512x8
+			    (WRITE_WIDTH == 4)  ? 10 : // 1024x4
+			    (WRITE_WIDTH == 2)  ? 11 : // 2048x2
+			    (WRITE_WIDTH == 1)  ? 12 : // 4096x1
+			    (WRITE_WIDTH == 20) ? 8 :  // 256x20
+			    (WRITE_WIDTH == 10) ? 9 :  // 512x10
+			    (WRITE_WIDTH == 5)  ? 10 : -1 // 1024x5
+)
+(
    input [WRITE_WIDTH-1:0] WDATA,
    input [WRITE_ADDR_WIDTH-1:0] WADDR,
    input WE, 
@@ -126,8 +150,6 @@ module EFX_RAM_5K(
    (* clkbuf_sink *)
    input RCLK
 );
-   parameter READ_WIDTH = 20;
-   parameter WRITE_WIDTH = 20;
    parameter OUTPUT_REG = 1'b0;
    parameter RCLK_POLARITY  = 1'b1;
    parameter RE_POLARITY    = 1'b1;
@@ -155,25 +177,4 @@ module EFX_RAM_5K(
    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-
-   localparam READ_ADDR_WIDTH = 
-			    (READ_WIDTH == 16) ? 8 :  // 256x16
-			    (READ_WIDTH == 8)  ? 9 :  // 512x8
-			    (READ_WIDTH == 4)  ? 10 : // 1024x4
-			    (READ_WIDTH == 2)  ? 11 : // 2048x2
-			    (READ_WIDTH == 1)  ? 12 : // 4096x1
-			    (READ_WIDTH == 20) ? 8 :  // 256x20
-			    (READ_WIDTH == 10) ? 9 :  // 512x10
-			    (READ_WIDTH == 5)  ? 10 : -1; // 1024x5
-   
-   localparam WRITE_ADDR_WIDTH = 
-			    (WRITE_WIDTH == 16) ? 8 :  // 256x16
-			    (WRITE_WIDTH == 8)  ? 9 :  // 512x8
-			    (WRITE_WIDTH == 4)  ? 10 : // 1024x4
-			    (WRITE_WIDTH == 2)  ? 11 : // 2048x2
-			    (WRITE_WIDTH == 1)  ? 12 : // 4096x1
-			    (WRITE_WIDTH == 20) ? 8 :  // 256x20
-			    (WRITE_WIDTH == 10) ? 9 :  // 512x10
-			    (WRITE_WIDTH == 5)  ? 10 : -1; // 1024x5
-   
 endmodule
diff --git a/yosys/techlibs/efinix/synth_efinix.cc b/yosys/techlibs/efinix/synth_efinix.cc
index bbc38944488..419bc2f884c 100644
--- a/yosys/techlibs/efinix/synth_efinix.cc
+++ b/yosys/techlibs/efinix/synth_efinix.cc
@@ -161,9 +161,13 @@ struct SynthEfinixPass : public ScriptPass
 		if (check_label("map_ram"))
 		{
 			std::string args = "";
-			if (nobram)
-				args += " -no-auto-block";
-			run("memory_libmap -lib +/efinix/brams.txt" + args);
+			if (help_mode)
+				args += " [-no-auto-block]";
+			else {
+				if (nobram)
+					args += " -no-auto-block";
+			}
+			run("memory_libmap -lib +/efinix/brams.txt" + args, "(-no-auto-block if -nobram)");
 			run("techmap -map +/efinix/brams_map.v");
 		}
 
diff --git a/yosys/techlibs/fabulous/synth_fabulous.cc b/yosys/techlibs/fabulous/synth_fabulous.cc
index b4a7ab2dc6f..8d2fb1471a9 100644
--- a/yosys/techlibs/fabulous/synth_fabulous.cc
+++ b/yosys/techlibs/fabulous/synth_fabulous.cc
@@ -320,7 +320,7 @@ struct SynthPass : public ScriptPass
 			run("opt_clean");
 		}
 
-		if (check_label("map_ram")) {
+		if (check_label("map_ram", "(unless -noregfile)")) {
 			// RegFile extraction
 			if (!noregfile) {
 				run("memory_libmap -lib +/fabulous/ram_regfile.txt");
@@ -342,7 +342,7 @@ struct SynthPass : public ScriptPass
 		}
 
 		if (check_label("map_iopad", "(if -iopad)")) {
-			if (iopad) {
+			if (iopad || help_mode) {
 				run("opt -full");
 				run("iopadmap -bits -outpad $__FABULOUS_OBUF I:PAD -inpad $__FABULOUS_IBUF O:PAD "
 					"-toutpad IO_1_bidirectional_frame_config_pass ~T:I:PAD "
diff --git a/yosys/techlibs/gowin/brams.txt b/yosys/techlibs/gowin/brams.txt
index 0c0d8fa3e3e..435d3b5cf57 100644
--- a/yosys/techlibs/gowin/brams.txt
+++ b/yosys/techlibs/gowin/brams.txt
@@ -1,13 +1,11 @@
 ram block $__GOWIN_SP_ {
 	abits 14;
 	widths 1 2 4 9 18 36 per_port;
-	byte 9;
 	cost 128;
 	init no_undef;
 	port srsw "A" {
 		clock posedge;
 		clken;
-		wrbe_separate;
 		option "RESET_MODE" "SYNC" {
 			rdsrst zero ungated;
 		}
@@ -30,13 +28,11 @@ ram block $__GOWIN_SP_ {
 ram block $__GOWIN_DP_ {
 	abits 14;
 	widths 1 2 4 9 18 per_port;
-	byte 9;
 	cost 128;
 	init no_undef;
 	port srsw "A" "B" {
 		clock posedge;
 		clken;
-		wrbe_separate;
 		option "RESET_MODE" "SYNC" {
 			rdsrst zero ungated;
 		}
@@ -59,7 +55,6 @@ ram block $__GOWIN_DP_ {
 ram block $__GOWIN_SDP_ {
 	abits 14;
 	widths 1 2 4 9 18 36 per_port;
-	byte 9;
 	cost 128;
 	init no_undef;
 	port sr "R" {
@@ -76,6 +71,5 @@ ram block $__GOWIN_SDP_ {
 	port sw "W" {
 		clock posedge;
 		clken;
-		wrbe_separate;
 	}
 }
diff --git a/yosys/techlibs/gowin/brams_map.v b/yosys/techlibs/gowin/brams_map.v
index 7ffc91bacc1..8e6cc61402d 100644
--- a/yosys/techlibs/gowin/brams_map.v
+++ b/yosys/techlibs/gowin/brams_map.v
@@ -14,8 +14,7 @@
 `define x8_width(width) (width / 9 * 8 + width % 9)
 `define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]}
 `define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]}
-`define wre(width, wr_en, wr_be) (width < 18 ? wr_en | wr_be[0] : wr_en)
-`define addrbe(width, addr, wr_be) (width < 18 ? addr : {addr[13:4], wr_be})
+`define addrbe_always(width, addr) (width < 18 ? addr :  width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111})
 
 
 `define INIT(func) \
@@ -90,7 +89,6 @@ parameter INIT = 0;
 parameter OPTION_RESET_MODE = "SYNC";
 
 parameter PORT_A_WIDTH = 36;
-parameter PORT_A_WR_BE_WIDTH = 4;
 parameter PORT_A_OPTION_WRITE_MODE = 0;
 
 input PORT_A_CLK;
@@ -99,15 +97,13 @@ input PORT_A_WR_EN;
 input PORT_A_RD_SRST;
 input PORT_A_RD_ARST;
 input [13:0] PORT_A_ADDR;
-input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
 input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
 output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
 
 `DEF_FUNCS
 
 wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
-wire WRE = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE);
-wire [13:0] AD = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
+wire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);
 
 generate
 
@@ -129,9 +125,9 @@ if (PORT_A_WIDTH < 9) begin
 		.BLKSEL(3'b000),
 		.CLK(PORT_A_CLK),
 		.CE(PORT_A_CLK_EN),
-		.WRE(WRE),
+		.WRE(PORT_A_WR_EN),
 		.RESET(RST),
-		.OCE(1'b0),
+		.OCE(1'b1),
 		.AD(AD),
 		.DI(DI),
 		.DO(DO),
@@ -155,9 +151,9 @@ end else begin
 		.BLKSEL(3'b000),
 		.CLK(PORT_A_CLK),
 		.CE(PORT_A_CLK_EN),
-		.WRE(WRE),
+		.WRE(PORT_A_WR_EN),
 		.RESET(RST),
-		.OCE(1'b0),
+		.OCE(1'b1),
 		.AD(AD),
 		.DI(DI),
 		.DO(DO),
@@ -176,11 +172,9 @@ parameter INIT = 0;
 parameter OPTION_RESET_MODE = "SYNC";
 
 parameter PORT_A_WIDTH = 18;
-parameter PORT_A_WR_BE_WIDTH = 2;
 parameter PORT_A_OPTION_WRITE_MODE = 0;
 
 parameter PORT_B_WIDTH = 18;
-parameter PORT_B_WR_BE_WIDTH = 2;
 parameter PORT_B_OPTION_WRITE_MODE = 0;
 
 input PORT_A_CLK;
@@ -189,7 +183,6 @@ input PORT_A_WR_EN;
 input PORT_A_RD_SRST;
 input PORT_A_RD_ARST;
 input [13:0] PORT_A_ADDR;
-input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
 input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
 output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
 
@@ -199,7 +192,6 @@ input PORT_B_WR_EN;
 input PORT_B_RD_SRST;
 input PORT_B_RD_ARST;
 input [13:0] PORT_B_ADDR;
-input [PORT_A_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
 input [PORT_A_WIDTH-1:0] PORT_B_WR_DATA;
 output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
 
@@ -207,10 +199,8 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
 
 wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
 wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST;
-wire WREA = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE);
-wire WREB = `wre(PORT_B_WIDTH, PORT_B_WR_EN, PORT_B_WR_BE);
-wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
-wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE);
+wire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);
+wire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR);
 
 generate
 
@@ -224,7 +214,7 @@ if (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin
 	assign PORT_A_RD_DATA = `x8_rd_data(DOA);
 	assign PORT_B_RD_DATA = `x8_rd_data(DOB);
 
-	DP #(
+	DPB #(
 		`INIT(init_slice_x8)
 		.READ_MODE0(1'b0),
 		.READ_MODE1(1'b0),
@@ -232,25 +222,27 @@ if (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin
 		.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),
 		.BIT_WIDTH_0(`x8_width(PORT_A_WIDTH)),
 		.BIT_WIDTH_1(`x8_width(PORT_B_WIDTH)),
-		.BLK_SEL(3'b000),
+		.BLK_SEL_0(3'b000),
+		.BLK_SEL_1(3'b000),
 		.RESET_MODE(OPTION_RESET_MODE),
 	) _TECHMAP_REPLACE_ (
-		.BLKSEL(3'b000),
+		.BLKSELA(3'b000),
+		.BLKSELB(3'b000),
 
 		.CLKA(PORT_A_CLK),
 		.CEA(PORT_A_CLK_EN),
-		.WREA(WREA),
+		.WREA(PORT_A_WR_EN),
 		.RESETA(RSTA),
-		.OCEA(1'b0),
+		.OCEA(1'b1),
 		.ADA(ADA),
 		.DIA(DIA),
 		.DOA(DOA),
 
 		.CLKB(PORT_B_CLK),
 		.CEB(PORT_B_CLK_EN),
-		.WREB(WREB),
+		.WREB(PORT_B_WR_EN),
 		.RESETB(RSTB),
-		.OCEB(1'b0),
+		.OCEB(1'b1),
 		.ADB(ADB),
 		.DIB(DIB),
 		.DOB(DOB),
@@ -266,7 +258,7 @@ end else begin
 	assign PORT_A_RD_DATA = DOA;
 	assign PORT_B_RD_DATA = DOB;
 
-	DPX9 #(
+	DPX9B #(
 		`INIT(init_slice_x9)
 		.READ_MODE0(1'b0),
 		.READ_MODE1(1'b0),
@@ -274,25 +266,27 @@ end else begin
 		.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),
 		.BIT_WIDTH_0(PORT_A_WIDTH),
 		.BIT_WIDTH_1(PORT_B_WIDTH),
-		.BLK_SEL(3'b000),
+		.BLK_SEL_0(3'b000),
+		.BLK_SEL_1(3'b000),
 		.RESET_MODE(OPTION_RESET_MODE),
 	) _TECHMAP_REPLACE_ (
-		.BLKSEL(3'b000),
+		.BLKSELA(3'b000),
+		.BLKSELB(3'b000),
 
 		.CLKA(PORT_A_CLK),
 		.CEA(PORT_A_CLK_EN),
-		.WREA(WREA),
+		.WREA(PORT_A_WR_EN),
 		.RESETA(RSTA),
-		.OCEA(1'b0),
+		.OCEA(1'b1),
 		.ADA(ADA),
 		.DIA(DIA),
 		.DOA(DOA),
 
 		.CLKB(PORT_B_CLK),
 		.CEB(PORT_B_CLK_EN),
-		.WREB(WREB),
+		.WREB(PORT_B_WR_EN),
 		.RESETB(RSTB),
-		.OCEB(1'b0),
+		.OCEB(1'b1),
 		.ADB(ADB),
 		.DIB(DIB),
 		.DOB(DOB),
@@ -311,9 +305,7 @@ parameter INIT = 0;
 parameter OPTION_RESET_MODE = "SYNC";
 
 parameter PORT_R_WIDTH = 18;
-
 parameter PORT_W_WIDTH = 18;
-parameter PORT_W_WR_BE_WIDTH = 2;
 
 input PORT_R_CLK;
 input PORT_R_CLK_EN;
@@ -326,14 +318,13 @@ input PORT_W_CLK;
 input PORT_W_CLK_EN;
 input PORT_W_WR_EN;
 input [13:0] PORT_W_ADDR;
-input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE;
 input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
 
 `DEF_FUNCS
 
 wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST;
-wire WRE = `wre(PORT_W_WIDTH, PORT_W_WR_EN, PORT_W_WR_BE);
-wire [13:0] ADW = `addrbe(PORT_W_WIDTH, PORT_W_ADDR, PORT_W_WR_BE);
+wire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR);
+wire WRE = PORT_W_CLK_EN & PORT_W_WR_EN;
 
 generate
 
@@ -344,28 +335,28 @@ if (PORT_W_WIDTH < 9 || PORT_R_WIDTH < 9) begin
 
 	assign PORT_R_RD_DATA = `x8_rd_data(DO);
 
-	SDP #(
+	SDPB #(
 		`INIT(init_slice_x8)
 		.READ_MODE(1'b0),
 		.BIT_WIDTH_0(`x8_width(PORT_W_WIDTH)),
 		.BIT_WIDTH_1(`x8_width(PORT_R_WIDTH)),
-		.BLK_SEL(3'b000),
+		.BLK_SEL_0(3'b000),
+		.BLK_SEL_1(3'b000),
 		.RESET_MODE(OPTION_RESET_MODE),
 	) _TECHMAP_REPLACE_ (
-		.BLKSEL(3'b000),
+		.BLKSELA(3'b000),
+		.BLKSELB(3'b000),
 
 		.CLKA(PORT_W_CLK),
-		.CEA(PORT_W_CLK_EN),
-		.WREA(WRE),
+		.CEA(WRE),
 		.RESETA(1'b0),
 		.ADA(ADW),
 		.DI(DI),
 
 		.CLKB(PORT_R_CLK),
 		.CEB(PORT_R_CLK_EN),
-		.WREB(1'b0),
 		.RESETB(RST),
-		.OCE(1'b0),
+		.OCE(1'b1),
 		.ADB(PORT_R_ADDR),
 		.DO(DO),
 	);
@@ -377,28 +368,28 @@ end else begin
 
 	assign PORT_R_RD_DATA = DO;
 
-	SDPX9 #(
+	SDPX9B #(
 		`INIT(init_slice_x9)
 		.READ_MODE(1'b0),
 		.BIT_WIDTH_0(PORT_W_WIDTH),
 		.BIT_WIDTH_1(PORT_R_WIDTH),
-		.BLK_SEL(3'b000),
+		.BLK_SEL_0(3'b000),
+		.BLK_SEL_1(3'b000),
 		.RESET_MODE(OPTION_RESET_MODE),
 	) _TECHMAP_REPLACE_ (
-		.BLKSEL(3'b000),
+		.BLKSELA(3'b000),
+		.BLKSELB(3'b000),
 
 		.CLKA(PORT_W_CLK),
-		.CEA(PORT_W_CLK_EN),
-		.WREA(WRE),
+		.CEA(WRE),
 		.RESETA(1'b0),
 		.ADA(ADW),
 		.DI(DI),
 
 		.CLKB(PORT_R_CLK),
 		.CEB(PORT_R_CLK_EN),
-		.WREB(1'b0),
 		.RESETB(RST),
-		.OCE(1'b0),
+		.OCE(1'b1),
 		.ADB(PORT_R_ADDR),
 		.DO(DO),
 	);
diff --git a/yosys/techlibs/gowin/cells_sim.v b/yosys/techlibs/gowin/cells_sim.v
index 86bd677e229..b268690803f 100644
--- a/yosys/techlibs/gowin/cells_sim.v
+++ b/yosys/techlibs/gowin/cells_sim.v
@@ -197,7 +197,7 @@ module DFFE (output reg Q, input D, CLK, CE);
   end
 endmodule // DFFE (positive clock edge; clock enable)
 
-(* abc9_box, lib_whitebox *)
+(* abc9_flop, lib_whitebox *)
 module DFFS (output reg Q, input D, CLK, SET);
   parameter [0:0] INIT = 1'b1;
   initial Q = INIT;
@@ -216,7 +216,7 @@ module DFFS (output reg Q, input D, CLK, SET);
   end
 endmodule // DFFS (positive clock edge; synchronous set)
 
-(* abc9_box, lib_whitebox *)
+(* abc9_flop, lib_whitebox *)
 module DFFSE (output reg Q, input D, CLK, CE, SET);
   parameter [0:0] INIT = 1'b1;
   initial Q = INIT;
@@ -282,7 +282,7 @@ module DFFP (output reg Q, input D, CLK, PRESET);
 
 	specify
 		(posedge CLK => (Q : D)) = (480, 660);
-		(posedge PRESET => (Q : 1'b1)) = (1800, 2679);
+		(PRESET => Q) = (1800, 2679);
 		$setup(D, posedge CLK, 576);
 	endspecify
 
@@ -301,7 +301,7 @@ module DFFPE (output reg Q, input D, CLK, CE, PRESET);
 
 	specify
 		if (CE) (posedge CLK => (Q : D)) = (480, 660);
-		(posedge PRESET => (Q : 1'b1)) = (1800, 2679);
+		(PRESET => Q) = (1800, 2679);
 		$setup(D, posedge CLK &&& CE, 576);
 		$setup(CE, posedge CLK, 63);
 	endspecify
@@ -321,7 +321,7 @@ module DFFC (output reg Q, input D, CLK, CLEAR);
 
 	specify
 		(posedge CLK => (Q : D)) = (480, 660);
-		(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
+		(CLEAR => Q) = (1800, 2679);
 		$setup(D, posedge CLK, 576);
 	endspecify
 
@@ -340,7 +340,7 @@ module DFFCE (output reg Q, input D, CLK, CE, CLEAR);
 
 	specify
 		if (CE) (posedge CLK => (Q : D)) = (480, 660);
-		(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
+		(CLEAR => Q) = (1800, 2679);
 		$setup(D, posedge CLK &&& CE, 576);
 		$setup(CE, posedge CLK, 63);
 	endspecify
@@ -384,7 +384,7 @@ module DFFNE (output reg Q, input D, CLK, CE);
   end
 endmodule // DFFNE (negative clock edge; clock enable)
 
-(* abc9_box, lib_whitebox *)
+(* abc9_flop, lib_whitebox *)
 module DFFNS (output reg Q, input D, CLK, SET);
   parameter [0:0] INIT = 1'b1;
   initial Q = INIT;
@@ -403,7 +403,7 @@ module DFFNS (output reg Q, input D, CLK, SET);
   end
 endmodule // DFFNS (negative clock edge; synchronous set)
 
-(* abc9_box, lib_whitebox *)
+(* abc9_flop, lib_whitebox *)
 module DFFNSE (output reg Q, input D, CLK, CE, SET);
   parameter [0:0] INIT = 1'b1;
   initial Q = INIT;
@@ -469,7 +469,7 @@ module DFFNP (output reg Q, input D, CLK, PRESET);
 
 	specify
 		(negedge CLK => (Q : D)) = (480, 660);
-		(posedge PRESET => (Q : 1'b1)) = (1800, 2679);
+		(PRESET => Q) = (1800, 2679);
 		$setup(D, negedge CLK, 576);
 	endspecify
 
@@ -488,7 +488,7 @@ module DFFNPE (output reg Q, input D, CLK, CE, PRESET);
   
 	specify
 		if (CE) (negedge CLK => (Q : D)) = (480, 660);
-		(posedge PRESET => (Q : 1'b1)) = (1800, 2679);
+		(PRESET => Q) = (1800, 2679);
 		$setup(D, negedge CLK &&& CE, 576);
 		$setup(CE, negedge CLK, 63);
 	endspecify
@@ -508,7 +508,7 @@ module DFFNC (output reg Q, input D, CLK, CLEAR);
 
 	specify
 		(negedge CLK => (Q : D)) = (480, 660);
-		(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
+		(CLEAR => Q) = (1800, 2679);
 		$setup(D, negedge CLK, 576);
 	endspecify
 
@@ -527,7 +527,7 @@ module DFFNCE (output reg Q, input D, CLK, CE, CLEAR);
 
 	specify
 		if (CE) (negedge CLK => (Q : D)) = (480, 660);
-		(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
+		(CLEAR => Q) = (1800, 2679);
 		$setup(D, negedge CLK &&& CE, 576);
 		$setup(CE, negedge CLK, 63);
 	endspecify
@@ -957,7 +957,7 @@ end
 
 endmodule
 
-
+(* abc9_flop, lib_whitebox *)
 module RAM16S1 (DO, DI, AD, WRE, CLK);
 
 parameter INIT_0 = 16'h0000;
@@ -992,7 +992,7 @@ end
 
 endmodule
 
-
+(* abc9_flop, lib_whitebox *)
 module RAM16S2 (DO, DI, AD, WRE, CLK);
 
 parameter INIT_0 = 16'h0000;
@@ -1031,7 +1031,7 @@ end
 
 endmodule
 
-
+(* abc9_flop, lib_whitebox *)
 module RAM16S4 (DO, DI, AD, WRE, CLK);
 
 parameter INIT_0 = 16'h0000;
diff --git a/yosys/techlibs/gowin/synth_gowin.cc b/yosys/techlibs/gowin/synth_gowin.cc
index 3b9d7424a7b..48b7563b1ec 100644
--- a/yosys/techlibs/gowin/synth_gowin.cc
+++ b/yosys/techlibs/gowin/synth_gowin.cc
@@ -78,8 +78,8 @@ struct SynthGowinPass : public ScriptPass
 		log("    -noalu\n");
 		log("        do not use ALU cells\n");
 		log("\n");
-		log("    -abc9\n");
-		log("        use new ABC9 flow (EXPERIMENTAL)\n");
+		log("    -noabc9\n");
+		log("        disable use of new ABC9 flow\n");
 		log("\n");
 		log("    -no-rw-check\n");
 		log("        marks all recognized read ports as \"return don't-care value on\n");
@@ -106,7 +106,7 @@ struct SynthGowinPass : public ScriptPass
 		nodffe = false;
 		nolutram = false;
 		nowidelut = false;
-		abc9 = false;
+		abc9 = true;
 		noiopads = false;
 		noalu = false;
 		no_rw_check = false;
@@ -130,7 +130,6 @@ struct SynthGowinPass : public ScriptPass
 			}
 			if (args[argidx] == "-json" && argidx+1 < args.size()) {
 				json_file = args[++argidx];
-				nobram = true;
 				continue;
 			}
 			if (args[argidx] == "-run" && argidx+1 < args.size()) {
@@ -170,7 +169,11 @@ struct SynthGowinPass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-abc9") {
-				abc9 = true;
+				// removed, ABC9 is on by default.
+				continue;
+			}
+			if (args[argidx] == "-noabc9") {
+				abc9 = false;
 				continue;
 			}
 			if (args[argidx] == "-noiopads") {
@@ -227,12 +230,14 @@ struct SynthGowinPass : public ScriptPass
 		if (check_label("map_ram"))
 		{
 			std::string args = "";
-			if (nobram)
-				args += " -no-auto-block";
-			if (nolutram)
-				args += " -no-auto-distributed";
 			if (help_mode)
 				args += " [-no-auto-block] [-no-auto-distributed]";
+			else {
+				if (nobram)
+					args += " -no-auto-block";
+				if (nolutram)
+					args += " -no-auto-distributed";
+			}
 			run("memory_libmap -lib +/gowin/lutrams.txt -lib +/gowin/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
 			run("techmap -map +/gowin/lutrams_map.v -map +/gowin/brams_map.v");
 		}
diff --git a/yosys/techlibs/ice40/synth_ice40.cc b/yosys/techlibs/ice40/synth_ice40.cc
index 2ae859efe32..81832389269 100644
--- a/yosys/techlibs/ice40/synth_ice40.cc
+++ b/yosys/techlibs/ice40/synth_ice40.cc
@@ -106,8 +106,8 @@ struct SynthIce40Pass : public ScriptPass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
-		log("    -abc9\n");
-		log("        use new ABC9 flow (EXPERIMENTAL)\n");
+		log("    -noabc9\n");
+		log("        disable use of new ABC9 flow\n");
 		log("\n");
 		log("    -flowmap\n");
 		log("        use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)\n");
@@ -144,7 +144,7 @@ struct SynthIce40Pass : public ScriptPass
 		noabc = false;
 		abc2 = false;
 		vpr = false;
-		abc9 = false;
+		abc9 = true;
 		flowmap = false;
 		device_opt = "hx";
 		no_rw_check = false;
@@ -235,7 +235,11 @@ struct SynthIce40Pass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-abc9") {
-				abc9 = true;
+				// removed, ABC9 is on by default.
+				continue;
+			}
+			if (args[argidx] == "-noabc9") {
+				abc9 = false;
 				continue;
 			}
 			if (args[argidx] == "-dff") {
@@ -349,12 +353,14 @@ struct SynthIce40Pass : public ScriptPass
 		if (check_label("map_ram"))
 		{
 			std::string args = "";
-			if (!spram)
-				args += " -no-auto-huge";
-			if (nobram)
-				args += " -no-auto-block";
 			if (help_mode)
 				args += " [-no-auto-huge] [-no-auto-block]";
+			else {
+				if (!spram)
+					args += " -no-auto-huge";
+				if (nobram)
+					args += " -no-auto-block";
+			}
 			run("memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt" + args, "(-no-auto-huge unless -spram, -no-auto-block if -nobram)");
 			run("techmap -map +/ice40/brams_map.v -map +/ice40/spram_map.v");
 			run("ice40_braminit");
@@ -428,7 +434,7 @@ struct SynthIce40Pass : public ScriptPass
 			run("ice40_wrapcarry -unwrap");
 			run("techmap -map +/ice40/ff_map.v");
 			run("clean");
-			run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 -dlogic SB_CARRY:CO=3");
+			run("opt_lut -tech ice40");
 		}
 
 		if (check_label("map_cells"))
diff --git a/yosys/techlibs/ice40/tests/test_bram.sh b/yosys/techlibs/ice40/tests/test_bram.sh
index d4d641a9c82..5c30db64411 100644
--- a/yosys/techlibs/ice40/tests/test_bram.sh
+++ b/yosys/techlibs/ice40/tests/test_bram.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -ex
 
diff --git a/yosys/techlibs/ice40/tests/test_dsp_map.sh b/yosys/techlibs/ice40/tests/test_dsp_map.sh
index 3f7f134e4c3..8523a4676e4 100644
--- a/yosys/techlibs/ice40/tests/test_dsp_map.sh
+++ b/yosys/techlibs/ice40/tests/test_dsp_map.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -ex
 
 for iter in {1..100}
diff --git a/yosys/techlibs/ice40/tests/test_dsp_model.sh b/yosys/techlibs/ice40/tests/test_dsp_model.sh
index 1e564d1b297..c79456f7086 100644
--- a/yosys/techlibs/ice40/tests/test_dsp_model.sh
+++ b/yosys/techlibs/ice40/tests/test_dsp_model.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -ex
 sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
 if [ ! -f "test_dsp_model_ref.v" ]; then
diff --git a/yosys/techlibs/ice40/tests/test_ffs.sh b/yosys/techlibs/ice40/tests/test_ffs.sh
index ff79ec534b7..438629c3e1b 100644
--- a/yosys/techlibs/ice40/tests/test_ffs.sh
+++ b/yosys/techlibs/ice40/tests/test_ffs.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -ex
 for CLKPOL in 0 1; do
 for ENABLE_EN in 0 1; do
diff --git a/yosys/techlibs/intel_alm/Makefile.inc b/yosys/techlibs/intel_alm/Makefile.inc
index b5f279a921c..9e24d695e85 100644
--- a/yosys/techlibs/intel_alm/Makefile.inc
+++ b/yosys/techlibs/intel_alm/Makefile.inc
@@ -20,10 +20,7 @@ $(eval $(call add_share_file,share/intel_alm/cyclonev,techlibs/intel_alm/cyclone
 # RAM
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k_map.v))
-$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k.txt))
-$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k_map.v))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
 
 # Miscellaneous
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/megafunction_bb.v))
-$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/quartus_rename.v))
diff --git a/yosys/techlibs/intel_alm/common/alm_sim.v b/yosys/techlibs/intel_alm/common/alm_sim.v
index d3bd673903f..858e43c76cc 100644
--- a/yosys/techlibs/intel_alm/common/alm_sim.v
+++ b/yosys/techlibs/intel_alm/common/alm_sim.v
@@ -1,4 +1,4 @@
-// The core logic primitive of the Cyclone V/10GX is the Adaptive Logic Module
+// The core logic primitive of the Cyclone V is the Adaptive Logic Module
 // (ALM). Each ALM is made up of an 8-input, 2-output look-up table, covered
 // in this file, connected to combinational outputs, a carry chain, and four
 // D flip-flops (which are covered as MISTRAL_FF in dff_sim.v).
@@ -77,14 +77,6 @@
 //   SUMOUT  368 1342 1323  887 927   -  785   -
 // CARRYOUT   71 1082 1062  866 813   - 1198   -
 
-// Arria V LUT output timings (picoseconds):
-//
-//          CARRY   A    B    C   D   E    F   G
-//  COMBOUT    -  387  375  316 317   -   76 319 (LUT6)
-//  COMBOUT    -  387  375  316 317 218   76 319 (LUT7)
-//   SUMOUT  249  744  732  562 576   -  511   -
-// CARRYOUT   19  629  623  530 514   -  696   -
-
 (* abc9_lut=2, lib_whitebox *)
 module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
 
@@ -100,26 +92,6 @@ specify
     (F => Q) = 97;
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A => Q) = 387;
-    (B => Q) = 375;
-    (C => Q) = 316;
-    (D => Q) = 317;
-    (E => Q) = 319;
-    (F => Q) = 76;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A => Q) = 275;
-    (B => Q) = 272;
-    (C => Q) = 175;
-    (D => Q) = 165;
-    (E => Q) = 162;
-    (F => Q) = 53;
-endspecify
-`endif
 
 assign Q = LUT >> {F, E, D, C, B, A};
 
@@ -140,24 +112,6 @@ specify
     (E => Q) = 97;
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A => Q) = 375;
-    (B => Q) = 316;
-    (C => Q) = 317;
-    (D => Q) = 319;
-    (E => Q) = 76;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A => Q) = 272;
-    (B => Q) = 175;
-    (C => Q) = 165;
-    (D => Q) = 162;
-    (E => Q) = 53;
-endspecify
-`endif
 
 assign Q = LUT >> {E, D, C, B, A};
 
@@ -177,22 +131,6 @@ specify
     (D => Q) = 97;
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A => Q) = 316;
-    (B => Q) = 317;
-    (C => Q) = 319;
-    (D => Q) = 76;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A => Q) = 175;
-    (B => Q) = 165;
-    (C => Q) = 162;
-    (D => Q) = 53;
-endspecify
-`endif
 
 assign Q = LUT >> {D, C, B, A};
 
@@ -211,20 +149,6 @@ specify
     (C => Q) = 97;
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A => Q) = 316;
-    (B => Q) = 317;
-    (C => Q) = 76;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A => Q) = 165;
-    (B => Q) = 162;
-    (C => Q) = 53;
-endspecify
-`endif
 
 assign Q = LUT >> {C, B, A};
 
@@ -242,18 +166,6 @@ specify
     (B => Q) = 97;
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A => Q) = 316;
-    (B => Q) = 76;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A => Q) = 162;
-    (B => Q) = 53;
-endspecify
-`endif
 
 assign Q = LUT >> {B, A};
 
@@ -268,16 +180,6 @@ specify
     (A => Q) = 97;
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A => Q) = 76;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A => Q) = 53;
-endspecify
-`endif
 
 assign Q = ~A;
 
@@ -306,40 +208,6 @@ specify
     (CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
 endspecify
 `endif
-`ifdef arriav
-specify
-    (A  => SO) = 744;
-    (B  => SO) = 732;
-    (C  => SO) = 562;
-    (D0 => SO) = 576;
-    (D1 => SO) = 511;
-    (CI => SO) = 249;
-
-    (A  => CO) = 629;
-    (B  => CO) = 623;
-    (C  => CO) = 530;
-    (D0 => CO) = 514;
-    (D1 => CO) = 696;
-    (CI => CO) = 10; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    (A  => SO) = 644;
-    (B  => SO) = 477;
-    (C  => SO) = 416;
-    (D0 => SO) = 380;
-    (D1 => SO) = 431;
-    (CI => SO) = 276;
-
-    (A  => CO) = 525;
-    (B  => CO) = 433;
-    (C  => CO) = 712;
-    (D0 => CO) = 653;
-    (D1 => CO) = 593;
-    (CI => CO) = 16;
-endspecify
-`endif
 
 wire q0, q1;
 
@@ -349,283 +217,3 @@ assign q1 = LUT1 >> {D1, C, B, A};
 assign {CO, SO} = q0 + !q1 + CI;
 
 endmodule
-
-
-/*
-// A, B, C0, C1, E0, E1, F0, F1: data inputs
-// CARRYIN: carry input
-// SHAREIN: shared-arithmetic input
-// CLK0, CLK1, CLK2: clock inputs
-//
-// COMB0, COMB1: combinational outputs
-// FF0, FF1, FF2, FF3: DFF outputs
-// SUM0, SUM1: adder outputs
-// CARRYOUT: carry output
-// SHAREOUT: shared-arithmetic output
-module MISTRAL_ALM(
-    input A, B, C0, C1, E0, E1, F0, F1, CARRYIN, SHAREIN, // LUT path
-    input CLK0, CLK1, CLK2, AC0, AC1,                     // FF path
-    output COMB0, COMB1, SUM0, SUM1, CARRYOUT, SHAREOUT,
-    output FF0, FF1, FF2, FF3
-);
-
-parameter LUT0 = 16'b0000;
-parameter LUT1 = 16'b0000;
-parameter LUT2 = 16'b0000;
-parameter LUT3 = 16'b0000;
-
-parameter INIT0 = 1'b0;
-parameter INIT1 = 1'b0;
-parameter INIT2 = 1'b0;
-parameter INIT3 = 1'b0;
-
-parameter C0_MUX = "C0";
-parameter C1_MUX = "C1";
-
-parameter F0_MUX = "VCC";
-parameter F1_MUX = "GND";
-
-parameter FEEDBACK0 = "FF0";
-parameter FEEDBACK1 = "FF2";
-
-parameter ADD_MUX = "LUT";
-
-parameter DFF01_DATA_MUX = "COMB";
-parameter DFF23_DATA_MUX = "COMB";
-
-parameter DFF0_CLK = "CLK0";
-parameter DFF1_CLK = "CLK0";
-parameter DFF2_CLK = "CLK0";
-parameter DFF3_CLK = "CLK0";
-
-parameter DFF0_AC  = "AC0";
-parameter DFF1_AC  = "AC0";
-parameter DFF2_AC  = "AC0";
-parameter DFF3_AC  = "AC0";
-
-// Feedback muxes from the flip-flop outputs.
-wire ff_feedback_mux0, ff_feedback_mux1;
-
-// C-input muxes which can be set to also use the F-input.
-wire c0_input_mux, c1_input_mux;
-
-// F-input muxes which can be set to a constant to allow LUT5 use.
-wire f0_input_mux, f1_input_mux;
-
-// Adder input muxes to select between shared-arithmetic mode and arithmetic mode.
-wire add0_input_mux, add1_input_mux;
-
-// Combinational-output muxes for LUT #1 and LUT #3
-wire lut1_comb_mux, lut3_comb_mux;
-
-// Sum-output muxes for LUT #1 and LUT #3
-wire lut1_sum_mux, lut3_sum_mux;
-
-// DFF data-input muxes
-wire dff01_data_mux, dff23_data_mux;
-
-// DFF clock selectors
-wire dff0_clk, dff1_clk, dff2_clk, dff3_clk;
-
-// DFF asynchronous-clear selectors
-wire dff0_ac, dff1_ac, dff2_ac, dff3_ac;
-
-// LUT, DFF and adder output wires for routing.
-wire lut0_out, lut1a_out, lut1b_out, lut2_out, lut3a_out, lut3b_out;
-wire dff0_out, dff1_out, dff2_out, dff3_out;
-wire add0_sum, add1_sum, add0_carry, add1_carry;
-
-generate
-    if (FEEDBACK0 === "FF0")
-        assign ff_feedback_mux0 = dff0_out;
-    else if (FEEDBACK0 === "FF1")
-        assign ff_feedback_mux0 = dff1_out;
-    else
-        $error("Invalid FEEDBACK0 setting!");
-
-    if (FEEDBACK1 == "FF2")
-        assign ff_feedback_mux1 = dff2_out;
-    else if (FEEDBACK1 == "FF3")
-        assign ff_feedback_mux1 = dff3_out;
-    else
-        $error("Invalid FEEDBACK1 setting!");
-
-    if (C0_MUX === "C0")
-        assign c0_input_mux = C0;
-    else if (C0_MUX === "F1")
-        assign c0_input_mux = F1;
-    else if (C0_MUX === "FEEDBACK1")
-        assign c0_input_mux = ff_feedback_mux1;
-    else
-        $error("Invalid C0_MUX setting!");
-
-    if (C1_MUX === "C1")
-        assign c1_input_mux = C1;
-    else if (C1_MUX === "F0")
-        assign c1_input_mux = F0;
-    else if (C1_MUX === "FEEDBACK0")
-        assign c1_input_mux = ff_feedback_mux0;
-    else
-        $error("Invalid C1_MUX setting!");
-
-    // F0 == VCC is LUT5
-    // F0 == F0 is LUT6
-    // F0 == FEEDBACK is unknown
-    if (F0_MUX === "VCC")
-        assign f0_input_mux = 1'b1;
-    else if (F0_MUX === "F0")
-        assign f0_input_mux = F0;
-    else if (F0_MUX === "FEEDBACK0")
-        assign f0_input_mux = ff_feedback_mux0;
-    else
-        $error("Invalid F0_MUX setting!");
-
-    // F1 == GND is LUT5
-    // F1 == F1 is LUT6
-    // F1 == FEEDBACK is unknown
-    if (F1_MUX === "GND")
-        assign f1_input_mux = 1'b0;
-    else if (F1_MUX === "F1")
-        assign f1_input_mux = F1;
-    else if (F1_MUX === "FEEDBACK1")
-        assign f1_input_mux = ff_feedback_mux1;
-    else
-        $error("Invalid F1_MUX setting!");
-
-    if (ADD_MUX === "LUT") begin
-        assign add0_input_mux = ~lut1_sum_mux;
-        assign add1_input_mux = ~lut3_sum_mux;
-    end else if (ADD_MUX === "SHARE") begin
-        assign add0_input_mux = SHAREIN;
-        assign add1_input_mux = lut1_comb_mux;
-    end else
-        $error("Invalid ADD_MUX setting!");
-
-    if (DFF01_DATA_MUX === "COMB")
-        assign dff01_data_mux = COMB0;
-    else if (DFF01_DATA_MUX === "SUM")
-        assign dff01_data_mux = SUM0;
-    else
-        $error("Invalid DFF01_DATA_MUX setting!");
-
-    if (DFF23_DATA_MUX === "COMB")
-        assign dff23_data_mux = COMB0;
-    else if (DFF23_DATA_MUX === "SUM")
-        assign dff23_data_mux = SUM0;
-    else
-        $error("Invalid DFF23_DATA_MUX setting!");
-
-    if (DFF0_CLK === "CLK0")
-        assign dff0_clk = CLK0;
-    else if (DFF0_CLK === "CLK1")
-        assign dff0_clk = CLK1;
-    else if (DFF0_CLK === "CLK2")
-        assign dff0_clk = CLK2;
-    else
-        $error("Invalid DFF0_CLK setting!");
-
-    if (DFF1_CLK === "CLK0")
-        assign dff1_clk = CLK0;
-    else if (DFF1_CLK === "CLK1")
-        assign dff1_clk = CLK1;
-    else if (DFF1_CLK === "CLK2")
-        assign dff1_clk = CLK2;
-    else
-        $error("Invalid DFF1_CLK setting!");
-
-    if (DFF2_CLK === "CLK0")
-        assign dff2_clk = CLK0;
-    else if (DFF2_CLK === "CLK1")
-        assign dff2_clk = CLK1;
-    else if (DFF2_CLK === "CLK2")
-        assign dff2_clk = CLK2;
-    else
-        $error("Invalid DFF2_CLK setting!");
-
-    if (DFF3_CLK === "CLK0")
-        assign dff3_clk = CLK0;
-    else if (DFF3_CLK === "CLK1")
-        assign dff3_clk = CLK1;
-    else if (DFF3_CLK === "CLK2")
-        assign dff3_clk = CLK2;
-    else
-        $error("Invalid DFF3_CLK setting!");
-
-    if (DFF0_AC === "AC0")
-        assign dff0_ac = AC0;
-    else if (DFF0_AC === "AC1")
-        assign dff0_ac = AC1;
-    else
-        $error("Invalid DFF0_AC setting!");
-
-    if (DFF1_AC === "AC0")
-        assign dff1_ac = AC0;
-    else if (DFF1_AC === "AC1")
-        assign dff1_ac = AC1;
-    else
-        $error("Invalid DFF1_AC setting!");
-
-    if (DFF2_AC === "AC0")
-        assign dff2_ac = AC0;
-    else if (DFF2_AC === "AC1")
-        assign dff2_ac = AC1;
-    else
-        $error("Invalid DFF2_AC setting!");
-
-    if (DFF3_AC === "AC0")
-        assign dff3_ac = AC0;
-    else if (DFF3_AC === "AC1")
-        assign dff3_ac = AC1;
-    else
-        $error("Invalid DFF3_AC setting!");
-
-endgenerate
-
-// F0 on the Quartus diagram
-MISTRAL_ALUT4 #(.LUT(LUT0)) lut0 (.A(A), .B(B), .C(C0), .D(c1_input_mux), .Q(lut0_out));
-
-// F2 on the Quartus diagram
-MISTRAL_ALUT4 #(.LUT(LUT1)) lut1_comb (.A(A), .B(B), .C(C0), .D(c1_input_mux), .Q(lut1_comb_mux));
-MISTRAL_ALUT4 #(.LUT(LUT1)) lut1_sum  (.A(A), .B(B), .C(C0), .D(E0), .Q(lut1_sum_mux));
-
-// F1 on the Quartus diagram
-MISTRAL_ALUT4 #(.LUT(LUT2)) lut2 (.A(A), .B(B), .C(C1), .D(c0_input_mux), .Q(lut2_out));
-
-// F3 on the Quartus diagram
-MISTRAL_ALUT4 #(.LUT(LUT3)) lut3_comb (.A(A), .B(B), .C(C1), .D(c0_input_mux), .Q(lut3_comb_mux));
-MISTRAL_ALUT4 #(.LUT(LUT3)) lut3_sum  (.A(A), .B(B), .C(C1), .D(E1), .Q(lut3_sum_mux));
-
-MISTRAL_FF #(.INIT(INIT0)) dff0 (.D(dff01_data_mux), .CLK(dff0_clk), .ACn(dff0_ac), .Q(dff0_out));
-MISTRAL_FF #(.INIT(INIT1)) dff1 (.D(dff01_data_mux), .CLK(dff1_clk), .ACn(dff1_ac), .Q(dff1_out));
-MISTRAL_FF #(.INIT(INIT2)) dff2 (.D(dff23_data_mux), .CLK(dff2_clk), .ACn(dff2_ac), .Q(dff2_out));
-MISTRAL_FF #(.INIT(INIT3)) dff3 (.D(dff23_data_mux), .CLK(dff3_clk), .ACn(dff3_ac), .Q(dff3_out));
-
-// Adders
-assign {add0_carry, add0_sum} = CARRYIN + lut0_out + lut1_sum_mux;
-assign {add1_carry, add1_sum} = add0_carry + lut2_out + lut3_sum_mux;
-
-// COMBOUT outputs on the Quartus diagram
-assign COMB0 = E0 ? (f0_input_mux ? lut3_comb_mux : lut1_comb_mux)
-                    : (f0_input_mux ? lut2_out : lut0_out);
-
-assign COMB1 = E1 ? (f1_input_mux ? lut3_comb_mux : lut1_comb_mux)
-                    : (f1_input_mux ? lut2_out : lut0_out);
-
-// SUMOUT output on the Quartus diagram
-assign SUM0 = add0_sum;
-assign SUM1 = add1_sum;
-
-// COUT output on the Quartus diagram
-assign CARRYOUT = add1_carry;
-
-// SHAREOUT output on the Quartus diagram
-assign SHAREOUT = lut3_comb_mux;
-
-// REGOUT outputs on the Quartus diagram
-assign FF0 = dff0_out;
-assign FF1 = dff1_out;
-assign FF2 = dff2_out;
-assign FF3 = dff3_out;
-
-endmodule
-*/
diff --git a/yosys/techlibs/intel_alm/common/bram_m20k.txt b/yosys/techlibs/intel_alm/common/bram_m20k.txt
deleted file mode 100644
index b4c5a537287..00000000000
--- a/yosys/techlibs/intel_alm/common/bram_m20k.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-bram __MISTRAL_M20K_SDP
-    init   1   # TODO: Re-enable when I figure out how BRAM init works
-    abits 14   @D16384x1
-    dbits  1   @D16384x1
-    abits 13   @D8192x2
-    dbits  2   @D8192x2
-    abits 12   @D4096x4 @D4096x5
-    dbits  4   @D4096x4
-    dbits  5   @D4096x5
-    abits 11   @D2048x8 @D2048x10
-    dbits  8   @D2048x8
-    dbits 10   @D2048x10
-    abits 10   @D1024x16 @D1024x20
-    dbits 16   @D1024x16
-    dbits 20   @D1024x20
-    abits  9   @D512x32 @D512x40
-    dbits 32   @D512x32
-    dbits 40   @D512x40
-    groups 2
-    ports  1 1
-    wrmode 1 0
-    # read enable; write enable + byte enables (only for multiples of 8)
-    enable 1 1
-    transp 0 0
-    clocks 1 1
-    clkpol 1 1
-endbram
-
-
-match __MISTRAL_M20K_SDP
-    min efficiency 5
-    make_transp
-endmatch
diff --git a/yosys/techlibs/intel_alm/common/bram_m20k_map.v b/yosys/techlibs/intel_alm/common/bram_m20k_map.v
deleted file mode 100644
index 15739d66a2e..00000000000
--- a/yosys/techlibs/intel_alm/common/bram_m20k_map.v
+++ /dev/null
@@ -1,31 +0,0 @@
-module __MISTRAL_M20K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
-
-parameter CFG_ABITS = 10;
-parameter CFG_DBITS = 20;
-parameter CFG_ENABLE_A = 1;
-parameter CFG_ENABLE_B = 1;
-
-input CLK1;
-input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
-input [CFG_DBITS-1:0] A1DATA;
-output [CFG_DBITS-1:0] B1DATA;
-input [CFG_ENABLE_A-1:0] A1EN, B1EN;
-
-altsyncram #(
-    .operation_mode("dual_port"),
-    .ram_block_type("m20k"),
-    .widthad_a(CFG_ABITS),
-    .width_a(CFG_DBITS),
-    .widthad_b(CFG_ABITS),
-    .width_b(CFG_DBITS),
-) _TECHMAP_REPLACE_ (
-    .address_a(A1ADDR),
-    .data_a(A1DATA),
-    .wren_a(A1EN),
-    .address_b(B1ADDR),
-    .q_b(B1DATA),
-    .clock0(CLK1),
-    .clock1(CLK1)
-);
-
-endmodule
diff --git a/yosys/techlibs/intel_alm/common/dff_sim.v b/yosys/techlibs/intel_alm/common/dff_sim.v
index 8d58bf61485..a558973f9fd 100644
--- a/yosys/techlibs/intel_alm/common/dff_sim.v
+++ b/yosys/techlibs/intel_alm/common/dff_sim.v
@@ -77,38 +77,6 @@ specify
     if (ACLR === 1'b0) (ACLR => Q) = 282;
 endspecify
 `endif
-`ifdef arriav
-specify
-    if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 470;
-    if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 633;
-    if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 439;
-
-    $setup(DATAIN, posedge CLK, /* -170 */ 0);
-    $setup(ENA, posedge CLK, /* -170 */ 0);
-    $setup(SCLR, posedge CLK, /* -170 */ 0);
-    $setup(SLOAD, posedge CLK, /* -170 */ 0);
-    $setup(SDATA, posedge CLK, /* -170 */ 0);
-
-    if (ACLR === 1'b0) (ACLR => Q) = 215;
-endspecify
-`endif
-`ifdef cyclone10gx
-specify
-    // TODO (long-term): investigate these numbers.
-    // It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly.
-    if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 219;
-    if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 219;
-    if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 219;
-
-    $setup(DATAIN, posedge CLK, 268);
-    $setup(ENA, posedge CLK, 268);
-    $setup(SCLR, posedge CLK, 268);
-    $setup(SLOAD, posedge CLK, 268);
-    $setup(SDATA, posedge CLK, 268);
-
-    if (ACLR === 1'b0) (ACLR => Q) = 0;
-endspecify
-`endif
 
 initial begin
     // Altera flops initialise to zero.
diff --git a/yosys/techlibs/intel_alm/common/mem_sim.v b/yosys/techlibs/intel_alm/common/mem_sim.v
index 563f1d2413e..5ab1b73261f 100644
--- a/yosys/techlibs/intel_alm/common/mem_sim.v
+++ b/yosys/techlibs/intel_alm/common/mem_sim.v
@@ -1,7 +1,7 @@
 // The MLAB
 // --------
 // In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic
-// Modules (ALMs, see alm_sim.v), the Cyclone V/10GX also contain
+// Modules (ALMs, see alm_sim.v), the Cyclone V also contains
 // Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise
 // the memory the ALM uses to store the look-up table data for general usage,
 // producing a 32 address by 20-bit block of memory. MLABs are spread out
@@ -14,11 +14,8 @@
 // or shift registers (by using the output of the Nth bit as input for the N+1th
 // bit).
 //
-// Oddly, instead of providing a block 32 address by 20-bit cell, Quartus asks
-// synthesis tools to build MLABs out of 32 address by 1-bit cells, and tries
-// to put these cells in the same MLAB during cell placement. Because of this
-// a MISTRAL_MLAB cell represents one of these 32 address by 1-bit cells, and
-// 20 of them represent a physical MLAB.
+// For historical reasons a MISTRAL_MLAB cell represents a 32 address by 1-bit cell,
+// and 20 of them represent a physical MLAB.
 //
 // How the MLAB works
 // ------------------
@@ -28,10 +25,7 @@
 // by the Yosys `memory_bram` pass, and it doesn't make sense to me to use
 // `techmap` just for the sake of renaming the cell ports.
 //
-// The MLAB can be initialised to any value, but unfortunately Quartus only
-// allows memory initialisation from a file. Since Yosys doesn't preserve input
-// file information, or write the contents of an `initial` block to a file,
-// Yosys can't currently initialise the MLAB in a way Quartus will accept.
+// The MLAB can be initialised to any value.
 //
 // The MLAB takes in data from A1DATA at the rising edge of CLK1, and if A1EN
 // is high, writes it to the address in A1ADDR. A1EN can therefore be used to
@@ -39,9 +33,7 @@
 //
 // Simultaneously, the MLAB reads data from B1ADDR, and outputs it to B1DATA,
 // asynchronous to CLK1 and ignoring A1EN. If a synchronous read is needed
-// then the output can be fed to embedded flops. Presently, Yosys assumes
-// Quartus will pack external flops into the MLAB, but this is an assumption
-// that needs testing.
+// then the output can be fed to embedded flops.
 
 // The vendor sim model outputs 'x for a very short period (a few
 // combinational delta cycles) after each write. This has been omitted from
@@ -69,33 +61,6 @@ specify
     (B1ADDR[4] => B1DATA) = 96;
 endspecify
 `endif
-`ifdef arriav
-specify
-    $setup(A1ADDR, posedge CLK1, 62);
-    $setup(A1DATA, posedge CLK1, 62);
-    $setup(A1EN, posedge CLK1, 62);
-
-    (B1ADDR[0] => B1DATA) = 370;
-    (B1ADDR[1] => B1DATA) = 292;
-    (B1ADDR[2] => B1DATA) = 218;
-    (B1ADDR[3] => B1DATA) = 74;
-    (B1ADDR[4] => B1DATA) = 177;
-endspecify
-`endif
-`ifdef cyclone10gx
-// TODO: Cyclone 10 GX timings; the below timings are for Cyclone V
-specify
-    $setup(A1ADDR, posedge CLK1, 86);
-    $setup(A1DATA, posedge CLK1, 86);
-    $setup(A1EN, posedge CLK1, 86);
-
-    (B1ADDR[0] => B1DATA) = 487;
-    (B1ADDR[1] => B1DATA) = 475;
-    (B1ADDR[2] => B1DATA) = 382;
-    (B1ADDR[3] => B1DATA) = 284;
-    (B1ADDR[4] => B1DATA) = 96;
-endspecify
-`endif
 
 always @(posedge CLK1)
     if (A1EN) mem[A1ADDR] <= A1DATA;
@@ -134,17 +99,6 @@ specify
     if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 1004;
 endspecify
 `endif
-`ifdef arriav
-specify
-    $setup(A1ADDR, posedge CLK1, 97);
-    $setup(A1DATA, posedge CLK1, 74);
-    $setup(A1EN, posedge CLK1, 109);
-    $setup(B1ADDR, posedge CLK1, 97);
-    $setup(B1EN, posedge CLK1, 126);
-
-    if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 787;
-endspecify
-`endif
 
 always @(posedge CLK1) begin
     if (!A1EN)
diff --git a/yosys/techlibs/intel_alm/common/quartus_rename.v b/yosys/techlibs/intel_alm/common/quartus_rename.v
deleted file mode 100644
index 217dc5de98b..00000000000
--- a/yosys/techlibs/intel_alm/common/quartus_rename.v
+++ /dev/null
@@ -1,311 +0,0 @@
-`ifdef cyclonev
-`define LCELL cyclonev_lcell_comb
-`define MAC cyclonev_mac
-`define MLAB cyclonev_mlab_cell
-`define RAM_BLOCK cyclonev_ram_block
-`define IBUF cyclonev_io_ibuf
-`define OBUF cyclonev_io_obuf
-`define CLKENA cyclonev_clkena
-`endif
-`ifdef arriav
-`define LCELL arriav_lcell_comb
-`define MAC arriav_mac
-`define MLAB arriav_mlab_cell
-`define RAM_BLOCK arriav_ram_block
-`define IBUF arriav_io_ibuf
-`define OBUF arriav_io_obuf
-`define CLKENA arriav_clkena
-`endif
-`ifdef cyclone10gx
-`define LCELL cyclone10gx_lcell_comb
-`define MAC cyclone10gx_mac
-`define MLAB cyclone10gx_mlab_cell
-`define RAM_BLOCK cyclone10gx_ram_block
-`define IBUF cyclone10gx_io_ibuf
-`define OBUF cyclone10gx_io_obuf
-`define CLKENA cyclone10gx_clkena
-`endif
-
-module __MISTRAL_VCC(output Q);
-
-MISTRAL_ALUT2 #(.LUT(4'b1111)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
-
-endmodule
-
-
-module __MISTRAL_GND(output Q);
-
-MISTRAL_ALUT2 #(.LUT(4'b0000)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
-
-endmodule
-
-
-module MISTRAL_FF(input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA, output reg Q);
-
-dffeas #(.power_up("low"), .is_wysiwyg("true")) _TECHMAP_REPLACE_ (.d(DATAIN), .clk(CLK), .clrn(ACLR), .ena(ENA), .sclr(SCLR), .sload(SLOAD), .asdata(SDATA), .q(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
-parameter [63:0] LUT = 64'h0000_0000_0000_0000;
-
-`LCELL #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
-parameter [31:0] LUT = 32'h0000_0000;
-
-`LCELL #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT4(input A, B, C, D, output Q);
-parameter [15:0] LUT = 16'h0000;
-
-`LCELL #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT3(input A, B, C, output Q);
-parameter [7:0] LUT = 8'h00;
-
-`LCELL #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT2(input A, B, output Q);
-parameter [3:0] LUT = 4'h0;
-
-`LCELL #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
-
-endmodule
-
-
-module MISTRAL_NOT(input A, output Q);
-
-NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
-
-endmodule
-
-
-module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
-parameter LUT0 = 16'h0000;
-parameter LUT1 = 16'h0000;
-
-`LCELL #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
-
-endmodule
-
-
-module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
-
-parameter _TECHMAP_CELLNAME_ = "";
-
-// Here we get to an unfortunate situation. The cell has a mem_init0 parameter,
-// which takes in a hexadecimal string that could be used to initialise RAM.
-// In the vendor simulation models, this appears to work fine, but Quartus,
-// either intentionally or not, forgets about this parameter and initialises the
-// RAM to zero.
-//
-// Because of this, RAM initialisation is presently disabled, but the source
-// used to generate mem_init0 is kept (commented out) in case this gets fixed
-// or an undocumented way to get Quartus to initialise from mem_init0 is found.
-
-`MLAB #(
-    .logical_ram_name(_TECHMAP_CELLNAME_),
-    .logical_ram_depth(32),
-    .logical_ram_width(1),
-    .mixed_port_feed_through_mode("Dont Care"),
-    .first_bit_number(0),
-    .first_address(0),
-    .last_address(31),
-    .address_width(5),
-    .data_width(1),
-    .byte_enable_mask_width(1),
-    .port_b_data_out_clock("NONE"),
-    // .mem_init0($sformatf("%08x", INIT))
-) _TECHMAP_REPLACE_ (
-    .portaaddr(A1ADDR),
-    .portadatain(A1DATA),
-    .portbaddr(B1ADDR),
-    .portbdataout(B1DATA),
-    .ena0(A1EN),
-    .clk0(CLK1)
-);
-
-endmodule
-
-
-module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
-
-parameter CFG_ABITS = 10;
-parameter CFG_DBITS = 10;
-
-parameter _TECHMAP_CELLNAME_ = "";
-
-input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
-input [CFG_DBITS-1:0] A1DATA;
-input CLK1, A1EN, B1EN;
-output [CFG_DBITS-1:0] B1DATA;
-
-// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
-// you initialise the RAM cell via hex literals. If they were implemented.
-
-// Since the MISTRAL_M10K block has an inverted write-enable (like the real hardware)
-// but the Quartus primitive expects a normal write-enable, we add an inverter.
-wire A1EN_N;
-NOT wren_inv (.IN(A1EN), .OUT(A1EN_N));
-
-`RAM_BLOCK #(
-    .operation_mode("dual_port"),
-    .logical_ram_name(_TECHMAP_CELLNAME_),
-    .port_a_address_width(CFG_ABITS),
-    .port_a_data_width(CFG_DBITS),
-    .port_a_logical_ram_depth(2**CFG_ABITS),
-    .port_a_logical_ram_width(CFG_DBITS),
-    .port_a_first_address(0),
-    .port_a_last_address(2**CFG_ABITS - 1),
-    .port_a_first_bit_number(0),
-    .port_b_address_width(CFG_ABITS),
-    .port_b_data_width(CFG_DBITS),
-    .port_b_logical_ram_depth(2**CFG_ABITS),
-    .port_b_logical_ram_width(CFG_DBITS),
-    .port_b_first_address(0),
-    .port_b_last_address(2**CFG_ABITS - 1),
-    .port_b_first_bit_number(0),
-    .port_b_address_clock("clock0"),
-    .port_b_read_enable_clock("clock0")
-) ram_block (
-    .portaaddr(A1ADDR),
-    .portadatain(A1DATA),
-    .portawe(A1EN_N),
-    .portbaddr(B1ADDR),
-    .portbdataout(B1DATA),
-    .portbre(B1EN),
-    .clk0(CLK1)
-);
-
-endmodule
-
-
-module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
-
-parameter A_SIGNED = 1;
-parameter B_SIGNED = 1;
-
-`MAC #(
-    .ax_width(27),
-    .signed_max(A_SIGNED ? "true" : "false"),
-    .ay_scan_in_width(27),
-    .signed_may(B_SIGNED ? "true" : "false"),
-    .result_a_width(54),
-    .operation_mode("M27x27")
-) _TECHMAP_REPLACE_ (
-    .ax(A),
-    .ay(B),
-    .resulta(Y)
-);
-
-endmodule
-
-
-module MISTRAL_MUL18X18(input [17:0] A, B, output [35:0] Y);
-
-parameter A_SIGNED = 1;
-parameter B_SIGNED = 1;
-
-`MAC #(
-    .ax_width(18),
-    .signed_max(A_SIGNED ? "true" : "false"),
-    .ay_scan_in_width(18),
-    .signed_may(B_SIGNED ? "true" : "false"),
-    .result_a_width(36),
-    .operation_mode("M18x18_FULL")
-) _TECHMAP_REPLACE_ (
-    .ax(A),
-    .ay(B),
-    .resulta(Y)
-);
-
-endmodule
-
-
-module MISTRAL_MUL9X9(input [8:0] A, B, output [17:0] Y);
-
-parameter A_SIGNED = 1;
-parameter B_SIGNED = 1;
-
-`MAC #(
-    .ax_width(9),
-    .signed_max(A_SIGNED ? "true" : "false"),
-    .ay_scan_in_width(9),
-    .signed_may(B_SIGNED ? "true" : "false"),
-    .result_a_width(18),
-    .operation_mode("M9x9")
-) _TECHMAP_REPLACE_ (
-    .ax(A),
-    .ay(B),
-    .resulta(Y)
-);
-
-endmodule
-
-module MISTRAL_IB(input PAD, output O);
-`IBUF #(
-    .bus_hold("false"),
-    .differential_mode("false")
-) _TECHMAP_REPLACE_ (
-    .i(PAD),
-    .o(O)
-);
-endmodule
-
-module MISTRAL_OB(output PAD, input I, OE);
-`OBUF #(
-    .bus_hold("false"),
-    .differential_mode("false")
-) _TECHMAP_REPLACE_ (
-    .i(I),
-    .o(PAD),
-    .oe(OE)
-);
-endmodule
-
-module MISTRAL_IO(output PAD, input I, OE, output O);
-`IBUF #(
-    .bus_hold("false"),
-    .differential_mode("false")
-) ibuf (
-    .i(PAD),
-    .o(O)
-);
-
-`OBUF #(
-    .bus_hold("false"),
-    .differential_mode("false")
-) obuf (
-    .i(I),
-    .o(PAD),
-    .oe(OE)
-);
-endmodule
-
-module MISTRAL_CLKBUF (input A, output Q);
-`CLKENA #(
-    .clock_type("auto"),
-    .ena_register_mode("always enabled"),
-    .ena_register_power_up("high"),
-    .disable_mode("low"),
-    .test_syn("high")
-) _TECHMAP_REPLACE_ (
-    .inclk(A),
-    .ena(1'b1),
-    .outclk(Q)
-);
-endmodule
diff --git a/yosys/techlibs/intel_alm/synth_intel_alm.cc b/yosys/techlibs/intel_alm/synth_intel_alm.cc
index c33eb43bf35..cdae9586eb0 100644
--- a/yosys/techlibs/intel_alm/synth_intel_alm.cc
+++ b/yosys/techlibs/intel_alm/synth_intel_alm.cc
@@ -2,7 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
- *  Copyright (C) 2019  Dan Ravensloft <dan.ravensloft@gmail.com>
+ *  Copyright (C) 2019  Hannah Ravensloft <dan.ravensloft@gmail.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -43,21 +43,11 @@ struct SynthIntelALMPass : public ScriptPass {
 		log("    -family <family>\n");
 		log("        target one of:\n");
 		log("        \"cyclonev\"    - Cyclone V (default)\n");
-		log("        \"arriav\"      - Arria V (non-GZ)\n");
-		log("        \"cyclone10gx\" - Cyclone 10GX\n");
-		log("\n");
-		log("    -vqm <file>\n");
-		log("        write the design to the specified Verilog Quartus Mapping File. Writing\n");
-		log("        of an output file is omitted if this parameter is not specified. Implies\n");
-		log("        -quartus.\n");
 		log("\n");
 		log("    -noflatten\n");
 		log("        do not flatten design before synthesis; useful for per-module area\n");
 		log("        statistics\n");
 		log("\n");
-		log("    -quartus\n");
-		log("        output a netlist using Quartus cells instead of MISTRAL_* cells\n");
-		log("\n");
 		log("    -dff\n");
 		log("        pass DFFs to ABC to perform sequential logic optimisations\n");
 		log("        (EXPERIMENTAL)\n");
@@ -87,17 +77,15 @@ struct SynthIntelALMPass : public ScriptPass {
 		log("\n");
 	}
 
-	string top_opt, family_opt, bram_type, vout_file;
-	bool flatten, quartus, nolutram, nobram, dff, nodsp, noiopad, noclkbuf;
+	string top_opt, family_opt, bram_type;
+	bool flatten, nolutram, nobram, dff, nodsp, noiopad, noclkbuf;
 
 	void clear_flags() override
 	{
 		top_opt = "-auto-top";
 		family_opt = "cyclonev";
 		bram_type = "m10k";
-		vout_file = "";
 		flatten = true;
-		quartus = false;
 		nolutram = false;
 		nobram = false;
 		dff = false;
@@ -121,11 +109,6 @@ struct SynthIntelALMPass : public ScriptPass {
 				top_opt = "-top " + args[++argidx];
 				continue;
 			}
-			if (args[argidx] == "-vqm" && argidx + 1 < args.size()) {
-				quartus = true;
-				vout_file = args[++argidx];
-				continue;
-			}
 			if (args[argidx] == "-run" && argidx + 1 < args.size()) {
 				size_t pos = args[argidx + 1].find(':');
 				if (pos == std::string::npos)
@@ -134,10 +117,6 @@ struct SynthIntelALMPass : public ScriptPass {
 				run_to = args[argidx].substr(pos + 1);
 				continue;
 			}
-			if (args[argidx] == "-quartus") {
-				quartus = true;
-				continue;
-			}
 			if (args[argidx] == "-nolutram") {
 				nolutram = true;
 				continue;
@@ -173,18 +152,6 @@ struct SynthIntelALMPass : public ScriptPass {
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 
-		if (family_opt == "cyclonev" || family_opt == "arriav") {
-			bram_type = "m10k";
-		} else if (family_opt == "cyclone10gx") {
-			bram_type = "m20k";
-		} else if (family_opt == "arriva") {
-			// I have typoed "arriav" as "arriva" (a local bus company)
-			// so many times I thought it would be funny to have an easter egg.
-			log_cmd_error("synth_intel_alm cannot synthesize for bus companies. (did you mean '-family arriav'?)\n");
-		} else {
-			log_cmd_error("Invalid family specified: '%s'\n", family_opt.c_str());
-		}
-
 		log_header(design, "Executing SYNTH_INTEL_ALM pass.\n");
 		log_push();
 
@@ -237,22 +204,16 @@ struct SynthIntelALMPass : public ScriptPass {
 			if (help_mode) {
 				run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)");
 			} else if (!nodsp) {
-				// Cyclone V/Arria V supports 9x9 multiplication, Cyclone 10 GX does not.
 				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=27  -D DSP_A_MINWIDTH=19 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL27X27");
 				run("chtype -set $mul t:$__soft_mul");
 				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=27  -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=19 -D DSP_NAME=__MUL27X27");
 				run("chtype -set $mul t:$__soft_mul");
-				if (family_opt == "cyclonev" || family_opt == "arriav") {
-					run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL18X18");
-					run("chtype -set $mul t:$__soft_mul");
-					run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=10 -D DSP_NAME=__MUL18X18");
-					run("chtype -set $mul t:$__soft_mul");
-					run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9  -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL9X9");
-					run("chtype -set $mul t:$__soft_mul");
-				} else if (family_opt == "cyclone10gx") {
-					run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL18X18");
-					run("chtype -set $mul t:$__soft_mul");
-				}
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL18X18");
+				run("chtype -set $mul t:$__soft_mul");
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=10 -D DSP_NAME=__MUL18X18");
+				run("chtype -set $mul t:$__soft_mul");
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9  -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL9X9");
+				run("chtype -set $mul t:$__soft_mul");
 			}
 			run("alumacc");
 			if (!noiopad)
@@ -269,7 +230,7 @@ struct SynthIntelALMPass : public ScriptPass {
 		}
 
 		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {
-			run("memory_bram -rules +/intel_alm/common/lutram_mlab.txt", "(for Cyclone V / Cyclone 10GX)");
+			run("memory_bram -rules +/intel_alm/common/lutram_mlab.txt", "(for Cyclone V)");
 		}
 
 		if (check_label("map_ffram")) {
@@ -303,28 +264,6 @@ struct SynthIntelALMPass : public ScriptPass {
 			run("check");
 			run("blackbox =A:whitebox");
 		}
-
-		if (check_label("quartus")) {
-			if (quartus || help_mode) {
-				// Quartus ICEs if you have a wire which has `[]` in its name,
-				// which Yosys produces when building memories out of flops.
-				run("rename -hide w:*[* w:*]*");
-				// VQM mode does not support 'x, so replace those with zero.
-				run("setundef -zero");
-				// VQM mode does not support multi-bit constant assignments
-				// (e.g. 2'b00 is an error), so as a workaround use references
-				// to constant driver cells, which Quartus accepts.
-				run("hilomap -singleton -hicell __MISTRAL_VCC Q -locell __MISTRAL_GND Q");
-				// Rename from Yosys-internal MISTRAL_* cells to Quartus cells.
-				run(stringf("techmap -D %s -map +/intel_alm/common/quartus_rename.v", family_opt.c_str()));
-			}
-		}
-
-		if (check_label("vqm")) {
-			if (!vout_file.empty() || help_mode) {
-				run(stringf("write_verilog -attr2comment -defparam -nohex -decimal %s", help_mode ? "<file-name>" : vout_file.c_str()));
-			}
-		}
 	}
 } SynthIntelALMPass;
 
diff --git a/yosys/techlibs/lattice/Makefile.inc b/yosys/techlibs/lattice/Makefile.inc
new file mode 100644
index 00000000000..fd9ec2ed5e0
--- /dev/null
+++ b/yosys/techlibs/lattice/Makefile.inc
@@ -0,0 +1,28 @@
+
+OBJS += techlibs/lattice/synth_lattice.o
+OBJS += techlibs/lattice/lattice_gsr.o
+
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_ff.vh))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_io.vh))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_map.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/common_sim.vh))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2d_sim.vh))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2c_sim.vh))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_ecp5.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo2.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3d.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_ecp5.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo2.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo3.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo3d.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_map.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams.txt))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_16kd.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_16kd.txt))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_8kc.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_8kc.txt))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2c.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2d.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/latches_map.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/dsp_map_18x18.v))
diff --git a/yosys/techlibs/lattice/arith_map_ccu2c.v b/yosys/techlibs/lattice/arith_map_ccu2c.v
new file mode 100644
index 00000000000..a5efc35613a
--- /dev/null
+++ b/yosys/techlibs/lattice/arith_map_ccu2c.v
@@ -0,0 +1,90 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+(* techmap_celltype = "$alu" *)
+module _80_ccu2c_alu (A, B, CI, BI, X, Y, CO);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 1;
+	parameter B_WIDTH = 1;
+	parameter Y_WIDTH = 1;
+
+	(* force_downto *)
+	input [A_WIDTH-1:0] A;
+	(* force_downto *)
+	input [B_WIDTH-1:0] B;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] CO;
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] A_buf, B_buf;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+	function integer round_up2;
+		input integer N;
+		begin
+			round_up2 = ((N + 1) / 2) * 2;
+		end
+	endfunction
+
+	localparam Y_WIDTH2 = round_up2(Y_WIDTH);
+
+	(* force_downto *)
+	wire [Y_WIDTH2-1:0] AA = A_buf;
+	(* force_downto *)
+	wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
+	(* force_downto *)
+	wire [Y_WIDTH2-1:0] BX = B_buf;
+	(* force_downto *)
+	wire [Y_WIDTH2-1:0] C = {CO, CI};
+	(* force_downto *)
+	wire [Y_WIDTH2-1:0] FCO, Y1;
+
+	genvar i;
+	generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
+		CCU2C #(
+			.INIT0(16'b1001011010101010),
+			.INIT1(16'b1001011010101010),
+			.INJECT1_0("NO"),
+			.INJECT1_1("NO")
+	   ) ccu2c_i (
+			.CIN(C[i]),
+			.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),
+			.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),
+			.S0(Y[i]), .S1(Y1[i]),
+			.COUT(FCO[i])
+		);
+
+		assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
+		if (i+1 < Y_WIDTH) begin
+			assign CO[i+1] = FCO[i];
+			assign Y[i+1] = Y1[i];
+		end
+	end endgenerate
+
+	assign X = AA ^ BB;
+endmodule
diff --git a/yosys/techlibs/machxo2/arith_map.v b/yosys/techlibs/lattice/arith_map_ccu2d.v
similarity index 98%
rename from yosys/techlibs/machxo2/arith_map.v
rename to yosys/techlibs/lattice/arith_map_ccu2d.v
index ab4a6b1da6c..31e4afe09a1 100644
--- a/yosys/techlibs/machxo2/arith_map.v
+++ b/yosys/techlibs/lattice/arith_map_ccu2d.v
@@ -19,7 +19,7 @@
  */
 
 (* techmap_celltype = "$alu" *)
-module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
+module _80_ccu2d_alu (A, B, CI, BI, X, Y, CO);
 	parameter A_SIGNED = 0;
 	parameter B_SIGNED = 0;
 	parameter A_WIDTH = 1;
diff --git a/yosys/techlibs/lattice/brams_16kd.txt b/yosys/techlibs/lattice/brams_16kd.txt
new file mode 100644
index 00000000000..ccdf490501f
--- /dev/null
+++ b/yosys/techlibs/lattice/brams_16kd.txt
@@ -0,0 +1,52 @@
+ram block $__DP16KD_ {
+	abits 14;
+	widths 1 2 4 9 18 per_port;
+	byte 9;
+	cost 128;
+	init no_undef;
+	port srsw "A" "B" {
+		clock anyedge;
+		clken;
+		wrbe_separate;
+		portoption "WRITEMODE" "NORMAL" {
+			rdwr no_change;
+		}
+		portoption "WRITEMODE" "WRITETHROUGH" {
+			rdwr new;
+		}
+		portoption "WRITEMODE" "READBEFOREWRITE" {
+			rdwr old;
+		}
+		option "RESETMODE" "SYNC" {
+			rdsrst zero ungated block_wr;
+		}
+		option "RESETMODE" "ASYNC" {
+			rdarst zero;
+		}
+		rdinit zero;
+	}
+}
+
+ram block $__PDPW16KD_ {
+	abits 14;
+	widths 1 2 4 9 18 36 per_port;
+	byte 9;
+	cost 128;
+	init no_undef;
+	port sr "R" {
+		clock anyedge;
+		clken;
+		option "RESETMODE" "SYNC" {
+			rdsrst zero ungated;
+		}
+		option "RESETMODE" "ASYNC" {
+			rdarst zero;
+		}
+		rdinit zero;
+	}
+	port sw "W" {
+		width 36;
+		clock anyedge;
+		clken;
+	}
+}
diff --git a/yosys/techlibs/machxo2/brams.txt b/yosys/techlibs/lattice/brams_8kc.txt
similarity index 84%
rename from yosys/techlibs/machxo2/brams.txt
rename to yosys/techlibs/lattice/brams_8kc.txt
index 3afbeda07e6..f254c46aa82 100644
--- a/yosys/techlibs/machxo2/brams.txt
+++ b/yosys/techlibs/lattice/brams_8kc.txt
@@ -32,6 +32,10 @@ ram block $__PDPW8KC_ {
 	cost 64;
 	init no_undef;
 	port sr "R" {
+		# width 2 cannot be supported because of quirks
+		# of the primitive, and memlib requires us to
+		# remove width 1 as well
+		width 4 9 18;
 		clock posedge;
 		clken;
 		option "RESETMODE" "SYNC" {
diff --git a/yosys/techlibs/lattice/brams_map_16kd.v b/yosys/techlibs/lattice/brams_map_16kd.v
new file mode 100644
index 00000000000..da4d8041770
--- /dev/null
+++ b/yosys/techlibs/lattice/brams_map_16kd.v
@@ -0,0 +1,489 @@
+module $__DP16KD_ (...);
+
+parameter INIT = 0;
+parameter OPTION_RESETMODE = "SYNC";
+
+parameter PORT_A_WIDTH = 18;
+parameter PORT_A_WR_BE_WIDTH = 2;
+parameter PORT_A_CLK_POL = 1;
+parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
+
+input PORT_A_CLK;
+input PORT_A_CLK_EN;
+input PORT_A_WR_EN;
+input PORT_A_RD_SRST;
+input PORT_A_RD_ARST;
+input [13:0] PORT_A_ADDR;
+input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
+input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
+output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
+
+parameter PORT_B_WIDTH = 18;
+parameter PORT_B_WR_BE_WIDTH = 2;
+parameter PORT_B_CLK_POL = 1;
+parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
+
+input PORT_B_CLK;
+input PORT_B_CLK_EN;
+input PORT_B_WR_EN;
+input PORT_B_RD_SRST;
+input PORT_B_RD_ARST;
+input [13:0] PORT_B_ADDR;
+input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
+input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
+output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
+
+function [319:0] init_slice;
+	input integer idx;
+	integer i, j;
+	init_slice = 0;
+	for (i = 0; i < 16; i = i + 1) begin
+		init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
+	end
+endfunction
+
+wire [17:0] DOA;
+wire [17:0] DOB;
+wire [17:0] DIA = PORT_A_WR_DATA;
+wire [17:0] DIB = PORT_B_WR_DATA;
+
+assign PORT_A_RD_DATA = DOA;
+assign PORT_B_RD_DATA = DOB;
+
+DP16KD #(
+	.INITVAL_00(init_slice('h00)),
+	.INITVAL_01(init_slice('h01)),
+	.INITVAL_02(init_slice('h02)),
+	.INITVAL_03(init_slice('h03)),
+	.INITVAL_04(init_slice('h04)),
+	.INITVAL_05(init_slice('h05)),
+	.INITVAL_06(init_slice('h06)),
+	.INITVAL_07(init_slice('h07)),
+	.INITVAL_08(init_slice('h08)),
+	.INITVAL_09(init_slice('h09)),
+	.INITVAL_0A(init_slice('h0a)),
+	.INITVAL_0B(init_slice('h0b)),
+	.INITVAL_0C(init_slice('h0c)),
+	.INITVAL_0D(init_slice('h0d)),
+	.INITVAL_0E(init_slice('h0e)),
+	.INITVAL_0F(init_slice('h0f)),
+	.INITVAL_10(init_slice('h10)),
+	.INITVAL_11(init_slice('h11)),
+	.INITVAL_12(init_slice('h12)),
+	.INITVAL_13(init_slice('h13)),
+	.INITVAL_14(init_slice('h14)),
+	.INITVAL_15(init_slice('h15)),
+	.INITVAL_16(init_slice('h16)),
+	.INITVAL_17(init_slice('h17)),
+	.INITVAL_18(init_slice('h18)),
+	.INITVAL_19(init_slice('h19)),
+	.INITVAL_1A(init_slice('h1a)),
+	.INITVAL_1B(init_slice('h1b)),
+	.INITVAL_1C(init_slice('h1c)),
+	.INITVAL_1D(init_slice('h1d)),
+	.INITVAL_1E(init_slice('h1e)),
+	.INITVAL_1F(init_slice('h1f)),
+	.INITVAL_20(init_slice('h20)),
+	.INITVAL_21(init_slice('h21)),
+	.INITVAL_22(init_slice('h22)),
+	.INITVAL_23(init_slice('h23)),
+	.INITVAL_24(init_slice('h24)),
+	.INITVAL_25(init_slice('h25)),
+	.INITVAL_26(init_slice('h26)),
+	.INITVAL_27(init_slice('h27)),
+	.INITVAL_28(init_slice('h28)),
+	.INITVAL_29(init_slice('h29)),
+	.INITVAL_2A(init_slice('h2a)),
+	.INITVAL_2B(init_slice('h2b)),
+	.INITVAL_2C(init_slice('h2c)),
+	.INITVAL_2D(init_slice('h2d)),
+	.INITVAL_2E(init_slice('h2e)),
+	.INITVAL_2F(init_slice('h2f)),
+	.INITVAL_30(init_slice('h30)),
+	.INITVAL_31(init_slice('h31)),
+	.INITVAL_32(init_slice('h32)),
+	.INITVAL_33(init_slice('h33)),
+	.INITVAL_34(init_slice('h34)),
+	.INITVAL_35(init_slice('h35)),
+	.INITVAL_36(init_slice('h36)),
+	.INITVAL_37(init_slice('h37)),
+	.INITVAL_38(init_slice('h38)),
+	.INITVAL_39(init_slice('h39)),
+	.INITVAL_3A(init_slice('h3a)),
+	.INITVAL_3B(init_slice('h3b)),
+	.INITVAL_3C(init_slice('h3c)),
+	.INITVAL_3D(init_slice('h3d)),
+	.INITVAL_3E(init_slice('h3e)),
+	.INITVAL_3F(init_slice('h3f)),
+	.DATA_WIDTH_A(PORT_A_WIDTH),
+	.DATA_WIDTH_B(PORT_B_WIDTH),
+	.REGMODE_A("NOREG"),
+	.REGMODE_B("NOREG"),
+	.RESETMODE(OPTION_RESETMODE),
+	.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
+	.CSDECODE_A("0b000"),
+	.CSDECODE_B("0b000"),
+	.CLKAMUX(PORT_A_CLK_POL ? "CLKA" : "INV"),
+	.CLKBMUX(PORT_B_CLK_POL ? "CLKB" : "INV"),
+	.WRITEMODE_A(PORT_A_OPTION_WRITEMODE),
+	.WRITEMODE_B(PORT_B_OPTION_WRITEMODE),
+	.GSR("AUTO")
+) _TECHMAP_REPLACE_ (
+	.CLKA(PORT_A_CLK),
+	.WEA(PORT_A_WIDTH == 18 ? PORT_A_WR_EN : (PORT_A_WR_EN | PORT_A_WR_BE[0])),
+	.CEA(PORT_A_CLK_EN),
+	.OCEA(1'b1),
+	.RSTA(OPTION_RESETMODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
+	.CSA0(1'b0),
+	.CSA1(1'b0),
+	.CSA2(1'b0),
+	.ADA0(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[0] : PORT_A_ADDR[0]),
+	.ADA1(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[1] : PORT_A_ADDR[1]),
+	.ADA2(PORT_A_ADDR[2]),
+	.ADA3(PORT_A_ADDR[3]),
+	.ADA4(PORT_A_ADDR[4]),
+	.ADA5(PORT_A_ADDR[5]),
+	.ADA6(PORT_A_ADDR[6]),
+	.ADA7(PORT_A_ADDR[7]),
+	.ADA8(PORT_A_ADDR[8]),
+	.ADA9(PORT_A_ADDR[9]),
+	.ADA10(PORT_A_ADDR[10]),
+	.ADA11(PORT_A_ADDR[11]),
+	.ADA12(PORT_A_ADDR[12]),
+	.ADA13(PORT_A_ADDR[13]),
+	.DIA0(DIA[0]),
+	.DIA1(DIA[1]),
+	.DIA2(DIA[2]),
+	.DIA3(DIA[3]),
+	.DIA4(DIA[4]),
+	.DIA5(DIA[5]),
+	.DIA6(DIA[6]),
+	.DIA7(DIA[7]),
+	.DIA8(DIA[8]),
+	.DIA9(DIA[9]),
+	.DIA10(DIA[10]),
+	.DIA11(DIA[11]),
+	.DIA12(DIA[12]),
+	.DIA13(DIA[13]),
+	.DIA14(DIA[14]),
+	.DIA15(DIA[15]),
+	.DIA16(DIA[16]),
+	.DIA17(DIA[17]),
+	.DOA0(DOA[0]),
+	.DOA1(DOA[1]),
+	.DOA2(DOA[2]),
+	.DOA3(DOA[3]),
+	.DOA4(DOA[4]),
+	.DOA5(DOA[5]),
+	.DOA6(DOA[6]),
+	.DOA7(DOA[7]),
+	.DOA8(DOA[8]),
+	.DOA9(DOA[9]),
+	.DOA10(DOA[10]),
+	.DOA11(DOA[11]),
+	.DOA12(DOA[12]),
+	.DOA13(DOA[13]),
+	.DOA14(DOA[14]),
+	.DOA15(DOA[15]),
+	.DOA16(DOA[16]),
+	.DOA17(DOA[17]),
+
+	.CLKB(PORT_B_CLK),
+	.WEB(PORT_B_WIDTH == 18 ? PORT_B_WR_EN : (PORT_B_WR_EN | PORT_B_WR_BE[0])),
+	.CEB(PORT_B_CLK_EN),
+	.OCEB(1'b1),
+	.RSTB(OPTION_RESETMODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST),
+	.CSB0(1'b0),
+	.CSB1(1'b0),
+	.CSB2(1'b0),
+	.ADB0(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[0] : PORT_B_ADDR[0]),
+	.ADB1(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[1] : PORT_B_ADDR[1]),
+	.ADB2(PORT_B_ADDR[2]),
+	.ADB3(PORT_B_ADDR[3]),
+	.ADB4(PORT_B_ADDR[4]),
+	.ADB5(PORT_B_ADDR[5]),
+	.ADB6(PORT_B_ADDR[6]),
+	.ADB7(PORT_B_ADDR[7]),
+	.ADB8(PORT_B_ADDR[8]),
+	.ADB9(PORT_B_ADDR[9]),
+	.ADB10(PORT_B_ADDR[10]),
+	.ADB11(PORT_B_ADDR[11]),
+	.ADB12(PORT_B_ADDR[12]),
+	.ADB13(PORT_B_ADDR[13]),
+	.DIB0(DIB[0]),
+	.DIB1(DIB[1]),
+	.DIB2(DIB[2]),
+	.DIB3(DIB[3]),
+	.DIB4(DIB[4]),
+	.DIB5(DIB[5]),
+	.DIB6(DIB[6]),
+	.DIB7(DIB[7]),
+	.DIB8(DIB[8]),
+	.DIB9(DIB[9]),
+	.DIB10(DIB[10]),
+	.DIB11(DIB[11]),
+	.DIB12(DIB[12]),
+	.DIB13(DIB[13]),
+	.DIB14(DIB[14]),
+	.DIB15(DIB[15]),
+	.DIB16(DIB[16]),
+	.DIB17(DIB[17]),
+	.DOB0(DOB[0]),
+	.DOB1(DOB[1]),
+	.DOB2(DOB[2]),
+	.DOB3(DOB[3]),
+	.DOB4(DOB[4]),
+	.DOB5(DOB[5]),
+	.DOB6(DOB[6]),
+	.DOB7(DOB[7]),
+	.DOB8(DOB[8]),
+	.DOB9(DOB[9]),
+	.DOB10(DOB[10]),
+	.DOB11(DOB[11]),
+	.DOB12(DOB[12]),
+	.DOB13(DOB[13]),
+	.DOB14(DOB[14]),
+	.DOB15(DOB[15]),
+	.DOB16(DOB[16]),
+	.DOB17(DOB[17]),
+);
+
+endmodule
+
+
+module $__PDPW16KD_ (...);
+
+parameter INIT = 0;
+parameter OPTION_RESETMODE = "SYNC";
+
+parameter PORT_R_WIDTH = 36;
+parameter PORT_R_CLK_POL = 1;
+
+input PORT_R_CLK;
+input PORT_R_CLK_EN;
+input PORT_R_RD_SRST;
+input PORT_R_RD_ARST;
+input [13:0] PORT_R_ADDR;
+output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
+
+parameter PORT_W_WIDTH = 36;
+parameter PORT_W_WR_EN_WIDTH = 4;
+parameter PORT_W_CLK_POL = 1;
+
+input PORT_W_CLK;
+input PORT_W_CLK_EN;
+input [13:0] PORT_W_ADDR;
+input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
+input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
+
+function [319:0] init_slice;
+	input integer idx;
+	integer i, j;
+	init_slice = 0;
+	for (i = 0; i < 16; i = i + 1) begin
+		init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
+	end
+endfunction
+
+wire [35:0] DI = PORT_W_WR_DATA;
+wire [35:0] DO;
+
+assign PORT_R_RD_DATA = PORT_R_WIDTH == 36 ? DO : DO[35:18];
+
+DP16KD #(
+	.INITVAL_00(init_slice('h00)),
+	.INITVAL_01(init_slice('h01)),
+	.INITVAL_02(init_slice('h02)),
+	.INITVAL_03(init_slice('h03)),
+	.INITVAL_04(init_slice('h04)),
+	.INITVAL_05(init_slice('h05)),
+	.INITVAL_06(init_slice('h06)),
+	.INITVAL_07(init_slice('h07)),
+	.INITVAL_08(init_slice('h08)),
+	.INITVAL_09(init_slice('h09)),
+	.INITVAL_0A(init_slice('h0a)),
+	.INITVAL_0B(init_slice('h0b)),
+	.INITVAL_0C(init_slice('h0c)),
+	.INITVAL_0D(init_slice('h0d)),
+	.INITVAL_0E(init_slice('h0e)),
+	.INITVAL_0F(init_slice('h0f)),
+	.INITVAL_10(init_slice('h10)),
+	.INITVAL_11(init_slice('h11)),
+	.INITVAL_12(init_slice('h12)),
+	.INITVAL_13(init_slice('h13)),
+	.INITVAL_14(init_slice('h14)),
+	.INITVAL_15(init_slice('h15)),
+	.INITVAL_16(init_slice('h16)),
+	.INITVAL_17(init_slice('h17)),
+	.INITVAL_18(init_slice('h18)),
+	.INITVAL_19(init_slice('h19)),
+	.INITVAL_1A(init_slice('h1a)),
+	.INITVAL_1B(init_slice('h1b)),
+	.INITVAL_1C(init_slice('h1c)),
+	.INITVAL_1D(init_slice('h1d)),
+	.INITVAL_1E(init_slice('h1e)),
+	.INITVAL_1F(init_slice('h1f)),
+	.INITVAL_20(init_slice('h20)),
+	.INITVAL_21(init_slice('h21)),
+	.INITVAL_22(init_slice('h22)),
+	.INITVAL_23(init_slice('h23)),
+	.INITVAL_24(init_slice('h24)),
+	.INITVAL_25(init_slice('h25)),
+	.INITVAL_26(init_slice('h26)),
+	.INITVAL_27(init_slice('h27)),
+	.INITVAL_28(init_slice('h28)),
+	.INITVAL_29(init_slice('h29)),
+	.INITVAL_2A(init_slice('h2a)),
+	.INITVAL_2B(init_slice('h2b)),
+	.INITVAL_2C(init_slice('h2c)),
+	.INITVAL_2D(init_slice('h2d)),
+	.INITVAL_2E(init_slice('h2e)),
+	.INITVAL_2F(init_slice('h2f)),
+	.INITVAL_30(init_slice('h30)),
+	.INITVAL_31(init_slice('h31)),
+	.INITVAL_32(init_slice('h32)),
+	.INITVAL_33(init_slice('h33)),
+	.INITVAL_34(init_slice('h34)),
+	.INITVAL_35(init_slice('h35)),
+	.INITVAL_36(init_slice('h36)),
+	.INITVAL_37(init_slice('h37)),
+	.INITVAL_38(init_slice('h38)),
+	.INITVAL_39(init_slice('h39)),
+	.INITVAL_3A(init_slice('h3a)),
+	.INITVAL_3B(init_slice('h3b)),
+	.INITVAL_3C(init_slice('h3c)),
+	.INITVAL_3D(init_slice('h3d)),
+	.INITVAL_3E(init_slice('h3e)),
+	.INITVAL_3F(init_slice('h3f)),
+	.DATA_WIDTH_A(PORT_W_WIDTH),
+	.DATA_WIDTH_B(PORT_R_WIDTH),
+	.REGMODE_A("NOREG"),
+	.REGMODE_B("NOREG"),
+	.RESETMODE(OPTION_RESETMODE),
+	.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
+	.CSDECODE_A("0b000"),
+	.CSDECODE_B("0b000"),
+	.CLKAMUX(PORT_W_CLK_POL ? "CLKA" : "INV"),
+	.CLKBMUX(PORT_R_CLK_POL ? "CLKB" : "INV"),
+	.GSR("AUTO")
+) _TECHMAP_REPLACE_ (
+	.CLKA(PORT_W_CLK),
+	.WEA(PORT_W_WIDTH >= 18 ? 1'b1 : PORT_W_WR_EN[0]),
+	.CEA(PORT_W_CLK_EN),
+	.OCEA(1'b0),
+	.RSTA(1'b0),
+	.CSA0(1'b0),
+	.CSA1(1'b0),
+	.CSA2(1'b0),
+	.ADA0(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]),
+	.ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]),
+	.ADA2(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[2] : PORT_W_ADDR[2]),
+	.ADA3(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[3] : PORT_W_ADDR[3]),
+	.ADA4(PORT_W_ADDR[4]),
+	.ADA5(PORT_W_ADDR[5]),
+	.ADA6(PORT_W_ADDR[6]),
+	.ADA7(PORT_W_ADDR[7]),
+	.ADA8(PORT_W_ADDR[8]),
+	.ADA9(PORT_W_ADDR[9]),
+	.ADA10(PORT_W_ADDR[10]),
+	.ADA11(PORT_W_ADDR[11]),
+	.ADA12(PORT_W_ADDR[12]),
+	.ADA13(PORT_W_ADDR[13]),
+	.DIA0(DI[0]),
+	.DIA1(DI[1]),
+	.DIA2(DI[2]),
+	.DIA3(DI[3]),
+	.DIA4(DI[4]),
+	.DIA5(DI[5]),
+	.DIA6(DI[6]),
+	.DIA7(DI[7]),
+	.DIA8(DI[8]),
+	.DIA9(DI[9]),
+	.DIA10(DI[10]),
+	.DIA11(DI[11]),
+	.DIA12(DI[12]),
+	.DIA13(DI[13]),
+	.DIA14(DI[14]),
+	.DIA15(DI[15]),
+	.DIA16(DI[16]),
+	.DIA17(DI[17]),
+	.DIB0(DI[18]),
+	.DIB1(DI[19]),
+	.DIB2(DI[20]),
+	.DIB3(DI[21]),
+	.DIB4(DI[22]),
+	.DIB5(DI[23]),
+	.DIB6(DI[24]),
+	.DIB7(DI[25]),
+	.DIB8(DI[26]),
+	.DIB9(DI[27]),
+	.DIB10(DI[28]),
+	.DIB11(DI[29]),
+	.DIB12(DI[30]),
+	.DIB13(DI[31]),
+	.DIB14(DI[32]),
+	.DIB15(DI[33]),
+	.DIB16(DI[34]),
+	.DIB17(DI[35]),
+
+	.CLKB(PORT_R_CLK),
+	.WEB(1'b0),
+	.CEB(PORT_R_CLK_EN),
+	.OCEB(1'b1),
+	.RSTB(OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST),
+	.CSB0(1'b0),
+	.CSB1(1'b0),
+	.CSB2(1'b0),
+	.ADB0(PORT_R_ADDR[0]),
+	.ADB1(PORT_R_ADDR[1]),
+	.ADB2(PORT_R_ADDR[2]),
+	.ADB3(PORT_R_ADDR[3]),
+	.ADB4(PORT_R_ADDR[4]),
+	.ADB5(PORT_R_ADDR[5]),
+	.ADB6(PORT_R_ADDR[6]),
+	.ADB7(PORT_R_ADDR[7]),
+	.ADB8(PORT_R_ADDR[8]),
+	.ADB9(PORT_R_ADDR[9]),
+	.ADB10(PORT_R_ADDR[10]),
+	.ADB11(PORT_R_ADDR[11]),
+	.ADB12(PORT_R_ADDR[12]),
+	.ADB13(PORT_R_ADDR[13]),
+	.DOA0(DO[0]),
+	.DOA1(DO[1]),
+	.DOA2(DO[2]),
+	.DOA3(DO[3]),
+	.DOA4(DO[4]),
+	.DOA5(DO[5]),
+	.DOA6(DO[6]),
+	.DOA7(DO[7]),
+	.DOA8(DO[8]),
+	.DOA9(DO[9]),
+	.DOA10(DO[10]),
+	.DOA11(DO[11]),
+	.DOA12(DO[12]),
+	.DOA13(DO[13]),
+	.DOA14(DO[14]),
+	.DOA15(DO[15]),
+	.DOA16(DO[16]),
+	.DOA17(DO[17]),
+	.DOB0(DO[18]),
+	.DOB1(DO[19]),
+	.DOB2(DO[20]),
+	.DOB3(DO[21]),
+	.DOB4(DO[22]),
+	.DOB5(DO[23]),
+	.DOB6(DO[24]),
+	.DOB7(DO[25]),
+	.DOB8(DO[26]),
+	.DOB9(DO[27]),
+	.DOB10(DO[28]),
+	.DOB11(DO[29]),
+	.DOB12(DO[30]),
+	.DOB13(DO[31]),
+	.DOB14(DO[32]),
+	.DOB15(DO[33]),
+	.DOB16(DO[34]),
+	.DOB17(DO[35]),
+);
+
+endmodule
diff --git a/yosys/techlibs/machxo2/brams_map.v b/yosys/techlibs/lattice/brams_map_8kc.v
similarity index 94%
rename from yosys/techlibs/machxo2/brams_map.v
rename to yosys/techlibs/lattice/brams_map_8kc.v
index 6783e5b2902..b57250fc7a6 100644
--- a/yosys/techlibs/machxo2/brams_map.v
+++ b/yosys/techlibs/lattice/brams_map_8kc.v
@@ -38,8 +38,20 @@ endfunction
 
 wire [8:0] DOA;
 wire [8:0] DOB;
-wire [8:0] DIA = PORT_A_WR_DATA;
-wire [8:0] DIB = PORT_B_WR_DATA;
+wire [8:0] DIA;
+wire [8:0] DIB;
+
+case(PORT_A_WIDTH)
+	1: assign DIA = {7'bx, PORT_A_WR_DATA[0], 1'bx};
+	2: assign DIA = {3'bx, PORT_A_WR_DATA[1], 2'bx, PORT_A_WR_DATA[0], 2'bx};
+	default: assign DIA = PORT_A_WR_DATA;
+endcase
+
+case(PORT_B_WIDTH)
+	1: assign DIB = {7'bx, PORT_B_WR_DATA[0], 1'bx};
+	2: assign DIB = {3'bx, PORT_B_WR_DATA[1], 2'bx, PORT_B_WR_DATA[0], 2'bx};
+	default: assign DIB = PORT_B_WR_DATA;
+endcase
 
 assign PORT_A_RD_DATA = DOA;
 assign PORT_B_RD_DATA = DOB;
diff --git a/yosys/techlibs/lattice/ccu2c_sim.vh b/yosys/techlibs/lattice/ccu2c_sim.vh
new file mode 100644
index 00000000000..d9eb69ab455
--- /dev/null
+++ b/yosys/techlibs/lattice/ccu2c_sim.vh
@@ -0,0 +1,61 @@
+// ---------------------------------------
+(* abc9_box, lib_whitebox *)
+module CCU2C(
+	(* abc9_carry *)
+	input  CIN,
+	input  A0, B0, C0, D0, A1, B1, C1, D1,
+	output S0, S1,
+	(* abc9_carry *)
+	output COUT
+);
+	parameter [15:0] INIT0 = 16'h0000;
+	parameter [15:0] INIT1 = 16'h0000;
+	parameter INJECT1_0 = "YES";
+	parameter INJECT1_1 = "YES";
+
+	// First half
+	wire LUT4_0, LUT2_0;
+	LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
+	LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
+	wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
+	assign S0 = LUT4_0 ^ gated_cin_0;
+
+	wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
+	wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
+
+	// Second half
+	wire LUT4_1, LUT2_1;
+	LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
+	LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
+	wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
+	assign S1 = LUT4_1 ^ gated_cin_1;
+
+	wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
+	assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
+
+	specify
+		(A0 => S0) = 379;
+		(B0 => S0) = 379;
+		(C0 => S0) = 275;
+		(D0 => S0) = 141;
+		(CIN => S0) = 257;
+		(A0 => S1) = 630;
+		(B0 => S1) = 630;
+		(C0 => S1) = 526;
+		(D0 => S1) = 392;
+		(A1 => S1) = 379;
+		(B1 => S1) = 379;
+		(C1 => S1) = 275;
+		(D1 => S1) = 141;
+		(CIN => S1) = 273;
+		(A0 => COUT) = 516;
+		(B0 => COUT) = 516;
+		(C0 => COUT) = 412;
+		(D0 => COUT) = 278;
+		(A1 => COUT) = 516;
+		(B1 => COUT) = 516;
+		(C1 => COUT) = 412;
+		(D1 => COUT) = 278;
+		(CIN => COUT) = 43;
+	endspecify
+endmodule
diff --git a/yosys/techlibs/lattice/ccu2d_sim.vh b/yosys/techlibs/lattice/ccu2d_sim.vh
new file mode 100644
index 00000000000..5b9c95cc9ef
--- /dev/null
+++ b/yosys/techlibs/lattice/ccu2d_sim.vh
@@ -0,0 +1,33 @@
+// ---------------------------------------
+(* lib_whitebox *)
+module CCU2D (
+	input  CIN,
+	input  A0, B0, C0, D0, A1, B1, C1, D1,
+	output S0, S1,
+	output COUT
+);
+	parameter [15:0] INIT0 = 16'h0000;
+	parameter [15:0] INIT1 = 16'h0000;
+	parameter INJECT1_0 = "YES";
+	parameter INJECT1_1 = "YES";
+
+	// First half
+	wire LUT4_0, LUT2_0;
+	LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
+	LUT2 #(.INIT(~INIT0[15:12])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
+	wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
+	assign S0 = LUT4_0 ^ gated_cin_0;
+
+	wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
+	wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
+
+	// Second half
+	wire LUT4_1, LUT2_1;
+	LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
+	LUT2 #(.INIT(~INIT1[15:12])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
+	wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
+	assign S1 = LUT4_1 ^ gated_cin_1;
+
+	wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
+	assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
+endmodule
diff --git a/yosys/techlibs/lattice/cells_bb_ecp5.v b/yosys/techlibs/lattice/cells_bb_ecp5.v
new file mode 100644
index 00000000000..fc22495e2ff
--- /dev/null
+++ b/yosys/techlibs/lattice/cells_bb_ecp5.v
@@ -0,0 +1,2175 @@
+// Created by cells_xtra.py from Lattice models
+
+(* blackbox *) (* keep *)
+module GSR (...);
+    input GSR;
+endmodule
+
+(* blackbox *)
+module PUR (...);
+    parameter RST_PULSE = 1;
+    input PUR;
+endmodule
+
+(* blackbox *) (* keep *)
+module SGSR (...);
+    input GSR;
+    input CLK;
+endmodule
+
+(* blackbox *)
+module DP16KD (...);
+    parameter DATA_WIDTH_A = 18;
+    parameter DATA_WIDTH_B = 18;
+    parameter REGMODE_A = "NOREG";
+    parameter REGMODE_B = "NOREG";
+    parameter RESETMODE = "SYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter WRITEMODE_A = "NORMAL";
+    parameter WRITEMODE_B = "NORMAL";
+    parameter CSDECODE_A = "0b000";
+    parameter CSDECODE_B = "0b000";
+    parameter GSR = "ENABLED";
+    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_DATA = "STATIC";
+    input DIA17;
+    input DIA16;
+    input DIA15;
+    input DIA14;
+    input DIA13;
+    input DIA12;
+    input DIA11;
+    input DIA10;
+    input DIA9;
+    input DIA8;
+    input DIA7;
+    input DIA6;
+    input DIA5;
+    input DIA4;
+    input DIA3;
+    input DIA2;
+    input DIA1;
+    input DIA0;
+    input ADA13;
+    input ADA12;
+    input ADA11;
+    input ADA10;
+    input ADA9;
+    input ADA8;
+    input ADA7;
+    input ADA6;
+    input ADA5;
+    input ADA4;
+    input ADA3;
+    input ADA2;
+    input ADA1;
+    input ADA0;
+    input CEA;
+    input OCEA;
+    input CLKA;
+    input WEA;
+    input CSA2;
+    input CSA1;
+    input CSA0;
+    input RSTA;
+    input DIB17;
+    input DIB16;
+    input DIB15;
+    input DIB14;
+    input DIB13;
+    input DIB12;
+    input DIB11;
+    input DIB10;
+    input DIB9;
+    input DIB8;
+    input DIB7;
+    input DIB6;
+    input DIB5;
+    input DIB4;
+    input DIB3;
+    input DIB2;
+    input DIB1;
+    input DIB0;
+    input ADB13;
+    input ADB12;
+    input ADB11;
+    input ADB10;
+    input ADB9;
+    input ADB8;
+    input ADB7;
+    input ADB6;
+    input ADB5;
+    input ADB4;
+    input ADB3;
+    input ADB2;
+    input ADB1;
+    input ADB0;
+    input CEB;
+    input OCEB;
+    input CLKB;
+    input WEB;
+    input CSB2;
+    input CSB1;
+    input CSB0;
+    input RSTB;
+    output DOA17;
+    output DOA16;
+    output DOA15;
+    output DOA14;
+    output DOA13;
+    output DOA12;
+    output DOA11;
+    output DOA10;
+    output DOA9;
+    output DOA8;
+    output DOA7;
+    output DOA6;
+    output DOA5;
+    output DOA4;
+    output DOA3;
+    output DOA2;
+    output DOA1;
+    output DOA0;
+    output DOB17;
+    output DOB16;
+    output DOB15;
+    output DOB14;
+    output DOB13;
+    output DOB12;
+    output DOB11;
+    output DOB10;
+    output DOB9;
+    output DOB8;
+    output DOB7;
+    output DOB6;
+    output DOB5;
+    output DOB4;
+    output DOB3;
+    output DOB2;
+    output DOB1;
+    output DOB0;
+endmodule
+
+(* blackbox *)
+module PDPW16KD (...);
+    parameter DATA_WIDTH_W = 36;
+    parameter DATA_WIDTH_R = 36;
+    parameter GSR = "ENABLED";
+    parameter REGMODE = "NOREG";
+    parameter RESETMODE = "SYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter CSDECODE_W = "0b000";
+    parameter CSDECODE_R = "0b000";
+    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_DATA = "STATIC";
+    input DI35;
+    input DI34;
+    input DI33;
+    input DI32;
+    input DI31;
+    input DI30;
+    input DI29;
+    input DI28;
+    input DI27;
+    input DI26;
+    input DI25;
+    input DI24;
+    input DI23;
+    input DI22;
+    input DI21;
+    input DI20;
+    input DI19;
+    input DI18;
+    input DI17;
+    input DI16;
+    input DI15;
+    input DI14;
+    input DI13;
+    input DI12;
+    input DI11;
+    input DI10;
+    input DI9;
+    input DI8;
+    input DI7;
+    input DI6;
+    input DI5;
+    input DI4;
+    input DI3;
+    input DI2;
+    input DI1;
+    input DI0;
+    input ADW8;
+    input ADW7;
+    input ADW6;
+    input ADW5;
+    input ADW4;
+    input ADW3;
+    input ADW2;
+    input ADW1;
+    input ADW0;
+    input BE3;
+    input BE2;
+    input BE1;
+    input BE0;
+    input CEW;
+    input CLKW;
+    input CSW2;
+    input CSW1;
+    input CSW0;
+    input ADR13;
+    input ADR12;
+    input ADR11;
+    input ADR10;
+    input ADR9;
+    input ADR8;
+    input ADR7;
+    input ADR6;
+    input ADR5;
+    input ADR4;
+    input ADR3;
+    input ADR2;
+    input ADR1;
+    input ADR0;
+    input CER;
+    input OCER;
+    input CLKR;
+    input CSR2;
+    input CSR1;
+    input CSR0;
+    input RST;
+    output DO35;
+    output DO34;
+    output DO33;
+    output DO32;
+    output DO31;
+    output DO30;
+    output DO29;
+    output DO28;
+    output DO27;
+    output DO26;
+    output DO25;
+    output DO24;
+    output DO23;
+    output DO22;
+    output DO21;
+    output DO20;
+    output DO19;
+    output DO18;
+    output DO17;
+    output DO16;
+    output DO15;
+    output DO14;
+    output DO13;
+    output DO12;
+    output DO11;
+    output DO10;
+    output DO9;
+    output DO8;
+    output DO7;
+    output DO6;
+    output DO5;
+    output DO4;
+    output DO3;
+    output DO2;
+    output DO1;
+    output DO0;
+endmodule
+
+(* blackbox *)
+module MULT18X18D (...);
+    parameter REG_INPUTA_CLK = "NONE";
+    parameter REG_INPUTA_CE = "CE0";
+    parameter REG_INPUTA_RST = "RST0";
+    parameter REG_INPUTB_CLK = "NONE";
+    parameter REG_INPUTB_CE = "CE0";
+    parameter REG_INPUTB_RST = "RST0";
+    parameter REG_INPUTC_CLK = "NONE";
+    parameter REG_INPUTC_CE = "CE0";
+    parameter REG_INPUTC_RST = "RST0";
+    parameter REG_PIPELINE_CLK = "NONE";
+    parameter REG_PIPELINE_CE = "CE0";
+    parameter REG_PIPELINE_RST = "RST0";
+    parameter REG_OUTPUT_CLK = "NONE";
+    parameter REG_OUTPUT_CE = "CE0";
+    parameter REG_OUTPUT_RST = "RST0";
+    parameter CLK0_DIV = "ENABLED";
+    parameter CLK1_DIV = "ENABLED";
+    parameter CLK2_DIV = "ENABLED";
+    parameter CLK3_DIV = "ENABLED";
+    parameter HIGHSPEED_CLK = "NONE";
+    parameter GSR = "ENABLED";
+    parameter CAS_MATCH_REG = "FALSE";
+    parameter SOURCEB_MODE = "B_SHIFT";
+    parameter MULT_BYPASS = "DISABLED";
+    parameter RESETMODE = "SYNC";
+    input A17;
+    input A16;
+    input A15;
+    input A14;
+    input A13;
+    input A12;
+    input A11;
+    input A10;
+    input A9;
+    input A8;
+    input A7;
+    input A6;
+    input A5;
+    input A4;
+    input A3;
+    input A2;
+    input A1;
+    input A0;
+    input B17;
+    input B16;
+    input B15;
+    input B14;
+    input B13;
+    input B12;
+    input B11;
+    input B10;
+    input B9;
+    input B8;
+    input B7;
+    input B6;
+    input B5;
+    input B4;
+    input B3;
+    input B2;
+    input B1;
+    input B0;
+    input C17;
+    input C16;
+    input C15;
+    input C14;
+    input C13;
+    input C12;
+    input C11;
+    input C10;
+    input C9;
+    input C8;
+    input C7;
+    input C6;
+    input C5;
+    input C4;
+    input C3;
+    input C2;
+    input C1;
+    input C0;
+    input SIGNEDA;
+    input SIGNEDB;
+    input SOURCEA;
+    input SOURCEB;
+    input CLK3;
+    input CLK2;
+    input CLK1;
+    input CLK0;
+    input CE3;
+    input CE2;
+    input CE1;
+    input CE0;
+    input RST3;
+    input RST2;
+    input RST1;
+    input RST0;
+    input SRIA17;
+    input SRIA16;
+    input SRIA15;
+    input SRIA14;
+    input SRIA13;
+    input SRIA12;
+    input SRIA11;
+    input SRIA10;
+    input SRIA9;
+    input SRIA8;
+    input SRIA7;
+    input SRIA6;
+    input SRIA5;
+    input SRIA4;
+    input SRIA3;
+    input SRIA2;
+    input SRIA1;
+    input SRIA0;
+    input SRIB17;
+    input SRIB16;
+    input SRIB15;
+    input SRIB14;
+    input SRIB13;
+    input SRIB12;
+    input SRIB11;
+    input SRIB10;
+    input SRIB9;
+    input SRIB8;
+    input SRIB7;
+    input SRIB6;
+    input SRIB5;
+    input SRIB4;
+    input SRIB3;
+    input SRIB2;
+    input SRIB1;
+    input SRIB0;
+    output SROA17;
+    output SROA16;
+    output SROA15;
+    output SROA14;
+    output SROA13;
+    output SROA12;
+    output SROA11;
+    output SROA10;
+    output SROA9;
+    output SROA8;
+    output SROA7;
+    output SROA6;
+    output SROA5;
+    output SROA4;
+    output SROA3;
+    output SROA2;
+    output SROA1;
+    output SROA0;
+    output SROB17;
+    output SROB16;
+    output SROB15;
+    output SROB14;
+    output SROB13;
+    output SROB12;
+    output SROB11;
+    output SROB10;
+    output SROB9;
+    output SROB8;
+    output SROB7;
+    output SROB6;
+    output SROB5;
+    output SROB4;
+    output SROB3;
+    output SROB2;
+    output SROB1;
+    output SROB0;
+    output ROA17;
+    output ROA16;
+    output ROA15;
+    output ROA14;
+    output ROA13;
+    output ROA12;
+    output ROA11;
+    output ROA10;
+    output ROA9;
+    output ROA8;
+    output ROA7;
+    output ROA6;
+    output ROA5;
+    output ROA4;
+    output ROA3;
+    output ROA2;
+    output ROA1;
+    output ROA0;
+    output ROB17;
+    output ROB16;
+    output ROB15;
+    output ROB14;
+    output ROB13;
+    output ROB12;
+    output ROB11;
+    output ROB10;
+    output ROB9;
+    output ROB8;
+    output ROB7;
+    output ROB6;
+    output ROB5;
+    output ROB4;
+    output ROB3;
+    output ROB2;
+    output ROB1;
+    output ROB0;
+    output ROC17;
+    output ROC16;
+    output ROC15;
+    output ROC14;
+    output ROC13;
+    output ROC12;
+    output ROC11;
+    output ROC10;
+    output ROC9;
+    output ROC8;
+    output ROC7;
+    output ROC6;
+    output ROC5;
+    output ROC4;
+    output ROC3;
+    output ROC2;
+    output ROC1;
+    output ROC0;
+    output P35;
+    output P34;
+    output P33;
+    output P32;
+    output P31;
+    output P30;
+    output P29;
+    output P28;
+    output P27;
+    output P26;
+    output P25;
+    output P24;
+    output P23;
+    output P22;
+    output P21;
+    output P20;
+    output P19;
+    output P18;
+    output P17;
+    output P16;
+    output P15;
+    output P14;
+    output P13;
+    output P12;
+    output P11;
+    output P10;
+    output P9;
+    output P8;
+    output P7;
+    output P6;
+    output P5;
+    output P4;
+    output P3;
+    output P2;
+    output P1;
+    output P0;
+    output SIGNEDP;
+endmodule
+
+(* blackbox *)
+module ALU54B (...);
+    parameter REG_INPUTC0_CLK = "NONE";
+    parameter REG_INPUTC0_CE = "CE0";
+    parameter REG_INPUTC0_RST = "RST0";
+    parameter REG_INPUTC1_CLK = "NONE";
+    parameter REG_INPUTC1_CE = "CE0";
+    parameter REG_INPUTC1_RST = "RST0";
+    parameter REG_OPCODEOP0_0_CLK = "NONE";
+    parameter REG_OPCODEOP0_0_CE = "CE0";
+    parameter REG_OPCODEOP0_0_RST = "RST0";
+    parameter REG_OPCODEOP1_0_CLK = "NONE";
+    parameter REG_OPCODEOP0_1_CLK = "NONE";
+    parameter REG_OPCODEOP0_1_CE = "CE0";
+    parameter REG_OPCODEOP0_1_RST = "RST0";
+    parameter REG_OPCODEOP1_1_CLK = "NONE";
+    parameter REG_OPCODEIN_0_CLK = "NONE";
+    parameter REG_OPCODEIN_0_CE = "CE0";
+    parameter REG_OPCODEIN_0_RST = "RST0";
+    parameter REG_OPCODEIN_1_CLK = "NONE";
+    parameter REG_OPCODEIN_1_CE = "CE0";
+    parameter REG_OPCODEIN_1_RST = "RST0";
+    parameter REG_OUTPUT0_CLK = "NONE";
+    parameter REG_OUTPUT0_CE = "CE0";
+    parameter REG_OUTPUT0_RST = "RST0";
+    parameter REG_OUTPUT1_CLK = "NONE";
+    parameter REG_OUTPUT1_CE = "CE0";
+    parameter REG_OUTPUT1_RST = "RST0";
+    parameter REG_FLAG_CLK = "NONE";
+    parameter REG_FLAG_CE = "CE0";
+    parameter REG_FLAG_RST = "RST0";
+    parameter MCPAT_SOURCE = "STATIC";
+    parameter MASKPAT_SOURCE = "STATIC";
+    parameter MASK01 = "0x00000000000000";
+    parameter REG_INPUTCFB_CLK = "NONE";
+    parameter REG_INPUTCFB_CE = "CE0";
+    parameter REG_INPUTCFB_RST = "RST0";
+    parameter CLK0_DIV = "ENABLED";
+    parameter CLK1_DIV = "ENABLED";
+    parameter CLK2_DIV = "ENABLED";
+    parameter CLK3_DIV = "ENABLED";
+    parameter MCPAT = "0x00000000000000";
+    parameter MASKPAT = "0x00000000000000";
+    parameter RNDPAT = "0x00000000000000";
+    parameter GSR = "ENABLED";
+    parameter RESETMODE = "SYNC";
+    parameter MULT9_MODE = "DISABLED";
+    parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
+    parameter LEGACY = "DISABLED";
+    input CE3;
+    input CE2;
+    input CE1;
+    input CE0;
+    input CLK3;
+    input CLK2;
+    input CLK1;
+    input CLK0;
+    input RST3;
+    input RST2;
+    input RST1;
+    input RST0;
+    input SIGNEDIA;
+    input SIGNEDIB;
+    input SIGNEDCIN;
+    input A35;
+    input A34;
+    input A33;
+    input A32;
+    input A31;
+    input A30;
+    input A29;
+    input A28;
+    input A27;
+    input A26;
+    input A25;
+    input A24;
+    input A23;
+    input A22;
+    input A21;
+    input A20;
+    input A19;
+    input A18;
+    input A17;
+    input A16;
+    input A15;
+    input A14;
+    input A13;
+    input A12;
+    input A11;
+    input A10;
+    input A9;
+    input A8;
+    input A7;
+    input A6;
+    input A5;
+    input A4;
+    input A3;
+    input A2;
+    input A1;
+    input A0;
+    input B35;
+    input B34;
+    input B33;
+    input B32;
+    input B31;
+    input B30;
+    input B29;
+    input B28;
+    input B27;
+    input B26;
+    input B25;
+    input B24;
+    input B23;
+    input B22;
+    input B21;
+    input B20;
+    input B19;
+    input B18;
+    input B17;
+    input B16;
+    input B15;
+    input B14;
+    input B13;
+    input B12;
+    input B11;
+    input B10;
+    input B9;
+    input B8;
+    input B7;
+    input B6;
+    input B5;
+    input B4;
+    input B3;
+    input B2;
+    input B1;
+    input B0;
+    input C53;
+    input C52;
+    input C51;
+    input C50;
+    input C49;
+    input C48;
+    input C47;
+    input C46;
+    input C45;
+    input C44;
+    input C43;
+    input C42;
+    input C41;
+    input C40;
+    input C39;
+    input C38;
+    input C37;
+    input C36;
+    input C35;
+    input C34;
+    input C33;
+    input C32;
+    input C31;
+    input C30;
+    input C29;
+    input C28;
+    input C27;
+    input C26;
+    input C25;
+    input C24;
+    input C23;
+    input C22;
+    input C21;
+    input C20;
+    input C19;
+    input C18;
+    input C17;
+    input C16;
+    input C15;
+    input C14;
+    input C13;
+    input C12;
+    input C11;
+    input C10;
+    input C9;
+    input C8;
+    input C7;
+    input C6;
+    input C5;
+    input C4;
+    input C3;
+    input C2;
+    input C1;
+    input C0;
+    input CFB53;
+    input CFB52;
+    input CFB51;
+    input CFB50;
+    input CFB49;
+    input CFB48;
+    input CFB47;
+    input CFB46;
+    input CFB45;
+    input CFB44;
+    input CFB43;
+    input CFB42;
+    input CFB41;
+    input CFB40;
+    input CFB39;
+    input CFB38;
+    input CFB37;
+    input CFB36;
+    input CFB35;
+    input CFB34;
+    input CFB33;
+    input CFB32;
+    input CFB31;
+    input CFB30;
+    input CFB29;
+    input CFB28;
+    input CFB27;
+    input CFB26;
+    input CFB25;
+    input CFB24;
+    input CFB23;
+    input CFB22;
+    input CFB21;
+    input CFB20;
+    input CFB19;
+    input CFB18;
+    input CFB17;
+    input CFB16;
+    input CFB15;
+    input CFB14;
+    input CFB13;
+    input CFB12;
+    input CFB11;
+    input CFB10;
+    input CFB9;
+    input CFB8;
+    input CFB7;
+    input CFB6;
+    input CFB5;
+    input CFB4;
+    input CFB3;
+    input CFB2;
+    input CFB1;
+    input CFB0;
+    input MA35;
+    input MA34;
+    input MA33;
+    input MA32;
+    input MA31;
+    input MA30;
+    input MA29;
+    input MA28;
+    input MA27;
+    input MA26;
+    input MA25;
+    input MA24;
+    input MA23;
+    input MA22;
+    input MA21;
+    input MA20;
+    input MA19;
+    input MA18;
+    input MA17;
+    input MA16;
+    input MA15;
+    input MA14;
+    input MA13;
+    input MA12;
+    input MA11;
+    input MA10;
+    input MA9;
+    input MA8;
+    input MA7;
+    input MA6;
+    input MA5;
+    input MA4;
+    input MA3;
+    input MA2;
+    input MA1;
+    input MA0;
+    input MB35;
+    input MB34;
+    input MB33;
+    input MB32;
+    input MB31;
+    input MB30;
+    input MB29;
+    input MB28;
+    input MB27;
+    input MB26;
+    input MB25;
+    input MB24;
+    input MB23;
+    input MB22;
+    input MB21;
+    input MB20;
+    input MB19;
+    input MB18;
+    input MB17;
+    input MB16;
+    input MB15;
+    input MB14;
+    input MB13;
+    input MB12;
+    input MB11;
+    input MB10;
+    input MB9;
+    input MB8;
+    input MB7;
+    input MB6;
+    input MB5;
+    input MB4;
+    input MB3;
+    input MB2;
+    input MB1;
+    input MB0;
+    input CIN53;
+    input CIN52;
+    input CIN51;
+    input CIN50;
+    input CIN49;
+    input CIN48;
+    input CIN47;
+    input CIN46;
+    input CIN45;
+    input CIN44;
+    input CIN43;
+    input CIN42;
+    input CIN41;
+    input CIN40;
+    input CIN39;
+    input CIN38;
+    input CIN37;
+    input CIN36;
+    input CIN35;
+    input CIN34;
+    input CIN33;
+    input CIN32;
+    input CIN31;
+    input CIN30;
+    input CIN29;
+    input CIN28;
+    input CIN27;
+    input CIN26;
+    input CIN25;
+    input CIN24;
+    input CIN23;
+    input CIN22;
+    input CIN21;
+    input CIN20;
+    input CIN19;
+    input CIN18;
+    input CIN17;
+    input CIN16;
+    input CIN15;
+    input CIN14;
+    input CIN13;
+    input CIN12;
+    input CIN11;
+    input CIN10;
+    input CIN9;
+    input CIN8;
+    input CIN7;
+    input CIN6;
+    input CIN5;
+    input CIN4;
+    input CIN3;
+    input CIN2;
+    input CIN1;
+    input CIN0;
+    input OP10;
+    input OP9;
+    input OP8;
+    input OP7;
+    input OP6;
+    input OP5;
+    input OP4;
+    input OP3;
+    input OP2;
+    input OP1;
+    input OP0;
+    output R53;
+    output R52;
+    output R51;
+    output R50;
+    output R49;
+    output R48;
+    output R47;
+    output R46;
+    output R45;
+    output R44;
+    output R43;
+    output R42;
+    output R41;
+    output R40;
+    output R39;
+    output R38;
+    output R37;
+    output R36;
+    output R35;
+    output R34;
+    output R33;
+    output R32;
+    output R31;
+    output R30;
+    output R29;
+    output R28;
+    output R27;
+    output R26;
+    output R25;
+    output R24;
+    output R23;
+    output R22;
+    output R21;
+    output R20;
+    output R19;
+    output R18;
+    output R17;
+    output R16;
+    output R15;
+    output R14;
+    output R13;
+    output R12;
+    output R11;
+    output R10;
+    output R9;
+    output R8;
+    output R7;
+    output R6;
+    output R5;
+    output R4;
+    output R3;
+    output R2;
+    output R1;
+    output R0;
+    output CO53;
+    output CO52;
+    output CO51;
+    output CO50;
+    output CO49;
+    output CO48;
+    output CO47;
+    output CO46;
+    output CO45;
+    output CO44;
+    output CO43;
+    output CO42;
+    output CO41;
+    output CO40;
+    output CO39;
+    output CO38;
+    output CO37;
+    output CO36;
+    output CO35;
+    output CO34;
+    output CO33;
+    output CO32;
+    output CO31;
+    output CO30;
+    output CO29;
+    output CO28;
+    output CO27;
+    output CO26;
+    output CO25;
+    output CO24;
+    output CO23;
+    output CO22;
+    output CO21;
+    output CO20;
+    output CO19;
+    output CO18;
+    output CO17;
+    output CO16;
+    output CO15;
+    output CO14;
+    output CO13;
+    output CO12;
+    output CO11;
+    output CO10;
+    output CO9;
+    output CO8;
+    output CO7;
+    output CO6;
+    output CO5;
+    output CO4;
+    output CO3;
+    output CO2;
+    output CO1;
+    output CO0;
+    output EQZ;
+    output EQZM;
+    output EQOM;
+    output EQPAT;
+    output EQPATB;
+    output OVER;
+    output UNDER;
+    output OVERUNDER;
+    output SIGNEDR;
+endmodule
+
+(* blackbox *)
+module CLKDIVF (...);
+    parameter GSR = "DISABLED";
+    parameter DIV = "2.0";
+    input CLKI;
+    input RST;
+    input ALIGNWD;
+    output CDIVX;
+endmodule
+
+(* blackbox *)
+module PCSCLKDIV (...);
+    parameter GSR = "DISABLED";
+    input CLKI;
+    input RST;
+    input SEL2;
+    input SEL1;
+    input SEL0;
+    output CDIV1;
+    output CDIVX;
+endmodule
+
+(* blackbox *)
+module DCSC (...);
+    parameter DCSMODE = "POS";
+    input CLK1;
+    input CLK0;
+    input SEL1;
+    input SEL0;
+    input MODESEL;
+    output DCSOUT;
+endmodule
+
+(* blackbox *)
+module DCCA (...);
+    input CLKI;
+    input CE;
+    output CLKO;
+endmodule
+
+(* blackbox *)
+module ECLKSYNCB (...);
+    input ECLKI;
+    input STOP;
+    output ECLKO;
+endmodule
+
+(* blackbox *)
+module ECLKBRIDGECS (...);
+    input CLK0;
+    input CLK1;
+    input SEL;
+    output ECSOUT;
+endmodule
+
+(* blackbox *)
+module DELAYF (...);
+    parameter DEL_MODE = "USER_DEFINED";
+    parameter DEL_VALUE = 0;
+    input A;
+    input LOADN;
+    input MOVE;
+    input DIRECTION;
+    output Z;
+    output CFLAG;
+endmodule
+
+(* blackbox *)
+module DELAYG (...);
+    parameter DEL_MODE = "USER_DEFINED";
+    parameter DEL_VALUE = 0;
+    input A;
+    output Z;
+endmodule
+
+(* blackbox *) (* keep *)
+module USRMCLK (...);
+    input USRMCLKI;
+    input USRMCLKTS;
+endmodule
+
+(* blackbox *)
+module DQSBUFM (...);
+    parameter DQS_LI_DEL_VAL = 4;
+    parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
+    parameter DQS_LO_DEL_VAL = 0;
+    parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
+    parameter GSR = "ENABLED";
+    input DQSI;
+    input READ1;
+    input READ0;
+    input READCLKSEL2;
+    input READCLKSEL1;
+    input READCLKSEL0;
+    input DDRDEL;
+    input ECLK;
+    input SCLK;
+    input RST;
+    input DYNDELAY7;
+    input DYNDELAY6;
+    input DYNDELAY5;
+    input DYNDELAY4;
+    input DYNDELAY3;
+    input DYNDELAY2;
+    input DYNDELAY1;
+    input DYNDELAY0;
+    input PAUSE;
+    input RDLOADN;
+    input RDMOVE;
+    input RDDIRECTION;
+    input WRLOADN;
+    input WRMOVE;
+    input WRDIRECTION;
+    output DQSR90;
+    output DQSW;
+    output DQSW270;
+    output RDPNTR2;
+    output RDPNTR1;
+    output RDPNTR0;
+    output WRPNTR2;
+    output WRPNTR1;
+    output WRPNTR0;
+    output DATAVALID;
+    output BURSTDET;
+    output RDCFLAG;
+    output WRCFLAG;
+endmodule
+
+(* blackbox *)
+module DDRDLLA (...);
+    parameter FORCE_MAX_DELAY = "NO";
+    parameter GSR = "ENABLED";
+    input CLK;
+    input RST;
+    input UDDCNTLN;
+    input FREEZE;
+    output DDRDEL;
+    output LOCK;
+    output DCNTL7;
+    output DCNTL6;
+    output DCNTL5;
+    output DCNTL4;
+    output DCNTL3;
+    output DCNTL2;
+    output DCNTL1;
+    output DCNTL0;
+endmodule
+
+(* blackbox *)
+module DLLDELD (...);
+    input A;
+    input DDRDEL;
+    input LOADN;
+    input MOVE;
+    input DIRECTION;
+    output Z;
+    output CFLAG;
+endmodule
+
+(* blackbox *)
+module IDDRX1F (...);
+    parameter GSR = "ENABLED";
+    input D;
+    input SCLK;
+    input RST;
+    output Q0;
+    output Q1;
+endmodule
+
+(* blackbox *)
+module IDDRX2F (...);
+    parameter GSR = "ENABLED";
+    input D;
+    input SCLK;
+    input ECLK;
+    input RST;
+    input ALIGNWD;
+    output Q3;
+    output Q2;
+    output Q1;
+    output Q0;
+endmodule
+
+(* blackbox *)
+module IDDR71B (...);
+    parameter GSR = "ENABLED";
+    input D;
+    input SCLK;
+    input ECLK;
+    input RST;
+    input ALIGNWD;
+    output Q6;
+    output Q5;
+    output Q4;
+    output Q3;
+    output Q2;
+    output Q1;
+    output Q0;
+endmodule
+
+(* blackbox *)
+module IDDRX2DQA (...);
+    parameter GSR = "ENABLED";
+    input SCLK;
+    input ECLK;
+    input DQSR90;
+    input D;
+    input RST;
+    input RDPNTR2;
+    input RDPNTR1;
+    input RDPNTR0;
+    input WRPNTR2;
+    input WRPNTR1;
+    input WRPNTR0;
+    output Q3;
+    output Q2;
+    output Q1;
+    output Q0;
+    output QWL;
+endmodule
+
+(* blackbox *)
+module ODDRX1F (...);
+    parameter GSR = "ENABLED";
+    input SCLK;
+    input RST;
+    input D0;
+    input D1;
+    output Q;
+endmodule
+
+(* blackbox *)
+module ODDRX2F (...);
+    parameter GSR = "ENABLED";
+    input SCLK;
+    input ECLK;
+    input RST;
+    input D3;
+    input D2;
+    input D1;
+    input D0;
+    output Q;
+endmodule
+
+(* blackbox *)
+module ODDR71B (...);
+    parameter GSR = "ENABLED";
+    input SCLK;
+    input ECLK;
+    input RST;
+    input D6;
+    input D5;
+    input D4;
+    input D3;
+    input D2;
+    input D1;
+    input D0;
+    output Q;
+endmodule
+
+(* blackbox *)
+module OSHX2A (...);
+    parameter GSR = "ENABLED";
+    input D1;
+    input D0;
+    input SCLK;
+    input ECLK;
+    input RST;
+    output Q;
+endmodule
+
+(* blackbox *)
+module TSHX2DQA (...);
+    parameter GSR = "ENABLED";
+    parameter REGSET = "SET";
+    input T1;
+    input T0;
+    input SCLK;
+    input ECLK;
+    input DQSW270;
+    input RST;
+    output Q;
+endmodule
+
+(* blackbox *)
+module TSHX2DQSA (...);
+    parameter GSR = "ENABLED";
+    parameter REGSET = "SET";
+    input T1;
+    input T0;
+    input SCLK;
+    input ECLK;
+    input DQSW;
+    input RST;
+    output Q;
+endmodule
+
+(* blackbox *)
+module ODDRX2DQA (...);
+    parameter GSR = "ENABLED";
+    input D3;
+    input D2;
+    input D1;
+    input D0;
+    input DQSW270;
+    input SCLK;
+    input ECLK;
+    input RST;
+    output Q;
+endmodule
+
+(* blackbox *)
+module ODDRX2DQSB (...);
+    parameter GSR = "ENABLED";
+    input D3;
+    input D2;
+    input D1;
+    input D0;
+    input SCLK;
+    input ECLK;
+    input DQSW;
+    input RST;
+    output Q;
+endmodule
+
+(* blackbox *)
+module EHXPLLL (...);
+    parameter CLKI_DIV = 1;
+    parameter CLKFB_DIV = 1;
+    parameter CLKOP_DIV = 8;
+    parameter CLKOS_DIV = 8;
+    parameter CLKOS2_DIV = 8;
+    parameter CLKOS3_DIV = 8;
+    parameter CLKOP_ENABLE = "ENABLED";
+    parameter CLKOS_ENABLE = "DISABLED";
+    parameter CLKOS2_ENABLE = "DISABLED";
+    parameter CLKOS3_ENABLE = "DISABLED";
+    parameter CLKOP_CPHASE = 0;
+    parameter CLKOS_CPHASE = 0;
+    parameter CLKOS2_CPHASE = 0;
+    parameter CLKOS3_CPHASE = 0;
+    parameter CLKOP_FPHASE = 0;
+    parameter CLKOS_FPHASE = 0;
+    parameter CLKOS2_FPHASE = 0;
+    parameter CLKOS3_FPHASE = 0;
+    parameter FEEDBK_PATH = "CLKOP";
+    parameter CLKOP_TRIM_POL = "RISING";
+    parameter CLKOP_TRIM_DELAY = 0;
+    parameter CLKOS_TRIM_POL = "RISING";
+    parameter CLKOS_TRIM_DELAY = 0;
+    parameter OUTDIVIDER_MUXA = "DIVA";
+    parameter OUTDIVIDER_MUXB = "DIVB";
+    parameter OUTDIVIDER_MUXC = "DIVC";
+    parameter OUTDIVIDER_MUXD = "DIVD";
+    parameter PLL_LOCK_MODE = 0;
+    parameter PLL_LOCK_DELAY = 200;
+    parameter STDBY_ENABLE = "DISABLED";
+    parameter REFIN_RESET = "DISABLED";
+    parameter SYNC_ENABLE = "DISABLED";
+    parameter INT_LOCK_STICKY = "ENABLED";
+    parameter DPHASE_SOURCE = "DISABLED";
+    parameter PLLRST_ENA = "DISABLED";
+    parameter INTFB_WAKE = "DISABLED";
+    input CLKI;
+    input CLKFB;
+    input PHASESEL1;
+    input PHASESEL0;
+    input PHASEDIR;
+    input PHASESTEP;
+    input PHASELOADREG;
+    input STDBY;
+    input PLLWAKESYNC;
+    input RST;
+    input ENCLKOP;
+    input ENCLKOS;
+    input ENCLKOS2;
+    input ENCLKOS3;
+    output CLKOP;
+    output CLKOS;
+    output CLKOS2;
+    output CLKOS3;
+    output LOCK;
+    output INTLOCK;
+    output REFCLK;
+    output CLKINTFB;
+endmodule
+
+(* blackbox *)
+module DTR (...);
+    parameter DTR_TEMP = 25;
+    input STARTPULSE;
+    output DTROUT7;
+    output DTROUT6;
+    output DTROUT5;
+    output DTROUT4;
+    output DTROUT3;
+    output DTROUT2;
+    output DTROUT1;
+    output DTROUT0;
+endmodule
+
+(* blackbox *)
+module OSCG (...);
+    parameter DIV = 128;
+    output OSC;
+endmodule
+
+(* blackbox *)
+module EXTREFB (...);
+    parameter REFCK_PWDNB = "DONTCARE";
+    parameter REFCK_RTERM = "DONTCARE";
+    parameter REFCK_DCBIAS_EN = "DONTCARE";
+    (* iopad_external_pin *)
+    input REFCLKP;
+    (* iopad_external_pin *)
+    input REFCLKN;
+    output REFCLKO;
+endmodule
+
+(* blackbox *) (* keep *)
+module JTAGG (...);
+    parameter ER1 = "ENABLED";
+    parameter ER2 = "ENABLED";
+    (* iopad_external_pin *)
+    input TCK;
+    (* iopad_external_pin *)
+    input TMS;
+    (* iopad_external_pin *)
+    input TDI;
+    input JTDO2;
+    input JTDO1;
+    (* iopad_external_pin *)
+    output TDO;
+    output JTDI;
+    output JTCK;
+    output JRTI2;
+    output JRTI1;
+    output JSHIFT;
+    output JUPDATE;
+    output JRSTN;
+    output JCE2;
+    output JCE1;
+endmodule
+
+(* blackbox *) (* keep *)
+module DCUA (...);
+    parameter D_MACROPDB = "DONTCARE";
+    parameter D_IB_PWDNB = "DONTCARE";
+    parameter D_XGE_MODE = "DONTCARE";
+    parameter D_LOW_MARK = "DONTCARE";
+    parameter D_HIGH_MARK = "DONTCARE";
+    parameter D_BUS8BIT_SEL = "DONTCARE";
+    parameter D_CDR_LOL_SET = "DONTCARE";
+    parameter D_BITCLK_LOCAL_EN = "DONTCARE";
+    parameter D_BITCLK_ND_EN = "DONTCARE";
+    parameter D_BITCLK_FROM_ND_EN = "DONTCARE";
+    parameter D_SYNC_LOCAL_EN = "DONTCARE";
+    parameter D_SYNC_ND_EN = "DONTCARE";
+    parameter CH0_UC_MODE = "DONTCARE";
+    parameter CH1_UC_MODE = "DONTCARE";
+    parameter CH0_PCIE_MODE = "DONTCARE";
+    parameter CH1_PCIE_MODE = "DONTCARE";
+    parameter CH0_RIO_MODE = "DONTCARE";
+    parameter CH1_RIO_MODE = "DONTCARE";
+    parameter CH0_WA_MODE = "DONTCARE";
+    parameter CH1_WA_MODE = "DONTCARE";
+    parameter CH0_INVERT_RX = "DONTCARE";
+    parameter CH1_INVERT_RX = "DONTCARE";
+    parameter CH0_INVERT_TX = "DONTCARE";
+    parameter CH1_INVERT_TX = "DONTCARE";
+    parameter CH0_PRBS_SELECTION = "DONTCARE";
+    parameter CH1_PRBS_SELECTION = "DONTCARE";
+    parameter CH0_GE_AN_ENABLE = "DONTCARE";
+    parameter CH1_GE_AN_ENABLE = "DONTCARE";
+    parameter CH0_PRBS_LOCK = "DONTCARE";
+    parameter CH1_PRBS_LOCK = "DONTCARE";
+    parameter CH0_PRBS_ENABLE = "DONTCARE";
+    parameter CH1_PRBS_ENABLE = "DONTCARE";
+    parameter CH0_ENABLE_CG_ALIGN = "DONTCARE";
+    parameter CH1_ENABLE_CG_ALIGN = "DONTCARE";
+    parameter CH0_TX_GEAR_MODE = "DONTCARE";
+    parameter CH1_TX_GEAR_MODE = "DONTCARE";
+    parameter CH0_RX_GEAR_MODE = "DONTCARE";
+    parameter CH1_RX_GEAR_MODE = "DONTCARE";
+    parameter CH0_PCS_DET_TIME_SEL = "DONTCARE";
+    parameter CH1_PCS_DET_TIME_SEL = "DONTCARE";
+    parameter CH0_PCIE_EI_EN = "DONTCARE";
+    parameter CH1_PCIE_EI_EN = "DONTCARE";
+    parameter CH0_TX_GEAR_BYPASS = "DONTCARE";
+    parameter CH1_TX_GEAR_BYPASS = "DONTCARE";
+    parameter CH0_ENC_BYPASS = "DONTCARE";
+    parameter CH1_ENC_BYPASS = "DONTCARE";
+    parameter CH0_SB_BYPASS = "DONTCARE";
+    parameter CH1_SB_BYPASS = "DONTCARE";
+    parameter CH0_RX_SB_BYPASS = "DONTCARE";
+    parameter CH1_RX_SB_BYPASS = "DONTCARE";
+    parameter CH0_WA_BYPASS = "DONTCARE";
+    parameter CH1_WA_BYPASS = "DONTCARE";
+    parameter CH0_DEC_BYPASS = "DONTCARE";
+    parameter CH1_DEC_BYPASS = "DONTCARE";
+    parameter CH0_CTC_BYPASS = "DONTCARE";
+    parameter CH1_CTC_BYPASS = "DONTCARE";
+    parameter CH0_RX_GEAR_BYPASS = "DONTCARE";
+    parameter CH1_RX_GEAR_BYPASS = "DONTCARE";
+    parameter CH0_LSM_DISABLE = "DONTCARE";
+    parameter CH1_LSM_DISABLE = "DONTCARE";
+    parameter CH0_MATCH_2_ENABLE = "DONTCARE";
+    parameter CH1_MATCH_2_ENABLE = "DONTCARE";
+    parameter CH0_MATCH_4_ENABLE = "DONTCARE";
+    parameter CH1_MATCH_4_ENABLE = "DONTCARE";
+    parameter CH0_MIN_IPG_CNT = "DONTCARE";
+    parameter CH1_MIN_IPG_CNT = "DONTCARE";
+    parameter CH0_CC_MATCH_1 = "DONTCARE";
+    parameter CH1_CC_MATCH_1 = "DONTCARE";
+    parameter CH0_CC_MATCH_2 = "DONTCARE";
+    parameter CH1_CC_MATCH_2 = "DONTCARE";
+    parameter CH0_CC_MATCH_3 = "DONTCARE";
+    parameter CH1_CC_MATCH_3 = "DONTCARE";
+    parameter CH0_CC_MATCH_4 = "DONTCARE";
+    parameter CH1_CC_MATCH_4 = "DONTCARE";
+    parameter CH0_UDF_COMMA_MASK = "DONTCARE";
+    parameter CH1_UDF_COMMA_MASK = "DONTCARE";
+    parameter CH0_UDF_COMMA_A = "DONTCARE";
+    parameter CH1_UDF_COMMA_A = "DONTCARE";
+    parameter CH0_UDF_COMMA_B = "DONTCARE";
+    parameter CH1_UDF_COMMA_B = "DONTCARE";
+    parameter CH0_RX_DCO_CK_DIV = "DONTCARE";
+    parameter CH1_RX_DCO_CK_DIV = "DONTCARE";
+    parameter CH0_RCV_DCC_EN = "DONTCARE";
+    parameter CH1_RCV_DCC_EN = "DONTCARE";
+    parameter CH0_REQ_LVL_SET = "DONTCARE";
+    parameter CH1_REQ_LVL_SET = "DONTCARE";
+    parameter CH0_REQ_EN = "DONTCARE";
+    parameter CH1_REQ_EN = "DONTCARE";
+    parameter CH0_RTERM_RX = "DONTCARE";
+    parameter CH1_RTERM_RX = "DONTCARE";
+    parameter CH0_PDEN_SEL = "DONTCARE";
+    parameter CH1_PDEN_SEL = "DONTCARE";
+    parameter CH0_LDR_RX2CORE_SEL = "DONTCARE";
+    parameter CH1_LDR_RX2CORE_SEL = "DONTCARE";
+    parameter CH0_LDR_CORE2TX_SEL = "DONTCARE";
+    parameter CH1_LDR_CORE2TX_SEL = "DONTCARE";
+    parameter CH0_TPWDNB = "DONTCARE";
+    parameter CH1_TPWDNB = "DONTCARE";
+    parameter CH0_RATE_MODE_TX = "DONTCARE";
+    parameter CH1_RATE_MODE_TX = "DONTCARE";
+    parameter CH0_RTERM_TX = "DONTCARE";
+    parameter CH1_RTERM_TX = "DONTCARE";
+    parameter CH0_TX_CM_SEL = "DONTCARE";
+    parameter CH1_TX_CM_SEL = "DONTCARE";
+    parameter CH0_TDRV_PRE_EN = "DONTCARE";
+    parameter CH1_TDRV_PRE_EN = "DONTCARE";
+    parameter CH0_TDRV_SLICE0_SEL = "DONTCARE";
+    parameter CH1_TDRV_SLICE0_SEL = "DONTCARE";
+    parameter CH0_TDRV_SLICE1_SEL = "DONTCARE";
+    parameter CH1_TDRV_SLICE1_SEL = "DONTCARE";
+    parameter CH0_TDRV_SLICE2_SEL = "DONTCARE";
+    parameter CH1_TDRV_SLICE2_SEL = "DONTCARE";
+    parameter CH0_TDRV_SLICE3_SEL = "DONTCARE";
+    parameter CH1_TDRV_SLICE3_SEL = "DONTCARE";
+    parameter CH0_TDRV_SLICE4_SEL = "DONTCARE";
+    parameter CH1_TDRV_SLICE4_SEL = "DONTCARE";
+    parameter CH0_TDRV_SLICE5_SEL = "DONTCARE";
+    parameter CH1_TDRV_SLICE5_SEL = "DONTCARE";
+    parameter CH0_TDRV_SLICE0_CUR = "DONTCARE";
+    parameter CH1_TDRV_SLICE0_CUR = "DONTCARE";
+    parameter CH0_TDRV_SLICE1_CUR = "DONTCARE";
+    parameter CH1_TDRV_SLICE1_CUR = "DONTCARE";
+    parameter CH0_TDRV_SLICE2_CUR = "DONTCARE";
+    parameter CH1_TDRV_SLICE2_CUR = "DONTCARE";
+    parameter CH0_TDRV_SLICE3_CUR = "DONTCARE";
+    parameter CH1_TDRV_SLICE3_CUR = "DONTCARE";
+    parameter CH0_TDRV_SLICE4_CUR = "DONTCARE";
+    parameter CH1_TDRV_SLICE4_CUR = "DONTCARE";
+    parameter CH0_TDRV_SLICE5_CUR = "DONTCARE";
+    parameter CH1_TDRV_SLICE5_CUR = "DONTCARE";
+    parameter CH0_TDRV_DAT_SEL = "DONTCARE";
+    parameter CH1_TDRV_DAT_SEL = "DONTCARE";
+    parameter CH0_TX_DIV11_SEL = "DONTCARE";
+    parameter CH1_TX_DIV11_SEL = "DONTCARE";
+    parameter CH0_RPWDNB = "DONTCARE";
+    parameter CH1_RPWDNB = "DONTCARE";
+    parameter CH0_RATE_MODE_RX = "DONTCARE";
+    parameter CH1_RATE_MODE_RX = "DONTCARE";
+    parameter CH0_RLOS_SEL = "DONTCARE";
+    parameter CH1_RLOS_SEL = "DONTCARE";
+    parameter CH0_RX_LOS_LVL = "DONTCARE";
+    parameter CH1_RX_LOS_LVL = "DONTCARE";
+    parameter CH0_RX_LOS_CEQ = "DONTCARE";
+    parameter CH1_RX_LOS_CEQ = "DONTCARE";
+    parameter CH0_RX_LOS_HYST_EN = "DONTCARE";
+    parameter CH1_RX_LOS_HYST_EN = "DONTCARE";
+    parameter CH0_RX_LOS_EN = "DONTCARE";
+    parameter CH1_RX_LOS_EN = "DONTCARE";
+    parameter CH0_RX_DIV11_SEL = "DONTCARE";
+    parameter CH1_RX_DIV11_SEL = "DONTCARE";
+    parameter CH0_SEL_SD_RX_CLK = "DONTCARE";
+    parameter CH1_SEL_SD_RX_CLK = "DONTCARE";
+    parameter CH0_FF_RX_H_CLK_EN = "DONTCARE";
+    parameter CH1_FF_RX_H_CLK_EN = "DONTCARE";
+    parameter CH0_FF_RX_F_CLK_DIS = "DONTCARE";
+    parameter CH1_FF_RX_F_CLK_DIS = "DONTCARE";
+    parameter CH0_FF_TX_H_CLK_EN = "DONTCARE";
+    parameter CH1_FF_TX_H_CLK_EN = "DONTCARE";
+    parameter CH0_FF_TX_F_CLK_DIS = "DONTCARE";
+    parameter CH1_FF_TX_F_CLK_DIS = "DONTCARE";
+    parameter CH0_RX_RATE_SEL = "DONTCARE";
+    parameter CH1_RX_RATE_SEL = "DONTCARE";
+    parameter CH0_TDRV_POST_EN = "DONTCARE";
+    parameter CH1_TDRV_POST_EN = "DONTCARE";
+    parameter CH0_TX_POST_SIGN = "DONTCARE";
+    parameter CH1_TX_POST_SIGN = "DONTCARE";
+    parameter CH0_TX_PRE_SIGN = "DONTCARE";
+    parameter CH1_TX_PRE_SIGN = "DONTCARE";
+    parameter CH0_RXTERM_CM = "DONTCARE";
+    parameter CH1_RXTERM_CM = "DONTCARE";
+    parameter CH0_RXIN_CM = "DONTCARE";
+    parameter CH1_RXIN_CM = "DONTCARE";
+    parameter CH0_LEQ_OFFSET_SEL = "DONTCARE";
+    parameter CH1_LEQ_OFFSET_SEL = "DONTCARE";
+    parameter CH0_LEQ_OFFSET_TRIM = "DONTCARE";
+    parameter CH1_LEQ_OFFSET_TRIM = "DONTCARE";
+    parameter D_TX_MAX_RATE = "DONTCARE";
+    parameter CH0_CDR_MAX_RATE = "DONTCARE";
+    parameter CH1_CDR_MAX_RATE = "DONTCARE";
+    parameter CH0_TXAMPLITUDE = "DONTCARE";
+    parameter CH1_TXAMPLITUDE = "DONTCARE";
+    parameter CH0_TXDEPRE = "DONTCARE";
+    parameter CH1_TXDEPRE = "DONTCARE";
+    parameter CH0_TXDEPOST = "DONTCARE";
+    parameter CH1_TXDEPOST = "DONTCARE";
+    parameter CH0_PROTOCOL = "DONTCARE";
+    parameter CH1_PROTOCOL = "DONTCARE";
+    parameter D_ISETLOS = "DONTCARE";
+    parameter D_SETIRPOLY_AUX = "DONTCARE";
+    parameter D_SETICONST_AUX = "DONTCARE";
+    parameter D_SETIRPOLY_CH = "DONTCARE";
+    parameter D_SETICONST_CH = "DONTCARE";
+    parameter D_REQ_ISET = "DONTCARE";
+    parameter D_PD_ISET = "DONTCARE";
+    parameter D_DCO_CALIB_TIME_SEL = "DONTCARE";
+    parameter CH0_DCOCTLGI = "DONTCARE";
+    parameter CH1_DCOCTLGI = "DONTCARE";
+    parameter CH0_DCOATDDLY = "DONTCARE";
+    parameter CH1_DCOATDDLY = "DONTCARE";
+    parameter CH0_DCOATDCFG = "DONTCARE";
+    parameter CH1_DCOATDCFG = "DONTCARE";
+    parameter CH0_DCOBYPSATD = "DONTCARE";
+    parameter CH1_DCOBYPSATD = "DONTCARE";
+    parameter CH0_DCOSCALEI = "DONTCARE";
+    parameter CH1_DCOSCALEI = "DONTCARE";
+    parameter CH0_DCOITUNE4LSB = "DONTCARE";
+    parameter CH1_DCOITUNE4LSB = "DONTCARE";
+    parameter CH0_DCOIOSTUNE = "DONTCARE";
+    parameter CH1_DCOIOSTUNE = "DONTCARE";
+    parameter CH0_DCODISBDAVOID = "DONTCARE";
+    parameter CH1_DCODISBDAVOID = "DONTCARE";
+    parameter CH0_DCOCALDIV = "DONTCARE";
+    parameter CH1_DCOCALDIV = "DONTCARE";
+    parameter CH0_DCONUOFLSB = "DONTCARE";
+    parameter CH1_DCONUOFLSB = "DONTCARE";
+    parameter CH0_DCOIUPDNX2 = "DONTCARE";
+    parameter CH1_DCOIUPDNX2 = "DONTCARE";
+    parameter CH0_DCOSTEP = "DONTCARE";
+    parameter CH1_DCOSTEP = "DONTCARE";
+    parameter CH0_DCOSTARTVAL = "DONTCARE";
+    parameter CH1_DCOSTARTVAL = "DONTCARE";
+    parameter CH0_DCOFLTDAC = "DONTCARE";
+    parameter CH1_DCOFLTDAC = "DONTCARE";
+    parameter CH0_DCOITUNE = "DONTCARE";
+    parameter CH1_DCOITUNE = "DONTCARE";
+    parameter CH0_DCOFTNRG = "DONTCARE";
+    parameter CH1_DCOFTNRG = "DONTCARE";
+    parameter CH0_CDR_CNT4SEL = "DONTCARE";
+    parameter CH1_CDR_CNT4SEL = "DONTCARE";
+    parameter CH0_CDR_CNT8SEL = "DONTCARE";
+    parameter CH1_CDR_CNT8SEL = "DONTCARE";
+    parameter CH0_BAND_THRESHOLD = "DONTCARE";
+    parameter CH1_BAND_THRESHOLD = "DONTCARE";
+    parameter CH0_AUTO_FACQ_EN = "DONTCARE";
+    parameter CH1_AUTO_FACQ_EN = "DONTCARE";
+    parameter CH0_AUTO_CALIB_EN = "DONTCARE";
+    parameter CH1_AUTO_CALIB_EN = "DONTCARE";
+    parameter CH0_CALIB_CK_MODE = "DONTCARE";
+    parameter CH1_CALIB_CK_MODE = "DONTCARE";
+    parameter CH0_REG_BAND_OFFSET = "DONTCARE";
+    parameter CH1_REG_BAND_OFFSET = "DONTCARE";
+    parameter CH0_REG_BAND_SEL = "DONTCARE";
+    parameter CH1_REG_BAND_SEL = "DONTCARE";
+    parameter CH0_REG_IDAC_SEL = "DONTCARE";
+    parameter CH1_REG_IDAC_SEL = "DONTCARE";
+    parameter CH0_REG_IDAC_EN = "DONTCARE";
+    parameter CH1_REG_IDAC_EN = "DONTCARE";
+    parameter D_TXPLL_PWDNB = "DONTCARE";
+    parameter D_SETPLLRC = "DONTCARE";
+    parameter D_REFCK_MODE = "DONTCARE";
+    parameter D_TX_VCO_CK_DIV = "DONTCARE";
+    parameter D_PLL_LOL_SET = "DONTCARE";
+    parameter D_RG_EN = "DONTCARE";
+    parameter D_RG_SET = "DONTCARE";
+    parameter D_CMUSETISCL4VCO = "DONTCARE";
+    parameter D_CMUSETI4VCO = "DONTCARE";
+    parameter D_CMUSETINITVCT = "DONTCARE";
+    parameter D_CMUSETZGM = "DONTCARE";
+    parameter D_CMUSETP2AGM = "DONTCARE";
+    parameter D_CMUSETP1GM = "DONTCARE";
+    parameter D_CMUSETI4CPZ = "DONTCARE";
+    parameter D_CMUSETI4CPP = "DONTCARE";
+    parameter D_CMUSETICP4Z = "DONTCARE";
+    parameter D_CMUSETICP4P = "DONTCARE";
+    parameter D_CMUSETBIASI = "DONTCARE";
+    (* iopad_external_pin *)
+    (* iopad_external_pin *)
+    input CH0_HDINP;
+    (* iopad_external_pin *)
+    input CH1_HDINP;
+    (* iopad_external_pin *)
+    input CH0_HDINN;
+    (* iopad_external_pin *)
+    input CH1_HDINN;
+    input D_TXBIT_CLKP_FROM_ND;
+    input D_TXBIT_CLKN_FROM_ND;
+    input D_SYNC_ND;
+    input D_TXPLL_LOL_FROM_ND;
+    input CH0_RX_REFCLK;
+    input CH1_RX_REFCLK;
+    input CH0_FF_RXI_CLK;
+    input CH1_FF_RXI_CLK;
+    input CH0_FF_TXI_CLK;
+    input CH1_FF_TXI_CLK;
+    input CH0_FF_EBRD_CLK;
+    input CH1_FF_EBRD_CLK;
+    input CH0_FF_TX_D_0;
+    input CH1_FF_TX_D_0;
+    input CH0_FF_TX_D_1;
+    input CH1_FF_TX_D_1;
+    input CH0_FF_TX_D_2;
+    input CH1_FF_TX_D_2;
+    input CH0_FF_TX_D_3;
+    input CH1_FF_TX_D_3;
+    input CH0_FF_TX_D_4;
+    input CH1_FF_TX_D_4;
+    input CH0_FF_TX_D_5;
+    input CH1_FF_TX_D_5;
+    input CH0_FF_TX_D_6;
+    input CH1_FF_TX_D_6;
+    input CH0_FF_TX_D_7;
+    input CH1_FF_TX_D_7;
+    input CH0_FF_TX_D_8;
+    input CH1_FF_TX_D_8;
+    input CH0_FF_TX_D_9;
+    input CH1_FF_TX_D_9;
+    input CH0_FF_TX_D_10;
+    input CH1_FF_TX_D_10;
+    input CH0_FF_TX_D_11;
+    input CH1_FF_TX_D_11;
+    input CH0_FF_TX_D_12;
+    input CH1_FF_TX_D_12;
+    input CH0_FF_TX_D_13;
+    input CH1_FF_TX_D_13;
+    input CH0_FF_TX_D_14;
+    input CH1_FF_TX_D_14;
+    input CH0_FF_TX_D_15;
+    input CH1_FF_TX_D_15;
+    input CH0_FF_TX_D_16;
+    input CH1_FF_TX_D_16;
+    input CH0_FF_TX_D_17;
+    input CH1_FF_TX_D_17;
+    input CH0_FF_TX_D_18;
+    input CH1_FF_TX_D_18;
+    input CH0_FF_TX_D_19;
+    input CH1_FF_TX_D_19;
+    input CH0_FF_TX_D_20;
+    input CH1_FF_TX_D_20;
+    input CH0_FF_TX_D_21;
+    input CH1_FF_TX_D_21;
+    input CH0_FF_TX_D_22;
+    input CH1_FF_TX_D_22;
+    input CH0_FF_TX_D_23;
+    input CH1_FF_TX_D_23;
+    input CH0_FFC_EI_EN;
+    input CH1_FFC_EI_EN;
+    input CH0_FFC_PCIE_DET_EN;
+    input CH1_FFC_PCIE_DET_EN;
+    input CH0_FFC_PCIE_CT;
+    input CH1_FFC_PCIE_CT;
+    input CH0_FFC_SB_INV_RX;
+    input CH1_FFC_SB_INV_RX;
+    input CH0_FFC_ENABLE_CGALIGN;
+    input CH1_FFC_ENABLE_CGALIGN;
+    input CH0_FFC_SIGNAL_DETECT;
+    input CH1_FFC_SIGNAL_DETECT;
+    input CH0_FFC_FB_LOOPBACK;
+    input CH1_FFC_FB_LOOPBACK;
+    input CH0_FFC_SB_PFIFO_LP;
+    input CH1_FFC_SB_PFIFO_LP;
+    input CH0_FFC_PFIFO_CLR;
+    input CH1_FFC_PFIFO_CLR;
+    input CH0_FFC_RATE_MODE_RX;
+    input CH1_FFC_RATE_MODE_RX;
+    input CH0_FFC_RATE_MODE_TX;
+    input CH1_FFC_RATE_MODE_TX;
+    input CH0_FFC_DIV11_MODE_RX;
+    input CH1_FFC_DIV11_MODE_RX;
+    input CH0_FFC_RX_GEAR_MODE;
+    input CH1_FFC_RX_GEAR_MODE;
+    input CH0_FFC_TX_GEAR_MODE;
+    input CH1_FFC_TX_GEAR_MODE;
+    input CH0_FFC_DIV11_MODE_TX;
+    input CH1_FFC_DIV11_MODE_TX;
+    input CH0_FFC_LDR_CORE2TX_EN;
+    input CH1_FFC_LDR_CORE2TX_EN;
+    input CH0_FFC_LANE_TX_RST;
+    input CH1_FFC_LANE_TX_RST;
+    input CH0_FFC_LANE_RX_RST;
+    input CH1_FFC_LANE_RX_RST;
+    input CH0_FFC_RRST;
+    input CH1_FFC_RRST;
+    input CH0_FFC_TXPWDNB;
+    input CH1_FFC_TXPWDNB;
+    input CH0_FFC_RXPWDNB;
+    input CH1_FFC_RXPWDNB;
+    input CH0_LDR_CORE2TX;
+    input CH1_LDR_CORE2TX;
+    input D_SCIWDATA0;
+    input D_SCIWDATA1;
+    input D_SCIWDATA2;
+    input D_SCIWDATA3;
+    input D_SCIWDATA4;
+    input D_SCIWDATA5;
+    input D_SCIWDATA6;
+    input D_SCIWDATA7;
+    input D_SCIADDR0;
+    input D_SCIADDR1;
+    input D_SCIADDR2;
+    input D_SCIADDR3;
+    input D_SCIADDR4;
+    input D_SCIADDR5;
+    input D_SCIENAUX;
+    input D_SCISELAUX;
+    input CH0_SCIEN;
+    input CH1_SCIEN;
+    input CH0_SCISEL;
+    input CH1_SCISEL;
+    input D_SCIRD;
+    input D_SCIWSTN;
+    input D_CYAWSTN;
+    input D_FFC_SYNC_TOGGLE;
+    input D_FFC_DUAL_RST;
+    input D_FFC_MACRO_RST;
+    input D_FFC_MACROPDB;
+    input D_FFC_TRST;
+    input CH0_FFC_CDR_EN_BITSLIP;
+    input CH1_FFC_CDR_EN_BITSLIP;
+    input D_SCAN_ENABLE;
+    input D_SCAN_IN_0;
+    input D_SCAN_IN_1;
+    input D_SCAN_IN_2;
+    input D_SCAN_IN_3;
+    input D_SCAN_IN_4;
+    input D_SCAN_IN_5;
+    input D_SCAN_IN_6;
+    input D_SCAN_IN_7;
+    input D_SCAN_MODE;
+    input D_SCAN_RESET;
+    input D_CIN0;
+    input D_CIN1;
+    input D_CIN2;
+    input D_CIN3;
+    input D_CIN4;
+    input D_CIN5;
+    input D_CIN6;
+    input D_CIN7;
+    input D_CIN8;
+    input D_CIN9;
+    input D_CIN10;
+    input D_CIN11;
+    output CH0_HDOUTP;
+    output CH1_HDOUTP;
+    output CH0_HDOUTN;
+    output CH1_HDOUTN;
+    output D_TXBIT_CLKP_TO_ND;
+    output D_TXBIT_CLKN_TO_ND;
+    output D_SYNC_PULSE2ND;
+    output D_TXPLL_LOL_TO_ND;
+    output CH0_FF_RX_F_CLK;
+    output CH1_FF_RX_F_CLK;
+    output CH0_FF_RX_H_CLK;
+    output CH1_FF_RX_H_CLK;
+    output CH0_FF_TX_F_CLK;
+    output CH1_FF_TX_F_CLK;
+    output CH0_FF_TX_H_CLK;
+    output CH1_FF_TX_H_CLK;
+    output CH0_FF_RX_PCLK;
+    output CH1_FF_RX_PCLK;
+    output CH0_FF_TX_PCLK;
+    output CH1_FF_TX_PCLK;
+    output CH0_FF_RX_D_0;
+    output CH1_FF_RX_D_0;
+    output CH0_FF_RX_D_1;
+    output CH1_FF_RX_D_1;
+    output CH0_FF_RX_D_2;
+    output CH1_FF_RX_D_2;
+    output CH0_FF_RX_D_3;
+    output CH1_FF_RX_D_3;
+    output CH0_FF_RX_D_4;
+    output CH1_FF_RX_D_4;
+    output CH0_FF_RX_D_5;
+    output CH1_FF_RX_D_5;
+    output CH0_FF_RX_D_6;
+    output CH1_FF_RX_D_6;
+    output CH0_FF_RX_D_7;
+    output CH1_FF_RX_D_7;
+    output CH0_FF_RX_D_8;
+    output CH1_FF_RX_D_8;
+    output CH0_FF_RX_D_9;
+    output CH1_FF_RX_D_9;
+    output CH0_FF_RX_D_10;
+    output CH1_FF_RX_D_10;
+    output CH0_FF_RX_D_11;
+    output CH1_FF_RX_D_11;
+    output CH0_FF_RX_D_12;
+    output CH1_FF_RX_D_12;
+    output CH0_FF_RX_D_13;
+    output CH1_FF_RX_D_13;
+    output CH0_FF_RX_D_14;
+    output CH1_FF_RX_D_14;
+    output CH0_FF_RX_D_15;
+    output CH1_FF_RX_D_15;
+    output CH0_FF_RX_D_16;
+    output CH1_FF_RX_D_16;
+    output CH0_FF_RX_D_17;
+    output CH1_FF_RX_D_17;
+    output CH0_FF_RX_D_18;
+    output CH1_FF_RX_D_18;
+    output CH0_FF_RX_D_19;
+    output CH1_FF_RX_D_19;
+    output CH0_FF_RX_D_20;
+    output CH1_FF_RX_D_20;
+    output CH0_FF_RX_D_21;
+    output CH1_FF_RX_D_21;
+    output CH0_FF_RX_D_22;
+    output CH1_FF_RX_D_22;
+    output CH0_FF_RX_D_23;
+    output CH1_FF_RX_D_23;
+    output CH0_FFS_PCIE_DONE;
+    output CH1_FFS_PCIE_DONE;
+    output CH0_FFS_PCIE_CON;
+    output CH1_FFS_PCIE_CON;
+    output CH0_FFS_RLOS;
+    output CH1_FFS_RLOS;
+    output CH0_FFS_LS_SYNC_STATUS;
+    output CH1_FFS_LS_SYNC_STATUS;
+    output CH0_FFS_CC_UNDERRUN;
+    output CH1_FFS_CC_UNDERRUN;
+    output CH0_FFS_CC_OVERRUN;
+    output CH1_FFS_CC_OVERRUN;
+    output CH0_FFS_RXFBFIFO_ERROR;
+    output CH1_FFS_RXFBFIFO_ERROR;
+    output CH0_FFS_TXFBFIFO_ERROR;
+    output CH1_FFS_TXFBFIFO_ERROR;
+    output CH0_FFS_RLOL;
+    output CH1_FFS_RLOL;
+    output CH0_FFS_SKP_ADDED;
+    output CH1_FFS_SKP_ADDED;
+    output CH0_FFS_SKP_DELETED;
+    output CH1_FFS_SKP_DELETED;
+    output CH0_LDR_RX2CORE;
+    output CH1_LDR_RX2CORE;
+    output D_SCIRDATA0;
+    output D_SCIRDATA1;
+    output D_SCIRDATA2;
+    output D_SCIRDATA3;
+    output D_SCIRDATA4;
+    output D_SCIRDATA5;
+    output D_SCIRDATA6;
+    output D_SCIRDATA7;
+    output D_SCIINT;
+    output D_SCAN_OUT_0;
+    output D_SCAN_OUT_1;
+    output D_SCAN_OUT_2;
+    output D_SCAN_OUT_3;
+    output D_SCAN_OUT_4;
+    output D_SCAN_OUT_5;
+    output D_SCAN_OUT_6;
+    output D_SCAN_OUT_7;
+    output D_COUT0;
+    output D_COUT1;
+    output D_COUT2;
+    output D_COUT3;
+    output D_COUT4;
+    output D_COUT5;
+    output D_COUT6;
+    output D_COUT7;
+    output D_COUT8;
+    output D_COUT9;
+    output D_COUT10;
+    output D_COUT11;
+    output D_COUT12;
+    output D_COUT13;
+    output D_COUT14;
+    output D_COUT15;
+    output D_COUT16;
+    output D_COUT17;
+    output D_COUT18;
+    output D_COUT19;
+    input D_REFCLKI;
+    output D_FFS_PLOL;
+endmodule
+
diff --git a/yosys/techlibs/lattice/cells_bb_xo2.v b/yosys/techlibs/lattice/cells_bb_xo2.v
new file mode 100644
index 00000000000..fdf8331b731
--- /dev/null
+++ b/yosys/techlibs/lattice/cells_bb_xo2.v
@@ -0,0 +1,571 @@
+// Created by cells_xtra.py from Lattice models
+
+(* blackbox *) (* keep *)
+module GSR (...);
+    input GSR;
+endmodule
+
+(* blackbox *) (* keep *)
+module SGSR (...);
+    input GSR;
+    input CLK;
+endmodule
+
+(* blackbox *)
+module DP8KC (...);
+    parameter DATA_WIDTH_A = 9;
+    parameter DATA_WIDTH_B = 9;
+    parameter REGMODE_A = "NOREG";
+    parameter REGMODE_B = "NOREG";
+    parameter CSDECODE_A = "0b000";
+    parameter CSDECODE_B = "0b000";
+    parameter WRITEMODE_A = "NORMAL";
+    parameter WRITEMODE_B = "NORMAL";
+    parameter GSR = "ENABLED";
+    parameter RESETMODE = "SYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter INIT_DATA = "STATIC";
+    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    input DIA8;
+    input DIA7;
+    input DIA6;
+    input DIA5;
+    input DIA4;
+    input DIA3;
+    input DIA2;
+    input DIA1;
+    input DIA0;
+    input ADA12;
+    input ADA11;
+    input ADA10;
+    input ADA9;
+    input ADA8;
+    input ADA7;
+    input ADA6;
+    input ADA5;
+    input ADA4;
+    input ADA3;
+    input ADA2;
+    input ADA1;
+    input ADA0;
+    input CEA;
+    input OCEA;
+    input CLKA;
+    input WEA;
+    input CSA2;
+    input CSA1;
+    input CSA0;
+    input RSTA;
+    input DIB8;
+    input DIB7;
+    input DIB6;
+    input DIB5;
+    input DIB4;
+    input DIB3;
+    input DIB2;
+    input DIB1;
+    input DIB0;
+    input ADB12;
+    input ADB11;
+    input ADB10;
+    input ADB9;
+    input ADB8;
+    input ADB7;
+    input ADB6;
+    input ADB5;
+    input ADB4;
+    input ADB3;
+    input ADB2;
+    input ADB1;
+    input ADB0;
+    input CEB;
+    input OCEB;
+    input CLKB;
+    input WEB;
+    input CSB2;
+    input CSB1;
+    input CSB0;
+    input RSTB;
+    output DOA8;
+    output DOA7;
+    output DOA6;
+    output DOA5;
+    output DOA4;
+    output DOA3;
+    output DOA2;
+    output DOA1;
+    output DOA0;
+    output DOB8;
+    output DOB7;
+    output DOB6;
+    output DOB5;
+    output DOB4;
+    output DOB3;
+    output DOB2;
+    output DOB1;
+    output DOB0;
+endmodule
+
+(* blackbox *)
+module PDPW8KC (...);
+    parameter DATA_WIDTH_W = 18;
+    parameter DATA_WIDTH_R = 9;
+    parameter REGMODE = "NOREG";
+    parameter CSDECODE_W = "0b000";
+    parameter CSDECODE_R = "0b000";
+    parameter GSR = "ENABLED";
+    parameter RESETMODE = "SYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter INIT_DATA = "STATIC";
+    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    input DI17;
+    input DI16;
+    input DI15;
+    input DI14;
+    input DI13;
+    input DI12;
+    input DI11;
+    input DI10;
+    input DI9;
+    input DI8;
+    input DI7;
+    input DI6;
+    input DI5;
+    input DI4;
+    input DI3;
+    input DI2;
+    input DI1;
+    input DI0;
+    input ADW8;
+    input ADW7;
+    input ADW6;
+    input ADW5;
+    input ADW4;
+    input ADW3;
+    input ADW2;
+    input ADW1;
+    input ADW0;
+    input BE1;
+    input BE0;
+    input CEW;
+    input CLKW;
+    input CSW2;
+    input CSW1;
+    input CSW0;
+    input ADR12;
+    input ADR11;
+    input ADR10;
+    input ADR9;
+    input ADR8;
+    input ADR7;
+    input ADR6;
+    input ADR5;
+    input ADR4;
+    input ADR3;
+    input ADR2;
+    input ADR1;
+    input ADR0;
+    input CER;
+    input OCER;
+    input CLKR;
+    input CSR2;
+    input CSR1;
+    input CSR0;
+    input RST;
+    output DO17;
+    output DO16;
+    output DO15;
+    output DO14;
+    output DO13;
+    output DO12;
+    output DO11;
+    output DO10;
+    output DO9;
+    output DO8;
+    output DO7;
+    output DO6;
+    output DO5;
+    output DO4;
+    output DO3;
+    output DO2;
+    output DO1;
+    output DO0;
+endmodule
+
+(* blackbox *)
+module SP8KC (...);
+    parameter DATA_WIDTH = 9;
+    parameter REGMODE = "NOREG";
+    parameter CSDECODE = "0b000";
+    parameter WRITEMODE = "NORMAL";
+    parameter GSR = "ENABLED";
+    parameter RESETMODE = "SYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter INIT_DATA = "STATIC";
+    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    input DI8;
+    input DI7;
+    input DI6;
+    input DI5;
+    input DI4;
+    input DI3;
+    input DI2;
+    input DI1;
+    input DI0;
+    input AD12;
+    input AD11;
+    input AD10;
+    input AD9;
+    input AD8;
+    input AD7;
+    input AD6;
+    input AD5;
+    input AD4;
+    input AD3;
+    input AD2;
+    input AD1;
+    input AD0;
+    input CE;
+    input OCE;
+    input CLK;
+    input WE;
+    input CS2;
+    input CS1;
+    input CS0;
+    input RST;
+    output DO8;
+    output DO7;
+    output DO6;
+    output DO5;
+    output DO4;
+    output DO3;
+    output DO2;
+    output DO1;
+    output DO0;
+endmodule
+
+(* blackbox *)
+module FIFO8KB (...);
+    parameter DATA_WIDTH_W = 18;
+    parameter DATA_WIDTH_R = 18;
+    parameter REGMODE = "NOREG";
+    parameter RESETMODE = "ASYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter CSDECODE_W = "0b00";
+    parameter CSDECODE_R = "0b00";
+    parameter AEPOINTER = "0b00000000000000";
+    parameter AEPOINTER1 = "0b00000000000000";
+    parameter AFPOINTER = "0b00000000000000";
+    parameter AFPOINTER1 = "0b00000000000000";
+    parameter FULLPOINTER = "0b00000000000000";
+    parameter FULLPOINTER1 = "0b00000000000000";
+    parameter GSR = "DISABLED";
+    input DI0;
+    input DI1;
+    input DI2;
+    input DI3;
+    input DI4;
+    input DI5;
+    input DI6;
+    input DI7;
+    input DI8;
+    input DI9;
+    input DI10;
+    input DI11;
+    input DI12;
+    input DI13;
+    input DI14;
+    input DI15;
+    input DI16;
+    input DI17;
+    input CSW0;
+    input CSW1;
+    input CSR0;
+    input CSR1;
+    input WE;
+    input RE;
+    input ORE;
+    input CLKW;
+    input CLKR;
+    input RST;
+    input RPRST;
+    input FULLI;
+    input EMPTYI;
+    output DO0;
+    output DO1;
+    output DO2;
+    output DO3;
+    output DO4;
+    output DO5;
+    output DO6;
+    output DO7;
+    output DO8;
+    output DO9;
+    output DO10;
+    output DO11;
+    output DO12;
+    output DO13;
+    output DO14;
+    output DO15;
+    output DO16;
+    output DO17;
+    output EF;
+    output AEF;
+    output AFF;
+    output FF;
+endmodule
+
+(* blackbox *)
+module CLKDIVC (...);
+    parameter GSR = "DISABLED";
+    parameter DIV = "2.0";
+    input RST;
+    input CLKI;
+    input ALIGNWD;
+    output CDIV1;
+    output CDIVX;
+endmodule
+
+(* blackbox *)
+module DCMA (...);
+    input CLK0;
+    input CLK1;
+    input SEL;
+    output DCMOUT;
+endmodule
+
+(* blackbox *)
+module ECLKSYNCA (...);
+    input ECLKI;
+    input STOP;
+    output ECLKO;
+endmodule
+
+(* blackbox *)
+module ECLKBRIDGECS (...);
+    input CLK0;
+    input CLK1;
+    input SEL;
+    output ECSOUT;
+endmodule
+
+(* blackbox *)
+module DCCA (...);
+    input CLKI;
+    input CE;
+    output CLKO;
+endmodule
+
+(* blackbox *) (* keep *)
+module START (...);
+    input STARTCLK;
+endmodule
+
+(* blackbox *)
+module EHXPLLJ (...);
+    parameter CLKI_DIV = 1;
+    parameter CLKFB_DIV = 1;
+    parameter CLKOP_DIV = 8;
+    parameter CLKOS_DIV = 8;
+    parameter CLKOS2_DIV = 8;
+    parameter CLKOS3_DIV = 8;
+    parameter CLKOP_ENABLE = "ENABLED";
+    parameter CLKOS_ENABLE = "ENABLED";
+    parameter CLKOS2_ENABLE = "ENABLED";
+    parameter CLKOS3_ENABLE = "ENABLED";
+    parameter VCO_BYPASS_A0 = "DISABLED";
+    parameter VCO_BYPASS_B0 = "DISABLED";
+    parameter VCO_BYPASS_C0 = "DISABLED";
+    parameter VCO_BYPASS_D0 = "DISABLED";
+    parameter CLKOP_CPHASE = 0;
+    parameter CLKOS_CPHASE = 0;
+    parameter CLKOS2_CPHASE = 0;
+    parameter CLKOS3_CPHASE = 0;
+    parameter CLKOP_FPHASE = 0;
+    parameter CLKOS_FPHASE = 0;
+    parameter CLKOS2_FPHASE = 0;
+    parameter CLKOS3_FPHASE = 0;
+    parameter FEEDBK_PATH = "CLKOP";
+    parameter FRACN_ENABLE = "DISABLED";
+    parameter FRACN_DIV = 0;
+    parameter CLKOP_TRIM_POL = "RISING";
+    parameter CLKOP_TRIM_DELAY = 0;
+    parameter CLKOS_TRIM_POL = "RISING";
+    parameter CLKOS_TRIM_DELAY = 0;
+    parameter PLL_USE_WB = "DISABLED";
+    parameter PREDIVIDER_MUXA1 = 0;
+    parameter PREDIVIDER_MUXB1 = 0;
+    parameter PREDIVIDER_MUXC1 = 0;
+    parameter PREDIVIDER_MUXD1 = 0;
+    parameter OUTDIVIDER_MUXA2 = "DIVA";
+    parameter OUTDIVIDER_MUXB2 = "DIVB";
+    parameter OUTDIVIDER_MUXC2 = "DIVC";
+    parameter OUTDIVIDER_MUXD2 = "DIVD";
+    parameter PLL_LOCK_MODE = 0;
+    parameter STDBY_ENABLE = "DISABLED";
+    parameter DPHASE_SOURCE = "DISABLED";
+    parameter PLLRST_ENA = "DISABLED";
+    parameter MRST_ENA = "DISABLED";
+    parameter DCRST_ENA = "DISABLED";
+    parameter DDRST_ENA = "DISABLED";
+    parameter INTFB_WAKE = "DISABLED";
+    input CLKI;
+    input CLKFB;
+    input PHASESEL1;
+    input PHASESEL0;
+    input PHASEDIR;
+    input PHASESTEP;
+    input LOADREG;
+    input STDBY;
+    input PLLWAKESYNC;
+    input RST;
+    input RESETM;
+    input RESETC;
+    input RESETD;
+    input ENCLKOP;
+    input ENCLKOS;
+    input ENCLKOS2;
+    input ENCLKOS3;
+    input PLLCLK;
+    input PLLRST;
+    input PLLSTB;
+    input PLLWE;
+    input PLLDATI7;
+    input PLLDATI6;
+    input PLLDATI5;
+    input PLLDATI4;
+    input PLLDATI3;
+    input PLLDATI2;
+    input PLLDATI1;
+    input PLLDATI0;
+    input PLLADDR4;
+    input PLLADDR3;
+    input PLLADDR2;
+    input PLLADDR1;
+    input PLLADDR0;
+    output CLKOP;
+    output CLKOS;
+    output CLKOS2;
+    output CLKOS3;
+    output LOCK;
+    output INTLOCK;
+    output REFCLK;
+    output PLLDATO7;
+    output PLLDATO6;
+    output PLLDATO5;
+    output PLLDATO4;
+    output PLLDATO3;
+    output PLLDATO2;
+    output PLLDATO1;
+    output PLLDATO0;
+    output PLLACK;
+    output DPHSRC;
+    output CLKINTFB;
+endmodule
+
+(* blackbox *)
+module OSCH (...);
+    parameter NOM_FREQ = "2.08";
+    input STDBY;
+    output OSC;
+    output SEDSTDBY;
+endmodule
+
+(* blackbox *) (* keep *)
+module TSALL (...);
+    input TSALL;
+endmodule
+
diff --git a/yosys/techlibs/lattice/cells_bb_xo3.v b/yosys/techlibs/lattice/cells_bb_xo3.v
new file mode 100644
index 00000000000..fdf8331b731
--- /dev/null
+++ b/yosys/techlibs/lattice/cells_bb_xo3.v
@@ -0,0 +1,571 @@
+// Created by cells_xtra.py from Lattice models
+
+(* blackbox *) (* keep *)
+module GSR (...);
+    input GSR;
+endmodule
+
+(* blackbox *) (* keep *)
+module SGSR (...);
+    input GSR;
+    input CLK;
+endmodule
+
+(* blackbox *)
+module DP8KC (...);
+    parameter DATA_WIDTH_A = 9;
+    parameter DATA_WIDTH_B = 9;
+    parameter REGMODE_A = "NOREG";
+    parameter REGMODE_B = "NOREG";
+    parameter CSDECODE_A = "0b000";
+    parameter CSDECODE_B = "0b000";
+    parameter WRITEMODE_A = "NORMAL";
+    parameter WRITEMODE_B = "NORMAL";
+    parameter GSR = "ENABLED";
+    parameter RESETMODE = "SYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter INIT_DATA = "STATIC";
+    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    input DIA8;
+    input DIA7;
+    input DIA6;
+    input DIA5;
+    input DIA4;
+    input DIA3;
+    input DIA2;
+    input DIA1;
+    input DIA0;
+    input ADA12;
+    input ADA11;
+    input ADA10;
+    input ADA9;
+    input ADA8;
+    input ADA7;
+    input ADA6;
+    input ADA5;
+    input ADA4;
+    input ADA3;
+    input ADA2;
+    input ADA1;
+    input ADA0;
+    input CEA;
+    input OCEA;
+    input CLKA;
+    input WEA;
+    input CSA2;
+    input CSA1;
+    input CSA0;
+    input RSTA;
+    input DIB8;
+    input DIB7;
+    input DIB6;
+    input DIB5;
+    input DIB4;
+    input DIB3;
+    input DIB2;
+    input DIB1;
+    input DIB0;
+    input ADB12;
+    input ADB11;
+    input ADB10;
+    input ADB9;
+    input ADB8;
+    input ADB7;
+    input ADB6;
+    input ADB5;
+    input ADB4;
+    input ADB3;
+    input ADB2;
+    input ADB1;
+    input ADB0;
+    input CEB;
+    input OCEB;
+    input CLKB;
+    input WEB;
+    input CSB2;
+    input CSB1;
+    input CSB0;
+    input RSTB;
+    output DOA8;
+    output DOA7;
+    output DOA6;
+    output DOA5;
+    output DOA4;
+    output DOA3;
+    output DOA2;
+    output DOA1;
+    output DOA0;
+    output DOB8;
+    output DOB7;
+    output DOB6;
+    output DOB5;
+    output DOB4;
+    output DOB3;
+    output DOB2;
+    output DOB1;
+    output DOB0;
+endmodule
+
+(* blackbox *)
+module PDPW8KC (...);
+    parameter DATA_WIDTH_W = 18;
+    parameter DATA_WIDTH_R = 9;
+    parameter REGMODE = "NOREG";
+    parameter CSDECODE_W = "0b000";
+    parameter CSDECODE_R = "0b000";
+    parameter GSR = "ENABLED";
+    parameter RESETMODE = "SYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter INIT_DATA = "STATIC";
+    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    input DI17;
+    input DI16;
+    input DI15;
+    input DI14;
+    input DI13;
+    input DI12;
+    input DI11;
+    input DI10;
+    input DI9;
+    input DI8;
+    input DI7;
+    input DI6;
+    input DI5;
+    input DI4;
+    input DI3;
+    input DI2;
+    input DI1;
+    input DI0;
+    input ADW8;
+    input ADW7;
+    input ADW6;
+    input ADW5;
+    input ADW4;
+    input ADW3;
+    input ADW2;
+    input ADW1;
+    input ADW0;
+    input BE1;
+    input BE0;
+    input CEW;
+    input CLKW;
+    input CSW2;
+    input CSW1;
+    input CSW0;
+    input ADR12;
+    input ADR11;
+    input ADR10;
+    input ADR9;
+    input ADR8;
+    input ADR7;
+    input ADR6;
+    input ADR5;
+    input ADR4;
+    input ADR3;
+    input ADR2;
+    input ADR1;
+    input ADR0;
+    input CER;
+    input OCER;
+    input CLKR;
+    input CSR2;
+    input CSR1;
+    input CSR0;
+    input RST;
+    output DO17;
+    output DO16;
+    output DO15;
+    output DO14;
+    output DO13;
+    output DO12;
+    output DO11;
+    output DO10;
+    output DO9;
+    output DO8;
+    output DO7;
+    output DO6;
+    output DO5;
+    output DO4;
+    output DO3;
+    output DO2;
+    output DO1;
+    output DO0;
+endmodule
+
+(* blackbox *)
+module SP8KC (...);
+    parameter DATA_WIDTH = 9;
+    parameter REGMODE = "NOREG";
+    parameter CSDECODE = "0b000";
+    parameter WRITEMODE = "NORMAL";
+    parameter GSR = "ENABLED";
+    parameter RESETMODE = "SYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter INIT_DATA = "STATIC";
+    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    input DI8;
+    input DI7;
+    input DI6;
+    input DI5;
+    input DI4;
+    input DI3;
+    input DI2;
+    input DI1;
+    input DI0;
+    input AD12;
+    input AD11;
+    input AD10;
+    input AD9;
+    input AD8;
+    input AD7;
+    input AD6;
+    input AD5;
+    input AD4;
+    input AD3;
+    input AD2;
+    input AD1;
+    input AD0;
+    input CE;
+    input OCE;
+    input CLK;
+    input WE;
+    input CS2;
+    input CS1;
+    input CS0;
+    input RST;
+    output DO8;
+    output DO7;
+    output DO6;
+    output DO5;
+    output DO4;
+    output DO3;
+    output DO2;
+    output DO1;
+    output DO0;
+endmodule
+
+(* blackbox *)
+module FIFO8KB (...);
+    parameter DATA_WIDTH_W = 18;
+    parameter DATA_WIDTH_R = 18;
+    parameter REGMODE = "NOREG";
+    parameter RESETMODE = "ASYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter CSDECODE_W = "0b00";
+    parameter CSDECODE_R = "0b00";
+    parameter AEPOINTER = "0b00000000000000";
+    parameter AEPOINTER1 = "0b00000000000000";
+    parameter AFPOINTER = "0b00000000000000";
+    parameter AFPOINTER1 = "0b00000000000000";
+    parameter FULLPOINTER = "0b00000000000000";
+    parameter FULLPOINTER1 = "0b00000000000000";
+    parameter GSR = "DISABLED";
+    input DI0;
+    input DI1;
+    input DI2;
+    input DI3;
+    input DI4;
+    input DI5;
+    input DI6;
+    input DI7;
+    input DI8;
+    input DI9;
+    input DI10;
+    input DI11;
+    input DI12;
+    input DI13;
+    input DI14;
+    input DI15;
+    input DI16;
+    input DI17;
+    input CSW0;
+    input CSW1;
+    input CSR0;
+    input CSR1;
+    input WE;
+    input RE;
+    input ORE;
+    input CLKW;
+    input CLKR;
+    input RST;
+    input RPRST;
+    input FULLI;
+    input EMPTYI;
+    output DO0;
+    output DO1;
+    output DO2;
+    output DO3;
+    output DO4;
+    output DO5;
+    output DO6;
+    output DO7;
+    output DO8;
+    output DO9;
+    output DO10;
+    output DO11;
+    output DO12;
+    output DO13;
+    output DO14;
+    output DO15;
+    output DO16;
+    output DO17;
+    output EF;
+    output AEF;
+    output AFF;
+    output FF;
+endmodule
+
+(* blackbox *)
+module CLKDIVC (...);
+    parameter GSR = "DISABLED";
+    parameter DIV = "2.0";
+    input RST;
+    input CLKI;
+    input ALIGNWD;
+    output CDIV1;
+    output CDIVX;
+endmodule
+
+(* blackbox *)
+module DCMA (...);
+    input CLK0;
+    input CLK1;
+    input SEL;
+    output DCMOUT;
+endmodule
+
+(* blackbox *)
+module ECLKSYNCA (...);
+    input ECLKI;
+    input STOP;
+    output ECLKO;
+endmodule
+
+(* blackbox *)
+module ECLKBRIDGECS (...);
+    input CLK0;
+    input CLK1;
+    input SEL;
+    output ECSOUT;
+endmodule
+
+(* blackbox *)
+module DCCA (...);
+    input CLKI;
+    input CE;
+    output CLKO;
+endmodule
+
+(* blackbox *) (* keep *)
+module START (...);
+    input STARTCLK;
+endmodule
+
+(* blackbox *)
+module EHXPLLJ (...);
+    parameter CLKI_DIV = 1;
+    parameter CLKFB_DIV = 1;
+    parameter CLKOP_DIV = 8;
+    parameter CLKOS_DIV = 8;
+    parameter CLKOS2_DIV = 8;
+    parameter CLKOS3_DIV = 8;
+    parameter CLKOP_ENABLE = "ENABLED";
+    parameter CLKOS_ENABLE = "ENABLED";
+    parameter CLKOS2_ENABLE = "ENABLED";
+    parameter CLKOS3_ENABLE = "ENABLED";
+    parameter VCO_BYPASS_A0 = "DISABLED";
+    parameter VCO_BYPASS_B0 = "DISABLED";
+    parameter VCO_BYPASS_C0 = "DISABLED";
+    parameter VCO_BYPASS_D0 = "DISABLED";
+    parameter CLKOP_CPHASE = 0;
+    parameter CLKOS_CPHASE = 0;
+    parameter CLKOS2_CPHASE = 0;
+    parameter CLKOS3_CPHASE = 0;
+    parameter CLKOP_FPHASE = 0;
+    parameter CLKOS_FPHASE = 0;
+    parameter CLKOS2_FPHASE = 0;
+    parameter CLKOS3_FPHASE = 0;
+    parameter FEEDBK_PATH = "CLKOP";
+    parameter FRACN_ENABLE = "DISABLED";
+    parameter FRACN_DIV = 0;
+    parameter CLKOP_TRIM_POL = "RISING";
+    parameter CLKOP_TRIM_DELAY = 0;
+    parameter CLKOS_TRIM_POL = "RISING";
+    parameter CLKOS_TRIM_DELAY = 0;
+    parameter PLL_USE_WB = "DISABLED";
+    parameter PREDIVIDER_MUXA1 = 0;
+    parameter PREDIVIDER_MUXB1 = 0;
+    parameter PREDIVIDER_MUXC1 = 0;
+    parameter PREDIVIDER_MUXD1 = 0;
+    parameter OUTDIVIDER_MUXA2 = "DIVA";
+    parameter OUTDIVIDER_MUXB2 = "DIVB";
+    parameter OUTDIVIDER_MUXC2 = "DIVC";
+    parameter OUTDIVIDER_MUXD2 = "DIVD";
+    parameter PLL_LOCK_MODE = 0;
+    parameter STDBY_ENABLE = "DISABLED";
+    parameter DPHASE_SOURCE = "DISABLED";
+    parameter PLLRST_ENA = "DISABLED";
+    parameter MRST_ENA = "DISABLED";
+    parameter DCRST_ENA = "DISABLED";
+    parameter DDRST_ENA = "DISABLED";
+    parameter INTFB_WAKE = "DISABLED";
+    input CLKI;
+    input CLKFB;
+    input PHASESEL1;
+    input PHASESEL0;
+    input PHASEDIR;
+    input PHASESTEP;
+    input LOADREG;
+    input STDBY;
+    input PLLWAKESYNC;
+    input RST;
+    input RESETM;
+    input RESETC;
+    input RESETD;
+    input ENCLKOP;
+    input ENCLKOS;
+    input ENCLKOS2;
+    input ENCLKOS3;
+    input PLLCLK;
+    input PLLRST;
+    input PLLSTB;
+    input PLLWE;
+    input PLLDATI7;
+    input PLLDATI6;
+    input PLLDATI5;
+    input PLLDATI4;
+    input PLLDATI3;
+    input PLLDATI2;
+    input PLLDATI1;
+    input PLLDATI0;
+    input PLLADDR4;
+    input PLLADDR3;
+    input PLLADDR2;
+    input PLLADDR1;
+    input PLLADDR0;
+    output CLKOP;
+    output CLKOS;
+    output CLKOS2;
+    output CLKOS3;
+    output LOCK;
+    output INTLOCK;
+    output REFCLK;
+    output PLLDATO7;
+    output PLLDATO6;
+    output PLLDATO5;
+    output PLLDATO4;
+    output PLLDATO3;
+    output PLLDATO2;
+    output PLLDATO1;
+    output PLLDATO0;
+    output PLLACK;
+    output DPHSRC;
+    output CLKINTFB;
+endmodule
+
+(* blackbox *)
+module OSCH (...);
+    parameter NOM_FREQ = "2.08";
+    input STDBY;
+    output OSC;
+    output SEDSTDBY;
+endmodule
+
+(* blackbox *) (* keep *)
+module TSALL (...);
+    input TSALL;
+endmodule
+
diff --git a/yosys/techlibs/lattice/cells_bb_xo3d.v b/yosys/techlibs/lattice/cells_bb_xo3d.v
new file mode 100644
index 00000000000..84d7d960198
--- /dev/null
+++ b/yosys/techlibs/lattice/cells_bb_xo3d.v
@@ -0,0 +1,572 @@
+// Created by cells_xtra.py from Lattice models
+
+(* blackbox *) (* keep *)
+module GSR (...);
+    input GSR;
+endmodule
+
+(* blackbox *) (* keep *)
+module SGSR (...);
+    input GSR;
+    input CLK;
+endmodule
+
+(* blackbox *)
+module DP8KC (...);
+    parameter DATA_WIDTH_A = 9;
+    parameter DATA_WIDTH_B = 9;
+    parameter REGMODE_A = "NOREG";
+    parameter REGMODE_B = "NOREG";
+    parameter CSDECODE_A = "0b000";
+    parameter CSDECODE_B = "0b000";
+    parameter WRITEMODE_A = "NORMAL";
+    parameter WRITEMODE_B = "NORMAL";
+    parameter GSR = "ENABLED";
+    parameter RESETMODE = "SYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter INIT_DATA = "STATIC";
+    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    input DIA8;
+    input DIA7;
+    input DIA6;
+    input DIA5;
+    input DIA4;
+    input DIA3;
+    input DIA2;
+    input DIA1;
+    input DIA0;
+    input ADA12;
+    input ADA11;
+    input ADA10;
+    input ADA9;
+    input ADA8;
+    input ADA7;
+    input ADA6;
+    input ADA5;
+    input ADA4;
+    input ADA3;
+    input ADA2;
+    input ADA1;
+    input ADA0;
+    input CEA;
+    input OCEA;
+    input CLKA;
+    input WEA;
+    input CSA2;
+    input CSA1;
+    input CSA0;
+    input RSTA;
+    input DIB8;
+    input DIB7;
+    input DIB6;
+    input DIB5;
+    input DIB4;
+    input DIB3;
+    input DIB2;
+    input DIB1;
+    input DIB0;
+    input ADB12;
+    input ADB11;
+    input ADB10;
+    input ADB9;
+    input ADB8;
+    input ADB7;
+    input ADB6;
+    input ADB5;
+    input ADB4;
+    input ADB3;
+    input ADB2;
+    input ADB1;
+    input ADB0;
+    input CEB;
+    input OCEB;
+    input CLKB;
+    input WEB;
+    input CSB2;
+    input CSB1;
+    input CSB0;
+    input RSTB;
+    output DOA8;
+    output DOA7;
+    output DOA6;
+    output DOA5;
+    output DOA4;
+    output DOA3;
+    output DOA2;
+    output DOA1;
+    output DOA0;
+    output DOB8;
+    output DOB7;
+    output DOB6;
+    output DOB5;
+    output DOB4;
+    output DOB3;
+    output DOB2;
+    output DOB1;
+    output DOB0;
+endmodule
+
+(* blackbox *)
+module PDPW8KC (...);
+    parameter DATA_WIDTH_W = 18;
+    parameter DATA_WIDTH_R = 9;
+    parameter REGMODE = "NOREG";
+    parameter CSDECODE_W = "0b000";
+    parameter CSDECODE_R = "0b000";
+    parameter GSR = "ENABLED";
+    parameter RESETMODE = "SYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter INIT_DATA = "STATIC";
+    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    input DI17;
+    input DI16;
+    input DI15;
+    input DI14;
+    input DI13;
+    input DI12;
+    input DI11;
+    input DI10;
+    input DI9;
+    input DI8;
+    input DI7;
+    input DI6;
+    input DI5;
+    input DI4;
+    input DI3;
+    input DI2;
+    input DI1;
+    input DI0;
+    input ADW8;
+    input ADW7;
+    input ADW6;
+    input ADW5;
+    input ADW4;
+    input ADW3;
+    input ADW2;
+    input ADW1;
+    input ADW0;
+    input BE1;
+    input BE0;
+    input CEW;
+    input CLKW;
+    input CSW2;
+    input CSW1;
+    input CSW0;
+    input ADR12;
+    input ADR11;
+    input ADR10;
+    input ADR9;
+    input ADR8;
+    input ADR7;
+    input ADR6;
+    input ADR5;
+    input ADR4;
+    input ADR3;
+    input ADR2;
+    input ADR1;
+    input ADR0;
+    input CER;
+    input OCER;
+    input CLKR;
+    input CSR2;
+    input CSR1;
+    input CSR0;
+    input RST;
+    output DO17;
+    output DO16;
+    output DO15;
+    output DO14;
+    output DO13;
+    output DO12;
+    output DO11;
+    output DO10;
+    output DO9;
+    output DO8;
+    output DO7;
+    output DO6;
+    output DO5;
+    output DO4;
+    output DO3;
+    output DO2;
+    output DO1;
+    output DO0;
+endmodule
+
+(* blackbox *)
+module SP8KC (...);
+    parameter DATA_WIDTH = 9;
+    parameter REGMODE = "NOREG";
+    parameter CSDECODE = "0b000";
+    parameter WRITEMODE = "NORMAL";
+    parameter GSR = "ENABLED";
+    parameter RESETMODE = "SYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter INIT_DATA = "STATIC";
+    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+    input DI8;
+    input DI7;
+    input DI6;
+    input DI5;
+    input DI4;
+    input DI3;
+    input DI2;
+    input DI1;
+    input DI0;
+    input AD12;
+    input AD11;
+    input AD10;
+    input AD9;
+    input AD8;
+    input AD7;
+    input AD6;
+    input AD5;
+    input AD4;
+    input AD3;
+    input AD2;
+    input AD1;
+    input AD0;
+    input CE;
+    input OCE;
+    input CLK;
+    input WE;
+    input CS2;
+    input CS1;
+    input CS0;
+    input RST;
+    output DO8;
+    output DO7;
+    output DO6;
+    output DO5;
+    output DO4;
+    output DO3;
+    output DO2;
+    output DO1;
+    output DO0;
+endmodule
+
+(* blackbox *)
+module FIFO8KB (...);
+    parameter DATA_WIDTH_W = 18;
+    parameter DATA_WIDTH_R = 18;
+    parameter REGMODE = "NOREG";
+    parameter RESETMODE = "ASYNC";
+    parameter ASYNC_RESET_RELEASE = "SYNC";
+    parameter CSDECODE_W = "0b00";
+    parameter CSDECODE_R = "0b00";
+    parameter AEPOINTER = "0b00000000000000";
+    parameter AEPOINTER1 = "0b00000000000000";
+    parameter AFPOINTER = "0b00000000000000";
+    parameter AFPOINTER1 = "0b00000000000000";
+    parameter FULLPOINTER = "0b00000000000000";
+    parameter FULLPOINTER1 = "0b00000000000000";
+    parameter GSR = "DISABLED";
+    input DI0;
+    input DI1;
+    input DI2;
+    input DI3;
+    input DI4;
+    input DI5;
+    input DI6;
+    input DI7;
+    input DI8;
+    input DI9;
+    input DI10;
+    input DI11;
+    input DI12;
+    input DI13;
+    input DI14;
+    input DI15;
+    input DI16;
+    input DI17;
+    input CSW0;
+    input CSW1;
+    input CSR0;
+    input CSR1;
+    input WE;
+    input RE;
+    input ORE;
+    input CLKW;
+    input CLKR;
+    input RST;
+    input RPRST;
+    input FULLI;
+    input EMPTYI;
+    output DO0;
+    output DO1;
+    output DO2;
+    output DO3;
+    output DO4;
+    output DO5;
+    output DO6;
+    output DO7;
+    output DO8;
+    output DO9;
+    output DO10;
+    output DO11;
+    output DO12;
+    output DO13;
+    output DO14;
+    output DO15;
+    output DO16;
+    output DO17;
+    output EF;
+    output AEF;
+    output AFF;
+    output FF;
+endmodule
+
+(* blackbox *)
+module CLKDIVC (...);
+    parameter GSR = "DISABLED";
+    parameter DIV = "2.0";
+    input RST;
+    input CLKI;
+    input ALIGNWD;
+    output CDIV1;
+    output CDIVX;
+endmodule
+
+(* blackbox *)
+module DCMA (...);
+    input CLK0;
+    input CLK1;
+    input SEL;
+    output DCMOUT;
+endmodule
+
+(* blackbox *)
+module ECLKSYNCA (...);
+    input ECLKI;
+    input STOP;
+    output ECLKO;
+endmodule
+
+(* blackbox *)
+module ECLKBRIDGECS (...);
+    input CLK0;
+    input CLK1;
+    input SEL;
+    output ECSOUT;
+endmodule
+
+(* blackbox *)
+module DCCA (...);
+    input CLKI;
+    input CE;
+    output CLKO;
+endmodule
+
+(* blackbox *) (* keep *)
+module START (...);
+    input STARTCLK;
+endmodule
+
+(* blackbox *)
+module EHXPLLJ (...);
+    parameter CLKI_DIV = 1;
+    parameter CLKFB_DIV = 1;
+    parameter CLKOP_DIV = 8;
+    parameter CLKOS_DIV = 8;
+    parameter CLKOS2_DIV = 8;
+    parameter CLKOS3_DIV = 8;
+    parameter CLKOP_ENABLE = "ENABLED";
+    parameter CLKOS_ENABLE = "ENABLED";
+    parameter CLKOS2_ENABLE = "ENABLED";
+    parameter CLKOS3_ENABLE = "ENABLED";
+    parameter VCO_BYPASS_A0 = "DISABLED";
+    parameter VCO_BYPASS_B0 = "DISABLED";
+    parameter VCO_BYPASS_C0 = "DISABLED";
+    parameter VCO_BYPASS_D0 = "DISABLED";
+    parameter CLKOP_CPHASE = 0;
+    parameter CLKOS_CPHASE = 0;
+    parameter CLKOS2_CPHASE = 0;
+    parameter CLKOS3_CPHASE = 0;
+    parameter CLKOP_FPHASE = 0;
+    parameter CLKOS_FPHASE = 0;
+    parameter CLKOS2_FPHASE = 0;
+    parameter CLKOS3_FPHASE = 0;
+    parameter FEEDBK_PATH = "CLKOP";
+    parameter FRACN_ENABLE = "DISABLED";
+    parameter FRACN_DIV = 0;
+    parameter CLKOP_TRIM_POL = "RISING";
+    parameter CLKOP_TRIM_DELAY = 0;
+    parameter CLKOS_TRIM_POL = "RISING";
+    parameter CLKOS_TRIM_DELAY = 0;
+    parameter PLL_USE_WB = "DISABLED";
+    parameter PREDIVIDER_MUXA1 = 0;
+    parameter PREDIVIDER_MUXB1 = 0;
+    parameter PREDIVIDER_MUXC1 = 0;
+    parameter PREDIVIDER_MUXD1 = 0;
+    parameter OUTDIVIDER_MUXA2 = "DIVA";
+    parameter OUTDIVIDER_MUXB2 = "DIVB";
+    parameter OUTDIVIDER_MUXC2 = "DIVC";
+    parameter OUTDIVIDER_MUXD2 = "DIVD";
+    parameter PLL_LOCK_MODE = 0;
+    parameter STDBY_ENABLE = "DISABLED";
+    parameter DPHASE_SOURCE = "DISABLED";
+    parameter PLLRST_ENA = "DISABLED";
+    parameter MRST_ENA = "DISABLED";
+    parameter DCRST_ENA = "DISABLED";
+    parameter DDRST_ENA = "DISABLED";
+    parameter INTFB_WAKE = "DISABLED";
+    input CLKI;
+    input CLKFB;
+    input PHASESEL1;
+    input PHASESEL0;
+    input PHASEDIR;
+    input PHASESTEP;
+    input LOADREG;
+    input STDBY;
+    input PLLWAKESYNC;
+    input RST;
+    input RESETM;
+    input RESETC;
+    input RESETD;
+    input ENCLKOP;
+    input ENCLKOS;
+    input ENCLKOS2;
+    input ENCLKOS3;
+    input PLLCLK;
+    input PLLRST;
+    input PLLSTB;
+    input PLLWE;
+    input PLLDATI7;
+    input PLLDATI6;
+    input PLLDATI5;
+    input PLLDATI4;
+    input PLLDATI3;
+    input PLLDATI2;
+    input PLLDATI1;
+    input PLLDATI0;
+    input PLLADDR4;
+    input PLLADDR3;
+    input PLLADDR2;
+    input PLLADDR1;
+    input PLLADDR0;
+    output CLKOP;
+    output CLKOS;
+    output CLKOS2;
+    output CLKOS3;
+    output LOCK;
+    output INTLOCK;
+    output REFCLK;
+    output PLLDATO7;
+    output PLLDATO6;
+    output PLLDATO5;
+    output PLLDATO4;
+    output PLLDATO3;
+    output PLLDATO2;
+    output PLLDATO1;
+    output PLLDATO0;
+    output PLLACK;
+    output DPHSRC;
+    output CLKINTFB;
+endmodule
+
+(* blackbox *)
+module OSCJ (...);
+    parameter NOM_FREQ = "2.08";
+    input STDBY;
+    output OSC;
+    output SEDSTDBY;
+    output OSCESB;
+endmodule
+
+(* blackbox *) (* keep *)
+module TSALL (...);
+    input TSALL;
+endmodule
+
diff --git a/yosys/techlibs/lattice/cells_ff.vh b/yosys/techlibs/lattice/cells_ff.vh
new file mode 100644
index 00000000000..6b745f391ee
--- /dev/null
+++ b/yosys/techlibs/lattice/cells_ff.vh
@@ -0,0 +1,40 @@
+// Diamond flip-flops
+module FD1P3AX(input     D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3AY(input     D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1S3AX(input     D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0),          .DI(D), .Q(Q)); endmodule
+module FD1S3AY(input     D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0),          .DI(D), .Q(Q)); endmodule
+module FD1S3BX(input PD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
+module FD1S3DX(input CD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
+module FD1S3IX(input CD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
+module FD1S3JX(input PD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
+
+// TODO: Diamond latches
+// module FL1P3AY(); endmodule
+// module FL1P3AZ(); endmodule
+// module FL1P3BX(); endmodule
+// module FL1P3DX(); endmodule
+// module FL1P3IY(); endmodule
+// module FL1P3JY(); endmodule
+// module FL1S3AX(); endmodule
+// module FL1S3AY(); endmodule
+
+// Diamond I/O registers
+module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+
+module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+
+// TODO: Diamond I/O latches
+// module IFS1S1B(input PD, D, SCLK, output Q); endmodule
+// module IFS1S1D(input CD, D, SCLK, output Q); endmodule
+// module IFS1S1I(input PD, D, SCLK, output Q); endmodule
+// module IFS1S1J(input CD, D, SCLK, output Q); endmodule
diff --git a/yosys/techlibs/lattice/cells_io.vh b/yosys/techlibs/lattice/cells_io.vh
new file mode 100644
index 00000000000..220460c4467
--- /dev/null
+++ b/yosys/techlibs/lattice/cells_io.vh
@@ -0,0 +1,14 @@
+// Diamond I/O buffers
+module IB   ((* iopad_external_pin *) input I,     output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPU ((* iopad_external_pin *) input I,     output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPD ((* iopad_external_pin *) input I,     output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module OB   (input I,     (* iopad_external_pin *) output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
+module OBZ  (input I, T,  (* iopad_external_pin *) output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPU(input I, T,  (* iopad_external_pin *) output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPD(input I, T,  (* iopad_external_pin *) output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBCO (input I,     output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
+module BB   (input I, T,  output O, (* iopad_external_pin *) inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPU (input I, T,  output O, (* iopad_external_pin *) inout B); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPD (input I, T,  output O, (* iopad_external_pin *) inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module ILVDS(input A, AN, (* iopad_external_pin *) output Z    ); TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
+module OLVDS(input A,     (* iopad_external_pin *) output Z, output ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
diff --git a/yosys/techlibs/machxo2/cells_map.v b/yosys/techlibs/lattice/cells_map.v
similarity index 64%
rename from yosys/techlibs/machxo2/cells_map.v
rename to yosys/techlibs/lattice/cells_map.v
index 22994a634df..4944ece4569 100644
--- a/yosys/techlibs/machxo2/cells_map.v
+++ b/yosys/techlibs/lattice/cells_map.v
@@ -88,30 +88,104 @@ module  \$_SDFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"),
 module  \$_SDFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
 module  \$_SDFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
 
-module \$lut (A, Y);
-	parameter WIDTH = 0;
-	parameter LUT = 0;
-	input [WIDTH-1:0] A;
-	output Y;
-
-	localparam rep = 1<<(4-WIDTH);
-	wire [3:0] I;
-
-	generate
-		if(WIDTH == 1) begin
-			assign I = {1'b0, 1'b0, 1'b0, A[0]};
-		end else if(WIDTH == 2) begin
-			assign I = {1'b0, 1'b0, A[1], A[0]};
-		end else if(WIDTH == 3) begin
-			assign I = {1'b0, A[2], A[1], A[0]};
-		end else if(WIDTH == 4) begin
-			assign I = {A[3], A[2], A[1], A[0]};
-		end else begin
-			wire _TECHMAP_FAIL_ = 1;
-		end
-	endgenerate
-
-	LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .Z(Y));
-endmodule
+module \$_ALDFF_NP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
+module \$_ALDFF_PP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
 
+module \$_ALDFFE_NPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
+module \$_ALDFFE_NPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
+module \$_ALDFFE_PPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
+module \$_ALDFFE_PPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule
+
+`include "cells_ff.vh"
 `include "cells_io.vh"
+
+`ifndef NO_LUT
+module \$lut (A, Y);
+    parameter WIDTH = 0;
+    parameter LUT = 0;
+
+    (* force_downto *)
+    input [WIDTH-1:0] A;
+    output Y;
+
+    generate
+        if (WIDTH == 1) begin
+            localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
+            LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(1'b0), .B(1'b0), .C(1'b0), .D(A[0]));
+        end else
+        if (WIDTH == 2) begin
+            localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};
+            LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(1'b0), .B(1'b0), .C(A[0]), .D(A[1]));
+        end else
+        if (WIDTH == 3) begin
+            localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};
+            LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(1'b0), .B(A[0]), .C(A[1]), .D(A[2]));
+        end else
+        if (WIDTH == 4) begin
+            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+        `ifndef NO_PFUMUX
+        end else
+        if (WIDTH == 5) begin
+            wire f0, f1;
+            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y));
+        end else
+        if (WIDTH == 6) begin
+            wire f0, f1, f2, f3, g0, g1;
+            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
+            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
+            L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));
+        end else
+        if (WIDTH == 7) begin
+            wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1;
+            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
+            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
+            PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2));
+            PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3));
+            L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));
+            L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));
+            L6MUX21 mux7  (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));
+        `endif
+        end else begin
+            wire _TECHMAP_FAIL_ = 1;
+        end
+    endgenerate
+endmodule
+`endif
diff --git a/yosys/techlibs/lattice/cells_sim_ecp5.v b/yosys/techlibs/lattice/cells_sim_ecp5.v
new file mode 100644
index 00000000000..9439e3a5b31
--- /dev/null
+++ b/yosys/techlibs/lattice/cells_sim_ecp5.v
@@ -0,0 +1,9 @@
+`include "common_sim.vh"
+`include "ccu2c_sim.vh"
+
+`ifndef NO_INCLUDES
+
+`include "cells_ff.vh"
+`include "cells_io.vh"
+
+`endif
diff --git a/yosys/techlibs/lattice/cells_sim_xo2.v b/yosys/techlibs/lattice/cells_sim_xo2.v
new file mode 100644
index 00000000000..54414287572
--- /dev/null
+++ b/yosys/techlibs/lattice/cells_sim_xo2.v
@@ -0,0 +1,9 @@
+`include "common_sim.vh"
+`include "ccu2d_sim.vh"
+
+`ifndef NO_INCLUDES
+
+`include "cells_ff.vh"
+`include "cells_io.vh"
+
+`endif
diff --git a/yosys/techlibs/lattice/cells_sim_xo3.v b/yosys/techlibs/lattice/cells_sim_xo3.v
new file mode 100644
index 00000000000..54414287572
--- /dev/null
+++ b/yosys/techlibs/lattice/cells_sim_xo3.v
@@ -0,0 +1,9 @@
+`include "common_sim.vh"
+`include "ccu2d_sim.vh"
+
+`ifndef NO_INCLUDES
+
+`include "cells_ff.vh"
+`include "cells_io.vh"
+
+`endif
diff --git a/yosys/techlibs/lattice/cells_sim_xo3d.v b/yosys/techlibs/lattice/cells_sim_xo3d.v
new file mode 100644
index 00000000000..54414287572
--- /dev/null
+++ b/yosys/techlibs/lattice/cells_sim_xo3d.v
@@ -0,0 +1,9 @@
+`include "common_sim.vh"
+`include "ccu2d_sim.vh"
+
+`ifndef NO_INCLUDES
+
+`include "cells_ff.vh"
+`include "cells_io.vh"
+
+`endif
diff --git a/yosys/techlibs/lattice/cells_xtra.py b/yosys/techlibs/lattice/cells_xtra.py
new file mode 100644
index 00000000000..c17281cc753
--- /dev/null
+++ b/yosys/techlibs/lattice/cells_xtra.py
@@ -0,0 +1,856 @@
+#!/usr/bin/env python3
+
+# Based on Xilinx cells_xtra.py; modified for Lattice's structure
+
+from argparse import ArgumentParser
+from io import StringIO
+from enum import Enum, auto
+import os.path
+import sys
+import re
+
+
+class Cell:
+    def __init__(self, name, keep=False, port_attrs={}):
+        self.name = name
+        self.keep = keep
+        self.port_attrs = port_attrs
+        self.found = False
+
+class State(Enum):
+    OUTSIDE = auto()
+    IN_MODULE = auto()
+    IN_OTHER_MODULE = auto()
+    IN_FUNCTION = auto()
+    IN_TASK = auto()
+
+devices = [
+    ("cells_bb_ecp5.v", "ecp5u", [
+        #Cell("AND2"),
+        #Cell("AND3"),
+        #Cell("AND4"),
+        #Cell("AND5"),
+        #Cell("BB"),
+        #Cell("BBPD"),
+        #Cell("BBPU"),
+        #Cell("CCU2C"),
+        #Cell("FD1P3AX"),
+        #Cell("FD1P3AY"),
+        #Cell("FD1P3BX"),
+        #Cell("FD1P3DX"),
+        #Cell("FD1P3IX"),
+        #Cell("FD1P3JX"),
+        #Cell("FD1S3AX"),
+        #Cell("FD1S3AY"),
+        #Cell("FD1S3BX"),
+        #Cell("FD1S3DX"),
+        #Cell("FD1S3IX"),
+        #Cell("FD1S3JX"),
+        #Cell("FL1P3AY"),
+        #Cell("FL1P3AZ"),
+        #Cell("FL1P3BX"),
+        #Cell("FL1P3DX"),
+        #Cell("FL1P3IY"),
+        #Cell("FL1P3JY"),
+        #Cell("FL1S3AX"),
+        #Cell("FL1S3AY"),
+        Cell("GSR", True),
+        #Cell("IB"),
+        #Cell("IBPD"),
+        #Cell("IBPU"),
+        #Cell("IFS1P3BX"),
+        #Cell("IFS1P3DX"),
+        #Cell("IFS1P3IX"),
+        #Cell("IFS1P3JX"),
+        #Cell("IFS1S1B"),
+        #Cell("IFS1S1D"),
+        #Cell("IFS1S1I"),
+        #Cell("IFS1S1J"),
+        #Cell("ILVDS"),
+        #Cell("INV"),
+        #Cell("L6MUX21"),
+        #Cell("LUT4"),
+        #Cell("LUT5"),
+        #Cell("LUT6"),
+        #Cell("LUT7"),
+        #Cell("LUT8"),
+        #Cell("MUX161"),
+        #Cell("MUX21"),
+        #Cell("MUX321"),
+        #Cell("MUX41"),
+        #Cell("MUX81"),
+        #Cell("ND2"),
+        #Cell("ND3"),
+        #Cell("ND4"),
+        #Cell("ND5"),
+        #Cell("NR2"),
+        #Cell("NR3"),
+        #Cell("NR4"),
+        #Cell("NR5"),
+        #Cell("OB"),
+        #Cell("OBCO"),
+        #Cell("OBZ"),
+        #Cell("OBZPU"),
+        #Cell("OFS1P3BX"),
+        #Cell("OFS1P3DX"),
+        #Cell("OFS1P3IX"),
+        #Cell("OFS1P3JX"),
+        #Cell("OLVDS"),
+        #Cell("OR2"),
+        #Cell("OR3"),
+        #Cell("OR4"),
+        #Cell("OR5"),
+        #Cell("PFUMX"),
+        Cell("PUR"),
+        #Cell("ROM128X1A"),
+        #Cell("ROM16X1A"),
+        #Cell("ROM256X1A"),
+        #Cell("ROM32X1A"),
+        #Cell("ROM64X1A"),
+        Cell("SGSR", True),
+        #Cell("VHI"),
+        #Cell("VLO"),
+        #Cell("XNOR2"),
+        #Cell("XNOR3"),
+        #Cell("XNOR4"),
+        #Cell("XNOR5"),
+        #Cell("XOR11"),
+        #Cell("XOR2"),
+        #Cell("XOR21"),
+        #Cell("XOR3"),
+        #Cell("XOR4"),
+        #Cell("XOR5"),
+        Cell("DP16KD"),
+        Cell("PDPW16KD"),
+        #Cell("DPR16X4C"),
+        #Cell("SPR16X4C"),
+        #Cell("LVDSOB"),
+        #Cell("IMIPI"),
+        #Cell("MULT9X9C"),
+        #Cell("MULT9X9D"),
+        #Cell("MULT18X18C"),
+        Cell("MULT18X18D"),
+        #Cell("ALU24A"),
+        #Cell("ALU54A"),
+        #Cell("ALU24B"),
+        Cell("ALU54B"),
+        #Cell("PRADD9A"),
+        #Cell("PRADD18A"),
+        #Cell("BCINRD"),
+        #Cell("BCLVDSOB"),
+        #Cell("INRDB"),
+        Cell("CLKDIVF"),
+        Cell("PCSCLKDIV"),
+        Cell("DCSC"),
+        Cell("DCCA"),
+        Cell("ECLKSYNCB"),
+        Cell("ECLKBRIDGECS"),
+        #Cell("PLLREFCS"),
+        Cell("DELAYF"),
+        Cell("DELAYG"),
+        #Cell("START"),
+        Cell("USRMCLK", True),
+        Cell("DQSBUFM"),
+        Cell("DDRDLLA"),
+        Cell("DLLDELD"),
+        Cell("IDDRX1F"),
+        Cell("IDDRX2F"),
+        Cell("IDDR71B"),
+        Cell("IDDRX2DQA"),
+        Cell("ODDRX1F"),
+        Cell("ODDRX2F"),
+        Cell("ODDR71B"),
+        Cell("OSHX2A"),
+        Cell("TSHX2DQA"),
+        Cell("TSHX2DQSA"),
+        Cell("ODDRX2DQA"),
+        Cell("ODDRX2DQSB"),
+        Cell("EHXPLLL"),
+        Cell("DTR"),
+        Cell("OSCG"),
+        Cell("EXTREFB"),
+        Cell("JTAGG", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
+        #Cell("SEDGA"),
+        Cell("DCUA", True, port_attrs={'CH0_HDINP': ['iopad_external_pin'], 'CH1_HDINP': ['iopad_external_pin'], 'CH0_HDINN': ['iopad_external_pin'], 'CH1_HDINN': ['iopad_external_pin']}),
+    ]),
+    ("cells_bb_xo2.v", "machxo2", [
+        #Cell("AGEB2"),
+        #Cell("ALEB2"),
+        #Cell("AND2"),
+        #Cell("AND3"),
+        #Cell("AND4"),
+        #Cell("AND5"),
+        #Cell("ANEB2"),
+        #Cell("BB"),
+        #Cell("BBPD"),
+        #Cell("BBPU"),
+        #Cell("BBW"),
+        #Cell("CB2"),
+        #Cell("CD2"),
+        #Cell("CU2"),
+        #Cell("FADD2B"),
+        #Cell("FADSU2"),
+        #Cell("FD1P3AX"),
+        #Cell("FD1P3AY"),
+        #Cell("FD1P3BX"),
+        #Cell("FD1P3DX"),
+        #Cell("FD1P3IX"),
+        #Cell("FD1P3JX"),
+        #Cell("FD1S1A"),
+        #Cell("FD1S1AY"),
+        #Cell("FD1S1B"),
+        #Cell("FD1S1D"),
+        #Cell("FD1S1I"),
+        #Cell("FD1S1J"),
+        #Cell("FD1S3AX"),
+        #Cell("FD1S3AY"),
+        #Cell("FD1S3BX"),
+        #Cell("FD1S3DX"),
+        #Cell("FD1S3IX"),
+        #Cell("FD1S3JX"),
+        #Cell("FL1P3AY"),
+        #Cell("FL1P3AZ"),
+        #Cell("FL1P3BX"),
+        #Cell("FL1P3DX"),
+        #Cell("FL1P3IY"),
+        #Cell("FL1P3JY"),
+        #Cell("FL1S1A"),
+        #Cell("FL1S1AY"),
+        #Cell("FL1S1B"),
+        #Cell("FL1S1D"),
+        #Cell("FL1S1I"),
+        #Cell("FL1S1J"),
+        #Cell("FL1S3AX"),
+        #Cell("FL1S3AY"),
+        #Cell("FSUB2B"),
+        Cell("GSR", True),
+        #Cell("IB"),
+        #Cell("IBPD"),
+        #Cell("IBPU"),
+        #Cell("IFS1P3BX"),
+        #Cell("IFS1P3DX"),
+        #Cell("IFS1P3IX"),
+        #Cell("IFS1P3JX"),
+        #Cell("ILVDS"),
+        #Cell("INV"),
+        #Cell("L6MUX21"),
+        #Cell("LB2P3AX"),
+        #Cell("LB2P3AY"),
+        #Cell("LB2P3BX"),
+        #Cell("LB2P3DX"),
+        #Cell("LB2P3IX"),
+        #Cell("LB2P3JX"),
+        #Cell("LD2P3AX"),
+        #Cell("LD2P3AY"),
+        #Cell("LD2P3BX"),
+        #Cell("LD2P3DX"),
+        #Cell("LD2P3IX"),
+        #Cell("LD2P3JX"),
+        #Cell("LU2P3AX"),
+        #Cell("LU2P3AY"),
+        #Cell("LU2P3BX"),
+        #Cell("LU2P3DX"),
+        #Cell("LU2P3IX"),
+        #Cell("LU2P3JX"),
+        #Cell("MULT2"),
+        #Cell("MUX161"),
+        #Cell("MUX21"),
+        #Cell("MUX321"),
+        #Cell("MUX41"),
+        #Cell("MUX81"),
+        #Cell("ND2"),
+        #Cell("ND3"),
+        #Cell("ND4"),
+        #Cell("ND5"),
+        #Cell("NR2"),
+        #Cell("NR3"),
+        #Cell("NR4"),
+        #Cell("NR5"),
+        #Cell("OB"),
+        #Cell("OBCO"),
+        #Cell("OBZ"),
+        #Cell("OBZPU"),
+        #Cell("OFS1P3BX"),
+        #Cell("OFS1P3DX"),
+        #Cell("OFS1P3IX"),
+        #Cell("OFS1P3JX"),
+        #Cell("OLVDS"),
+        #Cell("OR2"),
+        #Cell("OR3"),
+        #Cell("OR4"),
+        #Cell("OR5"),
+        #Cell("LUT4"),
+        #Cell("LUT5"),
+        #Cell("LUT6"),
+        #Cell("LUT7"),
+        #Cell("LUT8"),
+        #Cell("PFUMX"),
+        #Cell("PUR"),
+        #Cell("ROM128X1A"),
+        #Cell("ROM16X1A"),
+        #Cell("ROM256X1A"),
+        #Cell("ROM32X1A"),
+        #Cell("ROM64X1A"),
+        #Cell("CCU2D"),
+        #Cell("VHI"),
+        #Cell("VLO"),
+        #Cell("XNOR2"),
+        #Cell("XNOR3"),
+        #Cell("XNOR4"),
+        #Cell("XNOR5"),
+        #Cell("XOR11"),
+        #Cell("XOR2"),
+        #Cell("XOR21"),
+        #Cell("XOR3"),
+        #Cell("XOR4"),
+        #Cell("XOR5"),
+        #Cell("IFS1S1B"),
+        #Cell("IFS1S1D"),
+        #Cell("IFS1S1I"),
+        #Cell("IFS1S1J"),
+        #Cell("DPR16X4C"),
+        #Cell("SPR16X4C"),
+        Cell("SGSR", True),
+        Cell("DP8KC"),
+        Cell("PDPW8KC"),
+        Cell("SP8KC"),
+        Cell("FIFO8KB"),
+        Cell("CLKDIVC"),
+        Cell("DCMA"),
+        Cell("ECLKSYNCA"),
+        Cell("ECLKBRIDGECS"),
+        Cell("DCCA"),
+        #Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
+        Cell("START", True),
+        #Cell("SEDFA"),
+        #Cell("SEDFB"),
+        #Cell("IDDRXE"),
+        #Cell("IDDRX2E"),
+        #Cell("IDDRX4B"),
+        #Cell("IDDRDQSX1A"),
+        #Cell("IDDRX71A"),
+        #Cell("ODDRXE"),
+        #Cell("ODDRX2E"),
+        #Cell("ODDRX4B"),
+        #Cell("ODDRDQSX1A"),
+        #Cell("ODDRX71A"),
+        #Cell("TDDRA"),
+        #Cell("DQSBUFH"),
+        #Cell("DQSDLLC"),
+        #Cell("DELAYE"),
+        #Cell("DELAYD"),
+        #Cell("DLLDELC"),
+        #Cell("CLKFBBUFA"),
+        #Cell("PCNTR"),
+        #Cell("BCINRD"),
+        #Cell("BCLVDSO"),
+        #Cell("INRDB"),
+        #Cell("LVDSOB"),
+        #Cell("PG"),
+        Cell("EHXPLLJ"),
+        #Cell("PLLREFCS"),
+        Cell("OSCH"),
+        #Cell("EFB"),
+        Cell("TSALL", True),
+    ]),
+    ("cells_bb_xo3.v", "machxo3lf", [
+        #Cell("AGEB2"),
+        #Cell("ALEB2"),
+        #Cell("AND2"),
+        #Cell("AND3"),
+        #Cell("AND4"),
+        #Cell("AND5"),
+        #Cell("ANEB2"),
+        #Cell("BB"),
+        #Cell("BBPD"),
+        #Cell("BBPU"),
+        #Cell("BBW"),
+        #Cell("CB2"),
+        #Cell("CD2"),
+        #Cell("CU2"),
+        #Cell("FADD2B"),
+        #Cell("FADSU2"),
+        #Cell("FD1P3AX"),
+        #Cell("FD1P3AY"),
+        #Cell("FD1P3BX"),
+        #Cell("FD1P3DX"),
+        #Cell("FD1P3IX"),
+        #Cell("FD1P3JX"),
+        #Cell("FD1S1A"),
+        #Cell("FD1S1AY"),
+        #Cell("FD1S1B"),
+        #Cell("FD1S1D"),
+        #Cell("FD1S1I"),
+        #Cell("FD1S1J"),
+        #Cell("FD1S3AX"),
+        #Cell("FD1S3AY"),
+        #Cell("FD1S3BX"),
+        #Cell("FD1S3DX"),
+        #Cell("FD1S3IX"),
+        #Cell("FD1S3JX"),
+        #Cell("FL1P3AY"),
+        #Cell("FL1P3AZ"),
+        #Cell("FL1P3BX"),
+        #Cell("FL1P3DX"),
+        #Cell("FL1P3IY"),
+        #Cell("FL1P3JY"),
+        #Cell("FL1S1A"),
+        #Cell("FL1S1AY"),
+        #Cell("FL1S1B"),
+        #Cell("FL1S1D"),
+        #Cell("FL1S1I"),
+        #Cell("FL1S1J"),
+        #Cell("FL1S3AX"),
+        #Cell("FL1S3AY"),
+        #Cell("FSUB2B"),
+        Cell("GSR", True),
+        #Cell("IB"),
+        #Cell("IBPD"),
+        #Cell("IBPU"),
+        #Cell("IFS1P3BX"),
+        #Cell("IFS1P3DX"),
+        #Cell("IFS1P3IX"),
+        #Cell("IFS1P3JX"),
+        #Cell("ILVDS"),
+        #Cell("INV"),
+        #Cell("L6MUX21"),
+        #Cell("LB2P3AX"),
+        #Cell("LB2P3AY"),
+        #Cell("LB2P3BX"),
+        #Cell("LB2P3DX"),
+        #Cell("LB2P3IX"),
+        #Cell("LB2P3JX"),
+        #Cell("LD2P3AX"),
+        #Cell("LD2P3AY"),
+        #Cell("LD2P3BX"),
+        #Cell("LD2P3DX"),
+        #Cell("LD2P3IX"),
+        #Cell("LD2P3JX"),
+        #Cell("LU2P3AX"),
+        #Cell("LU2P3AY"),
+        #Cell("LU2P3BX"),
+        #Cell("LU2P3DX"),
+        #Cell("LU2P3IX"),
+        #Cell("LU2P3JX"),
+        #Cell("MULT2"),
+        #Cell("MUX161"),
+        #Cell("MUX21"),
+        #Cell("MUX321"),
+        #Cell("MUX41"),
+        #Cell("MUX81"),
+        #Cell("ND2"),
+        #Cell("ND3"),
+        #Cell("ND4"),
+        #Cell("ND5"),
+        #Cell("NR2"),
+        #Cell("NR3"),
+        #Cell("NR4"),
+        #Cell("NR5"),
+        #Cell("OB"),
+        #Cell("OBCO"),
+        #Cell("OBZ"),
+        #Cell("OBZPU"),
+        #Cell("OFS1P3BX"),
+        #Cell("OFS1P3DX"),
+        #Cell("OFS1P3IX"),
+        #Cell("OFS1P3JX"),
+        #Cell("OLVDS"),
+        #Cell("OR2"),
+        #Cell("OR3"),
+        #Cell("OR4"),
+        #Cell("OR5"),
+        #Cell("LUT4"),
+        #Cell("LUT5"),
+        #Cell("LUT6"),
+        #Cell("LUT7"),
+        #Cell("LUT8"),
+        #Cell("PFUMX"),
+        #Cell("PUR"),
+        #Cell("ROM128X1A"),
+        #Cell("ROM16X1A"),
+        #Cell("ROM256X1A"),
+        #Cell("ROM32X1A"),
+        #Cell("ROM64X1A"),
+        #Cell("CCU2D"),
+        #Cell("VHI"),
+        #Cell("VLO"),
+        #Cell("XNOR2"),
+        #Cell("XNOR3"),
+        #Cell("XNOR4"),
+        #Cell("XNOR5"),
+        #Cell("XOR11"),
+        #Cell("XOR2"),
+        #Cell("XOR21"),
+        #Cell("XOR3"),
+        #Cell("XOR4"),
+        #Cell("XOR5"),
+        #Cell("IFS1S1B"),
+        #Cell("IFS1S1D"),
+        #Cell("IFS1S1I"),
+        #Cell("IFS1S1J"),
+        #Cell("DPR16X4C"),
+        #Cell("SPR16X4C"),
+        Cell("SGSR", True),
+        Cell("DP8KC"),
+        Cell("PDPW8KC"),
+        Cell("SP8KC"),
+        Cell("FIFO8KB"),
+        Cell("CLKDIVC"),
+        Cell("DCMA"),
+        Cell("ECLKSYNCA"),
+        Cell("ECLKBRIDGECS"),
+        Cell("DCCA"),
+        #Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
+        Cell("START", True),
+        #Cell("SEDFA"),
+        #Cell("SEDFB"),
+        #Cell("IDDRXE"),
+        #Cell("IDDRX2E"),
+        #Cell("IDDRX4B"),
+        #Cell("IDDRX71A"),
+        #Cell("ODDRXE"),
+        #Cell("ODDRX2E"),
+        #Cell("ODDRX4B"),
+        #Cell("ODDRX71A"),
+        #Cell("DQSDLLC"),
+        #Cell("DELAYE"),
+        #Cell("DELAYD"),
+        #Cell("DLLDELC"),
+        #Cell("CLKFBBUFA"),
+        #Cell("PCNTR"),
+        #Cell("BCINRD"),
+        #Cell("BCLVDSO"),
+        #Cell("INRDB"),
+        #Cell("LVDSOB"),
+        #Cell("PG"),
+        Cell("EHXPLLJ"),
+        #Cell("PLLREFCS"),
+        Cell("OSCH"),
+        #Cell("EFB"),
+        Cell("TSALL", True),
+    ]),
+    ("cells_bb_xo3d.v", "machxo3d", [
+        #Cell("AGEB2"),
+        #Cell("ALEB2"),
+        #Cell("AND2"),
+        #Cell("AND3"),
+        #Cell("AND4"),
+        #Cell("AND5"),
+        #Cell("ANEB2"),
+        #Cell("BB"),
+        #Cell("BBPD"),
+        #Cell("BBPU"),
+        #Cell("BBI3C"),
+        #Cell("BBW"),
+        #Cell("CB2"),
+        #Cell("CD2"),
+        #Cell("CU2"),
+        #Cell("FADD2B"),
+        #Cell("FADSU2"),
+        #Cell("FD1P3AX"),
+        #Cell("FD1P3AY"),
+        #Cell("FD1P3BX"),
+        #Cell("FD1P3DX"),
+        #Cell("FD1P3IX"),
+        #Cell("FD1P3JX"),
+        #Cell("FD1S1A"),
+        #Cell("FD1S1AY"),
+        #Cell("FD1S1B"),
+        #Cell("FD1S1D"),
+        #Cell("FD1S1I"),
+        #Cell("FD1S1J"),
+        #Cell("FD1S3AX"),
+        #Cell("FD1S3AY"),
+        #Cell("FD1S3BX"),
+        #Cell("FD1S3DX"),
+        #Cell("FD1S3IX"),
+        #Cell("FD1S3JX"),
+        #Cell("FL1P3AY"),
+        #Cell("FL1P3AZ"),
+        #Cell("FL1P3BX"),
+        #Cell("FL1P3DX"),
+        #Cell("FL1P3IY"),
+        #Cell("FL1P3JY"),
+        #Cell("FL1S1A"),
+        #Cell("FL1S1AY"),
+        #Cell("FL1S1B"),
+        #Cell("FL1S1D"),
+        #Cell("FL1S1I"),
+        #Cell("FL1S1J"),
+        #Cell("FL1S3AX"),
+        #Cell("FL1S3AY"),
+        #Cell("FSUB2B"),
+        Cell("GSR", True),
+        #Cell("IB"),
+        #Cell("IBPD"),
+        #Cell("IBPU"),
+        #Cell("IFS1P3BX"),
+        #Cell("IFS1P3DX"),
+        #Cell("IFS1P3IX"),
+        #Cell("IFS1P3JX"),
+        #Cell("ILVDS"),
+        #Cell("INV"),
+        #Cell("L6MUX21"),
+        #Cell("LB2P3AX"),
+        #Cell("LB2P3AY"),
+        #Cell("LB2P3BX"),
+        #Cell("LB2P3DX"),
+        #Cell("LB2P3IX"),
+        #Cell("LB2P3JX"),
+        #Cell("LD2P3AX"),
+        #Cell("LD2P3AY"),
+        #Cell("LD2P3BX"),
+        #Cell("LD2P3DX"),
+        #Cell("LD2P3IX"),
+        #Cell("LD2P3JX"),
+        #Cell("LU2P3AX"),
+        #Cell("LU2P3AY"),
+        #Cell("LU2P3BX"),
+        #Cell("LU2P3DX"),
+        #Cell("LU2P3IX"),
+        #Cell("LU2P3JX"),
+        #Cell("MULT2"),
+        #Cell("MUX161"),
+        #Cell("MUX21"),
+        #Cell("MUX321"),
+        #Cell("MUX41"),
+        #Cell("MUX81"),
+        #Cell("ND2"),
+        #Cell("ND3"),
+        #Cell("ND4"),
+        #Cell("ND5"),
+        #Cell("NR2"),
+        #Cell("NR3"),
+        #Cell("NR4"),
+        #Cell("NR5"),
+        #Cell("OB"),
+        #Cell("OBCO"),
+        #Cell("OBZ"),
+        #Cell("OBZPU"),
+        #Cell("OFS1P3BX"),
+        #Cell("OFS1P3DX"),
+        #Cell("OFS1P3IX"),
+        #Cell("OFS1P3JX"),
+        #Cell("OLVDS"),
+        #Cell("OR2"),
+        #Cell("OR3"),
+        #Cell("OR4"),
+        #Cell("OR5"),
+        #Cell("LUT4"),
+        #Cell("LUT5"),
+        #Cell("LUT6"),
+        #Cell("LUT7"),
+        #Cell("LUT8"),
+        #Cell("PFUMX"),
+        #Cell("PUR"),
+        #Cell("ROM128X1A"),
+        #Cell("ROM16X1A"),
+        #Cell("ROM256X1A"),
+        #Cell("ROM32X1A"),
+        #Cell("ROM64X1A"),
+        #Cell("CCU2D"),
+        #Cell("VHI"),
+        #Cell("VLO"),
+        #Cell("XNOR2"),
+        #Cell("XNOR3"),
+        #Cell("XNOR4"),
+        #Cell("XNOR5"),
+        #Cell("XOR11"),
+        #Cell("XOR2"),
+        #Cell("XOR21"),
+        #Cell("XOR3"),
+        #Cell("XOR4"),
+        #Cell("XOR5"),
+        #Cell("IFS1S1B"),
+        #Cell("IFS1S1D"),
+        #Cell("IFS1S1I"),
+        #Cell("IFS1S1J"),
+        #Cell("DPR16X4C"),
+        #Cell("SPR16X4C"),
+        Cell("SGSR", True),
+        Cell("DP8KC"),
+        Cell("PDPW8KC"),
+        Cell("SP8KC"),
+        Cell("FIFO8KB"),
+        Cell("CLKDIVC"),
+        Cell("DCMA"),
+        Cell("ECLKSYNCA"),
+        Cell("ECLKBRIDGECS"),
+        Cell("DCCA"),
+        #Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
+        Cell("START", True),
+        #Cell("SEDFA"),
+        #Cell("SEDFB"),
+        #Cell("IDDRXE"),
+        #Cell("IDDRX2E"),
+        #Cell("IDDRX4B"),
+        #Cell("IDDRX71A"),
+        #Cell("ODDRXE"),
+        #Cell("ODDRX2E"),
+        #Cell("ODDRX4B"),
+        #Cell("ODDRX71A"),
+        #Cell("DQSDLLC"),
+        #Cell("DELAYE"),
+        #Cell("DELAYD"),
+        #Cell("DLLDELC"),
+        #Cell("CLKFBBUFA"),
+        #Cell("PCNTR"),
+        #Cell("BCINRD"),
+        #Cell("BCLVDSO"),
+        #Cell("INRDB"),
+        #Cell("LVDSOB"),
+        #Cell("PG"),
+        Cell("EHXPLLJ"),
+        #Cell("PLLREFCS"),
+        Cell("OSCJ"),
+        #Cell("EFBB"),
+        Cell("TSALL", True),
+        #Cell("ESBA"),
+        #Cell("BCSLEWRATEA"),
+    ])
+]
+
+def xtract_cells_decl(device, cells, dirs, outf):
+    fname = os.path.join(dir, device + '.v')
+    with open(fname) as f:
+        state = State.OUTSIDE
+        # Probably the most horrible Verilog "parser" ever written.
+        cell = None
+        kind = None
+        for l in f:
+            l, _, comment = l.partition('//')
+            l = l.strip()
+            m = re.search(r'synthesis .*black_box_pad_pin="([^"]*)"', comment)
+            if m:
+                iopad_pin = set(m.group(1).split(","))
+
+            if l.startswith("module "):
+                cell_name = l[7:l.find('(')].strip()
+                cell = None
+                kind = None
+                module_ports = []
+                iopad_pin = set()
+                if state != State.OUTSIDE:
+                    print('Nested modules in {}.'.format(fname))
+                    sys.exit(1)
+                for c in cells:
+                    if c.name != cell_name:
+                        continue
+                    cell = c
+                    state = State.IN_MODULE
+                    outf.write('(* blackbox *)')
+                    if cell.keep:
+                        outf.write(' (* keep *)\n')
+                    else:
+                        outf.write('\n')
+                    outf.write('module {} (...);\n'.format(cell.name))
+                    cell.found = True
+                if cell is None:
+                    state = State.IN_OTHER_MODULE
+            elif l.startswith('task '):
+                if state == State.IN_MODULE:
+                    state = State.IN_TASK
+            elif l.startswith('function '):
+                if state == State.IN_MODULE:
+                    state = State.IN_FUNCTION
+            elif l == 'endtask':
+                if state == State.IN_TASK:
+                    state = State.IN_MODULE
+            elif l == 'endfunction':
+                if state == State.IN_FUNCTION:
+                    state = State.IN_MODULE
+            elif l == 'endmodule':
+                if state == State.IN_MODULE:
+                    for kind, rng, port in module_ports:
+                        for attr in cell.port_attrs.get(port, []):
+                            outf.write('    (* {} *)\n'.format(attr))
+                        if port in iopad_pin:
+                            outf.write('    (* iopad_external_pin *)\n')
+                        if rng is None:
+                            outf.write('    {} {};\n'.format(kind, port))
+                        else:
+                            outf.write('    {} {} {};\n'.format(kind, rng, port))
+                    outf.write(l + '\n')
+                    outf.write('\n')
+                elif state != State.IN_OTHER_MODULE:
+                    print('endmodule in weird place in {}.'.format(cell.name, fname))
+                    sys.exit(1)
+                state = State.OUTSIDE
+            elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
+                l = l.strip()
+                if l == "":
+                    continue
+                if l.endswith((';', ',', ")")):
+                    l = l[:-1]
+                l = l.replace(")","")
+                if ';' in l:
+                    print('Weird port line in {} [{}].'.format(fname, l))
+                    sys.exit(1)
+                kind, _, ports = l.partition(' ')
+                for port in ports.split(','):
+                    port = port.strip()
+                    if port.startswith('['):
+                        rng, port = port.split()
+                    else:
+                        rng = None
+                    module_ports.append((kind, rng, port))
+            elif l.startswith('parameter ') and state == State.IN_MODULE:
+                l = l.strip()
+                if l.endswith((';', ',')):
+                    l = l[:-1]
+                while '  ' in l:
+                    l = l.replace('  ', ' ')
+
+                if "INITVAL" in l:
+                    l = l.replace('"0x', "320'h")
+                    l = l.replace('"', '')
+                if ';' in l:
+                    print('Weird parameter line in {} [{}].'.format(fname, l))
+                    sys.exit(1)
+                outf.write('    {};\n'.format(l))
+            elif kind is not None and state == State.IN_MODULE:
+                l = l.strip()
+                if l == "":
+                    continue
+                if l.endswith((';', ',', ")")):
+                    l = l[:-1]
+                l = l.replace(")","")
+                if l == "":
+                    continue
+                if ';' in l:
+                    print('Weird port line in {} [{}].'.format(fname, l))
+                    sys.exit(1)
+                ports = l
+                for port in ports.split(','):
+                    port = port.strip()
+                    if port.startswith('['):
+                        rng, port = port.split()
+                    else:
+                        rng = None
+                    module_ports.append((kind, rng, port))
+
+        if state != State.OUTSIDE:
+            print('endmodule not found in {}.'.format(fname))
+            sys.exit(1)
+        for cell in cells:
+            if not cell.found:
+                print('cell {} not found in {}.'.format(cell.name, fname))
+if __name__ == '__main__':
+    parser = ArgumentParser(description='Extract Lattice blackbox cell definitions from Lattice Diamond.')
+    parser.add_argument('diamond_dir', nargs='?', default='/usr/local/diamond/3.12/')
+    args = parser.parse_args()
+
+    dirs = [
+        os.path.join(args.diamond_dir, 'cae_library/synthesis/verilog/'),
+    ]
+    for dir in dirs:
+        if not os.path.isdir(dir):
+            print('{} is not a directory'.format(dir))
+
+    for fn, device, cells in devices:
+        out = StringIO()
+        xtract_cells_decl(device, cells, dirs, out)
+        with open(fn, 'w') as f:
+            f.write('// Created by cells_xtra.py from Lattice models\n')
+            f.write('\n')
+            f.write(out.getvalue())
diff --git a/yosys/techlibs/lattice/common_sim.vh b/yosys/techlibs/lattice/common_sim.vh
new file mode 100644
index 00000000000..2f8e1db1a82
--- /dev/null
+++ b/yosys/techlibs/lattice/common_sim.vh
@@ -0,0 +1,411 @@
+// ---------------------------------------
+
+(* abc9_lut=1, lib_whitebox *)
+module LUT4(input A, B, C, D, output Z);
+    parameter [15:0] INIT = 16'h0000;
+    wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
+    wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];
+    wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];
+    assign Z =      A ?          s1[1] :         s1[0];
+    specify
+        (A => Z) = 141;
+        (B => Z) = 275;
+        (C => Z) = 379;
+        (D => Z) = 379;
+    endspecify
+endmodule
+
+// This is a placeholder for ABC9 to extract the area/delay
+//   cost of 5-input LUTs and is not intended to be instantiated
+// LUT5 = 2x LUT4 + PFUMX
+(* abc9_lut=2 *)
+module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z);
+    specify
+        (M0 => Z) = 151;
+        (D => Z) = 239;
+        (C => Z) = 373;
+        (B => Z) = 477;
+        (A => Z) = 477;
+    endspecify
+endmodule
+
+// This is a placeholder for ABC9 to extract the area/delay
+//   of 6-input LUTs and is not intended to be instantiated
+// LUT6 = 2x LUT5 + MUX2
+(* abc9_lut=4 *)
+module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);
+    specify
+        (M1 => Z) = 148;
+        (M0 => Z) = 292;
+        (D => Z) = 380;
+        (C => Z) = 514;
+        (B => Z) = 618;
+        (A => Z) = 618;
+    endspecify
+endmodule
+
+// This is a placeholder for ABC9 to extract the area/delay
+//   of 7-input LUTs and is not intended to be instantiated
+// LUT7 = 2x LUT6 + MUX2
+(* abc9_lut=8 *)
+module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);
+    specify
+        (M2 => Z) = 148;
+        (M1 => Z) = 289;
+        (M0 => Z) = 433;
+        (D => Z) = 521;
+        (C => Z) = 655;
+        (B => Z) = 759;
+        (A => Z) = 759;
+    endspecify
+endmodule
+
+// ---------------------------------------
+(* abc9_box, lib_whitebox *)
+module L6MUX21 (input D0, D1, SD, output Z);
+	assign Z = SD ? D1 : D0;
+	specify
+		(D0 => Z) = 140;
+		(D1 => Z) = 141;
+		(SD => Z) = 148;
+	endspecify
+endmodule
+
+// ---------------------------------------
+
+module TRELLIS_RAM16X2 (
+	input DI0, DI1,
+	input WAD0, WAD1, WAD2, WAD3,
+	input WRE, WCK,
+	input RAD0, RAD1, RAD2, RAD3,
+	output DO0, DO1
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter INITVAL_0 = 16'h0000;
+	parameter INITVAL_1 = 16'h0000;
+
+	reg [1:0] mem[15:0];
+
+	integer i;
+	initial begin
+		for (i = 0; i < 16; i = i + 1)
+			mem[i] <= {INITVAL_1[i], INITVAL_0[i]};
+	end
+
+	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
+
+	reg muxwre;
+	always @(*)
+		case (WREMUX)
+			"1": muxwre = 1'b1;
+			"0": muxwre = 1'b0;
+			"INV": muxwre = ~WRE;
+			default: muxwre = WRE;
+		endcase
+
+
+	always @(posedge muxwck)
+		if (muxwre)
+			mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};
+
+	assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];
+endmodule
+
+// ---------------------------------------
+(* abc9_box, lib_whitebox *)
+module PFUMX (input ALUT, BLUT, C0, output Z);
+	assign Z = C0 ? ALUT : BLUT;
+	specify
+		(ALUT => Z) = 98;
+		(BLUT => Z) = 98;
+		(C0 => Z) = 151;
+	endspecify
+endmodule
+
+// ---------------------------------------
+(* abc9_box, lib_whitebox *)
+module TRELLIS_DPR16X4 (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+
+	reg [3:0] mem[15:0];
+
+	integer i;
+	initial begin
+		for (i = 0; i < 16; i = i + 1)
+			mem[i] <= INITVAL[4*i +: 4];
+	end
+
+	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
+
+	reg muxwre;
+	always @(*)
+		case (WREMUX)
+			"1": muxwre = 1'b1;
+			"0": muxwre = 1'b0;
+			"INV": muxwre = ~WRE;
+			default: muxwre = WRE;
+		endcase
+
+	always @(posedge muxwck)
+		if (muxwre)
+			mem[WAD] <= DI;
+
+	assign DO = mem[RAD];
+
+	specify
+		// TODO
+		(RAD *> DO) = 0;
+	endspecify
+endmodule
+
+// ---------------------------------------
+
+(* abc9_box, lib_whitebox *)
+module DPR16X4C (
+		input [3:0] DI,
+		input WCK, WRE,
+		input [3:0] RAD,
+		input [3:0] WAD,
+		output [3:0] DO
+);
+	// For legacy Lattice compatibility, INITIVAL is a hex
+	// string rather than a numeric parameter
+	parameter INITVAL = "0x0000000000000000";
+
+	function [63:0] convert_initval;
+		input [143:0] hex_initval;
+		reg done;
+		reg [63:0] temp;
+		reg [7:0] char;
+		integer i;
+		begin
+			done = 1'b0;
+			temp = 0;
+			for (i = 0; i < 16; i = i + 1) begin
+				if (!done) begin
+					char = hex_initval[8*i +: 8];
+					if (char == "x") begin
+						done = 1'b1;
+					end else begin
+						if (char >= "0" && char <= "9")
+							temp[4*i +: 4] = char - "0";
+						else if (char >= "A" && char <= "F")
+							temp[4*i +: 4] = 10 + char - "A";
+						else if (char >= "a" && char <= "f")
+							temp[4*i +: 4] = 10 + char - "a";
+					end
+				end
+			end
+			convert_initval = temp;
+		end
+	endfunction
+
+	localparam conv_initval = convert_initval(INITVAL);
+
+	reg [3:0] ram[0:15];
+	integer i;
+	initial begin
+		for (i = 0; i < 15; i = i + 1) begin
+			ram[i] <= conv_initval[4*i +: 4];
+		end
+	end
+
+	always @(posedge WCK)
+		if (WRE)
+			ram[WAD] <= DI;
+
+	assign DO = ram[RAD];
+
+	specify
+		// TODO
+		(RAD *> DO) = 0;
+	endspecify
+endmodule
+
+// ---------------------------------------
+
+(* lib_whitebox *)
+module LUT2(input A, B, output Z);
+    parameter [3:0] INIT = 4'h0;
+    wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];
+    assign Z =      A ?          s1[1] :         s1[0];
+endmodule
+
+// ---------------------------------------
+
+`ifdef YOSYS
+(* abc9_flop=(SRMODE != "ASYNC"), abc9_box=(SRMODE == "ASYNC"), lib_whitebox *)
+`endif
+module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
+	parameter GSR = "ENABLED";
+	parameter [127:0] CEMUX = "1";
+	parameter CLKMUX = "CLK";
+	parameter LSRMUX = "LSR";
+	parameter SRMODE = "LSR_OVER_CE";
+	parameter REGSET = "RESET";
+	parameter [127:0] LSRMODE = "LSR";
+
+	wire muxce;
+	generate
+		case (CEMUX)
+			"1": assign muxce = 1'b1;
+			"0": assign muxce = 1'b0;
+			"INV": assign muxce = ~CE;
+			default: assign muxce = CE;
+		endcase
+	endgenerate
+
+	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
+	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
+	wire srval;
+	generate
+		if (LSRMODE == "PRLD")
+			assign srval = M;
+		else
+			assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+	endgenerate
+
+	initial Q = srval;
+
+	generate
+		if (SRMODE == "ASYNC") begin
+			always @(posedge muxclk, posedge muxlsr)
+				if (muxlsr)
+					Q <= srval;
+				else if (muxce)
+					Q <= DI;
+		end else begin
+			always @(posedge muxclk)
+				if (muxlsr)
+					Q <= srval;
+				else if (muxce)
+					Q <= DI;
+		end
+	endgenerate
+
+	specify
+		$setup(DI, negedge CLK &&& CLKMUX == "INV", 0);
+		$setup(CE, negedge CLK &&& CLKMUX == "INV", 0);
+		$setup(LSR, negedge CLK &&& CLKMUX == "INV", 0);
+		$setup(DI, posedge CLK &&& CLKMUX != "INV", 0);
+		$setup(CE, posedge CLK &&& CLKMUX != "INV", 0);
+		$setup(LSR, posedge CLK &&& CLKMUX != "INV", 0);
+`ifndef YOSYS
+		if (SRMODE == "ASYNC" && muxlsr && CLKMUX == "INV") (negedge CLK => (Q : srval)) = 0;
+		if (SRMODE == "ASYNC" && muxlsr && CLKMUX != "INV") (posedge CLK => (Q : srval)) = 0;
+`else
+		if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; 	// Technically, this should be an edge sensitive path
+									// but for facilitating a bypass box, let's pretend it's
+									// a simple path
+`endif
+		if (!muxlsr && muxce && CLKMUX == "INV") (negedge CLK => (Q : DI)) = 0;
+		if (!muxlsr && muxce && CLKMUX != "INV") (posedge CLK => (Q : DI)) = 0;
+	endspecify
+endmodule
+
+// ---------------------------------------
+(* keep *)
+module TRELLIS_IO(
+	(* iopad_external_pin *)
+	inout B,
+	input I,
+	input T,
+	output O
+);
+	parameter DIR = "INPUT";
+	reg T_pd;
+	always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
+
+	generate
+		if (DIR == "INPUT") begin
+			assign B = 1'bz;
+			assign O = B;
+		end else if (DIR == "OUTPUT") begin
+			assign B = T_pd ? 1'bz : I;
+			assign O = 1'bx;
+		end else if (DIR == "BIDIR") begin
+			assign B = T_pd ? 1'bz : I;
+			assign O = B;
+		end else begin
+			ERROR_UNKNOWN_IO_MODE error();
+		end
+	endgenerate
+
+endmodule
+
+// ---------------------------------------
+
+module INV(input A, output Z);
+	assign Z = !A;
+endmodule
+
+// ---------------------------------------
+
+module TRELLIS_COMB(
+	input A, B, C, D, M,
+	input FCI, F1, FXA, FXB,
+	input WD,
+	input WAD0, WAD1, WAD2, WAD3,
+	input WRE, WCK,
+	output F, FCO, OFX
+);
+	parameter MODE = "LOGIC";
+	parameter INITVAL = 16'h0;
+	parameter CCU2_INJECT1 = "NO";
+	parameter WREMUX = "WRE";
+	parameter IS_Z1 = 1'b0;
+
+	generate
+		if (MODE == "LOGIC") begin: mode_logic
+			LUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F));
+		end else if (MODE == "CCU2") begin: mode_ccu2
+			wire l4o, l2o;
+			LUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o));
+			LUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o));
+			wire gated_cin_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : FCI;
+			assign F = l4o ^ gated_cin_0;
+			wire gated_lut2_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : l2o;
+			wire FCO = (~l4o & gated_lut2_0) | (l4o & FCI);
+		end else if (MODE == "DPRAM") begin: mode_dpram
+			reg [15:0] ram = INITVAL;
+			always @(posedge WCK)
+				if (WRE)
+					ram[{WAD3, WAD2, WAD1, WAD0}] <= WD;
+			assign F = ram[{A, C, B, D}];
+		end else begin
+			$error("unsupported COMB mode %s", MODE);
+		end
+
+ 		if (IS_Z1)
+			L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX));
+		else
+			PFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX));
+	endgenerate
+
+endmodule
+
+// Constants
+module VLO(output Z);
+	assign Z = 1'b0;
+endmodule
+
+module VHI(output Z);
+	assign Z = 1'b1;
+endmodule
+
+`ifndef NO_INCLUDES
+
+`include "cells_ff.vh"
+`include "cells_io.vh"
+
+`endif
diff --git a/yosys/techlibs/lattice/dsp_map_18x18.v b/yosys/techlibs/lattice/dsp_map_18x18.v
new file mode 100644
index 00000000000..df54d1d9f9f
--- /dev/null
+++ b/yosys/techlibs/lattice/dsp_map_18x18.v
@@ -0,0 +1,17 @@
+module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
+
+	parameter A_WIDTH = 18;
+	parameter B_WIDTH = 18;
+	parameter Y_WIDTH = 36;
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+
+	MULT18X18D _TECHMAP_REPLACE_ (
+		.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
+		.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
+		.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
+		.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0), .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),
+
+		.P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35])
+	);
+endmodule
diff --git a/yosys/techlibs/lattice/latches_map.v b/yosys/techlibs/lattice/latches_map.v
new file mode 100644
index 00000000000..c28f88cf767
--- /dev/null
+++ b/yosys/techlibs/lattice/latches_map.v
@@ -0,0 +1,11 @@
+module \$_DLATCH_N_ (E, D, Q);
+  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q = !E ? D : Q;
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q);
+  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q = E ? D : Q;
+endmodule
diff --git a/yosys/techlibs/ecp5/ecp5_gsr.cc b/yosys/techlibs/lattice/lattice_gsr.cc
similarity index 93%
rename from yosys/techlibs/ecp5/ecp5_gsr.cc
rename to yosys/techlibs/lattice/lattice_gsr.cc
index 62b231aab3b..d7d41eca519 100644
--- a/yosys/techlibs/ecp5/ecp5_gsr.cc
+++ b/yosys/techlibs/lattice/lattice_gsr.cc
@@ -24,13 +24,13 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-struct Ecp5GsrPass : public Pass {
-	Ecp5GsrPass() : Pass("ecp5_gsr", "ECP5: handle GSR") { }
+struct LatticeGsrPass : public Pass {
+	LatticeGsrPass() : Pass("lattice_gsr", "Lattice: handle GSR") { }
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    ecp5_gsr [options] [selection]\n");
+		log("    lattice_gsr [options] [selection]\n");
 		log("\n");
 		log("Trim active low async resets connected to GSR and resolve GSR parameter,\n");
 		log("if a GSR or SGSR primitive is used in the design.\n");
@@ -42,7 +42,7 @@ struct Ecp5GsrPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		log_header(design, "Executing ECP5_GSR pass (implement FF init values).\n");
+		log_header(design, "Executing LATTICE_GSR pass (implement FF init values).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -130,6 +130,6 @@ struct Ecp5GsrPass : public Pass {
 
 		}
 	}
-} Ecp5GsrPass;
+} LatticeGsrPass;
 
 PRIVATE_NAMESPACE_END
diff --git a/yosys/techlibs/machxo2/lutrams.txt b/yosys/techlibs/lattice/lutrams.txt
similarity index 54%
rename from yosys/techlibs/machxo2/lutrams.txt
rename to yosys/techlibs/lattice/lutrams.txt
index c6b0b6c4560..ea42d4fcb5e 100644
--- a/yosys/techlibs/machxo2/lutrams.txt
+++ b/yosys/techlibs/lattice/lutrams.txt
@@ -1,11 +1,11 @@
-ram distributed $__DPR16X4C_ {
+ram distributed $__TRELLIS_DPR16X4_ {
 	abits 4;
 	width 4;
 	cost 4;
-	init no_undef;
+	init any;
 	prune_rom;
 	port sw "W" {
-		clock posedge;
+		clock anyedge;
 	}
 	port ar "R" {
 	}
diff --git a/yosys/techlibs/lattice/lutrams_map.v b/yosys/techlibs/lattice/lutrams_map.v
new file mode 100644
index 00000000000..3cb325f041e
--- /dev/null
+++ b/yosys/techlibs/lattice/lutrams_map.v
@@ -0,0 +1,30 @@
+module $__TRELLIS_DPR16X4_(...);
+
+parameter INIT = 64'bx;
+parameter PORT_W_CLK_POL = 1;
+
+input PORT_W_CLK;
+input [3:0] PORT_W_ADDR;
+input [3:0] PORT_W_WR_DATA;
+input PORT_W_WR_EN;
+
+input [3:0] PORT_R_ADDR;
+output [3:0] PORT_R_RD_DATA;
+
+localparam WCKMUX = PORT_W_CLK_POL ? "WCK" : "INV";
+
+TRELLIS_DPR16X4 #(
+	.INITVAL(INIT),
+	.WCKMUX(WCKMUX),
+	.WREMUX("WRE")
+) _TECHMAP_REPLACE_ (
+	.RAD(PORT_R_ADDR),
+	.DO(PORT_R_RD_DATA),
+
+	.WAD(PORT_W_ADDR),
+	.DI(PORT_W_WR_DATA),
+	.WCK(PORT_W_CLK),
+	.WRE(PORT_W_WR_EN)
+);
+
+endmodule
diff --git a/yosys/techlibs/lattice/synth_lattice.cc b/yosys/techlibs/lattice/synth_lattice.cc
new file mode 100644
index 00000000000..16a068b0741
--- /dev/null
+++ b/yosys/techlibs/lattice/synth_lattice.cc
@@ -0,0 +1,520 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
+ *  Copyright (C) 2018 gatecat <gatecat@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthLatticePass : public ScriptPass
+{
+	SynthLatticePass() : ScriptPass("synth_lattice", "synthesis for Lattice FPGAs") { }
+
+	void on_register() override
+	{
+		RTLIL::constpad["synth_lattice.abc9.W"] = "300";
+	}
+
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    synth_lattice [options]\n");
+		log("\n");
+		log("This command runs synthesis for Lattice FPGAs (excluding iCE40 and Nexus).\n");
+		log("\n");
+		log("    -top <module>\n");
+		log("        use the specified module as top module\n");
+		log("\n");
+		log("    -family <family>\n");
+		log("        run synthesis for the specified Lattice architecture\n");
+		log("        generate the synthesis netlist for the specified family.\n");
+		log("        supported values:\n");
+		log("        - ecp5: ECP5\n");
+		log("        - xo2: MachXO2\n");
+		log("        - xo3: MachXO3L/LF\n");
+		log("        - xo3d: MachXO3D\n");
+		//log("        - xo: MachXO (EXPERIMENTAL)\n");
+		//log("        - pm: Platform Manager (EXPERIMENTAL)\n");
+		//log("        - pm2: Platform Manager 2 (EXPERIMENTAL)\n");
+		//log("        - xp: LatticeXP (EXPERIMENTAL)\n");
+		//log("        - xp2: LatticeXP2 (EXPERIMENTAL)\n");
+		//log("        - ecp: LatticeECP/EC (EXPERIMENTAL)\n");
+		//log("        - sm: LatticeSC/M (EXPERIMENTAL)\n");
+		//log("        - ecp2: LatticeECP2/M (EXPERIMENTAL)\n");
+		//log("        - ecp3: LatticeECP3 (EXPERIMENTAL)\n");
+		//log("        - lifmd: LIFMD (EXPERIMENTAL)\n");
+		//log("        - lifmdf: LIFMDF (EXPERIMENTAL)\n");
+		log("\n");
+		log("    -edif <file>\n");
+		log("        write the design to the specified EDIF file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -json <file>\n");
+		log("        write the design to the specified JSON file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -run <from_label>:<to_label>\n");
+		log("        only run the commands between the labels (see below). an empty\n");
+		log("        from label is synonymous to 'begin', and empty to label is\n");
+		log("        synonymous to the end of the command list.\n");
+		log("\n");
+		log("    -noflatten\n");
+		log("        do not flatten design before synthesis\n");
+		log("\n");
+		log("    -dff\n");
+		log("        run 'abc'/'abc9' with -dff option\n");
+		log("\n");
+		log("    -retime\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
+		log("\n");
+		log("    -noccu2\n");
+		log("        do not use CCU2 cells in output netlist\n");
+		log("\n");
+		log("    -nodffe\n");
+		log("        do not use flipflops with CE in output netlist\n");
+		log("\n");
+		log("    -nobram\n");
+		log("        do not use block RAM cells in output netlist\n");
+		log("\n");
+		log("    -nolutram\n");
+		log("        do not use LUT RAM cells in output netlist\n");
+		log("\n");
+		log("    -nowidelut\n");
+		log("        do not use PFU muxes to implement LUTs larger than LUT4s\n");
+		log("        (by default enabled on MachXO2/XO3/XO3D)\n");
+		log("\n");
+		log("    -widelut\n");
+		log("        force use of PFU muxes to implement LUTs larger than LUT4s\n");
+		log("\n");
+		log("    -asyncprld\n");
+		log("        use async PRLD mode to implement ALDFF (EXPERIMENTAL)\n");
+		log("\n");
+		log("    -abc2\n");
+		log("        run two passes of 'abc' for slightly improved logic density\n");
+		log("\n");
+		log("    -abc9\n");
+		log("        use new ABC9 flow (EXPERIMENTAL)\n");
+		log("\n");
+		log("    -iopad\n");
+		log("        insert IO buffers\n");
+		log("\n");
+		log("    -nodsp\n");
+		log("        do not map multipliers to MULT18X18D\n");
+		log("\n");
+		log("    -no-rw-check\n");
+		log("        marks all recognized read ports as \"return don't-care value on\n");
+		log("        read/write collision\" (same result as setting the no_rw_check\n");
+		log("        attribute on all memories).\n");
+		log("\n");
+		log("    -cmp2softlogic\n");
+		log("        implement constant comparisons in soft logic, do not involve\n");
+		log("        hard carry chains\n");
+		log("\n");
+		log("\n");
+		log("The following commands are executed by this synthesis command:\n");
+		help_script();
+		log("\n");
+	}
+
+	string top_opt, edif_file, json_file, family;
+	bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp;
+	bool cmp2softlogic;
+	string postfix, arith_map, brams_map, dsp_map;
+
+	void clear_flags() override
+	{
+		top_opt = "-auto-top";
+		edif_file = "";
+		json_file = "";
+		family = "";
+		noccu2 = false;
+		nodffe = false;
+		nobram = false;
+		nolutram = false;
+		nowidelut = false;
+		asyncprld = false;
+		flatten = true;
+		dff = false;
+		retime = false;
+		abc2 = false;
+		abc9 = false;
+		iopad = false;
+		nodsp = false;
+		no_rw_check = false;
+		postfix = "";
+		arith_map = "";
+		brams_map = "";
+		dsp_map = "";
+		have_dsp = false;
+		cmp2softlogic = false;
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		string run_from, run_to;
+		bool force_widelut = false;
+		clear_flags();
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-top" && argidx+1 < args.size()) {
+				top_opt = "-top " + args[++argidx];
+				continue;
+			}
+			if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
+				family = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
+				edif_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-json" && argidx+1 < args.size()) {
+				json_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-run" && argidx+1 < args.size()) {
+				size_t pos = args[argidx+1].find(':');
+				if (pos == std::string::npos)
+					break;
+				run_from = args[++argidx].substr(0, pos);
+				run_to = args[argidx].substr(pos+1);
+				continue;
+			}
+			if (args[argidx] == "-flatten") {
+				flatten = true;
+				continue;
+			}
+			if (args[argidx] == "-noflatten") {
+				flatten = false;
+				continue;
+			}
+			if (args[argidx] == "-dff") {
+				dff = true;
+				continue;
+			}
+			if (args[argidx] == "-retime") {
+				retime = true;
+				continue;
+			}
+			if (args[argidx] == "-noccu2") {
+				noccu2 = true;
+				continue;
+			}
+			if (args[argidx] == "-nodffe") {
+				nodffe = true;
+				continue;
+			}
+			if (args[argidx] == "-nobram") {
+				nobram = true;
+				continue;
+			}
+			if (args[argidx] == "-asyncprld") {
+				asyncprld = true;
+				continue;
+			}
+			if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
+				nolutram = true;
+				continue;
+			}
+			if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
+				nowidelut = true;
+				force_widelut = true;
+				continue;
+			}
+			if (args[argidx] == "-widelut") {
+				nowidelut = false;
+				force_widelut = true;
+				continue;
+			}
+			if (args[argidx] == "-abc2") {
+				abc2 = true;
+				continue;
+			}
+			if (args[argidx] == "-abc9") {
+				abc9 = true;
+				continue;
+			}
+			if (args[argidx] == "-iopad") {
+				iopad = true;
+				continue;
+			}
+			if (args[argidx] == "-nodsp") {
+				nodsp = true;
+				continue;
+			}
+			if (args[argidx] == "-no-rw-check") {
+				no_rw_check = true;
+				continue;
+			}
+			if (args[argidx] == "-cmp2softlogic") {
+				cmp2softlogic = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (family.empty())
+			log_cmd_error("Lattice family parameter must be set.\n");
+
+		if (family == "ecp5") {
+			postfix = "_ecp5";
+			arith_map = "_ccu2c";
+			brams_map = "_16kd";
+			dsp_map = "_18x18";
+			have_dsp = true;
+		} else if (family == "xo2" ||
+				family == "xo3" ||
+				family == "xo3d" /* ||
+				family == "pm2"*/) {
+			postfix = "_" + family;
+			arith_map = "_ccu2d";
+			brams_map = "_8kc";
+			have_dsp = false;
+			if (!force_widelut) nowidelut = true;
+/*		} else if (family == "xo" ||
+				family == "pm") {
+		} else if (family == "xp" ||
+				family == "xp2" ||
+				family == "ecp" ||
+				family == "sm" ||
+				family == "ecp2" ||
+				family == "ecp3" ||
+				family == "lifmd" ||
+				family == "lifmdf") {*/
+		} else
+			log_cmd_error("Invalid Lattice -family setting: '%s'.\n", family.c_str());
+
+		if (!design->full_selection())
+			log_cmd_error("This command only operates on fully selected designs!\n");
+
+		if (abc9 && retime)
+				log_cmd_error("-retime option not currently compatible with -abc9!\n");
+
+		log_header(design, "Executing SYNTH_LATTICE pass.\n");
+		log_push();
+
+		run_script(design, run_from, run_to);
+
+		log_pop();
+	}
+
+	void script() override
+	{
+		std::string no_rw_check_opt = "";
+		if (no_rw_check)
+			no_rw_check_opt = " -no-rw-check";
+		if (help_mode)
+			no_rw_check_opt = " [-no-rw-check]";
+
+		if (check_label("begin"))
+		{
+			run("read_verilog -lib -specify +/lattice/cells_sim" + postfix + ".v +/lattice/cells_bb" + postfix + ".v");
+			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+		}
+
+		if (check_label("coarse"))
+		{
+			run("proc");
+			if (flatten || help_mode)
+				run("flatten");
+			run("tribuf -logic");
+			run("deminout");
+			run("opt_expr");
+			run("opt_clean");
+			run("check");
+			run("opt -nodffe -nosdff");
+			run("fsm");
+			run("opt");
+			run("wreduce");
+			run("peepopt");
+			run("opt_clean");
+			run("share");
+			if (cmp2softlogic)
+				run("techmap -map +/cmp2softlogic.v");
+			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
+			run("opt_expr");
+			run("opt_clean");
+			if (have_dsp && !nodsp) {
+				run("techmap -map +/mul2dsp.v -map +/lattice/dsp_map" + dsp_map + ".v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2  -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
+				run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
+			}
+			if (family == "xo3" || help_mode)
+				run("booth", "(only if '-family xo3')");
+			run("alumacc");
+			run("opt");
+			run("memory -nomap" + no_rw_check_opt);
+			run("opt_clean");
+		}
+
+		if (check_label("map_ram"))
+		{
+			std::string args = "";
+			if (help_mode)
+				args += " [-no-auto-block] [-no-auto-distributed]";
+			else {
+				if (nobram)
+					args += " -no-auto-block";
+				if (nolutram)
+					args += " -no-auto-distributed";
+			}
+			run("memory_libmap -lib +/lattice/lutrams.txt -lib +/lattice/brams" + brams_map + ".txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
+			run("techmap -map +/lattice/lutrams_map.v -map +/lattice/brams_map" + brams_map + ".v");
+		}
+
+		if (check_label("map_ffram"))
+		{
+			run("opt -fast -mux_undef -undriven -fine");
+			run("memory_map");
+			run("opt -undriven -fine -mux_undef");
+		}
+
+		if (check_label("map_gates"))
+		{
+			if (noccu2)
+				run("techmap");
+			else
+				run("techmap -map +/techmap.v -map +/lattice/arith_map" + arith_map + ".v");
+			if (help_mode || iopad) {
+				run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')");
+				run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]");
+				run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]");
+			}
+			run("opt -fast");
+			if (retime || help_mode)
+				run("abc -dff -D 1", "(only if -retime)");
+		}
+
+		if (check_label("map_ffs"))
+		{
+			run("opt_clean");
+			std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
+			if (help_mode) {
+				dfflegalize_args += " [-cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r]";
+			} else if (!nodffe) {
+				dfflegalize_args += " -cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r";
+			}
+			if (help_mode) {
+				dfflegalize_args += " [-cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x] [-cell $_DLATCH_?_ x]";
+			} else if (asyncprld) {
+				dfflegalize_args += " -cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x";
+			} else {
+				dfflegalize_args += " -cell $_DLATCH_?_ x";
+			}
+			run("dfflegalize" + dfflegalize_args, "($_ALDFF_*_ only if -asyncprld, $_DLATCH_* only if not -asyncprld, $_*DFFE_* only if not -nodffe)");
+			run("opt_merge");
+			if ((abc9 && dff) || help_mode)
+				run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff)");
+			run("techmap -D NO_LUT -map +/lattice/cells_map.v");
+			run("opt_expr -undriven -mux_undef");
+			run("simplemap");
+			run("lattice_gsr");
+			run("attrmvcp -copy -attr syn_useioff");
+			run("opt_clean");
+		}
+
+		if (check_label("map_luts"))
+		{
+			if (abc2 || help_mode)
+				run("abc", "      (only if -abc2)");
+			if (!asyncprld || help_mode)
+				run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)");
+
+			if (abc9) {
+				std::string abc9_opts;
+				if (nowidelut)
+					abc9_opts += " -maxlut 4";
+				std::string k = "synth_lattice.abc9.W";
+				if (active_design && active_design->scratchpad.count(k))
+					abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
+				else
+					abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
+				if (nowidelut)
+					abc9_opts += " -maxlut 4";
+				if (dff)
+					abc9_opts += " -dff";
+				run("abc9" + abc9_opts);
+			} else {
+				std::string abc_args = " -dress";
+				if (nowidelut)
+					abc_args += " -lut 4";
+				else
+					abc_args += " -lut 4:7";
+				if (dff)
+					abc_args += " -dff";
+				run("abc" + abc_args);
+			}
+			run("clean");
+		}
+
+		if (check_label("map_cells"))
+		{
+			run("techmap -map +/lattice/cells_map.v");
+			run("opt_lut_ins -tech lattice");
+			run("clean");
+		}
+
+		if (check_label("check"))
+		{
+			run("autoname");
+			run("hierarchy -check");
+			run("stat");
+			run("check -noinit");
+			run("blackbox =A:whitebox");
+		}
+
+		if (check_label("edif"))
+		{
+			if (!edif_file.empty() || help_mode)
+				run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
+		}
+
+		if (check_label("json"))
+		{
+			if (!json_file.empty() || help_mode)
+				run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
+		}
+	}
+} SynthLatticePass;
+
+/*
+struct SynthEcp5Pass : public Pass
+{
+	SynthEcp5Pass() : Pass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		args[0] = "synth_lattice";
+		args.insert(args.begin()+1, std::string());
+		args.insert(args.begin()+1, std::string());
+		args[1] = "-family";
+		args[2] = "ecp5";
+		Pass::call(design, args);
+	}
+} SynthEcp5Pass;
+*/
+
+PRIVATE_NAMESPACE_END
diff --git a/yosys/techlibs/machxo2/Makefile.inc b/yosys/techlibs/machxo2/Makefile.inc
deleted file mode 100644
index cd4e27884fc..00000000000
--- a/yosys/techlibs/machxo2/Makefile.inc
+++ /dev/null
@@ -1,14 +0,0 @@
-
-OBJS += techlibs/machxo2/synth_machxo2.o
-
-$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/cells_io.vh))
-$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_map.v))
-$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_sim.v))
-$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_bb.v))
-
-$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/lutrams.txt))
-$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/lutrams_map.v))
-
-$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams.txt))
-$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams_map.v))
-$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/arith_map.v))
diff --git a/yosys/techlibs/machxo2/cells_bb.v b/yosys/techlibs/machxo2/cells_bb.v
deleted file mode 100644
index 3d047b1692a..00000000000
--- a/yosys/techlibs/machxo2/cells_bb.v
+++ /dev/null
@@ -1,227 +0,0 @@
-(* blackbox *)
-module EHXPLLJ (
-    input CLKI, CLKFB,
-    input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, 
-    input LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, 
-    input ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE, 
-    input PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, 
-    input PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0,
-    output CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, 
-    output PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, 
-    output DPHSRC, CLKINTFB
-);
-    parameter CLKI_DIV = 1;
-    parameter CLKFB_DIV = 1;
-    parameter CLKOP_DIV = 8;
-    parameter CLKOS_DIV = 8;
-    parameter CLKOS2_DIV = 8;
-    parameter CLKOS3_DIV = 8;
-    parameter CLKOP_ENABLE = "ENABLED";
-    parameter CLKOS_ENABLE = "ENABLED";
-    parameter CLKOS2_ENABLE = "ENABLED";
-    parameter CLKOS3_ENABLE = "ENABLED";
-    parameter VCO_BYPASS_A0 = "DISABLED";
-    parameter VCO_BYPASS_B0 = "DISABLED";
-    parameter VCO_BYPASS_C0 = "DISABLED";
-    parameter VCO_BYPASS_D0 = "DISABLED";
-    parameter CLKOP_CPHASE = 0;
-    parameter CLKOS_CPHASE = 0;
-    parameter CLKOS2_CPHASE = 0;
-    parameter CLKOS3_CPHASE = 0;
-    parameter CLKOP_FPHASE = 0;
-    parameter CLKOS_FPHASE = 0;
-    parameter CLKOS2_FPHASE = 0;
-    parameter CLKOS3_FPHASE = 0;
-    parameter FEEDBK_PATH = "CLKOP";
-    parameter FRACN_ENABLE = "DISABLED";
-    parameter FRACN_DIV = 0;
-    parameter CLKOP_TRIM_POL = "RISING";
-    parameter CLKOP_TRIM_DELAY = 0;
-    parameter CLKOS_TRIM_POL = "RISING";
-    parameter CLKOS_TRIM_DELAY = 0;
-    parameter PLL_USE_WB = "DISABLED";
-    parameter PREDIVIDER_MUXA1 = 0;
-    parameter PREDIVIDER_MUXB1 = 0;
-    parameter PREDIVIDER_MUXC1 = 0;
-    parameter PREDIVIDER_MUXD1 = 0;
-    parameter OUTDIVIDER_MUXA2 = "DIVA";
-    parameter OUTDIVIDER_MUXB2 = "DIVB";
-    parameter OUTDIVIDER_MUXC2 = "DIVC";
-    parameter OUTDIVIDER_MUXD2 = "DIVD";
-    parameter PLL_LOCK_MODE = 0;
-    parameter STDBY_ENABLE = "DISABLED";
-    parameter DPHASE_SOURCE = "DISABLED";
-    parameter PLLRST_ENA = "DISABLED";
-    parameter MRST_ENA = "DISABLED";
-    parameter DCRST_ENA = "DISABLED";
-    parameter DDRST_ENA = "DISABLED";
-    parameter INTFB_WAKE = "DISABLED";
-endmodule
-
-(* blackbox *)
-module OSCH #(
-	parameter NOM_FREQ = "2.08"
-) (
-	input STDBY,
-	output OSC,
-	output SEDSTDBY
-);
-endmodule
-
-(* blackbox *)
-module DCCA (
-	input CLKI,
-	input CE,
-	output CLKO
-);
-endmodule
-
-(* blackbox *)
-module DCMA (
-	input CLK0,
-	input CLK1,
-	input SEL,
-	output DCMOUT
-);
-endmodule
-
-(* blackbox *)
-module PDPW8KC (
-    input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
-    input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0,
-    input BE1, BE0,
-    input CEW, CLKW, CSW2, CSW1, CSW0,
-    input ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4,  ADR3,  ADR2, ADR1, ADR0,
-    input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST,
-    output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0
-);
-    parameter DATA_WIDTH_W = 18;
-    parameter DATA_WIDTH_R = 9;
-
-    parameter GSR = "ENABLED";
-
-    parameter REGMODE = "NOREG";
-
-    parameter RESETMODE = "SYNC";
-    parameter ASYNC_RESET_RELEASE = "SYNC";
-
-    parameter CSDECODE_W = "0b000";
-    parameter CSDECODE_R = "0b000";
-
-    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_DATA = "STATIC";
-
-endmodule
-
-(* blackbox *)
-module SP8KC (
-    input DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
-    input AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0,
-    input CE, OCE, CLK, WE, CS2, CS1, CS0, RST,
-    output DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0
-);
-    parameter DATA_WIDTH = 9;
-    parameter GSR = "ENABLED";
-
-    parameter REGMODE = "NOREG";
-
-    parameter RESETMODE = "SYNC";
-    parameter ASYNC_RESET_RELEASE = "SYNC";
-
-    parameter CSDECODE = "0b000";
-
-    parameter WRITEMODE = "NORMAL";
-
-    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_DATA = "STATIC";
-endmodule
-
-(* blackbox *)
-module FIFO8KB (
-    input DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17,
-    input CSW0, CSW1, CSR0, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI,
-    output DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17,
-    input EF, AEF, AFF, FF
-);
-    parameter DATA_WIDTH_W = 18;
-    parameter DATA_WIDTH_R = 18;
-
-    parameter GSR = "DISABLED";
-
-    parameter REGMODE = "NOREG";
-
-    parameter RESETMODE = "ASYNC";
-    parameter ASYNC_RESET_RELEASE = "SYNC";
-
-    parameter CSDECODE_W = "0b00";
-    parameter CSDECODE_R = "0b00";
-
-    parameter AEPOINTER    = "0b00000000000000";
-    parameter AEPOINTER1   = "0b00000000000000";
-    parameter AFPOINTER    = "0b00000000000000";
-    parameter AFPOINTER1   = "0b00000000000000";
-    parameter FULLPOINTER  = "0b00000000000000";
-    parameter FULLPOINTER1 = "0b00000000000000";
-endmodule
diff --git a/yosys/techlibs/machxo2/cells_sim.v b/yosys/techlibs/machxo2/cells_sim.v
deleted file mode 100644
index 8e0e411791c..00000000000
--- a/yosys/techlibs/machxo2/cells_sim.v
+++ /dev/null
@@ -1,385 +0,0 @@
-module LUT2(input A, B, output Z);
-    parameter [3:0] INIT = 4'h0;
-    wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];
-    assign Z =      A ?          s1[1] :         s1[0];
-endmodule
-
-module LUT4 #(
-	parameter [15:0] INIT = 0
-) (
-	input A, B, C, D,
-	output Z
-);
-	// This form of LUT propagates as few x's as possible.
-	wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
-	wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];
-	wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];
-	assign Z =      A ?          s1[1] :         s1[0];
-endmodule
-
-module TRELLIS_FF #(
-	parameter GSR = "ENABLED",
-	parameter CEMUX = "1",
-	parameter CLKMUX = "0",
-	parameter LSRMUX = "LSR",
-	parameter LSRONMUX = "LSRMUX",
-	parameter SRMODE = "LSR_OVER_CE",
-	parameter REGSET = "SET",
-	parameter REGMODE = "FF"
-) (
-	input CLK, DI, LSR, CE,
-	output reg Q
-);
-
-	wire muxce;
-	generate
-		case (CEMUX)
-			"1": assign muxce = 1'b1;
-			"0": assign muxce = 1'b0;
-			"INV": assign muxce = ~CE;
-			default: assign muxce = CE;
-		endcase
-	endgenerate
-
-	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
-	wire muxlsron = (LSRONMUX == "LSRMUX") ? muxlsr : 1'b0;
-	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
-	wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
-
-	initial Q = srval;
-
-	generate
-		if (REGMODE == "FF") begin
-			if (SRMODE == "ASYNC") begin
-				always @(posedge muxclk, posedge muxlsron)
-					if (muxlsron)
-						Q <= srval;
-					else if (muxce)
-						Q <= DI;
-			end else begin
-				always @(posedge muxclk)
-					if (muxlsron)
-						Q <= srval;
-					else if (muxce)
-						Q <= DI;
-			end
-		end else if (REGMODE == "LATCH") begin
-			ERROR_UNSUPPORTED_FF_MODE error();
-		end else begin
-			ERROR_UNKNOWN_FF_MODE error();
-		end
-	endgenerate
-endmodule
-
-/* For consistency with ECP5; represents F0/F1 => OFX0 mux in a slice. */
-module PFUMX (input ALUT, BLUT, C0, output Z);
-	assign Z = C0 ? ALUT : BLUT;
-endmodule
-
-/* For consistency with ECP5; represents FXA/FXB => OFX1 mux in a slice. */
-module L6MUX21 (input D0, D1, SD, output Z);
-	assign Z = SD ? D1 : D0;
-endmodule
-
-/* For consistency, input order matches TRELLIS_SLICE even though the BELs in
-prjtrellis were filled in clockwise order from bottom left. */
-module TRELLIS_SLICE #(
-	parameter MODE = "LOGIC",
-	parameter GSR = "ENABLED",
-	parameter SRMODE = "LSR_OVER_CE",
-	parameter CEMUX = "1",
-	parameter CLKMUX = "0",
-	parameter LSRMUX = "LSR",
-	parameter LSRONMUX = "LSRMUX",
-	parameter LUT0_INITVAL = 16'hFFFF,
-	parameter LUT1_INITVAL = 16'hFFFF,
-	parameter REGMODE = "FF",
-	parameter REG0_SD = "1",
-	parameter REG1_SD = "1",
-	parameter REG0_REGSET = "SET",
-	parameter REG1_REGSET = "SET",
-	parameter CCU2_INJECT1_0 = "YES",
-	parameter CCU2_INJECT1_1 = "YES",
-	parameter WREMUX = "INV"
-) (
-	input A0, B0, C0, D0,
-	input A1, B1, C1, D1,
-	input M0, M1,
-	input FCI, FXA, FXB,
-
-	input CLK, LSR, CE,
-	input DI0, DI1,
-
-	input WD0, WD1,
-	input WAD0, WAD1, WAD2, WAD3,
-	input WRE, WCK,
-
-	output F0, Q0,
-	output F1, Q1,
-	output FCO, OFX0, OFX1,
-
-	output WDO0, WDO1, WDO2, WDO3,
-	output WADO0, WADO1, WADO2, WADO3
-);
-
-	generate
-		if (MODE == "LOGIC") begin
-			L6MUX21 FXMUX (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
-
-			wire k0;
-			wire k1;
-			PFUMX K0K1MUX (.ALUT(k1), .BLUT(k0), .C0(M0), .Z(OFX0));
-
-			LUT4 #(.INIT(LUT0_INITVAL)) LUT_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k0));
-			LUT4 #(.INIT(LUT1_INITVAL)) LUT_1 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k1));
-
-			assign F0 = k0;
-			assign F1 = k1;
-		end else if (MODE == "CCU2") begin
-			ERROR_UNSUPPORTED_SLICE_MODE error();
-		end else if (MODE == "DPRAM") begin
-			ERROR_UNSUPPORTED_SLICE_MODE error();
-		end else begin
-			ERROR_UNKNOWN_SLICE_MODE error();
-		end
-	endgenerate
-
-	/* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F
-	outputs (in other words, feeds back into TRELLIS_SLICE). */
-	wire di0 = (REG0_SD == "1") ? DI0 : M0;
-	wire di1 = (REG1_SD == "1") ? DI1 : M1;
-
-	TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
-		.LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET),
-		.REGMODE(REGMODE)) REG_0 (.CLK(CLK), .DI(di0), .LSR(LSR), .CE(CE), .Q(Q0));
-	TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
-		.LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET),
-		.REGMODE(REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1));
-endmodule
-
-module TRELLIS_IO #(
-	parameter DIR = "INPUT"
-) (
-	(* iopad_external_pin *)
-	inout B,
-	input I, T,
-	output O
-);
-	generate
-		if (DIR == "INPUT") begin
-			assign O = B;
-		end else if (DIR == "OUTPUT") begin
-			assign B = T ? 1'bz : I;
-		end else if (DIR == "BIDIR") begin
-			assign B = T ? 1'bz : I;
-			assign O = B;
-		end else begin
-			ERROR_UNKNOWN_IO_MODE error();
-		end
-	endgenerate
-endmodule
-
-(* abc9_box, lib_whitebox *)
-module TRELLIS_DPR16X4 (
-	input  [3:0] DI,
-	input  [3:0] WAD,
-	input        WRE,
-	input        WCK,
-	input  [3:0] RAD,
-	output [3:0] DO
-);
-	parameter WCKMUX = "WCK";
-	parameter WREMUX = "WRE";
-	parameter [63:0] INITVAL = 64'h0000000000000000;
-
-	reg [3:0] mem[15:0];
-
-	integer i;
-	initial begin
-		for (i = 0; i < 16; i = i + 1)
-			mem[i] <= INITVAL[4*i +: 4];
-	end
-
-	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
-
-	reg muxwre;
-	always @(*)
-		case (WREMUX)
-			"1": muxwre = 1'b1;
-			"0": muxwre = 1'b0;
-			"INV": muxwre = ~WRE;
-			default: muxwre = WRE;
-		endcase
-
-	always @(posedge muxwck)
-		if (muxwre)
-			mem[WAD] <= DI;
-
-	assign DO = mem[RAD];
-
-	specify
-		// TODO
-		(RAD *> DO) = 0;
-	endspecify
-endmodule
-
-(* abc9_box, lib_whitebox *)
-module DPR16X4C (
-		input [3:0] DI,
-		input WCK, WRE,
-		input [3:0] RAD,
-		input [3:0] WAD,
-		output [3:0] DO
-);
-	parameter INITVAL = "0x0000000000000000";
-
-	function [63:0] convert_initval;
-		input [143:0] hex_initval;
-		reg done;
-		reg [63:0] temp;
-		reg [7:0] char;
-		integer i;
-		begin
-			done = 1'b0;
-			temp = 0;
-			for (i = 0; i < 16; i = i + 1) begin
-				if (!done) begin
-					char = hex_initval[8*i +: 8];
-					if (char == "x") begin
-						done = 1'b1;
-					end else begin
-						if (char >= "0" && char <= "9")
-							temp[4*i +: 4] = char - "0";
-						else if (char >= "A" && char <= "F")
-							temp[4*i +: 4] = 10 + char - "A";
-						else if (char >= "a" && char <= "f")
-							temp[4*i +: 4] = 10 + char - "a";
-					end
-				end
-			end
-			convert_initval = temp;
-		end
-	endfunction
-
-	localparam conv_initval = convert_initval(INITVAL);
-
-	reg [3:0] ram[0:15];
-	integer i;
-	initial begin
-		for (i = 0; i < 15; i = i + 1) begin
-			ram[i] <= conv_initval[4*i +: 4];
-		end
-	end
-
-	always @(posedge WCK)
-		if (WRE)
-			ram[WAD] <= DI;
-
-	assign DO = ram[RAD];
-endmodule
-
-// ---------------------------------------
-(* lib_whitebox *)
-module CCU2D (
-	input  CIN,
-	input  A0, B0, C0, D0, A1, B1, C1, D1,
-	output S0, S1,
-	output COUT
-);
-	parameter [15:0] INIT0 = 16'h0000;
-	parameter [15:0] INIT1 = 16'h0000;
-	parameter INJECT1_0 = "YES";
-	parameter INJECT1_1 = "YES";
-
-	// First half
-	wire LUT4_0, LUT2_0;
-	LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
-	LUT2 #(.INIT(~INIT0[15:12])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
-	wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
-	assign S0 = LUT4_0 ^ gated_cin_0;
-
-	wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
-	wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
-
-	// Second half
-	wire LUT4_1, LUT2_1;
-	LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
-	LUT2 #(.INIT(~INIT1[15:12])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
-	wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
-	assign S1 = LUT4_1 ^ gated_cin_1;
-
-	wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
-	assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
-endmodule
-
-(* blackbox *)
-module DP8KC(
-  input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
-  input ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
-  input CEA, OCEA, CLKA, WEA, RSTA,
-  input CSA2, CSA1, CSA0,
-  output DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
-
-  input DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
-  input ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
-  input CEB, OCEB, CLKB, WEB, RSTB,
-  input CSB2, CSB1, CSB0,
-  output DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
-);
-	parameter DATA_WIDTH_A = 9;
-	parameter DATA_WIDTH_B = 9;
-
-	parameter REGMODE_A = "NOREG";
-	parameter REGMODE_B = "NOREG";
-
-	parameter RESETMODE = "SYNC";
-	parameter ASYNC_RESET_RELEASE = "SYNC";
-
-	parameter CSDECODE_A = "0b000";
-	parameter CSDECODE_B = "0b000";
-
-	parameter WRITEMODE_A = "NORMAL";
-	parameter WRITEMODE_B = "NORMAL";
-
-	parameter GSR = "ENABLED";
-	parameter INIT_DATA = "STATIC";
-
-	parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-	parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-endmodule
-
-`ifndef NO_INCLUDES
-
-`include "cells_io.vh"
-
-`endif
diff --git a/yosys/techlibs/machxo2/lutrams_map.v b/yosys/techlibs/machxo2/lutrams_map.v
deleted file mode 100644
index b55253fb868..00000000000
--- a/yosys/techlibs/machxo2/lutrams_map.v
+++ /dev/null
@@ -1,23 +0,0 @@
-module $__DPR16X4C_ (...);
-	parameter INIT = 64'b0;
-
-	input PORT_W_CLK;
-	input [3:0] PORT_W_ADDR;
-	input [3:0] PORT_W_WR_DATA;
-	input PORT_W_WR_EN;
-
-	input [3:0] PORT_R_ADDR;
-	output [3:0] PORT_R_RD_DATA;
-
-	DPR16X4C #(
-		.INITVAL($sformatf("0x%08x", INIT))
-	) _TECHMAP_REPLACE_ (
-		.RAD(PORT_R_ADDR),
-		.DO(PORT_R_RD_DATA),
-
-		.WAD(PORT_W_ADDR),
-		.DI(PORT_W_WR_DATA),
-		.WCK(PORT_W_CLK),
-		.WRE(PORT_W_WR_EN)
-	);
-endmodule
diff --git a/yosys/techlibs/machxo2/synth_machxo2.cc b/yosys/techlibs/machxo2/synth_machxo2.cc
deleted file mode 100644
index 2b684a7d8fd..00000000000
--- a/yosys/techlibs/machxo2/synth_machxo2.cc
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2020 William D. Jones <wjones@wdj-consulting.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/register.h"
-#include "kernel/celltypes.h"
-#include "kernel/rtlil.h"
-#include "kernel/log.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-struct SynthMachXO2Pass : public ScriptPass
-{
-	SynthMachXO2Pass() : ScriptPass("synth_machxo2", "synthesis for MachXO2 FPGAs. This work is experimental.") { }
-
-	void help() override
-	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-		log("    synth_machxo2 [options]\n");
-		log("\n");
-		log("This command runs synthesis for MachXO2 FPGAs.\n");
-		log("\n");
-		log("    -top <module>\n");
-		log("        use the specified module as top module\n");
-		log("\n");
-		log("    -blif <file>\n");
-		log("        write the design to the specified BLIF file. writing of an output file\n");
-		log("        is omitted if this parameter is not specified.\n");
-		log("\n");
-		log("    -edif <file>\n");
-		log("        write the design to the specified EDIF file. writing of an output file\n");
-		log("        is omitted if this parameter is not specified.\n");
-		log("\n");
-		log("    -json <file>\n");
-		log("        write the design to the specified JSON file. writing of an output file\n");
-		log("        is omitted if this parameter is not specified.\n");
-		log("\n");
-		log("    -run <from_label>:<to_label>\n");
-		log("        only run the commands between the labels (see below). an empty\n");
-		log("        from label is synonymous to 'begin', and empty to label is\n");
-		log("        synonymous to the end of the command list.\n");
-		log("\n");
-		log("    -nobram\n");
-		log("        do not use block RAM cells in output netlist\n");
-		log("\n");
-		log("    -nolutram\n");
-		log("        do not use LUT RAM cells in output netlist\n");
-		log("\n");
-		log("    -noflatten\n");
-		log("        do not flatten design before synthesis\n");
-		log("\n");
-		log("    -noiopad\n");
-		log("        do not insert IO buffers\n");
-		log("\n");
-		log("    -ccu2\n");
-		log("        use CCU2 cells in output netlist\n");
-		log("\n");
-		log("    -vpr\n");
-		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
-		log("        (this feature is experimental and incomplete)\n");
-		log("\n");
-		log("\n");
-		log("The following commands are executed by this synthesis command:\n");
-		help_script();
-		log("\n");
-	}
-
-	string top_opt, blif_file, edif_file, json_file;
-	bool ccu2, nobram, nolutram, flatten, vpr, noiopad;
-
-	void clear_flags() override
-	{
-		top_opt = "-auto-top";
-		blif_file = "";
-		edif_file = "";
-		json_file = "";
-		ccu2 = false;
-		nobram = false;
-		nolutram = false;
-		flatten = true;
-		vpr = false;
-		noiopad = false;
-	}
-
-	void execute(std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		string run_from, run_to;
-		clear_flags();
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			if (args[argidx] == "-top" && argidx+1 < args.size()) {
-				top_opt = "-top " + args[++argidx];
-				continue;
-			}
-			if (args[argidx] == "-blif" && argidx+1 < args.size()) {
-				blif_file = args[++argidx];
-				continue;
-			}
-			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
-				edif_file = args[++argidx];
-				continue;
-			}
-			if (args[argidx] == "-json" && argidx+1 < args.size()) {
-				json_file = args[++argidx];
-				continue;
-			}
-			if (args[argidx] == "-run" && argidx+1 < args.size()) {
-				size_t pos = args[argidx+1].find(':');
-				if (pos == std::string::npos)
-					break;
-				run_from = args[++argidx].substr(0, pos);
-				run_to = args[argidx].substr(pos+1);
-				continue;
-			}
-			if (args[argidx] == "-flatten") {
-				flatten = true;
-				continue;
-			}
-			if (args[argidx] == "-noflatten") {
-				flatten = false;
-				continue;
-			}
-			if (args[argidx] == "-nobram") {
-				nobram = true;
-				continue;
-			}
-			if (args[argidx] == "-nolutram") {
-				nolutram = true;
-				continue;
-			}
-			if (args[argidx] == "-noiopad") {
-				noiopad = true;
-				continue;
-			}
-			if (args[argidx] == "-ccu2") {
-				ccu2 = true;
-				continue;
-			}
-			if (args[argidx] == "-vpr") {
-				vpr = true;
-				continue;
-			}
-			break;
-		}
-		extra_args(args, argidx, design);
-
-		if (!design->full_selection())
-			log_cmd_error("This command only operates on fully selected designs!\n");
-
-		log_header(design, "Executing SYNTH_MACHXO2 pass.\n");
-		log_push();
-
-		run_script(design, run_from, run_to);
-
-		log_pop();
-	}
-
-	void script() override
-	{
-		if (check_label("begin"))
-		{
-			run("read_verilog -lib -icells +/machxo2/cells_sim.v +/machxo2/cells_bb.v");
-			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
-		}
-
-		if (check_label("flatten", "(unless -noflatten)"))
-		{
-			if (flatten || help_mode) {
-				run("proc");
-				run("flatten");
-				run("tribuf -logic");
-				run("deminout");
-			}
-		}
-
-		if (check_label("coarse"))
-		{
-			run("synth -run coarse");
-		}
-
-		if (check_label("map_ram"))
-		{
-			std::string args = "";
-			if (nobram)
-				args += " -no-auto-block";
-			if (nolutram)
-				args += " -no-auto-distributed";
-			if (help_mode)
-				args += " [-no-auto-block] [-no-auto-distributed]";
-			run("memory_libmap -lib +/machxo2/lutrams.txt -lib +/machxo2/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
-			run("techmap -map +/machxo2/lutrams_map.v -map +/machxo2/brams_map.v");
-		}
-
-		if (check_label("fine"))
-		{
-			run("opt -fast -mux_undef -undriven -fine");
-			run("memory_map");
-			run("opt -undriven -fine");
-		}
-
-		if (check_label("map_gates", "(unless -noiopad)"))
-		{
-			if (!ccu2)
-				run("techmap");
-			else
-				run("techmap -map +/techmap.v -map +/machxo2/arith_map.v");
-			if (!noiopad || help_mode)
-			{
-				run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')");
-				run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]");
-				run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]");
-			}
-		}
-
-		if (check_label("map_ffs"))
-		{
-			run("opt_clean");
-			std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
-			run("dfflegalize" + dfflegalize_args);
-			run("techmap -D NO_LUT -map +/machxo2/cells_map.v");
-			run("opt_expr -undriven -mux_undef");
-			run("simplemap");
-			run("ecp5_gsr");
-			run("attrmvcp -copy -attr syn_useioff");
-			run("opt_clean");
-		}
-
-		if (check_label("map_luts"))
-		{
-			run("abc -lut 4 -dress");
-			run("clean");
-		}
-
-		if (check_label("map_cells"))
-		{
-			run("techmap -map +/machxo2/cells_map.v");
-			run("clean");
-		}
-
-		if (check_label("check"))
-		{
-			run("hierarchy -check");
-			run("stat");
-			run("blackbox =A:whitebox");
-		}
-
-		if (check_label("blif"))
-		{
-			if (!blif_file.empty() || help_mode) {
-				if (vpr || help_mode) {
-					run(stringf("opt_clean -purge"),
-							"                                 (vpr mode)");
-					run(stringf("write_blif -attr -cname -conn -param %s",
-							help_mode ? "<file-name>" : blif_file.c_str()),
-							" (vpr mode)");
-				}
-				if (!vpr)
-					run(stringf("write_blif -gates -attr -param %s",
-							help_mode ? "<file-name>" : blif_file.c_str()),
-							"       (non-vpr mode)");
-			}
-		}
-
-		if (check_label("edif"))
-		{
-			if (!edif_file.empty() || help_mode)
-				run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
-		}
-
-		if (check_label("json"))
-		{
-			if (!json_file.empty() || help_mode)
-				run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
-		}
-	}
-} SynthMachXO2Pass;
-
-PRIVATE_NAMESPACE_END
diff --git a/yosys/techlibs/nexus/brams_map.v b/yosys/techlibs/nexus/brams_map.v
index cec56cec4ab..dbcee5c41c7 100644
--- a/yosys/techlibs/nexus/brams_map.v
+++ b/yosys/techlibs/nexus/brams_map.v
@@ -134,8 +134,8 @@ DP16K #(
 	.INITVAL_3D($sformatf("0x%080x", init_slice('h3d))),
 	.INITVAL_3E($sformatf("0x%080x", init_slice('h3e))),
 	.INITVAL_3F($sformatf("0x%080x", init_slice('h3f))),
-	.DATA_WIDTH_A($sformatf("X%d", PORT_A_WIDTH)),
-	.DATA_WIDTH_B($sformatf("X%d", PORT_B_WIDTH)),
+	.DATA_WIDTH_A($sformatf("X%0d", PORT_A_WIDTH)),
+	.DATA_WIDTH_B($sformatf("X%0d", PORT_B_WIDTH)),
 	.OUTREG_A("BYPASSED"),
 	.OUTREG_B("BYPASSED"),
 	.RESETMODE_A(PORT_A_OPTION_RESETMODE),
@@ -298,8 +298,8 @@ PDPSC16K #(
 	.INITVAL_3D($sformatf("0x%080x", init_slice('h3d))),
 	.INITVAL_3E($sformatf("0x%080x", init_slice('h3e))),
 	.INITVAL_3F($sformatf("0x%080x", init_slice('h3f))),
-	.DATA_WIDTH_W($sformatf("X%d", PORT_W_WIDTH)),
-	.DATA_WIDTH_R($sformatf("X%d", PORT_R_WIDTH)),
+	.DATA_WIDTH_W($sformatf("X%0d", PORT_W_WIDTH)),
+	.DATA_WIDTH_R($sformatf("X%0d", PORT_R_WIDTH)),
 	.OUTREG("BYPASSED"),
 	.RESETMODE(PORT_R_OPTION_RESETMODE),
 	.ASYNC_RST_RELEASE(PORT_R_OPTION_RESETMODE),
@@ -389,8 +389,8 @@ PDP16K #(
 	.INITVAL_3D($sformatf("0x%080x", init_slice('h3d))),
 	.INITVAL_3E($sformatf("0x%080x", init_slice('h3e))),
 	.INITVAL_3F($sformatf("0x%080x", init_slice('h3f))),
-	.DATA_WIDTH_W($sformatf("X%d", PORT_W_WIDTH)),
-	.DATA_WIDTH_R($sformatf("X%d", PORT_R_WIDTH)),
+	.DATA_WIDTH_W($sformatf("X%0d", PORT_W_WIDTH)),
+	.DATA_WIDTH_R($sformatf("X%0d", PORT_R_WIDTH)),
 	.OUTREG("BYPASSED"),
 	.RESETMODE(PORT_R_OPTION_RESETMODE),
 	.ASYNC_RST_RELEASE(PORT_R_OPTION_RESETMODE),
diff --git a/yosys/techlibs/nexus/synth_nexus.cc b/yosys/techlibs/nexus/synth_nexus.cc
index 6fd15ba5577..2935fbd3bca 100644
--- a/yosys/techlibs/nexus/synth_nexus.cc
+++ b/yosys/techlibs/nexus/synth_nexus.cc
@@ -300,12 +300,14 @@ struct SynthNexusPass : public ScriptPass
 		{
 			std::string args = "";
 			args += " -no-auto-huge";
-			if (nobram)
-				args += " -no-auto-block";
-			if (nolutram)
-				args += " -no-auto-distributed";
 			if (help_mode)
 				args += " [-no-auto-block] [-no-auto-distributed]";
+			else {
+				if (nobram)
+					args += " -no-auto-block";
+				if (nolutram)
+					args += " -no-auto-distributed";
+			}
 			run("memory_libmap -lib +/nexus/lutrams.txt -lib +/nexus/brams.txt -lib +/nexus/lrams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
 			run("techmap -map +/nexus/lutrams_map.v -map +/nexus/brams_map.v -map +/nexus/lrams_map.v");
 		}
diff --git a/yosys/techlibs/quicklogic/.gitignore b/yosys/techlibs/quicklogic/.gitignore
new file mode 100644
index 00000000000..e52f3282f7f
--- /dev/null
+++ b/yosys/techlibs/quicklogic/.gitignore
@@ -0,0 +1 @@
+/*_pm.h
diff --git a/yosys/techlibs/quicklogic/Makefile.inc b/yosys/techlibs/quicklogic/Makefile.inc
index 51eb28d44bd..ade1443713c 100644
--- a/yosys/techlibs/quicklogic/Makefile.inc
+++ b/yosys/techlibs/quicklogic/Makefile.inc
@@ -1,13 +1,43 @@
+techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v: techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py
+	$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $^ $@
+
 OBJS += techlibs/quicklogic/synth_quicklogic.o
+OBJS += techlibs/quicklogic/ql_bram_merge.o
+OBJS += techlibs/quicklogic/ql_bram_types.o
+OBJS += techlibs/quicklogic/ql_dsp_simd.o
+OBJS += techlibs/quicklogic/ql_dsp_io_regs.o
+
+# --------------------------------------
+
+OBJS += techlibs/quicklogic/ql_dsp_macc.o
+GENFILES += techlibs/quicklogic/ql_dsp_macc_pm.h techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v
+techlibs/quicklogic/ql_dsp_macc.o: techlibs/quicklogic/ql_dsp_macc_pm.h
+$(eval $(call add_extra_objs,techlibs/quicklogic/ql_dsp_macc_pm.h))
+
+# --------------------------------------
+
+$(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v))
+
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/ffs_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/lut_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/latches_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_sim.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_model.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_map.v))
+$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_unmap.v))
 
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_ffs_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_lut_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_latches_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/cells_sim.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/lut_sim.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_sim.v))
-
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_model.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_map.v))
-$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_unmap.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/arith_map.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_map.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v))
+$(eval $(call add_gen_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_sim.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_map.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v))
+$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v))
\ No newline at end of file
diff --git a/yosys/techlibs/quicklogic/cells_sim.v b/yosys/techlibs/quicklogic/common/cells_sim.v
similarity index 100%
rename from yosys/techlibs/quicklogic/cells_sim.v
rename to yosys/techlibs/quicklogic/common/cells_sim.v
diff --git a/yosys/techlibs/quicklogic/lut_sim.v b/yosys/techlibs/quicklogic/lut_sim.v
deleted file mode 100644
index 851ce4d6845..00000000000
--- a/yosys/techlibs/quicklogic/lut_sim.v
+++ /dev/null
@@ -1,76 +0,0 @@
-(* abc9_lut=1, lib_whitebox *)
-module LUT1 (
-  output O,
-  input I0
-);
-  parameter [1:0] INIT = 0;
-  parameter EQN = "(I0)";
-
-  // These timings are for PolarPro 3E; other families will need updating.
-  specify
-    (I0 => O) = 698; // FS -> FZ
-  endspecify
-
-  assign O = I0 ? INIT[1] : INIT[0];
-endmodule
-
-//               TZ        TSL TAB
-(* abc9_lut=2, lib_whitebox *)
-module LUT2 (
-  output O,
-  input I0, I1
-);
-  parameter [3:0] INIT = 4'h0;
-  parameter EQN = "(I0)";
-
-  // These timings are for PolarPro 3E; other families will need updating.
-  specify
-    (I0 => O) = 1251; // TAB -> TZ
-    (I1 => O) = 1406; // TSL -> TZ
-  endspecify
-
-  wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0];
-  assign O = I0 ? s1[1] : s1[0];
-endmodule
-
-(* abc9_lut=2, lib_whitebox *)
-module LUT3 (
-  output O,
-  input I0, I1, I2
-);
-  parameter [7:0] INIT = 8'h0;
-  parameter EQN = "(I0)";
-
-  // These timings are for PolarPro 3E; other families will need updating.
-  specify
-    (I0 => O) = 1251; // TAB -> TZ
-    (I1 => O) = 1406; // TSL -> TZ
-    (I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ
-  endspecify
-
-  wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];
-  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
-  assign O = I0 ? s1[1] : s1[0];
-endmodule
-
-(* abc9_lut=4, lib_whitebox *)
-module LUT4 (
-  output O,
-  input I0, I1, I2, I3
-);
-  parameter [15:0] INIT = 16'h0;
-  parameter EQN = "(I0)";
-
-  // These timings are for PolarPro 3E; other families will need updating.
-  specify
-    (I0 => O) = 995;  // TBS -> CZ
-    (I1 => O) = 1437; // ('TAB', 'BAB') -> CZ
-    (I2 => O) = 1593; // ('TSL', 'BSL') -> CZ
-    (I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ
-  endspecify
-
-  wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
-  wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];
-  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
-  assign O = I0 ? s1[1] : s1[0];
-endmodule
diff --git a/yosys/techlibs/quicklogic/abc9_map.v b/yosys/techlibs/quicklogic/pp3/abc9_map.v
similarity index 100%
rename from yosys/techlibs/quicklogic/abc9_map.v
rename to yosys/techlibs/quicklogic/pp3/abc9_map.v
diff --git a/yosys/techlibs/quicklogic/abc9_model.v b/yosys/techlibs/quicklogic/pp3/abc9_model.v
similarity index 100%
rename from yosys/techlibs/quicklogic/abc9_model.v
rename to yosys/techlibs/quicklogic/pp3/abc9_model.v
diff --git a/yosys/techlibs/quicklogic/abc9_unmap.v b/yosys/techlibs/quicklogic/pp3/abc9_unmap.v
similarity index 100%
rename from yosys/techlibs/quicklogic/abc9_unmap.v
rename to yosys/techlibs/quicklogic/pp3/abc9_unmap.v
diff --git a/yosys/techlibs/quicklogic/pp3_cells_map.v b/yosys/techlibs/quicklogic/pp3/cells_map.v
similarity index 100%
rename from yosys/techlibs/quicklogic/pp3_cells_map.v
rename to yosys/techlibs/quicklogic/pp3/cells_map.v
diff --git a/yosys/techlibs/quicklogic/pp3_cells_sim.v b/yosys/techlibs/quicklogic/pp3/cells_sim.v
similarity index 76%
rename from yosys/techlibs/quicklogic/pp3_cells_sim.v
rename to yosys/techlibs/quicklogic/pp3/cells_sim.v
index 5820d7a9ec0..201a7d33331 100644
--- a/yosys/techlibs/quicklogic/pp3_cells_sim.v
+++ b/yosys/techlibs/quicklogic/pp3/cells_sim.v
@@ -327,3 +327,80 @@ module qlal4s3b_cell_macro (
 );
 
 endmodule
+
+(* abc9_lut=1, lib_whitebox *)
+module LUT1 (
+  output O,
+  input I0
+);
+  parameter [1:0] INIT = 0;
+  parameter EQN = "(I0)";
+
+  // These timings are for PolarPro 3E; other families will need updating.
+  specify
+    (I0 => O) = 698; // FS -> FZ
+  endspecify
+
+  assign O = I0 ? INIT[1] : INIT[0];
+endmodule
+
+//               TZ        TSL TAB
+(* abc9_lut=2, lib_whitebox *)
+module LUT2 (
+  output O,
+  input I0, I1
+);
+  parameter [3:0] INIT = 4'h0;
+  parameter EQN = "(I0)";
+
+  // These timings are for PolarPro 3E; other families will need updating.
+  specify
+    (I0 => O) = 1251; // TAB -> TZ
+    (I1 => O) = 1406; // TSL -> TZ
+  endspecify
+
+  wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0];
+  assign O = I0 ? s1[1] : s1[0];
+endmodule
+
+(* abc9_lut=2, lib_whitebox *)
+module LUT3 (
+  output O,
+  input I0, I1, I2
+);
+  parameter [7:0] INIT = 8'h0;
+  parameter EQN = "(I0)";
+
+  // These timings are for PolarPro 3E; other families will need updating.
+  specify
+    (I0 => O) = 1251; // TAB -> TZ
+    (I1 => O) = 1406; // TSL -> TZ
+    (I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ
+  endspecify
+
+  wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];
+  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
+  assign O = I0 ? s1[1] : s1[0];
+endmodule
+
+(* abc9_lut=4, lib_whitebox *)
+module LUT4 (
+  output O,
+  input I0, I1, I2, I3
+);
+  parameter [15:0] INIT = 16'h0;
+  parameter EQN = "(I0)";
+
+  // These timings are for PolarPro 3E; other families will need updating.
+  specify
+    (I0 => O) = 995;  // TBS -> CZ
+    (I1 => O) = 1437; // ('TAB', 'BAB') -> CZ
+    (I2 => O) = 1593; // ('TSL', 'BSL') -> CZ
+    (I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ
+  endspecify
+
+  wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
+  wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];
+  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
+  assign O = I0 ? s1[1] : s1[0];
+endmodule
diff --git a/yosys/techlibs/quicklogic/pp3_ffs_map.v b/yosys/techlibs/quicklogic/pp3/ffs_map.v
similarity index 100%
rename from yosys/techlibs/quicklogic/pp3_ffs_map.v
rename to yosys/techlibs/quicklogic/pp3/ffs_map.v
diff --git a/yosys/techlibs/quicklogic/pp3_latches_map.v b/yosys/techlibs/quicklogic/pp3/latches_map.v
similarity index 100%
rename from yosys/techlibs/quicklogic/pp3_latches_map.v
rename to yosys/techlibs/quicklogic/pp3/latches_map.v
diff --git a/yosys/techlibs/quicklogic/pp3_lut_map.v b/yosys/techlibs/quicklogic/pp3/lut_map.v
similarity index 100%
rename from yosys/techlibs/quicklogic/pp3_lut_map.v
rename to yosys/techlibs/quicklogic/pp3/lut_map.v
diff --git a/yosys/techlibs/quicklogic/ql_bram_merge.cc b/yosys/techlibs/quicklogic/ql_bram_merge.cc
new file mode 100644
index 00000000000..bed1ba572df
--- /dev/null
+++ b/yosys/techlibs/quicklogic/ql_bram_merge.cc
@@ -0,0 +1,216 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2023  N. Engelhardt <nak@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/log.h"
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+// ============================================================================
+
+
+
+struct QlBramMergeWorker {
+
+	// can be used to record parameter values that have to match on both sides
+	typedef dict<RTLIL::IdString, RTLIL::Const> MergeableGroupKeyType;
+
+	RTLIL::Module *module;
+	dict<MergeableGroupKeyType, pool<RTLIL::Cell*>> mergeable_groups;
+
+	QlBramMergeWorker(RTLIL::Module* module) : module(module)
+	{
+		const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K);
+
+		for (RTLIL::Cell* cell : module->selected_cells())
+		{
+			if(cell->type != split_cell_type) continue;
+			if(!cell->hasParam(ID(OPTION_SPLIT))) continue;
+			if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue;
+			mergeable_groups[get_key(cell)].insert(cell);
+		}
+	}
+
+	static MergeableGroupKeyType get_key(RTLIL::Cell* cell)
+	{
+		MergeableGroupKeyType key;
+		// For now, there are no restrictions on which cells can be merged
+		(void) cell;
+		return key;
+	}
+
+	const dict<RTLIL::IdString, RTLIL::IdString>& param_map(bool second)
+	{
+		static const dict<RTLIL::IdString, RTLIL::IdString> bram1_map = {
+			{ ID(INIT),                     ID(INIT1) },
+			{ ID(PORT_A_WIDTH),             ID(PORT_A1_WIDTH) },
+			{ ID(PORT_B_WIDTH),             ID(PORT_B1_WIDTH) },
+			{ ID(PORT_A_WR_BE_WIDTH),       ID(PORT_A1_WR_BE_WIDTH) },
+			{ ID(PORT_B_WR_BE_WIDTH),       ID(PORT_B1_WR_BE_WIDTH) }
+		};
+		static const dict<RTLIL::IdString, RTLIL::IdString> bram2_map = {
+			{ ID(INIT),                     ID(INIT2) },
+			{ ID(PORT_A_WIDTH),             ID(PORT_A2_WIDTH) },
+			{ ID(PORT_B_WIDTH),             ID(PORT_B2_WIDTH) },
+			{ ID(PORT_A_WR_BE_WIDTH),       ID(PORT_A2_WR_BE_WIDTH) },
+			{ ID(PORT_B_WR_BE_WIDTH),       ID(PORT_B2_WR_BE_WIDTH) }
+		};
+
+		if(second)
+			return bram2_map;
+		else
+			return bram1_map;
+	}
+
+	const dict<RTLIL::IdString, RTLIL::IdString>& port_map(bool second)
+	{
+		static const dict<RTLIL::IdString, RTLIL::IdString> bram1_map = {
+			{ ID(PORT_A_CLK),       ID(PORT_A1_CLK) },
+			{ ID(PORT_B_CLK),       ID(PORT_B1_CLK) },
+			{ ID(PORT_A_CLK_EN),    ID(PORT_A1_CLK_EN) },
+			{ ID(PORT_B_CLK_EN),    ID(PORT_B1_CLK_EN) },
+			{ ID(PORT_A_ADDR),      ID(PORT_A1_ADDR) },
+			{ ID(PORT_B_ADDR),      ID(PORT_B1_ADDR) },
+			{ ID(PORT_A_WR_DATA),   ID(PORT_A1_WR_DATA) },
+			{ ID(PORT_B_WR_DATA),   ID(PORT_B1_WR_DATA) },
+			{ ID(PORT_A_WR_EN),     ID(PORT_A1_WR_EN) },
+			{ ID(PORT_B_WR_EN),     ID(PORT_B1_WR_EN) },
+			{ ID(PORT_A_WR_BE),     ID(PORT_A1_WR_BE) },
+			{ ID(PORT_B_WR_BE),     ID(PORT_B1_WR_BE) },
+			{ ID(PORT_A_RD_DATA),   ID(PORT_A1_RD_DATA) },
+			{ ID(PORT_B_RD_DATA),   ID(PORT_B1_RD_DATA) }
+		};
+		static const dict<RTLIL::IdString, RTLIL::IdString> bram2_map = {
+			{ ID(PORT_A_CLK),       ID(PORT_A2_CLK) },
+			{ ID(PORT_B_CLK),       ID(PORT_B2_CLK) },
+			{ ID(PORT_A_CLK_EN),    ID(PORT_A2_CLK_EN) },
+			{ ID(PORT_B_CLK_EN),    ID(PORT_B2_CLK_EN) },
+			{ ID(PORT_A_ADDR),      ID(PORT_A2_ADDR) },
+			{ ID(PORT_B_ADDR),      ID(PORT_B2_ADDR) },
+			{ ID(PORT_A_WR_DATA),   ID(PORT_A2_WR_DATA) },
+			{ ID(PORT_B_WR_DATA),   ID(PORT_B2_WR_DATA) },
+			{ ID(PORT_A_WR_EN),     ID(PORT_A2_WR_EN) },
+			{ ID(PORT_B_WR_EN),     ID(PORT_B2_WR_EN) },
+			{ ID(PORT_A_WR_BE),     ID(PORT_A2_WR_BE) },
+			{ ID(PORT_B_WR_BE),     ID(PORT_B2_WR_BE) },
+			{ ID(PORT_A_RD_DATA),   ID(PORT_A2_RD_DATA) },
+			{ ID(PORT_B_RD_DATA),   ID(PORT_B2_RD_DATA) }
+		};
+
+		if(second)
+			return bram2_map;
+		else
+			return bram1_map;
+	}
+
+	void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2)
+	{
+		const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED);
+
+		// Create the new cell
+		RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type);
+		log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name));
+
+		for (auto &it : param_map(false))
+		{
+			if(bram1->hasParam(it.first))
+				merged->setParam(it.second, bram1->getParam(it.first));
+		}
+		for (auto &it : param_map(true))
+		{
+			if(bram2->hasParam(it.first))
+				merged->setParam(it.second, bram2->getParam(it.first));
+		}
+
+		for (auto &it : port_map(false))
+		{
+			if (bram1->hasPort(it.first))
+				merged->setPort(it.second, bram1->getPort(it.first));
+			else
+				log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name));
+		}
+		for (auto &it : port_map(true))
+		{
+			if (bram2->hasPort(it.first))
+				merged->setPort(it.second, bram2->getPort(it.first));
+			else
+				log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name));
+		}
+		merged->attributes = bram1->attributes;
+		for (auto attr: bram2->attributes)
+			if (!merged->has_attribute(attr.first))
+				merged->attributes.insert(attr);
+
+		// Remove the old cells
+		module->remove(bram1);
+		module->remove(bram2);
+
+	}
+
+	void merge_bram_groups()
+	{
+		for (auto &it : mergeable_groups)
+		{
+			while (it.second.size() > 1)
+			{
+				merge_brams(it.second.pop(), it.second.pop());
+			}
+		}
+	}
+
+};
+
+struct QlBramMergePass : public Pass {
+	
+	QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {}
+
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ql_bram_merge [selection]\n");
+		log("\n");
+		log("    This pass identifies k6n10f 18K BRAM cells and packs pairs of them together\n");
+		log("    into a TDP36K cell operating in split mode\n");
+		log("\n");
+	}
+
+
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing QL_BRAM_MERGE pass.\n");
+
+		size_t argidx = 1;
+		extra_args(args, argidx, design);
+
+		for (RTLIL::Module* module : design->selected_modules())
+		{
+			QlBramMergeWorker worker(module);
+			worker.merge_bram_groups();
+		}
+	}
+
+
+} QlBramMergePass;
+
+PRIVATE_NAMESPACE_END
diff --git a/yosys/techlibs/quicklogic/ql_bram_types.cc b/yosys/techlibs/quicklogic/ql_bram_types.cc
new file mode 100644
index 00000000000..cf42703aaac
--- /dev/null
+++ b/yosys/techlibs/quicklogic/ql_bram_types.cc
@@ -0,0 +1,165 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2023  N. Engelhardt <nak@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/log.h"
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+// ============================================================================
+
+
+struct QlBramTypesPass : public Pass {
+	
+	QlBramTypesPass() : Pass("ql_bram_types", "Change TDP36K type to subtypes") {}
+
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ql_bram_types [selection]\n");
+		log("\n");
+		log("    This pass changes the type of TDP36K cells to different types based on the\n");
+		log("    configuration of the cell.\n");
+		log("\n");
+	}
+
+	int width_for_mode(int mode){
+		// 1: mode = 3'b101;
+		// 2: mode = 3'b110;
+		// 4: mode = 3'b100;
+		// 8,9: mode = 3'b001;
+		// 16, 18: mode = 3'b010;
+		// 32, 36: mode = 3'b011;
+		switch (mode)
+		{
+		case 1:
+			return 9;
+		case 2:
+			return 18;
+		case 3:
+			return 36;
+		case 4:
+			return 4;
+		case 5:
+			return 1;
+		case 6:
+			return 2;
+		default:
+			log_error("Invalid mode: %x", mode);
+		}
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing QL_BRAM_TYPES pass.\n");
+
+		size_t argidx = 1;
+		extra_args(args, argidx, design);
+
+		for (RTLIL::Module* module : design->selected_modules())
+			for (RTLIL::Cell* cell: module->selected_cells())
+			{
+				if (cell->type != ID(TDP36K) || !cell->hasParam(ID(MODE_BITS)))
+					continue;
+				
+				RTLIL::Const mode_bits = cell->getParam(ID(MODE_BITS));
+
+				bool split = mode_bits.extract(80).as_bool();
+
+				bool FMODE1_i = mode_bits.extract(13).as_bool();
+				bool FMODE2_i = mode_bits.extract(54).as_bool();
+				if (FMODE1_i != FMODE2_i) {
+					log_debug("Can't change type of mixed use TDP36K block: FMODE1_i = %s, FMODE2_i = %s\n", FMODE1_i ? "true" : "false", FMODE2_i ? "true" : "false");
+					continue;
+				}
+				bool is_fifo = FMODE1_i;
+
+				bool SYNC_FIFO1_i = mode_bits.extract(0).as_bool();
+				bool SYNC_FIFO2_i = mode_bits.extract(41).as_bool();
+				if (SYNC_FIFO1_i != SYNC_FIFO2_i) {
+					log_debug("Can't change type of mixed use TDP36K block: SYNC_FIFO1_i = %s, SYNC_FIFO2_i = %s\n", SYNC_FIFO1_i ? "true" : "false", SYNC_FIFO2_i ? "true" : "false");
+					continue;
+				}
+				bool sync_fifo = SYNC_FIFO1_i;
+
+				int RMODE_A1_i = mode_bits.extract(1, 3).as_int();
+				int RMODE_B1_i = mode_bits.extract(4, 3).as_int();
+				int WMODE_A1_i = mode_bits.extract(7, 3).as_int();
+				int WMODE_B1_i = mode_bits.extract(10, 3).as_int();
+
+				int RMODE_A2_i = mode_bits.extract(42, 3).as_int();
+				int RMODE_B2_i = mode_bits.extract(45, 3).as_int();
+				int WMODE_A2_i = mode_bits.extract(48, 3).as_int();
+				int WMODE_B2_i = mode_bits.extract(51, 3).as_int();
+
+				// TODO: should these be a warning or an error?
+				if (RMODE_A1_i != WMODE_A1_i) {
+					log_warning("Can't change type of misconfigured TDP36K block: Port A1 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_A1_i), width_for_mode(WMODE_A1_i));
+					continue;
+				}
+				if (RMODE_B1_i != WMODE_B1_i) {
+					log_warning("Can't change type of misconfigured TDP36K block: Port B1 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_B1_i), width_for_mode(WMODE_B1_i));
+					continue;
+				}
+				if (RMODE_A2_i != WMODE_A2_i) {
+					log_warning("Can't change type of misconfigured TDP36K block: Port A2 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_A2_i), width_for_mode(WMODE_A2_i));
+					continue;
+				}
+				if (RMODE_B2_i != WMODE_B2_i) {
+					log_warning("Can't change type of misconfigured TDP36K block: Port B2 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_B2_i), width_for_mode(WMODE_B2_i));
+					continue;
+				}
+
+				// TODO: For nonsplit blocks, should RMODE_A1_i == RMODE_A2_i etc be checked/enforced?
+
+				std::string type = "TDP36K";
+				if (is_fifo) {
+					type += "_FIFO_";
+					if (sync_fifo)
+						type += "SYNC_";
+					else
+						type += "ASYNC_";
+				} else 
+					type += "_BRAM_";
+
+				if (split) {
+					type += stringf("A1_X%d_", width_for_mode(RMODE_A1_i));
+					type += stringf("B1_X%d_", width_for_mode(RMODE_B1_i));
+					type += stringf("A2_X%d_", width_for_mode(RMODE_A2_i));
+					type += stringf("B2_X%d_", width_for_mode(RMODE_B2_i));
+					type += "split";
+				} else {
+					type += stringf("A_X%d_", width_for_mode(RMODE_A1_i));
+					type += stringf("B_X%d_", width_for_mode(RMODE_B1_i));
+					type += "nonsplit";
+				}
+
+				cell->type = RTLIL::escape_id(type);
+				log_debug("Changed type of memory cell %s to %s\n", log_id(cell->name), log_id(cell->type));
+			}
+	}
+
+
+} QlBramMergePass;
+
+PRIVATE_NAMESPACE_END
\ No newline at end of file
diff --git a/yosys/techlibs/quicklogic/ql_dsp_io_regs.cc b/yosys/techlibs/quicklogic/ql_dsp_io_regs.cc
new file mode 100644
index 00000000000..ecf163dbf6b
--- /dev/null
+++ b/yosys/techlibs/quicklogic/ql_dsp_io_regs.cc
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2020-2022 F4PGA Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include "kernel/sigtools.h"
+#include "kernel/yosys.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+#define MODE_BITS_REGISTER_INPUTS_ID 92
+#define MODE_BITS_OUTPUT_SELECT_START_ID 81
+#define MODE_BITS_OUTPUT_SELECT_WIDTH 3
+
+// ============================================================================
+
+struct QlDspIORegs : public Pass {
+	SigMap sigmap;
+
+	// ..........................................
+
+	QlDspIORegs() : Pass("ql_dsp_io_regs", "change types of QL_DSP2 depending on configuration") {}
+
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ql_dsp_io_regs [options] [selection]\n");
+		log("\n");
+		log("This pass looks for QL_DSP2 cells and changes their cell type depending on their\n");
+		log("configuration.\n");
+	}
+
+	void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
+	{
+		log_header(a_Design, "Executing QL_DSP_IO_REGS pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < a_Args.size(); argidx++) {
+			break;
+		}
+		extra_args(a_Args, argidx, a_Design);
+
+		for (auto module : a_Design->selected_modules()) {
+			ql_dsp_io_regs_pass(module);
+		}
+	}
+
+	void ql_dsp_io_regs_pass(RTLIL::Module *module)
+	{
+		static const std::vector<IdString> ports2del_mult = {ID(load_acc), ID(subtract), ID(acc_fir), ID(dly_b),
+														ID(saturate_enable), ID(shift_right), ID(round)};
+		static const std::vector<IdString> ports2del_mult_acc = {ID(acc_fir), ID(dly_b)};
+
+
+		sigmap.set(module);
+
+		for (auto cell : module->cells()) {
+			if (cell->type != ID(QL_DSP2))
+				continue;
+
+			// If the cell does not have the "is_inferred" attribute set
+			// then don't touch it.
+			if (!cell->get_bool_attribute(ID(is_inferred)))
+				continue;
+
+			// Get DSP configuration
+			for (auto cfg_port : {ID(register_inputs), ID(output_select)})
+			if (!cell->hasPort(cfg_port) || !sigmap(cell->getPort(cfg_port)).is_fully_const())
+				log_error("Missing or non-constant '%s' port on DSP cell %s\n",
+						  log_id(cfg_port), log_id(cell));
+			int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int();
+			int out_sel_i = sigmap(cell->getPort(ID(output_select))).as_int();
+
+			// Get the feedback port
+			if (!cell->hasPort(ID(feedback)))
+				log_error("Missing 'feedback' port on %s", log_id(cell));
+			SigSpec feedback = sigmap(cell->getPort(ID(feedback)));
+
+			// Check the top two bits on 'feedback' to be constant zero.
+			// That's what we are expecting from inference.
+			if (feedback.extract(1, 2) != SigSpec(0, 2))
+				log_error("Unexpected feedback configuration on %s\n", log_id(cell));
+
+			// Build new type name
+			std::string new_type = "\\QL_DSP2_MULT";
+
+			// Decide if we should be deleting the clock port
+			bool del_clk = true;
+
+			switch (out_sel_i) {
+				case 1:
+				case 2:
+				case 3:
+				case 5:
+				case 7:
+					del_clk = false;
+					new_type += "ACC";
+					break;
+				default:
+					break;
+			}
+
+			if (reg_in_i) {
+				del_clk = false;
+				new_type += "_REGIN";
+			}
+
+			if (out_sel_i > 3) {
+				del_clk = false;
+				new_type += "_REGOUT";
+			}
+
+			// Set new type name
+			cell->type = RTLIL::IdString(new_type);
+
+			std::vector<std::string> ports2del;
+
+			if (del_clk)
+				cell->unsetPort(ID(clk));
+
+			switch (out_sel_i) {
+			case 0:
+			case 4:
+			case 6:
+				for (auto port : ports2del_mult)
+					cell->unsetPort(port);
+				break;
+			case 1:
+			case 2:
+			case 3:
+			case 5:
+			case 7:
+				for (auto port : ports2del_mult_acc)
+					cell->unsetPort(port);
+				break;
+			}
+		}
+	}
+} QlDspIORegs;
+
+PRIVATE_NAMESPACE_END
diff --git a/yosys/techlibs/quicklogic/ql_dsp_macc.cc b/yosys/techlibs/quicklogic/ql_dsp_macc.cc
new file mode 100644
index 00000000000..f0669da6c9b
--- /dev/null
+++ b/yosys/techlibs/quicklogic/ql_dsp_macc.cc
@@ -0,0 +1,214 @@
+/*
+ * Copyright 2020-2022 F4PGA Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include "kernel/sigtools.h"
+#include "kernel/yosys.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+#include "techlibs/quicklogic/ql_dsp_macc_pm.h"
+
+// ============================================================================
+
+static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
+{
+    auto &st = pm.st_ql_dsp_macc;
+
+    // Get port widths
+    size_t a_width = GetSize(st.mul->getPort(ID(A)));
+    size_t b_width = GetSize(st.mul->getPort(ID(B)));
+    size_t z_width = GetSize(st.ff->getPort(ID(Q)));
+
+    size_t min_width = std::min(a_width, b_width);
+    size_t max_width = std::max(a_width, b_width);
+
+    // Signed / unsigned
+    bool ab_signed = st.mul->getParam(ID(A_SIGNED)).as_bool();
+    log_assert(ab_signed == st.mul->getParam(ID(B_SIGNED)).as_bool());
+
+    // Determine DSP type or discard if too narrow / wide
+    RTLIL::IdString type;
+    size_t tgt_a_width;
+    size_t tgt_b_width;
+    size_t tgt_z_width;
+
+    string cell_base_name = "dsp_t1";
+    string cell_size_name = "";
+    string cell_cfg_name = "";
+    string cell_full_name = "";
+
+    if (min_width <= 2 && max_width <= 2 && z_width <= 4) {
+        log_debug("\trejected: too narrow (%zd %zd %zd)\n", min_width, max_width, z_width);
+        return;
+    } else if (min_width <= 9 && max_width <= 10 && z_width <= 19) {
+        cell_size_name = "_10x9x32";
+        tgt_a_width = 10;
+        tgt_b_width = 9;
+        tgt_z_width = 19;
+    } else if (min_width <= 18 && max_width <= 20 && z_width <= 38) {
+        cell_size_name = "_20x18x64";
+        tgt_a_width = 20;
+        tgt_b_width = 18;
+        tgt_z_width = 38;
+    } else {
+        log_debug("\trejected: too wide (%zd %zd %zd)\n", min_width, max_width, z_width);
+        return;
+    }
+
+    type = RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports");
+    log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, log_id(type));
+
+    for (auto cell : {st.mul, st.add, st.mux, st.ff})
+    if (cell)
+        log("  %s (%s)\n", log_id(cell), log_id(cell->type));
+
+    // Add the DSP cell
+    RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type);
+
+    // Set attributes
+    cell->set_bool_attribute(ID(is_inferred), true);
+
+    // Get input/output data signals
+    RTLIL::SigSpec sig_a, sig_b, sig_z;
+    sig_a = st.mul->getPort(ID(A));
+    sig_b = st.mul->getPort(ID(B));
+    sig_z = st.output_registered ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D));
+
+    if (a_width < b_width)
+        std::swap(sig_a, sig_b);
+
+    // Connect input data ports, sign extend / pad with zeros
+    sig_a.extend_u0(tgt_a_width, ab_signed);
+    sig_b.extend_u0(tgt_b_width, ab_signed);
+    cell->setPort(ID(a_i), sig_a);
+    cell->setPort(ID(b_i), sig_b);
+
+    // Connect output data port, pad if needed
+    if ((size_t) GetSize(sig_z) < tgt_z_width) {
+        auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z));
+        sig_z.append(wire);
+    }
+    cell->setPort(ID(z_o), sig_z);
+
+    // Connect clock, reset and enable
+    cell->setPort(ID(clock_i), st.ff->getPort(ID(CLK)));
+
+    RTLIL::SigSpec rst;
+    RTLIL::SigSpec ena;
+
+    if (st.ff->hasPort(ID(ARST))) {
+        if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) {
+            rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST)));
+        } else {
+            rst = st.ff->getPort(ID(ARST));
+        }
+    } else {
+        rst = RTLIL::SigSpec(RTLIL::S0);
+    }
+
+    if (st.ff->hasPort(ID(EN))) {
+        if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) {
+            ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN)));
+        } else {
+            ena = st.ff->getPort(ID(EN));
+        }
+    } else {
+        ena = RTLIL::SigSpec(RTLIL::S1);
+    }
+
+    cell->setPort(ID(reset_i), rst);
+    cell->setPort(ID(load_acc_i), ena);
+
+    // Insert feedback_i control logic used for clearing / loading the accumulator
+    if (st.mux_in_pattern) {
+        RTLIL::SigSpec sig_s = st.mux->getPort(ID(S));
+
+        // Depending on the mux port ordering insert inverter if needed
+        log_assert(st.mux_ab.in(ID(A), ID(B)));
+        if (st.mux_ab == ID(A))
+            sig_s = pm.module->Not(NEW_ID, sig_s);
+
+        // Assemble the full control signal for the feedback_i port
+        RTLIL::SigSpec sig_f;
+        sig_f.append(sig_s);
+        sig_f.append(RTLIL::S0);
+        sig_f.append(RTLIL::S0);
+        cell->setPort(ID(feedback_i), sig_f);
+    }
+    // No acc clear/load
+    else {
+        cell->setPort(ID(feedback_i), RTLIL::SigSpec(RTLIL::S0, 3));
+    }
+
+    // Connect control ports
+    cell->setPort(ID(unsigned_a_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
+    cell->setPort(ID(unsigned_b_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
+
+    // Connect config bits
+    cell->setPort(ID(saturate_enable_i), RTLIL::SigSpec(RTLIL::S0));
+    cell->setPort(ID(shift_right_i), RTLIL::SigSpec(RTLIL::S0, 6));
+    cell->setPort(ID(round_i), RTLIL::SigSpec(RTLIL::S0));
+    cell->setPort(ID(register_inputs_i), RTLIL::SigSpec(RTLIL::S0));
+    // 3 - output post acc; 1 - output pre acc
+    cell->setPort(ID(output_select_i), RTLIL::Const(st.output_registered ? 1 : 3, 3));
+
+    bool subtract = (st.add->type == ID($sub));
+    cell->setPort(ID(subtract_i), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
+
+    // Mark the cells for removal
+    pm.autoremove(st.mul);
+    pm.autoremove(st.add);
+    if (st.mux != nullptr) {
+        pm.autoremove(st.mux);
+    }
+    pm.autoremove(st.ff);
+}
+
+struct QlDspMacc : public Pass {
+	QlDspMacc() : Pass("ql_dsp_macc", "infer QuickLogic multiplier-accumulator DSP cells") {}
+
+	void help() override
+	{
+        //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ql_dsp_macc [selection]\n");
+        log("\n");
+        log("This pass looks for a multiply-accumulate pattern based on which it infers a\n");
+        log("QuickLogic DSP cell.\n");
+		log("\n");
+	}
+
+	void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
+	{
+		log_header(a_Design, "Executing QL_DSP_MACC pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < a_Args.size(); argidx++) {
+			break;
+		}
+		extra_args(a_Args, argidx, a_Design);
+
+		for (auto module : a_Design->selected_modules())
+			ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp);
+	}
+
+} QlDspMacc;
+
+PRIVATE_NAMESPACE_END
diff --git a/yosys/techlibs/quicklogic/ql_dsp_macc.pmg b/yosys/techlibs/quicklogic/ql_dsp_macc.pmg
new file mode 100644
index 00000000000..df18596d109
--- /dev/null
+++ b/yosys/techlibs/quicklogic/ql_dsp_macc.pmg
@@ -0,0 +1,77 @@
+pattern ql_dsp_macc
+// Rough sketch: (mux is optional)
+//
+//               /-----------------------\
+//               |                       |
+//              \ /                      |
+//   mul ----> add -----> mux -----> ff -+---->
+//         |              /\
+//         |              |
+//          --------------
+
+state <IdString> add_ba
+state <IdString> mux_ab
+
+// Is the output taken from before or after the FF?
+state <bool> output_registered
+
+// Is there a mux in the pattern?
+state <bool> mux_in_pattern
+
+code mux_in_pattern
+    mux_in_pattern = false;
+    branch;
+    mux_in_pattern = true;
+endcode
+
+// The multiplier is at the center of our pattern
+match mul
+    select mul->type.in($mul)
+    // It has either two or three consumers depending on whether there's a mux
+    // in the pattern or not
+    select nusers(port(mul, \Y)) <= 3
+    filter nusers(port(mul, \Y)) == (mux_in_pattern ? 3 : 2)
+endmatch
+
+code output_registered
+    output_registered = false;
+    branch;
+    output_registered = true;
+endcode
+
+match add
+    select add->type.in($add, $sub)
+    choice <IdString> AB {\A, \B}
+    define <IdString> BA (AB == \A ? \B : \A)
+    // One input to the adder is fed by the multiplier
+    index <SigSpec> port(add, AB) === port(mul, \Y)
+    // Save the other input port, it needs to be fed by the flip-flop
+    set add_ba BA
+    // Adder has either two or three consumers; it will have three consumers
+    // IFF there's no mux in the pattern and the multiplier-accumulator result
+    // is taken unregistered
+    filter nusers(port(add, \Y)) == (!mux_in_pattern && !output_registered ? 3 : 2)
+endmatch
+
+match mux
+    if mux_in_pattern
+    select mux->type.in($mux)
+    choice <IdString> AB {\A, \B}
+    define <IdString> BA (AB == \A ? \B : \A)
+    index <SigSpec> port(mux, AB) === port(mul, \Y)
+    index <SigSpec> port(mux, BA) === port(add, \Y)
+    filter nusers(port(mux, \Y)) == (output_registered ? 2 : 3)
+    set mux_ab AB
+endmatch
+
+match ff
+    select ff->type.in($dff, $adff, $dffe, $adffe)
+    select param(ff, \CLK_POLARITY).as_bool()
+    index <SigSpec> port(ff, \D) === mux_in_pattern ? port(mux, \Y) : port(add, \Y);
+    index <SigSpec> port(ff, \Q) === port(add, add_ba)
+    filter nusers(port(ff, \Q)) == (output_registered ? 3 : 2)
+endmatch
+
+code
+    accept;
+endcode
diff --git a/yosys/techlibs/quicklogic/ql_dsp_simd.cc b/yosys/techlibs/quicklogic/ql_dsp_simd.cc
new file mode 100644
index 00000000000..9df979c3362
--- /dev/null
+++ b/yosys/techlibs/quicklogic/ql_dsp_simd.cc
@@ -0,0 +1,276 @@
+/*
+ * Copyright 2020-2022 F4PGA Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "kernel/log.h"
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+
+// ============================================================================
+
+struct QlDspSimdPass : public Pass {
+
+	QlDspSimdPass() : Pass("ql_dsp_simd", "merge QuickLogic K6N10f DSP pairs to operate in SIMD mode") {}
+
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ql_dsp_simd [selection]\n");
+		log("\n");
+		log("This pass identifies K6N10f DSP cells with identical configuration and pack pairs\n");
+		log("of them together into other DSP cells that can perform SIMD operation.\n");
+	}
+
+	// ..........................................
+
+	/// Describes DSP config unique to a whole DSP cell
+	struct DspConfig {
+		// Port connections
+		dict<RTLIL::IdString, RTLIL::SigSpec> connections;
+
+		DspConfig() = default;
+
+		DspConfig(const DspConfig &ref) = default;
+		DspConfig(DspConfig &&ref) = default;
+
+		unsigned int hash() const { return connections.hash(); }
+
+		bool operator==(const DspConfig &ref) const { return connections == ref.connections; }
+	};
+
+	// ..........................................
+
+	const int m_ModeBitsSize = 80;
+
+	// DSP parameters
+	const std::vector<std::string> m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"};
+
+	/// Temporary SigBit to SigBit helper map.
+	SigMap sigmap;
+
+	// ..........................................
+
+	void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
+	{
+		log_header(a_Design, "Executing QL_DSP_SIMD pass.\n");
+
+		// DSP control and config ports to consider and how to map them to ports
+		// of the target DSP cell
+		static const std::vector<std::pair<IdString, IdString>> m_DspCfgPorts = {
+			std::make_pair(ID(clock_i), ID(clk)),
+			std::make_pair(ID(reset_i), ID(reset)),
+			std::make_pair(ID(feedback_i), ID(feedback)),
+			std::make_pair(ID(load_acc_i), ID(load_acc)),
+			std::make_pair(ID(unsigned_a_i), ID(unsigned_a)),
+			std::make_pair(ID(unsigned_b_i), ID(unsigned_b)),
+			std::make_pair(ID(subtract_i), ID(subtract)),
+			std::make_pair(ID(output_select_i), ID(output_select)),
+			std::make_pair(ID(saturate_enable_i), ID(saturate_enable)),
+			std::make_pair(ID(shift_right_i), ID(shift_right)),
+			std::make_pair(ID(round_i), ID(round)),
+			std::make_pair(ID(register_inputs_i), ID(register_inputs))
+		};
+
+		// DSP data ports and how to map them to ports of the target DSP cell
+		static const std::vector<std::pair<IdString, IdString>> m_DspDataPorts = {
+			std::make_pair(ID(a_i), ID(a)),
+			std::make_pair(ID(b_i), ID(b)),
+			std::make_pair(ID(acc_fir_i), ID(acc_fir)),
+			std::make_pair(ID(z_o), ID(z)),
+			std::make_pair(ID(dly_b_o), ID(dly_b))
+		};
+
+		// Source DSP cell type (SISD)
+		static const IdString m_SisdDspType = ID(dsp_t1_10x9x32);
+
+		// Target DSP cell types for the SIMD mode
+		static const IdString m_SimdDspType = ID(QL_DSP2);
+
+		// Parse args
+		extra_args(a_Args, 1, a_Design);
+
+		// Process modules
+		for (auto module : a_Design->selected_modules()) {
+			// Setup the SigMap
+			sigmap.set(module);
+
+			// Assemble DSP cell groups
+			dict<DspConfig, std::vector<RTLIL::Cell *>> groups;
+			for (auto cell : module->selected_cells()) {
+				// Check if this is a DSP cell we are looking for (type starts with m_SisdDspType)
+				if (cell->type != m_SisdDspType)
+					continue;
+
+				// Skip if it has the (* keep *) attribute set
+				if (cell->has_keep_attr())
+					continue;
+
+				// Add to a group
+				const auto key = getDspConfig(cell, m_DspCfgPorts);
+				groups[key].push_back(cell);
+			}
+
+			std::vector<Cell *> cellsToRemove;
+
+			// Map cell pairs to the target DSP SIMD cell
+			for (const auto &it : groups) {
+				const auto &group = it.second;
+				const auto &config = it.first;
+
+				// Ensure an even number
+				size_t count = group.size();
+				if (count & 1)
+					count--;
+
+				// Map SIMD pairs
+				for (size_t i = 0; i < count; i += 2) {
+					Cell *dsp_a = group[i];
+					Cell *dsp_b = group[i + 1];
+
+					// Create the new cell
+					Cell *simd = module->addCell(NEW_ID, m_SimdDspType);
+
+					log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", log_id(dsp_a), log_id(dsp_a->type),
+						log_id(dsp_b), log_id(dsp_b->type), log_id(simd), log_id(simd->type));
+
+					// Check if the target cell is known (important to know
+					// its port widths)
+					if (!simd->known())
+						log_error(" The target cell type '%s' is not known!", log_id(simd));
+
+					// Connect common ports
+					for (const auto &it : m_DspCfgPorts)
+						simd->setPort(it.first, config.connections.at(it.second));
+
+					// Connect data ports
+					for (const auto &it : m_DspDataPorts) {
+						size_t width;
+						bool isOutput;
+
+						std::tie(width, isOutput) = getPortInfo(simd, it.second);
+
+						auto getConnection = [&](const RTLIL::Cell *cell) {
+							RTLIL::SigSpec sigspec;
+							if (cell->hasPort(it.first)) {
+								const auto &sig = cell->getPort(it.first);
+								sigspec.append(sig);
+							}
+
+							int padding = width / 2 - sigspec.bits().size();
+
+							if (padding) {
+								if (!isOutput)
+									sigspec.append(RTLIL::SigSpec(RTLIL::Sx, padding));
+								else
+									sigspec.append(module->addWire(NEW_ID, padding));
+							}
+							return sigspec;
+						};
+
+						RTLIL::SigSpec sigspec;
+						sigspec.append(getConnection(dsp_a));
+						sigspec.append(getConnection(dsp_b));
+						simd->setPort(it.second, sigspec);
+					}
+
+					// Concatenate FIR coefficient parameters into the single
+					// MODE_BITS parameter
+					Const mode_bits;
+					for (const auto &it : m_DspParams) {
+						auto val_a = dsp_a->getParam(it);
+						auto val_b = dsp_b->getParam(it);
+
+						mode_bits.bits.insert(mode_bits.end(), val_a.begin(), val_a.end());
+						mode_bits.bits.insert(mode_bits.end(), val_b.begin(), val_b.end());
+					}
+
+					// Enable the fractured mode by connecting the control
+					// port.
+					simd->setPort(ID(f_mode), State::S1);
+					simd->setParam(ID(MODE_BITS), mode_bits);
+					log_assert(mode_bits.size() == m_ModeBitsSize);
+
+					// Handle the "is_inferred" attribute. If one of the fragments
+					// is not inferred mark the whole DSP as not inferred
+					bool is_inferred_a = dsp_a->get_bool_attribute(ID(is_inferred));
+					bool is_inferred_b = dsp_b->get_bool_attribute(ID(is_inferred));
+					simd->set_bool_attribute(ID(is_inferred), is_inferred_a && is_inferred_b);
+
+					// Mark DSP parts for removal
+					cellsToRemove.push_back(dsp_a);
+					cellsToRemove.push_back(dsp_b);
+				}
+			}
+
+			// Remove old cells
+			for (auto cell : cellsToRemove)
+				module->remove(cell);
+		}
+	}
+
+	// ..........................................
+
+	/// Looks up port width and direction in the cell definition and returns it.
+	/// Returns (0, false) if it cannot be determined.
+	std::pair<size_t, bool> getPortInfo(RTLIL::Cell *a_Cell, RTLIL::IdString a_Port)
+	{
+		if (!a_Cell->known()) {
+			return std::make_pair(0, false);
+		}
+
+		// Get the module defining the cell (the previous condition ensures
+		// that the pointers are valid)
+		RTLIL::Module *mod = a_Cell->module->design->module(a_Cell->type);
+		if (mod == nullptr) {
+			return std::make_pair(0, false);
+		}
+
+		// Get the wire representing the port
+		RTLIL::Wire *wire = mod->wire(a_Port);
+		if (wire == nullptr) {
+			return std::make_pair(0, false);
+		}
+
+		return std::make_pair(wire->width, wire->port_output);
+	}
+
+	/// Given a DSP cell populates and returns a DspConfig struct for it.
+	DspConfig getDspConfig(RTLIL::Cell *a_Cell, const std::vector<std::pair<IdString, IdString>> &dspCfgPorts)
+	{
+		DspConfig config;
+
+		for (const auto &it : dspCfgPorts) {
+			auto port = it.first;
+
+			// Port unconnected
+			if (!a_Cell->hasPort(port))
+				continue;
+
+			config.connections[port] = sigmap(a_Cell->getPort(port));
+		}
+
+		return config;
+	}
+} QlDspSimdPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/.gitignore b/yosys/techlibs/quicklogic/qlf_k6n10f/.gitignore
new file mode 100644
index 00000000000..b5ba978ce2a
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/.gitignore
@@ -0,0 +1 @@
+/bram_types_sim.v
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v b/yosys/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
new file mode 100644
index 00000000000..68c2eb0aa13
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
@@ -0,0 +1,344 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype wire
+module TDP18K_FIFO (
+	RMODE_A_i,
+	RMODE_B_i,
+	WMODE_A_i,
+	WMODE_B_i,
+	WEN_A_i,
+	WEN_B_i,
+	REN_A_i,
+	REN_B_i,
+	CLK_A_i,
+	CLK_B_i,
+	BE_A_i,
+	BE_B_i,
+	ADDR_A_i,
+	ADDR_B_i,
+	WDATA_A_i,
+	WDATA_B_i,
+	RDATA_A_o,
+	RDATA_B_o,
+	EMPTY_o,
+	EPO_o,
+	EWM_o,
+	UNDERRUN_o,
+	FULL_o,
+	FMO_o,
+	FWM_o,
+	OVERRUN_o,
+	FLUSH_ni,
+	FMODE_i,
+);
+	parameter SYNC_FIFO_i = 1'b0;
+	parameter POWERDN_i = 1'b0;
+	parameter SLEEP_i = 1'b0;
+	parameter PROTECT_i = 1'b0;
+	parameter UPAF_i = 11'b0;
+	parameter UPAE_i = 11'b0;
+	parameter [18*1024-1:0] INIT_i = 18431'bx;
+
+	input wire [2:0] RMODE_A_i;
+	input wire [2:0] RMODE_B_i;
+	input wire [2:0] WMODE_A_i;
+	input wire [2:0] WMODE_B_i;
+	input wire WEN_A_i;
+	input wire WEN_B_i;
+	input wire REN_A_i;
+	input wire REN_B_i;
+	(* clkbuf_sink *)
+	input wire CLK_A_i;
+	(* clkbuf_sink *)
+	input wire CLK_B_i;
+	input wire [1:0] BE_A_i;
+	input wire [1:0] BE_B_i;
+	input wire [13:0] ADDR_A_i;
+	input wire [13:0] ADDR_B_i;
+	input wire [17:0] WDATA_A_i;
+	input wire [17:0] WDATA_B_i;
+	output reg [17:0] RDATA_A_o;
+	output reg [17:0] RDATA_B_o;
+	output wire EMPTY_o;
+	output wire EPO_o;
+	output wire EWM_o;
+	output wire UNDERRUN_o;
+	output wire FULL_o;
+	output wire FMO_o;
+	output wire FWM_o;
+	output wire OVERRUN_o;
+	input wire FLUSH_ni;
+	input wire FMODE_i;
+	reg [17:0] wmsk_a;
+	reg [17:0] wmsk_b;
+	wire [8:0] addr_a;
+	wire [8:0] addr_b;
+	reg [4:0] addr_a_d;
+	reg [4:0] addr_b_d;
+	wire [17:0] ram_rdata_a;
+	wire [17:0] ram_rdata_b;
+	reg [17:0] aligned_wdata_a;
+	reg [17:0] aligned_wdata_b;
+	wire ren_o;
+	wire [10:0] ff_raddr;
+	wire [10:0] ff_waddr;
+	wire [13:0] ram_addr_a;
+	wire [13:0] ram_addr_b;
+	wire [3:0] ram_waddr_a;
+	wire [3:0] ram_waddr_b;
+	wire initn;
+	wire smux_rclk;
+	wire smux_wclk;
+	wire real_fmode;
+	wire [3:0] raw_fflags;
+	reg [1:0] fifo_rmode;
+	reg [1:0] fifo_wmode;
+	wire smux_clk_a;
+	wire smux_clk_b;
+	wire ram_ren_a;
+	wire ram_ren_b;
+	wire ram_wen_a;
+	wire ram_wen_b;
+	wire cen_a;
+	wire cen_b;
+	wire cen_a_n;
+	wire cen_b_n;
+	wire ram_wen_a_n;
+	wire ram_wen_b_n;
+	localparam MODE_9 = 3'b001;
+	always @(*) begin
+		fifo_rmode = (RMODE_B_i == MODE_9 ? 2'b10 : 2'b01);
+		fifo_wmode = (WMODE_A_i == MODE_9 ? 2'b10 : 2'b01);
+	end
+	assign smux_clk_a = CLK_A_i;
+	assign smux_clk_b = CLK_B_i;
+	assign real_fmode = FMODE_i;
+	assign ram_ren_b = real_fmode ? ren_o : REN_B_i;
+	assign ram_wen_a = FMODE_i ? ~FULL_o & WEN_A_i : WEN_A_i;
+	assign ram_ren_a = FMODE_i ? 0 : REN_A_i;
+	assign ram_wen_b = FMODE_i ? 1'b0 : WEN_B_i;
+	assign cen_b = ram_ren_b | ram_wen_b;
+	assign cen_a = ram_ren_a | ram_wen_a;
+	assign ram_waddr_b = real_fmode ? {ff_raddr[0], 3'b000} : ADDR_B_i[3:0];
+	assign ram_waddr_a = real_fmode ? {ff_waddr[0], 3'b000} : ADDR_A_i[3:0];
+	assign ram_addr_b = real_fmode ? {ff_raddr[10:0], 3'h0} : {ADDR_B_i[13:4], addr_b_d[3:0]};
+	assign ram_addr_a = real_fmode ? {ff_waddr[10:0], 3'h0} : {ADDR_A_i[13:4], addr_a_d[3:0]};
+	always @(posedge CLK_A_i) addr_a_d[3:0] <= ADDR_A_i[3:0];
+	always @(posedge CLK_B_i) addr_b_d[3:0] <= ADDR_B_i[3:0];
+	assign cen_a_n = ~cen_a;
+	assign ram_wen_a_n = ~ram_wen_a;
+	assign cen_b_n = ~cen_b;
+	assign ram_wen_b_n = ~ram_wen_b;
+
+	sram1024x18 #(
+		.init(INIT_i)
+	) uram(
+		.clk_a(smux_clk_a),
+		.cen_a(cen_a_n),
+		.wen_a(ram_wen_a_n),
+		.addr_a(ram_addr_a[13:4]),
+		.wmsk_a(wmsk_a),
+		.wdata_a(aligned_wdata_a),
+		.rdata_a(ram_rdata_a),
+		.clk_b(smux_clk_b),
+		.cen_b(cen_b_n),
+		.wen_b(ram_wen_b_n),
+		.addr_b(ram_addr_b[13:4]),
+		.wmsk_b(wmsk_b),
+		.wdata_b(aligned_wdata_b),
+		.rdata_b(ram_rdata_b)
+	);
+	fifo_ctl #(
+		.ADDR_WIDTH(11),
+		.FIFO_WIDTH(2),
+		.DEPTH(6)
+	) fifo_ctl(
+		.rclk(smux_clk_b),
+		.rst_R_n(FLUSH_ni),
+		.wclk(smux_clk_a),
+		.rst_W_n(FLUSH_ni),
+		.ren(REN_B_i),
+		.wen(ram_wen_a),
+		.sync(SYNC_FIFO_i),
+		.rmode(fifo_rmode),
+		.wmode(fifo_wmode),
+		.ren_o(ren_o),
+		.fflags({FULL_o, FMO_o, FWM_o, OVERRUN_o, EMPTY_o, EPO_o, EWM_o, UNDERRUN_o}),
+		.raddr(ff_raddr),
+		.waddr(ff_waddr),
+		.upaf(UPAF_i),
+		.upae(UPAE_i)
+	);
+	localparam MODE_1 = 3'b101;
+	localparam MODE_18 = 3'b010;
+	localparam MODE_2 = 3'b110;
+	localparam MODE_4 = 3'b100;
+	always @(*) begin : WDATA_MODE_SEL
+		if (ram_wen_a == 1) begin
+			case (WMODE_A_i)
+				MODE_18: begin
+					aligned_wdata_a = WDATA_A_i;
+					{wmsk_a[17], wmsk_a[15:8]} = (FMODE_i ? 9'h000 : (BE_A_i[1] ? 9'h000 : 9'h1ff));
+					{wmsk_a[16], wmsk_a[7:0]} = (FMODE_i ? 9'h000 : (BE_A_i[0] ? 9'h000 : 9'h1ff));
+				end
+				MODE_9: begin
+					aligned_wdata_a = {{2 {WDATA_A_i[16]}}, {2 {WDATA_A_i[7:0]}}};
+					{wmsk_a[17], wmsk_a[15:8]} = (ram_waddr_a[3] ? 9'h000 : 9'h1ff);
+					{wmsk_a[16], wmsk_a[7:0]} = (ram_waddr_a[3] ? 9'h1ff : 9'h000);
+				end
+				MODE_4: begin
+					aligned_wdata_a = {2'b00, {4 {WDATA_A_i[3:0]}}};
+					wmsk_a[17:16] = 2'b00;
+					wmsk_a[15:12] = (ram_waddr_a[3:2] == 2'b11 ? 4'h0 : 4'hf);
+					wmsk_a[11:8] = (ram_waddr_a[3:2] == 2'b10 ? 4'h0 : 4'hf);
+					wmsk_a[7:4] = (ram_waddr_a[3:2] == 2'b01 ? 4'h0 : 4'hf);
+					wmsk_a[3:0] = (ram_waddr_a[3:2] == 2'b00 ? 4'h0 : 4'hf);
+				end
+				MODE_2: begin
+					aligned_wdata_a = {2'b00, {8 {WDATA_A_i[1:0]}}};
+					wmsk_a[17:16] = 2'b00;
+					wmsk_a[15:14] = (ram_waddr_a[3:1] == 3'b111 ? 2'h0 : 2'h3);
+					wmsk_a[13:12] = (ram_waddr_a[3:1] == 3'b110 ? 2'h0 : 2'h3);
+					wmsk_a[11:10] = (ram_waddr_a[3:1] == 3'b101 ? 2'h0 : 2'h3);
+					wmsk_a[9:8] = (ram_waddr_a[3:1] == 3'b100 ? 2'h0 : 2'h3);
+					wmsk_a[7:6] = (ram_waddr_a[3:1] == 3'b011 ? 2'h0 : 2'h3);
+					wmsk_a[5:4] = (ram_waddr_a[3:1] == 3'b010 ? 2'h0 : 2'h3);
+					wmsk_a[3:2] = (ram_waddr_a[3:1] == 3'b001 ? 2'h0 : 2'h3);
+					wmsk_a[1:0] = (ram_waddr_a[3:1] == 3'b000 ? 2'h0 : 2'h3);
+				end
+				MODE_1: begin
+					aligned_wdata_a = {2'b00, {16 {WDATA_A_i[0]}}};
+					wmsk_a = 18'h0ffff;
+					wmsk_a[{1'b0, ram_waddr_a[3:0]}] = 0;
+				end
+				default: wmsk_a = 18'h3ffff;
+			endcase
+		end
+		else begin
+			aligned_wdata_a = 18'h00000;
+			wmsk_a = 18'h3ffff;
+		end
+		if (ram_wen_b == 1)
+			case (WMODE_B_i)
+				MODE_18: begin
+					aligned_wdata_b = WDATA_B_i;
+					{wmsk_b[17], wmsk_b[15:8]} = (BE_B_i[1] ? 9'h000 : 9'h1ff);
+					{wmsk_b[16], wmsk_b[7:0]} = (BE_B_i[0] ? 9'h000 : 9'h1ff);
+				end
+				MODE_9: begin
+					aligned_wdata_b = {{2 {WDATA_B_i[16]}}, {2 {WDATA_B_i[7:0]}}};
+					{wmsk_b[17], wmsk_b[15:8]} = (ram_waddr_b[3] ? 9'h000 : 9'h1ff);
+					{wmsk_b[16], wmsk_b[7:0]} = (ram_waddr_b[3] ? 9'h1ff : 9'h000);
+				end
+				MODE_4: begin
+					aligned_wdata_b = {2'b00, {4 {WDATA_B_i[3:0]}}};
+					wmsk_b[17:16] = 2'b00;
+					wmsk_b[15:12] = (ram_waddr_b[3:2] == 2'b11 ? 4'h0 : 4'hf);
+					wmsk_b[11:8] = (ram_waddr_b[3:2] == 2'b10 ? 4'h0 : 4'hf);
+					wmsk_b[7:4] = (ram_waddr_b[3:2] == 2'b01 ? 4'h0 : 4'hf);
+					wmsk_b[3:0] = (ram_waddr_b[3:2] == 2'b00 ? 4'h0 : 4'hf);
+				end
+				MODE_2: begin
+					aligned_wdata_b = {2'b00, {8 {WDATA_B_i[1:0]}}};
+					wmsk_b[17:16] = 2'b00;
+					wmsk_b[15:14] = (ram_waddr_b[3:1] == 3'b111 ? 2'h0 : 2'h3);
+					wmsk_b[13:12] = (ram_waddr_b[3:1] == 3'b110 ? 2'h0 : 2'h3);
+					wmsk_b[11:10] = (ram_waddr_b[3:1] == 3'b101 ? 2'h0 : 2'h3);
+					wmsk_b[9:8] = (ram_waddr_b[3:1] == 3'b100 ? 2'h0 : 2'h3);
+					wmsk_b[7:6] = (ram_waddr_b[3:1] == 3'b011 ? 2'h0 : 2'h3);
+					wmsk_b[5:4] = (ram_waddr_b[3:1] == 3'b010 ? 2'h0 : 2'h3);
+					wmsk_b[3:2] = (ram_waddr_b[3:1] == 3'b001 ? 2'h0 : 2'h3);
+					wmsk_b[1:0] = (ram_waddr_b[3:1] == 3'b000 ? 2'h0 : 2'h3);
+				end
+				MODE_1: begin
+					aligned_wdata_b = {2'b00, {16 {WDATA_B_i[0]}}};
+					wmsk_b = 18'h0ffff;
+					wmsk_b[{1'b0, ram_waddr_b[3:0]}] = 0;
+				end
+				default: wmsk_b = 18'h3ffff;
+			endcase
+		else begin
+			aligned_wdata_b = 18'b000000000000000000;
+			wmsk_b = 18'h3ffff;
+		end
+	end
+	always @(*) begin : RDATA_A_MODE_SEL
+		case (RMODE_A_i)
+			default: RDATA_A_o = 18'h00000;
+			MODE_18: RDATA_A_o = ram_rdata_a;
+			MODE_9: begin
+				{RDATA_A_o[17], RDATA_A_o[15:8]} = 9'h000;
+				{RDATA_A_o[16], RDATA_A_o[7:0]} = (ram_addr_a[3] ? {ram_rdata_a[17], ram_rdata_a[15:8]} : {ram_rdata_a[16], ram_rdata_a[7:0]});
+			end
+			MODE_4: begin
+				RDATA_A_o[17:4] = 14'h0000;
+				case (ram_addr_a[3:2])
+					3: RDATA_A_o[3:0] = ram_rdata_a[15:12];
+					2: RDATA_A_o[3:0] = ram_rdata_a[11:8];
+					1: RDATA_A_o[3:0] = ram_rdata_a[7:4];
+					0: RDATA_A_o[3:0] = ram_rdata_a[3:0];
+				endcase
+			end
+			MODE_2: begin
+				RDATA_A_o[17:2] = 16'h0000;
+				case (ram_addr_a[3:1])
+					7: RDATA_A_o[1:0] = ram_rdata_a[15:14];
+					6: RDATA_A_o[1:0] = ram_rdata_a[13:12];
+					5: RDATA_A_o[1:0] = ram_rdata_a[11:10];
+					4: RDATA_A_o[1:0] = ram_rdata_a[9:8];
+					3: RDATA_A_o[1:0] = ram_rdata_a[7:6];
+					2: RDATA_A_o[1:0] = ram_rdata_a[5:4];
+					1: RDATA_A_o[1:0] = ram_rdata_a[3:2];
+					0: RDATA_A_o[1:0] = ram_rdata_a[1:0];
+				endcase
+			end
+			MODE_1: begin
+				RDATA_A_o[17:1] = 17'h00000;
+				RDATA_A_o[0] = ram_rdata_a[ram_addr_a[3:0]];
+			end
+		endcase
+	end
+	always @(*)
+		case (RMODE_B_i)
+			default: RDATA_B_o = 18'h15566;
+			MODE_18: RDATA_B_o = ram_rdata_b;
+			MODE_9: begin
+				{RDATA_B_o[17], RDATA_B_o[15:8]} = 9'b000000000;
+				{RDATA_B_o[16], RDATA_B_o[7:0]} = (ram_addr_b[3] ? {ram_rdata_b[17], ram_rdata_b[15:8]} : {ram_rdata_b[16], ram_rdata_b[7:0]});
+			end
+			MODE_4:
+				case (ram_addr_b[3:2])
+					3: RDATA_B_o[3:0] = ram_rdata_b[15:12];
+					2: RDATA_B_o[3:0] = ram_rdata_b[11:8];
+					1: RDATA_B_o[3:0] = ram_rdata_b[7:4];
+					0: RDATA_B_o[3:0] = ram_rdata_b[3:0];
+				endcase
+			MODE_2:
+				case (ram_addr_b[3:1])
+					7: RDATA_B_o[1:0] = ram_rdata_b[15:14];
+					6: RDATA_B_o[1:0] = ram_rdata_b[13:12];
+					5: RDATA_B_o[1:0] = ram_rdata_b[11:10];
+					4: RDATA_B_o[1:0] = ram_rdata_b[9:8];
+					3: RDATA_B_o[1:0] = ram_rdata_b[7:6];
+					2: RDATA_B_o[1:0] = ram_rdata_b[5:4];
+					1: RDATA_B_o[1:0] = ram_rdata_b[3:2];
+					0: RDATA_B_o[1:0] = ram_rdata_b[1:0];
+				endcase
+			MODE_1: RDATA_B_o[0] = ram_rdata_b[{1'b0, ram_addr_b[3:0]}];
+		endcase
+endmodule
+`default_nettype none
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/arith_map.v b/yosys/techlibs/quicklogic/qlf_k6n10f/arith_map.v
new file mode 100644
index 00000000000..d39a3a19f9a
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/arith_map.v
@@ -0,0 +1,99 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+(* techmap_celltype = "$alu" *)
+module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 2;
+	parameter B_WIDTH = 2;
+	parameter Y_WIDTH = 2;
+	parameter _TECHMAP_CONSTVAL_CI_ = 0;
+	parameter _TECHMAP_CONSTMSK_CI_ = 0;
+
+	(* force_downto *)
+	input [A_WIDTH-1:0] A;
+	(* force_downto *)
+	input [B_WIDTH-1:0] B;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] CO;
+
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] A_buf, B_buf;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] AA = A_buf;
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+
+	genvar i;
+	wire co;
+
+	(* force_downto *)
+	//wire [Y_WIDTH-1:0] C = {CO, CI};
+	wire [Y_WIDTH:0] C;
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] S  = {AA ^ BB};
+	assign CO[Y_WIDTH-1:0] = C[Y_WIDTH:1];
+		//assign CO[Y_WIDTH-1] = co;
+
+	generate
+		adder_carry intermediate_adder (
+			.cin     ( ),
+			.cout    (C[0]),
+			.p       (1'b0),
+			.g       (CI),
+			.sumout  ()
+		);
+	endgenerate
+	genvar i;
+	generate if (Y_WIDTH > 2) begin
+	  for (i = 0; i < Y_WIDTH-2; i = i + 1) begin:slice
+		adder_carry  my_adder (
+			.cin     (C[i]),
+			.g       (AA[i]),
+			.p       (S[i]),
+			.cout    (C[i+1]),
+			.sumout  (Y[i])
+		);
+		  end
+	end endgenerate
+	generate
+		adder_carry final_adder (
+			.cin     (C[Y_WIDTH-2]),
+			.cout    (),
+			.p       (1'b0),
+			.g       (1'b0),
+			.sumout  (co)
+		);
+	endgenerate
+
+	assign Y[Y_WIDTH-2] = S[Y_WIDTH-2] ^ co;
+	assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2];
+	assign Y[Y_WIDTH-1] = S[Y_WIDTH-1] ^ C[Y_WIDTH-1];
+	assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1];
+
+	assign X = S;
+endmodule
+
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/brams_map.v b/yosys/techlibs/quicklogic/qlf_k6n10f/brams_map.v
new file mode 100644
index 00000000000..ba6382a2395
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/brams_map.v
@@ -0,0 +1,4288 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module RAM_36K_BLK (
+		WEN_i,
+		REN_i,
+		WR_CLK_i,
+		RD_CLK_i,
+		WR_BE_i,
+		WR_ADDR_i,
+		RD_ADDR_i,
+		WDATA_i,
+		RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 36;
+parameter RD_DATA_WIDTH = 36;
+parameter BE_WIDTH = 4;
+
+parameter INIT = 0;
+
+input wire WEN_i;
+input wire REN_i;
+input wire WR_CLK_i;
+input wire RD_CLK_i;
+input wire [BE_WIDTH-1:0] WR_BE_i;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+32, 36: mode = 3'b011;
+default: mode = 3'b000;
+endcase
+endfunction
+
+function integer rwmode;
+input integer rwwidth;
+case (rwwidth)
+1: rwmode = 1;
+2: rwmode = 2;
+4: rwmode = 4;
+8,9: rwmode = 9;
+16, 18: rwmode = 18;
+32, 36: rwmode = 36;
+default: rwmode = 36;
+endcase
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+wire [3:0] WR_BE;
+
+wire [35:0] PORT_B_RDATA;
+wire [35:0] PORT_A_WDATA;
+
+wire [14:0] WR_ADDR_INT;
+wire [14:0] RD_ADDR_INT;
+
+wire [14:0] PORT_A_ADDR;
+wire [14:0] PORT_B_ADDR;
+
+wire PORT_A_CLK;
+wire PORT_B_CLK;
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(WR_DATA_WIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(WR_DATA_WIDTH);
+localparam [ 2:0] RMODE_A2_i    = mode(WR_DATA_WIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(WR_DATA_WIDTH);
+
+localparam [ 2:0] RMODE_B1_i    = mode(RD_DATA_WIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(RD_DATA_WIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(RD_DATA_WIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(RD_DATA_WIDTH);
+
+localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH);
+localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH);
+
+assign PORT_A_CLK = WR_CLK_i;
+assign PORT_B_CLK = RD_CLK_i;
+
+generate
+	if (WR_ADDR_WIDTH == 15) begin
+		assign WR_ADDR_INT = WR_ADDR_i;
+	end else begin
+		assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0;
+		assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i;
+	end
+endgenerate
+
+case (WR_DATA_WIDTH)
+	1: begin
+		assign PORT_A_ADDR = WR_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A_ADDR = WR_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A_ADDR = WR_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A_ADDR = WR_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A_ADDR = WR_ADDR_INT << 4;
+	end
+	32, 36: begin
+		assign PORT_A_ADDR = WR_ADDR_INT << 5;
+	end
+	default: begin
+		assign PORT_A_ADDR = WR_ADDR_INT;
+	end
+endcase
+
+generate
+	if (RD_ADDR_WIDTH == 15) begin
+		assign RD_ADDR_INT = RD_ADDR_i;
+	end else begin
+		assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0;
+		assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i;
+	end
+endgenerate
+
+case (RD_DATA_WIDTH)
+	1: begin
+		assign PORT_B_ADDR = RD_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B_ADDR = RD_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B_ADDR = RD_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B_ADDR = RD_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B_ADDR = RD_ADDR_INT << 4;
+	end
+	32, 36: begin
+		assign PORT_B_ADDR = RD_ADDR_INT << 5;
+	end
+	default: begin
+		assign PORT_B_ADDR = RD_ADDR_INT;
+	end
+endcase
+
+case (BE_WIDTH)
+	4: begin
+		assign WR_BE = WR_BE_i[BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR_BE[3:BE_WIDTH] = 0;
+		assign WR_BE[BE_WIDTH-1 :0] = WR_BE_i[BE_WIDTH-1 :0];
+	end
+endcase
+
+assign REN_A1_i = 1'b0;
+assign WEN_A1_i = WEN_i;
+assign {BE_A2_i, BE_A1_i} = WR_BE;
+
+assign REN_B1_i = REN_i;
+assign WEN_B1_i = 1'b0;
+assign {BE_B2_i, BE_B1_i} = 4'h0;
+
+generate
+	if (WR_DATA_WIDTH == 36) begin
+		assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0];
+	end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin
+		assign PORT_A_WDATA[WR_DATA_WIDTH+1:18]  = WDATA_i[WR_DATA_WIDTH-1:16];
+		assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]};
+	end else if (WR_DATA_WIDTH == 9) begin
+		assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]};
+	end else begin
+		assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0;
+		assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A1_i = PORT_A_WDATA[17:0];
+assign WDATA_A2_i = PORT_A_WDATA[35:18];
+
+assign WDATA_B1_i = 18'h0;
+assign WDATA_B2_i = 18'h0;
+
+generate
+	if (RD_DATA_WIDTH == 36) begin
+		assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o};
+	end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin
+		assign PORT_B_RDATA  = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]};
+	end else if (RD_DATA_WIDTH == 9) begin
+		assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]};
+	end else begin
+		assign PORT_B_RDATA = {18'h0, RDATA_B1_o};
+	end
+endgenerate
+
+assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0];
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+};
+
+
+(* is_inferred = 0 *)
+(* is_split = 0 *)
+(* is_fifo = 0 *)
+(* port_a_dwidth = PORT_A_WRWIDTH *)
+(* port_b_dwidth = PORT_B_WRWIDTH *)
+TDP36K _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+
+	.CLK_A1_i(PORT_A_CLK),
+	.ADDR_A1_i(PORT_A_ADDR),
+	.WEN_A1_i(WEN_A1_i),
+	.BE_A1_i(BE_A1_i),
+	.WDATA_A1_i(WDATA_A1_i),
+	.REN_A1_i(REN_A1_i),
+	.RDATA_A1_o(RDATA_A1_o),
+
+	.CLK_A2_i(PORT_A_CLK),
+	.ADDR_A2_i(PORT_A_ADDR[13:0]),
+	.WEN_A2_i(WEN_A1_i),
+	.BE_A2_i(BE_A2_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.REN_A2_i(REN_A1_i),
+	.RDATA_A2_o(RDATA_A2_o),
+
+	.CLK_B1_i(PORT_B_CLK),
+	.ADDR_B1_i(PORT_B_ADDR),
+	.WEN_B1_i(WEN_B1_i),
+	.BE_B1_i(BE_B1_i),
+	.WDATA_B1_i(WDATA_B1_i),
+	.REN_B1_i(REN_B1_i),
+	.RDATA_B1_o(RDATA_B1_o),
+
+	.CLK_B2_i(PORT_B_CLK),
+	.ADDR_B2_i(PORT_B_ADDR[13:0]),
+	.WEN_B2_i(WEN_B1_i),
+	.BE_B2_i(BE_B2_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.REN_B2_i(REN_B1_i),
+	.RDATA_B2_o(RDATA_B2_o),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
+
+module RAM_18K_BLK (
+		WEN_i,
+		REN_i,
+		WR_CLK_i,
+		RD_CLK_i,
+		WR_BE_i,
+		WR_ADDR_i,
+		RD_ADDR_i,
+		WDATA_i,
+		RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 18;
+parameter BE_WIDTH = 2;
+
+input wire WEN_i;
+input wire REN_i;
+input wire WR_CLK_i;
+input wire RD_CLK_i;
+input wire [BE_WIDTH-1:0] WR_BE_i;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+	(* is_inferred = 0 *)
+	(* is_split = 0 *)
+	(* is_fifo = 0 *)
+	BRAM2x18_SP  #(
+			.WR1_ADDR_WIDTH(WR_ADDR_WIDTH),
+			.RD1_ADDR_WIDTH(RD_ADDR_WIDTH),
+			.WR1_DATA_WIDTH(WR_DATA_WIDTH),
+			.RD1_DATA_WIDTH(RD_DATA_WIDTH),
+			.BE1_WIDTH(BE_WIDTH),
+			.WR2_ADDR_WIDTH(),
+			.RD2_ADDR_WIDTH(),
+			.WR2_DATA_WIDTH(),
+			.RD2_DATA_WIDTH(),
+			.BE2_WIDTH()
+			 ) U1
+			(
+			.RESET_ni(1'b1),
+
+			.WEN1_i(WEN_i),
+			.REN1_i(REN_i),
+			.WR1_CLK_i(WR_CLK_i),
+			.RD1_CLK_i(RD_CLK_i),
+			.WR1_BE_i(WR_BE_i),
+			.WR1_ADDR_i(WR_ADDR_i),
+			.RD1_ADDR_i(RD_ADDR_i),
+			.WDATA1_i(WDATA_i),
+			.RDATA1_o(RDATA_o),
+
+			.WEN2_i(1'b0),
+			.REN2_i(1'b0),
+			.WR2_CLK_i(1'b0),
+			.RD2_CLK_i(1'b0),
+			.WR2_BE_i(2'b00),
+			.WR2_ADDR_i(14'h0),
+			.RD2_ADDR_i(14'h0),
+			.WDATA2_i(18'h0),
+			.RDATA2_o()
+			);
+
+endmodule
+
+module RAM_18K_X2_BLK (
+		RESET_ni,
+
+		WEN1_i,
+		REN1_i,
+		WR1_CLK_i,
+		RD1_CLK_i,
+		WR1_BE_i,
+		WR1_ADDR_i,
+		RD1_ADDR_i,
+		WDATA1_i,
+		RDATA1_o,
+
+		WEN2_i,
+		REN2_i,
+		WR2_CLK_i,
+		RD2_CLK_i,
+		WR2_BE_i,
+		WR2_ADDR_i,
+		RD2_ADDR_i,
+		WDATA2_i,
+		RDATA2_o
+);
+
+parameter WR1_ADDR_WIDTH = 10;
+parameter RD1_ADDR_WIDTH = 10;
+parameter WR1_DATA_WIDTH = 18;
+parameter RD1_DATA_WIDTH = 18;
+parameter BE1_WIDTH = 2;
+
+parameter WR2_ADDR_WIDTH = 10;
+parameter RD2_ADDR_WIDTH = 10;
+parameter WR2_DATA_WIDTH = 18;
+parameter RD2_DATA_WIDTH = 18;
+parameter BE2_WIDTH = 2;
+
+input wire RESET_ni;
+
+input wire WEN1_i;
+input wire REN1_i;
+input wire WR1_CLK_i;
+input wire RD1_CLK_i;
+input wire [BE1_WIDTH-1:0] WR1_BE_i;
+input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i;
+input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i;
+input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i;
+output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o;
+
+input wire WEN2_i;
+input wire REN2_i;
+input wire WR2_CLK_i;
+input wire RD2_CLK_i;
+input wire [BE2_WIDTH-1:0] WR2_BE_i;
+input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i;
+input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i;
+input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i;
+output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o;
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+32, 36: mode = 3'b011;
+default: mode = 3'b000;
+endcase
+endfunction
+
+function integer rwmode;
+input integer rwwidth;
+case (rwwidth)
+1: rwmode = 1;
+2: rwmode = 2;
+4: rwmode = 4;
+8,9: rwmode = 9;
+16, 18: rwmode = 18;
+default: rwmode = 18;
+endcase
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+wire [1:0] WR1_BE;
+wire [1:0] WR2_BE;
+
+wire [17:0] PORT_B1_RDATA;
+wire [17:0] PORT_A1_WDATA;
+
+wire [17:0] PORT_B2_RDATA;
+wire [17:0] PORT_A2_WDATA;
+
+wire [13:0] WR1_ADDR_INT;
+wire [13:0] RD1_ADDR_INT;
+
+wire [13:0] WR2_ADDR_INT;
+wire [13:0] RD2_ADDR_INT;
+
+wire [13:0] PORT_A1_ADDR;
+wire [13:0] PORT_B1_ADDR;
+
+wire [13:0] PORT_A2_ADDR;
+wire [13:0] PORT_B2_ADDR;
+
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(WR1_DATA_WIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(WR1_DATA_WIDTH);
+localparam [ 2:0] RMODE_A2_i    = mode(WR2_DATA_WIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(WR2_DATA_WIDTH);
+
+localparam [ 2:0] RMODE_B1_i    = mode(RD1_DATA_WIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(RD1_DATA_WIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(RD2_DATA_WIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(RD2_DATA_WIDTH);
+
+localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH);
+localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH);
+localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH);
+localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH);
+
+generate
+	if (WR1_ADDR_WIDTH == 14) begin
+		assign WR1_ADDR_INT = WR1_ADDR_i;
+	end else begin
+		assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0;
+		assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i;
+	end
+endgenerate
+
+case (WR1_DATA_WIDTH)
+	1: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (RD1_ADDR_WIDTH == 14) begin
+		assign RD1_ADDR_INT = RD1_ADDR_i;
+	end else begin
+		assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0;
+		assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i;
+	end
+endgenerate
+
+case (RD1_DATA_WIDTH)
+	1: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (WR2_ADDR_WIDTH == 14) begin
+		assign WR2_ADDR_INT = WR2_ADDR_i;
+	end else begin
+		assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0;
+		assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i;
+	end
+endgenerate
+
+case (WR2_DATA_WIDTH)
+	1: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT;
+	end
+endcase
+
+generate
+	if (RD2_ADDR_WIDTH == 14) begin
+		assign RD2_ADDR_INT = RD2_ADDR_i;
+	end else begin
+		assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0;
+		assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i;
+	end
+endgenerate
+
+case (RD2_DATA_WIDTH)
+	1: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT;
+	end
+endcase
+
+case (BE1_WIDTH)
+	2: begin
+		assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR1_BE[1:BE1_WIDTH] = 0;
+		assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0];
+	end
+endcase
+
+case (BE2_WIDTH)
+	2: begin
+		assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR2_BE[1:BE2_WIDTH] = 0;
+		assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0];
+	end
+endcase
+
+assign REN_A1_i = 1'b0;
+assign WEN_A1_i = WEN1_i;
+assign BE_A1_i = WR1_BE;
+assign REN_A2_i = 1'b0;
+assign WEN_A2_i = WEN2_i;
+assign BE_A2_i = WR2_BE;
+
+assign REN_B1_i = REN1_i;
+assign WEN_B1_i = 1'b0;
+assign BE_B1_i = 4'h0;
+assign REN_B2_i = REN2_i;
+assign WEN_B2_i = 1'b0;
+assign BE_B2_i = 4'h0;
+
+generate
+	if (WR1_DATA_WIDTH == 18) begin
+		assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0];
+	end else if (WR1_DATA_WIDTH == 9) begin
+		assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]};
+	end else begin
+		assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0;
+		assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A1_i = PORT_A1_WDATA[17:0];
+assign WDATA_B1_i = 18'h0;
+
+generate
+	if (RD1_DATA_WIDTH == 9) begin
+		assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]};
+	end else begin
+		assign PORT_B1_RDATA = RDATA_B1_o;
+	end
+endgenerate
+
+assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0];
+
+generate
+	if (WR2_DATA_WIDTH == 18) begin
+		assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0];
+	end else if (WR2_DATA_WIDTH == 9) begin
+		assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]};
+	end else begin
+		assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0;
+		assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A2_i = PORT_A2_WDATA[17:0];
+assign WDATA_B2_i = 18'h0;
+
+generate
+	if (RD2_DATA_WIDTH == 9) begin
+		assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]};
+	end else begin
+		assign PORT_B2_RDATA = RDATA_B2_o;
+	end
+endgenerate
+
+assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0];
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+};
+
+(* is_inferred = 0 *)
+(* is_split = 1 *)
+(* is_fifo = 0 *)
+(* port_a1_dwidth = PORT_A1_WRWIDTH *)
+(* port_a2_dwidth = PORT_A2_WRWIDTH *)
+(* port_b1_dwidth = PORT_B1_WRWIDTH *)
+(* port_b2_dwidth = PORT_B2_WRWIDTH *)
+TDP36K _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+
+	.CLK_A1_i(WR1_CLK_i),
+	.ADDR_A1_i({1'b0,PORT_A1_ADDR}),
+	.WEN_A1_i(WEN_A1_i),
+	.BE_A1_i(BE_A1_i),
+	.WDATA_A1_i(WDATA_A1_i),
+	.REN_A1_i(REN_A1_i),
+	.RDATA_A1_o(RDATA_A1_o),
+
+	.CLK_A2_i(WR2_CLK_i),
+	.ADDR_A2_i(PORT_A2_ADDR),
+	.WEN_A2_i(WEN_A2_i),
+	.BE_A2_i(BE_A2_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.REN_A2_i(REN_A2_i),
+	.RDATA_A2_o(RDATA_A2_o),
+
+	.CLK_B1_i(RD1_CLK_i),
+	.ADDR_B1_i({1'b0,PORT_B1_ADDR}),
+	.WEN_B1_i(WEN_B1_i),
+	.BE_B1_i(BE_B1_i),
+	.WDATA_B1_i(WDATA_B1_i),
+	.REN_B1_i(REN_B1_i),
+	.RDATA_B1_o(RDATA_B1_o),
+
+	.CLK_B2_i(RD2_CLK_i),
+	.ADDR_B2_i(PORT_B2_ADDR),
+	.WEN_B2_i(WEN_B2_i),
+	.BE_B2_i(BE_B2_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.REN_B2_i(REN_B2_i),
+	.RDATA_B2_o(RDATA_B2_o),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
+
+module DPRAM_36K_BLK (
+		PORT_A_CLK_i,
+		PORT_A_WEN_i,
+		PORT_A_WR_BE_i,
+		PORT_A_REN_i,
+		PORT_A_ADDR_i,
+		PORT_A_WR_DATA_i,
+		PORT_A_RD_DATA_o,
+
+		PORT_B_CLK_i,
+		PORT_B_WEN_i,
+		PORT_B_WR_BE_i,
+		PORT_B_REN_i,
+		PORT_B_ADDR_i,
+		PORT_B_WR_DATA_i,
+		PORT_B_RD_DATA_o
+);
+
+parameter PORT_A_AWIDTH = 10;
+parameter PORT_A_DWIDTH = 36;
+parameter PORT_A_WR_BE_WIDTH = 4;
+
+parameter PORT_B_AWIDTH = 10;
+parameter PORT_B_DWIDTH = 36;
+parameter PORT_B_WR_BE_WIDTH = 4;
+
+input PORT_A_CLK_i;
+input [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i;
+input [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i;
+input PORT_A_WEN_i;
+input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i;
+input PORT_A_REN_i;
+output [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o;
+
+input PORT_B_CLK_i;
+input [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i;
+input [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i;
+input PORT_B_WEN_i;
+input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i;
+input PORT_B_REN_i;
+output [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o;
+
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+32, 36: mode = 3'b011;
+default: mode = 3'b000;
+endcase
+endfunction
+
+function integer rwmode;
+input integer rwwidth;
+case (rwwidth)
+1: rwmode = 1;
+2: rwmode = 2;
+4: rwmode = 4;
+8,9: rwmode = 9;
+16, 18: rwmode = 18;
+32, 36: rwmode = 36;
+default: rwmode = 36;
+endcase
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+wire [3:0] PORT_A_WR_BE;
+wire [3:0] PORT_B_WR_BE;
+
+wire [35:0] PORT_B_WDATA;
+wire [35:0] PORT_B_RDATA;
+wire [35:0] PORT_A_WDATA;
+wire [35:0] PORT_A_RDATA;
+
+wire [14:0] PORT_A_ADDR_INT;
+wire [14:0] PORT_B_ADDR_INT;
+
+wire [14:0] PORT_A_ADDR;
+wire [14:0] PORT_B_ADDR;
+
+wire PORT_A_CLK;
+wire PORT_B_CLK;
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(PORT_A_DWIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(PORT_A_DWIDTH);
+localparam [ 2:0] RMODE_A2_i    = mode(PORT_A_DWIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(PORT_A_DWIDTH);
+
+localparam [ 2:0] RMODE_B1_i    = mode(PORT_B_DWIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(PORT_B_DWIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(PORT_B_DWIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(PORT_B_DWIDTH);
+
+localparam PORT_A_WRWIDTH = rwmode(PORT_A_DWIDTH);
+localparam PORT_B_WRWIDTH = rwmode(PORT_B_DWIDTH);
+
+assign PORT_A_CLK = PORT_A_CLK_i;
+assign PORT_B_CLK = PORT_B_CLK_i;
+
+generate
+	if (PORT_A_AWIDTH == 15) begin
+		assign PORT_A_ADDR_INT = PORT_A_ADDR_i;
+	end else begin
+		assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0;
+		assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i;
+	end
+endgenerate
+
+case (PORT_A_DWIDTH)
+	1: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT << 4;
+	end
+	32, 36: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT << 5;
+	end
+	default: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_B_AWIDTH == 15) begin
+		assign PORT_B_ADDR_INT = PORT_B_ADDR_i;
+	end else begin
+		assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0;
+		assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i;
+	end
+endgenerate
+
+case (PORT_B_DWIDTH)
+	1: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT << 4;
+	end
+	32, 36: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT << 5;
+	end
+	default: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT;
+	end
+endcase
+
+case (PORT_A_WR_BE_WIDTH)
+	4: begin
+		assign PORT_A_WR_BE = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_A_WR_BE[3:PORT_A_WR_BE_WIDTH] = 0;
+		assign PORT_A_WR_BE[PORT_A_WR_BE_WIDTH-1 :0] = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_B_WR_BE_WIDTH)
+	4: begin
+		assign PORT_B_WR_BE = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_B_WR_BE[3:PORT_B_WR_BE_WIDTH] = 0;
+		assign PORT_B_WR_BE[PORT_B_WR_BE_WIDTH-1 :0] = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+assign REN_A1_i = PORT_A_REN_i;
+assign WEN_A1_i = PORT_A_WEN_i;
+assign {BE_A2_i, BE_A1_i} = PORT_A_WR_BE;
+
+assign REN_B1_i = PORT_B_REN_i;
+assign WEN_B1_i = PORT_B_WEN_i;
+assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE;
+
+generate
+	if (PORT_A_DWIDTH == 36) begin
+		assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0];
+	end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin
+		assign PORT_A_WDATA[PORT_A_DWIDTH+1:18]  = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16];
+		assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]};
+	end else if (PORT_A_DWIDTH == 9) begin
+		assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0;
+		assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A1_i = PORT_A_WDATA[17:0];
+assign WDATA_A2_i = PORT_A_WDATA[35:18];
+
+generate
+	if (PORT_A_DWIDTH == 36) begin
+		assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o};
+	end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin
+		assign PORT_A_RDATA  = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]};
+	end else if (PORT_A_DWIDTH == 9) begin
+		assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]};
+	end else begin
+		assign PORT_A_RDATA = {18'h0, RDATA_A1_o};
+	end
+endgenerate
+
+assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0];
+
+generate
+	if (PORT_B_DWIDTH == 36) begin
+		assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0];
+	end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin
+		assign PORT_B_WDATA[PORT_B_DWIDTH+1:18]  = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16];
+		assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]};
+	end else if (PORT_B_DWIDTH == 9) begin
+		assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0;
+		assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_B1_i = PORT_B_WDATA[17:0];
+assign WDATA_B2_i = PORT_B_WDATA[35:18];
+
+generate
+	if (PORT_B_DWIDTH == 36) begin
+		assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o};
+	end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin
+		assign PORT_B_RDATA  = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]};
+	end else if (PORT_B_DWIDTH == 9) begin
+		assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]};
+	end else begin
+		assign PORT_B_RDATA = {18'h0, RDATA_B1_o};
+	end
+endgenerate
+
+assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0];
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+};
+
+(* is_inferred = 0 *)
+(* is_split = 0 *)
+(* is_fifo = 0 *)
+(* port_a_dwidth = PORT_A_WRWIDTH *)
+(* port_b_dwidth = PORT_B_WRWIDTH *)
+TDP36K _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+
+	.CLK_A1_i(PORT_A_CLK),
+	.ADDR_A1_i(PORT_A_ADDR),
+	.WEN_A1_i(WEN_A1_i),
+	.BE_A1_i(BE_A1_i),
+	.WDATA_A1_i(WDATA_A1_i),
+	.REN_A1_i(REN_A1_i),
+	.RDATA_A1_o(RDATA_A1_o),
+
+	.CLK_A2_i(PORT_A_CLK),
+	.ADDR_A2_i(PORT_A_ADDR[13:0]),
+	.WEN_A2_i(WEN_A1_i),
+	.BE_A2_i(BE_A2_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.REN_A2_i(REN_A1_i),
+	.RDATA_A2_o(RDATA_A2_o),
+
+	.CLK_B1_i(PORT_B_CLK),
+	.ADDR_B1_i(PORT_B_ADDR),
+	.WEN_B1_i(WEN_B1_i),
+	.BE_B1_i(BE_B1_i),
+	.WDATA_B1_i(WDATA_B1_i),
+	.REN_B1_i(REN_B1_i),
+	.RDATA_B1_o(RDATA_B1_o),
+
+	.CLK_B2_i(PORT_B_CLK),
+	.ADDR_B2_i(PORT_B_ADDR[13:0]),
+	.WEN_B2_i(WEN_B1_i),
+	.BE_B2_i(BE_B2_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.REN_B2_i(REN_B1_i),
+	.RDATA_B2_o(RDATA_B2_o),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
+
+module DPRAM_18K_BLK (
+		PORT_A_CLK_i,
+		PORT_A_WEN_i,
+		PORT_A_WR_BE_i,
+		PORT_A_REN_i,
+		PORT_A_ADDR_i,
+		PORT_A_WR_DATA_i,
+		PORT_A_RD_DATA_o,
+
+		PORT_B_CLK_i,
+		PORT_B_WEN_i,
+		PORT_B_WR_BE_i,
+		PORT_B_REN_i,
+		PORT_B_ADDR_i,
+		PORT_B_WR_DATA_i,
+		PORT_B_RD_DATA_o
+);
+
+parameter PORT_A_AWIDTH = 10;
+parameter PORT_A_DWIDTH = 36;
+parameter PORT_A_WR_BE_WIDTH = 4;
+
+parameter PORT_B_AWIDTH = 10;
+parameter PORT_B_DWIDTH = 36;
+parameter PORT_B_WR_BE_WIDTH = 4;
+
+input PORT_A_CLK_i;
+input [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i;
+input [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i;
+input PORT_A_WEN_i;
+input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i;
+input PORT_A_REN_i;
+output [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o;
+
+input PORT_B_CLK_i;
+input [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i;
+input [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i;
+input PORT_B_WEN_i;
+input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i;
+input PORT_B_REN_i;
+output [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o;
+
+
+(* is_inferred = 0 *)
+(* is_split = 0 *)
+(* is_fifo = 0 *)
+BRAM2x18_dP #(
+	.PORT_A1_AWIDTH(PORT_A_AWIDTH),
+	.PORT_A1_DWIDTH(PORT_A_DWIDTH),
+	.PORT_A1_WR_BE_WIDTH(PORT_A_WR_BE_WIDTH),
+	.PORT_B1_AWIDTH(PORT_B_AWIDTH),
+	.PORT_B1_DWIDTH(PORT_B_DWIDTH),
+	.PORT_B1_WR_BE_WIDTH(PORT_B_WR_BE_WIDTH),
+	.PORT_A2_AWIDTH(),
+	.PORT_A2_DWIDTH(),
+	.PORT_A2_WR_BE_WIDTH(),
+	.PORT_B2_AWIDTH(),
+	.PORT_B2_DWIDTH(),
+	.PORT_B2_WR_BE_WIDTH()
+) U1 (
+		.PORT_A1_CLK_i(PORT_A_CLK_i),
+		.PORT_A1_WEN_i(PORT_A_WEN_i),
+		.PORT_A1_WR_BE_i(PORT_A_WR_BE_i),
+		.PORT_A1_REN_i(PORT_A_REN_i),
+		.PORT_A1_ADDR_i(PORT_A_ADDR_i),
+		.PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i),
+		.PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o),
+
+		.PORT_B1_CLK_i(PORT_B_CLK_i),
+		.PORT_B1_WEN_i(PORT_B_WEN_i),
+		.PORT_B1_WR_BE_i(PORT_B_WR_BE_i),
+		.PORT_B1_REN_i(PORT_B_REN_i),
+		.PORT_B1_ADDR_i(PORT_B_ADDR_i),
+		.PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i),
+		.PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o),
+
+		.PORT_A2_CLK_i(1'b0),
+		.PORT_A2_WEN_i(1'b0),
+		.PORT_A2_WR_BE_i(2'b00),
+		.PORT_A2_REN_i(1'b0),
+		.PORT_A2_ADDR_i(14'h0),
+		.PORT_A2_WR_DATA_i(18'h0),
+		.PORT_A2_RD_DATA_o(),
+
+		.PORT_B2_CLK_i(1'b0),
+		.PORT_B2_WEN_i(1'b0),
+		.PORT_B2_WR_BE_i(2'b00),
+		.PORT_B2_REN_i(1'b0),
+		.PORT_B2_ADDR_i(14'h0),
+		.PORT_B2_WR_DATA_i(18'h0),
+		.PORT_B2_RD_DATA_o()
+);
+
+endmodule
+
+
+module DPRAM_18K_X2_BLK (
+		PORT_A1_CLK_i,
+		PORT_A1_WEN_i,
+		PORT_A1_WR_BE_i,
+		PORT_A1_REN_i,
+		PORT_A1_ADDR_i,
+		PORT_A1_WR_DATA_i,
+		PORT_A1_RD_DATA_o,
+
+		PORT_B1_CLK_i,
+		PORT_B1_WEN_i,
+		PORT_B1_WR_BE_i,
+		PORT_B1_REN_i,
+		PORT_B1_ADDR_i,
+		PORT_B1_WR_DATA_i,
+		PORT_B1_RD_DATA_o,
+
+		PORT_A2_CLK_i,
+		PORT_A2_WEN_i,
+		PORT_A2_WR_BE_i,
+		PORT_A2_REN_i,
+		PORT_A2_ADDR_i,
+		PORT_A2_WR_DATA_i,
+		PORT_A2_RD_DATA_o,
+
+		PORT_B2_CLK_i,
+		PORT_B2_WEN_i,
+		PORT_B2_WR_BE_i,
+		PORT_B2_REN_i,
+		PORT_B2_ADDR_i,
+		PORT_B2_WR_DATA_i,
+		PORT_B2_RD_DATA_o
+);
+
+parameter PORT_A1_AWIDTH = 10;
+parameter PORT_A1_DWIDTH = 18;
+parameter PORT_A1_WR_BE_WIDTH = 2;
+
+parameter PORT_B1_AWIDTH = 10;
+parameter PORT_B1_DWIDTH = 18;
+parameter PORT_B1_WR_BE_WIDTH = 2;
+
+parameter PORT_A2_AWIDTH = 10;
+parameter PORT_A2_DWIDTH = 18;
+parameter PORT_A2_WR_BE_WIDTH = 2;
+
+parameter PORT_B2_AWIDTH = 10;
+parameter PORT_B2_DWIDTH = 18;
+parameter PORT_B2_WR_BE_WIDTH = 2;
+
+
+input PORT_A1_CLK_i;
+input [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i;
+input [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i;
+input PORT_A1_WEN_i;
+input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i;
+input PORT_A1_REN_i;
+output [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o;
+
+input PORT_B1_CLK_i;
+input [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i;
+input [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i;
+input PORT_B1_WEN_i;
+input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i;
+input PORT_B1_REN_i;
+output [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o;
+
+input PORT_A2_CLK_i;
+input [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i;
+input [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i;
+input PORT_A2_WEN_i;
+input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i;
+input PORT_A2_REN_i;
+output [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o;
+
+input PORT_B2_CLK_i;
+input [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i;
+input [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i;
+input PORT_B2_WEN_i;
+input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i;
+input PORT_B2_REN_i;
+output [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o;
+
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+32, 36: mode = 3'b011;
+default: mode = 3'b000;
+endcase
+endfunction
+
+function integer rwmode;
+input integer rwwidth;
+case (rwwidth)
+1: rwmode = 1;
+2: rwmode = 2;
+4: rwmode = 4;
+8,9: rwmode = 9;
+16, 18: rwmode = 18;
+default: rwmode = 18;
+endcase
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+wire [1:0] PORT_A1_WR_BE;
+wire [1:0] PORT_B1_WR_BE;
+
+wire [1:0] PORT_A2_WR_BE;
+wire [1:0] PORT_B2_WR_BE;
+
+wire [17:0] PORT_B1_WDATA;
+wire [17:0] PORT_B1_RDATA;
+wire [17:0] PORT_A1_WDATA;
+wire [17:0] PORT_A1_RDATA;
+
+wire [17:0] PORT_B2_WDATA;
+wire [17:0] PORT_B2_RDATA;
+wire [17:0] PORT_A2_WDATA;
+wire [17:0] PORT_A2_RDATA;
+
+wire [13:0] PORT_A1_ADDR_INT;
+wire [13:0] PORT_B1_ADDR_INT;
+
+wire [13:0] PORT_A2_ADDR_INT;
+wire [13:0] PORT_B2_ADDR_INT;
+
+wire [13:0] PORT_A1_ADDR;
+wire [13:0] PORT_B1_ADDR;
+
+wire [13:0] PORT_A2_ADDR;
+wire [13:0] PORT_B2_ADDR;
+
+wire PORT_A1_CLK;
+wire PORT_B1_CLK;
+
+wire PORT_A2_CLK;
+wire PORT_B2_CLK;
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(PORT_A1_DWIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(PORT_A1_DWIDTH);
+localparam [ 2:0] RMODE_A2_i    = mode(PORT_A2_DWIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(PORT_A2_DWIDTH);
+
+localparam [ 2:0] RMODE_B1_i    = mode(PORT_B1_DWIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(PORT_B1_DWIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(PORT_B2_DWIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(PORT_B2_DWIDTH);
+
+localparam PORT_A1_WRWIDTH = rwmode(PORT_A1_DWIDTH);
+localparam PORT_B1_WRWIDTH = rwmode(PORT_B1_DWIDTH);
+localparam PORT_A2_WRWIDTH = rwmode(PORT_A2_DWIDTH);
+localparam PORT_B2_WRWIDTH = rwmode(PORT_B2_DWIDTH);
+
+assign PORT_A1_CLK = PORT_A1_CLK_i;
+assign PORT_B1_CLK = PORT_B1_CLK_i;
+
+assign PORT_A2_CLK = PORT_A2_CLK_i;
+assign PORT_B2_CLK = PORT_B2_CLK_i;
+
+generate
+	if (PORT_A1_AWIDTH == 14) begin
+		assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i;
+	end else begin
+		assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0;
+		assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i;
+	end
+endgenerate
+
+case (PORT_A1_DWIDTH)
+	1: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_B1_AWIDTH == 14) begin
+		assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i;
+	end else begin
+		assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0;
+		assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i;
+	end
+endgenerate
+
+case (PORT_B1_DWIDTH)
+	1: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_A2_AWIDTH == 14) begin
+		assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i;
+	end else begin
+		assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0;
+		assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i;
+	end
+endgenerate
+
+case (PORT_A2_DWIDTH)
+	1: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_B2_AWIDTH == 14) begin
+		assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i;
+	end else begin
+		assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0;
+		assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i;
+	end
+endgenerate
+
+case (PORT_B2_DWIDTH)
+	1: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT;
+	end
+endcase
+
+case (PORT_A1_WR_BE_WIDTH)
+	2: begin
+		assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0;
+		assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_B1_WR_BE_WIDTH)
+	2: begin
+		assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0;
+		assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_A2_WR_BE_WIDTH)
+	2: begin
+		assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0;
+		assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_B2_WR_BE_WIDTH)
+	2: begin
+		assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0;
+		assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+assign REN_A1_i = PORT_A1_REN_i;
+assign WEN_A1_i = PORT_A1_WEN_i;
+assign BE_A1_i  = PORT_A1_WR_BE;
+
+assign REN_A2_i = PORT_A2_REN_i;
+assign WEN_A2_i = PORT_A2_WEN_i;
+assign BE_A2_i  = PORT_A2_WR_BE;
+
+assign REN_B1_i = PORT_B1_REN_i;
+assign WEN_B1_i = PORT_B1_WEN_i;
+assign BE_B1_i  = PORT_B1_WR_BE;
+
+assign REN_B2_i = PORT_B2_REN_i;
+assign WEN_B2_i = PORT_B2_WEN_i;
+assign BE_B2_i  = PORT_B2_WR_BE;
+
+generate
+	if (PORT_A1_DWIDTH == 18) begin
+		assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0];
+	end else if (PORT_A1_DWIDTH == 9) begin
+		assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0;
+		assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A1_i = PORT_A1_WDATA;
+
+generate
+	if (PORT_A2_DWIDTH == 18) begin
+		assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0];
+	end else if (PORT_A2_DWIDTH == 9) begin
+		assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0;
+		assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A2_i = PORT_A2_WDATA;
+
+generate
+	if (PORT_A1_DWIDTH == 9) begin
+		assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]};
+	end else begin
+		assign PORT_A1_RDATA = RDATA_A1_o;
+	end
+endgenerate
+
+assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0];
+
+generate
+	if (PORT_A2_DWIDTH == 9) begin
+		assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]};
+	end else begin
+		assign PORT_A2_RDATA = RDATA_A2_o;
+	end
+endgenerate
+
+assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0];
+
+generate
+	if (PORT_B1_DWIDTH == 18) begin
+		assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0];
+	end else if (PORT_B1_DWIDTH == 9) begin
+		assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0;
+		assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_B1_i = PORT_B1_WDATA;
+
+generate
+	if (PORT_B2_DWIDTH == 18) begin
+		assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0];
+	end else if (PORT_B2_DWIDTH == 9) begin
+		assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0;
+		assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_B2_i = PORT_B2_WDATA;
+
+generate
+	if (PORT_B1_DWIDTH == 9) begin
+		assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]};
+	end else begin
+		assign PORT_B1_RDATA = RDATA_B1_o;
+	end
+endgenerate
+
+assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0];
+
+generate
+	if (PORT_B2_DWIDTH == 9) begin
+		assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]};
+	end else begin
+		assign PORT_B2_RDATA = RDATA_B2_o;
+	end
+endgenerate
+
+assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0];
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+};
+
+(* is_inferred = 0 *)
+(* is_split = 1 *)
+(* is_fifo = 0 *)
+(* port_a1_dwidth = PORT_A1_WRWIDTH *)
+(* port_a2_dwidth = PORT_A2_WRWIDTH *)
+(* port_b1_dwidth = PORT_B1_WRWIDTH *)
+(* port_b2_dwidth = PORT_B2_WRWIDTH *)
+TDP36K _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+
+	.CLK_A1_i(PORT_A1_CLK),
+	.ADDR_A1_i({1'b0,PORT_A1_ADDR}),
+	.WEN_A1_i(WEN_A1_i),
+	.BE_A1_i(BE_A1_i),
+	.WDATA_A1_i(WDATA_A1_i),
+	.REN_A1_i(REN_A1_i),
+	.RDATA_A1_o(RDATA_A1_o),
+
+	.CLK_A2_i(PORT_A2_CLK),
+	.ADDR_A2_i(PORT_A2_ADDR),
+	.WEN_A2_i(WEN_A2_i),
+	.BE_A2_i(BE_A2_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.REN_A2_i(REN_A2_i),
+	.RDATA_A2_o(RDATA_A2_o),
+
+	.CLK_B1_i(PORT_B1_CLK),
+	.ADDR_B1_i({1'b0,PORT_B1_ADDR}),
+	.WEN_B1_i(WEN_B1_i),
+	.BE_B1_i(BE_B1_i),
+	.WDATA_B1_i(WDATA_B1_i),
+	.REN_B1_i(REN_B1_i),
+	.RDATA_B1_o(RDATA_B1_o),
+
+	.CLK_B2_i(PORT_B2_CLK),
+	.ADDR_B2_i(PORT_B2_ADDR),
+	.WEN_B2_i(WEN_B2_i),
+	.BE_B2_i(BE_B2_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.REN_B2_i(REN_B2_i),
+	.RDATA_B2_o(RDATA_B2_o),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
+
+module SFIFO_36K_BLK (
+		DIN,
+		PUSH,
+		POP,
+		CLK,
+		Async_Flush,
+		Overrun_Error,
+		Full_Watermark,
+		Almost_Full,
+		Full,
+		Underrun_Error,
+		Empty_Watermark,
+		Almost_Empty,
+		Empty,
+		DOUT
+);
+
+	parameter WR_DATA_WIDTH = 36;
+	parameter RD_DATA_WIDTH = 36;
+	parameter UPAE_DBITS = 12'd10;
+	parameter UPAF_DBITS = 12'd10;
+
+	input wire CLK;
+	input wire PUSH, POP;
+	input wire [WR_DATA_WIDTH-1:0] DIN;
+	input wire Async_Flush;
+	output wire [RD_DATA_WIDTH-1:0] DOUT;
+	output wire Almost_Full, Almost_Empty;
+	output wire Full, Empty;
+	output wire Full_Watermark, Empty_Watermark;
+	output wire Overrun_Error, Underrun_Error;
+
+	// Fixed mode settings
+	localparam [ 0:0] SYNC_FIFO1_i  = 1'd1;
+	localparam [ 0:0] FMODE1_i      = 1'd1;
+	localparam [ 0:0] POWERDN1_i    = 1'd0;
+	localparam [ 0:0] SLEEP1_i      = 1'd0;
+	localparam [ 0:0] PROTECT1_i    = 1'd0;
+	localparam [11:0] UPAE1_i       = UPAE_DBITS;
+	localparam [11:0] UPAF1_i       = UPAF_DBITS;
+
+	localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+	localparam [ 0:0] FMODE2_i      = 1'd0;
+	localparam [ 0:0] POWERDN2_i    = 1'd0;
+	localparam [ 0:0] SLEEP2_i      = 1'd0;
+	localparam [ 0:0] PROTECT2_i    = 1'd0;
+	localparam [10:0] UPAE2_i       = 11'd10;
+	localparam [10:0] UPAF2_i       = 11'd10;
+
+	// Width mode function
+	function [2:0] mode;
+	input integer width;
+	case (width)
+	1: mode = 3'b101;
+	2: mode = 3'b110;
+	4: mode = 3'b100;
+	8,9: mode = 3'b001;
+	16, 18: mode = 3'b010;
+	32, 36: mode = 3'b011;
+	default: mode = 3'b000;
+	endcase
+	endfunction
+
+	function integer rwmode;
+	input integer rwwidth;
+	case (rwwidth)
+	1: rwmode = 1;
+	2: rwmode = 2;
+	4: rwmode = 4;
+	8,9: rwmode = 9;
+	16, 18: rwmode = 18;
+	32, 36: rwmode = 36;
+	default: rwmode = 36;
+	endcase
+	endfunction
+
+	wire [35:0] in_reg;
+	wire [35:0] out_reg;
+	wire [17:0] fifo_flags;
+
+	wire [35:0] RD_DATA_INT;
+
+	wire Push_Clk, Pop_Clk;
+
+	assign Push_Clk = CLK;
+	assign Pop_Clk = CLK;
+
+	assign Overrun_Error = fifo_flags[0];
+	assign Full_Watermark = fifo_flags[1];
+	assign Almost_Full = fifo_flags[2];
+	assign Full = fifo_flags[3];
+	assign Underrun_Error = fifo_flags[4];
+	assign Empty_Watermark = fifo_flags[5];
+	assign Almost_Empty = fifo_flags[6];
+	assign Empty = fifo_flags[7];
+
+	localparam [ 2:0] RMODE_A1_i    = mode(WR_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A1_i    = mode(WR_DATA_WIDTH);
+	localparam [ 2:0] RMODE_A2_i    = mode(WR_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A2_i    = mode(WR_DATA_WIDTH);
+
+	localparam [ 2:0] RMODE_B1_i    = mode(RD_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B1_i    = mode(RD_DATA_WIDTH);
+	localparam [ 2:0] RMODE_B2_i    = mode(RD_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B2_i    = mode(RD_DATA_WIDTH);
+
+	localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH);
+	localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH);
+
+	generate
+		if (WR_DATA_WIDTH == 36) begin
+			assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+		end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin
+			assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16];
+			assign in_reg[17:0] = {2'b00,DIN[15:0]};
+		end else if (WR_DATA_WIDTH == 9) begin
+			assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]};
+		end else begin
+			assign in_reg[35:WR_DATA_WIDTH]  = 0;
+			assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD_DATA_WIDTH == 36) begin
+			assign RD_DATA_INT = out_reg;
+		end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin
+			assign RD_DATA_INT  = {2'b00,out_reg[35:18],out_reg[15:0]};
+		end else if (RD_DATA_WIDTH == 9) begin
+			assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]};
+		end else begin
+			assign RD_DATA_INT = {18'h0, out_reg[17:0]};
+		end
+	endgenerate
+
+	assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0];
+
+	defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+	};
+
+	(* is_fifo = 1 *)
+	(* sync_fifo = 1 *)
+	(* is_inferred = 0 *)
+	(* is_split = 0 *)
+	(* port_a_dwidth = PORT_A_WRWIDTH *)
+	(* port_b_dwidth = PORT_B_WRWIDTH *)
+	 TDP36K _TECHMAP_REPLACE_ (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg[17:0]),
+		.WDATA_A2_i(in_reg[35:18]),
+		.RDATA_A1_o(fifo_flags),
+		.RDATA_A2_o(),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk),
+		.CLK_A2_i(1'b0),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b0),
+		.WEN_A1_i(PUSH),
+		.WEN_A2_i(1'b0),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg[17:0]),
+		.RDATA_B2_o(out_reg[35:18]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk),
+		.CLK_B2_i(1'b0),
+		.REN_B1_i(POP),
+		.REN_B2_i(1'b0),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush),
+		.FLUSH2_i(1'b0)
+	);
+
+
+
+endmodule
+
+module AFIFO_36K_BLK (
+		DIN,
+		PUSH,
+		POP,
+		Push_Clk,
+		Pop_Clk,
+		Async_Flush,
+		Overrun_Error,
+		Full_Watermark,
+		Almost_Full,
+		Full,
+		Underrun_Error,
+		Empty_Watermark,
+		Almost_Empty,
+		Empty,
+		DOUT
+);
+
+	parameter WR_DATA_WIDTH = 36;
+	parameter RD_DATA_WIDTH = 36;
+	parameter UPAE_DBITS = 12'd10;
+	parameter UPAF_DBITS = 12'd10;
+
+	input wire Push_Clk, Pop_Clk;
+	input wire PUSH, POP;
+	input wire [WR_DATA_WIDTH-1:0] DIN;
+	input wire Async_Flush;
+	output wire [RD_DATA_WIDTH-1:0] DOUT;
+	output wire Almost_Full, Almost_Empty;
+	output wire Full, Empty;
+	output wire Full_Watermark, Empty_Watermark;
+	output wire Overrun_Error, Underrun_Error;
+
+	// Fixed mode settings
+	localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+	localparam [ 0:0] FMODE1_i      = 1'd1;
+	localparam [ 0:0] POWERDN1_i    = 1'd0;
+	localparam [ 0:0] SLEEP1_i      = 1'd0;
+	localparam [ 0:0] PROTECT1_i    = 1'd0;
+	localparam [11:0] UPAE1_i       = UPAE_DBITS;
+	localparam [11:0] UPAF1_i       = UPAF_DBITS;
+
+	localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+	localparam [ 0:0] FMODE2_i      = 1'd0;
+	localparam [ 0:0] POWERDN2_i    = 1'd0;
+	localparam [ 0:0] SLEEP2_i      = 1'd0;
+	localparam [ 0:0] PROTECT2_i    = 1'd0;
+	localparam [10:0] UPAE2_i       = 11'd10;
+	localparam [10:0] UPAF2_i       = 11'd10;
+
+	// Width mode function
+	function [2:0] mode;
+	input integer width;
+	case (width)
+	1: mode = 3'b101;
+	2: mode = 3'b110;
+	4: mode = 3'b100;
+	8,9: mode = 3'b001;
+	16, 18: mode = 3'b010;
+	32, 36: mode = 3'b011;
+	default: mode = 3'b000;
+	endcase
+	endfunction
+
+	function integer rwmode;
+	input integer rwwidth;
+	case (rwwidth)
+	1: rwmode = 1;
+	2: rwmode = 2;
+	4: rwmode = 4;
+	8,9: rwmode = 9;
+	16, 18: rwmode = 18;
+	32, 36: rwmode = 36;
+	default: rwmode = 36;
+	endcase
+	endfunction
+
+	wire [35:0] in_reg;
+	wire [35:0] out_reg;
+	wire [17:0] fifo_flags;
+
+	wire [35:0] RD_DATA_INT;
+	wire [35:WR_DATA_WIDTH] WR_DATA_CMPL;
+
+	assign Overrun_Error = fifo_flags[0];
+	assign Full_Watermark = fifo_flags[1];
+	assign Almost_Full = fifo_flags[2];
+	assign Full = fifo_flags[3];
+	assign Underrun_Error = fifo_flags[4];
+	assign Empty_Watermark = fifo_flags[5];
+	assign Almost_Empty = fifo_flags[6];
+	assign Empty = fifo_flags[7];
+
+	localparam [ 2:0] RMODE_A1_i    = mode(WR_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A1_i    = mode(WR_DATA_WIDTH);
+	localparam [ 2:0] RMODE_A2_i    = mode(WR_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A2_i    = mode(WR_DATA_WIDTH);
+
+	localparam [ 2:0] RMODE_B1_i    = mode(RD_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B1_i    = mode(RD_DATA_WIDTH);
+	localparam [ 2:0] RMODE_B2_i    = mode(RD_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B2_i    = mode(RD_DATA_WIDTH);
+
+	localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH);
+	localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH);
+
+	generate
+		if (WR_DATA_WIDTH == 36) begin
+			assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+		end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin
+			assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16];
+			assign in_reg[17:0] = {2'b00,DIN[15:0]};
+		end else if (WR_DATA_WIDTH == 9) begin
+			assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]};
+		end else begin
+			assign in_reg[35:WR_DATA_WIDTH]  = 0;
+			assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD_DATA_WIDTH == 36) begin
+			assign RD_DATA_INT = out_reg;
+		end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin
+			assign RD_DATA_INT  = {2'b00,out_reg[35:18],out_reg[15:0]};
+		end else if (RD_DATA_WIDTH == 9) begin
+			assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]};
+		end else begin
+			assign RD_DATA_INT = {18'h0, out_reg[17:0]};
+		end
+	endgenerate
+
+	assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0];
+
+	defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+	};
+
+	(* is_fifo = 1 *)
+	(* sync_fifo = 0 *)
+	(* is_inferred = 0 *)
+	(* is_split = 0 *)
+	(* port_a_dwidth = PORT_A_WRWIDTH *)
+	(* port_b_dwidth = PORT_B_WRWIDTH *)
+ 	TDP36K _TECHMAP_REPLACE_ (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg[17:0]),
+		.WDATA_A2_i(in_reg[35:18]),
+		.RDATA_A1_o(fifo_flags),
+		.RDATA_A2_o(),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk),
+		.CLK_A2_i(1'b0),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b0),
+		.WEN_A1_i(PUSH),
+		.WEN_A2_i(1'b0),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg[17:0]),
+		.RDATA_B2_o(out_reg[35:18]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk),
+		.CLK_B2_i(1'b0),
+		.REN_B1_i(POP),
+		.REN_B2_i(1'b0),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush),
+		.FLUSH2_i(1'b0)
+	);
+
+
+
+endmodule
+
+module SFIFO_18K_BLK (
+		DIN,
+		PUSH,
+		POP,
+		CLK,
+		Async_Flush,
+		Overrun_Error,
+		Full_Watermark,
+		Almost_Full,
+		Full,
+		Underrun_Error,
+		Empty_Watermark,
+		Almost_Empty,
+		Empty,
+		DOUT
+);
+
+	parameter WR_DATA_WIDTH = 18;
+	parameter RD_DATA_WIDTH = 18;
+	parameter UPAE_DBITS = 11'd10;
+	parameter UPAF_DBITS = 11'd10;
+
+	input wire CLK;
+	input wire PUSH, POP;
+	input wire [WR_DATA_WIDTH-1:0] DIN;
+	input wire Async_Flush;
+	output wire [RD_DATA_WIDTH-1:0] DOUT;
+	output wire Almost_Full, Almost_Empty;
+	output wire Full, Empty;
+	output wire Full_Watermark, Empty_Watermark;
+	output wire Overrun_Error, Underrun_Error;
+
+ 	BRAM2x18_SFIFO  #(
+			.WR1_DATA_WIDTH(WR_DATA_WIDTH),
+			.RD1_DATA_WIDTH(RD_DATA_WIDTH),
+			.UPAE_DBITS1(UPAE_DBITS),
+			.UPAF_DBITS1(UPAF_DBITS),
+			.WR2_DATA_WIDTH(),
+			.RD2_DATA_WIDTH(),
+			.UPAE_DBITS2(),
+			.UPAF_DBITS2()
+			 ) U1
+			(
+			.DIN1(DIN),
+			.PUSH1(PUSH),
+			.POP1(POP),
+			.CLK1(CLK),
+			.Async_Flush1(Async_Flush),
+			.Overrun_Error1(Overrun_Error),
+			.Full_Watermark1(Full_Watermark),
+			.Almost_Full1(Almost_Full),
+			.Full1(Full),
+			.Underrun_Error1(Underrun_Error),
+			.Empty_Watermark1(Empty_Watermark),
+			.Almost_Empty1(Almost_Empty),
+			.Empty1(Empty),
+			.DOUT1(DOUT),
+
+			.DIN2(18'h0),
+			.PUSH2(1'b0),
+			.POP2(1'b0),
+			.CLK2(1'b0),
+			.Async_Flush2(1'b0),
+			.Overrun_Error2(),
+			.Full_Watermark2(),
+			.Almost_Full2(),
+			.Full2(),
+			.Underrun_Error2(),
+			.Empty_Watermark2(),
+			.Almost_Empty2(),
+			.Empty2(),
+			.DOUT2()
+	);
+
+endmodule
+
+module SFIFO_18K_X2_BLK (
+		DIN1,
+		PUSH1,
+		POP1,
+		CLK1,
+		Async_Flush1,
+		Overrun_Error1,
+		Full_Watermark1,
+		Almost_Full1,
+		Full1,
+		Underrun_Error1,
+		Empty_Watermark1,
+		Almost_Empty1,
+		Empty1,
+		DOUT1,
+
+		DIN2,
+		PUSH2,
+		POP2,
+		CLK2,
+		Async_Flush2,
+		Overrun_Error2,
+		Full_Watermark2,
+		Almost_Full2,
+		Full2,
+		Underrun_Error2,
+		Empty_Watermark2,
+		Almost_Empty2,
+		Empty2,
+		DOUT2
+);
+
+	parameter WR1_DATA_WIDTH = 18;
+	parameter RD1_DATA_WIDTH = 18;
+
+	parameter WR2_DATA_WIDTH = 18;
+	parameter RD2_DATA_WIDTH = 18;
+
+	parameter UPAE_DBITS1 = 12'd10;
+	parameter UPAF_DBITS1 = 12'd10;
+
+	parameter UPAE_DBITS2 = 11'd10;
+	parameter UPAF_DBITS2 = 11'd10;
+
+	input CLK1;
+	input PUSH1, POP1;
+	input [WR1_DATA_WIDTH-1:0] DIN1;
+	input Async_Flush1;
+	output [RD1_DATA_WIDTH-1:0] DOUT1;
+	output Almost_Full1, Almost_Empty1;
+	output Full1, Empty1;
+	output Full_Watermark1, Empty_Watermark1;
+	output Overrun_Error1, Underrun_Error1;
+
+	input CLK2;
+	input PUSH2, POP2;
+	input [WR2_DATA_WIDTH-1:0] DIN2;
+	input Async_Flush2;
+	output [RD2_DATA_WIDTH-1:0] DOUT2;
+	output Almost_Full2, Almost_Empty2;
+	output Full2, Empty2;
+	output Full_Watermark2, Empty_Watermark2;
+	output Overrun_Error2, Underrun_Error2;
+
+	// Fixed mode settings
+	localparam [ 0:0] SYNC_FIFO1_i  = 1'd1;
+	localparam [ 0:0] FMODE1_i      = 1'd1;
+	localparam [ 0:0] POWERDN1_i    = 1'd0;
+	localparam [ 0:0] SLEEP1_i      = 1'd0;
+	localparam [ 0:0] PROTECT1_i    = 1'd0;
+	localparam [11:0] UPAE1_i       = UPAE_DBITS1;
+	localparam [11:0] UPAF1_i       = UPAF_DBITS1;
+
+	localparam [ 0:0] SYNC_FIFO2_i  = 1'd1;
+	localparam [ 0:0] FMODE2_i      = 1'd1;
+	localparam [ 0:0] POWERDN2_i    = 1'd0;
+	localparam [ 0:0] SLEEP2_i      = 1'd0;
+	localparam [ 0:0] PROTECT2_i    = 1'd0;
+	localparam [10:0] UPAE2_i       = UPAE_DBITS2;
+	localparam [10:0] UPAF2_i       = UPAF_DBITS2;
+
+	// Width mode function
+	function [2:0] mode;
+	input integer width;
+	case (width)
+	1: mode = 3'b101;
+	2: mode = 3'b110;
+	4: mode = 3'b100;
+	8,9: mode = 3'b001;
+	16, 18: mode = 3'b010;
+	32, 36: mode = 3'b011;
+	default: mode = 3'b000;
+	endcase
+	endfunction
+
+	function integer rwmode;
+	input integer rwwidth;
+	case (rwwidth)
+	1: rwmode = 1;
+	2: rwmode = 2;
+	4: rwmode = 4;
+	8,9: rwmode = 9;
+	16, 18: rwmode = 18;
+	default: rwmode = 18;
+	endcase
+	endfunction
+
+	wire [17:0] in_reg1;
+	wire [17:0] out_reg1;
+	wire [17:0] fifo1_flags;
+
+	wire [17:0] in_reg2;
+	wire [17:0] out_reg2;
+	wire [17:0] fifo2_flags;
+
+	wire Push_Clk1, Pop_Clk1;
+	wire Push_Clk2, Pop_Clk2;
+	assign Push_Clk1 = CLK1;
+	assign Pop_Clk1 = CLK1;
+	assign Push_Clk2 = CLK2;
+	assign Pop_Clk2 = CLK2;
+
+	assign Overrun_Error1 = fifo1_flags[0];
+	assign Full_Watermark1 = fifo1_flags[1];
+	assign Almost_Full1 = fifo1_flags[2];
+	assign Full1 = fifo1_flags[3];
+	assign Underrun_Error1 = fifo1_flags[4];
+	assign Empty_Watermark1 = fifo1_flags[5];
+	assign Almost_Empty1 = fifo1_flags[6];
+	assign Empty1 = fifo1_flags[7];
+
+	assign Overrun_Error2 = fifo2_flags[0];
+	assign Full_Watermark2 = fifo2_flags[1];
+	assign Almost_Full2 = fifo2_flags[2];
+	assign Full2 = fifo2_flags[3];
+	assign Underrun_Error2 = fifo2_flags[4];
+	assign Empty_Watermark2 = fifo2_flags[5];
+	assign Almost_Empty2 = fifo2_flags[6];
+	assign Empty2 = fifo2_flags[7];
+
+	localparam [ 2:0] RMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_A2_i    = mode(WR2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A2_i    = mode(WR2_DATA_WIDTH);
+
+	localparam [ 2:0] RMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_B2_i    = mode(RD2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B2_i    = mode(RD2_DATA_WIDTH);
+
+	localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH);
+	localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH);
+	localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH);
+	localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH);
+
+	generate
+		if (WR1_DATA_WIDTH == 18) begin
+			assign in_reg1[17:0] = DIN1[17:0];
+		end else if (WR1_DATA_WIDTH == 9) begin
+			assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]};
+		end else begin
+			assign in_reg1[17:WR1_DATA_WIDTH]  = 0;
+			assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD1_DATA_WIDTH == 9) begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]};
+		end else begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (WR2_DATA_WIDTH == 18) begin
+			assign in_reg2[17:0] = DIN2[17:0];
+		end else if (WR2_DATA_WIDTH == 9) begin
+			assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]};
+		end else begin
+			assign in_reg2[17:WR2_DATA_WIDTH]  = 0;
+			assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD2_DATA_WIDTH == 9) begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]};
+		end else begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+	};
+
+	(* is_fifo = 1 *)
+	(* sync_fifo = 1 *)
+	(* is_split = 1 *)
+	(* is_inferred = 0 *)
+	(* port_a1_dwidth = PORT_A1_WRWIDTH *)
+	(* port_a2_dwidth = PORT_A2_WRWIDTH *)
+	(* port_b1_dwidth = PORT_B1_WRWIDTH *)
+	(* port_b2_dwidth = PORT_B2_WRWIDTH *)
+ 	TDP36K _TECHMAP_REPLACE_ (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg1[17:0]),
+		.WDATA_A2_i(in_reg2[17:0]),
+		.RDATA_A1_o(fifo1_flags),
+		.RDATA_A2_o(fifo2_flags),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk1),
+		.CLK_A2_i(Push_Clk2),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b1),
+		.WEN_A1_i(PUSH1),
+		.WEN_A2_i(PUSH2),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg1[17:0]),
+		.RDATA_B2_o(out_reg2[17:0]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk1),
+		.CLK_B2_i(Pop_Clk2),
+		.REN_B1_i(POP1),
+		.REN_B2_i(POP2),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush1),
+		.FLUSH2_i(Async_Flush2)
+	);
+
+endmodule
+
+module AFIFO_18K_BLK (
+		DIN,
+		PUSH,
+		POP,
+		Push_Clk,
+		Pop_Clk,
+		Async_Flush,
+		Overrun_Error,
+		Full_Watermark,
+		Almost_Full,
+		Full,
+		Underrun_Error,
+		Empty_Watermark,
+		Almost_Empty,
+		Empty,
+		DOUT
+);
+
+	parameter WR_DATA_WIDTH = 18;
+	parameter RD_DATA_WIDTH = 18;
+	parameter UPAE_DBITS = 11'd10;
+	parameter UPAF_DBITS = 11'd10;
+
+	input wire Push_Clk, Pop_Clk;
+	input wire PUSH, POP;
+	input wire [WR_DATA_WIDTH-1:0] DIN;
+	input wire Async_Flush;
+	output wire [RD_DATA_WIDTH-1:0] DOUT;
+	output wire Almost_Full, Almost_Empty;
+	output wire Full, Empty;
+	output wire Full_Watermark, Empty_Watermark;
+	output wire Overrun_Error, Underrun_Error;
+
+ 	BRAM2x18_AFIFO  #(
+			.WR1_DATA_WIDTH(WR_DATA_WIDTH),
+			.RD1_DATA_WIDTH(RD_DATA_WIDTH),
+			.UPAE_DBITS1(UPAE_DBITS),
+			.UPAF_DBITS1(UPAF_DBITS),
+			.WR2_DATA_WIDTH(),
+			.RD2_DATA_WIDTH(),
+			.UPAE_DBITS2(),
+			.UPAF_DBITS2()
+			 ) U1
+			(
+			.DIN1(DIN),
+			.PUSH1(PUSH),
+			.POP1(POP),
+			.Push_Clk1(Push_Clk),
+			.Pop_Clk1(Pop_Clk),
+			.Async_Flush1(Async_Flush),
+			.Overrun_Error1(Overrun_Error),
+			.Full_Watermark1(Full_Watermark),
+			.Almost_Full1(Almost_Full),
+			.Full1(Full),
+			.Underrun_Error1(Underrun_Error),
+			.Empty_Watermark1(Empty_Watermark),
+			.Almost_Empty1(Almost_Empty),
+			.Empty1(Empty),
+			.DOUT1(DOUT),
+
+			.DIN2(18'h0),
+			.PUSH2(1'b0),
+			.POP2(1'b0),
+			.Push_Clk2(1'b0),
+			.Pop_Clk2(1'b0),
+			.Async_Flush2(1'b0),
+			.Overrun_Error2(),
+			.Full_Watermark2(),
+			.Almost_Full2(),
+			.Full2(),
+			.Underrun_Error2(),
+			.Empty_Watermark2(),
+			.Almost_Empty2(),
+			.Empty2(),
+			.DOUT2()
+	);
+
+endmodule
+
+module AFIFO_18K_X2_BLK (
+		DIN1,
+		PUSH1,
+		POP1,
+		Push_Clk1,
+	Pop_Clk1,
+		Async_Flush1,
+		Overrun_Error1,
+		Full_Watermark1,
+		Almost_Full1,
+		Full1,
+		Underrun_Error1,
+		Empty_Watermark1,
+		Almost_Empty1,
+		Empty1,
+		DOUT1,
+
+		DIN2,
+		PUSH2,
+		POP2,
+		Push_Clk2,
+	Pop_Clk2,
+		Async_Flush2,
+		Overrun_Error2,
+		Full_Watermark2,
+		Almost_Full2,
+		Full2,
+		Underrun_Error2,
+		Empty_Watermark2,
+		Almost_Empty2,
+		Empty2,
+		DOUT2
+);
+
+	parameter WR1_DATA_WIDTH = 18;
+	parameter RD1_DATA_WIDTH = 18;
+
+	parameter WR2_DATA_WIDTH = 18;
+	parameter RD2_DATA_WIDTH = 18;
+
+	parameter UPAE_DBITS1 = 12'd10;
+	parameter UPAF_DBITS1 = 12'd10;
+
+	parameter UPAE_DBITS2 = 11'd10;
+	parameter UPAF_DBITS2 = 11'd10;
+
+	input Push_Clk1, Pop_Clk1;
+	input PUSH1, POP1;
+	input [WR1_DATA_WIDTH-1:0] DIN1;
+	input Async_Flush1;
+	output [RD1_DATA_WIDTH-1:0] DOUT1;
+	output Almost_Full1, Almost_Empty1;
+	output Full1, Empty1;
+	output Full_Watermark1, Empty_Watermark1;
+	output Overrun_Error1, Underrun_Error1;
+
+	input Push_Clk2, Pop_Clk2;
+	input PUSH2, POP2;
+	input [WR2_DATA_WIDTH-1:0] DIN2;
+	input Async_Flush2;
+	output [RD2_DATA_WIDTH-1:0] DOUT2;
+	output Almost_Full2, Almost_Empty2;
+	output Full2, Empty2;
+	output Full_Watermark2, Empty_Watermark2;
+	output Overrun_Error2, Underrun_Error2;
+
+	// Fixed mode settings
+	localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+	localparam [ 0:0] FMODE1_i      = 1'd1;
+	localparam [ 0:0] POWERDN1_i    = 1'd0;
+	localparam [ 0:0] SLEEP1_i      = 1'd0;
+	localparam [ 0:0] PROTECT1_i    = 1'd0;
+	localparam [11:0] UPAE1_i       = UPAE_DBITS1;
+	localparam [11:0] UPAF1_i       = UPAF_DBITS1;
+
+	localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+	localparam [ 0:0] FMODE2_i      = 1'd1;
+	localparam [ 0:0] POWERDN2_i    = 1'd0;
+	localparam [ 0:0] SLEEP2_i      = 1'd0;
+	localparam [ 0:0] PROTECT2_i    = 1'd0;
+	localparam [10:0] UPAE2_i       = UPAE_DBITS2;
+	localparam [10:0] UPAF2_i       = UPAF_DBITS2;
+
+	// Width mode function
+	function [2:0] mode;
+	input integer width;
+	case (width)
+	1: mode = 3'b101;
+	2: mode = 3'b110;
+	4: mode = 3'b100;
+	8,9: mode = 3'b001;
+	16, 18: mode = 3'b010;
+	32, 36: mode = 3'b011;
+	default: mode = 3'b000;
+	endcase
+	endfunction
+
+	function integer rwmode;
+	input integer rwwidth;
+	case (rwwidth)
+	1: rwmode = 1;
+	2: rwmode = 2;
+	4: rwmode = 4;
+	8,9: rwmode = 9;
+	16, 18: rwmode = 18;
+	default: rwmode = 18;
+	endcase
+	endfunction
+
+	wire [17:0] in_reg1;
+	wire [17:0] out_reg1;
+	wire [17:0] fifo1_flags;
+
+	wire [17:0] in_reg2;
+	wire [17:0] out_reg2;
+	wire [17:0] fifo2_flags;
+
+	wire Push_Clk1, Pop_Clk1;
+	wire Push_Clk2, Pop_Clk2;
+
+	assign Overrun_Error1 = fifo1_flags[0];
+	assign Full_Watermark1 = fifo1_flags[1];
+	assign Almost_Full1 = fifo1_flags[2];
+	assign Full1 = fifo1_flags[3];
+	assign Underrun_Error1 = fifo1_flags[4];
+	assign Empty_Watermark1 = fifo1_flags[5];
+	assign Almost_Empty1 = fifo1_flags[6];
+	assign Empty1 = fifo1_flags[7];
+
+	assign Overrun_Error2 = fifo2_flags[0];
+	assign Full_Watermark2 = fifo2_flags[1];
+	assign Almost_Full2 = fifo2_flags[2];
+	assign Full2 = fifo2_flags[3];
+	assign Underrun_Error2 = fifo2_flags[4];
+	assign Empty_Watermark2 = fifo2_flags[5];
+	assign Almost_Empty2 = fifo2_flags[6];
+	assign Empty2 = fifo2_flags[7];
+
+	localparam [ 2:0] RMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_A2_i    = mode(WR2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A2_i    = mode(WR2_DATA_WIDTH);
+
+	localparam [ 2:0] RMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_B2_i    = mode(RD2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B2_i    = mode(RD2_DATA_WIDTH);
+
+	localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH);
+	localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH);
+	localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH);
+	localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH);
+
+	generate
+		if (WR1_DATA_WIDTH == 18) begin
+			assign in_reg1[17:0] = DIN1[17:0];
+		end else if (WR1_DATA_WIDTH == 9) begin
+			assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]};
+		end else begin
+			assign in_reg1[17:WR1_DATA_WIDTH]  = 0;
+			assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD1_DATA_WIDTH == 9) begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]};
+		end else begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (WR2_DATA_WIDTH == 18) begin
+			assign in_reg2[17:0] = DIN2[17:0];
+		end else if (WR2_DATA_WIDTH == 9) begin
+			assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]};
+		end else begin
+			assign in_reg2[17:WR2_DATA_WIDTH]  = 0;
+			assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD2_DATA_WIDTH == 9) begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]};
+		end else begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+	};
+
+	(* is_fifo = 1 *)
+	(* sync_fifo = 0 *)
+	(* is_split = 1 *)
+	(* is_inferred = 0 *)
+	(* port_a1_dwidth = PORT_A1_WRWIDTH *)
+	(* port_a2_dwidth = PORT_A2_WRWIDTH *)
+	(* port_b1_dwidth = PORT_B1_WRWIDTH *)
+	(* port_b2_dwidth = PORT_B2_WRWIDTH *)
+ 	TDP36K _TECHMAP_REPLACE_ (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg1[17:0]),
+		.WDATA_A2_i(in_reg2[17:0]),
+		.RDATA_A1_o(fifo1_flags),
+		.RDATA_A2_o(fifo2_flags),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk1),
+		.CLK_A2_i(Push_Clk2),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b1),
+		.WEN_A1_i(PUSH1),
+		.WEN_A2_i(PUSH2),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg1[17:0]),
+		.RDATA_B2_o(out_reg2[17:0]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk1),
+		.CLK_B2_i(Pop_Clk2),
+		.REN_B1_i(POP1),
+		.REN_B2_i(POP2),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush1),
+		.FLUSH2_i(Async_Flush2)
+	);
+
+endmodule
+
+module BRAM2x18_SP (
+		RESET_ni,
+
+		WEN1_i,
+		REN1_i,
+		WR1_CLK_i,
+		RD1_CLK_i,
+		WR1_BE_i,
+		WR1_ADDR_i,
+		RD1_ADDR_i,
+		WDATA1_i,
+		RDATA1_o,
+
+		WEN2_i,
+		REN2_i,
+		WR2_CLK_i,
+		RD2_CLK_i,
+		WR2_BE_i,
+		WR2_ADDR_i,
+		RD2_ADDR_i,
+		WDATA2_i,
+		RDATA2_o
+);
+
+parameter WR1_ADDR_WIDTH = 10;
+parameter RD1_ADDR_WIDTH = 10;
+parameter WR1_DATA_WIDTH = 18;
+parameter RD1_DATA_WIDTH = 18;
+parameter BE1_WIDTH = 2;
+
+parameter WR2_ADDR_WIDTH = 10;
+parameter RD2_ADDR_WIDTH = 10;
+parameter WR2_DATA_WIDTH = 18;
+parameter RD2_DATA_WIDTH = 18;
+parameter BE2_WIDTH = 2;
+
+input wire RESET_ni;
+
+input wire WEN1_i;
+input wire REN1_i;
+input wire WR1_CLK_i;
+input wire RD1_CLK_i;
+input wire [BE1_WIDTH-1:0] WR1_BE_i;
+input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i;
+input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i;
+input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i;
+output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o;
+
+input wire WEN2_i;
+input wire REN2_i;
+input wire WR2_CLK_i;
+input wire RD2_CLK_i;
+input wire [BE2_WIDTH-1:0] WR2_BE_i;
+input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i;
+input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i;
+input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i;
+output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o;
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+32, 36: mode = 3'b011;
+default: mode = 3'b000;
+endcase
+endfunction
+
+function integer rwmode;
+input integer rwwidth;
+case (rwwidth)
+1: rwmode = 1;
+2: rwmode = 2;
+4: rwmode = 4;
+8,9: rwmode = 9;
+16, 18: rwmode = 18;
+default: rwmode = 18;
+endcase
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+wire [1:0] WR1_BE;
+wire [1:0] WR2_BE;
+
+wire [17:0] PORT_B1_RDATA;
+wire [17:0] PORT_A1_WDATA;
+
+wire [17:0] PORT_B2_RDATA;
+wire [17:0] PORT_A2_WDATA;
+
+wire [13:0] WR1_ADDR_INT;
+wire [13:0] RD1_ADDR_INT;
+
+wire [13:0] WR2_ADDR_INT;
+wire [13:0] RD2_ADDR_INT;
+
+wire [13:0] PORT_A1_ADDR;
+wire [13:0] PORT_B1_ADDR;
+
+wire [13:0] PORT_A2_ADDR;
+wire [13:0] PORT_B2_ADDR;
+
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(WR1_DATA_WIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(WR1_DATA_WIDTH);
+localparam [ 2:0] RMODE_A2_i    = mode(WR2_DATA_WIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(WR2_DATA_WIDTH);
+
+localparam [ 2:0] RMODE_B1_i    = mode(RD1_DATA_WIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(RD1_DATA_WIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(RD2_DATA_WIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(RD2_DATA_WIDTH);
+
+localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH);
+localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH);
+localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH);
+localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH);
+
+generate
+	if (WR1_ADDR_WIDTH == 14) begin
+		assign WR1_ADDR_INT = WR1_ADDR_i;
+	end else begin
+		assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0;
+		assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i;
+	end
+endgenerate
+
+case (WR1_DATA_WIDTH)
+	1: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (RD1_ADDR_WIDTH == 14) begin
+		assign RD1_ADDR_INT = RD1_ADDR_i;
+	end else begin
+		assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0;
+		assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i;
+	end
+endgenerate
+
+case (RD1_DATA_WIDTH)
+	1: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (WR2_ADDR_WIDTH == 14) begin
+		assign WR2_ADDR_INT = WR2_ADDR_i;
+	end else begin
+		assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0;
+		assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i;
+	end
+endgenerate
+
+case (WR2_DATA_WIDTH)
+	1: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT;
+	end
+endcase
+
+generate
+	if (RD2_ADDR_WIDTH == 14) begin
+		assign RD2_ADDR_INT = RD2_ADDR_i;
+	end else begin
+		assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0;
+		assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i;
+	end
+endgenerate
+
+case (RD2_DATA_WIDTH)
+	1: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT;
+	end
+endcase
+
+case (BE1_WIDTH)
+	2: begin
+		assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR1_BE[1:BE1_WIDTH] = 0;
+		assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0];
+	end
+endcase
+
+case (BE2_WIDTH)
+	2: begin
+		assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR2_BE[1:BE2_WIDTH] = 0;
+		assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0];
+	end
+endcase
+
+assign REN_A1_i = 1'b0;
+assign WEN_A1_i = WEN1_i;
+assign BE_A1_i = WR1_BE;
+assign REN_A2_i = 1'b0;
+assign WEN_A2_i = WEN2_i;
+assign BE_A2_i = WR2_BE;
+
+assign REN_B1_i = REN1_i;
+assign WEN_B1_i = 1'b0;
+assign BE_B1_i = 4'h0;
+assign REN_B2_i = REN2_i;
+assign WEN_B2_i = 1'b0;
+assign BE_B2_i = 4'h0;
+
+generate
+	if (WR1_DATA_WIDTH == 18) begin
+		assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0];
+	end else if (WR1_DATA_WIDTH == 9) begin
+		assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]};
+	end else begin
+		assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0;
+		assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A1_i = PORT_A1_WDATA[17:0];
+assign WDATA_B1_i = 18'h0;
+
+generate
+	if (RD1_DATA_WIDTH == 9) begin
+		assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]};
+	end else begin
+		assign PORT_B1_RDATA = RDATA_B1_o;
+	end
+endgenerate
+
+assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0];
+
+generate
+	if (WR2_DATA_WIDTH == 18) begin
+		assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0];
+	end else if (WR2_DATA_WIDTH == 9) begin
+		assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]};
+	end else begin
+		assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0;
+		assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A2_i = PORT_A2_WDATA[17:0];
+assign WDATA_B2_i = 18'h0;
+
+generate
+	if (RD2_DATA_WIDTH == 9) begin
+		assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]};
+	end else begin
+		assign PORT_B2_RDATA = RDATA_B2_o;
+	end
+endgenerate
+
+assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0];
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+};
+
+(* is_inferred = 0 *)
+(* is_split = 0 *)
+(* is_fifo = 0 *)
+(* port_a_dwidth = PORT_A1_WRWIDTH *)
+(* port_b_dwidth = PORT_B1_WRWIDTH *)
+TDP36K _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+
+	.CLK_A1_i(WR1_CLK_i),
+	.ADDR_A1_i({1'b0,PORT_A1_ADDR}),
+	.WEN_A1_i(WEN_A1_i),
+	.BE_A1_i(BE_A1_i),
+	.WDATA_A1_i(WDATA_A1_i),
+	.REN_A1_i(REN_A1_i),
+	.RDATA_A1_o(RDATA_A1_o),
+
+	.CLK_A2_i(WR2_CLK_i),
+	.ADDR_A2_i(PORT_A2_ADDR),
+	.WEN_A2_i(WEN_A2_i),
+	.BE_A2_i(BE_A2_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.REN_A2_i(REN_A2_i),
+	.RDATA_A2_o(RDATA_A2_o),
+
+	.CLK_B1_i(RD1_CLK_i),
+	.ADDR_B1_i({1'b0,PORT_B1_ADDR}),
+	.WEN_B1_i(WEN_B1_i),
+	.BE_B1_i(BE_B1_i),
+	.WDATA_B1_i(WDATA_B1_i),
+	.REN_B1_i(REN_B1_i),
+	.RDATA_B1_o(RDATA_B1_o),
+
+	.CLK_B2_i(RD2_CLK_i),
+	.ADDR_B2_i(PORT_B2_ADDR),
+	.WEN_B2_i(WEN_B2_i),
+	.BE_B2_i(BE_B2_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.REN_B2_i(REN_B2_i),
+	.RDATA_B2_o(RDATA_B2_o),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
+
+module BRAM2x18_dP (
+		PORT_A1_CLK_i,
+		PORT_A1_WEN_i,
+		PORT_A1_WR_BE_i,
+		PORT_A1_REN_i,
+		PORT_A1_ADDR_i,
+		PORT_A1_WR_DATA_i,
+		PORT_A1_RD_DATA_o,
+
+		PORT_B1_CLK_i,
+		PORT_B1_WEN_i,
+		PORT_B1_WR_BE_i,
+		PORT_B1_REN_i,
+		PORT_B1_ADDR_i,
+		PORT_B1_WR_DATA_i,
+		PORT_B1_RD_DATA_o,
+
+		PORT_A2_CLK_i,
+		PORT_A2_WEN_i,
+		PORT_A2_WR_BE_i,
+		PORT_A2_REN_i,
+		PORT_A2_ADDR_i,
+		PORT_A2_WR_DATA_i,
+		PORT_A2_RD_DATA_o,
+
+		PORT_B2_CLK_i,
+		PORT_B2_WEN_i,
+		PORT_B2_WR_BE_i,
+		PORT_B2_REN_i,
+		PORT_B2_ADDR_i,
+		PORT_B2_WR_DATA_i,
+		PORT_B2_RD_DATA_o
+);
+
+parameter PORT_A1_AWIDTH = 10;
+parameter PORT_A1_DWIDTH = 18;
+parameter PORT_A1_WR_BE_WIDTH = 2;
+
+parameter PORT_B1_AWIDTH = 10;
+parameter PORT_B1_DWIDTH = 18;
+parameter PORT_B1_WR_BE_WIDTH = 2;
+
+parameter PORT_A2_AWIDTH = 10;
+parameter PORT_A2_DWIDTH = 18;
+parameter PORT_A2_WR_BE_WIDTH = 2;
+
+parameter PORT_B2_AWIDTH = 10;
+parameter PORT_B2_DWIDTH = 18;
+parameter PORT_B2_WR_BE_WIDTH = 2;
+
+input PORT_A1_CLK_i;
+input [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i;
+input [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i;
+input PORT_A1_WEN_i;
+input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i;
+input PORT_A1_REN_i;
+output [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o;
+
+input PORT_B1_CLK_i;
+input [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i;
+input [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i;
+input PORT_B1_WEN_i;
+input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i;
+input PORT_B1_REN_i;
+output [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o;
+
+input PORT_A2_CLK_i;
+input [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i;
+input [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i;
+input PORT_A2_WEN_i;
+input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i;
+input PORT_A2_REN_i;
+output [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o;
+
+input PORT_B2_CLK_i;
+input [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i;
+input [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i;
+input PORT_B2_WEN_i;
+input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i;
+input PORT_B2_REN_i;
+output [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o;
+
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+32, 36: mode = 3'b011;
+default: mode = 3'b000;
+endcase
+endfunction
+
+function integer rwmode;
+input integer rwwidth;
+case (rwwidth)
+1: rwmode = 1;
+2: rwmode = 2;
+4: rwmode = 4;
+8,9: rwmode = 9;
+16, 18: rwmode = 18;
+default: rwmode = 18;
+endcase
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+wire [1:0] PORT_A1_WR_BE;
+wire [1:0] PORT_B1_WR_BE;
+
+wire [1:0] PORT_A2_WR_BE;
+wire [1:0] PORT_B2_WR_BE;
+
+wire [17:0] PORT_B1_WDATA;
+wire [17:0] PORT_B1_RDATA;
+wire [17:0] PORT_A1_WDATA;
+wire [17:0] PORT_A1_RDATA;
+
+wire [17:0] PORT_B2_WDATA;
+wire [17:0] PORT_B2_RDATA;
+wire [17:0] PORT_A2_WDATA;
+wire [17:0] PORT_A2_RDATA;
+
+wire [13:0] PORT_A1_ADDR_INT;
+wire [13:0] PORT_B1_ADDR_INT;
+
+wire [13:0] PORT_A2_ADDR_INT;
+wire [13:0] PORT_B2_ADDR_INT;
+
+wire [13:0] PORT_A1_ADDR;
+wire [13:0] PORT_B1_ADDR;
+
+wire [13:0] PORT_A2_ADDR;
+wire [13:0] PORT_B2_ADDR;
+
+wire PORT_A1_CLK;
+wire PORT_B1_CLK;
+
+wire PORT_A2_CLK;
+wire PORT_B2_CLK;
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(PORT_A1_DWIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(PORT_A1_DWIDTH);
+localparam [ 2:0] RMODE_A2_i    = mode(PORT_A2_DWIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(PORT_A2_DWIDTH);
+
+localparam [ 2:0] RMODE_B1_i    = mode(PORT_B1_DWIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(PORT_B1_DWIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(PORT_B2_DWIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(PORT_B2_DWIDTH);
+
+localparam PORT_A1_WRWIDTH = rwmode(PORT_A1_DWIDTH);
+localparam PORT_B1_WRWIDTH = rwmode(PORT_B1_DWIDTH);
+localparam PORT_A2_WRWIDTH = rwmode(PORT_A2_DWIDTH);
+localparam PORT_B2_WRWIDTH = rwmode(PORT_B2_DWIDTH);
+
+assign PORT_A1_CLK = PORT_A1_CLK_i;
+assign PORT_B1_CLK = PORT_B1_CLK_i;
+
+assign PORT_A2_CLK = PORT_A2_CLK_i;
+assign PORT_B2_CLK = PORT_B2_CLK_i;
+
+generate
+	if (PORT_A1_AWIDTH == 14) begin
+		assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i;
+	end else begin
+		assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0;
+		assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i;
+	end
+endgenerate
+
+case (PORT_A1_DWIDTH)
+	1: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_B1_AWIDTH == 14) begin
+		assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i;
+	end else begin
+		assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0;
+		assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i;
+	end
+endgenerate
+
+case (PORT_B1_DWIDTH)
+	1: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_A2_AWIDTH == 14) begin
+		assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i;
+	end else begin
+		assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0;
+		assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i;
+	end
+endgenerate
+
+case (PORT_A2_DWIDTH)
+	1: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_B2_AWIDTH == 14) begin
+		assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i;
+	end else begin
+		assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0;
+		assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i;
+	end
+endgenerate
+
+case (PORT_B2_DWIDTH)
+	1: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT;
+	end
+endcase
+
+case (PORT_A1_WR_BE_WIDTH)
+	2: begin
+		assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0;
+		assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_B1_WR_BE_WIDTH)
+	2: begin
+		assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0;
+		assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_A2_WR_BE_WIDTH)
+	2: begin
+		assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0;
+		assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_B2_WR_BE_WIDTH)
+	2: begin
+		assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0;
+		assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+assign REN_A1_i = PORT_A1_REN_i;
+assign WEN_A1_i = PORT_A1_WEN_i;
+assign BE_A1_i  = PORT_A1_WR_BE;
+
+assign REN_A2_i = PORT_A2_REN_i;
+assign WEN_A2_i = PORT_A2_WEN_i;
+assign BE_A2_i  = PORT_A2_WR_BE;
+
+assign REN_B1_i = PORT_B1_REN_i;
+assign WEN_B1_i = PORT_B1_WEN_i;
+assign BE_B1_i  = PORT_B1_WR_BE;
+
+assign REN_B2_i = PORT_B2_REN_i;
+assign WEN_B2_i = PORT_B2_WEN_i;
+assign BE_B2_i  = PORT_B2_WR_BE;
+
+generate
+	if (PORT_A1_DWIDTH == 18) begin
+		assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0];
+	end else if (PORT_A1_DWIDTH == 9) begin
+		assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0;
+		assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A1_i = PORT_A1_WDATA;
+
+generate
+	if (PORT_A2_DWIDTH == 18) begin
+		assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0];
+	end else if (PORT_A2_DWIDTH == 9) begin
+		assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0;
+		assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A2_i = PORT_A2_WDATA;
+
+generate
+	if (PORT_A1_DWIDTH == 9) begin
+		assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]};
+	end else begin
+		assign PORT_A1_RDATA = RDATA_A1_o;
+	end
+endgenerate
+
+assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0];
+
+generate
+	if (PORT_A2_DWIDTH == 9) begin
+		assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]};
+	end else begin
+		assign PORT_A2_RDATA = RDATA_A2_o;
+	end
+endgenerate
+
+assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0];
+
+generate
+	if (PORT_B1_DWIDTH == 18) begin
+		assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0];
+	end else if (PORT_B1_DWIDTH == 9) begin
+		assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0;
+		assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_B1_i = PORT_B1_WDATA;
+
+generate
+	if (PORT_B2_DWIDTH == 18) begin
+		assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0];
+	end else if (PORT_B2_DWIDTH == 9) begin
+		assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0;
+		assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_B2_i = PORT_B2_WDATA;
+
+generate
+	if (PORT_B1_DWIDTH == 9) begin
+		assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]};
+	end else begin
+		assign PORT_B1_RDATA = RDATA_B1_o;
+	end
+endgenerate
+
+assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0];
+
+generate
+	if (PORT_B2_DWIDTH == 9) begin
+		assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]};
+	end else begin
+		assign PORT_B2_RDATA = RDATA_B2_o;
+	end
+endgenerate
+
+assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0];
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+};
+
+(* is_inferred = 0 *)
+(* is_split = 0 *)
+(* is_fifo = 0 *)
+(* port_a_dwidth = PORT_A1_WRWIDTH *)
+(* port_b_dwidth = PORT_B1_WRWIDTH *)
+TDP36K _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+
+	.CLK_A1_i(PORT_A1_CLK),
+	.ADDR_A1_i({1'b0,PORT_A1_ADDR}),
+	.WEN_A1_i(WEN_A1_i),
+	.BE_A1_i(BE_A1_i),
+	.WDATA_A1_i(WDATA_A1_i),
+	.REN_A1_i(REN_A1_i),
+	.RDATA_A1_o(RDATA_A1_o),
+
+	.CLK_A2_i(PORT_A2_CLK),
+	.ADDR_A2_i(PORT_A2_ADDR),
+	.WEN_A2_i(WEN_A2_i),
+	.BE_A2_i(BE_A2_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.REN_A2_i(REN_A2_i),
+	.RDATA_A2_o(RDATA_A2_o),
+
+	.CLK_B1_i(PORT_B1_CLK),
+	.ADDR_B1_i({1'b0,PORT_B1_ADDR}),
+	.WEN_B1_i(WEN_B1_i),
+	.BE_B1_i(BE_B1_i),
+	.WDATA_B1_i(WDATA_B1_i),
+	.REN_B1_i(REN_B1_i),
+	.RDATA_B1_o(RDATA_B1_o),
+
+	.CLK_B2_i(PORT_B2_CLK),
+	.ADDR_B2_i(PORT_B2_ADDR),
+	.WEN_B2_i(WEN_B2_i),
+	.BE_B2_i(BE_B2_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.REN_B2_i(REN_B2_i),
+	.RDATA_B2_o(RDATA_B2_o),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
+
+
+module BRAM2x18_SFIFO (
+		DIN1,
+		PUSH1,
+		POP1,
+		CLK1,
+		Async_Flush1,
+		Overrun_Error1,
+		Full_Watermark1,
+		Almost_Full1,
+		Full1,
+		Underrun_Error1,
+		Empty_Watermark1,
+		Almost_Empty1,
+		Empty1,
+		DOUT1,
+
+		DIN2,
+		PUSH2,
+		POP2,
+		CLK2,
+		Async_Flush2,
+		Overrun_Error2,
+		Full_Watermark2,
+		Almost_Full2,
+		Full2,
+		Underrun_Error2,
+		Empty_Watermark2,
+		Almost_Empty2,
+		Empty2,
+		DOUT2
+);
+
+	parameter WR1_DATA_WIDTH = 18;
+	parameter RD1_DATA_WIDTH = 18;
+
+	parameter WR2_DATA_WIDTH = 18;
+	parameter RD2_DATA_WIDTH = 18;
+
+	parameter UPAE_DBITS1 = 12'd10;
+	parameter UPAF_DBITS1 = 12'd10;
+
+	parameter UPAE_DBITS2 = 11'd10;
+	parameter UPAF_DBITS2 = 11'd10;
+
+	input CLK1;
+	input PUSH1, POP1;
+	input [WR1_DATA_WIDTH-1:0] DIN1;
+	input Async_Flush1;
+	output [RD1_DATA_WIDTH-1:0] DOUT1;
+	output Almost_Full1, Almost_Empty1;
+	output Full1, Empty1;
+	output Full_Watermark1, Empty_Watermark1;
+	output Overrun_Error1, Underrun_Error1;
+
+	input CLK2;
+	input PUSH2, POP2;
+	input [WR2_DATA_WIDTH-1:0] DIN2;
+	input Async_Flush2;
+	output [RD2_DATA_WIDTH-1:0] DOUT2;
+	output Almost_Full2, Almost_Empty2;
+	output Full2, Empty2;
+	output Full_Watermark2, Empty_Watermark2;
+	output Overrun_Error2, Underrun_Error2;
+
+	// Fixed mode settings
+	localparam [ 0:0] SYNC_FIFO1_i  = 1'd1;
+	localparam [ 0:0] FMODE1_i      = 1'd1;
+	localparam [ 0:0] POWERDN1_i    = 1'd0;
+	localparam [ 0:0] SLEEP1_i      = 1'd0;
+	localparam [ 0:0] PROTECT1_i    = 1'd0;
+	localparam [11:0] UPAE1_i       = UPAE_DBITS1;
+	localparam [11:0] UPAF1_i       = UPAF_DBITS1;
+
+	localparam [ 0:0] SYNC_FIFO2_i  = 1'd1;
+	localparam [ 0:0] FMODE2_i      = 1'd1;
+	localparam [ 0:0] POWERDN2_i    = 1'd0;
+	localparam [ 0:0] SLEEP2_i      = 1'd0;
+	localparam [ 0:0] PROTECT2_i    = 1'd0;
+	localparam [10:0] UPAE2_i       = UPAE_DBITS2;
+	localparam [10:0] UPAF2_i       = UPAF_DBITS2;
+
+	// Width mode function
+	function [2:0] mode;
+	input integer width;
+	case (width)
+	1: mode = 3'b101;
+	2: mode = 3'b110;
+	4: mode = 3'b100;
+	8,9: mode = 3'b001;
+	16, 18: mode = 3'b010;
+	32, 36: mode = 3'b011;
+	default: mode = 3'b000;
+	endcase
+	endfunction
+
+	function integer rwmode;
+	input integer rwwidth;
+	case (rwwidth)
+	1: rwmode = 1;
+	2: rwmode = 2;
+	4: rwmode = 4;
+	8,9: rwmode = 9;
+	16, 18: rwmode = 18;
+	default: rwmode = 18;
+	endcase
+	endfunction
+
+	wire [17:0] in_reg1;
+	wire [17:0] out_reg1;
+	wire [17:0] fifo1_flags;
+
+	wire [17:0] in_reg2;
+	wire [17:0] out_reg2;
+	wire [17:0] fifo2_flags;
+
+	wire Push_Clk1, Pop_Clk1;
+	wire Push_Clk2, Pop_Clk2;
+	assign Push_Clk1 = CLK1;
+	assign Pop_Clk1 = CLK1;
+	assign Push_Clk2 = CLK2;
+	assign Pop_Clk2 = CLK2;
+
+	assign Overrun_Error1 = fifo1_flags[0];
+	assign Full_Watermark1 = fifo1_flags[1];
+	assign Almost_Full1 = fifo1_flags[2];
+	assign Full1 = fifo1_flags[3];
+	assign Underrun_Error1 = fifo1_flags[4];
+	assign Empty_Watermark1 = fifo1_flags[5];
+	assign Almost_Empty1 = fifo1_flags[6];
+	assign Empty1 = fifo1_flags[7];
+
+	assign Overrun_Error2 = fifo2_flags[0];
+	assign Full_Watermark2 = fifo2_flags[1];
+	assign Almost_Full2 = fifo2_flags[2];
+	assign Full2 = fifo2_flags[3];
+	assign Underrun_Error2 = fifo2_flags[4];
+	assign Empty_Watermark2 = fifo2_flags[5];
+	assign Almost_Empty2 = fifo2_flags[6];
+	assign Empty2 = fifo2_flags[7];
+
+	localparam [ 2:0] RMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_A2_i    = mode(WR2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A2_i    = mode(WR2_DATA_WIDTH);
+
+	localparam [ 2:0] RMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_B2_i    = mode(RD2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B2_i    = mode(RD2_DATA_WIDTH);
+
+	localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH);
+	localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH);
+	localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH);
+	localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH);
+
+	generate
+		if (WR1_DATA_WIDTH == 18) begin
+			assign in_reg1[17:0] = DIN1[17:0];
+		end else if (WR1_DATA_WIDTH == 9) begin
+			assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]};
+		end else begin
+			assign in_reg1[17:WR1_DATA_WIDTH]  = 0;
+			assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD1_DATA_WIDTH == 9) begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]};
+		end else begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (WR2_DATA_WIDTH == 18) begin
+			assign in_reg2[17:0] = DIN2[17:0];
+		end else if (WR2_DATA_WIDTH == 9) begin
+			assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]};
+		end else begin
+			assign in_reg2[17:WR2_DATA_WIDTH]  = 0;
+			assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD2_DATA_WIDTH == 9) begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]};
+		end else begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+	};
+
+	(* is_fifo = 1 *)
+	(* sync_fifo = 1 *)
+	(* is_split = 0 *)
+	(* is_inferred = 0 *)
+	(* port_a_dwidth = PORT_A1_WRWIDTH *)
+	(* port_b_dwidth = PORT_B1_WRWIDTH *)
+ 	TDP36K _TECHMAP_REPLACE_ (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg1[17:0]),
+		.WDATA_A2_i(in_reg2[17:0]),
+		.RDATA_A1_o(fifo1_flags),
+		.RDATA_A2_o(fifo2_flags),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk1),
+		.CLK_A2_i(Push_Clk2),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b1),
+		.WEN_A1_i(PUSH1),
+		.WEN_A2_i(PUSH2),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg1[17:0]),
+		.RDATA_B2_o(out_reg2[17:0]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk1),
+		.CLK_B2_i(Pop_Clk2),
+		.REN_B1_i(POP1),
+		.REN_B2_i(POP2),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush1),
+		.FLUSH2_i(Async_Flush2)
+	);
+
+endmodule
+
+
+module BRAM2x18_AFIFO (
+		DIN1,
+		PUSH1,
+		POP1,
+		Push_Clk1,
+	Pop_Clk1,
+		Async_Flush1,
+		Overrun_Error1,
+		Full_Watermark1,
+		Almost_Full1,
+		Full1,
+		Underrun_Error1,
+		Empty_Watermark1,
+		Almost_Empty1,
+		Empty1,
+		DOUT1,
+
+		DIN2,
+		PUSH2,
+		POP2,
+		Push_Clk2,
+	Pop_Clk2,
+		Async_Flush2,
+		Overrun_Error2,
+		Full_Watermark2,
+		Almost_Full2,
+		Full2,
+		Underrun_Error2,
+		Empty_Watermark2,
+		Almost_Empty2,
+		Empty2,
+		DOUT2
+);
+
+	parameter WR1_DATA_WIDTH = 18;
+	parameter RD1_DATA_WIDTH = 18;
+
+	parameter WR2_DATA_WIDTH = 18;
+	parameter RD2_DATA_WIDTH = 18;
+
+	parameter UPAE_DBITS1 = 12'd10;
+	parameter UPAF_DBITS1 = 12'd10;
+
+	parameter UPAE_DBITS2 = 11'd10;
+	parameter UPAF_DBITS2 = 11'd10;
+
+	input Push_Clk1, Pop_Clk1;
+	input PUSH1, POP1;
+	input [WR1_DATA_WIDTH-1:0] DIN1;
+	input Async_Flush1;
+	output [RD1_DATA_WIDTH-1:0] DOUT1;
+	output Almost_Full1, Almost_Empty1;
+	output Full1, Empty1;
+	output Full_Watermark1, Empty_Watermark1;
+	output Overrun_Error1, Underrun_Error1;
+
+	input Push_Clk2, Pop_Clk2;
+	input PUSH2, POP2;
+	input [WR2_DATA_WIDTH-1:0] DIN2;
+	input Async_Flush2;
+	output [RD2_DATA_WIDTH-1:0] DOUT2;
+	output Almost_Full2, Almost_Empty2;
+	output Full2, Empty2;
+	output Full_Watermark2, Empty_Watermark2;
+	output Overrun_Error2, Underrun_Error2;
+
+	// Fixed mode settings
+	localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+	localparam [ 0:0] FMODE1_i      = 1'd1;
+	localparam [ 0:0] POWERDN1_i    = 1'd0;
+	localparam [ 0:0] SLEEP1_i      = 1'd0;
+	localparam [ 0:0] PROTECT1_i    = 1'd0;
+	localparam [11:0] UPAE1_i       = UPAE_DBITS1;
+	localparam [11:0] UPAF1_i       = UPAF_DBITS1;
+
+	localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+	localparam [ 0:0] FMODE2_i      = 1'd1;
+	localparam [ 0:0] POWERDN2_i    = 1'd0;
+	localparam [ 0:0] SLEEP2_i      = 1'd0;
+	localparam [ 0:0] PROTECT2_i    = 1'd0;
+	localparam [10:0] UPAE2_i       = UPAE_DBITS2;
+	localparam [10:0] UPAF2_i       = UPAF_DBITS2;
+
+	// Width mode function
+	function [2:0] mode;
+	input integer width;
+	case (width)
+	1: mode = 3'b101;
+	2: mode = 3'b110;
+	4: mode = 3'b100;
+	8,9: mode = 3'b001;
+	16, 18: mode = 3'b010;
+	32, 36: mode = 3'b011;
+	default: mode = 3'b000;
+	endcase
+	endfunction
+
+	function integer rwmode;
+	input integer rwwidth;
+	case (rwwidth)
+	1: rwmode = 1;
+	2: rwmode = 2;
+	4: rwmode = 4;
+	8,9: rwmode = 9;
+	16, 18: rwmode = 18;
+	default: rwmode = 18;
+	endcase
+	endfunction
+
+	wire [17:0] in_reg1;
+	wire [17:0] out_reg1;
+	wire [17:0] fifo1_flags;
+
+	wire [17:0] in_reg2;
+	wire [17:0] out_reg2;
+	wire [17:0] fifo2_flags;
+
+	wire Push_Clk1, Pop_Clk1;
+	wire Push_Clk2, Pop_Clk2;
+
+	assign Overrun_Error1 = fifo1_flags[0];
+	assign Full_Watermark1 = fifo1_flags[1];
+	assign Almost_Full1 = fifo1_flags[2];
+	assign Full1 = fifo1_flags[3];
+	assign Underrun_Error1 = fifo1_flags[4];
+	assign Empty_Watermark1 = fifo1_flags[5];
+	assign Almost_Empty1 = fifo1_flags[6];
+	assign Empty1 = fifo1_flags[7];
+
+	assign Overrun_Error2 = fifo2_flags[0];
+	assign Full_Watermark2 = fifo2_flags[1];
+	assign Almost_Full2 = fifo2_flags[2];
+	assign Full2 = fifo2_flags[3];
+	assign Underrun_Error2 = fifo2_flags[4];
+	assign Empty_Watermark2 = fifo2_flags[5];
+	assign Almost_Empty2 = fifo2_flags[6];
+	assign Empty2 = fifo2_flags[7];
+
+	localparam [ 2:0] RMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_A2_i    = mode(WR2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A2_i    = mode(WR2_DATA_WIDTH);
+
+	localparam [ 2:0] RMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_B2_i    = mode(RD2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B2_i    = mode(RD2_DATA_WIDTH);
+
+	localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH);
+	localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH);
+	localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH);
+	localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH);
+
+	generate
+		if (WR1_DATA_WIDTH == 18) begin
+			assign in_reg1[17:0] = DIN1[17:0];
+		end else if (WR1_DATA_WIDTH == 9) begin
+			assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]};
+		end else begin
+			assign in_reg1[17:WR1_DATA_WIDTH]  = 0;
+			assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD1_DATA_WIDTH == 9) begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]};
+		end else begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (WR2_DATA_WIDTH == 18) begin
+			assign in_reg2[17:0] = DIN2[17:0];
+		end else if (WR2_DATA_WIDTH == 9) begin
+			assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]};
+		end else begin
+			assign in_reg2[17:WR2_DATA_WIDTH]  = 0;
+			assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD2_DATA_WIDTH == 9) begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]};
+		end else begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+	};
+
+	(* is_fifo = 1 *)
+	(* sync_fifo = 0 *)
+	(* is_split = 0 *)
+	(* is_inferred = 0 *)
+	(* port_a_dwidth = PORT_A1_WRWIDTH *)
+	(* port_b_dwidth = PORT_B1_WRWIDTH *)
+ 	TDP36K _TECHMAP_REPLACE_ (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg1[17:0]),
+		.WDATA_A2_i(in_reg2[17:0]),
+		.RDATA_A1_o(fifo1_flags),
+		.RDATA_A2_o(fifo2_flags),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk1),
+		.CLK_A2_i(Push_Clk2),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b1),
+		.WEN_A1_i(PUSH1),
+		.WEN_A2_i(PUSH2),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg1[17:0]),
+		.RDATA_B2_o(out_reg2[17:0]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk1),
+		.CLK_B2_i(Pop_Clk2),
+		.REN_B1_i(POP1),
+		.REN_B2_i(POP2),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush1),
+		.FLUSH2_i(Async_Flush2)
+	);
+
+endmodule
\ No newline at end of file
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/brams_sim.v b/yosys/techlibs/quicklogic/qlf_k6n10f/brams_sim.v
new file mode 100644
index 00000000000..de6d992335a
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/brams_sim.v
@@ -0,0 +1,10949 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns /10ps
+
+`default_nettype none
+
+module TDP36K (
+		RESET_ni,
+		WEN_A1_i,
+		WEN_B1_i,
+		REN_A1_i,
+		REN_B1_i,
+		CLK_A1_i,
+		CLK_B1_i,
+		BE_A1_i,
+		BE_B1_i,
+		ADDR_A1_i,
+		ADDR_B1_i,
+		WDATA_A1_i,
+		WDATA_B1_i,
+		RDATA_A1_o,
+		RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,
+		WEN_B2_i,
+		REN_A2_i,
+		REN_B2_i,
+		CLK_A2_i,
+		CLK_B2_i,
+		BE_A2_i,
+		BE_B2_i,
+		ADDR_A2_i,
+		ADDR_B2_i,
+		WDATA_A2_i,
+		WDATA_B2_i,
+		RDATA_A2_o,
+		RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		// First 18K RAMFIFO (41 bits)
+		localparam [ 0:0] SYNC_FIFO1_i  = MODE_BITS[0];
+		localparam [ 2:0] RMODE_A1_i    = MODE_BITS[3 : 1];
+		localparam [ 2:0] RMODE_B1_i    = MODE_BITS[6 : 4];
+		localparam [ 2:0] WMODE_A1_i    = MODE_BITS[9 : 7];
+		localparam [ 2:0] WMODE_B1_i    = MODE_BITS[12:10];
+		localparam [ 0:0] FMODE1_i      = MODE_BITS[13];
+		localparam [ 0:0] POWERDN1_i    = MODE_BITS[14];
+		localparam [ 0:0] SLEEP1_i      = MODE_BITS[15];
+		localparam [ 0:0] PROTECT1_i    = MODE_BITS[16];
+		localparam [11:0] UPAE1_i       = MODE_BITS[28:17];
+		localparam [11:0] UPAF1_i       = MODE_BITS[40:29];
+
+		// Second 18K RAMFIFO (39 bits)
+		localparam [ 0:0] SYNC_FIFO2_i  = MODE_BITS[41];
+		localparam [ 2:0] RMODE_A2_i    = MODE_BITS[44:42];
+		localparam [ 2:0] RMODE_B2_i    = MODE_BITS[47:45];
+		localparam [ 2:0] WMODE_A2_i    = MODE_BITS[50:48];
+		localparam [ 2:0] WMODE_B2_i    = MODE_BITS[53:51];
+		localparam [ 0:0] FMODE2_i      = MODE_BITS[54];
+		localparam [ 0:0] POWERDN2_i    = MODE_BITS[55];
+		localparam [ 0:0] SLEEP2_i      = MODE_BITS[56];
+		localparam [ 0:0] PROTECT2_i    = MODE_BITS[57];
+		localparam [10:0] UPAE2_i       = MODE_BITS[68:58];
+		localparam [10:0] UPAF2_i       = MODE_BITS[79:69];
+
+		// Split (1 bit)
+		localparam [ 0:0] SPLIT_i       = MODE_BITS[80];
+
+		parameter [1024*36-1:0] RAM_INIT = 36864'bx;
+
+		input wire RESET_ni;
+		input wire WEN_A1_i;
+		input wire WEN_B1_i;
+		input wire REN_A1_i;
+		input wire REN_B1_i;
+		(* clkbuf_sink *)
+		input wire CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire CLK_B1_i;
+		input wire [1:0] BE_A1_i;
+		input wire [1:0] BE_B1_i;
+		input wire [14:0] ADDR_A1_i;
+		input wire [14:0] ADDR_B1_i;
+		input wire [17:0] WDATA_A1_i;
+		input wire [17:0] WDATA_B1_i;
+		output reg [17:0] RDATA_A1_o;
+		output reg [17:0] RDATA_B1_o;
+		input wire FLUSH1_i;
+		input wire WEN_A2_i;
+		input wire WEN_B2_i;
+		input wire REN_A2_i;
+		input wire REN_B2_i;
+		(* clkbuf_sink *)
+		input wire CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire CLK_B2_i;
+		input wire [1:0] BE_A2_i;
+		input wire [1:0] BE_B2_i;
+		input wire [13:0] ADDR_A2_i;
+		input wire [13:0] ADDR_B2_i;
+		input wire [17:0] WDATA_A2_i;
+		input wire [17:0] WDATA_B2_i;
+		output reg [17:0] RDATA_A2_o;
+		output reg [17:0] RDATA_B2_o;
+		input wire FLUSH2_i;
+
+		function [18431:0] split_init;
+			input index;
+			integer i;
+			for (i = 0; i < 1024; i = i + 1) begin
+				split_init[i * 18 +: 18] = RAM_INIT[i * 36 + index * 18 +: 18];
+			end
+		endfunction
+
+		wire EMPTY2;
+		wire EPO2;
+		wire EWM2;
+		wire FULL2;
+		wire FMO2;
+		wire FWM2;
+		wire EMPTY1;
+		wire EPO1;
+		wire EWM1;
+		wire FULL1;
+		wire FMO1;
+		wire FWM1;
+		wire UNDERRUN1;
+		wire OVERRUN1;
+		wire UNDERRUN2;
+		wire OVERRUN2;
+		wire UNDERRUN3;
+		wire OVERRUN3;
+		wire EMPTY3;
+		wire EPO3;
+		wire EWM3;
+		wire FULL3;
+		wire FMO3;
+		wire FWM3;
+		wire ram_fmode1;
+		wire ram_fmode2;
+		wire [17:0] ram_rdata_a1;
+		wire [17:0] ram_rdata_b1;
+		wire [17:0] ram_rdata_a2;
+		wire [17:0] ram_rdata_b2;
+		reg [17:0] ram_wdata_a1;
+		reg [17:0] ram_wdata_b1;
+		reg [17:0] ram_wdata_a2;
+		reg [17:0] ram_wdata_b2;
+		reg [14:0] laddr_a1;
+		reg [14:0] laddr_b1;
+		wire [13:0] ram_addr_a1;
+		wire [13:0] ram_addr_b1;
+		wire [13:0] ram_addr_a2;
+		wire [13:0] ram_addr_b2;
+		wire smux_clk_a1;
+		wire smux_clk_b1;
+		wire smux_clk_a2;
+		wire smux_clk_b2;
+		reg [1:0] ram_be_a1;
+		reg [1:0] ram_be_a2;
+		reg [1:0] ram_be_b1;
+		reg [1:0] ram_be_b2;
+		wire [2:0] ram_rmode_a1;
+		wire [2:0] ram_wmode_a1;
+		wire [2:0] ram_rmode_b1;
+		wire [2:0] ram_wmode_b1;
+		wire [2:0] ram_rmode_a2;
+		wire [2:0] ram_wmode_a2;
+		wire [2:0] ram_rmode_b2;
+		wire [2:0] ram_wmode_b2;
+		wire ram_ren_a1;
+		wire ram_ren_b1;
+		wire ram_ren_a2;
+		wire ram_ren_b2;
+		wire ram_wen_a1;
+		wire ram_wen_b1;
+		wire ram_wen_a2;
+		wire ram_wen_b2;
+		wire ren_o;
+		wire [11:0] ff_raddr;
+		wire [11:0] ff_waddr;
+		reg [35:0] fifo_rdata;
+		wire [1:0] fifo_rmode;
+		wire [1:0] fifo_wmode;
+		wire [1:0] bwl;
+		wire [17:0] pl_dout0;
+		wire [17:0] pl_dout1;
+		wire sclk_a1;
+		wire sclk_b1;
+		wire sclk_a2;
+		wire sclk_b2;
+		wire sreset;
+		wire flush1;
+		wire flush2;
+		assign sreset = RESET_ni;
+		assign flush1 = ~FLUSH1_i;
+		assign flush2 = ~FLUSH2_i;
+		assign ram_fmode1 = FMODE1_i & SPLIT_i;
+		assign ram_fmode2 = FMODE2_i & SPLIT_i;
+		assign smux_clk_a1 = CLK_A1_i;
+		assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i);
+		assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i);
+		assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i));
+		assign sclk_a1 = smux_clk_a1;
+		assign sclk_a2 = smux_clk_a2;
+		assign sclk_b1 = smux_clk_b1;
+		assign sclk_b2 = smux_clk_b2;
+		assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i));
+		assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i));
+		assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i));
+		assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i));
+		localparam MODE_36 = 3'b011;
+		assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4])));
+		assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4])));
+		assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4]));
+		assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4]));
+		assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]}));
+		assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]}));
+		assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]}));
+		assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]}));
+		assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3]));
+		localparam MODE_18 = 3'b010;
+		localparam MODE_9 = 3'b001;
+		always @(*) begin : WDATA_SEL
+				case (SPLIT_i)
+						1: begin
+								ram_wdata_a1 = WDATA_A1_i;
+								ram_wdata_a2 = WDATA_A2_i;
+								ram_wdata_b1 = WDATA_B1_i;
+								ram_wdata_b2 = WDATA_B2_i;
+								ram_be_a2 = BE_A2_i;
+								ram_be_b2 = BE_B2_i;
+								ram_be_a1 = BE_A1_i;
+								ram_be_b1 = BE_B1_i;
+						end
+						0: begin
+								case (WMODE_A1_i)
+										MODE_36: begin
+												ram_wdata_a1 = WDATA_A1_i;
+												ram_wdata_a2 = WDATA_A2_i;
+												ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i);
+												ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i);
+										end
+										MODE_18: begin
+												ram_wdata_a1 = WDATA_A1_i;
+												ram_wdata_a2 = WDATA_A1_i;
+												ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i);
+												ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i);
+										end
+										MODE_9: begin
+												ram_wdata_a1[7:0] = WDATA_A1_i[7:0];
+												ram_wdata_a1[16] = WDATA_A1_i[16];
+												ram_wdata_a1[15:8] = WDATA_A1_i[7:0];
+												ram_wdata_a1[17] = WDATA_A1_i[16];
+												ram_wdata_a2[7:0] = WDATA_A1_i[7:0];
+												ram_wdata_a2[16] = WDATA_A1_i[16];
+												ram_wdata_a2[15:8] = WDATA_A1_i[7:0];
+												ram_wdata_a2[17] = WDATA_A1_i[16];
+												case (bwl)
+														0: {ram_be_a2, ram_be_a1} = 4'b0001;
+														1: {ram_be_a2, ram_be_a1} = 4'b0010;
+														2: {ram_be_a2, ram_be_a1} = 4'b0100;
+														3: {ram_be_a2, ram_be_a1} = 4'b1000;
+												endcase
+										end
+										default: begin
+												ram_wdata_a1 = WDATA_A1_i;
+												ram_wdata_a2 = WDATA_A1_i;
+												ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i);
+												ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i);
+										end
+								endcase
+								case (WMODE_B1_i)
+										MODE_36: begin
+												ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
+												ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i);
+												ram_be_b2 = BE_B2_i;
+												ram_be_b1 = BE_B1_i;
+										end
+										MODE_18: begin
+												ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
+												ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
+												ram_be_b1 = BE_B1_i;
+												ram_be_b2 = BE_B1_i;
+										end
+										MODE_9: begin
+												ram_wdata_b1[7:0] = WDATA_B1_i[7:0];
+												ram_wdata_b1[16] = WDATA_B1_i[16];
+												ram_wdata_b1[15:8] = WDATA_B1_i[7:0];
+												ram_wdata_b1[17] = WDATA_B1_i[16];
+												ram_wdata_b2[7:0] = WDATA_B1_i[7:0];
+												ram_wdata_b2[16] = WDATA_B1_i[16];
+												ram_wdata_b2[15:8] = WDATA_B1_i[7:0];
+												ram_wdata_b2[17] = WDATA_B1_i[16];
+												case (ADDR_B1_i[4:3])
+														0: {ram_be_b2, ram_be_b1} = 4'b0001;
+														1: {ram_be_b2, ram_be_b1} = 4'b0010;
+														2: {ram_be_b2, ram_be_b1} = 4'b0100;
+														3: {ram_be_b2, ram_be_b1} = 4'b1000;
+												endcase
+										end
+										default: begin
+												ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
+												ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i);
+												ram_be_b2 = BE_B1_i;
+												ram_be_b1 = BE_B1_i;
+										end
+								endcase
+						end
+				endcase
+		end
+		assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i));
+		assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i));
+		assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i)));
+		assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i)));
+		assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i)));
+		assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i)));
+		assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i));
+		assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i));
+		always @(*) begin : FIFO_READ_SEL
+				case (RMODE_B1_i)
+						MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]};
+						MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1});
+						MODE_9:
+								case (ff_raddr[1:0])
+										0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]};
+										1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]};
+										2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]};
+										3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]};
+								endcase
+						default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1};
+				endcase
+		end
+		localparam MODE_1 = 3'b101;
+		localparam MODE_2 = 3'b110;
+		localparam MODE_4 = 3'b100;
+		always @(*) begin : RDATA_SEL
+				case (SPLIT_i)
+						1: begin
+								RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1);
+								RDATA_B1_o = ram_rdata_b1;
+								RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2);
+								RDATA_B2_o = ram_rdata_b2;
+						end
+						0: begin
+								if (FMODE1_i) begin
+										RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3};
+										RDATA_A2_o = 18'b000000000000000000;
+								end
+								else
+										case (RMODE_A1_i)
+												MODE_36: begin
+														RDATA_A1_o = {ram_rdata_a1[17:0]};
+														RDATA_A2_o = {ram_rdata_a2[17:0]};
+												end
+												MODE_18: begin
+														RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1);
+														RDATA_A2_o = 18'b000000000000000000;
+												end
+												MODE_9: begin
+														RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}});
+														RDATA_A2_o = 18'b000000000000000000;
+												end
+												MODE_4: begin
+														RDATA_A2_o = 18'b000000000000000000;
+														RDATA_A1_o[17:4] = 14'b00000000000000;
+														RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]);
+												end
+												MODE_2: begin
+														RDATA_A2_o = 18'b000000000000000000;
+														RDATA_A1_o[17:2] = 16'b0000000000000000;
+														RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]);
+												end
+												MODE_1: begin
+														RDATA_A2_o = 18'b000000000000000000;
+														RDATA_A1_o[17:1] = 17'b00000000000000000;
+														RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]);
+												end
+												default: begin
+														RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]};
+														RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]};
+												end
+										endcase
+								case (RMODE_B1_i)
+										MODE_36: begin
+												RDATA_B1_o = {ram_rdata_b1};
+												RDATA_B2_o = {ram_rdata_b2};
+										end
+										MODE_18: begin
+												RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1));
+												RDATA_B2_o = 18'b000000000000000000;
+										end
+										MODE_9: begin
+												RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}));
+												RDATA_B2_o = 18'b000000000000000000;
+										end
+										MODE_4: begin
+												RDATA_B2_o = 18'b000000000000000000;
+												RDATA_B1_o[17:4] = 14'b00000000000000;
+												RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]);
+										end
+										MODE_2: begin
+												RDATA_B2_o = 18'b000000000000000000;
+												RDATA_B1_o[17:2] = 16'b0000000000000000;
+												RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]);
+										end
+										MODE_1: begin
+												RDATA_B2_o = 18'b000000000000000000;
+												RDATA_B1_o[17:1] = 17'b00000000000000000;
+												RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]);
+										end
+										default: begin
+												RDATA_B1_o = ram_rdata_b1;
+												RDATA_B2_o = ram_rdata_b2;
+										end
+								endcase
+						end
+				endcase
+		end
+		always @(posedge sclk_a1 or negedge sreset)
+				if (sreset == 0)
+						laddr_a1 <= 1'sb0;
+				else
+						laddr_a1 <= ADDR_A1_i;
+		always @(posedge sclk_b1 or negedge sreset)
+				if (sreset == 0)
+						laddr_b1 <= 1'sb0;
+				else
+						laddr_b1 <= ADDR_B1_i;
+		assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00)));
+		assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00)));
+		fifo_ctl #(
+				.ADDR_WIDTH(12),
+				.FIFO_WIDTH(3'd4),
+				.DEPTH(7)
+		) fifo36_ctl(
+				.rclk(sclk_b1),
+				.rst_R_n(flush1),
+				.wclk(sclk_a1),
+				.rst_W_n(flush1),
+				.ren(REN_B1_i),
+				.wen(ram_wen_a1),
+				.sync(SYNC_FIFO1_i),
+				.rmode(fifo_rmode),
+				.wmode(fifo_wmode),
+				.ren_o(ren_o),
+				.fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}),
+				.raddr(ff_raddr),
+				.waddr(ff_waddr),
+				.upaf(UPAF1_i),
+				.upae(UPAE1_i)
+		);
+		TDP18K_FIFO #(
+				.UPAF_i(UPAF1_i[10:0]),
+				.UPAE_i(UPAE1_i[10:0]),
+				.SYNC_FIFO_i(SYNC_FIFO1_i),
+				.POWERDN_i(POWERDN1_i),
+				.SLEEP_i(SLEEP1_i),
+				.PROTECT_i(PROTECT1_i),
+				.INIT_i(split_init(0))
+		)u1(
+				.RMODE_A_i(ram_rmode_a1),
+				.RMODE_B_i(ram_rmode_b1),
+				.WMODE_A_i(ram_wmode_a1),
+				.WMODE_B_i(ram_wmode_b1),
+				.WEN_A_i(ram_wen_a1),
+				.WEN_B_i(ram_wen_b1),
+				.REN_A_i(ram_ren_a1),
+				.REN_B_i(ram_ren_b1),
+				.CLK_A_i(sclk_a1),
+				.CLK_B_i(sclk_b1),
+				.BE_A_i(ram_be_a1),
+				.BE_B_i(ram_be_b1),
+				.ADDR_A_i(ram_addr_a1),
+				.ADDR_B_i(ram_addr_b1),
+				.WDATA_A_i(ram_wdata_a1),
+				.WDATA_B_i(ram_wdata_b1),
+				.RDATA_A_o(ram_rdata_a1),
+				.RDATA_B_o(ram_rdata_b1),
+				.EMPTY_o(EMPTY1),
+				.EPO_o(EPO1),
+				.EWM_o(EWM1),
+				.UNDERRUN_o(UNDERRUN1),
+				.FULL_o(FULL1),
+				.FMO_o(FMO1),
+				.FWM_o(FWM1),
+				.OVERRUN_o(OVERRUN1),
+				.FLUSH_ni(flush1),
+				.FMODE_i(ram_fmode1)
+		);
+		TDP18K_FIFO #(
+				.UPAF_i(UPAF2_i),
+				.UPAE_i(UPAE2_i),
+				.SYNC_FIFO_i(SYNC_FIFO2_i),
+				.POWERDN_i(POWERDN2_i),
+				.SLEEP_i(SLEEP2_i),
+				.PROTECT_i(PROTECT2_i),
+				.INIT_i(split_init(1))
+		)u2(
+				.RMODE_A_i(ram_rmode_a2),
+				.RMODE_B_i(ram_rmode_b2),
+				.WMODE_A_i(ram_wmode_a2),
+				.WMODE_B_i(ram_wmode_b2),
+				.WEN_A_i(ram_wen_a2),
+				.WEN_B_i(ram_wen_b2),
+				.REN_A_i(ram_ren_a2),
+				.REN_B_i(ram_ren_b2),
+				.CLK_A_i(sclk_a2),
+				.CLK_B_i(sclk_b2),
+				.BE_A_i(ram_be_a2),
+				.BE_B_i(ram_be_b2),
+				.ADDR_A_i(ram_addr_a2),
+				.ADDR_B_i(ram_addr_b2),
+				.WDATA_A_i(ram_wdata_a2),
+				.WDATA_B_i(ram_wdata_b2),
+				.RDATA_A_o(ram_rdata_a2),
+				.RDATA_B_o(ram_rdata_b2),
+				.EMPTY_o(EMPTY2),
+				.EPO_o(EPO2),
+				.EWM_o(EWM2),
+				.UNDERRUN_o(UNDERRUN2),
+				.FULL_o(FULL2),
+				.FMO_o(FMO2),
+				.FWM_o(FWM2),
+				.OVERRUN_o(OVERRUN2),
+				.FLUSH_ni(flush2),
+				.FMODE_i(ram_fmode2)
+		);
+endmodule
+
+module RAM_18K_X2_BLK (
+		RESET_ni,
+
+		WEN1_i,
+		REN1_i,
+		WR1_CLK_i,
+		RD1_CLK_i,
+		WR1_BE_i,
+		WR1_ADDR_i,
+		RD1_ADDR_i,
+		WDATA1_i,
+		RDATA1_o,
+
+		WEN2_i,
+		REN2_i,
+		WR2_CLK_i,
+		RD2_CLK_i,
+		WR2_BE_i,
+		WR2_ADDR_i,
+		RD2_ADDR_i,
+		WDATA2_i,
+		RDATA2_o
+);
+
+parameter WR1_ADDR_WIDTH = 10;
+parameter RD1_ADDR_WIDTH = 10;
+parameter WR1_DATA_WIDTH = 18;
+parameter RD1_DATA_WIDTH = 18;
+parameter BE1_WIDTH = 2;
+
+parameter WR2_ADDR_WIDTH = 10;
+parameter RD2_ADDR_WIDTH = 10;
+parameter WR2_DATA_WIDTH = 18;
+parameter RD2_DATA_WIDTH = 18;
+parameter BE2_WIDTH = 2;
+
+input wire RESET_ni;
+
+input wire WEN1_i;
+input wire REN1_i;
+input wire WR1_CLK_i;
+input wire RD1_CLK_i;
+input wire [BE1_WIDTH-1:0] WR1_BE_i;
+input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i;
+input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i;
+input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i;
+output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o;
+
+input wire WEN2_i;
+input wire REN2_i;
+input wire WR2_CLK_i;
+input wire RD2_CLK_i;
+input wire [BE2_WIDTH-1:0] WR2_BE_i;
+input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i;
+input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i;
+input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i;
+output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o;
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+32, 36: mode = 3'b011;
+default: mode = 3'b000;
+endcase
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+wire [1:0] WR1_BE;
+wire [1:0] WR2_BE;
+
+wire [17:0] PORT_B1_RDATA;
+wire [17:0] PORT_A1_WDATA;
+
+wire [17:0] PORT_B2_RDATA;
+wire [17:0] PORT_A2_WDATA;
+
+wire [13:0] WR1_ADDR_INT;
+wire [13:0] RD1_ADDR_INT;
+
+wire [13:0] WR2_ADDR_INT;
+wire [13:0] RD2_ADDR_INT;
+
+wire [13:0] PORT_A1_ADDR;
+wire [13:0] PORT_B1_ADDR;
+
+wire [13:0] PORT_A2_ADDR;
+wire [13:0] PORT_B2_ADDR;
+
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(WR1_DATA_WIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(WR1_DATA_WIDTH);
+localparam [ 2:0] RMODE_A2_i    = mode(WR2_DATA_WIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(WR2_DATA_WIDTH);
+
+localparam [ 2:0] RMODE_B1_i    = mode(RD1_DATA_WIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(RD1_DATA_WIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(RD2_DATA_WIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(RD2_DATA_WIDTH);
+
+generate
+	if (WR1_ADDR_WIDTH == 14) begin
+		assign WR1_ADDR_INT = WR1_ADDR_i;
+	end else begin
+		assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0;
+		assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i;
+	end
+endgenerate
+
+case (WR1_DATA_WIDTH)
+	1: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (RD1_ADDR_WIDTH == 14) begin
+		assign RD1_ADDR_INT = RD1_ADDR_i;
+	end else begin
+		assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0;
+		assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i;
+	end
+endgenerate
+
+case (RD1_DATA_WIDTH)
+	1: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (WR2_ADDR_WIDTH == 14) begin
+		assign WR2_ADDR_INT = WR2_ADDR_i;
+	end else begin
+		assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0;
+		assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i;
+	end
+endgenerate
+
+case (WR2_DATA_WIDTH)
+	1: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT;
+	end
+endcase
+
+generate
+	if (RD2_ADDR_WIDTH == 14) begin
+		assign RD2_ADDR_INT = RD2_ADDR_i;
+	end else begin
+		assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0;
+		assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i;
+	end
+endgenerate
+
+case (RD2_DATA_WIDTH)
+	1: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT;
+	end
+endcase
+
+case (BE1_WIDTH)
+	2: begin
+		assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR1_BE[1:BE1_WIDTH] = 0;
+		assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0];
+	end
+endcase
+
+case (BE2_WIDTH)
+	2: begin
+		assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR2_BE[1:BE2_WIDTH] = 0;
+		assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0];
+	end
+endcase
+
+assign REN_A1_i = 1'b0;
+assign WEN_A1_i = WEN1_i;
+assign BE_A1_i = WR1_BE;
+assign REN_A2_i = 1'b0;
+assign WEN_A2_i = WEN2_i;
+assign BE_A2_i = WR2_BE;
+
+assign REN_B1_i = REN1_i;
+assign WEN_B1_i = 1'b0;
+assign BE_B1_i = 2'h0;
+assign REN_B2_i = REN2_i;
+assign WEN_B2_i = 1'b0;
+assign BE_B2_i = 2'h0;
+
+generate
+	if (WR1_DATA_WIDTH == 18) begin
+		assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0];
+	end else if (WR1_DATA_WIDTH == 9) begin
+		assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]};
+	end else begin
+		assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0;
+		assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A1_i = PORT_A1_WDATA[17:0];
+assign WDATA_B1_i = 18'h0;
+
+generate
+	if (RD1_DATA_WIDTH == 9) begin
+		assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]};
+	end else begin
+		assign PORT_B1_RDATA = RDATA_B1_o;
+	end
+endgenerate
+
+assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0];
+
+generate
+	if (WR2_DATA_WIDTH == 18) begin
+		assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0];
+	end else if (WR2_DATA_WIDTH == 9) begin
+		assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]};
+	end else begin
+		assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0;
+		assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A2_i = PORT_A2_WDATA[17:0];
+assign WDATA_B2_i = 18'h0;
+
+generate
+	if (RD2_DATA_WIDTH == 9) begin
+		assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]};
+	end else begin
+		assign PORT_B2_RDATA = RDATA_B2_o;
+	end
+endgenerate
+
+assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0];
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+};
+
+(* is_inferred = 0 *)
+(* is_split = 1 *)
+(* port_a1_dwidth = WR1_DATA_WIDTH *)
+(* port_a2_dwidth = WR2_DATA_WIDTH *)
+(* port_b1_dwidth = RD1_DATA_WIDTH *)
+(* port_b2_dwidth = RD2_DATA_WIDTH *)
+TDP36K _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+
+	.CLK_A1_i(WR1_CLK_i),
+	.ADDR_A1_i({1'b0,PORT_A1_ADDR}),
+	.WEN_A1_i(WEN_A1_i),
+	.BE_A1_i(BE_A1_i),
+	.WDATA_A1_i(WDATA_A1_i),
+	.REN_A1_i(REN_A1_i),
+	.RDATA_A1_o(RDATA_A1_o),
+
+	.CLK_A2_i(WR2_CLK_i),
+	.ADDR_A2_i(PORT_A2_ADDR),
+	.WEN_A2_i(WEN_A2_i),
+	.BE_A2_i(BE_A2_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.REN_A2_i(REN_A2_i),
+	.RDATA_A2_o(RDATA_A2_o),
+
+	.CLK_B1_i(RD1_CLK_i),
+	.ADDR_B1_i({1'b0,PORT_B1_ADDR}),
+	.WEN_B1_i(WEN_B1_i),
+	.BE_B1_i(BE_B1_i),
+	.WDATA_B1_i(WDATA_B1_i),
+	.REN_B1_i(REN_B1_i),
+	.RDATA_B1_o(RDATA_B1_o),
+
+	.CLK_B2_i(RD2_CLK_i),
+	.ADDR_B2_i(PORT_B2_ADDR),
+	.WEN_B2_i(WEN_B2_i),
+	.BE_B2_i(BE_B2_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.REN_B2_i(REN_B2_i),
+	.RDATA_B2_o(RDATA_B2_o),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
+
+module BRAM2x18_SP (
+		RESET_ni,
+
+		WEN1_i,
+		REN1_i,
+		WR1_CLK_i,
+		RD1_CLK_i,
+		WR1_BE_i,
+		WR1_ADDR_i,
+		RD1_ADDR_i,
+		WDATA1_i,
+		RDATA1_o,
+
+		WEN2_i,
+		REN2_i,
+		WR2_CLK_i,
+		RD2_CLK_i,
+		WR2_BE_i,
+		WR2_ADDR_i,
+		RD2_ADDR_i,
+		WDATA2_i,
+		RDATA2_o
+);
+
+parameter WR1_ADDR_WIDTH = 10;
+parameter RD1_ADDR_WIDTH = 10;
+parameter WR1_DATA_WIDTH = 18;
+parameter RD1_DATA_WIDTH = 18;
+parameter BE1_WIDTH = 2;
+
+parameter WR2_ADDR_WIDTH = 10;
+parameter RD2_ADDR_WIDTH = 10;
+parameter WR2_DATA_WIDTH = 18;
+parameter RD2_DATA_WIDTH = 18;
+parameter BE2_WIDTH = 2;
+
+input wire RESET_ni;
+
+input wire WEN1_i;
+input wire REN1_i;
+input wire WR1_CLK_i;
+input wire RD1_CLK_i;
+input wire [BE1_WIDTH-1:0] WR1_BE_i;
+input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i;
+input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i;
+input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i;
+output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o;
+
+input wire WEN2_i;
+input wire REN2_i;
+input wire WR2_CLK_i;
+input wire RD2_CLK_i;
+input wire [BE2_WIDTH-1:0] WR2_BE_i;
+input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i;
+input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i;
+input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i;
+output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o;
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+32, 36: mode = 3'b011;
+default: mode = 3'b000;
+endcase
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+wire [1:0] WR1_BE;
+wire [1:0] WR2_BE;
+
+wire [17:0] PORT_B1_RDATA;
+wire [17:0] PORT_A1_WDATA;
+
+wire [17:0] PORT_B2_RDATA;
+wire [17:0] PORT_A2_WDATA;
+
+wire [13:0] WR1_ADDR_INT;
+wire [13:0] RD1_ADDR_INT;
+
+wire [13:0] WR2_ADDR_INT;
+wire [13:0] RD2_ADDR_INT;
+
+wire [13:0] PORT_A1_ADDR;
+wire [13:0] PORT_B1_ADDR;
+
+wire [13:0] PORT_A2_ADDR;
+wire [13:0] PORT_B2_ADDR;
+
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(WR1_DATA_WIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(WR1_DATA_WIDTH);
+localparam [ 2:0] RMODE_A2_i    = mode(WR2_DATA_WIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(WR2_DATA_WIDTH);
+
+localparam [ 2:0] RMODE_B1_i    = mode(RD1_DATA_WIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(RD1_DATA_WIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(RD2_DATA_WIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(RD2_DATA_WIDTH);
+
+generate
+	if (WR1_ADDR_WIDTH == 14) begin
+		assign WR1_ADDR_INT = WR1_ADDR_i;
+	end else begin
+		assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0;
+		assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i;
+	end
+endgenerate
+
+case (WR1_DATA_WIDTH)
+	1: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A1_ADDR = WR1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (RD1_ADDR_WIDTH == 14) begin
+		assign RD1_ADDR_INT = RD1_ADDR_i;
+	end else begin
+		assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0;
+		assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i;
+	end
+endgenerate
+
+case (RD1_DATA_WIDTH)
+	1: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B1_ADDR = RD1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (WR2_ADDR_WIDTH == 14) begin
+		assign WR2_ADDR_INT = WR2_ADDR_i;
+	end else begin
+		assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0;
+		assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i;
+	end
+endgenerate
+
+case (WR2_DATA_WIDTH)
+	1: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A2_ADDR = WR2_ADDR_INT;
+	end
+endcase
+
+generate
+	if (RD2_ADDR_WIDTH == 14) begin
+		assign RD2_ADDR_INT = RD2_ADDR_i;
+	end else begin
+		assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0;
+		assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i;
+	end
+endgenerate
+
+case (RD2_DATA_WIDTH)
+	1: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B2_ADDR = RD2_ADDR_INT;
+	end
+endcase
+
+case (BE1_WIDTH)
+	2: begin
+		assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR1_BE[1:BE1_WIDTH] = 0;
+		assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0];
+	end
+endcase
+
+case (BE2_WIDTH)
+	2: begin
+		assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR2_BE[1:BE2_WIDTH] = 0;
+		assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0];
+	end
+endcase
+
+assign REN_A1_i = 1'b0;
+assign WEN_A1_i = WEN1_i;
+assign BE_A1_i = WR1_BE;
+assign REN_A2_i = 1'b0;
+assign WEN_A2_i = WEN2_i;
+assign BE_A2_i = WR2_BE;
+
+assign REN_B1_i = REN1_i;
+assign WEN_B1_i = 1'b0;
+assign BE_B1_i = 2'h0;
+assign REN_B2_i = REN2_i;
+assign WEN_B2_i = 1'b0;
+assign BE_B2_i = 2'h0;
+
+generate
+	if (WR1_DATA_WIDTH == 18) begin
+		assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0];
+	end else if (WR1_DATA_WIDTH == 9) begin
+		assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]};
+	end else begin
+		assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0;
+		assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A1_i = PORT_A1_WDATA[17:0];
+assign WDATA_B1_i = 18'h0;
+
+generate
+	if (RD1_DATA_WIDTH == 9) begin
+		assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]};
+	end else begin
+		assign PORT_B1_RDATA = RDATA_B1_o;
+	end
+endgenerate
+
+assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0];
+
+generate
+	if (WR2_DATA_WIDTH == 18) begin
+		assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0];
+	end else if (WR2_DATA_WIDTH == 9) begin
+		assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]};
+	end else begin
+		assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0;
+		assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A2_i = PORT_A2_WDATA[17:0];
+assign WDATA_B2_i = 18'h0;
+
+generate
+	if (RD2_DATA_WIDTH == 9) begin
+		assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]};
+	end else begin
+		assign PORT_B2_RDATA = RDATA_B2_o;
+	end
+endgenerate
+
+assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0];
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+};
+
+(* is_inferred = 0 *)
+(* is_split = 0 *)
+(* port_a_dwidth = WR1_DATA_WIDTH *)
+(* port_b_dwidth = RD1_DATA_WIDTH *)
+TDP36K _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+
+	.CLK_A1_i(WR1_CLK_i),
+	.ADDR_A1_i({1'b0,PORT_A1_ADDR}),
+	.WEN_A1_i(WEN_A1_i),
+	.BE_A1_i(BE_A1_i),
+	.WDATA_A1_i(WDATA_A1_i),
+	.REN_A1_i(REN_A1_i),
+	.RDATA_A1_o(RDATA_A1_o),
+
+	.CLK_A2_i(WR2_CLK_i),
+	.ADDR_A2_i(PORT_A2_ADDR),
+	.WEN_A2_i(WEN_A2_i),
+	.BE_A2_i(BE_A2_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.REN_A2_i(REN_A2_i),
+	.RDATA_A2_o(RDATA_A2_o),
+
+	.CLK_B1_i(RD1_CLK_i),
+	.ADDR_B1_i({1'b0,PORT_B1_ADDR}),
+	.WEN_B1_i(WEN_B1_i),
+	.BE_B1_i(BE_B1_i),
+	.WDATA_B1_i(WDATA_B1_i),
+	.REN_B1_i(REN_B1_i),
+	.RDATA_B1_o(RDATA_B1_o),
+
+	.CLK_B2_i(RD2_CLK_i),
+	.ADDR_B2_i(PORT_B2_ADDR),
+	.WEN_B2_i(WEN_B2_i),
+	.BE_B2_i(BE_B2_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.REN_B2_i(REN_B2_i),
+	.RDATA_B2_o(RDATA_B2_o),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
+
+module RAM_18K_BLK (
+		WEN_i,
+		REN_i,
+		WR_CLK_i,
+		RD_CLK_i,
+		WR_BE_i,
+		WR_ADDR_i,
+		RD_ADDR_i,
+		WDATA_i,
+		RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 18;
+parameter RD_DATA_WIDTH = 18;
+parameter BE_WIDTH = 2;
+
+input wire WEN_i;
+input wire REN_i;
+input wire WR_CLK_i;
+input wire RD_CLK_i;
+input wire [BE_WIDTH-1:0] WR_BE_i;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+	(* is_inferred = 0 *)
+	(* is_split = 0 *)
+	BRAM2x18_SP  #(
+			.WR1_ADDR_WIDTH(WR_ADDR_WIDTH),
+			.RD1_ADDR_WIDTH(RD_ADDR_WIDTH),
+			.WR1_DATA_WIDTH(WR_DATA_WIDTH),
+			.RD1_DATA_WIDTH(RD_DATA_WIDTH),
+			.BE1_WIDTH(BE_WIDTH),
+			.WR2_ADDR_WIDTH(),
+			.RD2_ADDR_WIDTH(),
+			.WR2_DATA_WIDTH(),
+			.RD2_DATA_WIDTH(),
+			.BE2_WIDTH()
+			 ) U1
+			(
+			.RESET_ni(1'b1),
+
+			.WEN1_i(WEN_i),
+			.REN1_i(REN_i),
+			.WR1_CLK_i(WR_CLK_i),
+			.RD1_CLK_i(RD_CLK_i),
+			.WR1_BE_i(WR_BE_i),
+			.WR1_ADDR_i(WR_ADDR_i),
+			.RD1_ADDR_i(RD_ADDR_i),
+			.WDATA1_i(WDATA_i),
+			.RDATA1_o(RDATA_o),
+
+			.WEN2_i(1'b0),
+			.REN2_i(1'b0),
+			.WR2_CLK_i(1'b0),
+			.RD2_CLK_i(1'b0),
+			.WR2_BE_i(2'b00),
+			.WR2_ADDR_i(14'h0),
+			.RD2_ADDR_i(14'h0),
+			.WDATA2_i(18'h0),
+			.RDATA2_o()
+			);
+
+endmodule
+
+module RAM_36K_BLK (
+		WEN_i,
+		REN_i,
+		WR_CLK_i,
+		RD_CLK_i,
+		WR_BE_i,
+		WR_ADDR_i,
+		RD_ADDR_i,
+		WDATA_i,
+		RDATA_o
+);
+
+parameter WR_ADDR_WIDTH = 10;
+parameter RD_ADDR_WIDTH = 10;
+parameter WR_DATA_WIDTH = 36;
+parameter RD_DATA_WIDTH = 36;
+parameter BE_WIDTH = 4;
+
+parameter INIT = 0;
+
+input wire WEN_i;
+input wire REN_i;
+input wire WR_CLK_i;
+input wire RD_CLK_i;
+input wire [BE_WIDTH-1:0] WR_BE_i;
+input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i;
+input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i;
+input wire [WR_DATA_WIDTH-1 :0] WDATA_i;
+output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+32, 36: mode = 3'b011;
+default: mode = 3'b000;
+endcase
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+wire [3:0] WR_BE;
+
+wire [35:0] PORT_B_RDATA;
+wire [35:0] PORT_A_WDATA;
+
+wire [14:0] WR_ADDR_INT;
+wire [14:0] RD_ADDR_INT;
+
+wire [14:0] PORT_A_ADDR;
+wire [14:0] PORT_B_ADDR;
+
+wire PORT_A_CLK;
+wire PORT_B_CLK;
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(WR_DATA_WIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(WR_DATA_WIDTH);
+localparam [ 2:0] RMODE_A2_i    = mode(WR_DATA_WIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(WR_DATA_WIDTH);
+
+localparam [ 2:0] RMODE_B1_i    = mode(RD_DATA_WIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(RD_DATA_WIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(RD_DATA_WIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(RD_DATA_WIDTH);
+
+assign PORT_A_CLK = WR_CLK_i;
+assign PORT_B_CLK = RD_CLK_i;
+
+generate
+	if (WR_ADDR_WIDTH == 15) begin
+		assign WR_ADDR_INT = WR_ADDR_i;
+	end else begin
+		assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0;
+		assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i;
+	end
+endgenerate
+
+case (WR_DATA_WIDTH)
+	1: begin
+		assign PORT_A_ADDR = WR_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A_ADDR = WR_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A_ADDR = WR_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A_ADDR = WR_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A_ADDR = WR_ADDR_INT << 4;
+	end
+	32, 36: begin
+		assign PORT_A_ADDR = WR_ADDR_INT << 5;
+	end
+	default: begin
+		assign PORT_A_ADDR = WR_ADDR_INT;
+	end
+endcase
+
+generate
+	if (RD_ADDR_WIDTH == 15) begin
+		assign RD_ADDR_INT = RD_ADDR_i;
+	end else begin
+		assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0;
+		assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i;
+	end
+endgenerate
+
+case (RD_DATA_WIDTH)
+	1: begin
+		assign PORT_B_ADDR = RD_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B_ADDR = RD_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B_ADDR = RD_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B_ADDR = RD_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B_ADDR = RD_ADDR_INT << 4;
+	end
+	32, 36: begin
+		assign PORT_B_ADDR = RD_ADDR_INT << 5;
+	end
+	default: begin
+		assign PORT_B_ADDR = RD_ADDR_INT;
+	end
+endcase
+
+case (BE_WIDTH)
+	4: begin
+		assign WR_BE = WR_BE_i[BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign WR_BE[3:BE_WIDTH] = 0;
+		assign WR_BE[BE_WIDTH-1 :0] = WR_BE_i[BE_WIDTH-1 :0];
+	end
+endcase
+
+assign REN_A1_i = 1'b0;
+assign WEN_A1_i = WEN_i;
+assign {BE_A2_i, BE_A1_i} = WR_BE;
+
+assign REN_B1_i = REN_i;
+assign WEN_B1_i = 1'b0;
+assign {BE_B2_i, BE_B1_i} = 4'h0;
+
+generate
+	if (WR_DATA_WIDTH == 36) begin
+		assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0];
+	end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin
+		assign PORT_A_WDATA[WR_DATA_WIDTH+1:18]  = WDATA_i[WR_DATA_WIDTH-1:16];
+		assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]};
+	end else if (WR_DATA_WIDTH == 9) begin
+		assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]};
+	end else begin
+		assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0;
+		assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A1_i = PORT_A_WDATA[17:0];
+assign WDATA_A2_i = PORT_A_WDATA[35:18];
+
+assign WDATA_B1_i = 18'h0;
+assign WDATA_B2_i = 18'h0;
+
+generate
+	if (RD_DATA_WIDTH == 36) begin
+		assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o};
+	end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin
+		assign PORT_B_RDATA  = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]};
+	end else if (RD_DATA_WIDTH == 9) begin
+		assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]};
+	end else begin
+		assign PORT_B_RDATA = {18'h0, RDATA_B1_o};
+	end
+endgenerate
+
+assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0];
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+};
+
+(* is_inferred = 1 *)
+(* is_split = 0 *)
+(* port_a_width = WR_DATA_WIDTH *)
+(* port_b_width = RD_DATA_WIDTH *)
+TDP36K _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+
+	.CLK_A1_i(PORT_A_CLK),
+	.ADDR_A1_i(PORT_A_ADDR),
+	.WEN_A1_i(WEN_A1_i),
+	.BE_A1_i(BE_A1_i),
+	.WDATA_A1_i(WDATA_A1_i),
+	.REN_A1_i(REN_A1_i),
+	.RDATA_A1_o(RDATA_A1_o),
+
+	.CLK_A2_i(PORT_A_CLK),
+	.ADDR_A2_i(PORT_A_ADDR[13:0]),
+	.WEN_A2_i(WEN_A1_i),
+	.BE_A2_i(BE_A2_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.REN_A2_i(REN_A1_i),
+	.RDATA_A2_o(RDATA_A2_o),
+
+	.CLK_B1_i(PORT_B_CLK),
+	.ADDR_B1_i(PORT_B_ADDR),
+	.WEN_B1_i(WEN_B1_i),
+	.BE_B1_i(BE_B1_i),
+	.WDATA_B1_i(WDATA_B1_i),
+	.REN_B1_i(REN_B1_i),
+	.RDATA_B1_o(RDATA_B1_o),
+
+	.CLK_B2_i(PORT_B_CLK),
+	.ADDR_B2_i(PORT_B_ADDR[13:0]),
+	.WEN_B2_i(WEN_B1_i),
+	.BE_B2_i(BE_B2_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.REN_B2_i(REN_B1_i),
+	.RDATA_B2_o(RDATA_B2_o),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
+
+
+module DPRAM_18K_X2_BLK (
+		PORT_A1_CLK_i,
+		PORT_A1_WEN_i,
+		PORT_A1_WR_BE_i,
+		PORT_A1_REN_i,
+		PORT_A1_ADDR_i,
+		PORT_A1_WR_DATA_i,
+		PORT_A1_RD_DATA_o,
+
+		PORT_B1_CLK_i,
+		PORT_B1_WEN_i,
+		PORT_B1_WR_BE_i,
+		PORT_B1_REN_i,
+		PORT_B1_ADDR_i,
+		PORT_B1_WR_DATA_i,
+		PORT_B1_RD_DATA_o,
+
+		PORT_A2_CLK_i,
+		PORT_A2_WEN_i,
+		PORT_A2_WR_BE_i,
+		PORT_A2_REN_i,
+		PORT_A2_ADDR_i,
+		PORT_A2_WR_DATA_i,
+		PORT_A2_RD_DATA_o,
+
+		PORT_B2_CLK_i,
+		PORT_B2_WEN_i,
+		PORT_B2_WR_BE_i,
+		PORT_B2_REN_i,
+		PORT_B2_ADDR_i,
+		PORT_B2_WR_DATA_i,
+		PORT_B2_RD_DATA_o
+);
+
+parameter PORT_A1_AWIDTH = 10;
+parameter PORT_A1_DWIDTH = 18;
+parameter PORT_A1_WR_BE_WIDTH = 2;
+
+parameter PORT_B1_AWIDTH = 10;
+parameter PORT_B1_DWIDTH = 18;
+parameter PORT_B1_WR_BE_WIDTH = 2;
+
+parameter PORT_A2_AWIDTH = 10;
+parameter PORT_A2_DWIDTH = 18;
+parameter PORT_A2_WR_BE_WIDTH = 2;
+
+parameter PORT_B2_AWIDTH = 10;
+parameter PORT_B2_DWIDTH = 18;
+parameter PORT_B2_WR_BE_WIDTH = 2;
+
+
+input wire PORT_A1_CLK_i;
+input wire [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i;
+input wire [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i;
+input wire PORT_A1_WEN_i;
+input wire [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i;
+input wire PORT_A1_REN_i;
+output wire [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o;
+
+input wire PORT_B1_CLK_i;
+input wire [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i;
+input wire [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i;
+input wire PORT_B1_WEN_i;
+input wire [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i;
+input wire PORT_B1_REN_i;
+output wire [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o;
+
+input wire PORT_A2_CLK_i;
+input wire [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i;
+input wire [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i;
+input wire PORT_A2_WEN_i;
+input wire [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i;
+input wire PORT_A2_REN_i;
+output wire [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o;
+
+input wire PORT_B2_CLK_i;
+input wire [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i;
+input wire [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i;
+input wire PORT_B2_WEN_i;
+input wire [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i;
+input wire PORT_B2_REN_i;
+output wire [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o;
+
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+32, 36: mode = 3'b011;
+default: mode = 3'b000;
+endcase
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+wire [1:0] PORT_A1_WR_BE;
+wire [1:0] PORT_B1_WR_BE;
+
+wire [1:0] PORT_A2_WR_BE;
+wire [1:0] PORT_B2_WR_BE;
+
+wire [17:0] PORT_B1_WDATA;
+wire [17:0] PORT_B1_RDATA;
+wire [17:0] PORT_A1_WDATA;
+wire [17:0] PORT_A1_RDATA;
+
+wire [17:0] PORT_B2_WDATA;
+wire [17:0] PORT_B2_RDATA;
+wire [17:0] PORT_A2_WDATA;
+wire [17:0] PORT_A2_RDATA;
+
+wire [13:0] PORT_A1_ADDR_INT;
+wire [13:0] PORT_B1_ADDR_INT;
+
+wire [13:0] PORT_A2_ADDR_INT;
+wire [13:0] PORT_B2_ADDR_INT;
+
+wire [13:0] PORT_A1_ADDR;
+wire [13:0] PORT_B1_ADDR;
+
+wire [13:0] PORT_A2_ADDR;
+wire [13:0] PORT_B2_ADDR;
+
+wire PORT_A1_CLK;
+wire PORT_B1_CLK;
+
+wire PORT_A2_CLK;
+wire PORT_B2_CLK;
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(PORT_A1_DWIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(PORT_A1_DWIDTH);
+localparam [ 2:0] RMODE_A2_i    = mode(PORT_A2_DWIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(PORT_A2_DWIDTH);
+
+localparam [ 2:0] RMODE_B1_i    = mode(PORT_B1_DWIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(PORT_B1_DWIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(PORT_B2_DWIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(PORT_B2_DWIDTH);
+
+assign PORT_A1_CLK = PORT_A1_CLK_i;
+assign PORT_B1_CLK = PORT_B1_CLK_i;
+
+assign PORT_A2_CLK = PORT_A2_CLK_i;
+assign PORT_B2_CLK = PORT_B2_CLK_i;
+
+generate
+	if (PORT_A1_AWIDTH == 14) begin
+		assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i;
+	end else begin
+		assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0;
+		assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i;
+	end
+endgenerate
+
+case (PORT_A1_DWIDTH)
+	1: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_B1_AWIDTH == 14) begin
+		assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i;
+	end else begin
+		assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0;
+		assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i;
+	end
+endgenerate
+
+case (PORT_B1_DWIDTH)
+	1: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_A2_AWIDTH == 14) begin
+		assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i;
+	end else begin
+		assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0;
+		assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i;
+	end
+endgenerate
+
+case (PORT_A2_DWIDTH)
+	1: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_B2_AWIDTH == 14) begin
+		assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i;
+	end else begin
+		assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0;
+		assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i;
+	end
+endgenerate
+
+case (PORT_B2_DWIDTH)
+	1: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT;
+	end
+endcase
+
+case (PORT_A1_WR_BE_WIDTH)
+	2: begin
+		assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0;
+		assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_B1_WR_BE_WIDTH)
+	2: begin
+		assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0;
+		assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_A2_WR_BE_WIDTH)
+	2: begin
+		assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0;
+		assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_B2_WR_BE_WIDTH)
+	2: begin
+		assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0;
+		assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+assign REN_A1_i = PORT_A1_REN_i;
+assign WEN_A1_i = PORT_A1_WEN_i;
+assign BE_A1_i  = PORT_A1_WR_BE;
+
+assign REN_A2_i = PORT_A2_REN_i;
+assign WEN_A2_i = PORT_A2_WEN_i;
+assign BE_A2_i  = PORT_A2_WR_BE;
+
+assign REN_B1_i = PORT_B1_REN_i;
+assign WEN_B1_i = PORT_B1_WEN_i;
+assign BE_B1_i  = PORT_B1_WR_BE;
+
+assign REN_B2_i = PORT_B2_REN_i;
+assign WEN_B2_i = PORT_B2_WEN_i;
+assign BE_B2_i  = PORT_B2_WR_BE;
+
+generate
+	if (PORT_A1_DWIDTH == 18) begin
+		assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0];
+	end else if (PORT_A1_DWIDTH == 9) begin
+		assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0;
+		assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A1_i = PORT_A1_WDATA;
+
+generate
+	if (PORT_A2_DWIDTH == 18) begin
+		assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0];
+	end else if (PORT_A2_DWIDTH == 9) begin
+		assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0;
+		assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A2_i = PORT_A2_WDATA;
+
+generate
+	if (PORT_A1_DWIDTH == 9) begin
+		assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]};
+	end else begin
+		assign PORT_A1_RDATA = RDATA_A1_o;
+	end
+endgenerate
+
+assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0];
+
+generate
+	if (PORT_A2_DWIDTH == 9) begin
+		assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]};
+	end else begin
+		assign PORT_A2_RDATA = RDATA_A2_o;
+	end
+endgenerate
+
+assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0];
+
+generate
+	if (PORT_B1_DWIDTH == 18) begin
+		assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0];
+	end else if (PORT_B1_DWIDTH == 9) begin
+		assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0;
+		assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_B1_i = PORT_B1_WDATA;
+
+generate
+	if (PORT_B2_DWIDTH == 18) begin
+		assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0];
+	end else if (PORT_B2_DWIDTH == 9) begin
+		assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0;
+		assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_B2_i = PORT_B2_WDATA;
+
+generate
+	if (PORT_B1_DWIDTH == 9) begin
+		assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]};
+	end else begin
+		assign PORT_B1_RDATA = RDATA_B1_o;
+	end
+endgenerate
+
+assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0];
+
+generate
+	if (PORT_B2_DWIDTH == 9) begin
+		assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]};
+	end else begin
+		assign PORT_B2_RDATA = RDATA_B2_o;
+	end
+endgenerate
+
+assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0];
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+};
+
+(* is_inferred = 0 *)
+(* is_split = 1 *)
+(* port_a1_dwidth = PORT_A1_DWIDTH *)
+(* port_a2_dwidth = PORT_A2_DWIDTH *)
+(* port_b1_dwidth = PORT_B1_DWIDTH *)
+(* port_b2_dwidth = PORT_B2_DWIDTH *)
+TDP36K _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+
+	.CLK_A1_i(PORT_A1_CLK),
+	.ADDR_A1_i({1'b0,PORT_A1_ADDR}),
+	.WEN_A1_i(WEN_A1_i),
+	.BE_A1_i(BE_A1_i),
+	.WDATA_A1_i(WDATA_A1_i),
+	.REN_A1_i(REN_A1_i),
+	.RDATA_A1_o(RDATA_A1_o),
+
+	.CLK_A2_i(PORT_A2_CLK),
+	.ADDR_A2_i(PORT_A2_ADDR),
+	.WEN_A2_i(WEN_A2_i),
+	.BE_A2_i(BE_A2_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.REN_A2_i(REN_A2_i),
+	.RDATA_A2_o(RDATA_A2_o),
+
+	.CLK_B1_i(PORT_B1_CLK),
+	.ADDR_B1_i({1'b0,PORT_B1_ADDR}),
+	.WEN_B1_i(WEN_B1_i),
+	.BE_B1_i(BE_B1_i),
+	.WDATA_B1_i(WDATA_B1_i),
+	.REN_B1_i(REN_B1_i),
+	.RDATA_B1_o(RDATA_B1_o),
+
+	.CLK_B2_i(PORT_B2_CLK),
+	.ADDR_B2_i(PORT_B2_ADDR),
+	.WEN_B2_i(WEN_B2_i),
+	.BE_B2_i(BE_B2_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.REN_B2_i(REN_B2_i),
+	.RDATA_B2_o(RDATA_B2_o),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
+
+module BRAM2x18_dP (
+		PORT_A1_CLK_i,
+		PORT_A1_WEN_i,
+		PORT_A1_WR_BE_i,
+		PORT_A1_REN_i,
+		PORT_A1_ADDR_i,
+		PORT_A1_WR_DATA_i,
+		PORT_A1_RD_DATA_o,
+
+		PORT_B1_CLK_i,
+		PORT_B1_WEN_i,
+		PORT_B1_WR_BE_i,
+		PORT_B1_REN_i,
+		PORT_B1_ADDR_i,
+		PORT_B1_WR_DATA_i,
+		PORT_B1_RD_DATA_o,
+
+		PORT_A2_CLK_i,
+		PORT_A2_WEN_i,
+		PORT_A2_WR_BE_i,
+		PORT_A2_REN_i,
+		PORT_A2_ADDR_i,
+		PORT_A2_WR_DATA_i,
+		PORT_A2_RD_DATA_o,
+
+		PORT_B2_CLK_i,
+		PORT_B2_WEN_i,
+		PORT_B2_WR_BE_i,
+		PORT_B2_REN_i,
+		PORT_B2_ADDR_i,
+		PORT_B2_WR_DATA_i,
+		PORT_B2_RD_DATA_o
+);
+
+parameter PORT_A1_AWIDTH = 10;
+parameter PORT_A1_DWIDTH = 18;
+parameter PORT_A1_WR_BE_WIDTH = 2;
+
+parameter PORT_B1_AWIDTH = 10;
+parameter PORT_B1_DWIDTH = 18;
+parameter PORT_B1_WR_BE_WIDTH = 2;
+
+parameter PORT_A2_AWIDTH = 10;
+parameter PORT_A2_DWIDTH = 18;
+parameter PORT_A2_WR_BE_WIDTH = 2;
+
+parameter PORT_B2_AWIDTH = 10;
+parameter PORT_B2_DWIDTH = 18;
+parameter PORT_B2_WR_BE_WIDTH = 2;
+
+input wire PORT_A1_CLK_i;
+input wire [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i;
+input wire [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i;
+input wire PORT_A1_WEN_i;
+input wire [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i;
+input wire PORT_A1_REN_i;
+output wire [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o;
+
+input wire PORT_B1_CLK_i;
+input wire [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i;
+input wire [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i;
+input wire PORT_B1_WEN_i;
+input wire [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i;
+input wire PORT_B1_REN_i;
+output wire [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o;
+
+input wire PORT_A2_CLK_i;
+input wire [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i;
+input wire [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i;
+input wire PORT_A2_WEN_i;
+input wire [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i;
+input wire PORT_A2_REN_i;
+output wire [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o;
+
+input wire PORT_B2_CLK_i;
+input wire [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i;
+input wire [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i;
+input wire PORT_B2_WEN_i;
+input wire [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i;
+input wire PORT_B2_REN_i;
+output wire [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o;
+
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+32, 36: mode = 3'b011;
+default: mode = 3'b000;
+endcase
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+wire [1:0] PORT_A1_WR_BE;
+wire [1:0] PORT_B1_WR_BE;
+
+wire [1:0] PORT_A2_WR_BE;
+wire [1:0] PORT_B2_WR_BE;
+
+wire [17:0] PORT_B1_WDATA;
+wire [17:0] PORT_B1_RDATA;
+wire [17:0] PORT_A1_WDATA;
+wire [17:0] PORT_A1_RDATA;
+
+wire [17:0] PORT_B2_WDATA;
+wire [17:0] PORT_B2_RDATA;
+wire [17:0] PORT_A2_WDATA;
+wire [17:0] PORT_A2_RDATA;
+
+wire [13:0] PORT_A1_ADDR_INT;
+wire [13:0] PORT_B1_ADDR_INT;
+
+wire [13:0] PORT_A2_ADDR_INT;
+wire [13:0] PORT_B2_ADDR_INT;
+
+wire [13:0] PORT_A1_ADDR;
+wire [13:0] PORT_B1_ADDR;
+
+wire [13:0] PORT_A2_ADDR;
+wire [13:0] PORT_B2_ADDR;
+
+wire PORT_A1_CLK;
+wire PORT_B1_CLK;
+
+wire PORT_A2_CLK;
+wire PORT_B2_CLK;
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(PORT_A1_DWIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(PORT_A1_DWIDTH);
+localparam [ 2:0] RMODE_A2_i    = mode(PORT_A2_DWIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(PORT_A2_DWIDTH);
+
+localparam [ 2:0] RMODE_B1_i    = mode(PORT_B1_DWIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(PORT_B1_DWIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(PORT_B2_DWIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(PORT_B2_DWIDTH);
+
+assign PORT_A1_CLK = PORT_A1_CLK_i;
+assign PORT_B1_CLK = PORT_B1_CLK_i;
+
+assign PORT_A2_CLK = PORT_A2_CLK_i;
+assign PORT_B2_CLK = PORT_B2_CLK_i;
+
+generate
+	if (PORT_A1_AWIDTH == 14) begin
+		assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i;
+	end else begin
+		assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0;
+		assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i;
+	end
+endgenerate
+
+case (PORT_A1_DWIDTH)
+	1: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A1_ADDR = PORT_A1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_B1_AWIDTH == 14) begin
+		assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i;
+	end else begin
+		assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0;
+		assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i;
+	end
+endgenerate
+
+case (PORT_B1_DWIDTH)
+	1: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B1_ADDR = PORT_B1_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_A2_AWIDTH == 14) begin
+		assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i;
+	end else begin
+		assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0;
+		assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i;
+	end
+endgenerate
+
+case (PORT_A2_DWIDTH)
+	1: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_A2_ADDR = PORT_A2_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_B2_AWIDTH == 14) begin
+		assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i;
+	end else begin
+		assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0;
+		assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i;
+	end
+endgenerate
+
+case (PORT_B2_DWIDTH)
+	1: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4;
+	end
+	default: begin
+		assign PORT_B2_ADDR = PORT_B2_ADDR_INT;
+	end
+endcase
+
+case (PORT_A1_WR_BE_WIDTH)
+	2: begin
+		assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0;
+		assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_B1_WR_BE_WIDTH)
+	2: begin
+		assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0;
+		assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_A2_WR_BE_WIDTH)
+	2: begin
+		assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0;
+		assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_B2_WR_BE_WIDTH)
+	2: begin
+		assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0;
+		assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+assign REN_A1_i = PORT_A1_REN_i;
+assign WEN_A1_i = PORT_A1_WEN_i;
+assign BE_A1_i  = PORT_A1_WR_BE;
+
+assign REN_A2_i = PORT_A2_REN_i;
+assign WEN_A2_i = PORT_A2_WEN_i;
+assign BE_A2_i  = PORT_A2_WR_BE;
+
+assign REN_B1_i = PORT_B1_REN_i;
+assign WEN_B1_i = PORT_B1_WEN_i;
+assign BE_B1_i  = PORT_B1_WR_BE;
+
+assign REN_B2_i = PORT_B2_REN_i;
+assign WEN_B2_i = PORT_B2_WEN_i;
+assign BE_B2_i  = PORT_B2_WR_BE;
+
+generate
+	if (PORT_A1_DWIDTH == 18) begin
+		assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0];
+	end else if (PORT_A1_DWIDTH == 9) begin
+		assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0;
+		assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A1_i = PORT_A1_WDATA;
+
+generate
+	if (PORT_A2_DWIDTH == 18) begin
+		assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0];
+	end else if (PORT_A2_DWIDTH == 9) begin
+		assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0;
+		assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A2_i = PORT_A2_WDATA;
+
+generate
+	if (PORT_A1_DWIDTH == 9) begin
+		assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]};
+	end else begin
+		assign PORT_A1_RDATA = RDATA_A1_o;
+	end
+endgenerate
+
+assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0];
+
+generate
+	if (PORT_A2_DWIDTH == 9) begin
+		assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]};
+	end else begin
+		assign PORT_A2_RDATA = RDATA_A2_o;
+	end
+endgenerate
+
+assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0];
+
+generate
+	if (PORT_B1_DWIDTH == 18) begin
+		assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0];
+	end else if (PORT_B1_DWIDTH == 9) begin
+		assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0;
+		assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_B1_i = PORT_B1_WDATA;
+
+generate
+	if (PORT_B2_DWIDTH == 18) begin
+		assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0];
+	end else if (PORT_B2_DWIDTH == 9) begin
+		assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0;
+		assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_B2_i = PORT_B2_WDATA;
+
+generate
+	if (PORT_B1_DWIDTH == 9) begin
+		assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]};
+	end else begin
+		assign PORT_B1_RDATA = RDATA_B1_o;
+	end
+endgenerate
+
+assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0];
+
+generate
+	if (PORT_B2_DWIDTH == 9) begin
+		assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]};
+	end else begin
+		assign PORT_B2_RDATA = RDATA_B2_o;
+	end
+endgenerate
+
+assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0];
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+};
+
+(* is_inferred = 0 *)
+(* is_split = 0 *)
+(* port_a_dwidth = PORT_A1_DWIDTH *)
+(* port_b_dwidth = PORT_B1_DWIDTH *)
+TDP36K _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+
+	.CLK_A1_i(PORT_A1_CLK),
+	.ADDR_A1_i({1'b0,PORT_A1_ADDR}),
+	.WEN_A1_i(WEN_A1_i),
+	.BE_A1_i(BE_A1_i),
+	.WDATA_A1_i(WDATA_A1_i),
+	.REN_A1_i(REN_A1_i),
+	.RDATA_A1_o(RDATA_A1_o),
+
+	.CLK_A2_i(PORT_A2_CLK),
+	.ADDR_A2_i(PORT_A2_ADDR),
+	.WEN_A2_i(WEN_A2_i),
+	.BE_A2_i(BE_A2_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.REN_A2_i(REN_A2_i),
+	.RDATA_A2_o(RDATA_A2_o),
+
+	.CLK_B1_i(PORT_B1_CLK),
+	.ADDR_B1_i({1'b0,PORT_B1_ADDR}),
+	.WEN_B1_i(WEN_B1_i),
+	.BE_B1_i(BE_B1_i),
+	.WDATA_B1_i(WDATA_B1_i),
+	.REN_B1_i(REN_B1_i),
+	.RDATA_B1_o(RDATA_B1_o),
+
+	.CLK_B2_i(PORT_B2_CLK),
+	.ADDR_B2_i(PORT_B2_ADDR),
+	.WEN_B2_i(WEN_B2_i),
+	.BE_B2_i(BE_B2_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.REN_B2_i(REN_B2_i),
+	.RDATA_B2_o(RDATA_B2_o),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
+
+module DPRAM_18K_BLK (
+		PORT_A_CLK_i,
+		PORT_A_WEN_i,
+		PORT_A_WR_BE_i,
+		PORT_A_REN_i,
+		PORT_A_ADDR_i,
+		PORT_A_WR_DATA_i,
+		PORT_A_RD_DATA_o,
+
+		PORT_B_CLK_i,
+		PORT_B_WEN_i,
+		PORT_B_WR_BE_i,
+		PORT_B_REN_i,
+		PORT_B_ADDR_i,
+		PORT_B_WR_DATA_i,
+		PORT_B_RD_DATA_o
+);
+
+parameter PORT_A_AWIDTH = 10;
+parameter PORT_A_DWIDTH = 36;
+parameter PORT_A_WR_BE_WIDTH = 4;
+
+parameter PORT_B_AWIDTH = 10;
+parameter PORT_B_DWIDTH = 36;
+parameter PORT_B_WR_BE_WIDTH = 4;
+
+input wire PORT_A_CLK_i;
+input wire [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i;
+input wire [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i;
+input wire PORT_A_WEN_i;
+input wire [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i;
+input wire PORT_A_REN_i;
+output wire [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o;
+
+input wire PORT_B_CLK_i;
+input wire [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i;
+input wire [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i;
+input wire PORT_B_WEN_i;
+input wire [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i;
+input wire PORT_B_REN_i;
+output wire [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o;
+
+
+(* is_inferred = 0 *)
+(* is_split = 0 *)
+BRAM2x18_dP #(
+	.PORT_A1_AWIDTH(PORT_A_AWIDTH),
+	.PORT_A1_DWIDTH(PORT_A_DWIDTH),
+	.PORT_A1_WR_BE_WIDTH(PORT_A_WR_BE_WIDTH),
+	.PORT_B1_AWIDTH(PORT_B_AWIDTH),
+	.PORT_B1_DWIDTH(PORT_B_DWIDTH),
+	.PORT_B1_WR_BE_WIDTH(PORT_B_WR_BE_WIDTH),
+	.PORT_A2_AWIDTH(),
+	.PORT_A2_DWIDTH(),
+	.PORT_A2_WR_BE_WIDTH(),
+	.PORT_B2_AWIDTH(),
+	.PORT_B2_DWIDTH(),
+	.PORT_B2_WR_BE_WIDTH()
+) U1 (
+		.PORT_A1_CLK_i(PORT_A_CLK_i),
+		.PORT_A1_WEN_i(PORT_A_WEN_i),
+		.PORT_A1_WR_BE_i(PORT_A_WR_BE_i),
+		.PORT_A1_REN_i(PORT_A_REN_i),
+		.PORT_A1_ADDR_i(PORT_A_ADDR_i),
+		.PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i),
+		.PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o),
+
+		.PORT_B1_CLK_i(PORT_B_CLK_i),
+		.PORT_B1_WEN_i(PORT_B_WEN_i),
+		.PORT_B1_WR_BE_i(PORT_B_WR_BE_i),
+		.PORT_B1_REN_i(PORT_B_REN_i),
+		.PORT_B1_ADDR_i(PORT_B_ADDR_i),
+		.PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i),
+		.PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o),
+
+		.PORT_A2_CLK_i(1'b0),
+		.PORT_A2_WEN_i(1'b0),
+		.PORT_A2_WR_BE_i(2'b00),
+		.PORT_A2_REN_i(1'b0),
+		.PORT_A2_ADDR_i(14'h0),
+		.PORT_A2_WR_DATA_i(18'h0),
+		.PORT_A2_RD_DATA_o(),
+
+		.PORT_B2_CLK_i(1'b0),
+		.PORT_B2_WEN_i(1'b0),
+		.PORT_B2_WR_BE_i(2'b00),
+		.PORT_B2_REN_i(1'b0),
+		.PORT_B2_ADDR_i(14'h0),
+		.PORT_B2_WR_DATA_i(18'h0),
+		.PORT_B2_RD_DATA_o()
+);
+
+endmodule
+
+module DPRAM_36K_BLK (
+		PORT_A_CLK_i,
+		PORT_A_WEN_i,
+		PORT_A_WR_BE_i,
+		PORT_A_REN_i,
+		PORT_A_ADDR_i,
+		PORT_A_WR_DATA_i,
+		PORT_A_RD_DATA_o,
+
+		PORT_B_CLK_i,
+		PORT_B_WEN_i,
+		PORT_B_WR_BE_i,
+		PORT_B_REN_i,
+		PORT_B_ADDR_i,
+		PORT_B_WR_DATA_i,
+		PORT_B_RD_DATA_o
+);
+
+parameter PORT_A_AWIDTH = 10;
+parameter PORT_A_DWIDTH = 36;
+parameter PORT_A_WR_BE_WIDTH = 4;
+
+parameter PORT_B_AWIDTH = 10;
+parameter PORT_B_DWIDTH = 36;
+parameter PORT_B_WR_BE_WIDTH = 4;
+
+input wire PORT_A_CLK_i;
+input wire [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i;
+input wire [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i;
+input wire PORT_A_WEN_i;
+input wire [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i;
+input wire PORT_A_REN_i;
+output wire [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o;
+
+input wire PORT_B_CLK_i;
+input wire [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i;
+input wire [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i;
+input wire PORT_B_WEN_i;
+input wire [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i;
+input wire PORT_B_REN_i;
+output wire [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o;
+
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+32, 36: mode = 3'b011;
+default: mode = 3'b000;
+endcase
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+wire [3:0] PORT_A_WR_BE;
+wire [3:0] PORT_B_WR_BE;
+
+wire [35:0] PORT_B_WDATA;
+wire [35:0] PORT_B_RDATA;
+wire [35:0] PORT_A_WDATA;
+wire [35:0] PORT_A_RDATA;
+
+wire [14:0] PORT_A_ADDR_INT;
+wire [14:0] PORT_B_ADDR_INT;
+
+wire [14:0] PORT_A_ADDR;
+wire [14:0] PORT_B_ADDR;
+
+wire PORT_A_CLK;
+wire PORT_B_CLK;
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(PORT_A_DWIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(PORT_A_DWIDTH);
+localparam [ 2:0] RMODE_A2_i    = mode(PORT_A_DWIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(PORT_A_DWIDTH);
+
+localparam [ 2:0] RMODE_B1_i    = mode(PORT_B_DWIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(PORT_B_DWIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(PORT_B_DWIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(PORT_B_DWIDTH);
+
+assign PORT_A_CLK = PORT_A_CLK_i;
+assign PORT_B_CLK = PORT_B_CLK_i;
+
+generate
+	if (PORT_A_AWIDTH == 15) begin
+		assign PORT_A_ADDR_INT = PORT_A_ADDR_i;
+	end else begin
+		assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0;
+		assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i;
+	end
+endgenerate
+
+case (PORT_A_DWIDTH)
+	1: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT;
+	end
+	2: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT << 4;
+	end
+	32, 36: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT << 5;
+	end
+	default: begin
+		assign PORT_A_ADDR = PORT_A_ADDR_INT;
+	end
+endcase
+
+generate
+	if (PORT_B_AWIDTH == 15) begin
+		assign PORT_B_ADDR_INT = PORT_B_ADDR_i;
+	end else begin
+		assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0;
+		assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i;
+	end
+endgenerate
+
+case (PORT_B_DWIDTH)
+	1: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT;
+	end
+	2: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT << 1;
+	end
+	4: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT << 2;
+	end
+	8, 9: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT << 3;
+	end
+	16, 18: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT << 4;
+	end
+	32, 36: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT << 5;
+	end
+	default: begin
+		assign PORT_B_ADDR = PORT_B_ADDR_INT;
+	end
+endcase
+
+case (PORT_A_WR_BE_WIDTH)
+	4: begin
+		assign PORT_A_WR_BE = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_A_WR_BE[3:PORT_A_WR_BE_WIDTH] = 0;
+		assign PORT_A_WR_BE[PORT_A_WR_BE_WIDTH-1 :0] = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+case (PORT_B_WR_BE_WIDTH)
+	4: begin
+		assign PORT_B_WR_BE = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0];
+	end
+	default: begin
+		assign PORT_B_WR_BE[3:PORT_B_WR_BE_WIDTH] = 0;
+		assign PORT_B_WR_BE[PORT_B_WR_BE_WIDTH-1 :0] = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0];
+	end
+endcase
+
+assign REN_A1_i = PORT_A_REN_i;
+assign WEN_A1_i = PORT_A_WEN_i;
+assign {BE_A2_i, BE_A1_i} = PORT_A_WR_BE;
+
+assign REN_B1_i = PORT_B_REN_i;
+assign WEN_B1_i = PORT_B_WEN_i;
+assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE;
+
+generate
+	if (PORT_A_DWIDTH == 36) begin
+		assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0];
+	end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin
+		assign PORT_A_WDATA[PORT_A_DWIDTH+1:18]  = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16];
+		assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]};
+	end else if (PORT_A_DWIDTH == 9) begin
+		assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0;
+		assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_A1_i = PORT_A_WDATA[17:0];
+assign WDATA_A2_i = PORT_A_WDATA[35:18];
+
+generate
+	if (PORT_A_DWIDTH == 36) begin
+		assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o};
+	end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin
+		assign PORT_A_RDATA  = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]};
+	end else if (PORT_A_DWIDTH == 9) begin
+		assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]};
+	end else begin
+		assign PORT_A_RDATA = {18'h0, RDATA_A1_o};
+	end
+endgenerate
+
+assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0];
+
+generate
+	if (PORT_B_DWIDTH == 36) begin
+		assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0];
+	end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin
+		assign PORT_B_WDATA[PORT_B_DWIDTH+1:18]  = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16];
+		assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]};
+	end else if (PORT_B_DWIDTH == 9) begin
+		assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]};
+	end else begin
+		assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0;
+		assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0];
+	end
+endgenerate
+
+assign WDATA_B1_i = PORT_B_WDATA[17:0];
+assign WDATA_B2_i = PORT_B_WDATA[35:18];
+
+generate
+	if (PORT_B_DWIDTH == 36) begin
+		assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o};
+	end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin
+		assign PORT_B_RDATA  = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]};
+	end else if (PORT_B_DWIDTH == 9) begin
+		assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]};
+	end else begin
+		assign PORT_B_RDATA = {18'h0, RDATA_B1_o};
+	end
+endgenerate
+
+assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0];
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+};
+
+(* is_inferred = 1 *)
+(* is_split = 0 *)
+(* port_a_width = PORT_A_DWIDTH *)
+(* port_b_width = PORT_B_DWIDTH *)
+TDP36K _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+
+	.CLK_A1_i(PORT_A_CLK),
+	.ADDR_A1_i(PORT_A_ADDR),
+	.WEN_A1_i(WEN_A1_i),
+	.BE_A1_i(BE_A1_i),
+	.WDATA_A1_i(WDATA_A1_i),
+	.REN_A1_i(REN_A1_i),
+	.RDATA_A1_o(RDATA_A1_o),
+
+	.CLK_A2_i(PORT_A_CLK),
+	.ADDR_A2_i(PORT_A_ADDR[13:0]),
+	.WEN_A2_i(WEN_A1_i),
+	.BE_A2_i(BE_A2_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.REN_A2_i(REN_A1_i),
+	.RDATA_A2_o(RDATA_A2_o),
+
+	.CLK_B1_i(PORT_B_CLK),
+	.ADDR_B1_i(PORT_B_ADDR),
+	.WEN_B1_i(WEN_B1_i),
+	.BE_B1_i(BE_B1_i),
+	.WDATA_B1_i(WDATA_B1_i),
+	.REN_B1_i(REN_B1_i),
+	.RDATA_B1_o(RDATA_B1_o),
+
+	.CLK_B2_i(PORT_B_CLK),
+	.ADDR_B2_i(PORT_B_ADDR[13:0]),
+	.WEN_B2_i(WEN_B1_i),
+	.BE_B2_i(BE_B2_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.REN_B2_i(REN_B1_i),
+	.RDATA_B2_o(RDATA_B2_o),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
+
+module BRAM2x18_SFIFO (
+		DIN1,
+		PUSH1,
+		POP1,
+		CLK1,
+		Async_Flush1,
+		Overrun_Error1,
+		Full_Watermark1,
+		Almost_Full1,
+		Full1,
+		Underrun_Error1,
+		Empty_Watermark1,
+		Almost_Empty1,
+		Empty1,
+		DOUT1,
+
+		DIN2,
+		PUSH2,
+		POP2,
+		CLK2,
+		Async_Flush2,
+		Overrun_Error2,
+		Full_Watermark2,
+		Almost_Full2,
+		Full2,
+		Underrun_Error2,
+		Empty_Watermark2,
+		Almost_Empty2,
+		Empty2,
+		DOUT2
+);
+
+	parameter WR1_DATA_WIDTH = 18;
+	parameter RD1_DATA_WIDTH = 18;
+
+	parameter WR2_DATA_WIDTH = 18;
+	parameter RD2_DATA_WIDTH = 18;
+
+	parameter UPAE_DBITS1 = 12'd10;
+	parameter UPAF_DBITS1 = 12'd10;
+
+	parameter UPAE_DBITS2 = 11'd10;
+	parameter UPAF_DBITS2 = 11'd10;
+
+	input wire CLK1;
+	input wire PUSH1, POP1;
+	input wire [WR1_DATA_WIDTH-1:0] DIN1;
+	input wire Async_Flush1;
+	output wire [RD1_DATA_WIDTH-1:0] DOUT1;
+	output wire Almost_Full1, Almost_Empty1;
+	output wire Full1, Empty1;
+	output wire Full_Watermark1, Empty_Watermark1;
+	output wire Overrun_Error1, Underrun_Error1;
+
+	input wire CLK2;
+	input wire PUSH2, POP2;
+	input wire [WR2_DATA_WIDTH-1:0] DIN2;
+	input wire Async_Flush2;
+	output wire [RD2_DATA_WIDTH-1:0] DOUT2;
+	output wire Almost_Full2, Almost_Empty2;
+	output wire Full2, Empty2;
+	output wire Full_Watermark2, Empty_Watermark2;
+	output wire Overrun_Error2, Underrun_Error2;
+
+	// Fixed mode settings
+	localparam [ 0:0] SYNC_FIFO1_i  = 1'd1;
+	localparam [ 0:0] FMODE1_i      = 1'd1;
+	localparam [ 0:0] POWERDN1_i    = 1'd0;
+	localparam [ 0:0] SLEEP1_i      = 1'd0;
+	localparam [ 0:0] PROTECT1_i    = 1'd0;
+	localparam [11:0] UPAE1_i       = UPAE_DBITS1;
+	localparam [11:0] UPAF1_i       = UPAF_DBITS1;
+
+	localparam [ 0:0] SYNC_FIFO2_i  = 1'd1;
+	localparam [ 0:0] FMODE2_i      = 1'd1;
+	localparam [ 0:0] POWERDN2_i    = 1'd0;
+	localparam [ 0:0] SLEEP2_i      = 1'd0;
+	localparam [ 0:0] PROTECT2_i    = 1'd0;
+	localparam [10:0] UPAE2_i       = UPAE_DBITS2;
+	localparam [10:0] UPAF2_i       = UPAF_DBITS2;
+
+	// Width mode function
+	function [2:0] mode;
+	input integer width;
+	case (width)
+	1: mode = 3'b101;
+	2: mode = 3'b110;
+	4: mode = 3'b100;
+	8,9: mode = 3'b001;
+	16, 18: mode = 3'b010;
+	32, 36: mode = 3'b011;
+	default: mode = 3'b000;
+	endcase
+	endfunction
+
+	wire [17:0] in_reg1;
+	wire [17:0] out_reg1;
+	wire [17:0] fifo1_flags;
+
+	wire [17:0] in_reg2;
+	wire [17:0] out_reg2;
+	wire [17:0] fifo2_flags;
+
+	wire Push_Clk1, Pop_Clk1;
+	wire Push_Clk2, Pop_Clk2;
+	assign Push_Clk1 = CLK1;
+	assign Pop_Clk1 = CLK1;
+	assign Push_Clk2 = CLK2;
+	assign Pop_Clk2 = CLK2;
+
+	assign Overrun_Error1 = fifo1_flags[0];
+	assign Full_Watermark1 = fifo1_flags[1];
+	assign Almost_Full1 = fifo1_flags[2];
+	assign Full1 = fifo1_flags[3];
+	assign Underrun_Error1 = fifo1_flags[4];
+	assign Empty_Watermark1 = fifo1_flags[5];
+	assign Almost_Empty1 = fifo1_flags[6];
+	assign Empty1 = fifo1_flags[7];
+
+	assign Overrun_Error2 = fifo2_flags[0];
+	assign Full_Watermark2 = fifo2_flags[1];
+	assign Almost_Full2 = fifo2_flags[2];
+	assign Full2 = fifo2_flags[3];
+	assign Underrun_Error2 = fifo2_flags[4];
+	assign Empty_Watermark2 = fifo2_flags[5];
+	assign Almost_Empty2 = fifo2_flags[6];
+	assign Empty2 = fifo2_flags[7];
+
+	localparam [ 2:0] RMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_A2_i    = mode(WR2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A2_i    = mode(WR2_DATA_WIDTH);
+
+	localparam [ 2:0] RMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_B2_i    = mode(RD2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B2_i    = mode(RD2_DATA_WIDTH);
+
+	generate
+		if (WR1_DATA_WIDTH == 18) begin
+			assign in_reg1[17:0] = DIN1[17:0];
+		end else if (WR1_DATA_WIDTH == 9) begin
+			assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]};
+		end else begin
+			assign in_reg1[17:WR1_DATA_WIDTH]  = 0;
+			assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD1_DATA_WIDTH == 9) begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]};
+		end else begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (WR2_DATA_WIDTH == 18) begin
+			assign in_reg2[17:0] = DIN2[17:0];
+		end else if (WR2_DATA_WIDTH == 9) begin
+			assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]};
+		end else begin
+			assign in_reg2[17:WR2_DATA_WIDTH]  = 0;
+			assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD2_DATA_WIDTH == 9) begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]};
+		end else begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+	};
+
+	(* is_fifo = 1 *)
+	(* sync_fifo = 1 *)
+	(* is_split = 0 *)
+	(* is_inferred = 0 *)
+	(* port_a_dwidth = WR1_DATA_WIDTH *)
+	(* port_b_dwidth = RD1_DATA_WIDTH *)
+ 	TDP36K _TECHMAP_REPLACE_ (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg1[17:0]),
+		.WDATA_A2_i(in_reg2[17:0]),
+		.RDATA_A1_o(fifo1_flags),
+		.RDATA_A2_o(fifo2_flags),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk1),
+		.CLK_A2_i(Push_Clk2),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b1),
+		.WEN_A1_i(PUSH1),
+		.WEN_A2_i(PUSH2),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg1[17:0]),
+		.RDATA_B2_o(out_reg2[17:0]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk1),
+		.CLK_B2_i(Pop_Clk2),
+		.REN_B1_i(POP1),
+		.REN_B2_i(POP2),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush1),
+		.FLUSH2_i(Async_Flush2)
+	);
+
+endmodule
+
+module SFIFO_18K_BLK (
+		DIN,
+		PUSH,
+		POP,
+		CLK,
+		Async_Flush,
+		Overrun_Error,
+		Full_Watermark,
+		Almost_Full,
+		Full,
+		Underrun_Error,
+		Empty_Watermark,
+		Almost_Empty,
+		Empty,
+		DOUT
+);
+
+	parameter WR_DATA_WIDTH = 18;
+	parameter RD_DATA_WIDTH = 18;
+	parameter UPAE_DBITS = 11'd10;
+	parameter UPAF_DBITS = 11'd10;
+
+	input wire CLK;
+	input wire PUSH, POP;
+	input wire [WR_DATA_WIDTH-1:0] DIN;
+	input wire Async_Flush;
+	output wire [RD_DATA_WIDTH-1:0] DOUT;
+	output wire Almost_Full, Almost_Empty;
+	output wire Full, Empty;
+	output wire Full_Watermark, Empty_Watermark;
+	output wire Overrun_Error, Underrun_Error;
+
+ 	BRAM2x18_SFIFO  #(
+			.WR1_DATA_WIDTH(WR_DATA_WIDTH),
+			.RD1_DATA_WIDTH(RD_DATA_WIDTH),
+			.UPAE_DBITS1(UPAE_DBITS),
+			.UPAF_DBITS1(UPAF_DBITS),
+			.WR2_DATA_WIDTH(),
+			.RD2_DATA_WIDTH(),
+			.UPAE_DBITS2(),
+			.UPAF_DBITS2()
+			 ) U1
+			(
+			.DIN1(DIN),
+			.PUSH1(PUSH),
+			.POP1(POP),
+			.CLK1(CLK),
+			.Async_Flush1(Async_Flush),
+			.Overrun_Error1(Overrun_Error),
+			.Full_Watermark1(Full_Watermark),
+			.Almost_Full1(Almost_Full),
+			.Full1(Full),
+			.Underrun_Error1(Underrun_Error),
+			.Empty_Watermark1(Empty_Watermark),
+			.Almost_Empty1(Almost_Empty),
+			.Empty1(Empty),
+			.DOUT1(DOUT),
+
+			.DIN2(18'h0),
+			.PUSH2(1'b0),
+			.POP2(1'b0),
+			.CLK2(1'b0),
+			.Async_Flush2(1'b0),
+			.Overrun_Error2(),
+			.Full_Watermark2(),
+			.Almost_Full2(),
+			.Full2(),
+			.Underrun_Error2(),
+			.Empty_Watermark2(),
+			.Almost_Empty2(),
+			.Empty2(),
+			.DOUT2()
+	);
+
+endmodule
+
+module SFIFO_18K_X2_BLK (
+		DIN1,
+		PUSH1,
+		POP1,
+		CLK1,
+		Async_Flush1,
+		Overrun_Error1,
+		Full_Watermark1,
+		Almost_Full1,
+		Full1,
+		Underrun_Error1,
+		Empty_Watermark1,
+		Almost_Empty1,
+		Empty1,
+		DOUT1,
+
+		DIN2,
+		PUSH2,
+		POP2,
+		CLK2,
+		Async_Flush2,
+		Overrun_Error2,
+		Full_Watermark2,
+		Almost_Full2,
+		Full2,
+		Underrun_Error2,
+		Empty_Watermark2,
+		Almost_Empty2,
+		Empty2,
+		DOUT2
+);
+
+	parameter WR1_DATA_WIDTH = 18;
+	parameter RD1_DATA_WIDTH = 18;
+
+	parameter WR2_DATA_WIDTH = 18;
+	parameter RD2_DATA_WIDTH = 18;
+
+	parameter UPAE_DBITS1 = 12'd10;
+	parameter UPAF_DBITS1 = 12'd10;
+
+	parameter UPAE_DBITS2 = 11'd10;
+	parameter UPAF_DBITS2 = 11'd10;
+
+	input wire CLK1;
+	input wire PUSH1, POP1;
+	input wire [WR1_DATA_WIDTH-1:0] DIN1;
+	input wire Async_Flush1;
+	output wire [RD1_DATA_WIDTH-1:0] DOUT1;
+	output wire Almost_Full1, Almost_Empty1;
+	output wire Full1, Empty1;
+	output wire Full_Watermark1, Empty_Watermark1;
+	output wire Overrun_Error1, Underrun_Error1;
+
+	input wire CLK2;
+	input wire PUSH2, POP2;
+	input wire [WR2_DATA_WIDTH-1:0] DIN2;
+	input wire Async_Flush2;
+	output wire [RD2_DATA_WIDTH-1:0] DOUT2;
+	output wire Almost_Full2, Almost_Empty2;
+	output wire Full2, Empty2;
+	output wire Full_Watermark2, Empty_Watermark2;
+	output wire Overrun_Error2, Underrun_Error2;
+
+	// Fixed mode settings
+	localparam [ 0:0] SYNC_FIFO1_i  = 1'd1;
+	localparam [ 0:0] FMODE1_i      = 1'd1;
+	localparam [ 0:0] POWERDN1_i    = 1'd0;
+	localparam [ 0:0] SLEEP1_i      = 1'd0;
+	localparam [ 0:0] PROTECT1_i    = 1'd0;
+	localparam [11:0] UPAE1_i       = UPAE_DBITS1;
+	localparam [11:0] UPAF1_i       = UPAF_DBITS1;
+
+	localparam [ 0:0] SYNC_FIFO2_i  = 1'd1;
+	localparam [ 0:0] FMODE2_i      = 1'd1;
+	localparam [ 0:0] POWERDN2_i    = 1'd0;
+	localparam [ 0:0] SLEEP2_i      = 1'd0;
+	localparam [ 0:0] PROTECT2_i    = 1'd0;
+	localparam [10:0] UPAE2_i       = UPAE_DBITS2;
+	localparam [10:0] UPAF2_i       = UPAF_DBITS2;
+
+	// Width mode function
+	function [2:0] mode;
+	input integer width;
+	case (width)
+	1: mode = 3'b101;
+	2: mode = 3'b110;
+	4: mode = 3'b100;
+	8,9: mode = 3'b001;
+	16, 18: mode = 3'b010;
+	32, 36: mode = 3'b011;
+	default: mode = 3'b000;
+	endcase
+	endfunction
+
+	wire [17:0] in_reg1;
+	wire [17:0] out_reg1;
+	wire [17:0] fifo1_flags;
+
+	wire [17:0] in_reg2;
+	wire [17:0] out_reg2;
+	wire [17:0] fifo2_flags;
+
+	wire Push_Clk1, Pop_Clk1;
+	wire Push_Clk2, Pop_Clk2;
+	assign Push_Clk1 = CLK1;
+	assign Pop_Clk1 = CLK1;
+	assign Push_Clk2 = CLK2;
+	assign Pop_Clk2 = CLK2;
+
+	assign Overrun_Error1 = fifo1_flags[0];
+	assign Full_Watermark1 = fifo1_flags[1];
+	assign Almost_Full1 = fifo1_flags[2];
+	assign Full1 = fifo1_flags[3];
+	assign Underrun_Error1 = fifo1_flags[4];
+	assign Empty_Watermark1 = fifo1_flags[5];
+	assign Almost_Empty1 = fifo1_flags[6];
+	assign Empty1 = fifo1_flags[7];
+
+	assign Overrun_Error2 = fifo2_flags[0];
+	assign Full_Watermark2 = fifo2_flags[1];
+	assign Almost_Full2 = fifo2_flags[2];
+	assign Full2 = fifo2_flags[3];
+	assign Underrun_Error2 = fifo2_flags[4];
+	assign Empty_Watermark2 = fifo2_flags[5];
+	assign Almost_Empty2 = fifo2_flags[6];
+	assign Empty2 = fifo2_flags[7];
+
+	localparam [ 2:0] RMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_A2_i    = mode(WR2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A2_i    = mode(WR2_DATA_WIDTH);
+
+	localparam [ 2:0] RMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_B2_i    = mode(RD2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B2_i    = mode(RD2_DATA_WIDTH);
+
+	generate
+		if (WR1_DATA_WIDTH == 18) begin
+			assign in_reg1[17:0] = DIN1[17:0];
+		end else if (WR1_DATA_WIDTH == 9) begin
+			assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]};
+		end else begin
+			assign in_reg1[17:WR1_DATA_WIDTH]  = 0;
+			assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD1_DATA_WIDTH == 9) begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]};
+		end else begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (WR2_DATA_WIDTH == 18) begin
+			assign in_reg2[17:0] = DIN2[17:0];
+		end else if (WR2_DATA_WIDTH == 9) begin
+			assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]};
+		end else begin
+			assign in_reg2[17:WR2_DATA_WIDTH]  = 0;
+			assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD2_DATA_WIDTH == 9) begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]};
+		end else begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+	};
+
+	(* is_fifo = 1 *)
+	(* sync_fifo = 1 *)
+	(* is_split = 1 *)
+	(* is_inferred = 0 *)
+	(* port_a1_dwidth = WR1_DATA_WIDTH *)
+	(* port_a2_dwidth = WR2_DATA_WIDTH *)
+	(* port_b1_dwidth = RD1_DATA_WIDTH *)
+	(* port_b2_dwidth = RD2_DATA_WIDTH *)
+ 	TDP36K _TECHMAP_REPLACE_ (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg1[17:0]),
+		.WDATA_A2_i(in_reg2[17:0]),
+		.RDATA_A1_o(fifo1_flags),
+		.RDATA_A2_o(fifo2_flags),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk1),
+		.CLK_A2_i(Push_Clk2),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b1),
+		.WEN_A1_i(PUSH1),
+		.WEN_A2_i(PUSH2),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg1[17:0]),
+		.RDATA_B2_o(out_reg2[17:0]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk1),
+		.CLK_B2_i(Pop_Clk2),
+		.REN_B1_i(POP1),
+		.REN_B2_i(POP2),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush1),
+		.FLUSH2_i(Async_Flush2)
+	);
+
+endmodule
+
+
+module BRAM2x18_AFIFO (
+		DIN1,
+		PUSH1,
+		POP1,
+		Push_Clk1,
+	Pop_Clk1,
+		Async_Flush1,
+		Overrun_Error1,
+		Full_Watermark1,
+		Almost_Full1,
+		Full1,
+		Underrun_Error1,
+		Empty_Watermark1,
+		Almost_Empty1,
+		Empty1,
+		DOUT1,
+
+		DIN2,
+		PUSH2,
+		POP2,
+		Push_Clk2,
+	Pop_Clk2,
+		Async_Flush2,
+		Overrun_Error2,
+		Full_Watermark2,
+		Almost_Full2,
+		Full2,
+		Underrun_Error2,
+		Empty_Watermark2,
+		Almost_Empty2,
+		Empty2,
+		DOUT2
+);
+
+	parameter WR1_DATA_WIDTH = 18;
+	parameter RD1_DATA_WIDTH = 18;
+
+	parameter WR2_DATA_WIDTH = 18;
+	parameter RD2_DATA_WIDTH = 18;
+
+	parameter UPAE_DBITS1 = 12'd10;
+	parameter UPAF_DBITS1 = 12'd10;
+
+	parameter UPAE_DBITS2 = 11'd10;
+	parameter UPAF_DBITS2 = 11'd10;
+
+	input wire Push_Clk1, Pop_Clk1;
+	input wire PUSH1, POP1;
+	input wire [WR1_DATA_WIDTH-1:0] DIN1;
+	input wire Async_Flush1;
+	output wire [RD1_DATA_WIDTH-1:0] DOUT1;
+	output wire Almost_Full1, Almost_Empty1;
+	output wire Full1, Empty1;
+	output wire Full_Watermark1, Empty_Watermark1;
+	output wire Overrun_Error1, Underrun_Error1;
+
+	input wire Push_Clk2, Pop_Clk2;
+	input wire PUSH2, POP2;
+	input wire [WR2_DATA_WIDTH-1:0] DIN2;
+	input wire Async_Flush2;
+	output wire [RD2_DATA_WIDTH-1:0] DOUT2;
+	output wire Almost_Full2, Almost_Empty2;
+	output wire Full2, Empty2;
+	output wire Full_Watermark2, Empty_Watermark2;
+	output wire Overrun_Error2, Underrun_Error2;
+
+	// Fixed mode settings
+	localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+	localparam [ 0:0] FMODE1_i      = 1'd1;
+	localparam [ 0:0] POWERDN1_i    = 1'd0;
+	localparam [ 0:0] SLEEP1_i      = 1'd0;
+	localparam [ 0:0] PROTECT1_i    = 1'd0;
+	localparam [11:0] UPAE1_i       = UPAE_DBITS1;
+	localparam [11:0] UPAF1_i       = UPAF_DBITS1;
+
+	localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+	localparam [ 0:0] FMODE2_i      = 1'd1;
+	localparam [ 0:0] POWERDN2_i    = 1'd0;
+	localparam [ 0:0] SLEEP2_i      = 1'd0;
+	localparam [ 0:0] PROTECT2_i    = 1'd0;
+	localparam [10:0] UPAE2_i       = UPAE_DBITS2;
+	localparam [10:0] UPAF2_i       = UPAF_DBITS2;
+
+	// Width mode function
+	function [2:0] mode;
+	input integer width;
+	case (width)
+	1: mode = 3'b101;
+	2: mode = 3'b110;
+	4: mode = 3'b100;
+	8,9: mode = 3'b001;
+	16, 18: mode = 3'b010;
+	32, 36: mode = 3'b011;
+	default: mode = 3'b000;
+	endcase
+	endfunction
+
+	wire [17:0] in_reg1;
+	wire [17:0] out_reg1;
+	wire [17:0] fifo1_flags;
+
+	wire [17:0] in_reg2;
+	wire [17:0] out_reg2;
+	wire [17:0] fifo2_flags;
+
+	assign Overrun_Error1 = fifo1_flags[0];
+	assign Full_Watermark1 = fifo1_flags[1];
+	assign Almost_Full1 = fifo1_flags[2];
+	assign Full1 = fifo1_flags[3];
+	assign Underrun_Error1 = fifo1_flags[4];
+	assign Empty_Watermark1 = fifo1_flags[5];
+	assign Almost_Empty1 = fifo1_flags[6];
+	assign Empty1 = fifo1_flags[7];
+
+	assign Overrun_Error2 = fifo2_flags[0];
+	assign Full_Watermark2 = fifo2_flags[1];
+	assign Almost_Full2 = fifo2_flags[2];
+	assign Full2 = fifo2_flags[3];
+	assign Underrun_Error2 = fifo2_flags[4];
+	assign Empty_Watermark2 = fifo2_flags[5];
+	assign Almost_Empty2 = fifo2_flags[6];
+	assign Empty2 = fifo2_flags[7];
+
+	localparam [ 2:0] RMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_A2_i    = mode(WR2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A2_i    = mode(WR2_DATA_WIDTH);
+
+	localparam [ 2:0] RMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_B2_i    = mode(RD2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B2_i    = mode(RD2_DATA_WIDTH);
+
+	generate
+		if (WR1_DATA_WIDTH == 18) begin
+			assign in_reg1[17:0] = DIN1[17:0];
+		end else if (WR1_DATA_WIDTH == 9) begin
+			assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]};
+		end else begin
+			assign in_reg1[17:WR1_DATA_WIDTH]  = 0;
+			assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD1_DATA_WIDTH == 9) begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]};
+		end else begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (WR2_DATA_WIDTH == 18) begin
+			assign in_reg2[17:0] = DIN2[17:0];
+		end else if (WR2_DATA_WIDTH == 9) begin
+			assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]};
+		end else begin
+			assign in_reg2[17:WR2_DATA_WIDTH]  = 0;
+			assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD2_DATA_WIDTH == 9) begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]};
+		end else begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+	};
+
+	(* is_fifo = 1 *)
+	(* sync_fifo = 0 *)
+	(* is_split = 0 *)
+	(* is_inferred = 0 *)
+	(* port_a_dwidth = WR1_DATA_WIDTH *)
+	(* port_b_dwidth = RD1_DATA_WIDTH *)
+ 	TDP36K _TECHMAP_REPLACE_ (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg1[17:0]),
+		.WDATA_A2_i(in_reg2[17:0]),
+		.RDATA_A1_o(fifo1_flags),
+		.RDATA_A2_o(fifo2_flags),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk1),
+		.CLK_A2_i(Push_Clk2),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b1),
+		.WEN_A1_i(PUSH1),
+		.WEN_A2_i(PUSH2),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg1[17:0]),
+		.RDATA_B2_o(out_reg2[17:0]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk1),
+		.CLK_B2_i(Pop_Clk2),
+		.REN_B1_i(POP1),
+		.REN_B2_i(POP2),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush1),
+		.FLUSH2_i(Async_Flush2)
+	);
+
+endmodule
+
+module AFIFO_18K_BLK (
+		DIN,
+		PUSH,
+		POP,
+		Push_Clk,
+		Pop_Clk,
+		Async_Flush,
+		Overrun_Error,
+		Full_Watermark,
+		Almost_Full,
+		Full,
+		Underrun_Error,
+		Empty_Watermark,
+		Almost_Empty,
+		Empty,
+		DOUT
+);
+
+	parameter WR_DATA_WIDTH = 18;
+	parameter RD_DATA_WIDTH = 18;
+	parameter UPAE_DBITS = 11'd10;
+	parameter UPAF_DBITS = 11'd10;
+
+	input wire Push_Clk, Pop_Clk;
+	input wire PUSH, POP;
+	input wire [WR_DATA_WIDTH-1:0] DIN;
+	input wire Async_Flush;
+	output wire [RD_DATA_WIDTH-1:0] DOUT;
+	output wire Almost_Full, Almost_Empty;
+	output wire Full, Empty;
+	output wire Full_Watermark, Empty_Watermark;
+	output wire Overrun_Error, Underrun_Error;
+
+ 	BRAM2x18_AFIFO  #(
+			.WR1_DATA_WIDTH(WR_DATA_WIDTH),
+			.RD1_DATA_WIDTH(RD_DATA_WIDTH),
+			.UPAE_DBITS1(UPAE_DBITS),
+			.UPAF_DBITS1(UPAF_DBITS),
+			.WR2_DATA_WIDTH(),
+			.RD2_DATA_WIDTH(),
+			.UPAE_DBITS2(),
+			.UPAF_DBITS2()
+			 ) U1
+			(
+			.DIN1(DIN),
+			.PUSH1(PUSH),
+			.POP1(POP),
+			.Push_Clk1(Push_Clk),
+			.Pop_Clk1(Pop_Clk),
+			.Async_Flush1(Async_Flush),
+			.Overrun_Error1(Overrun_Error),
+			.Full_Watermark1(Full_Watermark),
+			.Almost_Full1(Almost_Full),
+			.Full1(Full),
+			.Underrun_Error1(Underrun_Error),
+			.Empty_Watermark1(Empty_Watermark),
+			.Almost_Empty1(Almost_Empty),
+			.Empty1(Empty),
+			.DOUT1(DOUT),
+
+			.DIN2(18'h0),
+			.PUSH2(1'b0),
+			.POP2(1'b0),
+			.Push_Clk2(1'b0),
+			.Pop_Clk2(1'b0),
+			.Async_Flush2(1'b0),
+			.Overrun_Error2(),
+			.Full_Watermark2(),
+			.Almost_Full2(),
+			.Full2(),
+			.Underrun_Error2(),
+			.Empty_Watermark2(),
+			.Almost_Empty2(),
+			.Empty2(),
+			.DOUT2()
+	);
+
+endmodule
+
+module AFIFO_18K_X2_BLK (
+		DIN1,
+		PUSH1,
+		POP1,
+		Push_Clk1,
+	Pop_Clk1,
+		Async_Flush1,
+		Overrun_Error1,
+		Full_Watermark1,
+		Almost_Full1,
+		Full1,
+		Underrun_Error1,
+		Empty_Watermark1,
+		Almost_Empty1,
+		Empty1,
+		DOUT1,
+
+		DIN2,
+		PUSH2,
+		POP2,
+		Push_Clk2,
+	Pop_Clk2,
+		Async_Flush2,
+		Overrun_Error2,
+		Full_Watermark2,
+		Almost_Full2,
+		Full2,
+		Underrun_Error2,
+		Empty_Watermark2,
+		Almost_Empty2,
+		Empty2,
+		DOUT2
+);
+
+	parameter WR1_DATA_WIDTH = 18;
+	parameter RD1_DATA_WIDTH = 18;
+
+	parameter WR2_DATA_WIDTH = 18;
+	parameter RD2_DATA_WIDTH = 18;
+
+	parameter UPAE_DBITS1 = 12'd10;
+	parameter UPAF_DBITS1 = 12'd10;
+
+	parameter UPAE_DBITS2 = 11'd10;
+	parameter UPAF_DBITS2 = 11'd10;
+
+	input wire Push_Clk1, Pop_Clk1;
+	input wire PUSH1, POP1;
+	input wire [WR1_DATA_WIDTH-1:0] DIN1;
+	input wire Async_Flush1;
+	output wire [RD1_DATA_WIDTH-1:0] DOUT1;
+	output wire Almost_Full1, Almost_Empty1;
+	output wire Full1, Empty1;
+	output wire Full_Watermark1, Empty_Watermark1;
+	output wire Overrun_Error1, Underrun_Error1;
+
+	input wire Push_Clk2, Pop_Clk2;
+	input wire PUSH2, POP2;
+	input wire [WR2_DATA_WIDTH-1:0] DIN2;
+	input wire Async_Flush2;
+	output wire [RD2_DATA_WIDTH-1:0] DOUT2;
+	output wire Almost_Full2, Almost_Empty2;
+	output wire Full2, Empty2;
+	output wire Full_Watermark2, Empty_Watermark2;
+	output wire Overrun_Error2, Underrun_Error2;
+
+	// Fixed mode settings
+	localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+	localparam [ 0:0] FMODE1_i      = 1'd1;
+	localparam [ 0:0] POWERDN1_i    = 1'd0;
+	localparam [ 0:0] SLEEP1_i      = 1'd0;
+	localparam [ 0:0] PROTECT1_i    = 1'd0;
+	localparam [11:0] UPAE1_i       = UPAE_DBITS1;
+	localparam [11:0] UPAF1_i       = UPAF_DBITS1;
+
+	localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+	localparam [ 0:0] FMODE2_i      = 1'd1;
+	localparam [ 0:0] POWERDN2_i    = 1'd0;
+	localparam [ 0:0] SLEEP2_i      = 1'd0;
+	localparam [ 0:0] PROTECT2_i    = 1'd0;
+	localparam [10:0] UPAE2_i       = UPAE_DBITS2;
+	localparam [10:0] UPAF2_i       = UPAF_DBITS2;
+
+	// Width mode function
+	function [2:0] mode;
+	input integer width;
+	case (width)
+	1: mode = 3'b101;
+	2: mode = 3'b110;
+	4: mode = 3'b100;
+	8,9: mode = 3'b001;
+	16, 18: mode = 3'b010;
+	32, 36: mode = 3'b011;
+	default: mode = 3'b000;
+	endcase
+	endfunction
+
+	wire [17:0] in_reg1;
+	wire [17:0] out_reg1;
+	wire [17:0] fifo1_flags;
+
+	wire [17:0] in_reg2;
+	wire [17:0] out_reg2;
+	wire [17:0] fifo2_flags;
+
+	assign Overrun_Error1 = fifo1_flags[0];
+	assign Full_Watermark1 = fifo1_flags[1];
+	assign Almost_Full1 = fifo1_flags[2];
+	assign Full1 = fifo1_flags[3];
+	assign Underrun_Error1 = fifo1_flags[4];
+	assign Empty_Watermark1 = fifo1_flags[5];
+	assign Almost_Empty1 = fifo1_flags[6];
+	assign Empty1 = fifo1_flags[7];
+
+	assign Overrun_Error2 = fifo2_flags[0];
+	assign Full_Watermark2 = fifo2_flags[1];
+	assign Almost_Full2 = fifo2_flags[2];
+	assign Full2 = fifo2_flags[3];
+	assign Underrun_Error2 = fifo2_flags[4];
+	assign Empty_Watermark2 = fifo2_flags[5];
+	assign Almost_Empty2 = fifo2_flags[6];
+	assign Empty2 = fifo2_flags[7];
+
+	localparam [ 2:0] RMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A1_i    = mode(WR1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_A2_i    = mode(WR2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A2_i    = mode(WR2_DATA_WIDTH);
+
+	localparam [ 2:0] RMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B1_i    = mode(RD1_DATA_WIDTH);
+	localparam [ 2:0] RMODE_B2_i    = mode(RD2_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B2_i    = mode(RD2_DATA_WIDTH);
+
+	generate
+		if (WR1_DATA_WIDTH == 18) begin
+			assign in_reg1[17:0] = DIN1[17:0];
+		end else if (WR1_DATA_WIDTH == 9) begin
+			assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]};
+		end else begin
+			assign in_reg1[17:WR1_DATA_WIDTH]  = 0;
+			assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD1_DATA_WIDTH == 9) begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]};
+		end else begin
+			assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (WR2_DATA_WIDTH == 18) begin
+			assign in_reg2[17:0] = DIN2[17:0];
+		end else if (WR2_DATA_WIDTH == 9) begin
+			assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]};
+		end else begin
+			assign in_reg2[17:WR2_DATA_WIDTH]  = 0;
+			assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD2_DATA_WIDTH == 9) begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]};
+		end else begin
+			assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+	};
+
+	(* is_fifo = 1 *)
+	(* sync_fifo = 0 *)
+	(* is_split = 1 *)
+	(* is_inferred = 0 *)
+	(* port_a1_dwidth = WR1_DATA_WIDTH *)
+	(* port_a2_dwidth = WR2_DATA_WIDTH *)
+	(* port_b1_dwidth = RD1_DATA_WIDTH *)
+	(* port_b2_dwidth = RD2_DATA_WIDTH *)
+ 	TDP36K _TECHMAP_REPLACE_ (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg1[17:0]),
+		.WDATA_A2_i(in_reg2[17:0]),
+		.RDATA_A1_o(fifo1_flags),
+		.RDATA_A2_o(fifo2_flags),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk1),
+		.CLK_A2_i(Push_Clk2),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b1),
+		.WEN_A1_i(PUSH1),
+		.WEN_A2_i(PUSH2),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg1[17:0]),
+		.RDATA_B2_o(out_reg2[17:0]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk1),
+		.CLK_B2_i(Pop_Clk2),
+		.REN_B1_i(POP1),
+		.REN_B2_i(POP2),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush1),
+		.FLUSH2_i(Async_Flush2)
+	);
+
+endmodule
+
+module SFIFO_36K_BLK (
+		DIN,
+		PUSH,
+		POP,
+		CLK,
+		Async_Flush,
+		Overrun_Error,
+		Full_Watermark,
+		Almost_Full,
+		Full,
+		Underrun_Error,
+		Empty_Watermark,
+		Almost_Empty,
+		Empty,
+		DOUT
+);
+
+	parameter WR_DATA_WIDTH = 36;
+	parameter RD_DATA_WIDTH = 36;
+	parameter UPAE_DBITS = 12'd10;
+	parameter UPAF_DBITS = 12'd10;
+
+	input wire CLK;
+	input wire PUSH, POP;
+	input wire [WR_DATA_WIDTH-1:0] DIN;
+	input wire Async_Flush;
+	output wire [RD_DATA_WIDTH-1:0] DOUT;
+	output wire Almost_Full, Almost_Empty;
+	output wire Full, Empty;
+	output wire Full_Watermark, Empty_Watermark;
+	output wire Overrun_Error, Underrun_Error;
+
+	// Fixed mode settings
+	localparam [ 0:0] SYNC_FIFO1_i  = 1'd1;
+	localparam [ 0:0] FMODE1_i      = 1'd1;
+	localparam [ 0:0] POWERDN1_i    = 1'd0;
+	localparam [ 0:0] SLEEP1_i      = 1'd0;
+	localparam [ 0:0] PROTECT1_i    = 1'd0;
+	localparam [11:0] UPAE1_i       = UPAE_DBITS;
+	localparam [11:0] UPAF1_i       = UPAF_DBITS;
+
+	localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+	localparam [ 0:0] FMODE2_i      = 1'd0;
+	localparam [ 0:0] POWERDN2_i    = 1'd0;
+	localparam [ 0:0] SLEEP2_i      = 1'd0;
+	localparam [ 0:0] PROTECT2_i    = 1'd0;
+	localparam [10:0] UPAE2_i       = 11'd10;
+	localparam [10:0] UPAF2_i       = 11'd10;
+
+	// Width mode function
+	function [2:0] mode;
+	input integer width;
+	case (width)
+	1: mode = 3'b101;
+	2: mode = 3'b110;
+	4: mode = 3'b100;
+	8,9: mode = 3'b001;
+	16, 18: mode = 3'b010;
+	32, 36: mode = 3'b011;
+	default: mode = 3'b000;
+	endcase
+	endfunction
+
+	wire [35:0] in_reg;
+	wire [35:0] out_reg;
+	wire [17:0] fifo_flags;
+
+	wire [35:0] RD_DATA_INT;
+
+	wire Push_Clk, Pop_Clk;
+
+	assign Push_Clk = CLK;
+	assign Pop_Clk = CLK;
+
+	assign Overrun_Error = fifo_flags[0];
+	assign Full_Watermark = fifo_flags[1];
+	assign Almost_Full = fifo_flags[2];
+	assign Full = fifo_flags[3];
+	assign Underrun_Error = fifo_flags[4];
+	assign Empty_Watermark = fifo_flags[5];
+	assign Almost_Empty = fifo_flags[6];
+	assign Empty = fifo_flags[7];
+
+	localparam [ 2:0] RMODE_A1_i    = mode(WR_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A1_i    = mode(WR_DATA_WIDTH);
+	localparam [ 2:0] RMODE_A2_i    = mode(WR_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A2_i    = mode(WR_DATA_WIDTH);
+
+	localparam [ 2:0] RMODE_B1_i    = mode(RD_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B1_i    = mode(RD_DATA_WIDTH);
+	localparam [ 2:0] RMODE_B2_i    = mode(RD_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B2_i    = mode(RD_DATA_WIDTH);
+
+	generate
+		if (WR_DATA_WIDTH == 36) begin
+			assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+		end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin
+			assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16];
+			assign in_reg[17:0] = {2'b00,DIN[15:0]};
+		end else if (WR_DATA_WIDTH == 9) begin
+			assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]};
+		end else begin
+			assign in_reg[35:WR_DATA_WIDTH]  = 0;
+			assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD_DATA_WIDTH == 36) begin
+			assign RD_DATA_INT = out_reg;
+		end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin
+			assign RD_DATA_INT  = {2'b00,out_reg[35:18],out_reg[15:0]};
+		end else if (RD_DATA_WIDTH == 9) begin
+			assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]};
+		end else begin
+			assign RD_DATA_INT = {18'h0, out_reg[17:0]};
+		end
+	endgenerate
+
+	assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0];
+
+	defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+	};
+
+	(* is_fifo = 1 *)
+	(* sync_fifo = 1 *)
+	(* is_inferred = 0 *)
+	(* is_split = 0 *)
+	(* port_a_dwidth = WR_DATA_WIDTH *)
+	(* port_b_dwidth = RD_DATA_WIDTH *)
+	 TDP36K _TECHMAP_REPLACE_ (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg[17:0]),
+		.WDATA_A2_i(in_reg[35:18]),
+		.RDATA_A1_o(fifo_flags),
+		.RDATA_A2_o(),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk),
+		.CLK_A2_i(1'b0),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b0),
+		.WEN_A1_i(PUSH),
+		.WEN_A2_i(1'b0),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg[17:0]),
+		.RDATA_B2_o(out_reg[35:18]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk),
+		.CLK_B2_i(1'b0),
+		.REN_B1_i(POP),
+		.REN_B2_i(1'b0),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush),
+		.FLUSH2_i(1'b0)
+	);
+
+endmodule
+
+
+module AFIFO_36K_BLK (
+		DIN,
+		PUSH,
+		POP,
+		Push_Clk,
+		Pop_Clk,
+		Async_Flush,
+		Overrun_Error,
+		Full_Watermark,
+		Almost_Full,
+		Full,
+		Underrun_Error,
+		Empty_Watermark,
+		Almost_Empty,
+		Empty,
+		DOUT
+);
+
+	parameter WR_DATA_WIDTH = 36;
+	parameter RD_DATA_WIDTH = 36;
+	parameter UPAE_DBITS = 12'd10;
+	parameter UPAF_DBITS = 12'd10;
+
+	input wire Push_Clk, Pop_Clk;
+	input wire PUSH, POP;
+	input wire [WR_DATA_WIDTH-1:0] DIN;
+	input wire Async_Flush;
+	output wire [RD_DATA_WIDTH-1:0] DOUT;
+	output wire Almost_Full, Almost_Empty;
+	output wire Full, Empty;
+	output wire Full_Watermark, Empty_Watermark;
+	output wire Overrun_Error, Underrun_Error;
+
+	// Fixed mode settings
+	localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+	localparam [ 0:0] FMODE1_i      = 1'd1;
+	localparam [ 0:0] POWERDN1_i    = 1'd0;
+	localparam [ 0:0] SLEEP1_i      = 1'd0;
+	localparam [ 0:0] PROTECT1_i    = 1'd0;
+	localparam [11:0] UPAE1_i       = UPAE_DBITS;
+	localparam [11:0] UPAF1_i       = UPAF_DBITS;
+
+	localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+	localparam [ 0:0] FMODE2_i      = 1'd0;
+	localparam [ 0:0] POWERDN2_i    = 1'd0;
+	localparam [ 0:0] SLEEP2_i      = 1'd0;
+	localparam [ 0:0] PROTECT2_i    = 1'd0;
+	localparam [10:0] UPAE2_i       = 11'd10;
+	localparam [10:0] UPAF2_i       = 11'd10;
+
+	// Width mode function
+	function [2:0] mode;
+	input integer width;
+	case (width)
+	1: mode = 3'b101;
+	2: mode = 3'b110;
+	4: mode = 3'b100;
+	8,9: mode = 3'b001;
+	16, 18: mode = 3'b010;
+	32, 36: mode = 3'b011;
+	default: mode = 3'b000;
+	endcase
+	endfunction
+
+	wire [35:0] in_reg;
+	wire [35:0] out_reg;
+	wire [17:0] fifo_flags;
+
+	wire [35:0] RD_DATA_INT;
+	wire [35:WR_DATA_WIDTH] WR_DATA_CMPL;
+
+	assign Overrun_Error = fifo_flags[0];
+	assign Full_Watermark = fifo_flags[1];
+	assign Almost_Full = fifo_flags[2];
+	assign Full = fifo_flags[3];
+	assign Underrun_Error = fifo_flags[4];
+	assign Empty_Watermark = fifo_flags[5];
+	assign Almost_Empty = fifo_flags[6];
+	assign Empty = fifo_flags[7];
+
+	localparam [ 2:0] RMODE_A1_i    = mode(WR_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A1_i    = mode(WR_DATA_WIDTH);
+	localparam [ 2:0] RMODE_A2_i    = mode(WR_DATA_WIDTH);
+	localparam [ 2:0] WMODE_A2_i    = mode(WR_DATA_WIDTH);
+
+	localparam [ 2:0] RMODE_B1_i    = mode(RD_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B1_i    = mode(RD_DATA_WIDTH);
+	localparam [ 2:0] RMODE_B2_i    = mode(RD_DATA_WIDTH);
+	localparam [ 2:0] WMODE_B2_i    = mode(RD_DATA_WIDTH);
+
+	generate
+		if (WR_DATA_WIDTH == 36) begin
+			assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+		end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin
+			assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16];
+			assign in_reg[17:0] = {2'b00,DIN[15:0]};
+		end else if (WR_DATA_WIDTH == 9) begin
+			assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]};
+		end else begin
+			assign in_reg[35:WR_DATA_WIDTH]  = 0;
+			assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0];
+		end
+	endgenerate
+
+	generate
+		if (RD_DATA_WIDTH == 36) begin
+			assign RD_DATA_INT = out_reg;
+		end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin
+			assign RD_DATA_INT  = {2'b00,out_reg[35:18],out_reg[15:0]};
+		end else if (RD_DATA_WIDTH == 9) begin
+			assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]};
+		end else begin
+			assign RD_DATA_INT = {18'h0, out_reg[17:0]};
+		end
+	endgenerate
+
+	assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0];
+
+	defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+	};
+
+	(* is_fifo = 1 *)
+	(* sync_fifo = 0 *)
+	(* is_inferred = 0 *)
+	(* is_split = 0 *)
+	(* port_a_dwidth = WR_DATA_WIDTH *)
+	(* port_b_dwidth = RD_DATA_WIDTH *)
+ 	TDP36K _TECHMAP_REPLACE_ (
+		.RESET_ni(1'b1),
+		.WDATA_A1_i(in_reg[17:0]),
+		.WDATA_A2_i(in_reg[35:18]),
+		.RDATA_A1_o(fifo_flags),
+		.RDATA_A2_o(),
+		.ADDR_A1_i(14'h0),
+		.ADDR_A2_i(14'h0),
+		.CLK_A1_i(Push_Clk),
+		.CLK_A2_i(1'b0),
+		.REN_A1_i(1'b1),
+		.REN_A2_i(1'b0),
+		.WEN_A1_i(PUSH),
+		.WEN_A2_i(1'b0),
+		.BE_A1_i(2'b11),
+		.BE_A2_i(2'b11),
+
+		.WDATA_B1_i(18'h0),
+		.WDATA_B2_i(18'h0),
+		.RDATA_B1_o(out_reg[17:0]),
+		.RDATA_B2_o(out_reg[35:18]),
+		.ADDR_B1_i(14'h0),
+		.ADDR_B2_i(14'h0),
+		.CLK_B1_i(Pop_Clk),
+		.CLK_B2_i(1'b0),
+		.REN_B1_i(POP),
+		.REN_B2_i(1'b0),
+		.WEN_B1_i(1'b0),
+		.WEN_B2_i(1'b0),
+		.BE_B1_i(2'b11),
+		.BE_B2_i(2'b11),
+
+		.FLUSH1_i(Async_Flush),
+		.FLUSH2_i(1'b0)
+	);
+
+endmodule
+
+//===============================================================================
+module TDP36K_FIFO_ASYNC_A_X9_B_X9_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A_X9_B_X18_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A_X9_B_X36_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A_X18_B_X9_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A_X18_B_X18_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A_X18_B_X36_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A_X36_B_X9_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A_X36_B_X18_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A_X36_B_X36_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A_X9_B_X9_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A_X9_B_X18_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A_X9_B_X36_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A_X18_B_X9_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A_X18_B_X18_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A_X18_B_X36_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A_X36_B_X9_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A_X36_B_X18_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A_X36_B_X36_nonsplit (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X18_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X9_split (
+		RESET_ni,
+		WEN_A1_i,   WEN_B1_i,
+		REN_A1_i,   REN_B1_i,
+		CLK_A1_i,   CLK_B1_i,
+		BE_A1_i,    BE_B1_i,
+		ADDR_A1_i,  ADDR_B1_i,
+		WDATA_A1_i, WDATA_B1_i,
+		RDATA_A1_o, RDATA_B1_o,
+		FLUSH1_i,
+		WEN_A2_i,   WEN_B2_i,
+		REN_A2_i,   REN_B2_i,
+		CLK_A2_i,   CLK_B2_i,
+		BE_A2_i,    BE_B2_i,
+		ADDR_A2_i,  ADDR_B2_i,
+		WDATA_A2_i, WDATA_B2_i,
+		RDATA_A2_o, RDATA_B2_o,
+		FLUSH2_i
+);
+		parameter [80:0] MODE_BITS = 81'd0;
+
+		input wire  RESET_ni;
+		input wire  WEN_A1_i, WEN_B1_i;
+		input wire  REN_A1_i, REN_B1_i;
+		input wire  WEN_A2_i, WEN_B2_i;
+		input wire  REN_A2_i, REN_B2_i;
+
+		(* clkbuf_sink *)
+		input wire  CLK_A1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B1_i;
+		(* clkbuf_sink *)
+		input wire  CLK_A2_i;
+		(* clkbuf_sink *)
+		input wire  CLK_B2_i;
+
+		input wire  [ 1:0] BE_A1_i,    BE_B1_i;
+		input wire  [14:0] ADDR_A1_i,  ADDR_B1_i;
+		input wire  [17:0] WDATA_A1_i, WDATA_B1_i;
+		output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+		input wire  FLUSH1_i;
+
+		input wire  [ 1:0] BE_A2_i,    BE_B2_i;
+		input wire  [13:0] ADDR_A2_i,  ADDR_B2_i;
+		input wire  [17:0] WDATA_A2_i, WDATA_B2_i;
+		output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+		input wire  FLUSH2_i;
+
+		TDP36K #(.MODE_BITS(MODE_BITS)) bram (
+				.RESET_ni   (RESET_ni),
+				.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+				.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+				.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+				.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+				.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+				.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+				.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+				.FLUSH1_i   (FLUSH1_i),
+				.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+				.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+				.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+				.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+				.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+				.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+				.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+				.FLUSH2_i   (FLUSH2_i)
+		);
+
+`ifdef SDF_SIM
+	specify
+		(FLUSH1_i => RDATA_A1_o[0]) = 0;
+		(FLUSH1_i => RDATA_A1_o[1]) = 0;
+		(FLUSH1_i => RDATA_A1_o[2]) = 0;
+		(FLUSH1_i => RDATA_A1_o[3]) = 0;
+		(FLUSH1_i => RDATA_A1_o[4]) = 0;
+		(FLUSH1_i => RDATA_A1_o[5]) = 0;
+		(FLUSH1_i => RDATA_A1_o[6]) = 0;
+		(FLUSH1_i => RDATA_A1_o[7]) = 0;
+		(FLUSH2_i => RDATA_A2_o[0]) = 0;
+		(FLUSH2_i => RDATA_A2_o[1]) = 0;
+		(FLUSH2_i => RDATA_A2_o[2]) = 0;
+		(FLUSH2_i => RDATA_A2_o[3]) = 0;
+		(FLUSH2_i => RDATA_A2_o[4]) = 0;
+		(FLUSH2_i => RDATA_A2_o[5]) = 0;
+		(FLUSH2_i => RDATA_A2_o[6]) = 0;
+		(FLUSH2_i => RDATA_A2_o[7]) = 0;
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+`endif
+
+endmodule
\ No newline at end of file
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/cells_sim.v b/yosys/techlibs/quicklogic/qlf_k6n10f/cells_sim.v
new file mode 100644
index 00000000000..ddfd51ee7ce
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/cells_sim.v
@@ -0,0 +1,375 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ps/1ps
+
+`default_nettype none
+(* abc9_lut=1 *)
+module LUT1(output wire O, input wire I0);
+	parameter [1:0] INIT = 0;
+	assign O = I0 ? INIT[1] : INIT[0];
+	specify
+		(I0 => O) = 74;
+	endspecify
+endmodule
+
+(* abc9_lut=2 *)
+module LUT2(output wire O, input wire I0, I1);
+	parameter [3:0] INIT = 0;
+	wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
+	assign O = I0 ? s1[1] : s1[0];
+	specify
+		(I0 => O) = 116;
+		(I1 => O) = 74;
+	endspecify
+endmodule
+
+(* abc9_lut=3 *)
+module LUT3(output wire O, input wire I0, I1, I2);
+	parameter [7:0] INIT = 0;
+	wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
+	wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+	assign O = I0 ? s1[1] : s1[0];
+	specify
+		(I0 => O) = 162;
+		(I1 => O) = 116;
+		(I2 => O) = 174;
+	endspecify
+endmodule
+
+(* abc9_lut=3 *)
+module LUT4(output wire O, input wire I0, I1, I2, I3);
+	parameter [15:0] INIT = 0;
+	wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
+	wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
+	wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+	assign O = I0 ? s1[1] : s1[0];
+	specify
+		(I0 => O) = 201;
+		(I1 => O) = 162;
+		(I2 => O) = 116;
+		(I3 => O) = 74;
+	endspecify
+endmodule
+
+(* abc9_lut=3 *)
+module LUT5(output wire O, input wire I0, I1, I2, I3, I4);
+	parameter [31:0] INIT = 0;
+	wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
+	wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
+	wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
+	wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+	assign O = I0 ? s1[1] : s1[0];
+	specify
+		(I0 => O) = 228;
+		(I1 => O) = 189;
+		(I2 => O) = 143;
+		(I3 => O) = 100;
+		(I4 => O) = 55;
+	endspecify
+endmodule
+
+(* abc9_lut=5 *)
+module LUT6(output wire O, input wire I0, I1, I2, I3, I4, I5);
+	parameter [63:0] INIT = 0;
+	wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
+	wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
+	wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
+	wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
+	wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+	assign O = I0 ? s1[1] : s1[0];
+	specify
+		(I0 => O) = 251;
+		(I1 => O) = 212;
+		(I2 => O) = 166;
+		(I3 => O) = 123;
+		(I4 => O) = 77;
+		(I5 => O) = 43;
+	endspecify
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module sh_dff(
+		output reg Q,
+		input wire D,
+		(* clkbuf_sink *)
+		input wire C
+);
+
+		initial Q = 1'b0;
+		always @(posedge C)
+				Q <= D;
+
+		specify
+			(posedge C => (Q +: D)) = 0;
+			$setuphold(posedge C, D, 0, 0);
+		endspecify
+
+endmodule
+
+(* abc9_box, lib_whitebox *)
+(* keep *)
+module adder_carry(
+		output wire sumout,
+		(* abc9_carry *)
+		output wire cout,
+		input wire p,
+		input wire g,
+		(* abc9_carry *)
+		input wire cin
+);
+		assign sumout = p ^ cin;
+		assign cout = p ? cin : g;
+
+		specify
+				(p => sumout) = 35;
+				(g => sumout) = 35;
+				(cin => sumout) = 40;
+				(p => cout) = 67;
+				(g => cout) = 65;
+				(cin => cout) = 69;
+		endspecify
+
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module dff(
+		output reg Q,
+		input wire D,
+		(* clkbuf_sink *)
+		input wire C
+);
+		initial Q = 1'b0;
+
+		always @(posedge C)
+			Q <= D;
+
+		specify
+			(posedge C=>(Q+:D)) = 285;
+			$setuphold(posedge C, D, 56, 0);
+		endspecify
+
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module dffn(
+		output reg Q,
+		input wire D,
+		(* clkbuf_sink *)
+		input wire C
+);
+		initial Q = 1'b0;
+
+		always @(negedge C)
+			Q <= D;
+
+		specify
+			(negedge C=>(Q+:D)) = 285;
+			$setuphold(negedge C, D, 56, 0);
+		endspecify
+
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module dffsre(
+		output reg Q,
+		input wire D,
+		(* clkbuf_sink *)
+		input wire C,
+		input wire E,
+		input wire R,
+		input wire S
+);
+		initial Q = 1'b0;
+
+		always @(posedge C or negedge S or negedge R)
+			if (!R)
+				Q <= 1'b0;
+			else if (!S)
+				Q <= 1'b1;
+			else if (E)
+				Q <= D;
+
+		specify
+			(posedge C => (Q +: D)) = 280;
+			(R => Q) = 0;
+			(S => Q) = 0;
+			$setuphold(posedge C, D, 56, 0);
+			$setuphold(posedge C, E, 32, 0);
+			$setuphold(posedge C, R, 0, 0);
+			$setuphold(posedge C, S, 0, 0);
+			$recrem(posedge R, posedge C, 0, 0);
+			$recrem(posedge S, posedge C, 0, 0);
+		endspecify
+
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module dffnsre(
+		output reg Q,
+		input wire D,
+		(* clkbuf_sink *)
+		input wire C,
+		input wire E,
+		input wire R,
+		input wire S
+);
+		initial Q = 1'b0;
+
+		always @(negedge C or negedge S or negedge R)
+			if (!R)
+				Q <= 1'b0;
+			else if (!S)
+				Q <= 1'b1;
+			else if (E)
+				Q <= D;
+
+		specify
+			(negedge C => (Q +: D)) = 280;
+			(R => Q) = 0;
+			(S => Q) = 0;
+			$setuphold(negedge C, D, 56, 0);
+			$setuphold(negedge C, E, 32, 0);
+			$setuphold(negedge C, R, 0, 0);
+			$setuphold(negedge C, S, 0, 0);
+			$recrem(posedge R, negedge C, 0, 0);
+			$recrem(posedge S, negedge C, 0, 0);
+		endspecify
+
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module sdffsre(
+		output reg Q,
+		input wire D,
+		(* clkbuf_sink *)
+		input wire C,
+		input wire E,
+		input wire R,
+		input wire S
+);
+		initial Q = 1'b0;
+
+		always @(posedge C)
+			if (!R)
+				Q <= 1'b0;
+			else if (!S)
+				Q <= 1'b1;
+			else if (E)
+				Q <= D;
+
+		specify
+				(posedge C => (Q +: D)) = 280;
+				$setuphold(posedge C, D, 56, 0);
+				$setuphold(posedge C, R, 32, 0);
+				$setuphold(posedge C, S, 0, 0);
+				$setuphold(posedge C, E, 0, 0);
+		endspecify
+
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module sdffnsre(
+		output reg Q,
+		input wire D,
+		(* clkbuf_sink *)
+		input wire C,
+		input wire E,
+		input wire R,
+		input wire S
+);
+		initial Q = 1'b0;
+
+		always @(negedge C)
+			if (!R)
+				Q <= 1'b0;
+			else if (!S)
+				Q <= 1'b1;
+			else if (E)
+				Q <= D;
+
+		specify
+				(negedge C => (Q +: D)) = 280;
+				$setuphold(negedge C, D, 56, 0);
+				$setuphold(negedge C, R, 32, 0);
+				$setuphold(negedge C, S, 0, 0);
+				$setuphold(negedge C, E, 0, 0);
+		endspecify
+
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module latchsre (
+		output reg Q,
+		input wire S,
+		input wire R,
+		input wire D,
+		input wire G,
+		input wire E
+);
+		initial Q = 1'b0;
+
+		always @*
+			begin
+				if (!R)
+					Q <= 1'b0;
+				else if (!S)
+					Q <= 1'b1;
+				else if (E && G)
+					Q <= D;
+			end
+
+		specify
+			(posedge G => (Q +: D)) = 0;
+			$setuphold(posedge G, D, 0, 0);
+			$setuphold(posedge G, E, 0, 0);
+			$setuphold(posedge G, R, 0, 0);
+			$setuphold(posedge G, S, 0, 0);
+		endspecify
+
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module latchnsre (
+		output reg Q,
+		input wire S,
+		input wire R,
+		input wire D,
+		input wire G,
+		input wire E
+);
+		initial Q = 1'b0;
+
+		always @*
+			begin
+				if (!R)
+					Q <= 1'b0;
+				else if (!S)
+					Q <= 1'b1;
+				else if (E && !G)
+					Q <= D;
+			end
+
+		specify
+			(negedge G => (Q +: D)) = 0;
+			$setuphold(negedge G, D, 0, 0);
+			$setuphold(negedge G, E, 0, 0);
+			$setuphold(negedge G, R, 0, 0);
+			$setuphold(negedge G, S, 0, 0);
+		endspecify
+
+endmodule
+
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v b/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v
new file mode 100644
index 00000000000..9eae617b90f
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v
@@ -0,0 +1,265 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module dsp_t1_20x18x64_cfg_ports (
+    input  [19:0] a_i,
+    input  [17:0] b_i,
+    input  [ 5:0] acc_fir_i,
+    output [37:0] z_o,
+    output [17:0] dly_b_o,
+
+    input         clock_i,
+    input         reset_i,
+
+    input  [2:0]  feedback_i,
+    input         load_acc_i,
+    input         unsigned_a_i,
+    input         unsigned_b_i,
+
+    input  [2:0]  output_select_i,
+    input         saturate_enable_i,
+    input  [5:0]  shift_right_i,
+    input         round_i,
+    input         subtract_i,
+    input         register_inputs_i
+);
+
+    parameter [19:0] COEFF_0 = 20'd0;
+    parameter [19:0] COEFF_1 = 20'd0;
+    parameter [19:0] COEFF_2 = 20'd0;
+    parameter [19:0] COEFF_3 = 20'd0;
+
+    QL_DSP2 # (
+        .MODE_BITS          ({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+    ) _TECHMAP_REPLACE_ (
+        .a                  (a_i),
+        .b                  (b_i),
+        .acc_fir            (acc_fir_i),
+        .z                  (z_o),
+        .dly_b              (dly_b_o),
+
+        .clk                (clock_i),
+        .reset              (reset_i),
+
+        .feedback           (feedback_i),
+        .load_acc           (load_acc_i),
+        .unsigned_a         (unsigned_a_i),
+        .unsigned_b         (unsigned_b_i),
+
+        .f_mode             (1'b0), // No fracturation
+        .output_select      (output_select_i),
+        .saturate_enable    (saturate_enable_i),
+        .shift_right        (shift_right_i),
+        .round              (round_i),
+        .subtract           (subtract_i),
+        .register_inputs    (register_inputs_i)
+    );
+
+endmodule
+
+module dsp_t1_10x9x32_cfg_ports (
+    input  [ 9:0] a_i,
+    input  [ 8:0] b_i,
+    input  [ 5:0] acc_fir_i,
+    output [18:0] z_o,
+    output [ 8:0] dly_b_o,
+
+    (* clkbuf_sink *)
+    input         clock_i,
+    input         reset_i,
+
+    input  [2:0]  feedback_i,
+    input         load_acc_i,
+    input         unsigned_a_i,
+    input         unsigned_b_i,
+
+    input  [2:0]  output_select_i,
+    input         saturate_enable_i,
+    input  [5:0]  shift_right_i,
+    input         round_i,
+    input         subtract_i,
+    input         register_inputs_i
+);
+
+    parameter [9:0] COEFF_0 = 10'd0;
+    parameter [9:0] COEFF_1 = 10'd0;
+    parameter [9:0] COEFF_2 = 10'd0;
+    parameter [9:0] COEFF_3 = 10'd0;
+
+    wire [37:0] z;
+    wire [17:0] dly_b;
+
+    QL_DSP2 # (
+        .MODE_BITS          ({10'd0, COEFF_3,
+                              10'd0, COEFF_2,
+                              10'd0, COEFF_1,
+                              10'd0, COEFF_0})
+    ) _TECHMAP_REPLACE_ (
+        .a                  ({10'd0, a_i}),
+        .b                  ({ 9'd0, b_i}),
+        .acc_fir            (acc_fir_i),
+        .z                  (z),
+        .dly_b              (dly_b),
+
+        .clk                (clock_i),
+        .reset              (reset_i),
+
+        .feedback           (feedback_i),
+        .load_acc           (load_acc_i),
+        .unsigned_a         (unsigned_a_i),
+        .unsigned_b         (unsigned_b_i),
+
+        .f_mode             (1'b1), // Enable fractuation, Use the lower half
+        .output_select      (output_select_i),
+        .saturate_enable    (saturate_enable_i),
+        .shift_right        (shift_right_i),
+        .round              (round_i),
+        .subtract           (subtract_i),
+        .register_inputs    (register_inputs_i)
+    );
+
+    assign z_o = z[18:0];
+    assign dly_b_o = dly_b_o[8:0];
+
+endmodule
+
+module dsp_t1_20x18x64_cfg_params (
+    input  [19:0] a_i,
+    input  [17:0] b_i,
+    input  [ 5:0] acc_fir_i,
+    output [37:0] z_o,
+    output [17:0] dly_b_o,
+
+    input         clock_i,
+    input         reset_i,
+
+    input  [2:0]  feedback_i,
+    input         load_acc_i,
+    input         unsigned_a_i,
+    input         unsigned_b_i,
+    input         subtract_i
+);
+
+    parameter [19:0] COEFF_0 = 20'd0;
+    parameter [19:0] COEFF_1 = 20'd0;
+    parameter [19:0] COEFF_2 = 20'd0;
+    parameter [19:0] COEFF_3 = 20'd0;
+
+    parameter [2:0] OUTPUT_SELECT   = 3'd0;
+    parameter [0:0] SATURATE_ENABLE = 1'd0;
+    parameter [5:0] SHIFT_RIGHT     = 6'd0;
+    parameter [0:0] ROUND           = 1'd0;
+    parameter [0:0] REGISTER_INPUTS = 1'd0;
+
+    QL_DSP3 # (
+        .MODE_BITS ({
+            REGISTER_INPUTS,
+            ROUND,
+            SHIFT_RIGHT,
+            SATURATE_ENABLE,
+            OUTPUT_SELECT,
+            1'b0, // Not fractured
+            COEFF_3,
+            COEFF_2,
+            COEFF_1,
+            COEFF_0
+        })
+    ) _TECHMAP_REPLACE_ (
+        .a                  (a_i),
+        .b                  (b_i),
+        .acc_fir            (acc_fir_i),
+        .z                  (z_o),
+        .dly_b              (dly_b_o),
+
+        .clk                (clock_i),
+        .reset              (reset_i),
+
+        .feedback           (feedback_i),
+        .load_acc           (load_acc_i),
+        .unsigned_a         (unsigned_a_i),
+        .unsigned_b         (unsigned_b_i),
+        .subtract           (subtract_i)
+    );
+
+endmodule
+
+module dsp_t1_10x9x32_cfg_params (
+    input  [ 9:0] a_i,
+    input  [ 8:0] b_i,
+    input  [ 5:0] acc_fir_i,
+    output [18:0] z_o,
+    output [ 8:0] dly_b_o,
+
+    (* clkbuf_sink *)
+    input         clock_i,
+    input         reset_i,
+
+    input  [2:0]  feedback_i,
+    input         load_acc_i,
+    input         unsigned_a_i,
+    input         unsigned_b_i,
+    input         subtract_i
+);
+
+    parameter [9:0] COEFF_0 = 10'd0;
+    parameter [9:0] COEFF_1 = 10'd0;
+    parameter [9:0] COEFF_2 = 10'd0;
+    parameter [9:0] COEFF_3 = 10'd0;
+
+    parameter [2:0] OUTPUT_SELECT   = 3'd0;
+    parameter [0:0] SATURATE_ENABLE = 1'd0;
+    parameter [5:0] SHIFT_RIGHT     = 6'd0;
+    parameter [0:0] ROUND           = 1'd0;
+    parameter [0:0] REGISTER_INPUTS = 1'd0;
+
+    wire [37:0] z;
+    wire [17:0] dly_b;
+
+    QL_DSP3 # (
+        .MODE_BITS  ({
+            REGISTER_INPUTS,
+            ROUND,
+            SHIFT_RIGHT,
+            SATURATE_ENABLE,
+            OUTPUT_SELECT,
+            1'b1, // Fractured
+            10'd0, COEFF_3,
+            10'd0, COEFF_2,
+            10'd0, COEFF_1,
+            10'd0, COEFF_0
+        })
+    ) _TECHMAP_REPLACE_ (
+        .a                  ({10'd0, a_i}),
+        .b                  ({ 9'd0, b_i}),
+        .acc_fir            (acc_fir_i),
+        .z                  (z),
+        .dly_b              (dly_b),
+
+        .clk                (clock_i),
+        .reset              (reset_i),
+
+        .feedback           (feedback_i),
+        .load_acc           (load_acc_i),
+        .unsigned_a         (unsigned_a_i),
+        .unsigned_b         (unsigned_b_i),
+        .subtract           (subtract_i)
+    );
+
+    assign z_o = z[18:0];
+    assign dly_b_o = dly_b_o[8:0];
+
+endmodule
+
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_map.v b/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_map.v
new file mode 100644
index 00000000000..127145b71a9
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_map.v
@@ -0,0 +1,102 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module \$__QL_MUL20X18 (input [19:0] A, input [17:0] B, output [37:0] Y);
+    parameter A_SIGNED = 0;
+    parameter B_SIGNED = 0;
+    parameter A_WIDTH = 0;
+    parameter B_WIDTH = 0;
+    parameter Y_WIDTH = 0;
+
+    wire [19:0] a;
+    wire [17:0] b;
+    wire [37:0] z;
+
+    assign a = (A_WIDTH == 20) ? A :
+               (A_SIGNED) ? {{(20 - A_WIDTH){A[A_WIDTH-1]}}, A} :
+                            {{(20 - A_WIDTH){1'b0}},         A};
+
+    assign b = (B_WIDTH == 18) ? B :
+               (B_SIGNED) ? {{(18 - B_WIDTH){B[B_WIDTH-1]}}, B} :
+                            {{(18 - B_WIDTH){1'b0}},         B};
+
+    (* is_inferred=1 *)
+    dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ (
+        .a_i                (a),
+        .b_i                (b),
+        .acc_fir_i          (6'd0),
+        .z_o                (z),
+
+        .feedback_i         (3'd0),
+        .load_acc_i         (1'b0),
+        .unsigned_a_i       (!A_SIGNED),
+        .unsigned_b_i       (!B_SIGNED),
+
+        .output_select_i    (3'd0),
+        .saturate_enable_i  (1'b0),
+        .shift_right_i      (6'd0),
+        .round_i            (1'b0),
+        .subtract_i         (1'b0),
+        .register_inputs_i  (1'b0)
+    );
+
+    assign Y = z;
+
+endmodule
+
+module \$__QL_MUL10X9 (input [9:0] A, input [8:0] B, output [18:0] Y);
+    parameter A_SIGNED = 0;
+    parameter B_SIGNED = 0;
+    parameter A_WIDTH = 0;
+    parameter B_WIDTH = 0;
+    parameter Y_WIDTH = 0;
+
+    wire [ 9:0] a;
+    wire [ 8:0] b;
+    wire [18:0] z;
+
+    assign a = (A_WIDTH == 10) ? A :
+               (A_SIGNED) ? {{(10 - A_WIDTH){A[A_WIDTH-1]}}, A} :
+                            {{(10 - A_WIDTH){1'b0}},         A};
+
+    assign b = (B_WIDTH ==  9) ? B :
+               (B_SIGNED) ? {{( 9 - B_WIDTH){B[B_WIDTH-1]}}, B} :
+                            {{( 9 - B_WIDTH){1'b0}},         B};
+
+    (* is_inferred=1 *)
+    dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ (
+        .a_i                (a),
+        .b_i                (b),
+        .acc_fir_i          (6'd0),
+        .z_o                (z),
+
+        .feedback_i         (3'd0),
+        .load_acc_i         (1'b0),
+        .unsigned_a_i       (!A_SIGNED),
+        .unsigned_b_i       (!B_SIGNED),
+
+        .output_select_i    (3'd0),
+        .saturate_enable_i  (1'b0),
+        .shift_right_i      (6'd0),
+        .round_i            (1'b0),
+        .subtract_i         (1'b0),
+        .register_inputs_i  (1'b0)
+    );
+
+
+    assign Y = z;
+
+endmodule
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v b/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v
new file mode 100644
index 00000000000..5f43b322912
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v
@@ -0,0 +1,4527 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ps/1ps
+
+`default_nettype none
+
+(* blackbox *)
+module QL_DSP1 (
+	input wire [19:0] a,
+	input wire [17:0] b,
+	(* clkbuf_sink *)
+	input wire clk0,
+	(* clkbuf_sink *)
+	input wire clk1,
+	input wire [ 1:0] feedback0,
+	input wire [ 1:0] feedback1,
+	input wire        load_acc0,
+	input wire        load_acc1,
+	input wire        reset0,
+	input wire        reset1,
+	output reg [37:0] z
+);
+	parameter MODE_BITS = 27'b00000000000000000000000000;
+endmodule  /* QL_DSP1 */
+
+
+
+// ---------------------------------------- //
+// ----- DSP cells simulation modules ----- //
+// --------- Control bits in ports -------- //
+// ---------------------------------------- //
+
+module QL_DSP2 ( // TODO: Name subject to change
+	input  wire [19:0] a,
+	input  wire [17:0] b,
+	input  wire [ 5:0] acc_fir,
+	output wire [37:0] z,
+	output wire [17:0] dly_b,
+
+	(* clkbuf_sink *)
+	input  wire       clk,
+	input  wire       reset,
+
+	input  wire [2:0] feedback,
+	input  wire       load_acc,
+	input  wire       unsigned_a,
+	input  wire       unsigned_b,
+
+	input  wire       f_mode,
+	input  wire [2:0] output_select,
+	input  wire       saturate_enable,
+	input  wire [5:0] shift_right,
+	input  wire       round,
+	input  wire       subtract,
+	input  wire       register_inputs
+);
+
+	parameter [79:0] MODE_BITS = 80'd0;
+
+	localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+	localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+	localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+	localparam [19:0] COEFF_3 = MODE_BITS[79:60];
+
+	localparam NBITS_ACC = 64;
+	localparam NBITS_A = 20;
+	localparam NBITS_B = 18;
+	localparam NBITS_Z = 38;
+
+	wire [NBITS_Z-1:0] dsp_full_z;
+	wire [(NBITS_Z/2)-1:0] dsp_frac0_z;
+	wire [(NBITS_Z/2)-1:0] dsp_frac1_z;
+
+	wire [NBITS_B-1:0] dsp_full_dly_b;
+	wire [(NBITS_B/2)-1:0] dsp_frac0_dly_b;
+	wire [(NBITS_B/2)-1:0] dsp_frac1_dly_b;
+
+	assign z = f_mode ? {dsp_frac1_z, dsp_frac0_z} : dsp_full_z;
+	assign dly_b = f_mode ? {dsp_frac1_dly_b, dsp_frac0_dly_b} : dsp_full_dly_b;
+
+	// Output used when fmode == 1
+		dsp_t1_sim_cfg_ports #(
+		.NBITS_A(NBITS_A/2),
+			.NBITS_B(NBITS_B/2),
+			.NBITS_ACC(NBITS_ACC/2),
+			.NBITS_Z(NBITS_Z/2)
+		) dsp_frac0 (
+			.a_i(a[(NBITS_A/2)-1:0]),
+			.b_i(b[(NBITS_B/2)-1:0]),
+			.z_o(dsp_frac0_z),
+			.dly_b_o(dsp_frac0_dly_b),
+
+			.acc_fir_i(acc_fir),
+			.feedback_i(feedback),
+			.load_acc_i(load_acc),
+
+			.unsigned_a_i(unsigned_a),
+			.unsigned_b_i(unsigned_b),
+
+			.clock_i(clk),
+			.s_reset(reset),
+
+			.saturate_enable_i(saturate_enable),
+			.output_select_i(output_select),
+			.round_i(round),
+			.shift_right_i(shift_right),
+			.subtract_i(subtract),
+			.register_inputs_i(register_inputs),
+			.coef_0_i(COEFF_0[(NBITS_A/2)-1:0]),
+			.coef_1_i(COEFF_1[(NBITS_A/2)-1:0]),
+			.coef_2_i(COEFF_2[(NBITS_A/2)-1:0]),
+			.coef_3_i(COEFF_3[(NBITS_A/2)-1:0])
+		);
+
+	// Output used when fmode == 1
+		dsp_t1_sim_cfg_ports #(
+		.NBITS_A(NBITS_A/2),
+			.NBITS_B(NBITS_B/2),
+			.NBITS_ACC(NBITS_ACC/2),
+			.NBITS_Z(NBITS_Z/2)
+		) dsp_frac1 (
+			.a_i(a[NBITS_A-1:NBITS_A/2]),
+			.b_i(b[NBITS_B-1:NBITS_B/2]),
+			.z_o(dsp_frac1_z),
+			.dly_b_o(dsp_frac1_dly_b),
+
+			.acc_fir_i(acc_fir),
+			.feedback_i(feedback),
+			.load_acc_i(load_acc),
+
+			.unsigned_a_i(unsigned_a),
+			.unsigned_b_i(unsigned_b),
+
+			.clock_i(clk),
+			.s_reset(reset),
+
+			.saturate_enable_i(saturate_enable),
+			.output_select_i(output_select),
+			.round_i(round),
+			.shift_right_i(shift_right),
+			.subtract_i(subtract),
+			.register_inputs_i(register_inputs),
+			.coef_0_i(COEFF_0[NBITS_A-1:NBITS_A/2]),
+			.coef_1_i(COEFF_1[NBITS_A-1:NBITS_A/2]),
+			.coef_2_i(COEFF_2[NBITS_A-1:NBITS_A/2]),
+			.coef_3_i(COEFF_3[NBITS_A-1:NBITS_A/2])
+		);
+
+	// Output used when fmode == 0
+		dsp_t1_sim_cfg_ports #(
+			.NBITS_A(NBITS_A),
+			.NBITS_B(NBITS_B),
+			.NBITS_ACC(NBITS_ACC),
+			.NBITS_Z(NBITS_Z)
+		) dsp_full (
+			.a_i(a),
+			.b_i(b),
+			.z_o(dsp_full_z),
+			.dly_b_o(dsp_full_dly_b),
+
+			.acc_fir_i(acc_fir),
+			.feedback_i(feedback),
+			.load_acc_i(load_acc),
+
+			.unsigned_a_i(unsigned_a),
+			.unsigned_b_i(unsigned_b),
+
+			.clock_i(clk),
+			.s_reset(reset),
+
+			.saturate_enable_i(saturate_enable),
+			.output_select_i(output_select),
+			.round_i(round),
+			.shift_right_i(shift_right),
+			.subtract_i(subtract),
+			.register_inputs_i(register_inputs),
+			.coef_0_i(COEFF_0),
+			.coef_1_i(COEFF_1),
+			.coef_2_i(COEFF_2),
+			.coef_3_i(COEFF_3)
+		);
+endmodule
+
+module QL_DSP2_MULT ( // TODO: Name subject to change
+	input  wire [19:0] a,
+	input  wire [17:0] b,
+	output wire [37:0] z,
+
+	input  wire       reset,
+
+	input  wire [2:0] feedback,
+	input  wire       unsigned_a,
+	input  wire       unsigned_b,
+
+	input  wire       f_mode,
+	input  wire [2:0] output_select,
+	input  wire       register_inputs
+);
+
+	parameter [79:0] MODE_BITS = 80'd0;
+
+	localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+	localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+	localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+	localparam [19:0] COEFF_3 = MODE_BITS[79:60];
+
+	QL_DSP2 #(
+		.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+	) dsp (
+		.a(a),
+		.b(b),
+		.acc_fir(6'b0),
+		.z(z),
+		.dly_b(),
+
+		.clk(1'b0),
+		.reset(reset),
+
+		.f_mode(f_mode),
+
+		.feedback(feedback),
+		.load_acc(1'b0),
+
+		.unsigned_a(unsigned_a),
+		.unsigned_b(unsigned_b),
+
+		.output_select(output_select),      // unregistered output: a * b (0)
+		.saturate_enable(1'b0),
+		.shift_right(6'b0),
+		.round(1'b0),
+		.subtract(1'b0),
+		.register_inputs(register_inputs)   // unregistered inputs
+	);
+
+`ifdef SDF_SIM
+	specify
+		(a[0] => z[0]) = 0;
+		(a[1] => z[0]) = 0;
+		(a[2] => z[0]) = 0;
+		(a[3] => z[0]) = 0;
+		(a[4] => z[0]) = 0;
+		(a[5] => z[0]) = 0;
+		(a[6] => z[0]) = 0;
+		(a[7] => z[0]) = 0;
+		(a[8] => z[0]) = 0;
+		(a[9] => z[0]) = 0;
+		(a[10] => z[0]) = 0;
+		(a[11] => z[0]) = 0;
+		(a[12] => z[0]) = 0;
+		(a[13] => z[0]) = 0;
+		(a[14] => z[0]) = 0;
+		(a[15] => z[0]) = 0;
+		(a[16] => z[0]) = 0;
+		(a[17] => z[0]) = 0;
+		(a[18] => z[0]) = 0;
+		(a[19] => z[0]) = 0;
+		(b[0] => z[0]) = 0;
+		(b[1] => z[0]) = 0;
+		(b[2] => z[0]) = 0;
+		(b[3] => z[0]) = 0;
+		(b[4] => z[0]) = 0;
+		(b[5] => z[0]) = 0;
+		(b[6] => z[0]) = 0;
+		(b[7] => z[0]) = 0;
+		(b[8] => z[0]) = 0;
+		(b[9] => z[0]) = 0;
+		(b[10] => z[0]) = 0;
+		(b[11] => z[0]) = 0;
+		(b[12] => z[0]) = 0;
+		(b[13] => z[0]) = 0;
+		(b[14] => z[0]) = 0;
+		(b[15] => z[0]) = 0;
+		(b[16] => z[0]) = 0;
+		(b[17] => z[0]) = 0;
+		(a[0] => z[1]) = 0;
+		(a[1] => z[1]) = 0;
+		(a[2] => z[1]) = 0;
+		(a[3] => z[1]) = 0;
+		(a[4] => z[1]) = 0;
+		(a[5] => z[1]) = 0;
+		(a[6] => z[1]) = 0;
+		(a[7] => z[1]) = 0;
+		(a[8] => z[1]) = 0;
+		(a[9] => z[1]) = 0;
+		(a[10] => z[1]) = 0;
+		(a[11] => z[1]) = 0;
+		(a[12] => z[1]) = 0;
+		(a[13] => z[1]) = 0;
+		(a[14] => z[1]) = 0;
+		(a[15] => z[1]) = 0;
+		(a[16] => z[1]) = 0;
+		(a[17] => z[1]) = 0;
+		(a[18] => z[1]) = 0;
+		(a[19] => z[1]) = 0;
+		(b[0] => z[1]) = 0;
+		(b[1] => z[1]) = 0;
+		(b[2] => z[1]) = 0;
+		(b[3] => z[1]) = 0;
+		(b[4] => z[1]) = 0;
+		(b[5] => z[1]) = 0;
+		(b[6] => z[1]) = 0;
+		(b[7] => z[1]) = 0;
+		(b[8] => z[1]) = 0;
+		(b[9] => z[1]) = 0;
+		(b[10] => z[1]) = 0;
+		(b[11] => z[1]) = 0;
+		(b[12] => z[1]) = 0;
+		(b[13] => z[1]) = 0;
+		(b[14] => z[1]) = 0;
+		(b[15] => z[1]) = 0;
+		(b[16] => z[1]) = 0;
+		(b[17] => z[1]) = 0;
+		(a[0] => z[2]) = 0;
+		(a[1] => z[2]) = 0;
+		(a[2] => z[2]) = 0;
+		(a[3] => z[2]) = 0;
+		(a[4] => z[2]) = 0;
+		(a[5] => z[2]) = 0;
+		(a[6] => z[2]) = 0;
+		(a[7] => z[2]) = 0;
+		(a[8] => z[2]) = 0;
+		(a[9] => z[2]) = 0;
+		(a[10] => z[2]) = 0;
+		(a[11] => z[2]) = 0;
+		(a[12] => z[2]) = 0;
+		(a[13] => z[2]) = 0;
+		(a[14] => z[2]) = 0;
+		(a[15] => z[2]) = 0;
+		(a[16] => z[2]) = 0;
+		(a[17] => z[2]) = 0;
+		(a[18] => z[2]) = 0;
+		(a[19] => z[2]) = 0;
+		(b[0] => z[2]) = 0;
+		(b[1] => z[2]) = 0;
+		(b[2] => z[2]) = 0;
+		(b[3] => z[2]) = 0;
+		(b[4] => z[2]) = 0;
+		(b[5] => z[2]) = 0;
+		(b[6] => z[2]) = 0;
+		(b[7] => z[2]) = 0;
+		(b[8] => z[2]) = 0;
+		(b[9] => z[2]) = 0;
+		(b[10] => z[2]) = 0;
+		(b[11] => z[2]) = 0;
+		(b[12] => z[2]) = 0;
+		(b[13] => z[2]) = 0;
+		(b[14] => z[2]) = 0;
+		(b[15] => z[2]) = 0;
+		(b[16] => z[2]) = 0;
+		(b[17] => z[2]) = 0;
+		(a[0] => z[3]) = 0;
+		(a[1] => z[3]) = 0;
+		(a[2] => z[3]) = 0;
+		(a[3] => z[3]) = 0;
+		(a[4] => z[3]) = 0;
+		(a[5] => z[3]) = 0;
+		(a[6] => z[3]) = 0;
+		(a[7] => z[3]) = 0;
+		(a[8] => z[3]) = 0;
+		(a[9] => z[3]) = 0;
+		(a[10] => z[3]) = 0;
+		(a[11] => z[3]) = 0;
+		(a[12] => z[3]) = 0;
+		(a[13] => z[3]) = 0;
+		(a[14] => z[3]) = 0;
+		(a[15] => z[3]) = 0;
+		(a[16] => z[3]) = 0;
+		(a[17] => z[3]) = 0;
+		(a[18] => z[3]) = 0;
+		(a[19] => z[3]) = 0;
+		(b[0] => z[3]) = 0;
+		(b[1] => z[3]) = 0;
+		(b[2] => z[3]) = 0;
+		(b[3] => z[3]) = 0;
+		(b[4] => z[3]) = 0;
+		(b[5] => z[3]) = 0;
+		(b[6] => z[3]) = 0;
+		(b[7] => z[3]) = 0;
+		(b[8] => z[3]) = 0;
+		(b[9] => z[3]) = 0;
+		(b[10] => z[3]) = 0;
+		(b[11] => z[3]) = 0;
+		(b[12] => z[3]) = 0;
+		(b[13] => z[3]) = 0;
+		(b[14] => z[3]) = 0;
+		(b[15] => z[3]) = 0;
+		(b[16] => z[3]) = 0;
+		(b[17] => z[3]) = 0;
+		(a[0] => z[4]) = 0;
+		(a[1] => z[4]) = 0;
+		(a[2] => z[4]) = 0;
+		(a[3] => z[4]) = 0;
+		(a[4] => z[4]) = 0;
+		(a[5] => z[4]) = 0;
+		(a[6] => z[4]) = 0;
+		(a[7] => z[4]) = 0;
+		(a[8] => z[4]) = 0;
+		(a[9] => z[4]) = 0;
+		(a[10] => z[4]) = 0;
+		(a[11] => z[4]) = 0;
+		(a[12] => z[4]) = 0;
+		(a[13] => z[4]) = 0;
+		(a[14] => z[4]) = 0;
+		(a[15] => z[4]) = 0;
+		(a[16] => z[4]) = 0;
+		(a[17] => z[4]) = 0;
+		(a[18] => z[4]) = 0;
+		(a[19] => z[4]) = 0;
+		(b[0] => z[4]) = 0;
+		(b[1] => z[4]) = 0;
+		(b[2] => z[4]) = 0;
+		(b[3] => z[4]) = 0;
+		(b[4] => z[4]) = 0;
+		(b[5] => z[4]) = 0;
+		(b[6] => z[4]) = 0;
+		(b[7] => z[4]) = 0;
+		(b[8] => z[4]) = 0;
+		(b[9] => z[4]) = 0;
+		(b[10] => z[4]) = 0;
+		(b[11] => z[4]) = 0;
+		(b[12] => z[4]) = 0;
+		(b[13] => z[4]) = 0;
+		(b[14] => z[4]) = 0;
+		(b[15] => z[4]) = 0;
+		(b[16] => z[4]) = 0;
+		(b[17] => z[4]) = 0;
+		(a[0] => z[5]) = 0;
+		(a[1] => z[5]) = 0;
+		(a[2] => z[5]) = 0;
+		(a[3] => z[5]) = 0;
+		(a[4] => z[5]) = 0;
+		(a[5] => z[5]) = 0;
+		(a[6] => z[5]) = 0;
+		(a[7] => z[5]) = 0;
+		(a[8] => z[5]) = 0;
+		(a[9] => z[5]) = 0;
+		(a[10] => z[5]) = 0;
+		(a[11] => z[5]) = 0;
+		(a[12] => z[5]) = 0;
+		(a[13] => z[5]) = 0;
+		(a[14] => z[5]) = 0;
+		(a[15] => z[5]) = 0;
+		(a[16] => z[5]) = 0;
+		(a[17] => z[5]) = 0;
+		(a[18] => z[5]) = 0;
+		(a[19] => z[5]) = 0;
+		(b[0] => z[5]) = 0;
+		(b[1] => z[5]) = 0;
+		(b[2] => z[5]) = 0;
+		(b[3] => z[5]) = 0;
+		(b[4] => z[5]) = 0;
+		(b[5] => z[5]) = 0;
+		(b[6] => z[5]) = 0;
+		(b[7] => z[5]) = 0;
+		(b[8] => z[5]) = 0;
+		(b[9] => z[5]) = 0;
+		(b[10] => z[5]) = 0;
+		(b[11] => z[5]) = 0;
+		(b[12] => z[5]) = 0;
+		(b[13] => z[5]) = 0;
+		(b[14] => z[5]) = 0;
+		(b[15] => z[5]) = 0;
+		(b[16] => z[5]) = 0;
+		(b[17] => z[5]) = 0;
+		(a[0] => z[6]) = 0;
+		(a[1] => z[6]) = 0;
+		(a[2] => z[6]) = 0;
+		(a[3] => z[6]) = 0;
+		(a[4] => z[6]) = 0;
+		(a[5] => z[6]) = 0;
+		(a[6] => z[6]) = 0;
+		(a[7] => z[6]) = 0;
+		(a[8] => z[6]) = 0;
+		(a[9] => z[6]) = 0;
+		(a[10] => z[6]) = 0;
+		(a[11] => z[6]) = 0;
+		(a[12] => z[6]) = 0;
+		(a[13] => z[6]) = 0;
+		(a[14] => z[6]) = 0;
+		(a[15] => z[6]) = 0;
+		(a[16] => z[6]) = 0;
+		(a[17] => z[6]) = 0;
+		(a[18] => z[6]) = 0;
+		(a[19] => z[6]) = 0;
+		(b[0] => z[6]) = 0;
+		(b[1] => z[6]) = 0;
+		(b[2] => z[6]) = 0;
+		(b[3] => z[6]) = 0;
+		(b[4] => z[6]) = 0;
+		(b[5] => z[6]) = 0;
+		(b[6] => z[6]) = 0;
+		(b[7] => z[6]) = 0;
+		(b[8] => z[6]) = 0;
+		(b[9] => z[6]) = 0;
+		(b[10] => z[6]) = 0;
+		(b[11] => z[6]) = 0;
+		(b[12] => z[6]) = 0;
+		(b[13] => z[6]) = 0;
+		(b[14] => z[6]) = 0;
+		(b[15] => z[6]) = 0;
+		(b[16] => z[6]) = 0;
+		(b[17] => z[6]) = 0;
+		(a[0] => z[7]) = 0;
+		(a[1] => z[7]) = 0;
+		(a[2] => z[7]) = 0;
+		(a[3] => z[7]) = 0;
+		(a[4] => z[7]) = 0;
+		(a[5] => z[7]) = 0;
+		(a[6] => z[7]) = 0;
+		(a[7] => z[7]) = 0;
+		(a[8] => z[7]) = 0;
+		(a[9] => z[7]) = 0;
+		(a[10] => z[7]) = 0;
+		(a[11] => z[7]) = 0;
+		(a[12] => z[7]) = 0;
+		(a[13] => z[7]) = 0;
+		(a[14] => z[7]) = 0;
+		(a[15] => z[7]) = 0;
+		(a[16] => z[7]) = 0;
+		(a[17] => z[7]) = 0;
+		(a[18] => z[7]) = 0;
+		(a[19] => z[7]) = 0;
+		(b[0] => z[7]) = 0;
+		(b[1] => z[7]) = 0;
+		(b[2] => z[7]) = 0;
+		(b[3] => z[7]) = 0;
+		(b[4] => z[7]) = 0;
+		(b[5] => z[7]) = 0;
+		(b[6] => z[7]) = 0;
+		(b[7] => z[7]) = 0;
+		(b[8] => z[7]) = 0;
+		(b[9] => z[7]) = 0;
+		(b[10] => z[7]) = 0;
+		(b[11] => z[7]) = 0;
+		(b[12] => z[7]) = 0;
+		(b[13] => z[7]) = 0;
+		(b[14] => z[7]) = 0;
+		(b[15] => z[7]) = 0;
+		(b[16] => z[7]) = 0;
+		(b[17] => z[7]) = 0;
+		(a[0] => z[8]) = 0;
+		(a[1] => z[8]) = 0;
+		(a[2] => z[8]) = 0;
+		(a[3] => z[8]) = 0;
+		(a[4] => z[8]) = 0;
+		(a[5] => z[8]) = 0;
+		(a[6] => z[8]) = 0;
+		(a[7] => z[8]) = 0;
+		(a[8] => z[8]) = 0;
+		(a[9] => z[8]) = 0;
+		(a[10] => z[8]) = 0;
+		(a[11] => z[8]) = 0;
+		(a[12] => z[8]) = 0;
+		(a[13] => z[8]) = 0;
+		(a[14] => z[8]) = 0;
+		(a[15] => z[8]) = 0;
+		(a[16] => z[8]) = 0;
+		(a[17] => z[8]) = 0;
+		(a[18] => z[8]) = 0;
+		(a[19] => z[8]) = 0;
+		(b[0] => z[8]) = 0;
+		(b[1] => z[8]) = 0;
+		(b[2] => z[8]) = 0;
+		(b[3] => z[8]) = 0;
+		(b[4] => z[8]) = 0;
+		(b[5] => z[8]) = 0;
+		(b[6] => z[8]) = 0;
+		(b[7] => z[8]) = 0;
+		(b[8] => z[8]) = 0;
+		(b[9] => z[8]) = 0;
+		(b[10] => z[8]) = 0;
+		(b[11] => z[8]) = 0;
+		(b[12] => z[8]) = 0;
+		(b[13] => z[8]) = 0;
+		(b[14] => z[8]) = 0;
+		(b[15] => z[8]) = 0;
+		(b[16] => z[8]) = 0;
+		(b[17] => z[8]) = 0;
+		(a[0] => z[9]) = 0;
+		(a[1] => z[9]) = 0;
+		(a[2] => z[9]) = 0;
+		(a[3] => z[9]) = 0;
+		(a[4] => z[9]) = 0;
+		(a[5] => z[9]) = 0;
+		(a[6] => z[9]) = 0;
+		(a[7] => z[9]) = 0;
+		(a[8] => z[9]) = 0;
+		(a[9] => z[9]) = 0;
+		(a[10] => z[9]) = 0;
+		(a[11] => z[9]) = 0;
+		(a[12] => z[9]) = 0;
+		(a[13] => z[9]) = 0;
+		(a[14] => z[9]) = 0;
+		(a[15] => z[9]) = 0;
+		(a[16] => z[9]) = 0;
+		(a[17] => z[9]) = 0;
+		(a[18] => z[9]) = 0;
+		(a[19] => z[9]) = 0;
+		(b[0] => z[9]) = 0;
+		(b[1] => z[9]) = 0;
+		(b[2] => z[9]) = 0;
+		(b[3] => z[9]) = 0;
+		(b[4] => z[9]) = 0;
+		(b[5] => z[9]) = 0;
+		(b[6] => z[9]) = 0;
+		(b[7] => z[9]) = 0;
+		(b[8] => z[9]) = 0;
+		(b[9] => z[9]) = 0;
+		(b[10] => z[9]) = 0;
+		(b[11] => z[9]) = 0;
+		(b[12] => z[9]) = 0;
+		(b[13] => z[9]) = 0;
+		(b[14] => z[9]) = 0;
+		(b[15] => z[9]) = 0;
+		(b[16] => z[9]) = 0;
+		(b[17] => z[9]) = 0;
+		(a[0] => z[10]) = 0;
+		(a[1] => z[10]) = 0;
+		(a[2] => z[10]) = 0;
+		(a[3] => z[10]) = 0;
+		(a[4] => z[10]) = 0;
+		(a[5] => z[10]) = 0;
+		(a[6] => z[10]) = 0;
+		(a[7] => z[10]) = 0;
+		(a[8] => z[10]) = 0;
+		(a[9] => z[10]) = 0;
+		(a[10] => z[10]) = 0;
+		(a[11] => z[10]) = 0;
+		(a[12] => z[10]) = 0;
+		(a[13] => z[10]) = 0;
+		(a[14] => z[10]) = 0;
+		(a[15] => z[10]) = 0;
+		(a[16] => z[10]) = 0;
+		(a[17] => z[10]) = 0;
+		(a[18] => z[10]) = 0;
+		(a[19] => z[10]) = 0;
+		(b[0] => z[10]) = 0;
+		(b[1] => z[10]) = 0;
+		(b[2] => z[10]) = 0;
+		(b[3] => z[10]) = 0;
+		(b[4] => z[10]) = 0;
+		(b[5] => z[10]) = 0;
+		(b[6] => z[10]) = 0;
+		(b[7] => z[10]) = 0;
+		(b[8] => z[10]) = 0;
+		(b[9] => z[10]) = 0;
+		(b[10] => z[10]) = 0;
+		(b[11] => z[10]) = 0;
+		(b[12] => z[10]) = 0;
+		(b[13] => z[10]) = 0;
+		(b[14] => z[10]) = 0;
+		(b[15] => z[10]) = 0;
+		(b[16] => z[10]) = 0;
+		(b[17] => z[10]) = 0;
+		(a[0] => z[11]) = 0;
+		(a[1] => z[11]) = 0;
+		(a[2] => z[11]) = 0;
+		(a[3] => z[11]) = 0;
+		(a[4] => z[11]) = 0;
+		(a[5] => z[11]) = 0;
+		(a[6] => z[11]) = 0;
+		(a[7] => z[11]) = 0;
+		(a[8] => z[11]) = 0;
+		(a[9] => z[11]) = 0;
+		(a[10] => z[11]) = 0;
+		(a[11] => z[11]) = 0;
+		(a[12] => z[11]) = 0;
+		(a[13] => z[11]) = 0;
+		(a[14] => z[11]) = 0;
+		(a[15] => z[11]) = 0;
+		(a[16] => z[11]) = 0;
+		(a[17] => z[11]) = 0;
+		(a[18] => z[11]) = 0;
+		(a[19] => z[11]) = 0;
+		(b[0] => z[11]) = 0;
+		(b[1] => z[11]) = 0;
+		(b[2] => z[11]) = 0;
+		(b[3] => z[11]) = 0;
+		(b[4] => z[11]) = 0;
+		(b[5] => z[11]) = 0;
+		(b[6] => z[11]) = 0;
+		(b[7] => z[11]) = 0;
+		(b[8] => z[11]) = 0;
+		(b[9] => z[11]) = 0;
+		(b[10] => z[11]) = 0;
+		(b[11] => z[11]) = 0;
+		(b[12] => z[11]) = 0;
+		(b[13] => z[11]) = 0;
+		(b[14] => z[11]) = 0;
+		(b[15] => z[11]) = 0;
+		(b[16] => z[11]) = 0;
+		(b[17] => z[11]) = 0;
+		(a[0] => z[12]) = 0;
+		(a[1] => z[12]) = 0;
+		(a[2] => z[12]) = 0;
+		(a[3] => z[12]) = 0;
+		(a[4] => z[12]) = 0;
+		(a[5] => z[12]) = 0;
+		(a[6] => z[12]) = 0;
+		(a[7] => z[12]) = 0;
+		(a[8] => z[12]) = 0;
+		(a[9] => z[12]) = 0;
+		(a[10] => z[12]) = 0;
+		(a[11] => z[12]) = 0;
+		(a[12] => z[12]) = 0;
+		(a[13] => z[12]) = 0;
+		(a[14] => z[12]) = 0;
+		(a[15] => z[12]) = 0;
+		(a[16] => z[12]) = 0;
+		(a[17] => z[12]) = 0;
+		(a[18] => z[12]) = 0;
+		(a[19] => z[12]) = 0;
+		(b[0] => z[12]) = 0;
+		(b[1] => z[12]) = 0;
+		(b[2] => z[12]) = 0;
+		(b[3] => z[12]) = 0;
+		(b[4] => z[12]) = 0;
+		(b[5] => z[12]) = 0;
+		(b[6] => z[12]) = 0;
+		(b[7] => z[12]) = 0;
+		(b[8] => z[12]) = 0;
+		(b[9] => z[12]) = 0;
+		(b[10] => z[12]) = 0;
+		(b[11] => z[12]) = 0;
+		(b[12] => z[12]) = 0;
+		(b[13] => z[12]) = 0;
+		(b[14] => z[12]) = 0;
+		(b[15] => z[12]) = 0;
+		(b[16] => z[12]) = 0;
+		(b[17] => z[12]) = 0;
+		(a[0] => z[13]) = 0;
+		(a[1] => z[13]) = 0;
+		(a[2] => z[13]) = 0;
+		(a[3] => z[13]) = 0;
+		(a[4] => z[13]) = 0;
+		(a[5] => z[13]) = 0;
+		(a[6] => z[13]) = 0;
+		(a[7] => z[13]) = 0;
+		(a[8] => z[13]) = 0;
+		(a[9] => z[13]) = 0;
+		(a[10] => z[13]) = 0;
+		(a[11] => z[13]) = 0;
+		(a[12] => z[13]) = 0;
+		(a[13] => z[13]) = 0;
+		(a[14] => z[13]) = 0;
+		(a[15] => z[13]) = 0;
+		(a[16] => z[13]) = 0;
+		(a[17] => z[13]) = 0;
+		(a[18] => z[13]) = 0;
+		(a[19] => z[13]) = 0;
+		(b[0] => z[13]) = 0;
+		(b[1] => z[13]) = 0;
+		(b[2] => z[13]) = 0;
+		(b[3] => z[13]) = 0;
+		(b[4] => z[13]) = 0;
+		(b[5] => z[13]) = 0;
+		(b[6] => z[13]) = 0;
+		(b[7] => z[13]) = 0;
+		(b[8] => z[13]) = 0;
+		(b[9] => z[13]) = 0;
+		(b[10] => z[13]) = 0;
+		(b[11] => z[13]) = 0;
+		(b[12] => z[13]) = 0;
+		(b[13] => z[13]) = 0;
+		(b[14] => z[13]) = 0;
+		(b[15] => z[13]) = 0;
+		(b[16] => z[13]) = 0;
+		(b[17] => z[13]) = 0;
+		(a[0] => z[14]) = 0;
+		(a[1] => z[14]) = 0;
+		(a[2] => z[14]) = 0;
+		(a[3] => z[14]) = 0;
+		(a[4] => z[14]) = 0;
+		(a[5] => z[14]) = 0;
+		(a[6] => z[14]) = 0;
+		(a[7] => z[14]) = 0;
+		(a[8] => z[14]) = 0;
+		(a[9] => z[14]) = 0;
+		(a[10] => z[14]) = 0;
+		(a[11] => z[14]) = 0;
+		(a[12] => z[14]) = 0;
+		(a[13] => z[14]) = 0;
+		(a[14] => z[14]) = 0;
+		(a[15] => z[14]) = 0;
+		(a[16] => z[14]) = 0;
+		(a[17] => z[14]) = 0;
+		(a[18] => z[14]) = 0;
+		(a[19] => z[14]) = 0;
+		(b[0] => z[14]) = 0;
+		(b[1] => z[14]) = 0;
+		(b[2] => z[14]) = 0;
+		(b[3] => z[14]) = 0;
+		(b[4] => z[14]) = 0;
+		(b[5] => z[14]) = 0;
+		(b[6] => z[14]) = 0;
+		(b[7] => z[14]) = 0;
+		(b[8] => z[14]) = 0;
+		(b[9] => z[14]) = 0;
+		(b[10] => z[14]) = 0;
+		(b[11] => z[14]) = 0;
+		(b[12] => z[14]) = 0;
+		(b[13] => z[14]) = 0;
+		(b[14] => z[14]) = 0;
+		(b[15] => z[14]) = 0;
+		(b[16] => z[14]) = 0;
+		(b[17] => z[14]) = 0;
+		(a[0] => z[15]) = 0;
+		(a[1] => z[15]) = 0;
+		(a[2] => z[15]) = 0;
+		(a[3] => z[15]) = 0;
+		(a[4] => z[15]) = 0;
+		(a[5] => z[15]) = 0;
+		(a[6] => z[15]) = 0;
+		(a[7] => z[15]) = 0;
+		(a[8] => z[15]) = 0;
+		(a[9] => z[15]) = 0;
+		(a[10] => z[15]) = 0;
+		(a[11] => z[15]) = 0;
+		(a[12] => z[15]) = 0;
+		(a[13] => z[15]) = 0;
+		(a[14] => z[15]) = 0;
+		(a[15] => z[15]) = 0;
+		(a[16] => z[15]) = 0;
+		(a[17] => z[15]) = 0;
+		(a[18] => z[15]) = 0;
+		(a[19] => z[15]) = 0;
+		(b[0] => z[15]) = 0;
+		(b[1] => z[15]) = 0;
+		(b[2] => z[15]) = 0;
+		(b[3] => z[15]) = 0;
+		(b[4] => z[15]) = 0;
+		(b[5] => z[15]) = 0;
+		(b[6] => z[15]) = 0;
+		(b[7] => z[15]) = 0;
+		(b[8] => z[15]) = 0;
+		(b[9] => z[15]) = 0;
+		(b[10] => z[15]) = 0;
+		(b[11] => z[15]) = 0;
+		(b[12] => z[15]) = 0;
+		(b[13] => z[15]) = 0;
+		(b[14] => z[15]) = 0;
+		(b[15] => z[15]) = 0;
+		(b[16] => z[15]) = 0;
+		(b[17] => z[15]) = 0;
+		(a[0] => z[16]) = 0;
+		(a[1] => z[16]) = 0;
+		(a[2] => z[16]) = 0;
+		(a[3] => z[16]) = 0;
+		(a[4] => z[16]) = 0;
+		(a[5] => z[16]) = 0;
+		(a[6] => z[16]) = 0;
+		(a[7] => z[16]) = 0;
+		(a[8] => z[16]) = 0;
+		(a[9] => z[16]) = 0;
+		(a[10] => z[16]) = 0;
+		(a[11] => z[16]) = 0;
+		(a[12] => z[16]) = 0;
+		(a[13] => z[16]) = 0;
+		(a[14] => z[16]) = 0;
+		(a[15] => z[16]) = 0;
+		(a[16] => z[16]) = 0;
+		(a[17] => z[16]) = 0;
+		(a[18] => z[16]) = 0;
+		(a[19] => z[16]) = 0;
+		(b[0] => z[16]) = 0;
+		(b[1] => z[16]) = 0;
+		(b[2] => z[16]) = 0;
+		(b[3] => z[16]) = 0;
+		(b[4] => z[16]) = 0;
+		(b[5] => z[16]) = 0;
+		(b[6] => z[16]) = 0;
+		(b[7] => z[16]) = 0;
+		(b[8] => z[16]) = 0;
+		(b[9] => z[16]) = 0;
+		(b[10] => z[16]) = 0;
+		(b[11] => z[16]) = 0;
+		(b[12] => z[16]) = 0;
+		(b[13] => z[16]) = 0;
+		(b[14] => z[16]) = 0;
+		(b[15] => z[16]) = 0;
+		(b[16] => z[16]) = 0;
+		(b[17] => z[16]) = 0;
+		(a[0] => z[17]) = 0;
+		(a[1] => z[17]) = 0;
+		(a[2] => z[17]) = 0;
+		(a[3] => z[17]) = 0;
+		(a[4] => z[17]) = 0;
+		(a[5] => z[17]) = 0;
+		(a[6] => z[17]) = 0;
+		(a[7] => z[17]) = 0;
+		(a[8] => z[17]) = 0;
+		(a[9] => z[17]) = 0;
+		(a[10] => z[17]) = 0;
+		(a[11] => z[17]) = 0;
+		(a[12] => z[17]) = 0;
+		(a[13] => z[17]) = 0;
+		(a[14] => z[17]) = 0;
+		(a[15] => z[17]) = 0;
+		(a[16] => z[17]) = 0;
+		(a[17] => z[17]) = 0;
+		(a[18] => z[17]) = 0;
+		(a[19] => z[17]) = 0;
+		(b[0] => z[17]) = 0;
+		(b[1] => z[17]) = 0;
+		(b[2] => z[17]) = 0;
+		(b[3] => z[17]) = 0;
+		(b[4] => z[17]) = 0;
+		(b[5] => z[17]) = 0;
+		(b[6] => z[17]) = 0;
+		(b[7] => z[17]) = 0;
+		(b[8] => z[17]) = 0;
+		(b[9] => z[17]) = 0;
+		(b[10] => z[17]) = 0;
+		(b[11] => z[17]) = 0;
+		(b[12] => z[17]) = 0;
+		(b[13] => z[17]) = 0;
+		(b[14] => z[17]) = 0;
+		(b[15] => z[17]) = 0;
+		(b[16] => z[17]) = 0;
+		(b[17] => z[17]) = 0;
+		(a[0] => z[18]) = 0;
+		(a[1] => z[18]) = 0;
+		(a[2] => z[18]) = 0;
+		(a[3] => z[18]) = 0;
+		(a[4] => z[18]) = 0;
+		(a[5] => z[18]) = 0;
+		(a[6] => z[18]) = 0;
+		(a[7] => z[18]) = 0;
+		(a[8] => z[18]) = 0;
+		(a[9] => z[18]) = 0;
+		(a[10] => z[18]) = 0;
+		(a[11] => z[18]) = 0;
+		(a[12] => z[18]) = 0;
+		(a[13] => z[18]) = 0;
+		(a[14] => z[18]) = 0;
+		(a[15] => z[18]) = 0;
+		(a[16] => z[18]) = 0;
+		(a[17] => z[18]) = 0;
+		(a[18] => z[18]) = 0;
+		(a[19] => z[18]) = 0;
+		(b[0] => z[18]) = 0;
+		(b[1] => z[18]) = 0;
+		(b[2] => z[18]) = 0;
+		(b[3] => z[18]) = 0;
+		(b[4] => z[18]) = 0;
+		(b[5] => z[18]) = 0;
+		(b[6] => z[18]) = 0;
+		(b[7] => z[18]) = 0;
+		(b[8] => z[18]) = 0;
+		(b[9] => z[18]) = 0;
+		(b[10] => z[18]) = 0;
+		(b[11] => z[18]) = 0;
+		(b[12] => z[18]) = 0;
+		(b[13] => z[18]) = 0;
+		(b[14] => z[18]) = 0;
+		(b[15] => z[18]) = 0;
+		(b[16] => z[18]) = 0;
+		(b[17] => z[18]) = 0;
+		(a[0] => z[19]) = 0;
+		(a[1] => z[19]) = 0;
+		(a[2] => z[19]) = 0;
+		(a[3] => z[19]) = 0;
+		(a[4] => z[19]) = 0;
+		(a[5] => z[19]) = 0;
+		(a[6] => z[19]) = 0;
+		(a[7] => z[19]) = 0;
+		(a[8] => z[19]) = 0;
+		(a[9] => z[19]) = 0;
+		(a[10] => z[19]) = 0;
+		(a[11] => z[19]) = 0;
+		(a[12] => z[19]) = 0;
+		(a[13] => z[19]) = 0;
+		(a[14] => z[19]) = 0;
+		(a[15] => z[19]) = 0;
+		(a[16] => z[19]) = 0;
+		(a[17] => z[19]) = 0;
+		(a[18] => z[19]) = 0;
+		(a[19] => z[19]) = 0;
+		(b[0] => z[19]) = 0;
+		(b[1] => z[19]) = 0;
+		(b[2] => z[19]) = 0;
+		(b[3] => z[19]) = 0;
+		(b[4] => z[19]) = 0;
+		(b[5] => z[19]) = 0;
+		(b[6] => z[19]) = 0;
+		(b[7] => z[19]) = 0;
+		(b[8] => z[19]) = 0;
+		(b[9] => z[19]) = 0;
+		(b[10] => z[19]) = 0;
+		(b[11] => z[19]) = 0;
+		(b[12] => z[19]) = 0;
+		(b[13] => z[19]) = 0;
+		(b[14] => z[19]) = 0;
+		(b[15] => z[19]) = 0;
+		(b[16] => z[19]) = 0;
+		(b[17] => z[19]) = 0;
+		(a[0] => z[20]) = 0;
+		(a[1] => z[20]) = 0;
+		(a[2] => z[20]) = 0;
+		(a[3] => z[20]) = 0;
+		(a[4] => z[20]) = 0;
+		(a[5] => z[20]) = 0;
+		(a[6] => z[20]) = 0;
+		(a[7] => z[20]) = 0;
+		(a[8] => z[20]) = 0;
+		(a[9] => z[20]) = 0;
+		(a[10] => z[20]) = 0;
+		(a[11] => z[20]) = 0;
+		(a[12] => z[20]) = 0;
+		(a[13] => z[20]) = 0;
+		(a[14] => z[20]) = 0;
+		(a[15] => z[20]) = 0;
+		(a[16] => z[20]) = 0;
+		(a[17] => z[20]) = 0;
+		(a[18] => z[20]) = 0;
+		(a[19] => z[20]) = 0;
+		(b[0] => z[20]) = 0;
+		(b[1] => z[20]) = 0;
+		(b[2] => z[20]) = 0;
+		(b[3] => z[20]) = 0;
+		(b[4] => z[20]) = 0;
+		(b[5] => z[20]) = 0;
+		(b[6] => z[20]) = 0;
+		(b[7] => z[20]) = 0;
+		(b[8] => z[20]) = 0;
+		(b[9] => z[20]) = 0;
+		(b[10] => z[20]) = 0;
+		(b[11] => z[20]) = 0;
+		(b[12] => z[20]) = 0;
+		(b[13] => z[20]) = 0;
+		(b[14] => z[20]) = 0;
+		(b[15] => z[20]) = 0;
+		(b[16] => z[20]) = 0;
+		(b[17] => z[20]) = 0;
+		(a[0] => z[21]) = 0;
+		(a[1] => z[21]) = 0;
+		(a[2] => z[21]) = 0;
+		(a[3] => z[21]) = 0;
+		(a[4] => z[21]) = 0;
+		(a[5] => z[21]) = 0;
+		(a[6] => z[21]) = 0;
+		(a[7] => z[21]) = 0;
+		(a[8] => z[21]) = 0;
+		(a[9] => z[21]) = 0;
+		(a[10] => z[21]) = 0;
+		(a[11] => z[21]) = 0;
+		(a[12] => z[21]) = 0;
+		(a[13] => z[21]) = 0;
+		(a[14] => z[21]) = 0;
+		(a[15] => z[21]) = 0;
+		(a[16] => z[21]) = 0;
+		(a[17] => z[21]) = 0;
+		(a[18] => z[21]) = 0;
+		(a[19] => z[21]) = 0;
+		(b[0] => z[21]) = 0;
+		(b[1] => z[21]) = 0;
+		(b[2] => z[21]) = 0;
+		(b[3] => z[21]) = 0;
+		(b[4] => z[21]) = 0;
+		(b[5] => z[21]) = 0;
+		(b[6] => z[21]) = 0;
+		(b[7] => z[21]) = 0;
+		(b[8] => z[21]) = 0;
+		(b[9] => z[21]) = 0;
+		(b[10] => z[21]) = 0;
+		(b[11] => z[21]) = 0;
+		(b[12] => z[21]) = 0;
+		(b[13] => z[21]) = 0;
+		(b[14] => z[21]) = 0;
+		(b[15] => z[21]) = 0;
+		(b[16] => z[21]) = 0;
+		(b[17] => z[21]) = 0;
+		(a[0] => z[22]) = 0;
+		(a[1] => z[22]) = 0;
+		(a[2] => z[22]) = 0;
+		(a[3] => z[22]) = 0;
+		(a[4] => z[22]) = 0;
+		(a[5] => z[22]) = 0;
+		(a[6] => z[22]) = 0;
+		(a[7] => z[22]) = 0;
+		(a[8] => z[22]) = 0;
+		(a[9] => z[22]) = 0;
+		(a[10] => z[22]) = 0;
+		(a[11] => z[22]) = 0;
+		(a[12] => z[22]) = 0;
+		(a[13] => z[22]) = 0;
+		(a[14] => z[22]) = 0;
+		(a[15] => z[22]) = 0;
+		(a[16] => z[22]) = 0;
+		(a[17] => z[22]) = 0;
+		(a[18] => z[22]) = 0;
+		(a[19] => z[22]) = 0;
+		(b[0] => z[22]) = 0;
+		(b[1] => z[22]) = 0;
+		(b[2] => z[22]) = 0;
+		(b[3] => z[22]) = 0;
+		(b[4] => z[22]) = 0;
+		(b[5] => z[22]) = 0;
+		(b[6] => z[22]) = 0;
+		(b[7] => z[22]) = 0;
+		(b[8] => z[22]) = 0;
+		(b[9] => z[22]) = 0;
+		(b[10] => z[22]) = 0;
+		(b[11] => z[22]) = 0;
+		(b[12] => z[22]) = 0;
+		(b[13] => z[22]) = 0;
+		(b[14] => z[22]) = 0;
+		(b[15] => z[22]) = 0;
+		(b[16] => z[22]) = 0;
+		(b[17] => z[22]) = 0;
+		(a[0] => z[23]) = 0;
+		(a[1] => z[23]) = 0;
+		(a[2] => z[23]) = 0;
+		(a[3] => z[23]) = 0;
+		(a[4] => z[23]) = 0;
+		(a[5] => z[23]) = 0;
+		(a[6] => z[23]) = 0;
+		(a[7] => z[23]) = 0;
+		(a[8] => z[23]) = 0;
+		(a[9] => z[23]) = 0;
+		(a[10] => z[23]) = 0;
+		(a[11] => z[23]) = 0;
+		(a[12] => z[23]) = 0;
+		(a[13] => z[23]) = 0;
+		(a[14] => z[23]) = 0;
+		(a[15] => z[23]) = 0;
+		(a[16] => z[23]) = 0;
+		(a[17] => z[23]) = 0;
+		(a[18] => z[23]) = 0;
+		(a[19] => z[23]) = 0;
+		(b[0] => z[23]) = 0;
+		(b[1] => z[23]) = 0;
+		(b[2] => z[23]) = 0;
+		(b[3] => z[23]) = 0;
+		(b[4] => z[23]) = 0;
+		(b[5] => z[23]) = 0;
+		(b[6] => z[23]) = 0;
+		(b[7] => z[23]) = 0;
+		(b[8] => z[23]) = 0;
+		(b[9] => z[23]) = 0;
+		(b[10] => z[23]) = 0;
+		(b[11] => z[23]) = 0;
+		(b[12] => z[23]) = 0;
+		(b[13] => z[23]) = 0;
+		(b[14] => z[23]) = 0;
+		(b[15] => z[23]) = 0;
+		(b[16] => z[23]) = 0;
+		(b[17] => z[23]) = 0;
+		(a[0] => z[24]) = 0;
+		(a[1] => z[24]) = 0;
+		(a[2] => z[24]) = 0;
+		(a[3] => z[24]) = 0;
+		(a[4] => z[24]) = 0;
+		(a[5] => z[24]) = 0;
+		(a[6] => z[24]) = 0;
+		(a[7] => z[24]) = 0;
+		(a[8] => z[24]) = 0;
+		(a[9] => z[24]) = 0;
+		(a[10] => z[24]) = 0;
+		(a[11] => z[24]) = 0;
+		(a[12] => z[24]) = 0;
+		(a[13] => z[24]) = 0;
+		(a[14] => z[24]) = 0;
+		(a[15] => z[24]) = 0;
+		(a[16] => z[24]) = 0;
+		(a[17] => z[24]) = 0;
+		(a[18] => z[24]) = 0;
+		(a[19] => z[24]) = 0;
+		(b[0] => z[24]) = 0;
+		(b[1] => z[24]) = 0;
+		(b[2] => z[24]) = 0;
+		(b[3] => z[24]) = 0;
+		(b[4] => z[24]) = 0;
+		(b[5] => z[24]) = 0;
+		(b[6] => z[24]) = 0;
+		(b[7] => z[24]) = 0;
+		(b[8] => z[24]) = 0;
+		(b[9] => z[24]) = 0;
+		(b[10] => z[24]) = 0;
+		(b[11] => z[24]) = 0;
+		(b[12] => z[24]) = 0;
+		(b[13] => z[24]) = 0;
+		(b[14] => z[24]) = 0;
+		(b[15] => z[24]) = 0;
+		(b[16] => z[24]) = 0;
+		(b[17] => z[24]) = 0;
+		(a[0] => z[25]) = 0;
+		(a[1] => z[25]) = 0;
+		(a[2] => z[25]) = 0;
+		(a[3] => z[25]) = 0;
+		(a[4] => z[25]) = 0;
+		(a[5] => z[25]) = 0;
+		(a[6] => z[25]) = 0;
+		(a[7] => z[25]) = 0;
+		(a[8] => z[25]) = 0;
+		(a[9] => z[25]) = 0;
+		(a[10] => z[25]) = 0;
+		(a[11] => z[25]) = 0;
+		(a[12] => z[25]) = 0;
+		(a[13] => z[25]) = 0;
+		(a[14] => z[25]) = 0;
+		(a[15] => z[25]) = 0;
+		(a[16] => z[25]) = 0;
+		(a[17] => z[25]) = 0;
+		(a[18] => z[25]) = 0;
+		(a[19] => z[25]) = 0;
+		(b[0] => z[25]) = 0;
+		(b[1] => z[25]) = 0;
+		(b[2] => z[25]) = 0;
+		(b[3] => z[25]) = 0;
+		(b[4] => z[25]) = 0;
+		(b[5] => z[25]) = 0;
+		(b[6] => z[25]) = 0;
+		(b[7] => z[25]) = 0;
+		(b[8] => z[25]) = 0;
+		(b[9] => z[25]) = 0;
+		(b[10] => z[25]) = 0;
+		(b[11] => z[25]) = 0;
+		(b[12] => z[25]) = 0;
+		(b[13] => z[25]) = 0;
+		(b[14] => z[25]) = 0;
+		(b[15] => z[25]) = 0;
+		(b[16] => z[25]) = 0;
+		(b[17] => z[25]) = 0;
+		(a[0] => z[26]) = 0;
+		(a[1] => z[26]) = 0;
+		(a[2] => z[26]) = 0;
+		(a[3] => z[26]) = 0;
+		(a[4] => z[26]) = 0;
+		(a[5] => z[26]) = 0;
+		(a[6] => z[26]) = 0;
+		(a[7] => z[26]) = 0;
+		(a[8] => z[26]) = 0;
+		(a[9] => z[26]) = 0;
+		(a[10] => z[26]) = 0;
+		(a[11] => z[26]) = 0;
+		(a[12] => z[26]) = 0;
+		(a[13] => z[26]) = 0;
+		(a[14] => z[26]) = 0;
+		(a[15] => z[26]) = 0;
+		(a[16] => z[26]) = 0;
+		(a[17] => z[26]) = 0;
+		(a[18] => z[26]) = 0;
+		(a[19] => z[26]) = 0;
+		(b[0] => z[26]) = 0;
+		(b[1] => z[26]) = 0;
+		(b[2] => z[26]) = 0;
+		(b[3] => z[26]) = 0;
+		(b[4] => z[26]) = 0;
+		(b[5] => z[26]) = 0;
+		(b[6] => z[26]) = 0;
+		(b[7] => z[26]) = 0;
+		(b[8] => z[26]) = 0;
+		(b[9] => z[26]) = 0;
+		(b[10] => z[26]) = 0;
+		(b[11] => z[26]) = 0;
+		(b[12] => z[26]) = 0;
+		(b[13] => z[26]) = 0;
+		(b[14] => z[26]) = 0;
+		(b[15] => z[26]) = 0;
+		(b[16] => z[26]) = 0;
+		(b[17] => z[26]) = 0;
+		(a[0] => z[27]) = 0;
+		(a[1] => z[27]) = 0;
+		(a[2] => z[27]) = 0;
+		(a[3] => z[27]) = 0;
+		(a[4] => z[27]) = 0;
+		(a[5] => z[27]) = 0;
+		(a[6] => z[27]) = 0;
+		(a[7] => z[27]) = 0;
+		(a[8] => z[27]) = 0;
+		(a[9] => z[27]) = 0;
+		(a[10] => z[27]) = 0;
+		(a[11] => z[27]) = 0;
+		(a[12] => z[27]) = 0;
+		(a[13] => z[27]) = 0;
+		(a[14] => z[27]) = 0;
+		(a[15] => z[27]) = 0;
+		(a[16] => z[27]) = 0;
+		(a[17] => z[27]) = 0;
+		(a[18] => z[27]) = 0;
+		(a[19] => z[27]) = 0;
+		(b[0] => z[27]) = 0;
+		(b[1] => z[27]) = 0;
+		(b[2] => z[27]) = 0;
+		(b[3] => z[27]) = 0;
+		(b[4] => z[27]) = 0;
+		(b[5] => z[27]) = 0;
+		(b[6] => z[27]) = 0;
+		(b[7] => z[27]) = 0;
+		(b[8] => z[27]) = 0;
+		(b[9] => z[27]) = 0;
+		(b[10] => z[27]) = 0;
+		(b[11] => z[27]) = 0;
+		(b[12] => z[27]) = 0;
+		(b[13] => z[27]) = 0;
+		(b[14] => z[27]) = 0;
+		(b[15] => z[27]) = 0;
+		(b[16] => z[27]) = 0;
+		(b[17] => z[27]) = 0;
+		(a[0] => z[28]) = 0;
+		(a[1] => z[28]) = 0;
+		(a[2] => z[28]) = 0;
+		(a[3] => z[28]) = 0;
+		(a[4] => z[28]) = 0;
+		(a[5] => z[28]) = 0;
+		(a[6] => z[28]) = 0;
+		(a[7] => z[28]) = 0;
+		(a[8] => z[28]) = 0;
+		(a[9] => z[28]) = 0;
+		(a[10] => z[28]) = 0;
+		(a[11] => z[28]) = 0;
+		(a[12] => z[28]) = 0;
+		(a[13] => z[28]) = 0;
+		(a[14] => z[28]) = 0;
+		(a[15] => z[28]) = 0;
+		(a[16] => z[28]) = 0;
+		(a[17] => z[28]) = 0;
+		(a[18] => z[28]) = 0;
+		(a[19] => z[28]) = 0;
+		(b[0] => z[28]) = 0;
+		(b[1] => z[28]) = 0;
+		(b[2] => z[28]) = 0;
+		(b[3] => z[28]) = 0;
+		(b[4] => z[28]) = 0;
+		(b[5] => z[28]) = 0;
+		(b[6] => z[28]) = 0;
+		(b[7] => z[28]) = 0;
+		(b[8] => z[28]) = 0;
+		(b[9] => z[28]) = 0;
+		(b[10] => z[28]) = 0;
+		(b[11] => z[28]) = 0;
+		(b[12] => z[28]) = 0;
+		(b[13] => z[28]) = 0;
+		(b[14] => z[28]) = 0;
+		(b[15] => z[28]) = 0;
+		(b[16] => z[28]) = 0;
+		(b[17] => z[28]) = 0;
+		(a[0] => z[29]) = 0;
+		(a[1] => z[29]) = 0;
+		(a[2] => z[29]) = 0;
+		(a[3] => z[29]) = 0;
+		(a[4] => z[29]) = 0;
+		(a[5] => z[29]) = 0;
+		(a[6] => z[29]) = 0;
+		(a[7] => z[29]) = 0;
+		(a[8] => z[29]) = 0;
+		(a[9] => z[29]) = 0;
+		(a[10] => z[29]) = 0;
+		(a[11] => z[29]) = 0;
+		(a[12] => z[29]) = 0;
+		(a[13] => z[29]) = 0;
+		(a[14] => z[29]) = 0;
+		(a[15] => z[29]) = 0;
+		(a[16] => z[29]) = 0;
+		(a[17] => z[29]) = 0;
+		(a[18] => z[29]) = 0;
+		(a[19] => z[29]) = 0;
+		(b[0] => z[29]) = 0;
+		(b[1] => z[29]) = 0;
+		(b[2] => z[29]) = 0;
+		(b[3] => z[29]) = 0;
+		(b[4] => z[29]) = 0;
+		(b[5] => z[29]) = 0;
+		(b[6] => z[29]) = 0;
+		(b[7] => z[29]) = 0;
+		(b[8] => z[29]) = 0;
+		(b[9] => z[29]) = 0;
+		(b[10] => z[29]) = 0;
+		(b[11] => z[29]) = 0;
+		(b[12] => z[29]) = 0;
+		(b[13] => z[29]) = 0;
+		(b[14] => z[29]) = 0;
+		(b[15] => z[29]) = 0;
+		(b[16] => z[29]) = 0;
+		(b[17] => z[29]) = 0;
+		(a[0] => z[30]) = 0;
+		(a[1] => z[30]) = 0;
+		(a[2] => z[30]) = 0;
+		(a[3] => z[30]) = 0;
+		(a[4] => z[30]) = 0;
+		(a[5] => z[30]) = 0;
+		(a[6] => z[30]) = 0;
+		(a[7] => z[30]) = 0;
+		(a[8] => z[30]) = 0;
+		(a[9] => z[30]) = 0;
+		(a[10] => z[30]) = 0;
+		(a[11] => z[30]) = 0;
+		(a[12] => z[30]) = 0;
+		(a[13] => z[30]) = 0;
+		(a[14] => z[30]) = 0;
+		(a[15] => z[30]) = 0;
+		(a[16] => z[30]) = 0;
+		(a[17] => z[30]) = 0;
+		(a[18] => z[30]) = 0;
+		(a[19] => z[30]) = 0;
+		(b[0] => z[30]) = 0;
+		(b[1] => z[30]) = 0;
+		(b[2] => z[30]) = 0;
+		(b[3] => z[30]) = 0;
+		(b[4] => z[30]) = 0;
+		(b[5] => z[30]) = 0;
+		(b[6] => z[30]) = 0;
+		(b[7] => z[30]) = 0;
+		(b[8] => z[30]) = 0;
+		(b[9] => z[30]) = 0;
+		(b[10] => z[30]) = 0;
+		(b[11] => z[30]) = 0;
+		(b[12] => z[30]) = 0;
+		(b[13] => z[30]) = 0;
+		(b[14] => z[30]) = 0;
+		(b[15] => z[30]) = 0;
+		(b[16] => z[30]) = 0;
+		(b[17] => z[30]) = 0;
+		(a[0] => z[31]) = 0;
+		(a[1] => z[31]) = 0;
+		(a[2] => z[31]) = 0;
+		(a[3] => z[31]) = 0;
+		(a[4] => z[31]) = 0;
+		(a[5] => z[31]) = 0;
+		(a[6] => z[31]) = 0;
+		(a[7] => z[31]) = 0;
+		(a[8] => z[31]) = 0;
+		(a[9] => z[31]) = 0;
+		(a[10] => z[31]) = 0;
+		(a[11] => z[31]) = 0;
+		(a[12] => z[31]) = 0;
+		(a[13] => z[31]) = 0;
+		(a[14] => z[31]) = 0;
+		(a[15] => z[31]) = 0;
+		(a[16] => z[31]) = 0;
+		(a[17] => z[31]) = 0;
+		(a[18] => z[31]) = 0;
+		(a[19] => z[31]) = 0;
+		(b[0] => z[31]) = 0;
+		(b[1] => z[31]) = 0;
+		(b[2] => z[31]) = 0;
+		(b[3] => z[31]) = 0;
+		(b[4] => z[31]) = 0;
+		(b[5] => z[31]) = 0;
+		(b[6] => z[31]) = 0;
+		(b[7] => z[31]) = 0;
+		(b[8] => z[31]) = 0;
+		(b[9] => z[31]) = 0;
+		(b[10] => z[31]) = 0;
+		(b[11] => z[31]) = 0;
+		(b[12] => z[31]) = 0;
+		(b[13] => z[31]) = 0;
+		(b[14] => z[31]) = 0;
+		(b[15] => z[31]) = 0;
+		(b[16] => z[31]) = 0;
+		(b[17] => z[31]) = 0;
+		(a[0] => z[32]) = 0;
+		(a[1] => z[32]) = 0;
+		(a[2] => z[32]) = 0;
+		(a[3] => z[32]) = 0;
+		(a[4] => z[32]) = 0;
+		(a[5] => z[32]) = 0;
+		(a[6] => z[32]) = 0;
+		(a[7] => z[32]) = 0;
+		(a[8] => z[32]) = 0;
+		(a[9] => z[32]) = 0;
+		(a[10] => z[32]) = 0;
+		(a[11] => z[32]) = 0;
+		(a[12] => z[32]) = 0;
+		(a[13] => z[32]) = 0;
+		(a[14] => z[32]) = 0;
+		(a[15] => z[32]) = 0;
+		(a[16] => z[32]) = 0;
+		(a[17] => z[32]) = 0;
+		(a[18] => z[32]) = 0;
+		(a[19] => z[32]) = 0;
+		(b[0] => z[32]) = 0;
+		(b[1] => z[32]) = 0;
+		(b[2] => z[32]) = 0;
+		(b[3] => z[32]) = 0;
+		(b[4] => z[32]) = 0;
+		(b[5] => z[32]) = 0;
+		(b[6] => z[32]) = 0;
+		(b[7] => z[32]) = 0;
+		(b[8] => z[32]) = 0;
+		(b[9] => z[32]) = 0;
+		(b[10] => z[32]) = 0;
+		(b[11] => z[32]) = 0;
+		(b[12] => z[32]) = 0;
+		(b[13] => z[32]) = 0;
+		(b[14] => z[32]) = 0;
+		(b[15] => z[32]) = 0;
+		(b[16] => z[32]) = 0;
+		(b[17] => z[32]) = 0;
+		(a[0] => z[33]) = 0;
+		(a[1] => z[33]) = 0;
+		(a[2] => z[33]) = 0;
+		(a[3] => z[33]) = 0;
+		(a[4] => z[33]) = 0;
+		(a[5] => z[33]) = 0;
+		(a[6] => z[33]) = 0;
+		(a[7] => z[33]) = 0;
+		(a[8] => z[33]) = 0;
+		(a[9] => z[33]) = 0;
+		(a[10] => z[33]) = 0;
+		(a[11] => z[33]) = 0;
+		(a[12] => z[33]) = 0;
+		(a[13] => z[33]) = 0;
+		(a[14] => z[33]) = 0;
+		(a[15] => z[33]) = 0;
+		(a[16] => z[33]) = 0;
+		(a[17] => z[33]) = 0;
+		(a[18] => z[33]) = 0;
+		(a[19] => z[33]) = 0;
+		(b[0] => z[33]) = 0;
+		(b[1] => z[33]) = 0;
+		(b[2] => z[33]) = 0;
+		(b[3] => z[33]) = 0;
+		(b[4] => z[33]) = 0;
+		(b[5] => z[33]) = 0;
+		(b[6] => z[33]) = 0;
+		(b[7] => z[33]) = 0;
+		(b[8] => z[33]) = 0;
+		(b[9] => z[33]) = 0;
+		(b[10] => z[33]) = 0;
+		(b[11] => z[33]) = 0;
+		(b[12] => z[33]) = 0;
+		(b[13] => z[33]) = 0;
+		(b[14] => z[33]) = 0;
+		(b[15] => z[33]) = 0;
+		(b[16] => z[33]) = 0;
+		(b[17] => z[33]) = 0;
+		(a[0] => z[34]) = 0;
+		(a[1] => z[34]) = 0;
+		(a[2] => z[34]) = 0;
+		(a[3] => z[34]) = 0;
+		(a[4] => z[34]) = 0;
+		(a[5] => z[34]) = 0;
+		(a[6] => z[34]) = 0;
+		(a[7] => z[34]) = 0;
+		(a[8] => z[34]) = 0;
+		(a[9] => z[34]) = 0;
+		(a[10] => z[34]) = 0;
+		(a[11] => z[34]) = 0;
+		(a[12] => z[34]) = 0;
+		(a[13] => z[34]) = 0;
+		(a[14] => z[34]) = 0;
+		(a[15] => z[34]) = 0;
+		(a[16] => z[34]) = 0;
+		(a[17] => z[34]) = 0;
+		(a[18] => z[34]) = 0;
+		(a[19] => z[34]) = 0;
+		(b[0] => z[34]) = 0;
+		(b[1] => z[34]) = 0;
+		(b[2] => z[34]) = 0;
+		(b[3] => z[34]) = 0;
+		(b[4] => z[34]) = 0;
+		(b[5] => z[34]) = 0;
+		(b[6] => z[34]) = 0;
+		(b[7] => z[34]) = 0;
+		(b[8] => z[34]) = 0;
+		(b[9] => z[34]) = 0;
+		(b[10] => z[34]) = 0;
+		(b[11] => z[34]) = 0;
+		(b[12] => z[34]) = 0;
+		(b[13] => z[34]) = 0;
+		(b[14] => z[34]) = 0;
+		(b[15] => z[34]) = 0;
+		(b[16] => z[34]) = 0;
+		(b[17] => z[34]) = 0;
+		(a[0] => z[35]) = 0;
+		(a[1] => z[35]) = 0;
+		(a[2] => z[35]) = 0;
+		(a[3] => z[35]) = 0;
+		(a[4] => z[35]) = 0;
+		(a[5] => z[35]) = 0;
+		(a[6] => z[35]) = 0;
+		(a[7] => z[35]) = 0;
+		(a[8] => z[35]) = 0;
+		(a[9] => z[35]) = 0;
+		(a[10] => z[35]) = 0;
+		(a[11] => z[35]) = 0;
+		(a[12] => z[35]) = 0;
+		(a[13] => z[35]) = 0;
+		(a[14] => z[35]) = 0;
+		(a[15] => z[35]) = 0;
+		(a[16] => z[35]) = 0;
+		(a[17] => z[35]) = 0;
+		(a[18] => z[35]) = 0;
+		(a[19] => z[35]) = 0;
+		(b[0] => z[35]) = 0;
+		(b[1] => z[35]) = 0;
+		(b[2] => z[35]) = 0;
+		(b[3] => z[35]) = 0;
+		(b[4] => z[35]) = 0;
+		(b[5] => z[35]) = 0;
+		(b[6] => z[35]) = 0;
+		(b[7] => z[35]) = 0;
+		(b[8] => z[35]) = 0;
+		(b[9] => z[35]) = 0;
+		(b[10] => z[35]) = 0;
+		(b[11] => z[35]) = 0;
+		(b[12] => z[35]) = 0;
+		(b[13] => z[35]) = 0;
+		(b[14] => z[35]) = 0;
+		(b[15] => z[35]) = 0;
+		(b[16] => z[35]) = 0;
+		(b[17] => z[35]) = 0;
+		(a[0] => z[36]) = 0;
+		(a[1] => z[36]) = 0;
+		(a[2] => z[36]) = 0;
+		(a[3] => z[36]) = 0;
+		(a[4] => z[36]) = 0;
+		(a[5] => z[36]) = 0;
+		(a[6] => z[36]) = 0;
+		(a[7] => z[36]) = 0;
+		(a[8] => z[36]) = 0;
+		(a[9] => z[36]) = 0;
+		(a[10] => z[36]) = 0;
+		(a[11] => z[36]) = 0;
+		(a[12] => z[36]) = 0;
+		(a[13] => z[36]) = 0;
+		(a[14] => z[36]) = 0;
+		(a[15] => z[36]) = 0;
+		(a[16] => z[36]) = 0;
+		(a[17] => z[36]) = 0;
+		(a[18] => z[36]) = 0;
+		(a[19] => z[36]) = 0;
+		(b[0] => z[36]) = 0;
+		(b[1] => z[36]) = 0;
+		(b[2] => z[36]) = 0;
+		(b[3] => z[36]) = 0;
+		(b[4] => z[36]) = 0;
+		(b[5] => z[36]) = 0;
+		(b[6] => z[36]) = 0;
+		(b[7] => z[36]) = 0;
+		(b[8] => z[36]) = 0;
+		(b[9] => z[36]) = 0;
+		(b[10] => z[36]) = 0;
+		(b[11] => z[36]) = 0;
+		(b[12] => z[36]) = 0;
+		(b[13] => z[36]) = 0;
+		(b[14] => z[36]) = 0;
+		(b[15] => z[36]) = 0;
+		(b[16] => z[36]) = 0;
+		(b[17] => z[36]) = 0;
+		(a[0] => z[37]) = 0;
+		(a[1] => z[37]) = 0;
+		(a[2] => z[37]) = 0;
+		(a[3] => z[37]) = 0;
+		(a[4] => z[37]) = 0;
+		(a[5] => z[37]) = 0;
+		(a[6] => z[37]) = 0;
+		(a[7] => z[37]) = 0;
+		(a[8] => z[37]) = 0;
+		(a[9] => z[37]) = 0;
+		(a[10] => z[37]) = 0;
+		(a[11] => z[37]) = 0;
+		(a[12] => z[37]) = 0;
+		(a[13] => z[37]) = 0;
+		(a[14] => z[37]) = 0;
+		(a[15] => z[37]) = 0;
+		(a[16] => z[37]) = 0;
+		(a[17] => z[37]) = 0;
+		(a[18] => z[37]) = 0;
+		(a[19] => z[37]) = 0;
+		(b[0] => z[37]) = 0;
+		(b[1] => z[37]) = 0;
+		(b[2] => z[37]) = 0;
+		(b[3] => z[37]) = 0;
+		(b[4] => z[37]) = 0;
+		(b[5] => z[37]) = 0;
+		(b[6] => z[37]) = 0;
+		(b[7] => z[37]) = 0;
+		(b[8] => z[37]) = 0;
+		(b[9] => z[37]) = 0;
+		(b[10] => z[37]) = 0;
+		(b[11] => z[37]) = 0;
+		(b[12] => z[37]) = 0;
+		(b[13] => z[37]) = 0;
+		(b[14] => z[37]) = 0;
+		(b[15] => z[37]) = 0;
+		(b[16] => z[37]) = 0;
+		(b[17] => z[37]) = 0;
+	endspecify
+`endif
+
+endmodule
+
+module QL_DSP2_MULT_REGIN ( // TODO: Name subject to change
+	input  wire [19:0] a,
+	input  wire [17:0] b,
+	output wire [37:0] z,
+
+	(* clkbuf_sink *)
+	input  wire       clk,
+	input  wire       reset,
+
+	input  wire [2:0] feedback,
+	input  wire       unsigned_a,
+	input  wire       unsigned_b,
+
+	input  wire       f_mode,
+	input  wire [2:0] output_select,
+	input  wire       register_inputs
+);
+
+	parameter [79:0] MODE_BITS = 80'd0;
+
+	localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+	localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+	localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+	localparam [19:0] COEFF_3 = MODE_BITS[79:60];
+
+	QL_DSP2 #(
+		.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+	) dsp (
+		.a(a),
+		.b(b),
+		.acc_fir(6'b0),
+		.z(z),
+		.dly_b(),
+
+		.f_mode(f_mode),
+
+		.feedback(feedback),
+		.load_acc(1'b0),
+
+		.unsigned_a(unsigned_a),
+		.unsigned_b(unsigned_b),
+
+		.clk(clk),
+		.reset(reset),
+
+		.output_select(output_select),      // unregistered output: a * b (0)
+		.saturate_enable(1'b0),
+		.shift_right(6'b0),
+		.round(1'b0),
+		.subtract(1'b0),
+		.register_inputs(register_inputs)   // registered inputs
+	);
+
+`ifdef SDF_SIM
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module QL_DSP2_MULT_REGOUT ( // TODO: Name subject to change
+	input  wire [19:0] a,
+	input  wire [17:0] b,
+	output wire [37:0] z,
+
+	(* clkbuf_sink *)
+	input  wire       clk,
+	input  wire       reset,
+
+	input  wire [2:0] feedback,
+	input  wire       unsigned_a,
+	input  wire       unsigned_b,
+	input  wire       f_mode,
+	input  wire [2:0] output_select,
+	input  wire       register_inputs
+);
+
+	parameter [79:0] MODE_BITS = 80'd0;
+
+	localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+	localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+	localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+	localparam [19:0] COEFF_3 = MODE_BITS[79:60];
+
+	QL_DSP2 #(
+		.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+	) dsp (
+		.a(a),
+		.b(b),
+		.acc_fir(6'b0),
+		.z(z),
+		.dly_b(),
+
+		.f_mode(f_mode),
+
+		.feedback(feedback),
+		.load_acc(1'b0),
+
+		.unsigned_a(unsigned_a),
+		.unsigned_b(unsigned_b),
+
+		.clk(clk),
+		.reset(reset),
+
+		.output_select(output_select),      // registered output: a * b (4)
+		.saturate_enable(1'b0),
+		.shift_right(6'b0),
+		.round(1'b0),
+		.subtract(1'b0),
+		.register_inputs(register_inputs)   // unregistered inputs
+	);
+
+`ifdef SDF_SIM
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module QL_DSP2_MULT_REGIN_REGOUT ( // TODO: Name subject to change
+	input  wire [19:0] a,
+	input  wire [17:0] b,
+	output wire [37:0] z,
+
+	(* clkbuf_sink *)
+	input  wire       clk,
+	input  wire       reset,
+
+	input  wire [2:0] feedback,
+	input  wire       unsigned_a,
+	input  wire       unsigned_b,
+	input  wire       f_mode,
+	input  wire [2:0] output_select,
+	input  wire       register_inputs
+);
+
+	parameter [79:0] MODE_BITS = 80'd0;
+
+	localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+	localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+	localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+	localparam [19:0] COEFF_3 = MODE_BITS[79:60];
+
+	QL_DSP2 #(
+		.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+	) dsp (
+		.a(a),
+		.b(b),
+		.acc_fir(6'b0),
+		.z(z),
+		.dly_b(),
+
+		.f_mode(f_mode),
+
+		.feedback(feedback),
+		.load_acc(1'b0),
+
+		.unsigned_a(unsigned_a),
+		.unsigned_b(unsigned_b),
+
+		.clk(clk),
+		.reset(reset),
+
+		.output_select(output_select),      // registered output: a * b (4)
+		.saturate_enable(1'b0),
+		.shift_right(6'b0),
+		.round(1'b0),
+		.subtract(1'b0),
+		.register_inputs(register_inputs)   // registered inputs
+	);
+
+`ifdef SDF_SIM
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module QL_DSP2_MULTADD (
+	input  wire [19:0] a,
+	input  wire [17:0] b,
+	output wire [37:0] z,
+
+	input  wire        reset,
+
+	input  wire [ 2:0] feedback,
+	input  wire [ 5:0] acc_fir,
+	input  wire        load_acc,
+	input  wire        unsigned_a,
+	input  wire        unsigned_b,
+
+	input  wire        f_mode,
+	input  wire [ 2:0] output_select,
+	input  wire        saturate_enable,
+	input  wire [ 5:0] shift_right,
+	input  wire        round,
+	input  wire        subtract,
+	input  wire        register_inputs
+);
+
+	parameter [79:0] MODE_BITS = 80'd0;
+
+	localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+	localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+	localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+	localparam [19:0] COEFF_3 = MODE_BITS[79:60];
+
+	QL_DSP2 #(
+		.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+	) dsp (
+		.a(a),
+		.b(b),
+		.dly_b(),
+		.z(z),
+
+		.f_mode(f_mode),
+
+		.feedback(feedback),
+		.acc_fir(acc_fir),
+		.load_acc(load_acc),
+
+		.unsigned_a(unsigned_a),
+		.unsigned_b(unsigned_b),
+
+		//.clk(1'b0),
+		.reset(reset),
+
+		.output_select(output_select),      // unregistered output: ACCin (2, 3)
+		.saturate_enable(saturate_enable),
+		.shift_right(shift_right),
+		.round(round),
+		.subtract(subtract),
+		.register_inputs(register_inputs)   // unregistered inputs
+	);
+
+`ifdef SDF_SIM
+	specify
+		(a[0] => z[0]) = 0;
+		(a[1] => z[0]) = 0;
+		(a[2] => z[0]) = 0;
+		(a[3] => z[0]) = 0;
+		(a[4] => z[0]) = 0;
+		(a[5] => z[0]) = 0;
+		(a[6] => z[0]) = 0;
+		(a[7] => z[0]) = 0;
+		(a[8] => z[0]) = 0;
+		(a[9] => z[0]) = 0;
+		(a[10] => z[0]) = 0;
+		(a[11] => z[0]) = 0;
+		(a[12] => z[0]) = 0;
+		(a[13] => z[0]) = 0;
+		(a[14] => z[0]) = 0;
+		(a[15] => z[0]) = 0;
+		(a[16] => z[0]) = 0;
+		(a[17] => z[0]) = 0;
+		(a[18] => z[0]) = 0;
+		(a[19] => z[0]) = 0;
+		(b[0] => z[0]) = 0;
+		(b[1] => z[0]) = 0;
+		(b[2] => z[0]) = 0;
+		(b[3] => z[0]) = 0;
+		(b[4] => z[0]) = 0;
+		(b[5] => z[0]) = 0;
+		(b[6] => z[0]) = 0;
+		(b[7] => z[0]) = 0;
+		(b[8] => z[0]) = 0;
+		(b[9] => z[0]) = 0;
+		(b[10] => z[0]) = 0;
+		(b[11] => z[0]) = 0;
+		(b[12] => z[0]) = 0;
+		(b[13] => z[0]) = 0;
+		(b[14] => z[0]) = 0;
+		(b[15] => z[0]) = 0;
+		(b[16] => z[0]) = 0;
+		(b[17] => z[0]) = 0;
+		(a[0] => z[1]) = 0;
+		(a[1] => z[1]) = 0;
+		(a[2] => z[1]) = 0;
+		(a[3] => z[1]) = 0;
+		(a[4] => z[1]) = 0;
+		(a[5] => z[1]) = 0;
+		(a[6] => z[1]) = 0;
+		(a[7] => z[1]) = 0;
+		(a[8] => z[1]) = 0;
+		(a[9] => z[1]) = 0;
+		(a[10] => z[1]) = 0;
+		(a[11] => z[1]) = 0;
+		(a[12] => z[1]) = 0;
+		(a[13] => z[1]) = 0;
+		(a[14] => z[1]) = 0;
+		(a[15] => z[1]) = 0;
+		(a[16] => z[1]) = 0;
+		(a[17] => z[1]) = 0;
+		(a[18] => z[1]) = 0;
+		(a[19] => z[1]) = 0;
+		(b[0] => z[1]) = 0;
+		(b[1] => z[1]) = 0;
+		(b[2] => z[1]) = 0;
+		(b[3] => z[1]) = 0;
+		(b[4] => z[1]) = 0;
+		(b[5] => z[1]) = 0;
+		(b[6] => z[1]) = 0;
+		(b[7] => z[1]) = 0;
+		(b[8] => z[1]) = 0;
+		(b[9] => z[1]) = 0;
+		(b[10] => z[1]) = 0;
+		(b[11] => z[1]) = 0;
+		(b[12] => z[1]) = 0;
+		(b[13] => z[1]) = 0;
+		(b[14] => z[1]) = 0;
+		(b[15] => z[1]) = 0;
+		(b[16] => z[1]) = 0;
+		(b[17] => z[1]) = 0;
+		(a[0] => z[2]) = 0;
+		(a[1] => z[2]) = 0;
+		(a[2] => z[2]) = 0;
+		(a[3] => z[2]) = 0;
+		(a[4] => z[2]) = 0;
+		(a[5] => z[2]) = 0;
+		(a[6] => z[2]) = 0;
+		(a[7] => z[2]) = 0;
+		(a[8] => z[2]) = 0;
+		(a[9] => z[2]) = 0;
+		(a[10] => z[2]) = 0;
+		(a[11] => z[2]) = 0;
+		(a[12] => z[2]) = 0;
+		(a[13] => z[2]) = 0;
+		(a[14] => z[2]) = 0;
+		(a[15] => z[2]) = 0;
+		(a[16] => z[2]) = 0;
+		(a[17] => z[2]) = 0;
+		(a[18] => z[2]) = 0;
+		(a[19] => z[2]) = 0;
+		(b[0] => z[2]) = 0;
+		(b[1] => z[2]) = 0;
+		(b[2] => z[2]) = 0;
+		(b[3] => z[2]) = 0;
+		(b[4] => z[2]) = 0;
+		(b[5] => z[2]) = 0;
+		(b[6] => z[2]) = 0;
+		(b[7] => z[2]) = 0;
+		(b[8] => z[2]) = 0;
+		(b[9] => z[2]) = 0;
+		(b[10] => z[2]) = 0;
+		(b[11] => z[2]) = 0;
+		(b[12] => z[2]) = 0;
+		(b[13] => z[2]) = 0;
+		(b[14] => z[2]) = 0;
+		(b[15] => z[2]) = 0;
+		(b[16] => z[2]) = 0;
+		(b[17] => z[2]) = 0;
+		(a[0] => z[3]) = 0;
+		(a[1] => z[3]) = 0;
+		(a[2] => z[3]) = 0;
+		(a[3] => z[3]) = 0;
+		(a[4] => z[3]) = 0;
+		(a[5] => z[3]) = 0;
+		(a[6] => z[3]) = 0;
+		(a[7] => z[3]) = 0;
+		(a[8] => z[3]) = 0;
+		(a[9] => z[3]) = 0;
+		(a[10] => z[3]) = 0;
+		(a[11] => z[3]) = 0;
+		(a[12] => z[3]) = 0;
+		(a[13] => z[3]) = 0;
+		(a[14] => z[3]) = 0;
+		(a[15] => z[3]) = 0;
+		(a[16] => z[3]) = 0;
+		(a[17] => z[3]) = 0;
+		(a[18] => z[3]) = 0;
+		(a[19] => z[3]) = 0;
+		(b[0] => z[3]) = 0;
+		(b[1] => z[3]) = 0;
+		(b[2] => z[3]) = 0;
+		(b[3] => z[3]) = 0;
+		(b[4] => z[3]) = 0;
+		(b[5] => z[3]) = 0;
+		(b[6] => z[3]) = 0;
+		(b[7] => z[3]) = 0;
+		(b[8] => z[3]) = 0;
+		(b[9] => z[3]) = 0;
+		(b[10] => z[3]) = 0;
+		(b[11] => z[3]) = 0;
+		(b[12] => z[3]) = 0;
+		(b[13] => z[3]) = 0;
+		(b[14] => z[3]) = 0;
+		(b[15] => z[3]) = 0;
+		(b[16] => z[3]) = 0;
+		(b[17] => z[3]) = 0;
+		(a[0] => z[4]) = 0;
+		(a[1] => z[4]) = 0;
+		(a[2] => z[4]) = 0;
+		(a[3] => z[4]) = 0;
+		(a[4] => z[4]) = 0;
+		(a[5] => z[4]) = 0;
+		(a[6] => z[4]) = 0;
+		(a[7] => z[4]) = 0;
+		(a[8] => z[4]) = 0;
+		(a[9] => z[4]) = 0;
+		(a[10] => z[4]) = 0;
+		(a[11] => z[4]) = 0;
+		(a[12] => z[4]) = 0;
+		(a[13] => z[4]) = 0;
+		(a[14] => z[4]) = 0;
+		(a[15] => z[4]) = 0;
+		(a[16] => z[4]) = 0;
+		(a[17] => z[4]) = 0;
+		(a[18] => z[4]) = 0;
+		(a[19] => z[4]) = 0;
+		(b[0] => z[4]) = 0;
+		(b[1] => z[4]) = 0;
+		(b[2] => z[4]) = 0;
+		(b[3] => z[4]) = 0;
+		(b[4] => z[4]) = 0;
+		(b[5] => z[4]) = 0;
+		(b[6] => z[4]) = 0;
+		(b[7] => z[4]) = 0;
+		(b[8] => z[4]) = 0;
+		(b[9] => z[4]) = 0;
+		(b[10] => z[4]) = 0;
+		(b[11] => z[4]) = 0;
+		(b[12] => z[4]) = 0;
+		(b[13] => z[4]) = 0;
+		(b[14] => z[4]) = 0;
+		(b[15] => z[4]) = 0;
+		(b[16] => z[4]) = 0;
+		(b[17] => z[4]) = 0;
+		(a[0] => z[5]) = 0;
+		(a[1] => z[5]) = 0;
+		(a[2] => z[5]) = 0;
+		(a[3] => z[5]) = 0;
+		(a[4] => z[5]) = 0;
+		(a[5] => z[5]) = 0;
+		(a[6] => z[5]) = 0;
+		(a[7] => z[5]) = 0;
+		(a[8] => z[5]) = 0;
+		(a[9] => z[5]) = 0;
+		(a[10] => z[5]) = 0;
+		(a[11] => z[5]) = 0;
+		(a[12] => z[5]) = 0;
+		(a[13] => z[5]) = 0;
+		(a[14] => z[5]) = 0;
+		(a[15] => z[5]) = 0;
+		(a[16] => z[5]) = 0;
+		(a[17] => z[5]) = 0;
+		(a[18] => z[5]) = 0;
+		(a[19] => z[5]) = 0;
+		(b[0] => z[5]) = 0;
+		(b[1] => z[5]) = 0;
+		(b[2] => z[5]) = 0;
+		(b[3] => z[5]) = 0;
+		(b[4] => z[5]) = 0;
+		(b[5] => z[5]) = 0;
+		(b[6] => z[5]) = 0;
+		(b[7] => z[5]) = 0;
+		(b[8] => z[5]) = 0;
+		(b[9] => z[5]) = 0;
+		(b[10] => z[5]) = 0;
+		(b[11] => z[5]) = 0;
+		(b[12] => z[5]) = 0;
+		(b[13] => z[5]) = 0;
+		(b[14] => z[5]) = 0;
+		(b[15] => z[5]) = 0;
+		(b[16] => z[5]) = 0;
+		(b[17] => z[5]) = 0;
+		(a[0] => z[6]) = 0;
+		(a[1] => z[6]) = 0;
+		(a[2] => z[6]) = 0;
+		(a[3] => z[6]) = 0;
+		(a[4] => z[6]) = 0;
+		(a[5] => z[6]) = 0;
+		(a[6] => z[6]) = 0;
+		(a[7] => z[6]) = 0;
+		(a[8] => z[6]) = 0;
+		(a[9] => z[6]) = 0;
+		(a[10] => z[6]) = 0;
+		(a[11] => z[6]) = 0;
+		(a[12] => z[6]) = 0;
+		(a[13] => z[6]) = 0;
+		(a[14] => z[6]) = 0;
+		(a[15] => z[6]) = 0;
+		(a[16] => z[6]) = 0;
+		(a[17] => z[6]) = 0;
+		(a[18] => z[6]) = 0;
+		(a[19] => z[6]) = 0;
+		(b[0] => z[6]) = 0;
+		(b[1] => z[6]) = 0;
+		(b[2] => z[6]) = 0;
+		(b[3] => z[6]) = 0;
+		(b[4] => z[6]) = 0;
+		(b[5] => z[6]) = 0;
+		(b[6] => z[6]) = 0;
+		(b[7] => z[6]) = 0;
+		(b[8] => z[6]) = 0;
+		(b[9] => z[6]) = 0;
+		(b[10] => z[6]) = 0;
+		(b[11] => z[6]) = 0;
+		(b[12] => z[6]) = 0;
+		(b[13] => z[6]) = 0;
+		(b[14] => z[6]) = 0;
+		(b[15] => z[6]) = 0;
+		(b[16] => z[6]) = 0;
+		(b[17] => z[6]) = 0;
+		(a[0] => z[7]) = 0;
+		(a[1] => z[7]) = 0;
+		(a[2] => z[7]) = 0;
+		(a[3] => z[7]) = 0;
+		(a[4] => z[7]) = 0;
+		(a[5] => z[7]) = 0;
+		(a[6] => z[7]) = 0;
+		(a[7] => z[7]) = 0;
+		(a[8] => z[7]) = 0;
+		(a[9] => z[7]) = 0;
+		(a[10] => z[7]) = 0;
+		(a[11] => z[7]) = 0;
+		(a[12] => z[7]) = 0;
+		(a[13] => z[7]) = 0;
+		(a[14] => z[7]) = 0;
+		(a[15] => z[7]) = 0;
+		(a[16] => z[7]) = 0;
+		(a[17] => z[7]) = 0;
+		(a[18] => z[7]) = 0;
+		(a[19] => z[7]) = 0;
+		(b[0] => z[7]) = 0;
+		(b[1] => z[7]) = 0;
+		(b[2] => z[7]) = 0;
+		(b[3] => z[7]) = 0;
+		(b[4] => z[7]) = 0;
+		(b[5] => z[7]) = 0;
+		(b[6] => z[7]) = 0;
+		(b[7] => z[7]) = 0;
+		(b[8] => z[7]) = 0;
+		(b[9] => z[7]) = 0;
+		(b[10] => z[7]) = 0;
+		(b[11] => z[7]) = 0;
+		(b[12] => z[7]) = 0;
+		(b[13] => z[7]) = 0;
+		(b[14] => z[7]) = 0;
+		(b[15] => z[7]) = 0;
+		(b[16] => z[7]) = 0;
+		(b[17] => z[7]) = 0;
+		(a[0] => z[8]) = 0;
+		(a[1] => z[8]) = 0;
+		(a[2] => z[8]) = 0;
+		(a[3] => z[8]) = 0;
+		(a[4] => z[8]) = 0;
+		(a[5] => z[8]) = 0;
+		(a[6] => z[8]) = 0;
+		(a[7] => z[8]) = 0;
+		(a[8] => z[8]) = 0;
+		(a[9] => z[8]) = 0;
+		(a[10] => z[8]) = 0;
+		(a[11] => z[8]) = 0;
+		(a[12] => z[8]) = 0;
+		(a[13] => z[8]) = 0;
+		(a[14] => z[8]) = 0;
+		(a[15] => z[8]) = 0;
+		(a[16] => z[8]) = 0;
+		(a[17] => z[8]) = 0;
+		(a[18] => z[8]) = 0;
+		(a[19] => z[8]) = 0;
+		(b[0] => z[8]) = 0;
+		(b[1] => z[8]) = 0;
+		(b[2] => z[8]) = 0;
+		(b[3] => z[8]) = 0;
+		(b[4] => z[8]) = 0;
+		(b[5] => z[8]) = 0;
+		(b[6] => z[8]) = 0;
+		(b[7] => z[8]) = 0;
+		(b[8] => z[8]) = 0;
+		(b[9] => z[8]) = 0;
+		(b[10] => z[8]) = 0;
+		(b[11] => z[8]) = 0;
+		(b[12] => z[8]) = 0;
+		(b[13] => z[8]) = 0;
+		(b[14] => z[8]) = 0;
+		(b[15] => z[8]) = 0;
+		(b[16] => z[8]) = 0;
+		(b[17] => z[8]) = 0;
+		(a[0] => z[9]) = 0;
+		(a[1] => z[9]) = 0;
+		(a[2] => z[9]) = 0;
+		(a[3] => z[9]) = 0;
+		(a[4] => z[9]) = 0;
+		(a[5] => z[9]) = 0;
+		(a[6] => z[9]) = 0;
+		(a[7] => z[9]) = 0;
+		(a[8] => z[9]) = 0;
+		(a[9] => z[9]) = 0;
+		(a[10] => z[9]) = 0;
+		(a[11] => z[9]) = 0;
+		(a[12] => z[9]) = 0;
+		(a[13] => z[9]) = 0;
+		(a[14] => z[9]) = 0;
+		(a[15] => z[9]) = 0;
+		(a[16] => z[9]) = 0;
+		(a[17] => z[9]) = 0;
+		(a[18] => z[9]) = 0;
+		(a[19] => z[9]) = 0;
+		(b[0] => z[9]) = 0;
+		(b[1] => z[9]) = 0;
+		(b[2] => z[9]) = 0;
+		(b[3] => z[9]) = 0;
+		(b[4] => z[9]) = 0;
+		(b[5] => z[9]) = 0;
+		(b[6] => z[9]) = 0;
+		(b[7] => z[9]) = 0;
+		(b[8] => z[9]) = 0;
+		(b[9] => z[9]) = 0;
+		(b[10] => z[9]) = 0;
+		(b[11] => z[9]) = 0;
+		(b[12] => z[9]) = 0;
+		(b[13] => z[9]) = 0;
+		(b[14] => z[9]) = 0;
+		(b[15] => z[9]) = 0;
+		(b[16] => z[9]) = 0;
+		(b[17] => z[9]) = 0;
+		(a[0] => z[10]) = 0;
+		(a[1] => z[10]) = 0;
+		(a[2] => z[10]) = 0;
+		(a[3] => z[10]) = 0;
+		(a[4] => z[10]) = 0;
+		(a[5] => z[10]) = 0;
+		(a[6] => z[10]) = 0;
+		(a[7] => z[10]) = 0;
+		(a[8] => z[10]) = 0;
+		(a[9] => z[10]) = 0;
+		(a[10] => z[10]) = 0;
+		(a[11] => z[10]) = 0;
+		(a[12] => z[10]) = 0;
+		(a[13] => z[10]) = 0;
+		(a[14] => z[10]) = 0;
+		(a[15] => z[10]) = 0;
+		(a[16] => z[10]) = 0;
+		(a[17] => z[10]) = 0;
+		(a[18] => z[10]) = 0;
+		(a[19] => z[10]) = 0;
+		(b[0] => z[10]) = 0;
+		(b[1] => z[10]) = 0;
+		(b[2] => z[10]) = 0;
+		(b[3] => z[10]) = 0;
+		(b[4] => z[10]) = 0;
+		(b[5] => z[10]) = 0;
+		(b[6] => z[10]) = 0;
+		(b[7] => z[10]) = 0;
+		(b[8] => z[10]) = 0;
+		(b[9] => z[10]) = 0;
+		(b[10] => z[10]) = 0;
+		(b[11] => z[10]) = 0;
+		(b[12] => z[10]) = 0;
+		(b[13] => z[10]) = 0;
+		(b[14] => z[10]) = 0;
+		(b[15] => z[10]) = 0;
+		(b[16] => z[10]) = 0;
+		(b[17] => z[10]) = 0;
+		(a[0] => z[11]) = 0;
+		(a[1] => z[11]) = 0;
+		(a[2] => z[11]) = 0;
+		(a[3] => z[11]) = 0;
+		(a[4] => z[11]) = 0;
+		(a[5] => z[11]) = 0;
+		(a[6] => z[11]) = 0;
+		(a[7] => z[11]) = 0;
+		(a[8] => z[11]) = 0;
+		(a[9] => z[11]) = 0;
+		(a[10] => z[11]) = 0;
+		(a[11] => z[11]) = 0;
+		(a[12] => z[11]) = 0;
+		(a[13] => z[11]) = 0;
+		(a[14] => z[11]) = 0;
+		(a[15] => z[11]) = 0;
+		(a[16] => z[11]) = 0;
+		(a[17] => z[11]) = 0;
+		(a[18] => z[11]) = 0;
+		(a[19] => z[11]) = 0;
+		(b[0] => z[11]) = 0;
+		(b[1] => z[11]) = 0;
+		(b[2] => z[11]) = 0;
+		(b[3] => z[11]) = 0;
+		(b[4] => z[11]) = 0;
+		(b[5] => z[11]) = 0;
+		(b[6] => z[11]) = 0;
+		(b[7] => z[11]) = 0;
+		(b[8] => z[11]) = 0;
+		(b[9] => z[11]) = 0;
+		(b[10] => z[11]) = 0;
+		(b[11] => z[11]) = 0;
+		(b[12] => z[11]) = 0;
+		(b[13] => z[11]) = 0;
+		(b[14] => z[11]) = 0;
+		(b[15] => z[11]) = 0;
+		(b[16] => z[11]) = 0;
+		(b[17] => z[11]) = 0;
+		(a[0] => z[12]) = 0;
+		(a[1] => z[12]) = 0;
+		(a[2] => z[12]) = 0;
+		(a[3] => z[12]) = 0;
+		(a[4] => z[12]) = 0;
+		(a[5] => z[12]) = 0;
+		(a[6] => z[12]) = 0;
+		(a[7] => z[12]) = 0;
+		(a[8] => z[12]) = 0;
+		(a[9] => z[12]) = 0;
+		(a[10] => z[12]) = 0;
+		(a[11] => z[12]) = 0;
+		(a[12] => z[12]) = 0;
+		(a[13] => z[12]) = 0;
+		(a[14] => z[12]) = 0;
+		(a[15] => z[12]) = 0;
+		(a[16] => z[12]) = 0;
+		(a[17] => z[12]) = 0;
+		(a[18] => z[12]) = 0;
+		(a[19] => z[12]) = 0;
+		(b[0] => z[12]) = 0;
+		(b[1] => z[12]) = 0;
+		(b[2] => z[12]) = 0;
+		(b[3] => z[12]) = 0;
+		(b[4] => z[12]) = 0;
+		(b[5] => z[12]) = 0;
+		(b[6] => z[12]) = 0;
+		(b[7] => z[12]) = 0;
+		(b[8] => z[12]) = 0;
+		(b[9] => z[12]) = 0;
+		(b[10] => z[12]) = 0;
+		(b[11] => z[12]) = 0;
+		(b[12] => z[12]) = 0;
+		(b[13] => z[12]) = 0;
+		(b[14] => z[12]) = 0;
+		(b[15] => z[12]) = 0;
+		(b[16] => z[12]) = 0;
+		(b[17] => z[12]) = 0;
+		(a[0] => z[13]) = 0;
+		(a[1] => z[13]) = 0;
+		(a[2] => z[13]) = 0;
+		(a[3] => z[13]) = 0;
+		(a[4] => z[13]) = 0;
+		(a[5] => z[13]) = 0;
+		(a[6] => z[13]) = 0;
+		(a[7] => z[13]) = 0;
+		(a[8] => z[13]) = 0;
+		(a[9] => z[13]) = 0;
+		(a[10] => z[13]) = 0;
+		(a[11] => z[13]) = 0;
+		(a[12] => z[13]) = 0;
+		(a[13] => z[13]) = 0;
+		(a[14] => z[13]) = 0;
+		(a[15] => z[13]) = 0;
+		(a[16] => z[13]) = 0;
+		(a[17] => z[13]) = 0;
+		(a[18] => z[13]) = 0;
+		(a[19] => z[13]) = 0;
+		(b[0] => z[13]) = 0;
+		(b[1] => z[13]) = 0;
+		(b[2] => z[13]) = 0;
+		(b[3] => z[13]) = 0;
+		(b[4] => z[13]) = 0;
+		(b[5] => z[13]) = 0;
+		(b[6] => z[13]) = 0;
+		(b[7] => z[13]) = 0;
+		(b[8] => z[13]) = 0;
+		(b[9] => z[13]) = 0;
+		(b[10] => z[13]) = 0;
+		(b[11] => z[13]) = 0;
+		(b[12] => z[13]) = 0;
+		(b[13] => z[13]) = 0;
+		(b[14] => z[13]) = 0;
+		(b[15] => z[13]) = 0;
+		(b[16] => z[13]) = 0;
+		(b[17] => z[13]) = 0;
+		(a[0] => z[14]) = 0;
+		(a[1] => z[14]) = 0;
+		(a[2] => z[14]) = 0;
+		(a[3] => z[14]) = 0;
+		(a[4] => z[14]) = 0;
+		(a[5] => z[14]) = 0;
+		(a[6] => z[14]) = 0;
+		(a[7] => z[14]) = 0;
+		(a[8] => z[14]) = 0;
+		(a[9] => z[14]) = 0;
+		(a[10] => z[14]) = 0;
+		(a[11] => z[14]) = 0;
+		(a[12] => z[14]) = 0;
+		(a[13] => z[14]) = 0;
+		(a[14] => z[14]) = 0;
+		(a[15] => z[14]) = 0;
+		(a[16] => z[14]) = 0;
+		(a[17] => z[14]) = 0;
+		(a[18] => z[14]) = 0;
+		(a[19] => z[14]) = 0;
+		(b[0] => z[14]) = 0;
+		(b[1] => z[14]) = 0;
+		(b[2] => z[14]) = 0;
+		(b[3] => z[14]) = 0;
+		(b[4] => z[14]) = 0;
+		(b[5] => z[14]) = 0;
+		(b[6] => z[14]) = 0;
+		(b[7] => z[14]) = 0;
+		(b[8] => z[14]) = 0;
+		(b[9] => z[14]) = 0;
+		(b[10] => z[14]) = 0;
+		(b[11] => z[14]) = 0;
+		(b[12] => z[14]) = 0;
+		(b[13] => z[14]) = 0;
+		(b[14] => z[14]) = 0;
+		(b[15] => z[14]) = 0;
+		(b[16] => z[14]) = 0;
+		(b[17] => z[14]) = 0;
+		(a[0] => z[15]) = 0;
+		(a[1] => z[15]) = 0;
+		(a[2] => z[15]) = 0;
+		(a[3] => z[15]) = 0;
+		(a[4] => z[15]) = 0;
+		(a[5] => z[15]) = 0;
+		(a[6] => z[15]) = 0;
+		(a[7] => z[15]) = 0;
+		(a[8] => z[15]) = 0;
+		(a[9] => z[15]) = 0;
+		(a[10] => z[15]) = 0;
+		(a[11] => z[15]) = 0;
+		(a[12] => z[15]) = 0;
+		(a[13] => z[15]) = 0;
+		(a[14] => z[15]) = 0;
+		(a[15] => z[15]) = 0;
+		(a[16] => z[15]) = 0;
+		(a[17] => z[15]) = 0;
+		(a[18] => z[15]) = 0;
+		(a[19] => z[15]) = 0;
+		(b[0] => z[15]) = 0;
+		(b[1] => z[15]) = 0;
+		(b[2] => z[15]) = 0;
+		(b[3] => z[15]) = 0;
+		(b[4] => z[15]) = 0;
+		(b[5] => z[15]) = 0;
+		(b[6] => z[15]) = 0;
+		(b[7] => z[15]) = 0;
+		(b[8] => z[15]) = 0;
+		(b[9] => z[15]) = 0;
+		(b[10] => z[15]) = 0;
+		(b[11] => z[15]) = 0;
+		(b[12] => z[15]) = 0;
+		(b[13] => z[15]) = 0;
+		(b[14] => z[15]) = 0;
+		(b[15] => z[15]) = 0;
+		(b[16] => z[15]) = 0;
+		(b[17] => z[15]) = 0;
+		(a[0] => z[16]) = 0;
+		(a[1] => z[16]) = 0;
+		(a[2] => z[16]) = 0;
+		(a[3] => z[16]) = 0;
+		(a[4] => z[16]) = 0;
+		(a[5] => z[16]) = 0;
+		(a[6] => z[16]) = 0;
+		(a[7] => z[16]) = 0;
+		(a[8] => z[16]) = 0;
+		(a[9] => z[16]) = 0;
+		(a[10] => z[16]) = 0;
+		(a[11] => z[16]) = 0;
+		(a[12] => z[16]) = 0;
+		(a[13] => z[16]) = 0;
+		(a[14] => z[16]) = 0;
+		(a[15] => z[16]) = 0;
+		(a[16] => z[16]) = 0;
+		(a[17] => z[16]) = 0;
+		(a[18] => z[16]) = 0;
+		(a[19] => z[16]) = 0;
+		(b[0] => z[16]) = 0;
+		(b[1] => z[16]) = 0;
+		(b[2] => z[16]) = 0;
+		(b[3] => z[16]) = 0;
+		(b[4] => z[16]) = 0;
+		(b[5] => z[16]) = 0;
+		(b[6] => z[16]) = 0;
+		(b[7] => z[16]) = 0;
+		(b[8] => z[16]) = 0;
+		(b[9] => z[16]) = 0;
+		(b[10] => z[16]) = 0;
+		(b[11] => z[16]) = 0;
+		(b[12] => z[16]) = 0;
+		(b[13] => z[16]) = 0;
+		(b[14] => z[16]) = 0;
+		(b[15] => z[16]) = 0;
+		(b[16] => z[16]) = 0;
+		(b[17] => z[16]) = 0;
+		(a[0] => z[17]) = 0;
+		(a[1] => z[17]) = 0;
+		(a[2] => z[17]) = 0;
+		(a[3] => z[17]) = 0;
+		(a[4] => z[17]) = 0;
+		(a[5] => z[17]) = 0;
+		(a[6] => z[17]) = 0;
+		(a[7] => z[17]) = 0;
+		(a[8] => z[17]) = 0;
+		(a[9] => z[17]) = 0;
+		(a[10] => z[17]) = 0;
+		(a[11] => z[17]) = 0;
+		(a[12] => z[17]) = 0;
+		(a[13] => z[17]) = 0;
+		(a[14] => z[17]) = 0;
+		(a[15] => z[17]) = 0;
+		(a[16] => z[17]) = 0;
+		(a[17] => z[17]) = 0;
+		(a[18] => z[17]) = 0;
+		(a[19] => z[17]) = 0;
+		(b[0] => z[17]) = 0;
+		(b[1] => z[17]) = 0;
+		(b[2] => z[17]) = 0;
+		(b[3] => z[17]) = 0;
+		(b[4] => z[17]) = 0;
+		(b[5] => z[17]) = 0;
+		(b[6] => z[17]) = 0;
+		(b[7] => z[17]) = 0;
+		(b[8] => z[17]) = 0;
+		(b[9] => z[17]) = 0;
+		(b[10] => z[17]) = 0;
+		(b[11] => z[17]) = 0;
+		(b[12] => z[17]) = 0;
+		(b[13] => z[17]) = 0;
+		(b[14] => z[17]) = 0;
+		(b[15] => z[17]) = 0;
+		(b[16] => z[17]) = 0;
+		(b[17] => z[17]) = 0;
+		(a[0] => z[18]) = 0;
+		(a[1] => z[18]) = 0;
+		(a[2] => z[18]) = 0;
+		(a[3] => z[18]) = 0;
+		(a[4] => z[18]) = 0;
+		(a[5] => z[18]) = 0;
+		(a[6] => z[18]) = 0;
+		(a[7] => z[18]) = 0;
+		(a[8] => z[18]) = 0;
+		(a[9] => z[18]) = 0;
+		(a[10] => z[18]) = 0;
+		(a[11] => z[18]) = 0;
+		(a[12] => z[18]) = 0;
+		(a[13] => z[18]) = 0;
+		(a[14] => z[18]) = 0;
+		(a[15] => z[18]) = 0;
+		(a[16] => z[18]) = 0;
+		(a[17] => z[18]) = 0;
+		(a[18] => z[18]) = 0;
+		(a[19] => z[18]) = 0;
+		(b[0] => z[18]) = 0;
+		(b[1] => z[18]) = 0;
+		(b[2] => z[18]) = 0;
+		(b[3] => z[18]) = 0;
+		(b[4] => z[18]) = 0;
+		(b[5] => z[18]) = 0;
+		(b[6] => z[18]) = 0;
+		(b[7] => z[18]) = 0;
+		(b[8] => z[18]) = 0;
+		(b[9] => z[18]) = 0;
+		(b[10] => z[18]) = 0;
+		(b[11] => z[18]) = 0;
+		(b[12] => z[18]) = 0;
+		(b[13] => z[18]) = 0;
+		(b[14] => z[18]) = 0;
+		(b[15] => z[18]) = 0;
+		(b[16] => z[18]) = 0;
+		(b[17] => z[18]) = 0;
+		(a[0] => z[19]) = 0;
+		(a[1] => z[19]) = 0;
+		(a[2] => z[19]) = 0;
+		(a[3] => z[19]) = 0;
+		(a[4] => z[19]) = 0;
+		(a[5] => z[19]) = 0;
+		(a[6] => z[19]) = 0;
+		(a[7] => z[19]) = 0;
+		(a[8] => z[19]) = 0;
+		(a[9] => z[19]) = 0;
+		(a[10] => z[19]) = 0;
+		(a[11] => z[19]) = 0;
+		(a[12] => z[19]) = 0;
+		(a[13] => z[19]) = 0;
+		(a[14] => z[19]) = 0;
+		(a[15] => z[19]) = 0;
+		(a[16] => z[19]) = 0;
+		(a[17] => z[19]) = 0;
+		(a[18] => z[19]) = 0;
+		(a[19] => z[19]) = 0;
+		(b[0] => z[19]) = 0;
+		(b[1] => z[19]) = 0;
+		(b[2] => z[19]) = 0;
+		(b[3] => z[19]) = 0;
+		(b[4] => z[19]) = 0;
+		(b[5] => z[19]) = 0;
+		(b[6] => z[19]) = 0;
+		(b[7] => z[19]) = 0;
+		(b[8] => z[19]) = 0;
+		(b[9] => z[19]) = 0;
+		(b[10] => z[19]) = 0;
+		(b[11] => z[19]) = 0;
+		(b[12] => z[19]) = 0;
+		(b[13] => z[19]) = 0;
+		(b[14] => z[19]) = 0;
+		(b[15] => z[19]) = 0;
+		(b[16] => z[19]) = 0;
+		(b[17] => z[19]) = 0;
+		(a[0] => z[20]) = 0;
+		(a[1] => z[20]) = 0;
+		(a[2] => z[20]) = 0;
+		(a[3] => z[20]) = 0;
+		(a[4] => z[20]) = 0;
+		(a[5] => z[20]) = 0;
+		(a[6] => z[20]) = 0;
+		(a[7] => z[20]) = 0;
+		(a[8] => z[20]) = 0;
+		(a[9] => z[20]) = 0;
+		(a[10] => z[20]) = 0;
+		(a[11] => z[20]) = 0;
+		(a[12] => z[20]) = 0;
+		(a[13] => z[20]) = 0;
+		(a[14] => z[20]) = 0;
+		(a[15] => z[20]) = 0;
+		(a[16] => z[20]) = 0;
+		(a[17] => z[20]) = 0;
+		(a[18] => z[20]) = 0;
+		(a[19] => z[20]) = 0;
+		(b[0] => z[20]) = 0;
+		(b[1] => z[20]) = 0;
+		(b[2] => z[20]) = 0;
+		(b[3] => z[20]) = 0;
+		(b[4] => z[20]) = 0;
+		(b[5] => z[20]) = 0;
+		(b[6] => z[20]) = 0;
+		(b[7] => z[20]) = 0;
+		(b[8] => z[20]) = 0;
+		(b[9] => z[20]) = 0;
+		(b[10] => z[20]) = 0;
+		(b[11] => z[20]) = 0;
+		(b[12] => z[20]) = 0;
+		(b[13] => z[20]) = 0;
+		(b[14] => z[20]) = 0;
+		(b[15] => z[20]) = 0;
+		(b[16] => z[20]) = 0;
+		(b[17] => z[20]) = 0;
+		(a[0] => z[21]) = 0;
+		(a[1] => z[21]) = 0;
+		(a[2] => z[21]) = 0;
+		(a[3] => z[21]) = 0;
+		(a[4] => z[21]) = 0;
+		(a[5] => z[21]) = 0;
+		(a[6] => z[21]) = 0;
+		(a[7] => z[21]) = 0;
+		(a[8] => z[21]) = 0;
+		(a[9] => z[21]) = 0;
+		(a[10] => z[21]) = 0;
+		(a[11] => z[21]) = 0;
+		(a[12] => z[21]) = 0;
+		(a[13] => z[21]) = 0;
+		(a[14] => z[21]) = 0;
+		(a[15] => z[21]) = 0;
+		(a[16] => z[21]) = 0;
+		(a[17] => z[21]) = 0;
+		(a[18] => z[21]) = 0;
+		(a[19] => z[21]) = 0;
+		(b[0] => z[21]) = 0;
+		(b[1] => z[21]) = 0;
+		(b[2] => z[21]) = 0;
+		(b[3] => z[21]) = 0;
+		(b[4] => z[21]) = 0;
+		(b[5] => z[21]) = 0;
+		(b[6] => z[21]) = 0;
+		(b[7] => z[21]) = 0;
+		(b[8] => z[21]) = 0;
+		(b[9] => z[21]) = 0;
+		(b[10] => z[21]) = 0;
+		(b[11] => z[21]) = 0;
+		(b[12] => z[21]) = 0;
+		(b[13] => z[21]) = 0;
+		(b[14] => z[21]) = 0;
+		(b[15] => z[21]) = 0;
+		(b[16] => z[21]) = 0;
+		(b[17] => z[21]) = 0;
+		(a[0] => z[22]) = 0;
+		(a[1] => z[22]) = 0;
+		(a[2] => z[22]) = 0;
+		(a[3] => z[22]) = 0;
+		(a[4] => z[22]) = 0;
+		(a[5] => z[22]) = 0;
+		(a[6] => z[22]) = 0;
+		(a[7] => z[22]) = 0;
+		(a[8] => z[22]) = 0;
+		(a[9] => z[22]) = 0;
+		(a[10] => z[22]) = 0;
+		(a[11] => z[22]) = 0;
+		(a[12] => z[22]) = 0;
+		(a[13] => z[22]) = 0;
+		(a[14] => z[22]) = 0;
+		(a[15] => z[22]) = 0;
+		(a[16] => z[22]) = 0;
+		(a[17] => z[22]) = 0;
+		(a[18] => z[22]) = 0;
+		(a[19] => z[22]) = 0;
+		(b[0] => z[22]) = 0;
+		(b[1] => z[22]) = 0;
+		(b[2] => z[22]) = 0;
+		(b[3] => z[22]) = 0;
+		(b[4] => z[22]) = 0;
+		(b[5] => z[22]) = 0;
+		(b[6] => z[22]) = 0;
+		(b[7] => z[22]) = 0;
+		(b[8] => z[22]) = 0;
+		(b[9] => z[22]) = 0;
+		(b[10] => z[22]) = 0;
+		(b[11] => z[22]) = 0;
+		(b[12] => z[22]) = 0;
+		(b[13] => z[22]) = 0;
+		(b[14] => z[22]) = 0;
+		(b[15] => z[22]) = 0;
+		(b[16] => z[22]) = 0;
+		(b[17] => z[22]) = 0;
+		(a[0] => z[23]) = 0;
+		(a[1] => z[23]) = 0;
+		(a[2] => z[23]) = 0;
+		(a[3] => z[23]) = 0;
+		(a[4] => z[23]) = 0;
+		(a[5] => z[23]) = 0;
+		(a[6] => z[23]) = 0;
+		(a[7] => z[23]) = 0;
+		(a[8] => z[23]) = 0;
+		(a[9] => z[23]) = 0;
+		(a[10] => z[23]) = 0;
+		(a[11] => z[23]) = 0;
+		(a[12] => z[23]) = 0;
+		(a[13] => z[23]) = 0;
+		(a[14] => z[23]) = 0;
+		(a[15] => z[23]) = 0;
+		(a[16] => z[23]) = 0;
+		(a[17] => z[23]) = 0;
+		(a[18] => z[23]) = 0;
+		(a[19] => z[23]) = 0;
+		(b[0] => z[23]) = 0;
+		(b[1] => z[23]) = 0;
+		(b[2] => z[23]) = 0;
+		(b[3] => z[23]) = 0;
+		(b[4] => z[23]) = 0;
+		(b[5] => z[23]) = 0;
+		(b[6] => z[23]) = 0;
+		(b[7] => z[23]) = 0;
+		(b[8] => z[23]) = 0;
+		(b[9] => z[23]) = 0;
+		(b[10] => z[23]) = 0;
+		(b[11] => z[23]) = 0;
+		(b[12] => z[23]) = 0;
+		(b[13] => z[23]) = 0;
+		(b[14] => z[23]) = 0;
+		(b[15] => z[23]) = 0;
+		(b[16] => z[23]) = 0;
+		(b[17] => z[23]) = 0;
+		(a[0] => z[24]) = 0;
+		(a[1] => z[24]) = 0;
+		(a[2] => z[24]) = 0;
+		(a[3] => z[24]) = 0;
+		(a[4] => z[24]) = 0;
+		(a[5] => z[24]) = 0;
+		(a[6] => z[24]) = 0;
+		(a[7] => z[24]) = 0;
+		(a[8] => z[24]) = 0;
+		(a[9] => z[24]) = 0;
+		(a[10] => z[24]) = 0;
+		(a[11] => z[24]) = 0;
+		(a[12] => z[24]) = 0;
+		(a[13] => z[24]) = 0;
+		(a[14] => z[24]) = 0;
+		(a[15] => z[24]) = 0;
+		(a[16] => z[24]) = 0;
+		(a[17] => z[24]) = 0;
+		(a[18] => z[24]) = 0;
+		(a[19] => z[24]) = 0;
+		(b[0] => z[24]) = 0;
+		(b[1] => z[24]) = 0;
+		(b[2] => z[24]) = 0;
+		(b[3] => z[24]) = 0;
+		(b[4] => z[24]) = 0;
+		(b[5] => z[24]) = 0;
+		(b[6] => z[24]) = 0;
+		(b[7] => z[24]) = 0;
+		(b[8] => z[24]) = 0;
+		(b[9] => z[24]) = 0;
+		(b[10] => z[24]) = 0;
+		(b[11] => z[24]) = 0;
+		(b[12] => z[24]) = 0;
+		(b[13] => z[24]) = 0;
+		(b[14] => z[24]) = 0;
+		(b[15] => z[24]) = 0;
+		(b[16] => z[24]) = 0;
+		(b[17] => z[24]) = 0;
+		(a[0] => z[25]) = 0;
+		(a[1] => z[25]) = 0;
+		(a[2] => z[25]) = 0;
+		(a[3] => z[25]) = 0;
+		(a[4] => z[25]) = 0;
+		(a[5] => z[25]) = 0;
+		(a[6] => z[25]) = 0;
+		(a[7] => z[25]) = 0;
+		(a[8] => z[25]) = 0;
+		(a[9] => z[25]) = 0;
+		(a[10] => z[25]) = 0;
+		(a[11] => z[25]) = 0;
+		(a[12] => z[25]) = 0;
+		(a[13] => z[25]) = 0;
+		(a[14] => z[25]) = 0;
+		(a[15] => z[25]) = 0;
+		(a[16] => z[25]) = 0;
+		(a[17] => z[25]) = 0;
+		(a[18] => z[25]) = 0;
+		(a[19] => z[25]) = 0;
+		(b[0] => z[25]) = 0;
+		(b[1] => z[25]) = 0;
+		(b[2] => z[25]) = 0;
+		(b[3] => z[25]) = 0;
+		(b[4] => z[25]) = 0;
+		(b[5] => z[25]) = 0;
+		(b[6] => z[25]) = 0;
+		(b[7] => z[25]) = 0;
+		(b[8] => z[25]) = 0;
+		(b[9] => z[25]) = 0;
+		(b[10] => z[25]) = 0;
+		(b[11] => z[25]) = 0;
+		(b[12] => z[25]) = 0;
+		(b[13] => z[25]) = 0;
+		(b[14] => z[25]) = 0;
+		(b[15] => z[25]) = 0;
+		(b[16] => z[25]) = 0;
+		(b[17] => z[25]) = 0;
+		(a[0] => z[26]) = 0;
+		(a[1] => z[26]) = 0;
+		(a[2] => z[26]) = 0;
+		(a[3] => z[26]) = 0;
+		(a[4] => z[26]) = 0;
+		(a[5] => z[26]) = 0;
+		(a[6] => z[26]) = 0;
+		(a[7] => z[26]) = 0;
+		(a[8] => z[26]) = 0;
+		(a[9] => z[26]) = 0;
+		(a[10] => z[26]) = 0;
+		(a[11] => z[26]) = 0;
+		(a[12] => z[26]) = 0;
+		(a[13] => z[26]) = 0;
+		(a[14] => z[26]) = 0;
+		(a[15] => z[26]) = 0;
+		(a[16] => z[26]) = 0;
+		(a[17] => z[26]) = 0;
+		(a[18] => z[26]) = 0;
+		(a[19] => z[26]) = 0;
+		(b[0] => z[26]) = 0;
+		(b[1] => z[26]) = 0;
+		(b[2] => z[26]) = 0;
+		(b[3] => z[26]) = 0;
+		(b[4] => z[26]) = 0;
+		(b[5] => z[26]) = 0;
+		(b[6] => z[26]) = 0;
+		(b[7] => z[26]) = 0;
+		(b[8] => z[26]) = 0;
+		(b[9] => z[26]) = 0;
+		(b[10] => z[26]) = 0;
+		(b[11] => z[26]) = 0;
+		(b[12] => z[26]) = 0;
+		(b[13] => z[26]) = 0;
+		(b[14] => z[26]) = 0;
+		(b[15] => z[26]) = 0;
+		(b[16] => z[26]) = 0;
+		(b[17] => z[26]) = 0;
+		(a[0] => z[27]) = 0;
+		(a[1] => z[27]) = 0;
+		(a[2] => z[27]) = 0;
+		(a[3] => z[27]) = 0;
+		(a[4] => z[27]) = 0;
+		(a[5] => z[27]) = 0;
+		(a[6] => z[27]) = 0;
+		(a[7] => z[27]) = 0;
+		(a[8] => z[27]) = 0;
+		(a[9] => z[27]) = 0;
+		(a[10] => z[27]) = 0;
+		(a[11] => z[27]) = 0;
+		(a[12] => z[27]) = 0;
+		(a[13] => z[27]) = 0;
+		(a[14] => z[27]) = 0;
+		(a[15] => z[27]) = 0;
+		(a[16] => z[27]) = 0;
+		(a[17] => z[27]) = 0;
+		(a[18] => z[27]) = 0;
+		(a[19] => z[27]) = 0;
+		(b[0] => z[27]) = 0;
+		(b[1] => z[27]) = 0;
+		(b[2] => z[27]) = 0;
+		(b[3] => z[27]) = 0;
+		(b[4] => z[27]) = 0;
+		(b[5] => z[27]) = 0;
+		(b[6] => z[27]) = 0;
+		(b[7] => z[27]) = 0;
+		(b[8] => z[27]) = 0;
+		(b[9] => z[27]) = 0;
+		(b[10] => z[27]) = 0;
+		(b[11] => z[27]) = 0;
+		(b[12] => z[27]) = 0;
+		(b[13] => z[27]) = 0;
+		(b[14] => z[27]) = 0;
+		(b[15] => z[27]) = 0;
+		(b[16] => z[27]) = 0;
+		(b[17] => z[27]) = 0;
+		(a[0] => z[28]) = 0;
+		(a[1] => z[28]) = 0;
+		(a[2] => z[28]) = 0;
+		(a[3] => z[28]) = 0;
+		(a[4] => z[28]) = 0;
+		(a[5] => z[28]) = 0;
+		(a[6] => z[28]) = 0;
+		(a[7] => z[28]) = 0;
+		(a[8] => z[28]) = 0;
+		(a[9] => z[28]) = 0;
+		(a[10] => z[28]) = 0;
+		(a[11] => z[28]) = 0;
+		(a[12] => z[28]) = 0;
+		(a[13] => z[28]) = 0;
+		(a[14] => z[28]) = 0;
+		(a[15] => z[28]) = 0;
+		(a[16] => z[28]) = 0;
+		(a[17] => z[28]) = 0;
+		(a[18] => z[28]) = 0;
+		(a[19] => z[28]) = 0;
+		(b[0] => z[28]) = 0;
+		(b[1] => z[28]) = 0;
+		(b[2] => z[28]) = 0;
+		(b[3] => z[28]) = 0;
+		(b[4] => z[28]) = 0;
+		(b[5] => z[28]) = 0;
+		(b[6] => z[28]) = 0;
+		(b[7] => z[28]) = 0;
+		(b[8] => z[28]) = 0;
+		(b[9] => z[28]) = 0;
+		(b[10] => z[28]) = 0;
+		(b[11] => z[28]) = 0;
+		(b[12] => z[28]) = 0;
+		(b[13] => z[28]) = 0;
+		(b[14] => z[28]) = 0;
+		(b[15] => z[28]) = 0;
+		(b[16] => z[28]) = 0;
+		(b[17] => z[28]) = 0;
+		(a[0] => z[29]) = 0;
+		(a[1] => z[29]) = 0;
+		(a[2] => z[29]) = 0;
+		(a[3] => z[29]) = 0;
+		(a[4] => z[29]) = 0;
+		(a[5] => z[29]) = 0;
+		(a[6] => z[29]) = 0;
+		(a[7] => z[29]) = 0;
+		(a[8] => z[29]) = 0;
+		(a[9] => z[29]) = 0;
+		(a[10] => z[29]) = 0;
+		(a[11] => z[29]) = 0;
+		(a[12] => z[29]) = 0;
+		(a[13] => z[29]) = 0;
+		(a[14] => z[29]) = 0;
+		(a[15] => z[29]) = 0;
+		(a[16] => z[29]) = 0;
+		(a[17] => z[29]) = 0;
+		(a[18] => z[29]) = 0;
+		(a[19] => z[29]) = 0;
+		(b[0] => z[29]) = 0;
+		(b[1] => z[29]) = 0;
+		(b[2] => z[29]) = 0;
+		(b[3] => z[29]) = 0;
+		(b[4] => z[29]) = 0;
+		(b[5] => z[29]) = 0;
+		(b[6] => z[29]) = 0;
+		(b[7] => z[29]) = 0;
+		(b[8] => z[29]) = 0;
+		(b[9] => z[29]) = 0;
+		(b[10] => z[29]) = 0;
+		(b[11] => z[29]) = 0;
+		(b[12] => z[29]) = 0;
+		(b[13] => z[29]) = 0;
+		(b[14] => z[29]) = 0;
+		(b[15] => z[29]) = 0;
+		(b[16] => z[29]) = 0;
+		(b[17] => z[29]) = 0;
+		(a[0] => z[30]) = 0;
+		(a[1] => z[30]) = 0;
+		(a[2] => z[30]) = 0;
+		(a[3] => z[30]) = 0;
+		(a[4] => z[30]) = 0;
+		(a[5] => z[30]) = 0;
+		(a[6] => z[30]) = 0;
+		(a[7] => z[30]) = 0;
+		(a[8] => z[30]) = 0;
+		(a[9] => z[30]) = 0;
+		(a[10] => z[30]) = 0;
+		(a[11] => z[30]) = 0;
+		(a[12] => z[30]) = 0;
+		(a[13] => z[30]) = 0;
+		(a[14] => z[30]) = 0;
+		(a[15] => z[30]) = 0;
+		(a[16] => z[30]) = 0;
+		(a[17] => z[30]) = 0;
+		(a[18] => z[30]) = 0;
+		(a[19] => z[30]) = 0;
+		(b[0] => z[30]) = 0;
+		(b[1] => z[30]) = 0;
+		(b[2] => z[30]) = 0;
+		(b[3] => z[30]) = 0;
+		(b[4] => z[30]) = 0;
+		(b[5] => z[30]) = 0;
+		(b[6] => z[30]) = 0;
+		(b[7] => z[30]) = 0;
+		(b[8] => z[30]) = 0;
+		(b[9] => z[30]) = 0;
+		(b[10] => z[30]) = 0;
+		(b[11] => z[30]) = 0;
+		(b[12] => z[30]) = 0;
+		(b[13] => z[30]) = 0;
+		(b[14] => z[30]) = 0;
+		(b[15] => z[30]) = 0;
+		(b[16] => z[30]) = 0;
+		(b[17] => z[30]) = 0;
+		(a[0] => z[31]) = 0;
+		(a[1] => z[31]) = 0;
+		(a[2] => z[31]) = 0;
+		(a[3] => z[31]) = 0;
+		(a[4] => z[31]) = 0;
+		(a[5] => z[31]) = 0;
+		(a[6] => z[31]) = 0;
+		(a[7] => z[31]) = 0;
+		(a[8] => z[31]) = 0;
+		(a[9] => z[31]) = 0;
+		(a[10] => z[31]) = 0;
+		(a[11] => z[31]) = 0;
+		(a[12] => z[31]) = 0;
+		(a[13] => z[31]) = 0;
+		(a[14] => z[31]) = 0;
+		(a[15] => z[31]) = 0;
+		(a[16] => z[31]) = 0;
+		(a[17] => z[31]) = 0;
+		(a[18] => z[31]) = 0;
+		(a[19] => z[31]) = 0;
+		(b[0] => z[31]) = 0;
+		(b[1] => z[31]) = 0;
+		(b[2] => z[31]) = 0;
+		(b[3] => z[31]) = 0;
+		(b[4] => z[31]) = 0;
+		(b[5] => z[31]) = 0;
+		(b[6] => z[31]) = 0;
+		(b[7] => z[31]) = 0;
+		(b[8] => z[31]) = 0;
+		(b[9] => z[31]) = 0;
+		(b[10] => z[31]) = 0;
+		(b[11] => z[31]) = 0;
+		(b[12] => z[31]) = 0;
+		(b[13] => z[31]) = 0;
+		(b[14] => z[31]) = 0;
+		(b[15] => z[31]) = 0;
+		(b[16] => z[31]) = 0;
+		(b[17] => z[31]) = 0;
+		(a[0] => z[32]) = 0;
+		(a[1] => z[32]) = 0;
+		(a[2] => z[32]) = 0;
+		(a[3] => z[32]) = 0;
+		(a[4] => z[32]) = 0;
+		(a[5] => z[32]) = 0;
+		(a[6] => z[32]) = 0;
+		(a[7] => z[32]) = 0;
+		(a[8] => z[32]) = 0;
+		(a[9] => z[32]) = 0;
+		(a[10] => z[32]) = 0;
+		(a[11] => z[32]) = 0;
+		(a[12] => z[32]) = 0;
+		(a[13] => z[32]) = 0;
+		(a[14] => z[32]) = 0;
+		(a[15] => z[32]) = 0;
+		(a[16] => z[32]) = 0;
+		(a[17] => z[32]) = 0;
+		(a[18] => z[32]) = 0;
+		(a[19] => z[32]) = 0;
+		(b[0] => z[32]) = 0;
+		(b[1] => z[32]) = 0;
+		(b[2] => z[32]) = 0;
+		(b[3] => z[32]) = 0;
+		(b[4] => z[32]) = 0;
+		(b[5] => z[32]) = 0;
+		(b[6] => z[32]) = 0;
+		(b[7] => z[32]) = 0;
+		(b[8] => z[32]) = 0;
+		(b[9] => z[32]) = 0;
+		(b[10] => z[32]) = 0;
+		(b[11] => z[32]) = 0;
+		(b[12] => z[32]) = 0;
+		(b[13] => z[32]) = 0;
+		(b[14] => z[32]) = 0;
+		(b[15] => z[32]) = 0;
+		(b[16] => z[32]) = 0;
+		(b[17] => z[32]) = 0;
+		(a[0] => z[33]) = 0;
+		(a[1] => z[33]) = 0;
+		(a[2] => z[33]) = 0;
+		(a[3] => z[33]) = 0;
+		(a[4] => z[33]) = 0;
+		(a[5] => z[33]) = 0;
+		(a[6] => z[33]) = 0;
+		(a[7] => z[33]) = 0;
+		(a[8] => z[33]) = 0;
+		(a[9] => z[33]) = 0;
+		(a[10] => z[33]) = 0;
+		(a[11] => z[33]) = 0;
+		(a[12] => z[33]) = 0;
+		(a[13] => z[33]) = 0;
+		(a[14] => z[33]) = 0;
+		(a[15] => z[33]) = 0;
+		(a[16] => z[33]) = 0;
+		(a[17] => z[33]) = 0;
+		(a[18] => z[33]) = 0;
+		(a[19] => z[33]) = 0;
+		(b[0] => z[33]) = 0;
+		(b[1] => z[33]) = 0;
+		(b[2] => z[33]) = 0;
+		(b[3] => z[33]) = 0;
+		(b[4] => z[33]) = 0;
+		(b[5] => z[33]) = 0;
+		(b[6] => z[33]) = 0;
+		(b[7] => z[33]) = 0;
+		(b[8] => z[33]) = 0;
+		(b[9] => z[33]) = 0;
+		(b[10] => z[33]) = 0;
+		(b[11] => z[33]) = 0;
+		(b[12] => z[33]) = 0;
+		(b[13] => z[33]) = 0;
+		(b[14] => z[33]) = 0;
+		(b[15] => z[33]) = 0;
+		(b[16] => z[33]) = 0;
+		(b[17] => z[33]) = 0;
+		(a[0] => z[34]) = 0;
+		(a[1] => z[34]) = 0;
+		(a[2] => z[34]) = 0;
+		(a[3] => z[34]) = 0;
+		(a[4] => z[34]) = 0;
+		(a[5] => z[34]) = 0;
+		(a[6] => z[34]) = 0;
+		(a[7] => z[34]) = 0;
+		(a[8] => z[34]) = 0;
+		(a[9] => z[34]) = 0;
+		(a[10] => z[34]) = 0;
+		(a[11] => z[34]) = 0;
+		(a[12] => z[34]) = 0;
+		(a[13] => z[34]) = 0;
+		(a[14] => z[34]) = 0;
+		(a[15] => z[34]) = 0;
+		(a[16] => z[34]) = 0;
+		(a[17] => z[34]) = 0;
+		(a[18] => z[34]) = 0;
+		(a[19] => z[34]) = 0;
+		(b[0] => z[34]) = 0;
+		(b[1] => z[34]) = 0;
+		(b[2] => z[34]) = 0;
+		(b[3] => z[34]) = 0;
+		(b[4] => z[34]) = 0;
+		(b[5] => z[34]) = 0;
+		(b[6] => z[34]) = 0;
+		(b[7] => z[34]) = 0;
+		(b[8] => z[34]) = 0;
+		(b[9] => z[34]) = 0;
+		(b[10] => z[34]) = 0;
+		(b[11] => z[34]) = 0;
+		(b[12] => z[34]) = 0;
+		(b[13] => z[34]) = 0;
+		(b[14] => z[34]) = 0;
+		(b[15] => z[34]) = 0;
+		(b[16] => z[34]) = 0;
+		(b[17] => z[34]) = 0;
+		(a[0] => z[35]) = 0;
+		(a[1] => z[35]) = 0;
+		(a[2] => z[35]) = 0;
+		(a[3] => z[35]) = 0;
+		(a[4] => z[35]) = 0;
+		(a[5] => z[35]) = 0;
+		(a[6] => z[35]) = 0;
+		(a[7] => z[35]) = 0;
+		(a[8] => z[35]) = 0;
+		(a[9] => z[35]) = 0;
+		(a[10] => z[35]) = 0;
+		(a[11] => z[35]) = 0;
+		(a[12] => z[35]) = 0;
+		(a[13] => z[35]) = 0;
+		(a[14] => z[35]) = 0;
+		(a[15] => z[35]) = 0;
+		(a[16] => z[35]) = 0;
+		(a[17] => z[35]) = 0;
+		(a[18] => z[35]) = 0;
+		(a[19] => z[35]) = 0;
+		(b[0] => z[35]) = 0;
+		(b[1] => z[35]) = 0;
+		(b[2] => z[35]) = 0;
+		(b[3] => z[35]) = 0;
+		(b[4] => z[35]) = 0;
+		(b[5] => z[35]) = 0;
+		(b[6] => z[35]) = 0;
+		(b[7] => z[35]) = 0;
+		(b[8] => z[35]) = 0;
+		(b[9] => z[35]) = 0;
+		(b[10] => z[35]) = 0;
+		(b[11] => z[35]) = 0;
+		(b[12] => z[35]) = 0;
+		(b[13] => z[35]) = 0;
+		(b[14] => z[35]) = 0;
+		(b[15] => z[35]) = 0;
+		(b[16] => z[35]) = 0;
+		(b[17] => z[35]) = 0;
+		(a[0] => z[36]) = 0;
+		(a[1] => z[36]) = 0;
+		(a[2] => z[36]) = 0;
+		(a[3] => z[36]) = 0;
+		(a[4] => z[36]) = 0;
+		(a[5] => z[36]) = 0;
+		(a[6] => z[36]) = 0;
+		(a[7] => z[36]) = 0;
+		(a[8] => z[36]) = 0;
+		(a[9] => z[36]) = 0;
+		(a[10] => z[36]) = 0;
+		(a[11] => z[36]) = 0;
+		(a[12] => z[36]) = 0;
+		(a[13] => z[36]) = 0;
+		(a[14] => z[36]) = 0;
+		(a[15] => z[36]) = 0;
+		(a[16] => z[36]) = 0;
+		(a[17] => z[36]) = 0;
+		(a[18] => z[36]) = 0;
+		(a[19] => z[36]) = 0;
+		(b[0] => z[36]) = 0;
+		(b[1] => z[36]) = 0;
+		(b[2] => z[36]) = 0;
+		(b[3] => z[36]) = 0;
+		(b[4] => z[36]) = 0;
+		(b[5] => z[36]) = 0;
+		(b[6] => z[36]) = 0;
+		(b[7] => z[36]) = 0;
+		(b[8] => z[36]) = 0;
+		(b[9] => z[36]) = 0;
+		(b[10] => z[36]) = 0;
+		(b[11] => z[36]) = 0;
+		(b[12] => z[36]) = 0;
+		(b[13] => z[36]) = 0;
+		(b[14] => z[36]) = 0;
+		(b[15] => z[36]) = 0;
+		(b[16] => z[36]) = 0;
+		(b[17] => z[36]) = 0;
+		(a[0] => z[37]) = 0;
+		(a[1] => z[37]) = 0;
+		(a[2] => z[37]) = 0;
+		(a[3] => z[37]) = 0;
+		(a[4] => z[37]) = 0;
+		(a[5] => z[37]) = 0;
+		(a[6] => z[37]) = 0;
+		(a[7] => z[37]) = 0;
+		(a[8] => z[37]) = 0;
+		(a[9] => z[37]) = 0;
+		(a[10] => z[37]) = 0;
+		(a[11] => z[37]) = 0;
+		(a[12] => z[37]) = 0;
+		(a[13] => z[37]) = 0;
+		(a[14] => z[37]) = 0;
+		(a[15] => z[37]) = 0;
+		(a[16] => z[37]) = 0;
+		(a[17] => z[37]) = 0;
+		(a[18] => z[37]) = 0;
+		(a[19] => z[37]) = 0;
+		(b[0] => z[37]) = 0;
+		(b[1] => z[37]) = 0;
+		(b[2] => z[37]) = 0;
+		(b[3] => z[37]) = 0;
+		(b[4] => z[37]) = 0;
+		(b[5] => z[37]) = 0;
+		(b[6] => z[37]) = 0;
+		(b[7] => z[37]) = 0;
+		(b[8] => z[37]) = 0;
+		(b[9] => z[37]) = 0;
+		(b[10] => z[37]) = 0;
+		(b[11] => z[37]) = 0;
+		(b[12] => z[37]) = 0;
+		(b[13] => z[37]) = 0;
+		(b[14] => z[37]) = 0;
+		(b[15] => z[37]) = 0;
+		(b[16] => z[37]) = 0;
+		(b[17] => z[37]) = 0;
+		(subtract => z[0]) = 0;
+		(subtract => z[1]) = 0;
+		(subtract => z[2]) = 0;
+		(subtract => z[3]) = 0;
+		(subtract => z[4]) = 0;
+		(subtract => z[5]) = 0;
+		(subtract => z[6]) = 0;
+		(subtract => z[7]) = 0;
+		(subtract => z[8]) = 0;
+		(subtract => z[9]) = 0;
+		(subtract => z[10]) = 0;
+		(subtract => z[11]) = 0;
+		(subtract => z[12]) = 0;
+		(subtract => z[13]) = 0;
+		(subtract => z[14]) = 0;
+		(subtract => z[15]) = 0;
+		(subtract => z[16]) = 0;
+		(subtract => z[17]) = 0;
+		(subtract => z[18]) = 0;
+		(subtract => z[19]) = 0;
+		(subtract => z[20]) = 0;
+		(subtract => z[21]) = 0;
+		(subtract => z[22]) = 0;
+		(subtract => z[23]) = 0;
+		(subtract => z[24]) = 0;
+		(subtract => z[25]) = 0;
+		(subtract => z[26]) = 0;
+		(subtract => z[27]) = 0;
+		(subtract => z[28]) = 0;
+		(subtract => z[29]) = 0;
+		(subtract => z[30]) = 0;
+		(subtract => z[31]) = 0;
+		(subtract => z[32]) = 0;
+		(subtract => z[33]) = 0;
+		(subtract => z[34]) = 0;
+		(subtract => z[35]) = 0;
+		(subtract => z[36]) = 0;
+		(subtract => z[37]) = 0;
+		(acc_fir[0] => z[0]) = 0;
+		(acc_fir[1] => z[0]) = 0;
+		(acc_fir[2] => z[0]) = 0;
+		(acc_fir[3] => z[0]) = 0;
+		(acc_fir[4] => z[0]) = 0;
+		(acc_fir[5] => z[0]) = 0;
+		(acc_fir[0] => z[1]) = 0;
+		(acc_fir[1] => z[1]) = 0;
+		(acc_fir[2] => z[1]) = 0;
+		(acc_fir[3] => z[1]) = 0;
+		(acc_fir[4] => z[1]) = 0;
+		(acc_fir[5] => z[1]) = 0;
+		(acc_fir[0] => z[2]) = 0;
+		(acc_fir[1] => z[2]) = 0;
+		(acc_fir[2] => z[2]) = 0;
+		(acc_fir[3] => z[2]) = 0;
+		(acc_fir[4] => z[2]) = 0;
+		(acc_fir[5] => z[2]) = 0;
+		(acc_fir[0] => z[3]) = 0;
+		(acc_fir[1] => z[3]) = 0;
+		(acc_fir[2] => z[3]) = 0;
+		(acc_fir[3] => z[3]) = 0;
+		(acc_fir[4] => z[3]) = 0;
+		(acc_fir[5] => z[3]) = 0;
+		(acc_fir[0] => z[4]) = 0;
+		(acc_fir[1] => z[4]) = 0;
+		(acc_fir[2] => z[4]) = 0;
+		(acc_fir[3] => z[4]) = 0;
+		(acc_fir[4] => z[4]) = 0;
+		(acc_fir[5] => z[4]) = 0;
+		(acc_fir[0] => z[5]) = 0;
+		(acc_fir[1] => z[5]) = 0;
+		(acc_fir[2] => z[5]) = 0;
+		(acc_fir[3] => z[5]) = 0;
+		(acc_fir[4] => z[5]) = 0;
+		(acc_fir[5] => z[5]) = 0;
+		(acc_fir[0] => z[6]) = 0;
+		(acc_fir[1] => z[6]) = 0;
+		(acc_fir[2] => z[6]) = 0;
+		(acc_fir[3] => z[6]) = 0;
+		(acc_fir[4] => z[6]) = 0;
+		(acc_fir[5] => z[6]) = 0;
+		(acc_fir[0] => z[7]) = 0;
+		(acc_fir[1] => z[7]) = 0;
+		(acc_fir[2] => z[7]) = 0;
+		(acc_fir[3] => z[7]) = 0;
+		(acc_fir[4] => z[7]) = 0;
+		(acc_fir[5] => z[7]) = 0;
+		(acc_fir[0] => z[8]) = 0;
+		(acc_fir[1] => z[8]) = 0;
+		(acc_fir[2] => z[8]) = 0;
+		(acc_fir[3] => z[8]) = 0;
+		(acc_fir[4] => z[8]) = 0;
+		(acc_fir[5] => z[8]) = 0;
+		(acc_fir[0] => z[9]) = 0;
+		(acc_fir[1] => z[9]) = 0;
+		(acc_fir[2] => z[9]) = 0;
+		(acc_fir[3] => z[9]) = 0;
+		(acc_fir[4] => z[9]) = 0;
+		(acc_fir[5] => z[9]) = 0;
+		(acc_fir[0] => z[10]) = 0;
+		(acc_fir[1] => z[10]) = 0;
+		(acc_fir[2] => z[10]) = 0;
+		(acc_fir[3] => z[10]) = 0;
+		(acc_fir[4] => z[10]) = 0;
+		(acc_fir[5] => z[10]) = 0;
+		(acc_fir[0] => z[11]) = 0;
+		(acc_fir[1] => z[11]) = 0;
+		(acc_fir[2] => z[11]) = 0;
+		(acc_fir[3] => z[11]) = 0;
+		(acc_fir[4] => z[11]) = 0;
+		(acc_fir[5] => z[11]) = 0;
+		(acc_fir[0] => z[12]) = 0;
+		(acc_fir[1] => z[12]) = 0;
+		(acc_fir[2] => z[12]) = 0;
+		(acc_fir[3] => z[12]) = 0;
+		(acc_fir[4] => z[12]) = 0;
+		(acc_fir[5] => z[12]) = 0;
+		(acc_fir[0] => z[13]) = 0;
+		(acc_fir[1] => z[13]) = 0;
+		(acc_fir[2] => z[13]) = 0;
+		(acc_fir[3] => z[13]) = 0;
+		(acc_fir[4] => z[13]) = 0;
+		(acc_fir[5] => z[13]) = 0;
+		(acc_fir[0] => z[14]) = 0;
+		(acc_fir[1] => z[14]) = 0;
+		(acc_fir[2] => z[14]) = 0;
+		(acc_fir[3] => z[14]) = 0;
+		(acc_fir[4] => z[14]) = 0;
+		(acc_fir[5] => z[14]) = 0;
+		(acc_fir[0] => z[15]) = 0;
+		(acc_fir[1] => z[15]) = 0;
+		(acc_fir[2] => z[15]) = 0;
+		(acc_fir[3] => z[15]) = 0;
+		(acc_fir[4] => z[15]) = 0;
+		(acc_fir[5] => z[15]) = 0;
+		(acc_fir[0] => z[16]) = 0;
+		(acc_fir[1] => z[16]) = 0;
+		(acc_fir[2] => z[16]) = 0;
+		(acc_fir[3] => z[16]) = 0;
+		(acc_fir[4] => z[16]) = 0;
+		(acc_fir[5] => z[16]) = 0;
+		(acc_fir[0] => z[17]) = 0;
+		(acc_fir[1] => z[17]) = 0;
+		(acc_fir[2] => z[17]) = 0;
+		(acc_fir[3] => z[17]) = 0;
+		(acc_fir[4] => z[17]) = 0;
+		(acc_fir[5] => z[17]) = 0;
+		(acc_fir[0] => z[18]) = 0;
+		(acc_fir[1] => z[18]) = 0;
+		(acc_fir[2] => z[18]) = 0;
+		(acc_fir[3] => z[18]) = 0;
+		(acc_fir[4] => z[18]) = 0;
+		(acc_fir[5] => z[18]) = 0;
+		(acc_fir[0] => z[19]) = 0;
+		(acc_fir[1] => z[19]) = 0;
+		(acc_fir[2] => z[19]) = 0;
+		(acc_fir[3] => z[19]) = 0;
+		(acc_fir[4] => z[19]) = 0;
+		(acc_fir[5] => z[19]) = 0;
+		(acc_fir[0] => z[20]) = 0;
+		(acc_fir[1] => z[20]) = 0;
+		(acc_fir[2] => z[20]) = 0;
+		(acc_fir[3] => z[20]) = 0;
+		(acc_fir[4] => z[20]) = 0;
+		(acc_fir[5] => z[20]) = 0;
+		(acc_fir[0] => z[21]) = 0;
+		(acc_fir[1] => z[21]) = 0;
+		(acc_fir[2] => z[21]) = 0;
+		(acc_fir[3] => z[21]) = 0;
+		(acc_fir[4] => z[21]) = 0;
+		(acc_fir[5] => z[21]) = 0;
+		(acc_fir[0] => z[22]) = 0;
+		(acc_fir[1] => z[22]) = 0;
+		(acc_fir[2] => z[22]) = 0;
+		(acc_fir[3] => z[22]) = 0;
+		(acc_fir[4] => z[22]) = 0;
+		(acc_fir[5] => z[22]) = 0;
+		(acc_fir[0] => z[23]) = 0;
+		(acc_fir[1] => z[23]) = 0;
+		(acc_fir[2] => z[23]) = 0;
+		(acc_fir[3] => z[23]) = 0;
+		(acc_fir[4] => z[23]) = 0;
+		(acc_fir[5] => z[23]) = 0;
+		(acc_fir[0] => z[24]) = 0;
+		(acc_fir[1] => z[24]) = 0;
+		(acc_fir[2] => z[24]) = 0;
+		(acc_fir[3] => z[24]) = 0;
+		(acc_fir[4] => z[24]) = 0;
+		(acc_fir[5] => z[24]) = 0;
+		(acc_fir[0] => z[25]) = 0;
+		(acc_fir[1] => z[25]) = 0;
+		(acc_fir[2] => z[25]) = 0;
+		(acc_fir[3] => z[25]) = 0;
+		(acc_fir[4] => z[25]) = 0;
+		(acc_fir[5] => z[25]) = 0;
+		(acc_fir[0] => z[26]) = 0;
+		(acc_fir[1] => z[26]) = 0;
+		(acc_fir[2] => z[26]) = 0;
+		(acc_fir[3] => z[26]) = 0;
+		(acc_fir[4] => z[26]) = 0;
+		(acc_fir[5] => z[26]) = 0;
+		(acc_fir[0] => z[27]) = 0;
+		(acc_fir[1] => z[27]) = 0;
+		(acc_fir[2] => z[27]) = 0;
+		(acc_fir[3] => z[27]) = 0;
+		(acc_fir[4] => z[27]) = 0;
+		(acc_fir[5] => z[27]) = 0;
+		(acc_fir[0] => z[28]) = 0;
+		(acc_fir[1] => z[28]) = 0;
+		(acc_fir[2] => z[28]) = 0;
+		(acc_fir[3] => z[28]) = 0;
+		(acc_fir[4] => z[28]) = 0;
+		(acc_fir[5] => z[28]) = 0;
+		(acc_fir[0] => z[29]) = 0;
+		(acc_fir[1] => z[29]) = 0;
+		(acc_fir[2] => z[29]) = 0;
+		(acc_fir[3] => z[29]) = 0;
+		(acc_fir[4] => z[29]) = 0;
+		(acc_fir[5] => z[29]) = 0;
+		(acc_fir[0] => z[30]) = 0;
+		(acc_fir[1] => z[30]) = 0;
+		(acc_fir[2] => z[30]) = 0;
+		(acc_fir[3] => z[30]) = 0;
+		(acc_fir[4] => z[30]) = 0;
+		(acc_fir[5] => z[30]) = 0;
+		(acc_fir[0] => z[31]) = 0;
+		(acc_fir[1] => z[31]) = 0;
+		(acc_fir[2] => z[31]) = 0;
+		(acc_fir[3] => z[31]) = 0;
+		(acc_fir[4] => z[31]) = 0;
+		(acc_fir[5] => z[31]) = 0;
+		(acc_fir[0] => z[32]) = 0;
+		(acc_fir[1] => z[32]) = 0;
+		(acc_fir[2] => z[32]) = 0;
+		(acc_fir[3] => z[32]) = 0;
+		(acc_fir[4] => z[32]) = 0;
+		(acc_fir[5] => z[32]) = 0;
+		(acc_fir[0] => z[33]) = 0;
+		(acc_fir[1] => z[33]) = 0;
+		(acc_fir[2] => z[33]) = 0;
+		(acc_fir[3] => z[33]) = 0;
+		(acc_fir[4] => z[33]) = 0;
+		(acc_fir[5] => z[33]) = 0;
+		(acc_fir[0] => z[34]) = 0;
+		(acc_fir[1] => z[34]) = 0;
+		(acc_fir[2] => z[34]) = 0;
+		(acc_fir[3] => z[34]) = 0;
+		(acc_fir[4] => z[34]) = 0;
+		(acc_fir[5] => z[34]) = 0;
+		(acc_fir[0] => z[35]) = 0;
+		(acc_fir[1] => z[35]) = 0;
+		(acc_fir[2] => z[35]) = 0;
+		(acc_fir[3] => z[35]) = 0;
+		(acc_fir[4] => z[35]) = 0;
+		(acc_fir[5] => z[35]) = 0;
+		(acc_fir[0] => z[36]) = 0;
+		(acc_fir[1] => z[36]) = 0;
+		(acc_fir[2] => z[36]) = 0;
+		(acc_fir[3] => z[36]) = 0;
+		(acc_fir[4] => z[36]) = 0;
+		(acc_fir[5] => z[36]) = 0;
+		(acc_fir[0] => z[37]) = 0;
+		(acc_fir[1] => z[37]) = 0;
+		(acc_fir[2] => z[37]) = 0;
+		(acc_fir[3] => z[37]) = 0;
+		(acc_fir[4] => z[37]) = 0;
+		(acc_fir[5] => z[37]) = 0;
+	endspecify
+`endif
+
+endmodule
+
+module QL_DSP2_MULTADD_REGIN (
+	input  wire [19:0] a,
+	input  wire [17:0] b,
+	output wire [37:0] z,
+
+	(* clkbuf_sink *)
+	input  wire        clk,
+	input  wire        reset,
+
+	input  wire [ 2:0] feedback,
+	input  wire [ 5:0] acc_fir,
+	input  wire        load_acc,
+	input  wire        unsigned_a,
+	input  wire        unsigned_b,
+
+	input  wire        f_mode,
+	input  wire [ 2:0] output_select,
+	input  wire        saturate_enable,
+	input  wire [ 5:0] shift_right,
+	input  wire        round,
+	input  wire        subtract,
+	input  wire        register_inputs
+);
+
+	parameter [79:0] MODE_BITS = 80'd0;
+
+	localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+	localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+	localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+	localparam [19:0] COEFF_3 = MODE_BITS[79:60];
+
+	QL_DSP2 #(
+		.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+	) dsp (
+		.a(a),
+		.b(b),
+		.dly_b(),
+		.z(z),
+
+		.f_mode(f_mode),
+
+		.feedback(feedback),
+		.acc_fir(acc_fir),
+		.load_acc(load_acc),
+
+		.unsigned_a(unsigned_a),
+		.unsigned_b(unsigned_b),
+
+		.clk(clk),
+		.reset(reset),
+
+		.output_select(output_select),      // unregistered output: ACCin (2, 3)
+		.saturate_enable(saturate_enable),
+		.shift_right(shift_right),
+		.round(round),
+		.subtract(subtract),
+		.register_inputs(register_inputs)   // registered inputs
+	);
+
+`ifdef SDF_SIM
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+		$setuphold(posedge clk, acc_fir, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module QL_DSP2_MULTADD_REGOUT (
+	input  wire [19:0] a,
+	input  wire [17:0] b,
+	output wire [37:0] z,
+
+	(* clkbuf_sink *)
+	input  wire        clk,
+	input  wire        reset,
+
+	input  wire [ 2:0] feedback,
+	input  wire [ 5:0] acc_fir,
+	input  wire        load_acc,
+	input  wire        unsigned_a,
+	input  wire        unsigned_b,
+
+	input  wire        f_mode,
+	input  wire [ 2:0] output_select,
+	input  wire        saturate_enable,
+	input  wire [ 5:0] shift_right,
+	input  wire        round,
+	input  wire        subtract,
+	input  wire        register_inputs
+);
+
+	parameter [79:0] MODE_BITS = 80'd0;
+
+	localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+	localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+	localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+	localparam [19:0] COEFF_3 = MODE_BITS[79:60];
+
+	QL_DSP2 #(
+		.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+	) dsp (
+		.a(a),
+		.b(b),
+		.dly_b(),
+		.z(z),
+
+		.f_mode(f_mode),
+
+		.feedback(feedback),
+		.acc_fir(acc_fir),
+		.load_acc(load_acc),
+
+		.unsigned_a(unsigned_a),
+		.unsigned_b(unsigned_b),
+
+		.clk(clk),
+		.reset(reset),
+
+		.output_select(output_select),      // registered output: ACCin (6, 7)
+		.saturate_enable(saturate_enable),
+		.shift_right(shift_right),
+		.round(round),
+		.subtract(subtract),
+		.register_inputs(register_inputs)   // unregistered inputs
+	);
+
+`ifdef SDF_SIM
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+		$setuphold(posedge clk, acc_fir, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module QL_DSP2_MULTADD_REGIN_REGOUT (
+	input  wire [19:0] a,
+	input  wire [17:0] b,
+	output wire [37:0] z,
+
+	(* clkbuf_sink *)
+	input  wire        clk,
+	input  wire        reset,
+
+	input  wire [ 2:0] feedback,
+	input  wire [ 5:0] acc_fir,
+	input  wire        load_acc,
+	input  wire        unsigned_a,
+	input  wire        unsigned_b,
+
+	input  wire        f_mode,
+	input  wire [ 2:0] output_select,
+	input  wire        saturate_enable,
+	input  wire [ 5:0] shift_right,
+	input  wire        round,
+	input  wire        subtract,
+	input  wire        register_inputs
+);
+
+	parameter [79:0] MODE_BITS = 80'd0;
+
+	localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+	localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+	localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+	localparam [19:0] COEFF_3 = MODE_BITS[79:60];
+
+	QL_DSP2 #(
+		.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+	) dsp (
+		.a(a),
+		.b(b),
+		.dly_b(),
+		.z(z),
+
+		.f_mode(f_mode),
+
+		.feedback(feedback),
+		.acc_fir(acc_fir),
+		.load_acc(load_acc),
+
+		.unsigned_a(unsigned_a),
+		.unsigned_b(unsigned_b),
+
+		.clk(clk),
+		.reset(reset),
+
+		.output_select(output_select),      // registered output: ACCin (6, 7)
+		.saturate_enable(saturate_enable),
+		.shift_right(shift_right),
+		.round(round),
+		.subtract(subtract),
+		.register_inputs(register_inputs)   // registered inputs
+	);
+
+`ifdef SDF_SIM
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+		$setuphold(posedge clk, acc_fir, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module QL_DSP2_MULTACC (
+	input  wire [19:0] a,
+	input  wire [17:0] b,
+	output wire [37:0] z,
+
+	(* clkbuf_sink *)
+	input  wire        clk,
+	input  wire        reset,
+
+	input  wire        load_acc,
+	input  wire [ 2:0] feedback,
+	input  wire        unsigned_a,
+	input  wire        unsigned_b,
+
+	input  wire        f_mode,
+	input  wire [ 2:0] output_select,
+	input  wire        saturate_enable,
+	input  wire [ 5:0] shift_right,
+	input  wire        round,
+	input  wire        subtract,
+	input  wire        register_inputs
+);
+
+	parameter [79:0] MODE_BITS = 80'd0;
+
+	localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+	localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+	localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+	localparam [19:0] COEFF_3 = MODE_BITS[79:60];
+
+	QL_DSP2 #(
+		.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+	) dsp (
+		.a(a),
+		.b(b),
+		.acc_fir(6'b0),
+		.z(z),
+		.dly_b(),
+
+		.f_mode(f_mode),
+
+		.feedback(feedback),
+		.load_acc(load_acc),
+
+		.unsigned_a(unsigned_a),
+		.unsigned_b(unsigned_b),
+
+		.clk(clk),
+		.reset(reset),
+
+		.output_select(output_select),      // unregistered output: ACCout (1)
+		.saturate_enable(saturate_enable),
+		.shift_right(shift_right),
+		.round(round),
+		.subtract(subtract),
+		.register_inputs(register_inputs)   // unregistered inputs
+	);
+
+`ifdef SDF_SIM
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module QL_DSP2_MULTACC_REGIN (
+	input  wire [19:0] a,
+	input  wire [17:0] b,
+	output wire [37:0] z,
+
+	(* clkbuf_sink *)
+	input  wire        clk,
+	input  wire        reset,
+
+	input  wire [ 2:0] feedback,
+	input  wire        load_acc,
+	input  wire        unsigned_a,
+	input  wire        unsigned_b,
+
+	input  wire        f_mode,
+	input  wire [ 2:0] output_select,
+	input  wire        saturate_enable,
+	input  wire [ 5:0] shift_right,
+	input  wire        round,
+	input  wire        subtract,
+	input  wire        register_inputs
+);
+
+	parameter [79:0] MODE_BITS = 80'd0;
+
+	localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+	localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+	localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+	localparam [19:0] COEFF_3 = MODE_BITS[79:60];
+
+	QL_DSP2 #(
+		.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+	) dsp (
+		.a(a),
+		.b(b),
+		.acc_fir(6'b0),
+		.z(z),
+		.dly_b(),
+
+		.f_mode(f_mode),
+
+		.feedback(feedback),
+		.load_acc(load_acc),
+
+		.unsigned_a(unsigned_a),
+		.unsigned_b(unsigned_b),
+
+		.clk(clk),
+		.reset(reset),
+
+		.output_select(output_select),      // unregistered output: ACCout (1)
+		.saturate_enable(saturate_enable),
+		.shift_right(shift_right),
+		.round(round),
+		.subtract(subtract),
+		.register_inputs(register_inputs)   // registered inputs
+	);
+
+`ifdef SDF_SIM
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module QL_DSP2_MULTACC_REGOUT (
+	input  wire [19:0] a,
+	input  wire [17:0] b,
+	output wire [37:0] z,
+
+	(* clkbuf_sink *)
+	input  wire        clk,
+	input  wire        reset,
+
+	input  wire [ 2:0] feedback,
+	input  wire        load_acc,
+	input  wire        unsigned_a,
+	input  wire        unsigned_b,
+
+	input  wire        f_mode,
+	input  wire [ 2:0] output_select,
+	input  wire        saturate_enable,
+	input  wire [ 5:0] shift_right,
+	input  wire        round,
+	input  wire        subtract,
+	input  wire        register_inputs
+);
+
+	parameter [79:0] MODE_BITS = 80'd0;
+
+	localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+	localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+	localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+	localparam [19:0] COEFF_3 = MODE_BITS[79:60];
+
+	QL_DSP2 #(
+		.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+	) dsp (
+		.a(a),
+		.b(b),
+		.acc_fir(6'b0),
+		.z(z),
+		.dly_b(),
+
+		.f_mode(f_mode),
+
+		.feedback(feedback),
+		.load_acc(load_acc),
+
+		.unsigned_a(unsigned_a),
+		.unsigned_b(unsigned_b),
+
+		.clk(clk),
+		.reset(reset),
+
+		.output_select(output_select),      // registered output: ACCout (5)
+		.saturate_enable(saturate_enable),
+		.shift_right(shift_right),
+		.round(round),
+		.subtract(subtract),
+		.register_inputs(register_inputs)   // unregistered inputs
+	);
+
+`ifdef SDF_SIM
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module QL_DSP2_MULTACC_REGIN_REGOUT (
+	input  wire [19:0] a,
+	input  wire [17:0] b,
+	output wire [37:0] z,
+
+	(* clkbuf_sink *)
+	input  wire        clk,
+	input  wire        reset,
+
+	input  wire [ 2:0] feedback,
+	input  wire        load_acc,
+	input  wire        unsigned_a,
+	input  wire        unsigned_b,
+
+	input  wire        f_mode,
+	input  wire [ 2:0] output_select,
+	input  wire        saturate_enable,
+	input  wire [ 5:0] shift_right,
+	input  wire        round,
+	input  wire        subtract,
+	input  wire        register_inputs
+);
+
+	parameter [79:0] MODE_BITS = 80'd0;
+
+	localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+	localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+	localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+	localparam [19:0] COEFF_3 = MODE_BITS[79:60];
+
+	QL_DSP2 #(
+		.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+	) dsp (
+		.a(a),
+		.b(b),
+		.acc_fir(6'b0),
+		.z(z),
+		.dly_b(),
+
+		.f_mode(f_mode),
+
+		.feedback(feedback),
+		.load_acc(load_acc),
+
+		.unsigned_a(unsigned_a),
+		.unsigned_b(unsigned_b),
+
+		.clk(clk),
+		.reset(reset),
+
+		.output_select(output_select),      // registered output: ACCout (5)
+		.saturate_enable(saturate_enable),
+		.shift_right(shift_right),
+		.round(round),
+		.subtract(subtract),
+		.register_inputs(register_inputs)   // registered inputs
+	);
+
+`ifdef SDF_SIM
+	specify
+		(posedge clk => (z +: a)) = 0;
+		(posedge clk => (z +: b)) = 0;
+		$setuphold(posedge clk, a, 0, 0);
+		$setuphold(posedge clk, b, 0, 0);
+		$setuphold(posedge clk, feedback, 0, 0);
+		$setuphold(posedge clk, load_acc, 0, 0);
+		$setuphold(posedge clk, subtract, 0, 0);
+	endspecify
+`endif
+
+endmodule
+
+module dsp_t1_20x18x64_cfg_ports (
+	input  wire [19:0] a_i,
+	input  wire [17:0] b_i,
+	input  wire [ 5:0] acc_fir_i,
+	output wire [37:0] z_o,
+	output wire [17:0] dly_b_o,
+
+	(* clkbuf_sink *)
+	input  wire        clock_i,
+	input  wire        reset_i,
+
+	input  wire [ 2:0] feedback_i,
+	input  wire        load_acc_i,
+	input  wire        unsigned_a_i,
+	input  wire        unsigned_b_i,
+
+	input  wire [ 2:0] output_select_i,
+	input  wire        saturate_enable_i,
+	input  wire [ 5:0] shift_right_i,
+	input  wire        round_i,
+	input  wire        subtract_i,
+	input  wire        register_inputs_i
+);
+
+	parameter [19:0] COEFF_0 = 20'd0;
+	parameter [19:0] COEFF_1 = 20'd0;
+	parameter [19:0] COEFF_2 = 20'd0;
+	parameter [19:0] COEFF_3 = 20'd0;
+
+	QL_DSP2 #(
+		.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
+	) dsp (
+		.a(a_i),
+		.b(b_i),
+		.z(z_o),
+		.dly_b(dly_b_o),
+
+		.f_mode(1'b0),  // 20x18x64 DSP
+
+		.acc_fir(acc_fir_i),
+		.feedback(feedback_i),
+		.load_acc(load_acc_i),
+
+		.unsigned_a(unsigned_a_i),
+		.unsigned_b(unsigned_b_i),
+
+		.clk(clock_i),
+		.reset(reset_i),
+
+		.saturate_enable(saturate_enable_i),
+		.output_select(output_select_i),
+		.round(round_i),
+		.shift_right(shift_right_i),
+		.subtract(subtract_i),
+		.register_inputs(register_inputs_i)
+	);
+endmodule
+
+module dsp_t1_10x9x32_cfg_ports (
+	input  wire [ 9:0] a_i,
+	input  wire [ 8:0] b_i,
+	input  wire [ 5:0] acc_fir_i,
+	output wire [18:0] z_o,
+	output wire [ 8:0] dly_b_o,
+
+	(* clkbuf_sink *)
+	input  wire        clock_i,
+	input  wire        reset_i,
+
+	input  wire [ 2:0] feedback_i,
+	input  wire        load_acc_i,
+	input  wire        unsigned_a_i,
+	input  wire        unsigned_b_i,
+
+	input  wire [ 2:0] output_select_i,
+	input  wire        saturate_enable_i,
+	input  wire [ 5:0] shift_right_i,
+	input  wire        round_i,
+	input  wire        subtract_i,
+	input  wire        register_inputs_i
+);
+
+	parameter [9:0] COEFF_0 = 10'd0;
+	parameter [9:0] COEFF_1 = 10'd0;
+	parameter [9:0] COEFF_2 = 10'd0;
+	parameter [9:0] COEFF_3 = 10'd0;
+
+	wire [18:0] z_rem;
+	wire [8:0] dly_b_rem;
+
+	QL_DSP2 #(
+		.MODE_BITS({10'd0, COEFF_3,
+					10'd0, COEFF_2,
+					10'd0, COEFF_1,
+					10'd0, COEFF_0})
+	) dsp (
+		.a({10'd0, a_i}),
+		.b({9'd0, b_i}),
+		.z({z_rem, z_o}),
+		.dly_b({dly_b_rem, dly_b_o}),
+
+		.f_mode(1'b1),  // 10x9x32 DSP
+
+		.acc_fir(acc_fir_i),
+		.feedback(feedback_i),
+		.load_acc(load_acc_i),
+
+		.unsigned_a(unsigned_a_i),
+		.unsigned_b(unsigned_b_i),
+
+		.clk(clock_i),
+		.reset(reset_i),
+
+		.saturate_enable(saturate_enable_i),
+		.output_select(output_select_i),
+		.round(round_i),
+		.shift_right(shift_right_i),
+		.subtract(subtract_i),
+		.register_inputs(register_inputs_i)
+	);
+endmodule
+
+module dsp_t1_sim_cfg_ports # (
+	parameter NBITS_ACC  = 64,
+	parameter NBITS_A    = 20,
+	parameter NBITS_B    = 18,
+	parameter NBITS_Z    = 38
+)(
+	input  wire [NBITS_A-1:0] a_i,
+	input  wire [NBITS_B-1:0] b_i,
+	output wire [NBITS_Z-1:0] z_o,
+	output reg  [NBITS_B-1:0] dly_b_o,
+
+	input  wire [5:0]         acc_fir_i,
+	input  wire [2:0]         feedback_i,
+	input  wire               load_acc_i,
+
+	input  wire               unsigned_a_i,
+	input  wire               unsigned_b_i,
+
+	input  wire               clock_i,
+	input  wire               s_reset,
+
+	input  wire               saturate_enable_i,
+	input  wire [2:0]         output_select_i,
+	input  wire               round_i,
+	input  wire [5:0]         shift_right_i,
+	input  wire               subtract_i,
+	input  wire               register_inputs_i,
+	input  wire [NBITS_A-1:0] coef_0_i,
+	input  wire [NBITS_A-1:0] coef_1_i,
+	input  wire [NBITS_A-1:0] coef_2_i,
+	input  wire [NBITS_A-1:0] coef_3_i
+);
+
+// FIXME: The version of Icarus Verilog from Conda seems not to recognize the
+// $error macro. Disable this sanity check for now because of that.
+
+
+	// Input registers
+	reg  [NBITS_A-1:0]  r_a;
+	reg  [NBITS_B-1:0]  r_b;
+	reg  [5:0]          r_acc_fir;
+	reg                 r_unsigned_a;
+	reg                 r_unsigned_b;
+	reg                 r_load_acc;
+	reg  [2:0]          r_feedback;
+	reg  [5:0]          r_shift_d1;
+	reg  [5:0]          r_shift_d2;
+	reg         r_subtract;
+	reg         r_sat;
+	reg         r_rnd;
+	reg [NBITS_ACC-1:0] acc;
+
+	initial begin
+		r_a          <= 0;
+		r_b          <= 0;
+
+		r_acc_fir    <= 0;
+		r_unsigned_a <= 0;
+		r_unsigned_b <= 0;
+		r_feedback   <= 0;
+		r_shift_d1   <= 0;
+		r_shift_d2   <= 0;
+		r_subtract   <= 0;
+		r_load_acc   <= 0;
+		r_sat        <= 0;
+		r_rnd        <= 0;
+	end
+
+	always @(posedge clock_i or posedge s_reset) begin
+		if (s_reset) begin
+
+			r_a <= 'h0;
+			r_b <= 'h0;
+
+			r_acc_fir    <= 0;
+			r_unsigned_a <= 0;
+			r_unsigned_b <= 0;
+			r_feedback   <= 0;
+			r_shift_d1   <= 0;
+			r_shift_d2   <= 0;
+			r_subtract   <= 0;
+			r_load_acc   <= 0;
+			r_sat    <= 0;
+			r_rnd    <= 0;
+
+		end else begin
+
+			r_a <= a_i;
+			r_b <= b_i;
+
+			r_acc_fir    <= acc_fir_i;
+			r_unsigned_a <= unsigned_a_i;
+			r_unsigned_b <= unsigned_b_i;
+			r_feedback   <= feedback_i;
+			r_shift_d1   <= shift_right_i;
+			r_shift_d2   <= r_shift_d1;
+			r_subtract   <= subtract_i;
+			r_load_acc   <= load_acc_i;
+			r_sat    <= r_sat;
+			r_rnd    <= r_rnd;
+
+		end
+	end
+
+	// Registered / non-registered input path select
+	wire [NBITS_A-1:0]  a = register_inputs_i ? r_a : a_i;
+	wire [NBITS_B-1:0]  b = register_inputs_i ? r_b : b_i;
+
+	wire [5:0] acc_fir = register_inputs_i ? r_acc_fir : acc_fir_i;
+	wire       unsigned_a = register_inputs_i ? r_unsigned_a : unsigned_a_i;
+	wire       unsigned_b = register_inputs_i ? r_unsigned_b : unsigned_b_i;
+	wire [2:0] feedback   = register_inputs_i ? r_feedback   : feedback_i;
+	wire       load_acc   = register_inputs_i ? r_load_acc   : load_acc_i;
+	wire       subtract   = register_inputs_i ? r_subtract   : subtract_i;
+	wire       sat    = register_inputs_i ? r_sat : saturate_enable_i;
+	wire       rnd    = register_inputs_i ? r_rnd : round_i;
+
+	// Shift right control
+	wire [5:0] shift_d1 = register_inputs_i ? r_shift_d1 : shift_right_i;
+	wire [5:0] shift_d2 = output_select_i[1] ? shift_d1 : r_shift_d2;
+
+	// Multiplier
+	wire unsigned_mode = unsigned_a & unsigned_b;
+	wire [NBITS_A-1:0] mult_a;
+	assign mult_a = (feedback == 3'h0) ?   a :
+					(feedback == 3'h1) ?   a :
+					(feedback == 3'h2) ?   a :
+					(feedback == 3'h3) ?   acc[NBITS_A-1:0] :
+					(feedback == 3'h4) ?   coef_0_i :
+					(feedback == 3'h5) ?   coef_1_i :
+					(feedback == 3'h6) ?   coef_2_i :
+					   coef_3_i;    // if feedback == 3'h7
+
+	wire [NBITS_B-1:0] mult_b = (feedback == 2'h2) ? {NBITS_B{1'b0}}  : b;
+
+	wire [NBITS_A-1:0] mult_sgn_a = mult_a[NBITS_A-1];
+	wire [NBITS_A-1:0] mult_mag_a = (mult_sgn_a && !unsigned_a) ? (~mult_a + 1) : mult_a;
+	wire [NBITS_B-1:0] mult_sgn_b = mult_b[NBITS_B-1];
+	wire [NBITS_B-1:0] mult_mag_b = (mult_sgn_b && !unsigned_b) ? (~mult_b + 1) : mult_b;
+
+	wire [NBITS_A+NBITS_B-1:0] mult_mag = mult_mag_a * mult_mag_b;
+	wire mult_sgn = (mult_sgn_a && !unsigned_a) ^ (mult_sgn_b && !unsigned_b);
+
+	wire [NBITS_A+NBITS_B-1:0] mult = (unsigned_a && unsigned_b) ?
+		(mult_a * mult_b) : (mult_sgn ? (~mult_mag + 1) : mult_mag);
+
+	// Sign extension
+	wire [NBITS_ACC-1:0] mult_xtnd = unsigned_mode ?
+		{{(NBITS_ACC-NBITS_A-NBITS_B){1'b0}},                    mult[NBITS_A+NBITS_B-1:0]} :
+		{{(NBITS_ACC-NBITS_A-NBITS_B){mult[NBITS_A+NBITS_B-1]}}, mult[NBITS_A+NBITS_B-1:0]};
+
+	// Adder
+	wire [NBITS_ACC-1:0] acc_fir_int = unsigned_a ? {{(NBITS_ACC-NBITS_A){1'b0}},         a} :
+													{{(NBITS_ACC-NBITS_A){a[NBITS_A-1]}}, a} ;
+
+	wire [NBITS_ACC-1:0] add_a = (subtract) ? (~mult_xtnd + 1) : mult_xtnd;
+	wire [NBITS_ACC-1:0] add_b = (feedback_i == 3'h0) ? acc :
+								 (feedback_i == 3'h1) ? {{NBITS_ACC}{1'b0}} : (acc_fir_int << acc_fir);
+
+	wire [NBITS_ACC-1:0] add_o = add_a + add_b;
+
+	// Accumulator
+	initial acc <= 0;
+
+	always @(posedge clock_i or posedge s_reset)
+		if (s_reset) acc <= 'h0;
+		else begin
+			if (load_acc)
+				acc <= add_o;
+			else
+				acc <= acc;
+		end
+
+	// Adder/accumulator output selection
+	wire [NBITS_ACC-1:0] acc_out = (output_select_i[1]) ? add_o : acc;
+
+	// Round, shift, saturate
+	wire [NBITS_ACC-1:0] acc_rnd = (rnd && (shift_right_i != 0)) ? (acc_out + ({{(NBITS_ACC-1){1'b0}}, 1'b1} << (shift_right_i - 1))) :
+																	acc_out;
+
+	wire [NBITS_ACC-1:0] acc_shr = (unsigned_mode) ? (acc_rnd  >> shift_right_i) :
+													 (acc_rnd >>> shift_right_i);
+
+	wire [NBITS_ACC-1:0] acc_sat_u = (acc_shr[NBITS_ACC-1:NBITS_Z] != 0) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{NBITS_Z{1'b1}}} :
+																		   {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}};
+
+	wire [NBITS_ACC-1:0] acc_sat_s = ((|acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b0) ||
+									  (&acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b1)) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}} :
+																				   {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_ACC-1],{NBITS_Z-1{~acc_shr[NBITS_ACC-1]}}}};
+
+	wire [NBITS_ACC-1:0] acc_sat = (sat) ? ((unsigned_mode) ? acc_sat_u : acc_sat_s) : acc_shr;
+
+	// Output signals
+	wire [NBITS_Z-1:0]  z0;
+	reg  [NBITS_Z-1:0]  z1;
+	wire [NBITS_Z-1:0]  z2;
+
+	assign z0 = mult_xtnd[NBITS_Z-1:0];
+	assign z2 = acc_sat[NBITS_Z-1:0];
+
+	initial z1 <= 0;
+
+	always @(posedge clock_i or posedge s_reset)
+		if (s_reset)
+			z1 <= 0;
+		else begin
+			z1 <= (output_select_i == 3'b100) ? z0 : z2;
+		end
+
+	// Output mux
+	assign z_o = (output_select_i == 3'h0) ?   z0 :
+				 (output_select_i == 3'h1) ?   z2 :
+				 (output_select_i == 3'h2) ?   z2 :
+				 (output_select_i == 3'h3) ?   z2 :
+				 (output_select_i == 3'h4) ?   z1 :
+				 (output_select_i == 3'h5) ?   z1 :
+				 (output_select_i == 3'h6) ?   z1 :
+						   z1;  // if output_select_i == 3'h7
+
+	// B input delayed passthrough
+	initial dly_b_o <= 0;
+
+	always @(posedge clock_i or posedge s_reset)
+		if (s_reset)
+			dly_b_o <= 0;
+		else
+			dly_b_o <= b_i;
+
+endmodule
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/ffs_map.v b/yosys/techlibs/quicklogic/qlf_k6n10f/ffs_map.v
new file mode 100644
index 00000000000..43a71b425a1
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/ffs_map.v
@@ -0,0 +1,133 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+// DFF, asynchronous set/reset, enable
+module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q);
+	input  C;
+	input  S;
+	input  R;
+	input  E;
+	input  D;
+	output Q;
+	dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
+endmodule
+
+module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q);
+	input  C;
+	input  S;
+	input  R;
+	input  E;
+	input  D;
+	output Q;
+	dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
+endmodule
+
+// DFF, synchronous set or reset, enable
+module \$_SDFFE_PN0P_ (D, C, R, E, Q);
+	input  D;
+	input  C;
+	input  R;
+	input  E;
+	output Q;
+	sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1));
+endmodule
+
+module \$_SDFFE_PN1P_ (D, C, R, E, Q);
+	input  D;
+	input  C;
+	input  R;
+	input  E;
+	output Q;
+	sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R));
+endmodule
+
+module \$_SDFFE_NN0P_ (D, C, R, E, Q);
+	input  D;
+	input  C;
+	input  R;
+	input  E;
+	output Q;
+	sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1));
+endmodule
+
+module \$_SDFFE_NN1P_ (D, C, R, E, Q);
+	input  D;
+	input  C;
+	input  R;
+	input  E;
+	output Q;
+	sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R));
+endmodule
+
+// Latch, no set/reset, no enable
+module  \$_DLATCH_P_ (input E, D, output Q);
+	latchsre  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1));
+endmodule
+
+module  \$_DLATCH_N_ (input E, D, output Q);
+	latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1));
+endmodule
+
+// Latch with async set and reset and enable
+module  \$_DLATCHSR_PPP_ (input E, S, R, D, output Q);
+	latchsre  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E),  .R(!R), .S(!S));
+endmodule
+
+module  \$_DLATCHSR_NPP_ (input E, S, R, D, output Q);
+	latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E),  .R(!R), .S(!S));
+endmodule
+
+module \$__SHREG_DFF_P_ (D, Q, C);
+	input  D;
+	input  C;
+	output Q;
+
+	parameter DEPTH = 2;
+
+	reg [DEPTH-2:0] q;
+
+	genvar i;
+	generate for (i = 0; i < DEPTH; i = i + 1) begin: slice
+
+		// First in chain
+		generate if (i == 0) begin
+				 sh_dff #() shreg_beg (
+					.Q(q[i]),
+					.D(D),
+					.C(C)
+				);
+		end endgenerate
+		// Middle in chain
+		generate if (i > 0 && i != DEPTH-1) begin
+				 sh_dff #() shreg_mid (
+					.Q(q[i]),
+					.D(q[i-1]),
+					.C(C)
+				);
+		end endgenerate
+		// Last in chain
+		generate if (i == DEPTH-1) begin
+				 sh_dff #() shreg_end (
+					.Q(Q),
+					.D(q[i-1]),
+					.C(C)
+				);
+		end endgenerate
+   end: slice
+   endgenerate
+
+endmodule
+
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py b/yosys/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py
new file mode 100644
index 00000000000..e57c04a0887
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py
@@ -0,0 +1,248 @@
+import sys
+from datetime import datetime, timezone
+
+def generate(filename):
+	with open(filename, "w") as f:
+		f.write("// **AUTOGENERATED FILE** **DO NOT EDIT**\n")
+		f.write(f"// Generated by {sys.argv[0]} at {datetime.now(timezone.utc)}\n")
+
+		f.write("`timescale 1ns /10ps\n")
+		for a_width in [1,2,4,9,18,36]:
+			for b_width in [1,2,4,9,18,36]:
+				f.write(f"""
+module TDP36K_BRAM_A_X{a_width}_B_X{b_width}_nonsplit (
+	RESET_ni,
+	WEN_A1_i,   WEN_B1_i,
+	REN_A1_i,   REN_B1_i,
+	CLK_A1_i,   CLK_B1_i,
+	BE_A1_i,    BE_B1_i,
+	ADDR_A1_i,  ADDR_B1_i,
+	WDATA_A1_i, WDATA_B1_i,
+	RDATA_A1_o, RDATA_B1_o,
+	FLUSH1_i,
+	WEN_A2_i,   WEN_B2_i,
+	REN_A2_i,   REN_B2_i,
+	CLK_A2_i,   CLK_B2_i,
+	BE_A2_i,    BE_B2_i,
+	ADDR_A2_i,  ADDR_B2_i,
+	WDATA_A2_i, WDATA_B2_i,
+	RDATA_A2_o, RDATA_B2_o,
+	FLUSH2_i
+	);
+
+	parameter [80:0] MODE_BITS = 81'd0;
+	parameter [1024*36-1:0] RAM_INIT = 36864'bx;
+
+	input  wire RESET_ni;
+	input  wire WEN_A1_i, WEN_B1_i;
+	input  wire REN_A1_i, REN_B1_i;
+	input  wire WEN_A2_i, WEN_B2_i;
+	input  wire REN_A2_i, REN_B2_i;
+
+	(* clkbuf_sink *)
+	input  wire CLK_A1_i;
+	(* clkbuf_sink *)
+	input  wire CLK_B1_i;
+	(* clkbuf_sink *)
+	input  wire CLK_A2_i;
+	(* clkbuf_sink *)
+	input  wire CLK_B2_i;
+
+	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+	output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+	input  wire FLUSH1_i;
+
+	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+	output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+	input  wire FLUSH2_i;
+
+	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
+		.RESET_ni   (RESET_ni),
+		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+		.FLUSH1_i   (FLUSH1_i),
+		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+		.FLUSH2_i   (FLUSH2_i)
+	);
+
+	`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+	`endif
+endmodule
+""")
+
+		for a1_width in [1,2,4,9,18]:
+			for b1_width in [1,2,4,9,18]:
+				for a2_width in [1,2,4,9,18]:
+					for b2_width in [1,2,4,9,18]:
+						f.write(f"""
+module TDP36K_BRAM_A1_X{a1_width}_B1_X{b1_width}_A2_X{a2_width}_B2_X{b2_width}_split (
+	RESET_ni,
+	WEN_A1_i,   WEN_B1_i,
+	REN_A1_i,   REN_B1_i,
+	CLK_A1_i,   CLK_B1_i,
+	BE_A1_i,    BE_B1_i,
+	ADDR_A1_i,  ADDR_B1_i,
+	WDATA_A1_i, WDATA_B1_i,
+	RDATA_A1_o, RDATA_B1_o,
+	FLUSH1_i,
+	WEN_A2_i,   WEN_B2_i,
+	REN_A2_i,   REN_B2_i,
+	CLK_A2_i,   CLK_B2_i,
+	BE_A2_i,    BE_B2_i,
+	ADDR_A2_i,  ADDR_B2_i,
+	WDATA_A2_i, WDATA_B2_i,
+	RDATA_A2_o, RDATA_B2_o,
+	FLUSH2_i
+	);
+
+	parameter [80:0] MODE_BITS = 81'd0;
+	parameter [1024*36-1:0] RAM_INIT = 36864'bx;
+
+	input  wire RESET_ni;
+	input  wire WEN_A1_i, WEN_B1_i;
+	input  wire REN_A1_i, REN_B1_i;
+	input  wire WEN_A2_i, WEN_B2_i;
+	input  wire REN_A2_i, REN_B2_i;
+
+	(* clkbuf_sink *)
+	input  wire CLK_A1_i;
+	(* clkbuf_sink *)
+	input  wire CLK_B1_i;
+	(* clkbuf_sink *)
+	input  wire CLK_A2_i;
+	(* clkbuf_sink *)
+	input  wire CLK_B2_i;
+
+	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
+	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
+	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
+	output wire [17:0] RDATA_A1_o, RDATA_B1_o;
+
+	input  wire FLUSH1_i;
+
+	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
+	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
+	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
+	output wire [17:0] RDATA_A2_o, RDATA_B2_o;
+
+	input  wire FLUSH2_i;
+
+	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
+		.RESET_ni   (RESET_ni),
+		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
+		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
+		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
+		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
+		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
+		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
+		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
+		.FLUSH1_i   (FLUSH1_i),
+		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
+		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
+		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
+		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
+		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
+		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
+		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
+		.FLUSH2_i   (FLUSH2_i)
+	);
+
+	`ifdef SDF_SIM
+	specify
+		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
+		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
+		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
+		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
+		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
+		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
+		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
+		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
+		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
+		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
+	endspecify
+	`endif
+endmodule
+""")
+
+if __name__ == "__main__":
+	filename = "bram_types_sim.v"
+	if len(sys.argv) > 1:
+		filename = sys.argv[1]
+	generate(filename)
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt b/yosys/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt
new file mode 100644
index 00000000000..3317956f822
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt
@@ -0,0 +1,22 @@
+ram block $__QLF_TDP36K {
+	init any;
+	byte 9;
+	option "SPLIT" 0 {
+		abits 15;
+		widths 1 2 4 9 18 36 per_port;
+	}
+	option "SPLIT" 1 {
+		abits 14;
+		widths 1 2 4 9 18 per_port;
+	}
+	cost 65;
+	port srsw "A" "B" {
+		width tied;
+		clock posedge;
+		# wen causes read even when ren is low
+		# map clken = wen || ren
+		clken;
+		wrbe_separate;
+		rdwr old;
+	}
+}
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v b/yosys/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v
new file mode 100644
index 00000000000..3a5641bb880
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v
@@ -0,0 +1,483 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+module \$__QLF_TDP36K (PORT_A_CLK, PORT_A_ADDR, PORT_A_WR_DATA, PORT_A_WR_EN, PORT_A_WR_BE, PORT_A_CLK_EN, PORT_A_RD_DATA,
+					   PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA);  
+
+parameter INIT = 0;
+
+parameter OPTION_SPLIT = 0;
+
+parameter PORT_A_WIDTH = 1;
+parameter PORT_A_WR_BE_WIDTH = 1;
+
+parameter PORT_B_WIDTH = 1;
+parameter PORT_B_WR_BE_WIDTH = 1;
+
+input PORT_A_CLK;
+input [14:0] PORT_A_ADDR;
+input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
+input PORT_A_WR_EN;
+input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
+input PORT_A_CLK_EN;
+output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
+
+input PORT_B_CLK;
+input [14:0] PORT_B_ADDR;
+input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
+input PORT_B_WR_EN;
+input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
+input PORT_B_CLK_EN;
+output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
+
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+32, 36: mode = 3'b011;
+default: mode = 3'b000;
+endcase
+endfunction
+
+function [36863:0] pack_init;
+	integer i;
+	reg [35:0] ri;
+	for (i = 0; i < (OPTION_SPLIT ? 512 : 1024); i = i + 1) begin
+		ri = INIT[i*36 +: 36];
+		pack_init[i*36 +: 36] = {ri[35], ri[26], ri[34:27], ri[25:18],
+								 ri[17], ri[8], ri[16:9], ri[7:0]};
+	end
+	if (OPTION_SPLIT)
+		pack_init[36863:18432] = 18432'bx;
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(PORT_A_WIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(PORT_A_WIDTH);
+localparam [ 2:0] RMODE_A2_i    = mode(PORT_A_WIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(PORT_A_WIDTH);
+
+localparam [ 2:0] RMODE_B1_i    = mode(PORT_B_WIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(PORT_B_WIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(PORT_B_WIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(PORT_B_WIDTH);
+
+assign REN_A1_i = PORT_A_CLK_EN;
+assign WEN_A1_i = PORT_A_CLK_EN & PORT_A_WR_EN;
+assign {BE_A2_i, BE_A1_i} = PORT_A_WR_BE;
+
+assign REN_B1_i = PORT_B_CLK_EN;
+assign WEN_B1_i = PORT_B_CLK_EN & PORT_B_WR_EN;
+assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE;
+
+case (PORT_A_WIDTH)
+9: assign { WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A_WR_DATA;
+18: assign { WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A_WR_DATA;
+36: assign { WDATA_A2_i[17], WDATA_A2_i[15:8], WDATA_A2_i[16], WDATA_A2_i[7:0], WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0]} = PORT_A_WR_DATA;
+default: assign WDATA_A1_i = PORT_A_WR_DATA; // 1,2,4
+endcase
+
+case (PORT_B_WIDTH)
+9: assign { WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B_WR_DATA;
+18: assign { WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B_WR_DATA;
+36: assign { WDATA_B2_i[17], WDATA_B2_i[15:8], WDATA_B2_i[16], WDATA_B2_i[7:0], WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0]} = PORT_B_WR_DATA;
+default: assign WDATA_B1_i = PORT_B_WR_DATA; // 1,2,4
+endcase
+
+case (PORT_A_WIDTH)
+9: assign PORT_A_RD_DATA = { RDATA_A1_o[16], RDATA_A1_o[7:0] };
+18: assign PORT_A_RD_DATA = { RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0] };
+36: assign PORT_A_RD_DATA = { RDATA_A2_o[17], RDATA_A2_o[15:8], RDATA_A2_o[16], RDATA_A2_o[7:0], RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0]};
+default: assign PORT_A_RD_DATA = RDATA_A1_o; // 1,2,4
+endcase
+
+case (PORT_B_WIDTH)
+9: assign PORT_B_RD_DATA = { RDATA_B1_o[16], RDATA_B1_o[7:0] };
+18: assign PORT_B_RD_DATA = { RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0] };
+36: assign PORT_B_RD_DATA = { RDATA_B2_o[17], RDATA_B2_o[15:8], RDATA_B2_o[16], RDATA_B2_o[7:0], RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0]};
+default: assign PORT_B_RD_DATA = RDATA_B1_o; // 1,2,4
+endcase
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
+	UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+	UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+};
+
+(* is_inferred = 1 *)
+(* is_split = 0 *)
+(* was_split_candidate = OPTION_SPLIT *)
+(* port_a_width = PORT_A_WIDTH *)
+(* port_b_width = PORT_B_WIDTH *)
+TDP36K #(
+	.RAM_INIT(pack_init()),
+) _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+
+	.CLK_A1_i(PORT_A_CLK),
+	.ADDR_A1_i(PORT_A_ADDR),
+	.WEN_A1_i(WEN_A1_i),
+	.BE_A1_i(BE_A1_i),
+	.WDATA_A1_i(WDATA_A1_i),
+	.REN_A1_i(REN_A1_i),
+	.RDATA_A1_o(RDATA_A1_o),
+
+	.CLK_A2_i(PORT_A_CLK),
+	.ADDR_A2_i(PORT_A_ADDR[13:0]),
+	.WEN_A2_i(WEN_A1_i),
+	.BE_A2_i(BE_A2_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.REN_A2_i(REN_A1_i),
+	.RDATA_A2_o(RDATA_A2_o),
+
+	.CLK_B1_i(PORT_B_CLK),
+	.ADDR_B1_i(PORT_B_ADDR),
+	.WEN_B1_i(WEN_B1_i),
+	.BE_B1_i(BE_B1_i),
+	.WDATA_B1_i(WDATA_B1_i),
+	.REN_B1_i(REN_B1_i),
+	.RDATA_B1_o(RDATA_B1_o),
+
+	.CLK_B2_i(PORT_B_CLK),
+	.ADDR_B2_i(PORT_B_ADDR[13:0]),
+	.WEN_B2_i(WEN_B1_i),
+	.BE_B2_i(BE_B2_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.REN_B2_i(REN_B1_i),
+	.RDATA_B2_o(RDATA_B2_o),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
+
+
+module \$__QLF_TDP36K_MERGED (...);
+
+parameter INIT1 = 0;
+
+parameter PORT_A1_WIDTH = 1;
+parameter PORT_B1_WIDTH = 1;
+
+parameter PORT_A1_WR_BE_WIDTH = 1;
+parameter PORT_B1_WR_BE_WIDTH = 1;
+
+input PORT_A1_CLK;
+input [14:0] PORT_A1_ADDR;
+input [PORT_A1_WIDTH-1:0] PORT_A1_WR_DATA;
+input PORT_A1_WR_EN;
+input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE;
+input PORT_A1_CLK_EN;
+output [PORT_A1_WIDTH-1:0] PORT_A1_RD_DATA;
+
+input PORT_B1_CLK;
+input [14:0] PORT_B1_ADDR;
+input [PORT_B1_WIDTH-1:0] PORT_B1_WR_DATA;
+input PORT_B1_WR_EN;
+input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE;
+input PORT_B1_CLK_EN;
+output [PORT_B1_WIDTH-1:0] PORT_B1_RD_DATA;
+
+parameter INIT2 = 0;
+
+parameter PORT_A2_WIDTH = 1;
+parameter PORT_B2_WIDTH = 1;
+parameter PORT_A2_WR_BE_WIDTH = 1;
+parameter PORT_B2_WR_BE_WIDTH = 1;
+
+input PORT_A2_CLK;
+input [14:0] PORT_A2_ADDR;
+input [PORT_A2_WIDTH-1:0] PORT_A2_WR_DATA;
+input PORT_A2_WR_EN;
+input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE;
+input PORT_A2_CLK_EN;
+output [PORT_A2_WIDTH-1:0] PORT_A2_RD_DATA;
+
+input PORT_B2_CLK;
+input [14:0] PORT_B2_ADDR;
+input [PORT_B2_WIDTH-1:0] PORT_B2_WR_DATA;
+input PORT_B2_WR_EN;
+input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE;
+input PORT_B2_CLK_EN;
+output [PORT_B2_WIDTH-1:0] PORT_B2_RD_DATA;
+
+
+// Fixed mode settings
+localparam [ 0:0] SYNC_FIFO1_i  = 1'd0;
+localparam [ 0:0] FMODE1_i      = 1'd0;
+localparam [ 0:0] POWERDN1_i    = 1'd0;
+localparam [ 0:0] SLEEP1_i      = 1'd0;
+localparam [ 0:0] PROTECT1_i    = 1'd0;
+localparam [11:0] UPAE1_i       = 12'd10;
+localparam [11:0] UPAF1_i       = 12'd10;
+
+localparam [ 0:0] SYNC_FIFO2_i  = 1'd0;
+localparam [ 0:0] FMODE2_i      = 1'd0;
+localparam [ 0:0] POWERDN2_i    = 1'd0;
+localparam [ 0:0] SLEEP2_i      = 1'd0;
+localparam [ 0:0] PROTECT2_i    = 1'd0;
+localparam [10:0] UPAE2_i       = 11'd10;
+localparam [10:0] UPAF2_i       = 11'd10;
+
+// Width mode function
+function [2:0] mode;
+input integer width;
+case (width)
+1: mode = 3'b101;
+2: mode = 3'b110;
+4: mode = 3'b100;
+8,9: mode = 3'b001;
+16, 18: mode = 3'b010;
+default: mode = 3'b000;
+endcase
+endfunction
+
+function [36863:0] pack_init;
+	integer i;
+	reg [35:0] ri;
+	for (i = 0; i < 1024; i = i + 1) begin
+		ri = {INIT2[i*18 +: 18], INIT1[i*18 +: 18]};
+		pack_init[i*36 +: 36] = {ri[35], ri[26], ri[34:27], ri[25:18], ri[17], ri[8], ri[16:9], ri[7:0]};
+	end
+endfunction
+
+wire REN_A1_i;
+wire REN_A2_i;
+
+wire REN_B1_i;
+wire REN_B2_i;
+
+wire WEN_A1_i;
+wire WEN_A2_i;
+
+wire WEN_B1_i;
+wire WEN_B2_i;
+
+wire [1:0] BE_A1_i;
+wire [1:0] BE_A2_i;
+
+wire [1:0] BE_B1_i;
+wire [1:0] BE_B2_i;
+
+wire [14:0] ADDR_A1_i;
+wire [13:0] ADDR_A2_i;
+
+wire [14:0] ADDR_B1_i;
+wire [13:0] ADDR_B2_i;
+
+wire [17:0] WDATA_A1_i;
+wire [17:0] WDATA_A2_i;
+
+wire [17:0] WDATA_B1_i;
+wire [17:0] WDATA_B2_i;
+
+wire [17:0] RDATA_A1_o;
+wire [17:0] RDATA_A2_o;
+
+wire [17:0] RDATA_B1_o;
+wire [17:0] RDATA_B2_o;
+
+
+// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
+localparam [ 2:0] RMODE_A1_i    = mode(PORT_A1_WIDTH);
+localparam [ 2:0] WMODE_A1_i    = mode(PORT_A1_WIDTH);
+localparam [ 2:0] RMODE_B1_i    = mode(PORT_B1_WIDTH);
+localparam [ 2:0] WMODE_B1_i    = mode(PORT_B1_WIDTH);
+
+localparam [ 2:0] RMODE_A2_i    = mode(PORT_A2_WIDTH);
+localparam [ 2:0] WMODE_A2_i    = mode(PORT_A2_WIDTH);
+localparam [ 2:0] RMODE_B2_i    = mode(PORT_B2_WIDTH);
+localparam [ 2:0] WMODE_B2_i    = mode(PORT_B2_WIDTH);
+
+assign REN_A1_i = PORT_A1_CLK_EN;
+assign WEN_A1_i = PORT_A1_CLK_EN & PORT_A1_WR_EN;
+assign BE_A1_i = PORT_A1_WR_BE;
+
+assign REN_B1_i = PORT_B1_CLK_EN;
+assign WEN_B1_i = PORT_B1_CLK_EN & PORT_B1_WR_EN;
+assign BE_B1_i = PORT_B1_WR_BE;
+
+assign REN_A2_i = PORT_A2_CLK_EN;
+assign WEN_A2_i = PORT_A2_CLK_EN & PORT_A2_WR_EN;
+assign BE_A2_i = PORT_A2_WR_BE;
+
+assign REN_B2_i = PORT_B2_CLK_EN;
+assign WEN_B2_i = PORT_B2_CLK_EN & PORT_B2_WR_EN;
+assign BE_B2_i = PORT_B2_WR_BE;
+
+assign ADDR_A1_i = PORT_A1_ADDR;
+assign ADDR_B1_i = PORT_B1_ADDR;
+assign ADDR_A2_i = PORT_A2_ADDR;
+assign ADDR_B2_i = PORT_B2_ADDR;
+
+case (PORT_A1_WIDTH)
+9: assign { WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A1_WR_DATA;
+18: assign { WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A1_WR_DATA;
+default: assign WDATA_A1_i = PORT_A1_WR_DATA; // 1,2,4,8,16
+endcase
+
+case (PORT_B1_WIDTH)
+9: assign { WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B1_WR_DATA;
+18: assign { WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B1_WR_DATA;
+default: assign WDATA_B1_i = PORT_B1_WR_DATA; // 1,2,4,8,16
+endcase
+
+case (PORT_A1_WIDTH)
+9: assign PORT_A1_RD_DATA = { RDATA_A1_o[16], RDATA_A1_o[7:0] };
+18: assign PORT_A1_RD_DATA = { RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0] };
+default: assign PORT_A1_RD_DATA = RDATA_A1_o; // 1,2,4,8,16
+endcase
+
+case (PORT_B1_WIDTH)
+9: assign PORT_B1_RD_DATA = { RDATA_B1_o[16], RDATA_B1_o[7:0] };
+18: assign PORT_B1_RD_DATA = { RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0] };
+default: assign PORT_B1_RD_DATA = RDATA_B1_o; // 1,2,4,8,16
+endcase
+
+case (PORT_A2_WIDTH)
+9: assign { WDATA_A2_i[16], WDATA_A2_i[7:0] } = PORT_A2_WR_DATA;
+18: assign { WDATA_A2_i[17], WDATA_A2_i[15:8], WDATA_A2_i[16], WDATA_A2_i[7:0] } = PORT_A2_WR_DATA;
+default: assign WDATA_A2_i = PORT_A2_WR_DATA; // 1,2,4,8,16
+endcase
+
+case (PORT_B2_WIDTH)
+9: assign { WDATA_B2_i[16], WDATA_B2_i[7:0] } = PORT_B2_WR_DATA;
+18: assign { WDATA_B2_i[17], WDATA_B2_i[15:8], WDATA_B2_i[16], WDATA_B2_i[7:0] } = PORT_B2_WR_DATA;
+default: assign WDATA_B2_i = PORT_B2_WR_DATA; // 1,2,4,8,16
+endcase
+
+case (PORT_A2_WIDTH)
+9: assign PORT_A2_RD_DATA = { RDATA_A2_o[16], RDATA_A2_o[7:0] };
+18: assign PORT_A2_RD_DATA = { RDATA_A2_o[17], RDATA_A2_o[15:8], RDATA_A2_o[16], RDATA_A2_o[7:0] };
+default: assign PORT_A2_RD_DATA = RDATA_A2_o; // 1,2,4,8,16
+endcase
+
+case (PORT_B2_WIDTH)
+9: assign PORT_B2_RD_DATA = { RDATA_B2_o[16], RDATA_B2_o[7:0] };
+18: assign PORT_B2_RD_DATA = { RDATA_B2_o[17], RDATA_B2_o[15:8], RDATA_B2_o[16], RDATA_B2_o[7:0] };
+default: assign PORT_B2_RD_DATA = RDATA_B2_o; // 1,2,4,8,16
+endcase
+
+defparam _TECHMAP_REPLACE_.MODE_BITS = {1'b1,
+			UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
+			UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
+		};
+
+(* is_inferred = 1 *)
+(* is_split = 1 *)
+(* port_a1_width = PORT_A1_WIDTH *)
+(* port_a2_width = PORT_A2_WIDTH *)
+(* port_b1_width = PORT_B1_WIDTH *)
+(* port_b2_width = PORT_B2_WIDTH *)
+TDP36K #(
+	.RAM_INIT(pack_init()),
+) _TECHMAP_REPLACE_ (
+	.RESET_ni(1'b1),
+	.WDATA_A1_i(WDATA_A1_i),
+	.WDATA_A2_i(WDATA_A2_i),
+	.RDATA_A1_o(RDATA_A1_o),
+	.RDATA_A2_o(RDATA_A2_o),
+	.ADDR_A1_i(ADDR_A1_i),
+	.ADDR_A2_i(ADDR_A2_i),
+	.CLK_A1_i(PORT_A1_CLK),
+	.CLK_A2_i(PORT_A2_CLK),
+	.REN_A1_i(REN_A1_i),
+	.REN_A2_i(REN_A2_i),
+	.WEN_A1_i(WEN_A1_i),
+	.WEN_A2_i(WEN_A2_i),
+	.BE_A1_i(BE_A1_i),
+	.BE_A2_i(BE_A2_i),
+
+	.WDATA_B1_i(WDATA_B1_i),
+	.WDATA_B2_i(WDATA_B2_i),
+	.RDATA_B1_o(RDATA_B1_o),
+	.RDATA_B2_o(RDATA_B2_o),
+	.ADDR_B1_i(ADDR_B1_i),
+	.ADDR_B2_i(ADDR_B2_i),
+	.CLK_B1_i(PORT_B1_CLK),
+	.CLK_B2_i(PORT_B2_CLK),
+	.REN_B1_i(REN_B1_i),
+	.REN_B2_i(REN_B2_i),
+	.WEN_B1_i(WEN_B1_i),
+	.WEN_B2_i(WEN_B2_i),
+	.BE_B1_i(BE_B1_i),
+	.BE_B2_i(BE_B2_i),
+
+	.FLUSH1_i(1'b0),
+	.FLUSH2_i(1'b0)
+);
+
+endmodule
\ No newline at end of file
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v b/yosys/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v
new file mode 100644
index 00000000000..86698ffefd3
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v
@@ -0,0 +1,64 @@
+`default_nettype none
+module sram1024x18 (
+	clk_a,
+	cen_a,
+	wen_a,
+	addr_a,
+	wmsk_a,
+	wdata_a,
+	rdata_a,
+	clk_b,
+	cen_b,
+	wen_b,
+	addr_b,
+	wmsk_b,
+	wdata_b,
+	rdata_b
+);
+	parameter [1024*18-1:0] init = 18431'bx;
+	(* clkbuf_sink *)
+	input wire clk_a;
+	input wire cen_a;
+	input wire wen_a;
+	input wire [9:0] addr_a;
+	input wire [17:0] wmsk_a;
+	input wire [17:0] wdata_a;
+	output reg [17:0] rdata_a;
+	(* clkbuf_sink *)
+	input wire clk_b;
+	input wire cen_b;
+	input wire wen_b;
+	input wire [9:0] addr_b;
+	input wire [17:0] wmsk_b;
+	input wire [17:0] wdata_b;
+	output reg [17:0] rdata_b;
+	reg [17:0] ram [1023:0];
+	integer i;
+	initial begin
+		for (i = 0; i < 1024; i = i + 1) begin
+			ram[i] = init[18*i +: 18];
+		end
+	end
+
+	always @(posedge clk_a) begin
+		if (!cen_a) begin
+	 		if (!wen_a)
+				for (i = 0; i < 18; i++) begin
+					if (!wmsk_a[i]) ram[addr_a][i] <= wdata_a[i];
+				end
+			rdata_a <= ram[addr_a];
+		end
+	end
+
+	always @(posedge clk_b) begin
+		if (!cen_b) begin
+	 		if (!wen_b)
+				for (i = 0; i < 18; i++) begin
+					if (!wmsk_b[i]) ram[addr_b][i] <= wdata_b[i];
+				end
+			rdata_b <= ram[addr_b];
+		end
+	end
+
+endmodule
+
diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v b/yosys/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v
new file mode 100644
index 00000000000..441f6bc4a81
--- /dev/null
+++ b/yosys/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v
@@ -0,0 +1,620 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype wire
+module fifo_ctl (
+	raddr,
+	waddr,
+	fflags,
+	ren_o,
+	sync,
+	rmode,
+	wmode,
+	rclk,
+	rst_R_n,
+	wclk,
+	rst_W_n,
+	ren,
+	wen,
+	upaf,
+	upae
+);
+	parameter ADDR_WIDTH = 11;
+	parameter FIFO_WIDTH = 3'd2;
+	parameter DEPTH = 6;
+	output wire [ADDR_WIDTH - 1:0] raddr;
+	output wire [ADDR_WIDTH - 1:0] waddr;
+	output wire [7:0] fflags;
+	output wire ren_o;
+	input wire sync;
+	input wire [1:0] rmode;
+	input wire [1:0] wmode;
+	(* clkbuf_sink *)
+	input wire rclk;
+	input wire rst_R_n;
+	(* clkbuf_sink *)
+	input wire wclk;
+	input wire rst_W_n;
+	input wire ren;
+	input wire wen;
+	input wire [ADDR_WIDTH - 1:0] upaf;
+	input wire [ADDR_WIDTH - 1:0] upae;
+	localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1;
+	reg [ADDR_WIDTH:0] pushtopop1;
+	reg [ADDR_WIDTH:0] pushtopop2;
+	reg [ADDR_WIDTH:0] poptopush1;
+	reg [ADDR_WIDTH:0] poptopush2;
+	wire [ADDR_WIDTH:0] pushtopop0;
+	wire [ADDR_WIDTH:0] poptopush0;
+	wire [ADDR_WIDTH:0] smux_poptopush;
+	wire [ADDR_WIDTH:0] smux_pushtopop;
+	assign smux_poptopush = (sync ? poptopush0 : poptopush2);
+	assign smux_pushtopop = (sync ? pushtopop0 : pushtopop2);
+	always @(posedge rclk or negedge rst_R_n)
+		if (~rst_R_n) begin
+			pushtopop1 <= 'h0;
+			pushtopop2 <= 'h0;
+		end
+		else begin
+			pushtopop1 = pushtopop0;
+			pushtopop2 = pushtopop1;
+		end
+	always @(posedge wclk or negedge rst_W_n)
+		if (~rst_W_n) begin
+			poptopush1 <= 'h0;
+			poptopush2 <= 'h0;
+		end
+		else begin
+			poptopush1 <= poptopush0;
+			poptopush2 <= poptopush1;
+		end
+	fifo_push #(
+		.ADDR_WIDTH(ADDR_WIDTH),
+		.DEPTH(DEPTH)
+	) u_fifo_push(
+		.wclk(wclk),
+		.wen(wen),
+		.rst_n(rst_W_n),
+		.rmode(rmode),
+		.wmode(wmode),
+		.gcout(pushtopop0),
+		.gcin(smux_poptopush),
+		.ff_waddr(waddr),
+		.pushflags(fflags[7:4]),
+		.upaf(upaf)
+	);
+	fifo_pop #(
+		.ADDR_WIDTH(ADDR_WIDTH),
+		.FIFO_WIDTH(FIFO_WIDTH),
+		.DEPTH(DEPTH)
+	) u_fifo_pop(
+		.rclk(rclk),
+		.ren_in(ren),
+		.rst_n(rst_R_n),
+		.rmode(rmode),
+		.wmode(wmode),
+		.ren_o(ren_o),
+		.gcout(poptopush0),
+		.gcin(smux_pushtopop),
+		.out_raddr(raddr),
+		.popflags(fflags[3:0]),
+		.upae(upae)
+	);
+endmodule
+module fifo_push (
+	pushflags,
+	gcout,
+	ff_waddr,
+	rst_n,
+	wclk,
+	wen,
+	rmode,
+	wmode,
+	gcin,
+	upaf
+);
+	parameter ADDR_WIDTH = 11;
+	parameter DEPTH = 6;
+	output wire [3:0] pushflags;
+	output wire [ADDR_WIDTH:0] gcout;
+	output wire [ADDR_WIDTH - 1:0] ff_waddr;
+	input rst_n;
+	(* clkbuf_sink *)
+	input wclk;
+	input wen;
+	input [1:0] rmode;
+	input [1:0] wmode;
+	input [ADDR_WIDTH:0] gcin;
+	input [ADDR_WIDTH - 1:0] upaf;
+	localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1;
+	reg full_next;
+	reg full;
+	reg paf_next;
+	reg paf;
+	reg fmo;
+	reg fmo_next;
+	reg overflow;
+	reg p1;
+	reg p2;
+	reg f1;
+	reg f2;
+	reg q1;
+	reg q2;
+	reg [1:0] gmode;
+	reg [ADDR_WIDTH:0] waddr;
+	reg [ADDR_WIDTH:0] raddr;
+	reg [ADDR_WIDTH:0] gcout_reg;
+	reg [ADDR_WIDTH:0] gcout_next;
+	reg [ADDR_WIDTH:0] raddr_next;
+	reg [ADDR_WIDTH - 1:0] paf_thresh;
+	wire overflow_next;
+	wire [ADDR_WIDTH:0] waddr_next;
+	wire [ADDR_WIDTH:0] gc8out_next;
+	wire [ADDR_WIDTH - 1:0] gc16out_next;
+	wire [ADDR_WIDTH - 2:0] gc32out_next;
+	wire [ADDR_WIDTH:0] tmp;
+	wire [ADDR_WIDTH:0] next_count;
+	wire [ADDR_WIDTH:0] count;
+	wire [ADDR_WIDTH:0] fbytes;
+	genvar i;
+	assign next_count = fbytes - (waddr_next >= raddr_next ? waddr_next - raddr_next : (~raddr_next + waddr_next) + 1);
+	assign count = fbytes - (waddr >= raddr ? waddr - raddr : (~raddr + waddr) + 1);
+	assign fbytes = 1 << (DEPTH + 5);
+	always @(*) begin
+		paf_thresh = wmode[1] ? upaf : (wmode[0] ? upaf << 1 : upaf << 2);
+	end
+	always @(*)
+		case (wmode)
+			2'h0, 2'h1, 2'h2: begin
+				full_next = (wen ? f1 : f2);
+				fmo_next = (wen ? p1 : p2);
+				paf_next = (wen ? q1 : q2);
+			end
+			default: begin
+				full_next = 1'b0;
+				fmo_next = 1'b0;
+				paf_next = 1'b0;
+			end
+		endcase
+	always @(*) begin : PUSH_FULL_FLAGS
+		f1 = 1'b0;
+		f2 = 1'b0;
+		p1 = 1'b0;
+		p2 = 1'b0;
+		q1 = next_count < {1'b0, paf_thresh};
+		q2 = count < {1'b0, paf_thresh};
+		case (wmode)
+			2'h0:
+				case (DEPTH)
+					3'h6: begin
+						f1 = {~waddr_next[11], waddr_next[10:2]} == raddr_next[11:2];
+						f2 = {~waddr[11], waddr[10:2]} == raddr_next[11:2];
+						p1 = ((waddr_next[10:2] + 1) & 9'h1ff) == raddr_next[10:2];
+						p2 = ((waddr[10:2] + 1) & 9'h1ff) == raddr_next[10:2];
+					end
+					3'h5: begin
+						f1 = {~waddr_next[10], waddr_next[9:2]} == raddr_next[10:2];
+						f2 = {~waddr[10], waddr[9:2]} == raddr_next[10:2];
+						p1 = ((waddr_next[9:2] + 1) & 8'hff) == raddr_next[9:2];
+						p2 = ((waddr[9:2] + 1) & 8'hff) == raddr_next[9:2];
+					end
+					3'h4: begin
+						f1 = {~waddr_next[9], waddr_next[8:2]} == raddr_next[9:2];
+						f2 = {~waddr[9], waddr[8:2]} == raddr_next[9:2];
+						p1 = ((waddr_next[8:2] + 1) & 7'h7f) == raddr_next[8:2];
+						p2 = ((waddr[8:2] + 1) & 7'h7f) == raddr_next[8:2];
+					end
+					3'h3: begin
+						f1 = {~waddr_next[8], waddr_next[7:2]} == raddr_next[8:2];
+						f2 = {~waddr[8], waddr[7:2]} == raddr_next[8:2];
+						p1 = ((waddr_next[7:2] + 1) & 6'h3f) == raddr_next[7:2];
+						p2 = ((waddr[7:2] + 1) & 6'h3f) == raddr_next[7:2];
+					end
+					3'h2: begin
+						f1 = {~waddr_next[7], waddr_next[6:2]} == raddr_next[7:2];
+						f2 = {~waddr[7], waddr[6:2]} == raddr_next[7:2];
+						p1 = ((waddr_next[6:2] + 1) & 5'h1f) == raddr_next[6:2];
+						p2 = ((waddr[6:2] + 1) & 5'h1f) == raddr_next[6:2];
+					end
+					3'h1: begin
+						f1 = {~waddr_next[6], waddr_next[5:2]} == raddr_next[6:2];
+						f2 = {~waddr[6], waddr[5:2]} == raddr_next[6:2];
+						p1 = ((waddr_next[5:2] + 1) & 4'hf) == raddr_next[5:2];
+						p2 = ((waddr[5:2] + 1) & 4'hf) == raddr_next[5:2];
+					end
+					3'h0: begin
+						f1 = {~waddr_next[5], waddr_next[4:2]} == raddr_next[5:2];
+						f2 = {~waddr[5], waddr[4:2]} == raddr_next[5:2];
+						p1 = ((waddr_next[4:2] + 1) & 3'h7) == raddr_next[4:2];
+						p2 = ((waddr[4:2] + 1) & 3'h7) == raddr_next[4:2];
+					end
+					3'h7: begin
+						f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:2]} == raddr_next[ADDR_WIDTH:2];
+						f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:2]} == raddr_next[ADDR_WIDTH:2];
+						p1 = ((waddr_next[ADDR_WIDTH - 1:2] + 1) & {ADDR_WIDTH - 2 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:2];
+						p2 = ((waddr[ADDR_WIDTH - 1:2] + 1) & {ADDR_WIDTH - 2 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:2];
+					end
+				endcase
+			2'h1:
+				case (DEPTH)
+					3'h6: begin
+						f1 = {~waddr_next[11], waddr_next[10:1]} == raddr_next[11:1];
+						f2 = {~waddr[11], waddr[10:1]} == raddr_next[11:1];
+						p1 = ((waddr_next[10:1] + 1) & 10'h3ff) == raddr_next[10:1];
+						p2 = ((waddr[10:1] + 1) & 10'h3ff) == raddr_next[10:1];
+					end
+					3'h5: begin
+						f1 = {~waddr_next[10], waddr_next[9:1]} == raddr_next[10:1];
+						f2 = {~waddr[10], waddr[9:1]} == raddr_next[10:1];
+						p1 = ((waddr_next[9:1] + 1) & 9'h1ff) == raddr_next[9:1];
+						p2 = ((waddr[9:1] + 1) & 9'h1ff) == raddr_next[9:1];
+					end
+					3'h4: begin
+						f1 = {~waddr_next[9], waddr_next[8:1]} == raddr_next[9:1];
+						f2 = {~waddr[9], waddr[8:1]} == raddr_next[9:1];
+						p1 = ((waddr_next[8:1] + 1) & 8'hff) == raddr_next[8:1];
+						p2 = ((waddr[8:1] + 1) & 8'hff) == raddr_next[8:1];
+					end
+					3'h3: begin
+						f1 = {~waddr_next[8], waddr_next[7:1]} == raddr_next[8:1];
+						f2 = {~waddr[8], waddr[7:1]} == raddr_next[8:1];
+						p1 = ((waddr_next[7:1] + 1) & 7'h7f) == raddr_next[7:1];
+						p2 = ((waddr[7:1] + 1) & 7'h7f) == raddr_next[7:1];
+					end
+					3'h2: begin
+						f1 = {~waddr_next[7], waddr_next[6:1]} == raddr_next[7:1];
+						f2 = {~waddr[7], waddr[6:1]} == raddr_next[7:1];
+						p1 = ((waddr_next[6:1] + 1) & 6'h3f) == raddr_next[6:1];
+						p2 = ((waddr[6:1] + 1) & 6'h3f) == raddr_next[6:1];
+					end
+					3'h1: begin
+						f1 = {~waddr_next[6], waddr_next[5:1]} == raddr_next[6:1];
+						f2 = {~waddr[6], waddr[5:1]} == raddr_next[6:1];
+						p1 = ((waddr_next[5:1] + 1) & 5'h1f) == raddr_next[5:1];
+						p2 = ((waddr[5:1] + 1) & 5'h1f) == raddr_next[5:1];
+					end
+					3'h0: begin
+						f1 = {~waddr_next[5], waddr_next[4:1]} == raddr_next[5:1];
+						f2 = {~waddr[5], waddr[4:1]} == raddr_next[5:1];
+						p1 = ((waddr_next[4:1] + 1) & 4'hf) == raddr_next[4:1];
+						p2 = ((waddr[4:1] + 1) & 4'hf) == raddr_next[4:1];
+					end
+					3'h7: begin
+						f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:1]} == raddr_next[ADDR_WIDTH:1];
+						f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:1]} == raddr_next[ADDR_WIDTH:1];
+						p1 = ((waddr_next[ADDR_WIDTH - 1:1] + 1) & {ADDR_WIDTH - 1 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:1];
+						p2 = ((waddr[ADDR_WIDTH - 1:1] + 1) & {ADDR_WIDTH - 1 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:1];
+					end
+				endcase
+			2'h2:
+				case (DEPTH)
+					3'h6: begin
+						f1 = {~waddr_next[11], waddr_next[10:0]} == raddr_next[11:0];
+						f2 = {~waddr[11], waddr[10:0]} == raddr_next[11:0];
+						p1 = ((waddr_next[10:0] + 1) & 11'h7ff) == raddr_next[10:0];
+						p2 = ((waddr[10:0] + 1) & 11'h7ff) == raddr_next[10:0];
+					end
+					3'h5: begin
+						f1 = {~waddr_next[10], waddr_next[9:0]} == raddr_next[10:0];
+						f2 = {~waddr[10], waddr[9:0]} == raddr_next[10:0];
+						p1 = ((waddr_next[9:0] + 1) & 10'h3ff) == raddr_next[9:0];
+						p2 = ((waddr[9:0] + 1) & 10'h3ff) == raddr_next[9:0];
+					end
+					3'h4: begin
+						f1 = {~waddr_next[9], waddr_next[8:0]} == raddr_next[9:0];
+						f2 = {~waddr[9], waddr[8:0]} == raddr_next[9:0];
+						p1 = ((waddr_next[8:0] + 1) & 9'h1ff) == raddr_next[8:0];
+						p2 = ((waddr[8:0] + 1) & 9'h1ff) == raddr_next[8:0];
+					end
+					3'h3: begin
+						f1 = {~waddr_next[8], waddr_next[7:0]} == raddr_next[8:0];
+						f2 = {~waddr[8], waddr[7:0]} == raddr_next[8:0];
+						p1 = ((waddr_next[7:0] + 1) & 8'hff) == raddr_next[7:0];
+						p2 = ((waddr[7:0] + 1) & 8'hff) == raddr_next[7:0];
+					end
+					3'h2: begin
+						f1 = {~waddr_next[7], waddr_next[6:0]} == raddr_next[7:0];
+						f2 = {~waddr[7], waddr[6:0]} == raddr_next[7:0];
+						p1 = ((waddr_next[6:0] + 1) & 7'h7f) == raddr_next[6:0];
+						p2 = ((waddr[6:0] + 1) & 7'h7f) == raddr_next[6:0];
+					end
+					3'h1: begin
+						f1 = {~waddr_next[6], waddr_next[5:0]} == raddr_next[6:0];
+						f2 = {~waddr[6], waddr[5:0]} == raddr_next[6:0];
+						p1 = ((waddr_next[5:0] + 1) & 6'h3f) == raddr_next[5:0];
+						p2 = ((waddr[5:0] + 1) & 6'h3f) == raddr_next[5:0];
+					end
+					3'h0: begin
+						f1 = {~waddr_next[5], waddr_next[4:0]} == raddr_next[5:0];
+						f2 = {~waddr[5], waddr[4:0]} == raddr_next[5:0];
+						p1 = ((waddr_next[4:0] + 1) & 5'h1f) == raddr_next[4:0];
+						p2 = ((waddr[4:0] + 1) & 5'h1f) == raddr_next[4:0];
+					end
+					3'h7: begin
+						f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:0]} == raddr_next[ADDR_WIDTH:0];
+						f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:0]} == raddr_next[ADDR_WIDTH:0];
+						p1 = ((waddr_next[ADDR_WIDTH - 1:0] + 1) & {ADDR_WIDTH {1'b1}}) == raddr_next[ADDR_WIDTH - 1:0];
+						p2 = ((waddr[ADDR_WIDTH - 1:0] + 1) & {ADDR_WIDTH {1'b1}}) == raddr_next[ADDR_WIDTH - 1:0];
+					end
+				endcase
+			2'h3: begin
+				f1 = 1'b0;
+				f2 = 1'b0;
+				p1 = 1'b0;
+				p2 = 1'b0;
+			end
+		endcase
+	end
+	always @(*)
+		case (wmode)
+			2'h0: gmode = 2'h0;
+			2'h1: gmode = (rmode == 2'h0 ? 2'h0 : 2'h1);
+			2'h2: gmode = (rmode == 2'h2 ? 2'h2 : rmode);
+			2'h3: gmode = 2'h3;
+		endcase
+	assign gc8out_next = (waddr_next >> 1) ^ waddr_next;
+	assign gc16out_next = (waddr_next >> 2) ^ (waddr_next >> 1);
+	assign gc32out_next = (waddr_next >> 3) ^ (waddr_next >> 2);
+	always @(*)
+		if (wen)
+			case (gmode)
+				2'h2: gcout_next = gc8out_next;
+				2'h1: gcout_next = {1'b0, gc16out_next};
+				2'h0: gcout_next = {2'b00, gc32out_next};
+				default: gcout_next = {ADDR_PLUS_ONE {1'b0}};
+			endcase
+		else
+			gcout_next = {ADDR_PLUS_ONE {1'b0}};
+	always @(posedge wclk or negedge rst_n)
+		if (~rst_n) begin
+			full <= 1'b0;
+			fmo <= 1'b0;
+			paf <= 1'b0;
+			raddr <= {ADDR_PLUS_ONE {1'b0}};
+		end
+		else begin
+			full <= full_next;
+			fmo <= fmo_next;
+			paf <= paf_next;
+			case (gmode)
+				0: raddr <= raddr_next & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00};
+				1: raddr <= raddr_next & {{ADDR_WIDTH {1'b1}}, 1'b0};
+				2: raddr <= raddr_next & {ADDR_WIDTH + 1 {1'b1}};
+				3: raddr <= 12'h000;
+			endcase
+		end
+	assign overflow_next = full & wen;
+	always @(posedge wclk or negedge rst_n)
+		if (~rst_n)
+			overflow <= 1'b0;
+		else if (wen == 1'b1)
+			overflow <= overflow_next;
+	always @(posedge wclk or negedge rst_n)
+		if (~rst_n) begin
+			waddr <= {ADDR_WIDTH + 1 {1'b0}};
+			gcout_reg <= {ADDR_WIDTH + 1 {1'b0}};
+		end
+		else if (wen == 1'b1) begin
+			waddr <= waddr_next;
+			gcout_reg <= gcout_next;
+		end
+	assign gcout = gcout_reg;
+	generate
+		for (i = 0; i < (ADDR_WIDTH + 1); i = i + 1) begin : genblk1
+			assign tmp[i] = ^(gcin >> i);
+		end
+	endgenerate
+	always @(*)
+		case (gmode)
+			2'h0: raddr_next = {tmp[ADDR_WIDTH - 2:0], 2'b00} & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00};
+			2'h1: raddr_next = {tmp[ADDR_WIDTH - 1:0], 1'b0} & {{ADDR_WIDTH {1'b1}}, 1'b0};
+			2'h2: raddr_next = {tmp[ADDR_WIDTH:0]} & {ADDR_WIDTH + 1 {1'b1}};
+			default: raddr_next = {ADDR_WIDTH + 1 {1'b0}};
+		endcase
+	assign ff_waddr = waddr[ADDR_WIDTH - 1:0];
+	assign pushflags = {full, fmo, paf, overflow};
+	assign waddr_next = waddr + (wmode == 2'h0 ? 'h4 : (wmode == 2'h1 ? 'h2 : 'h1));
+endmodule
+module fifo_pop (
+	ren_o,
+	popflags,
+	out_raddr,
+	gcout,
+	rst_n,
+	rclk,
+	ren_in,
+	rmode,
+	wmode,
+	gcin,
+	upae
+);
+	parameter ADDR_WIDTH = 11;
+	parameter FIFO_WIDTH = 3'd2;
+	parameter DEPTH = 6;
+	output wire ren_o;
+	output wire [3:0] popflags;
+	output reg [ADDR_WIDTH - 1:0] out_raddr;
+	output wire [ADDR_WIDTH:0] gcout;
+	input rst_n;
+	(* clkbuf_sink *)
+	input rclk;
+	input ren_in;
+	input [1:0] rmode;
+	input [1:0] wmode;
+	input [ADDR_WIDTH:0] gcin;
+	input [ADDR_WIDTH - 1:0] upae;
+	localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1;
+	reg empty;
+	reg epo;
+	reg pae;
+	reg underflow;
+	reg e1;
+	reg e2;
+	reg o1;
+	reg o2;
+	reg q1;
+	reg q2;
+	reg [1:0] bwl_sel;
+	reg [1:0] gmode;
+	reg [ADDR_WIDTH - 1:0] ff_raddr;
+	reg [ADDR_WIDTH:0] waddr;
+	reg [ADDR_WIDTH:0] raddr;
+	reg [ADDR_WIDTH:0] gcout_reg;
+	reg [ADDR_WIDTH:0] gcout_next;
+	reg [ADDR_WIDTH:0] waddr_next;
+	reg [ADDR_WIDTH - 1:0] pae_thresh;
+	wire ren_out;
+	wire empty_next;
+	wire pae_next;
+	wire epo_next;
+	wire [ADDR_WIDTH - 2:0] gc32out_next;
+	wire [ADDR_WIDTH - 1:0] gc16out_next;
+	wire [ADDR_WIDTH:0] gc8out_next;
+	wire [ADDR_WIDTH:0] raddr_next;
+	wire [ADDR_WIDTH - 1:0] ff_raddr_next;
+	wire [ADDR_WIDTH:0] tmp;
+	wire [ADDR_PLUS_ONE:0] next_count;
+	wire [ADDR_PLUS_ONE:0] count;
+	wire [ADDR_PLUS_ONE:0] fbytes;
+	genvar i;
+	assign next_count = waddr - raddr_next;
+	assign count = waddr - raddr;
+	assign fbytes = 1 << (DEPTH + 5);
+	always @(*) pae_thresh = rmode[1] ? upae : (rmode[0] ? upae << 1 : upae << 2);
+	assign ren_out = (empty ? 1'b1 : ren_in);
+	always @(*)
+		case (rmode)
+			2'h0: gmode = 2'h0;
+			2'h1: gmode = (wmode == 2'h0 ? 2'h0 : 2'h1);
+			2'h2: gmode = (wmode == 2'h2 ? 2'h2 : wmode);
+			2'h3: gmode = 2'h3;
+		endcase
+	always @(*) begin
+		e1 = 1'b0;
+		e2 = 1'b0;
+		o1 = 1'b0;
+		o2 = 1'b0;
+		q1 = next_count < {1'b0, pae_thresh};
+		q2 = count < {1'b0, pae_thresh};
+		case (rmode)
+			2'h0: begin
+				e1 = raddr_next[ADDR_WIDTH:2] == waddr_next[ADDR_WIDTH:2];
+				e2 = raddr[ADDR_WIDTH:2] == waddr_next[ADDR_WIDTH:2];
+				o1 = (raddr_next[ADDR_WIDTH:2] + 1) == waddr_next[ADDR_WIDTH:2];
+				o2 = (raddr[ADDR_WIDTH:2] + 1) == waddr_next[ADDR_WIDTH:2];
+			end
+			2'h1: begin
+				e1 = raddr_next[ADDR_WIDTH:1] == waddr_next[ADDR_WIDTH:1];
+				e2 = raddr[ADDR_WIDTH:1] == waddr_next[ADDR_WIDTH:1];
+				o1 = (raddr_next[ADDR_WIDTH:1] + 1) == waddr_next[ADDR_WIDTH:1];
+				o2 = (raddr[ADDR_WIDTH:1] + 1) == waddr_next[ADDR_WIDTH:1];
+			end
+			2'h2: begin
+				e1 = raddr_next[ADDR_WIDTH:0] == waddr_next[ADDR_WIDTH:0];
+				e2 = raddr[ADDR_WIDTH:0] == waddr_next[ADDR_WIDTH:0];
+				o1 = (raddr_next[ADDR_WIDTH:0] + 1) == waddr_next[ADDR_WIDTH:0];
+				o2 = (raddr[ADDR_WIDTH:0] + 1) == waddr_next[11:0];
+			end
+			2'h3: begin
+				e1 = 1'b0;
+				e2 = 1'b0;
+				o1 = 1'b0;
+				o2 = 1'b0;
+			end
+		endcase
+	end
+	assign empty_next = (ren_in & !empty ? e1 : e2);
+	assign epo_next = (ren_in & !empty ? o1 : o2);
+	assign pae_next = (ren_in & !empty ? q1 : q2);
+	always @(posedge rclk or negedge rst_n)
+		if (~rst_n) begin
+			empty <= 1'b1;
+			pae <= 1'b1;
+			epo <= 1'b0;
+		end
+		else begin
+			empty <= empty_next;
+			pae <= pae_next;
+			epo <= epo_next;
+		end
+	assign gc8out_next = (raddr_next >> 1) ^ raddr_next;
+	assign gc16out_next = (raddr_next >> 2) ^ (raddr_next >> 1);
+	assign gc32out_next = (raddr_next >> 3) ^ (raddr_next >> 2);
+	always @(*)
+		if (ren_in)
+			case (gmode)
+				2'h2: gcout_next = gc8out_next;
+				2'h1: gcout_next = {1'b0, gc16out_next};
+				2'h0: gcout_next = {2'b00, gc32out_next};
+				default: gcout_next = 'h0;
+			endcase
+		else
+			gcout_next = 'h0;
+	always @(posedge rclk or negedge rst_n)
+		if (~rst_n)
+			waddr <= 12'h000;
+		else
+			waddr <= waddr_next;
+	always @(posedge rclk or negedge rst_n)
+		if (~rst_n) begin
+			underflow <= 1'b0;
+			bwl_sel <= 2'h0;
+			gcout_reg <= 12'h000;
+		end
+		else if (ren_in) begin
+			underflow <= empty;
+			if (!empty) begin
+				bwl_sel <= raddr_next[1:0];
+				gcout_reg <= gcout_next;
+			end
+		end
+	generate
+		for (i = 0; i < (ADDR_WIDTH + 1); i = i + 1) begin : genblk1
+			assign tmp[i] = ^(gcin >> i);
+		end
+	endgenerate
+	always @(*)
+		case (gmode)
+			2'h0: waddr_next = {tmp[ADDR_WIDTH - 2:0], 2'b00} & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00};
+			2'h1: waddr_next = {tmp[ADDR_WIDTH - 1:0], 1'b0} & {{ADDR_WIDTH {1'b1}}, 1'b0};
+			2'h2: waddr_next = {tmp[ADDR_WIDTH:0]} & {ADDR_PLUS_ONE {1'b1}};
+			default: waddr_next = {ADDR_PLUS_ONE {1'b0}};
+		endcase
+	assign ff_raddr_next = ff_raddr + (rmode == 2'h0 ? 'h4 : (rmode == 2'h1 ? 'h2 : 'h1));
+	assign raddr_next = raddr + (rmode == 2'h0 ? 'h4 : (rmode == 2'h1 ? 'h2 : 'h1));
+	always @(posedge rclk or negedge rst_n)
+		if (~rst_n)
+			ff_raddr <= 1'sb0;
+		else if (empty & ~empty_next)
+			ff_raddr <= raddr_next[ADDR_WIDTH - 1:0];
+		else if ((ren_in & !empty) & ~empty_next)
+			ff_raddr <= ff_raddr_next;
+	always @(posedge rclk or negedge rst_n)
+		if (~rst_n)
+			raddr <= 12'h000;
+		else if (ren_in & !empty)
+			raddr <= raddr_next;
+	always @(*)
+		case (FIFO_WIDTH)
+			3'h2: out_raddr = {ff_raddr[ADDR_WIDTH - 1:1], bwl_sel[0]};
+			3'h4: out_raddr = {ff_raddr[ADDR_WIDTH - 1:2], bwl_sel};
+			default: out_raddr = ff_raddr[ADDR_WIDTH - 1:0];
+		endcase
+	assign ren_o = ren_out;
+	assign gcout = gcout_reg;
+	assign popflags = {empty, epo, pae, underflow};
+endmodule
+`default_nettype none
diff --git a/yosys/techlibs/quicklogic/synth_quicklogic.cc b/yosys/techlibs/quicklogic/synth_quicklogic.cc
index 94bd44db008..0e7aaa75276 100644
--- a/yosys/techlibs/quicklogic/synth_quicklogic.cc
+++ b/yosys/techlibs/quicklogic/synth_quicklogic.cc
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2021 QuickLogic Corp.
+ *  Copyright 2020-2022 F4PGA Authors
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -30,6 +31,7 @@ struct SynthQuickLogicPass : public ScriptPass {
 
 	void help() override
 	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
 		log("   synth_quicklogic [options]\n");
 		log("This command runs synthesis for QuickLogic FPGAs\n");
@@ -42,6 +44,21 @@ struct SynthQuickLogicPass : public ScriptPass {
 		log("        generate the synthesis netlist for the specified family.\n");
 		log("        supported values:\n");
 		log("        - pp3: PolarPro 3 \n");
+		log("        - qlf_k6n10f: K6N10f\n");
+		log("\n");
+		log("    -nodsp\n");
+		log("        do not use dsp_t1_* to implement multipliers and associated logic\n");
+		log("        (qlf_k6n10f only).\n");
+		log("\n");
+		log("    -nocarry\n");
+		log("        do not use adder_carry cells in output netlist.\n");
+		log("\n");
+		log("    -nobram\n");
+		log("        do not use block RAM cells in output netlist.\n");
+		log("\n");
+		log("    -bramtypes\n");
+		log("        Emit specialized BRAM cells for particular address and data width\n");
+		log("        configurations.\n");
 		log("\n");
 		log("    -blif <file>\n");
 		log("        write the design to the specified BLIF file. writing of an output file\n");
@@ -60,27 +77,51 @@ struct SynthQuickLogicPass : public ScriptPass {
 		log("\n");
 	}
 
-	string top_opt, blif_file, family, currmodule, verilog_file;
-	bool abc9;
+	string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path;
+	bool abc9, inferAdder, nobram, bramTypes, dsp;
 
 	void clear_flags() override
 	{
 		top_opt = "-auto-top";
 		blif_file = "";
+		edif_file = "";
 		verilog_file = "";
 		currmodule = "";
 		family = "pp3";
 		abc9 = true;
+		inferAdder = true;
+		nobram = false;
+		bramTypes = false;
+		lib_path = "+/quicklogic/";
+		dsp = true;
+	}
+
+	void set_scratchpad_defaults(RTLIL::Design *design) {
+		lib_path = design->scratchpad_get_string("ql.lib_path", lib_path);
+		if (lib_path.back() != '/')
+			lib_path += "/";
+		inferAdder = !design->scratchpad_get_bool("ql.nocarry", false);
+		nobram = design->scratchpad_get_bool("ql.nobram", false);
+		bramTypes = design->scratchpad_get_bool("ql.bramtypes", false);
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		string run_from, run_to;
 		clear_flags();
+		set_scratchpad_defaults(design);
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
+			if (args[argidx] == "-run" && argidx+1 < args.size()) {
+				size_t pos = args[argidx+1].find(':');
+				if (pos == std::string::npos)
+					break;
+				run_from = args[++argidx].substr(0, pos);
+				run_to = args[argidx].substr(pos+1);
+				continue;
+			}
 			if (args[argidx] == "-top" && argidx+1 < args.size()) {
 				top_opt = "-top " + args[++argidx];
 				continue;
@@ -101,6 +142,22 @@ struct SynthQuickLogicPass : public ScriptPass {
 				abc9 = false;
 				continue;
 			}
+			if (args[argidx] == "-nocarry" || args[argidx] == "-no_adder") {
+				inferAdder = false;
+				continue;
+			}
+			if (args[argidx] == "-nobram" || args[argidx] == "-no_bram") {
+				nobram = true;
+				continue;
+			}
+			if (args[argidx] == "-bramtypes" || args[argidx] == "-bram_types") {
+				bramTypes = true;
+				continue;
+			}
+			if (args[argidx] == "-nodsp" || args[argidx] == "-no_dsp") {
+				dsp = false;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -108,7 +165,7 @@ struct SynthQuickLogicPass : public ScriptPass {
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 
-		if (family != "pp3")
+		if (family != "pp3" && family != "qlf_k6n10f")
 			log_cmd_error("Invalid family specified: '%s'\n", family.c_str());
 
 		if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) {
@@ -126,16 +183,29 @@ struct SynthQuickLogicPass : public ScriptPass {
 
 	void script() override
 	{
+		if (help_mode) {
+			family = "<family>";
+		}
+
 		if (check_label("begin")) {
-			run(stringf("read_verilog -lib -specify +/quicklogic/cells_sim.v +/quicklogic/%s_cells_sim.v", family.c_str()));
-			run("read_verilog -lib -specify +/quicklogic/lut_sim.v");
+			std::string read_simlibs = stringf("read_verilog -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path.c_str(), lib_path.c_str(), family.c_str());
+			if (family == "qlf_k6n10f") {
+				read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path.c_str());
+				if (bramTypes)
+					read_simlibs += stringf(" %sqlf_k6n10f/bram_types_sim.v", lib_path.c_str());
+				if (dsp)
+					read_simlibs += stringf(" %sqlf_k6n10f/dsp_sim.v", lib_path.c_str());
+			}
+			run(read_simlibs);
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
-		if (check_label("coarse")) {
+		if (check_label("prepare")) {
 			run("proc");
 			run("flatten");
-			run("tribuf -logic");
+			if (help_mode || family == "pp3") {
+				run("tribuf -logic", "                   (for pp3)");
+			}
 			run("deminout");
 			run("opt_expr");
 			run("opt_clean");
@@ -147,6 +217,24 @@ struct SynthQuickLogicPass : public ScriptPass {
 			run("peepopt");
 			run("opt_clean");
 			run("share");
+		}
+
+		if (check_label("map_dsp", "(for qlf_k6n10f, skip if -nodsp)")
+				&& ((dsp && family == "qlf_k6n10f") || help_mode)) {
+			run("wreduce t:$mul");
+			run("ql_dsp_macc");
+
+			run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18");
+			run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9");
+			run("chtype -set $mul t:$__soft_mul");
+
+			run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0");
+			run("ql_dsp_simd");
+			run("techmap -map " + lib_path + family + "/dsp_final_map.v");
+			run("ql_dsp_io_regs");
+		}
+
+		if (check_label("coarse")) {
 			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
 			run("opt_expr");
 			run("opt_clean");
@@ -157,6 +245,17 @@ struct SynthQuickLogicPass : public ScriptPass {
 			run("opt_clean");
 		}
 
+		if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)")
+				&& (family == "qlf_k6n10f" || help_mode)) {
+			run("memory_libmap -lib " + lib_path + family + "/libmap_brams.txt");
+			run("ql_bram_merge");
+			run("techmap -map " + lib_path + family + "/libmap_brams_map.v");
+			run("techmap -autoproc -map " + lib_path + family + "/brams_map.v");
+
+			if (bramTypes || help_mode)
+				run("ql_bram_types", "(if -bramtypes)");
+		}
+
 		if (check_label("map_ffram")) {
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block "
@@ -166,36 +265,67 @@ struct SynthQuickLogicPass : public ScriptPass {
 		}
 
 		if (check_label("map_gates")) {
-			run("techmap");
+			if (inferAdder && family == "qlf_k6n10f") {
+				run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v", "(unless -no_adder)");
+			} else {
+				run("techmap");
+			}
 			run("opt -fast");
-			run("muxcover -mux8 -mux4");
+			if (help_mode || family == "pp3") {
+				run("muxcover -mux8 -mux4", "(for pp3)");
+			}
 		}
 
 		if (check_label("map_ffs")) {
 			run("opt_expr");
-			run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x");
-
-			run(stringf("techmap -map +/quicklogic/%s_cells_map.v -map +/quicklogic/%s_ffs_map.v", family.c_str(), family.c_str()));
-
-			run("opt_expr -mux_undef");
+			if (help_mode) {
+				run("shregmap -minlen <min> -maxlen <max>", "(for qlf_k6n10f)");
+				run("dfflegalize -cell <supported FF types>");
+				run("techmap -map " + lib_path + family + "/cells_map.v", "(for pp3)");
+				run("techmap -map " + lib_path + family + "/ffs_map.v", "(for ql_k6n10f)");
+			}
+			if (family == "pp3") {
+				run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x");
+				run("techmap -map " + lib_path + family + "/cells_map.v -map " + lib_path + family + "/ffs_map.v");
+				run("opt_expr -mux_undef");
+			} else if (family == "qlf_k6n10f") {
+				run("shregmap -minlen 8 -maxlen 20");
+				// FIXME: Apparently dfflegalize leaves around $_DLATCH_[NP]_ even if
+				// not in the allowed set. As a workaround we put them in the allowed
+				// set explicitly and map them later to $_DLATCHSR_[NP]NN_.
+				run("dfflegalize -cell $_DFFSRE_?NNP_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0" " -cell $_SDFFE_?N?P_ 0");
+				run("techmap -map " + lib_path + family + "/ffs_map.v");
+			}
+			run("opt");
 		}
 
-		if (check_label("map_luts")) {
-			run(stringf("techmap -map +/quicklogic/%s_latches_map.v", family.c_str()));
+		if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
+			run("techmap -map " + lib_path + family + "/latches_map.v");
 			if (abc9) {
-				run("read_verilog -lib -specify -icells +/quicklogic/abc9_model.v");
-				run("techmap -map +/quicklogic/abc9_map.v");
+				run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");
+				run("techmap -map " + lib_path + family + "/abc9_map.v");
 				run("abc9 -maxlut 4 -dff");
-				run("techmap -map +/quicklogic/abc9_unmap.v");
+				run("techmap -map " + lib_path + family + "/abc9_unmap.v");
 			} else {
 				run("abc -luts 1,2,2,4 -dress");
 			}
 			run("clean");
 		}
 
-		if (check_label("map_cells")) {
-			run(stringf("techmap -map +/quicklogic/%s_lut_map.v", family.c_str()));
+		if (check_label("map_luts", "(for qlf_k6n10f)") && (help_mode || family == "qlf_k6n10f")) {
+			if (abc9) {
+				run("abc9 -maxlut 6");
+			} else {
+				run("abc -lut 6 -dress");
+			}
 			run("clean");
+			run("opt_lut");
+		}
+
+		if (check_label("map_cells", "(for pp3)") && (help_mode || family == "pp3")) {
+			run("techmap -map " + lib_path + family + "/lut_map.v");
+			run("clean");
+			run("opt_lut");
 		}
 
 		if (check_label("check")) {
@@ -205,26 +335,30 @@ struct SynthQuickLogicPass : public ScriptPass {
 			run("check -noinit");
 		}
 
-		if (check_label("iomap")) {
+		if (check_label("iomap", "(for pp3)") && (family == "pp3" || help_mode)) {
 			run("clkbufmap -inpad ckpad Q:P");
 			run("iopadmap -bits -outpad outpad A:P -inpad inpad Q:P -tinoutpad bipad EN:Q:A:P A:top");
 		}
 
 		if (check_label("finalize")) {
-			run("setundef -zero -params -undriven");
-			run("hilomap -hicell logic_1 A -locell logic_0 A -singleton A:top");
+			if (help_mode || family == "pp3") {
+				run("setundef -zero -params -undriven", "(for pp3)");
+			}
+			if (family == "pp3" || !edif_file.empty()) {
+				run("hilomap -hicell logic_1 A -locell logic_0 A -singleton A:top", "(for pp3 or if -edif)");
+			}
 			run("opt_clean -purge");
 			run("check");
 			run("blackbox =A:whitebox");
 		}
 
-		if (check_label("blif")) {
+		if (check_label("blif", "(if -blif)")) {
 			if (!blif_file.empty() || help_mode) {
 				run(stringf("write_blif -attr -param %s %s", top_opt.c_str(), blif_file.c_str()));
 			}
 		}
 
-		if (check_label("verilog")) {
+		if (check_label("verilog", "(if -verilog)")) {
 			if (!verilog_file.empty() || help_mode) {
 				run(stringf("write_verilog -noattr -nohex %s", help_mode ? "<file-name>" : verilog_file.c_str()));
 			}
diff --git a/yosys/techlibs/xilinx/tests/bram1.sh b/yosys/techlibs/xilinx/tests/bram1.sh
index 7451a1b3e25..7e99368048d 100644
--- a/yosys/techlibs/xilinx/tests/bram1.sh
+++ b/yosys/techlibs/xilinx/tests/bram1.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -e
 
diff --git a/yosys/techlibs/xilinx/tests/bram2.sh b/yosys/techlibs/xilinx/tests/bram2.sh
index 5d9c84dace1..5c18d30e246 100644
--- a/yosys/techlibs/xilinx/tests/bram2.sh
+++ b/yosys/techlibs/xilinx/tests/bram2.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -ex
 unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims
diff --git a/yosys/techlibs/xilinx/tests/test_dsp48_model.sh b/yosys/techlibs/xilinx/tests/test_dsp48_model.sh
index 9a73f9b0c3e..bd72572d5f9 100644
--- a/yosys/techlibs/xilinx/tests/test_dsp48_model.sh
+++ b/yosys/techlibs/xilinx/tests/test_dsp48_model.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -ex
 if [ -z $ISE_DIR ]; then
 	ISE_DIR=/opt/Xilinx/ISE/14.7
diff --git a/yosys/techlibs/xilinx/tests/test_dsp48a1_model.sh b/yosys/techlibs/xilinx/tests/test_dsp48a1_model.sh
index a14a78e7267..02ce2fef999 100644
--- a/yosys/techlibs/xilinx/tests/test_dsp48a1_model.sh
+++ b/yosys/techlibs/xilinx/tests/test_dsp48a1_model.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -ex
 if [ -z $ISE_DIR ]; then
 	ISE_DIR=/opt/Xilinx/ISE/14.7
diff --git a/yosys/techlibs/xilinx/tests/test_dsp_model.sh b/yosys/techlibs/xilinx/tests/test_dsp_model.sh
index d005cd40c73..b2a2bb44582 100644
--- a/yosys/techlibs/xilinx/tests/test_dsp_model.sh
+++ b/yosys/techlibs/xilinx/tests/test_dsp_model.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -ex
 if [ -z $VIVADO_DIR ]; then
 	VIVADO_DIR=/opt/Xilinx/Vivado/2019.1
diff --git a/yosys/tests/aiger/and_to_bad_out.aag b/yosys/tests/aiger/and_to_bad_out.aag
new file mode 100644
index 00000000000..96f1e7cad12
--- /dev/null
+++ b/yosys/tests/aiger/and_to_bad_out.aag
@@ -0,0 +1,8 @@
+aag 3 2 0 0 1 1 0 0 0
+2
+4
+6
+6 2 4
+i0 pi0
+i1 pi1
+b0 b0
diff --git a/yosys/tests/aiger/and_to_bad_out.aig b/yosys/tests/aiger/and_to_bad_out.aig
new file mode 100644
index 00000000000..3be65ae895b
--- /dev/null
+++ b/yosys/tests/aiger/and_to_bad_out.aig
@@ -0,0 +1,5 @@
+aig 3 2 0 0 1 1
+6
+i0 pi0
+i1 pi1
+b0 b0
diff --git a/yosys/tests/aiger/run-test.sh b/yosys/tests/aiger/run-test.sh
index bcf2b964a27..ca7339ff0b5 100755
--- a/yosys/tests/aiger/run-test.sh
+++ b/yosys/tests/aiger/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -e
 
diff --git a/yosys/tests/arch/common/blockram.v b/yosys/tests/arch/common/blockram.v
index c06ac96d5bc..4a9d45a6b4a 100644
--- a/yosys/tests/arch/common/blockram.v
+++ b/yosys/tests/arch/common/blockram.v
@@ -45,6 +45,113 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
 endmodule // sync_ram_sdp
 
 
+module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, SHIFT_VAL=1) // wd=16, wa=9
+(
+		input  wire                          clk_w, clk_r, write_enable,
+    		input  wire  [WORD-1:0]              data_in,
+    		input  wire  [ADDRESS_WIDTH_W-1:0]   address_in_w,
+    		input  wire  [ADDRESS_WIDTH-1:0]     address_in_r,
+    		output wire  [DATA_WIDTH-1:0]        data_out
+);
+
+	localparam ADDRESS_WIDTH_W = ADDRESS_WIDTH-SHIFT_VAL;
+	localparam BYTE = DATA_WIDTH;
+	localparam WORD  = DATA_WIDTH<<SHIFT_VAL;
+	localparam DEPTH = 2**ADDRESS_WIDTH_W;
+	localparam SUB_DEPTH = 2**SHIFT_VAL;
+
+	reg [BYTE-1:0] data_out_r;
+	reg [BYTE-1:0] memory [0:DEPTH-1];
+
+	integer i;
+	always @(posedge clk_w) begin
+		for (i=0; i<SUB_DEPTH; i=i+1)
+			if (write_enable)
+				memory[{address_in_w, i}] <= data_in[i*BYTE+:BYTE];
+	end
+
+	always @(posedge clk_r) begin
+		data_out_r <= memory[address_in_r];
+	end
+
+	assign data_out = data_out_r;
+
+endmodule // sync_ram_sdp_wwr
+
+
+module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, SHIFT_VAL=1) // rd=16, ra=9
+(
+		input  wire                         clk_w, clk_r, write_enable,
+		input  wire  [DATA_WIDTH-1:0]       data_in,
+		input  wire  [ADDRESS_WIDTH-1:0]    address_in_w,
+		input  wire  [ADDRESS_WIDTH_R-1:0]  address_in_r,
+		output wire  [WORD-1:0]             data_out
+);
+	localparam ADDRESS_WIDTH_R = ADDRESS_WIDTH-SHIFT_VAL;
+	localparam BYTE = DATA_WIDTH;
+	localparam WORD  = BYTE<<SHIFT_VAL;
+	localparam DEPTH = 2**ADDRESS_WIDTH;
+	localparam SUB_DEPTH = 2**SHIFT_VAL;
+
+	reg [WORD-1:0] data_out_r;
+	reg [BYTE-1:0] memory [0:DEPTH-1];
+
+	always @(posedge clk_w) begin
+		if (write_enable)
+			memory[address_in_w] <= data_in;
+	end
+
+	integer i;
+	always @(posedge clk_r) begin
+		for (i=0; i<SUB_DEPTH; i=i+1)
+			data_out_r[i*BYTE+:BYTE] <= memory[{address_in_r, i}];
+	end
+
+	assign data_out = data_out_r;
+
+endmodule // sync_ram_sdp_wrr
+
+
+module double_sync_ram_sdp #(parameter DATA_WIDTH_A=8, ADDRESS_WIDTH_A=10, DATA_WIDTH_B=8, ADDRESS_WIDTH_B=10)
+(
+    input  wire                        write_enable_a, clk_a,
+    input  wire  [DATA_WIDTH_A-1:0]    data_in_a,
+    input  wire  [ADDRESS_WIDTH_A-1:0] address_in_r_a, address_in_w_a,
+    output wire  [DATA_WIDTH_A-1:0]    data_out_a,
+
+    input  wire                        write_enable_b, clk_b,
+    input  wire  [DATA_WIDTH_B-1:0]    data_in_b,
+    input  wire  [ADDRESS_WIDTH_B-1:0] address_in_r_b, address_in_w_b,
+    output wire  [DATA_WIDTH_B-1:0]    data_out_b
+);
+
+    sync_ram_sdp #(
+        .DATA_WIDTH(DATA_WIDTH_A),
+        .ADDRESS_WIDTH(ADDRESS_WIDTH_A)
+    ) a_ram (
+    .write_enable(write_enable_a),
+    .clk(clk_a),
+    .data_in(data_in_a),
+    .address_in_r(address_in_r_a),
+    .address_in_w(address_in_w_a),
+    .data_out(data_out_a)
+    );
+
+    sync_ram_sdp #(
+        .DATA_WIDTH(DATA_WIDTH_B),
+        .ADDRESS_WIDTH(ADDRESS_WIDTH_B)
+    ) b_ram (
+    .write_enable(write_enable_b),
+    .clk(clk_b),
+    .data_in(data_in_b),
+    .address_in_r(address_in_r_b),
+    .address_in_w(address_in_w_b),
+    .data_out(data_out_b)
+    );
+
+endmodule // double_sync_ram_sdp
+
+
 module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
    (input  wire                      clk_a, clk_b, 
     input  wire                      write_enable_a, write_enable_b,
@@ -74,3 +181,68 @@ module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
 
 endmodule // sync_ram_tdp
 
+module double_sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
+(
+    input  wire                         clk_a_0,
+    input  wire                         write_enable_a_0, read_enable_a_0,
+    input  wire  [DATA_WIDTH-1:0]       write_data_a_0,
+    input  wire  [ADDRESS_WIDTH-1:0]    addr_a_0,
+    output wire  [DATA_WIDTH-1:0]       read_data_a_0,
+
+    input  wire                         clk_a_1,
+    input  wire                         write_enable_a_1, read_enable_a_1,
+    input  wire  [DATA_WIDTH-1:0]       write_data_a_1,
+    input  wire  [ADDRESS_WIDTH-1:0]    addr_a_1,
+    output wire  [DATA_WIDTH-1:0]       read_data_a_1,
+
+    input  wire                         clk_b_0,
+    input  wire                         write_enable_b_0, read_enable_b_0,
+    input  wire  [DATA_WIDTH-1:0]       write_data_b_0,
+    input  wire  [ADDRESS_WIDTH-1:0]    addr_b_0,
+    output wire  [DATA_WIDTH-1:0]       read_data_b_0,
+
+    input  wire                         clk_b_1,
+    input  wire                         write_enable_b_1, read_enable_b_1,
+    input  wire  [DATA_WIDTH-1:0]       write_data_b_1,
+    input  wire  [ADDRESS_WIDTH-1:0]    addr_b_1,
+    output wire  [DATA_WIDTH-1:0]       read_data_b_1
+);
+
+    sync_ram_tdp #(
+        .DATA_WIDTH(DATA_WIDTH),
+        .ADDRESS_WIDTH(ADDRESS_WIDTH)
+    ) ram_0 (
+        .clk_a(clk_a_0),
+        .clk_b(clk_b_0),
+        .write_enable_a(write_enable_a_0),
+        .write_enable_b(write_enable_b_0),
+        .read_enable_a(read_enable_a_0),
+        .read_enable_b(read_enable_b_0),
+        .write_data_a(write_data_a_0),
+        .write_data_b(write_data_b_0),
+        .addr_a(addr_a_0),
+        .addr_b(addr_b_0),
+        .read_data_a(read_data_a_0),
+        .read_data_b(read_data_b_0)
+    );
+
+    sync_ram_tdp #(
+        .DATA_WIDTH(DATA_WIDTH),
+        .ADDRESS_WIDTH(ADDRESS_WIDTH)
+    ) ram_1 (
+        .clk_a(clk_a_1),
+        .clk_b(clk_b_1),
+        .write_enable_a(write_enable_a_1),
+        .write_enable_b(write_enable_b_1),
+        .read_enable_a(read_enable_a_1),
+        .read_enable_b(read_enable_b_1),
+        .write_data_a(write_data_a_1),
+        .write_data_b(write_data_b_1),
+        .addr_a(addr_a_1),
+        .addr_b(addr_b_1),
+        .read_data_a(read_data_a_1),
+        .read_data_b(read_data_b_1)
+    );
+
+endmodule // double_sync_ram_tdp
+
diff --git a/yosys/tests/arch/ecp5/add_sub.ys b/yosys/tests/arch/ecp5/add_sub.ys
index d85ce792ee6..c3ce8c56dae 100644
--- a/yosys/tests/arch/ecp5/add_sub.ys
+++ b/yosys/tests/arch/ecp5/add_sub.ys
@@ -4,6 +4,9 @@ proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 10 t:LUT4
-select -assert-none t:LUT4 %% t:* %D
+select -assert-min 25 t:LUT4
+select -assert-max 26 t:LUT4
+select -assert-count 10 t:PFUMX
+select -assert-count 6 t:L6MUX21
+select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D
 
diff --git a/yosys/tests/arch/ecp5/counter.ys b/yosys/tests/arch/ecp5/counter.ys
index e46001ffede..e3f713228c3 100644
--- a/yosys/tests/arch/ecp5/counter.ys
+++ b/yosys/tests/arch/ecp5/counter.ys
@@ -5,6 +5,7 @@ flatten
 equiv_opt -assert -multiclock -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT4
 select -assert-count 4 t:CCU2C
 select -assert-count 8 t:TRELLIS_FF
-select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D
+select -assert-none t:LUT4 t:CCU2C t:TRELLIS_FF %% t:* %D
diff --git a/yosys/tests/arch/gowin/counter.ys b/yosys/tests/arch/gowin/counter.ys
index bdbc7ee2432..ec6ca0f5ee2 100644
--- a/yosys/tests/arch/gowin/counter.ys
+++ b/yosys/tests/arch/gowin/counter.ys
@@ -6,10 +6,11 @@ equiv_opt -assert -multiclock -map +/gowin/cells_sim.v synth_gowin # equivalency
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
+select -assert-count 1 t:LUT1
 select -assert-count 8 t:DFFC
 select -assert-count 8 t:ALU
 select -assert-count 1 t:GND
 select -assert-count 1 t:VCC
 select -assert-count 2 t:IBUF
 select -assert-count 8 t:OBUF
-select -assert-none t:DFFC t:ALU t:GND t:VCC t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT1 t:DFFC t:ALU t:GND t:VCC t:IBUF t:OBUF %% t:* %D
diff --git a/yosys/tests/arch/gowin/init.ys b/yosys/tests/arch/gowin/init.ys
index fba7c2fa583..d522801c63d 100644
--- a/yosys/tests/arch/gowin/init.ys
+++ b/yosys/tests/arch/gowin/init.ys
@@ -1,5 +1,5 @@
 read_verilog init.v
-read_verilog -lib +/gowin/cells_sim.v
+read_verilog -lib -specify +/gowin/cells_sim.v
 design -save read
 
 proc
diff --git a/yosys/tests/arch/gowin/mux.ys b/yosys/tests/arch/gowin/mux.ys
index 33b092284fa..d5978f4ea5c 100644
--- a/yosys/tests/arch/gowin/mux.ys
+++ b/yosys/tests/arch/gowin/mux.ys
@@ -32,10 +32,17 @@ proc
 equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT1
+select -assert-count 10 t:LUT3
+select -assert-count 1 t:LUT4
+select -assert-count 5 t:MUX2_LUT5
+select -assert-count 2 t:MUX2_LUT6
+select -assert-count 1 t:MUX2_LUT7
 select -assert-count 11 t:IBUF
 select -assert-count 1 t:OBUF
+select -assert-count 1 t:GND
 
-select -assert-none t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT* t:MUX2_LUT7 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF t:GND %% t:* %D
 
 design -load read
 hierarchy -top mux16
diff --git a/yosys/tests/arch/ice40/add_sub.ys b/yosys/tests/arch/ice40/add_sub.ys
index 578ec080380..74b83b8ee91 100644
--- a/yosys/tests/arch/ice40/add_sub.ys
+++ b/yosys/tests/arch/ice40/add_sub.ys
@@ -3,7 +3,7 @@ hierarchy -top top
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 11 t:SB_LUT4
+select -assert-count 10 t:SB_LUT4
 select -assert-count 6 t:SB_CARRY
 select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
 
diff --git a/yosys/tests/arch/ice40/mux.ys b/yosys/tests/arch/ice40/mux.ys
index 2b661fd6b1a..977d6975063 100644
--- a/yosys/tests/arch/ice40/mux.ys
+++ b/yosys/tests/arch/ice40/mux.ys
@@ -15,7 +15,7 @@ proc
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 2 t:SB_LUT4
+select -assert-count 3 t:SB_LUT4
 
 select -assert-none t:SB_LUT4 %% t:* %D
 
@@ -25,7 +25,7 @@ proc
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 5 t:SB_LUT4
+select -assert-count 6 t:SB_LUT4
 
 select -assert-none t:SB_LUT4 %% t:* %D
 
@@ -35,7 +35,7 @@ proc
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-min 11 t:SB_LUT4
-select -assert-max 12 t:SB_LUT4
+select -assert-min 13 t:SB_LUT4
+select -assert-max 14 t:SB_LUT4
 
 select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/yosys/tests/arch/intel_alm/add_sub.ys b/yosys/tests/arch/intel_alm/add_sub.ys
index 8f87adf2713..6453da116a1 100644
--- a/yosys/tests/arch/intel_alm/add_sub.ys
+++ b/yosys/tests/arch/intel_alm/add_sub.ys
@@ -7,12 +7,3 @@ stat
 select -assert-count 9 t:MISTRAL_ALUT_ARITH
 select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
 
-design -reset
-read_verilog ../common/add_sub.v
-hierarchy -top top
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-stat
-select -assert-count 9 t:MISTRAL_ALUT_ARITH
-select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
diff --git a/yosys/tests/arch/intel_alm/adffs.ys b/yosys/tests/arch/intel_alm/adffs.ys
index d7487c40bec..1f81902ec5a 100644
--- a/yosys/tests/arch/intel_alm/adffs.ys
+++ b/yosys/tests/arch/intel_alm/adffs.ys
@@ -12,18 +12,6 @@ select -assert-count 1 t:MISTRAL_NOT
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 
 
-design -load read
-hierarchy -top adff
-proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd adff # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_FF
-select -assert-count 1 t:MISTRAL_NOT
-
-select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
-
-
 design -load read
 hierarchy -top adffn
 proc
@@ -35,17 +23,6 @@ select -assert-count 1 t:MISTRAL_FF
 select -assert-none t:MISTRAL_FF %% t:* %D
 
 
-design -load read
-hierarchy -top adffn
-proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd adffn # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_FF
-
-select -assert-none t:MISTRAL_FF %% t:* %D
-
-
 design -load read
 hierarchy -top dffs
 proc
@@ -58,18 +35,6 @@ select -assert-count 1 t:MISTRAL_ALUT2
 select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
 
 
-design -load read
-hierarchy -top dffs
-proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dffs # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_FF
-select -assert-count 1 t:MISTRAL_ALUT2
-
-select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
-
-
 design -load read
 hierarchy -top ndffnr
 proc
@@ -81,14 +46,3 @@ select -assert-count 2 t:MISTRAL_NOT
 
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 
-
-design -load read
-hierarchy -top ndffnr
-proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd ndffnr # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_FF
-select -assert-count 2 t:MISTRAL_NOT
-
-select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
diff --git a/yosys/tests/arch/intel_alm/blockram.ys b/yosys/tests/arch/intel_alm/blockram.ys
index 21b5ecbfb60..4af59e7d434 100644
--- a/yosys/tests/arch/intel_alm/blockram.ys
+++ b/yosys/tests/arch/intel_alm/blockram.ys
@@ -5,3 +5,4 @@ cd sync_ram_sdp
 select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 1 t:MISTRAL_M10K
 select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D
+
diff --git a/yosys/tests/arch/intel_alm/counter.ys b/yosys/tests/arch/intel_alm/counter.ys
index 2b428fb3e51..44e00081445 100644
--- a/yosys/tests/arch/intel_alm/counter.ys
+++ b/yosys/tests/arch/intel_alm/counter.ys
@@ -11,17 +11,3 @@ select -assert-count 8 t:MISTRAL_ALUT_ARITH
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
 
-
-design -reset
-read_verilog ../common/counter.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 2 t:MISTRAL_NOT
-select -assert-count 8 t:MISTRAL_ALUT_ARITH
-select -assert-count 8 t:MISTRAL_FF
-select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
diff --git a/yosys/tests/arch/intel_alm/dffs.ys b/yosys/tests/arch/intel_alm/dffs.ys
index 34b99f04cbf..aeaae4aa3ce 100644
--- a/yosys/tests/arch/intel_alm/dffs.ys
+++ b/yosys/tests/arch/intel_alm/dffs.ys
@@ -7,17 +7,6 @@ equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
-
-select -assert-none t:MISTRAL_FF %% t:* %D
-
-design -load read
-hierarchy -top dff
-proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dff # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_FF
-
 select -assert-none t:MISTRAL_FF %% t:* %D
 
 
@@ -28,16 +17,5 @@ equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
-
 select -assert-none t:MISTRAL_FF %% t:* %D
 
-
-design -load read
-hierarchy -top dffe
-proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dffe # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_FF
-
-select -assert-none t:MISTRAL_FF %% t:* %D
diff --git a/yosys/tests/arch/intel_alm/fsm.ys b/yosys/tests/arch/intel_alm/fsm.ys
index 0aeea450ac5..f3060684a9f 100644
--- a/yosys/tests/arch/intel_alm/fsm.ys
+++ b/yosys/tests/arch/intel_alm/fsm.ys
@@ -20,25 +20,3 @@ select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
 select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
 
-design -reset
-read_verilog ../common/fsm.v
-hierarchy -top fsm
-proc
-flatten
-
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf
-async2sync
-miter -equiv -make_assert -flatten gold gate miter
-sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
-
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd fsm # Constrain all select calls below inside the top module
-
-select -assert-count 6 t:MISTRAL_FF
-select -assert-max 1 t:MISTRAL_NOT
-select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1
-select -assert-max 2 t:MISTRAL_ALUT3 # Clang returns 2, GCC returns 1
-select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
-select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
-select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
-select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
diff --git a/yosys/tests/arch/intel_alm/logic.ys b/yosys/tests/arch/intel_alm/logic.ys
index d34d1bc65de..831f9f1741e 100644
--- a/yosys/tests/arch/intel_alm/logic.ys
+++ b/yosys/tests/arch/intel_alm/logic.ys
@@ -10,16 +10,3 @@ select -assert-count 6 t:MISTRAL_ALUT2
 select -assert-count 2 t:MISTRAL_ALUT4
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
 
-
-design -reset
-read_verilog ../common/logic.v
-hierarchy -top top
-proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 1 t:MISTRAL_NOT
-select -assert-count 6 t:MISTRAL_ALUT2
-select -assert-count 2 t:MISTRAL_ALUT4
-select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
\ No newline at end of file
diff --git a/yosys/tests/arch/intel_alm/lutram.ys b/yosys/tests/arch/intel_alm/lutram.ys
index 9ddb1ec874e..4e77afded78 100644
--- a/yosys/tests/arch/intel_alm/lutram.ys
+++ b/yosys/tests/arch/intel_alm/lutram.ys
@@ -37,3 +37,4 @@ select -assert-count 2 t:MISTRAL_ALUT2
 select -assert-count 8 t:MISTRAL_ALUT3
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
+
diff --git a/yosys/tests/arch/intel_alm/mul.ys b/yosys/tests/arch/intel_alm/mul.ys
index e147d93ac1e..75b32846304 100644
--- a/yosys/tests/arch/intel_alm/mul.ys
+++ b/yosys/tests/arch/intel_alm/mul.ys
@@ -9,8 +9,6 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_MUL9X9
 select -assert-none t:MISTRAL_MUL9X9 %% t:* %D
 
-# Cyclone 10 GX does not have 9x9 multipliers.
-
 design -reset
 read_verilog ../common/mul.v
 chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
@@ -23,18 +21,6 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_MUL18X18
 select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
 
-design -reset
-read_verilog ../common/mul.v
-chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
-hierarchy -top top
-proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 1 t:MISTRAL_MUL18X18
-select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
-
 design -reset
 read_verilog ../common/mul.v
 chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
@@ -47,14 +33,3 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_MUL27X27
 select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
 
-design -reset
-read_verilog ../common/mul.v
-chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
-hierarchy -top top
-proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 1 t:MISTRAL_MUL27X27
-select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
diff --git a/yosys/tests/arch/intel_alm/mux.ys b/yosys/tests/arch/intel_alm/mux.ys
index 20969ead35f..951b0eff6b4 100644
--- a/yosys/tests/arch/intel_alm/mux.ys
+++ b/yosys/tests/arch/intel_alm/mux.ys
@@ -11,16 +11,6 @@ select -assert-count 1 t:MISTRAL_ALUT3
 select -assert-none t:MISTRAL_ALUT3 %% t:* %D
 
 
-design -load read
-hierarchy -top mux2
-proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux2 # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_ALUT3
-select -assert-none t:MISTRAL_ALUT3 %% t:* %D
-
-
 design -load read
 hierarchy -top mux4
 proc
@@ -31,16 +21,6 @@ select -assert-count 1 t:MISTRAL_ALUT6
 select -assert-none t:MISTRAL_ALUT6 %% t:* %D
 
 
-design -load read
-hierarchy -top mux4
-proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_ALUT6 %% t:* %D
-
-
 design -load read
 hierarchy -top mux8
 proc
@@ -52,17 +32,6 @@ select -assert-count 2 t:MISTRAL_ALUT6
 select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
 
 
-design -load read
-hierarchy -top mux8
-proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_ALUT3
-select -assert-count 2 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
-
-
 design -load read
 hierarchy -top mux16
 proc
@@ -74,15 +43,3 @@ select -assert-max 2 t:MISTRAL_ALUT5
 select -assert-max 5 t:MISTRAL_ALUT6
 select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
 
-
-design -load read
-hierarchy -top mux16
-proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux16 # Constrain all select calls below inside the top module
-select -assert-max 1 t:MISTRAL_ALUT3
-select -assert-max 2 t:MISTRAL_ALUT5
-select -assert-max 5 t:MISTRAL_ALUT6
-
-select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
diff --git a/yosys/tests/arch/intel_alm/quartus_ice.ys b/yosys/tests/arch/intel_alm/quartus_ice.ys
deleted file mode 100644
index 4e1896b82a8..00000000000
--- a/yosys/tests/arch/intel_alm/quartus_ice.ys
+++ /dev/null
@@ -1,26 +0,0 @@
-read_verilog <<EOT
-// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
-// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
-module top();
-  (* keep *) wire [31:0] \a[10] ;
-  (* keep *) wire b;
-  assign b = \a[10] [31];
-endmodule
-EOT
-
-synth_intel_alm -family cyclonev -quartus
-select -assert-none w:*[* w:*]*
-
-design -reset
-read_verilog <<EOT
-// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
-// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
-module top();
-  (* keep *) wire [31:0] \a[10] ;
-  (* keep *) wire b;
-  assign b = \a[10] [31];
-endmodule
-EOT
-
-synth_intel_alm -family cyclone10gx -quartus -noiopad -noclkbuf
-select -assert-none w:*[* w:*]*
diff --git a/yosys/tests/arch/intel_alm/shifter.ys b/yosys/tests/arch/intel_alm/shifter.ys
index 77ff9889658..da10c82d734 100644
--- a/yosys/tests/arch/intel_alm/shifter.ys
+++ b/yosys/tests/arch/intel_alm/shifter.ys
@@ -8,14 +8,3 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_FF %% t:* %D
 
-
-design -reset
-read_verilog ../common/shifter.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 8 t:MISTRAL_FF
-select -assert-none t:MISTRAL_FF %% t:* %D
diff --git a/yosys/tests/arch/intel_alm/tribuf.ys b/yosys/tests/arch/intel_alm/tribuf.ys
index fb5fecb7855..96dde1c9da7 100644
--- a/yosys/tests/arch/intel_alm/tribuf.ys
+++ b/yosys/tests/arch/intel_alm/tribuf.ys
@@ -11,17 +11,3 @@ cd tristate # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D
 
-
-design -reset
-read_verilog ../common/tribuf.v
-hierarchy -top tristate
-proc
-tribuf
-flatten
-synth
-equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd tristate # Constrain all select calls below inside the top module
-#Internal cell type used. Need support it.
-select -assert-count 1 t:$_TBUF_
-select -assert-none t:$_TBUF_ %% t:* %D
diff --git a/yosys/tests/arch/machxo2/add_sub.ys b/yosys/tests/arch/machxo2/add_sub.ys
index 97ee90fbbe2..cc6ffb41a29 100644
--- a/yosys/tests/arch/machxo2/add_sub.ys
+++ b/yosys/tests/arch/machxo2/add_sub.ys
@@ -1,7 +1,7 @@
 read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 10 t:LUT4
diff --git a/yosys/tests/arch/machxo2/adffs.ys b/yosys/tests/arch/machxo2/adffs.ys
index a9f8980c6e4..49e93f9ac30 100644
--- a/yosys/tests/arch/machxo2/adffs.ys
+++ b/yosys/tests/arch/machxo2/adffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top adff
 proc
-equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
@@ -12,7 +12,7 @@ select -assert-none t:TRELLIS_FF %% t:* %D
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
@@ -22,7 +22,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
@@ -32,7 +32,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check
+equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
diff --git a/yosys/tests/arch/machxo2/counter.ys b/yosys/tests/arch/machxo2/counter.ys
index 54ee80066ff..3d68c9900fa 100644
--- a/yosys/tests/arch/machxo2/counter.ys
+++ b/yosys/tests/arch/machxo2/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -multiclock -map +/machxo2/cells_sim.v synth_machxo2 -ccu2 -noiopad # equivalency check
+equiv_opt -assert -multiclock -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 4 t:CCU2D
diff --git a/yosys/tests/arch/machxo2/dffs.ys b/yosys/tests/arch/machxo2/dffs.ys
index 29dcafe2383..531d5ca5a27 100644
--- a/yosys/tests/arch/machxo2/dffs.ys
+++ b/yosys/tests/arch/machxo2/dffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top dff
 proc
-equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
@@ -12,8 +12,8 @@ select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D
 design -load read
 hierarchy -top dffe
 proc
-equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
-select -assert-count 2 t:TRELLIS_FF t:LUT4
+select -assert-count 1 t:TRELLIS_FF t:LUT4
 select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D
diff --git a/yosys/tests/arch/machxo2/fsm.ys b/yosys/tests/arch/machxo2/fsm.ys
index a61357fcdd2..3e10a069a74 100644
--- a/yosys/tests/arch/machxo2/fsm.ys
+++ b/yosys/tests/arch/machxo2/fsm.ys
@@ -3,7 +3,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2
+equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
 
diff --git a/yosys/tests/arch/machxo2/logic.ys b/yosys/tests/arch/machxo2/logic.ys
index 0cf57310c81..dbd702f905e 100644
--- a/yosys/tests/arch/machxo2/logic.ys
+++ b/yosys/tests/arch/machxo2/logic.ys
@@ -1,7 +1,7 @@
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 9 t:LUT4
diff --git a/yosys/tests/arch/machxo2/lutram.ys b/yosys/tests/arch/machxo2/lutram.ys
index dc6b86fd349..65af7b2c267 100644
--- a/yosys/tests/arch/machxo2/lutram.ys
+++ b/yosys/tests/arch/machxo2/lutram.ys
@@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
 proc
 memory -nomap
-equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 -noiopad
+equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2
 memory
 opt -full
 
diff --git a/yosys/tests/arch/machxo2/mux.ys b/yosys/tests/arch/machxo2/mux.ys
index 27bffbe63aa..6d4e10dc7e7 100644
--- a/yosys/tests/arch/machxo2/mux.ys
+++ b/yosys/tests/arch/machxo2/mux.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT4
@@ -12,7 +12,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 2 t:LUT4
@@ -22,7 +22,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 5 t:LUT4
@@ -32,7 +32,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-max 12 t:LUT4
diff --git a/yosys/tests/arch/machxo2/shifter.ys b/yosys/tests/arch/machxo2/shifter.ys
index bff881fb734..ca7abb8098b 100644
--- a/yosys/tests/arch/machxo2/shifter.ys
+++ b/yosys/tests/arch/machxo2/shifter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/yosys/tests/arch/machxo2/tribuf.ys b/yosys/tests/arch/machxo2/tribuf.ys
index 840979439f8..00c7012d748 100644
--- a/yosys/tests/arch/machxo2/tribuf.ys
+++ b/yosys/tests/arch/machxo2/tribuf.ys
@@ -2,9 +2,8 @@ read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 flatten
-equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v -map +/simcells.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
-select -assert-count 3 t:TRELLIS_IO
-select -assert-count 1 t:LUT4
-select -assert-none t:TRELLIS_IO t:LUT4 %% t:* %D
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:$_TBUF_ %% t:* %D
diff --git a/yosys/tests/arch/quicklogic/.gitignore b/yosys/tests/arch/quicklogic/.gitignore
index 9a71dca69b0..ae20ed34262 100644
--- a/yosys/tests/arch/quicklogic/.gitignore
+++ b/yosys/tests/arch/quicklogic/.gitignore
@@ -1,4 +1,4 @@
 *.log
-/run-test.mk
+run-test.mk
 +*_synth.v
 +*_testbench
diff --git a/yosys/tests/arch/quicklogic/dffs.ys b/yosys/tests/arch/quicklogic/dffs.ys
deleted file mode 100644
index 2e0a34540ec..00000000000
--- a/yosys/tests/arch/quicklogic/dffs.ys
+++ /dev/null
@@ -1,20 +0,0 @@
-read_verilog ../common/dffs.v
-rename dff my_dff # Work around conflicting module names between test and vendor cells
-rename dffe my_dffe
-design -save read
-
-hierarchy -top my_dff
-proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dff # Constrain all select calls below inside the top module
-select -assert-none t:*
-
-design -load read
-hierarchy -top my_dffe
-proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dffe # Constrain all select calls below inside the top module
-
-select -assert-none t:*
\ No newline at end of file
diff --git a/yosys/tests/arch/quicklogic/add_sub.ys b/yosys/tests/arch/quicklogic/pp3/add_sub.ys
similarity index 71%
rename from yosys/tests/arch/quicklogic/add_sub.ys
rename to yosys/tests/arch/quicklogic/pp3/add_sub.ys
index 73ee5cb4413..c5e9fb29be8 100644
--- a/yosys/tests/arch/quicklogic/add_sub.ys
+++ b/yosys/tests/arch/quicklogic/pp3/add_sub.ys
@@ -1,6 +1,6 @@
-read_verilog ../common/add_sub.v
+read_verilog ../../common/add_sub.v
 hierarchy -top top
-equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 2 t:LUT2
diff --git a/yosys/tests/arch/quicklogic/adffs.ys b/yosys/tests/arch/quicklogic/pp3/adffs.ys
similarity index 76%
rename from yosys/tests/arch/quicklogic/adffs.ys
rename to yosys/tests/arch/quicklogic/pp3/adffs.ys
index 41a17584427..fb9f34df429 100644
--- a/yosys/tests/arch/quicklogic/adffs.ys
+++ b/yosys/tests/arch/quicklogic/pp3/adffs.ys
@@ -1,9 +1,9 @@
-read_verilog ../common/adffs.v
+read_verilog ../../common/adffs.v
 design -save read
 
 hierarchy -top adff
 proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:dffepc
@@ -19,7 +19,7 @@ select -assert-none t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:*
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT1
@@ -36,7 +36,7 @@ select -assert-none t:LUT1 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT2
@@ -53,7 +53,7 @@ select -assert-none t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT1
diff --git a/yosys/tests/arch/quicklogic/counter.ys b/yosys/tests/arch/quicklogic/pp3/counter.ys
similarity index 75%
rename from yosys/tests/arch/quicklogic/counter.ys
rename to yosys/tests/arch/quicklogic/pp3/counter.ys
index 2e266417caf..5095cb8efe8 100644
--- a/yosys/tests/arch/quicklogic/counter.ys
+++ b/yosys/tests/arch/quicklogic/pp3/counter.ys
@@ -1,8 +1,8 @@
-read_verilog ../common/counter.v
+read_verilog ../../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -multiclock -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -assert -multiclock -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT1
diff --git a/yosys/tests/arch/quicklogic/pp3/dffs.ys b/yosys/tests/arch/quicklogic/pp3/dffs.ys
new file mode 100644
index 00000000000..f5023e48e14
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/pp3/dffs.ys
@@ -0,0 +1,33 @@
+read_verilog ../../common/dffs.v
+rename dff my_dff # Work around conflicting module names between test and vendor cells
+rename dffe my_dffe
+design -save read
+
+hierarchy -top my_dff
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd my_dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:ckpad
+select -assert-count 1 t:dffepc
+select -assert-count 1 t:inpad
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:logic_1
+select -assert-count 1 t:outpad
+
+select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:logic_1 t:outpad %% t:* %D
+
+design -load read
+hierarchy -top my_dffe
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd my_dffe # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:ckpad
+select -assert-count 1 t:dffepc
+select -assert-count 2 t:inpad
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:outpad
+
+select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:outpad %% t:* %D
diff --git a/yosys/tests/arch/quicklogic/fsm.ys b/yosys/tests/arch/quicklogic/pp3/fsm.ys
similarity index 81%
rename from yosys/tests/arch/quicklogic/fsm.ys
rename to yosys/tests/arch/quicklogic/pp3/fsm.ys
index 130dacf42a9..418db8025bd 100644
--- a/yosys/tests/arch/quicklogic/fsm.ys
+++ b/yosys/tests/arch/quicklogic/pp3/fsm.ys
@@ -1,9 +1,9 @@
-read_verilog ../common/fsm.v
+read_verilog ../../common/fsm.v
 hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic
+equiv_opt -run :prove -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic
 async2sync
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
diff --git a/yosys/tests/arch/quicklogic/latches.ys b/yosys/tests/arch/quicklogic/pp3/latches.ys
similarity index 96%
rename from yosys/tests/arch/quicklogic/latches.ys
rename to yosys/tests/arch/quicklogic/pp3/latches.ys
index bcef429904b..90a4f515b75 100644
--- a/yosys/tests/arch/quicklogic/latches.ys
+++ b/yosys/tests/arch/quicklogic/pp3/latches.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/latches.v
+read_verilog ../../common/latches.v
 design -save read
 
 hierarchy -top latchp
diff --git a/yosys/tests/arch/quicklogic/logic.ys b/yosys/tests/arch/quicklogic/pp3/logic.ys
similarity index 69%
rename from yosys/tests/arch/quicklogic/logic.ys
rename to yosys/tests/arch/quicklogic/pp3/logic.ys
index 4b327c00af7..ecddda577d3 100644
--- a/yosys/tests/arch/quicklogic/logic.ys
+++ b/yosys/tests/arch/quicklogic/pp3/logic.ys
@@ -1,7 +1,7 @@
-read_verilog ../common/logic.v
+read_verilog ../../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/yosys/tests/arch/quicklogic/mux.ys b/yosys/tests/arch/quicklogic/pp3/mux.ys
similarity index 71%
rename from yosys/tests/arch/quicklogic/mux.ys
rename to yosys/tests/arch/quicklogic/pp3/mux.ys
index ea17fa99b3d..a3b12a73d2a 100644
--- a/yosys/tests/arch/quicklogic/mux.ys
+++ b/yosys/tests/arch/quicklogic/pp3/mux.ys
@@ -1,9 +1,9 @@
-read_verilog ../common/mux.v
+read_verilog ../../common/mux.v
 design -save read
 
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT3
@@ -15,7 +15,7 @@ select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 3 t:LUT3
@@ -27,7 +27,7 @@ select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT1
@@ -41,7 +41,7 @@ select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT3
diff --git a/yosys/tests/arch/quicklogic/run-test.sh b/yosys/tests/arch/quicklogic/pp3/run-test.sh
similarity index 79%
rename from yosys/tests/arch/quicklogic/run-test.sh
rename to yosys/tests/arch/quicklogic/pp3/run-test.sh
index 4be4b70ae17..3f8515f9aa6 100755
--- a/yosys/tests/arch/quicklogic/run-test.sh
+++ b/yosys/tests/arch/quicklogic/pp3/run-test.sh
@@ -1,4 +1,4 @@
 #!/usr/bin/env bash
 set -eu
-source ../../gen-tests-makefile.sh
+source ../../../gen-tests-makefile.sh
 run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
diff --git a/yosys/tests/arch/quicklogic/tribuf.ys b/yosys/tests/arch/quicklogic/pp3/tribuf.ys
similarity index 67%
rename from yosys/tests/arch/quicklogic/tribuf.ys
rename to yosys/tests/arch/quicklogic/pp3/tribuf.ys
index de763009eaf..f68a0d7790e 100644
--- a/yosys/tests/arch/quicklogic/tribuf.ys
+++ b/yosys/tests/arch/quicklogic/pp3/tribuf.ys
@@ -1,10 +1,10 @@
-read_verilog ../common/tribuf.v
+read_verilog ../../common/tribuf.v
 hierarchy -top tristate
 proc
 tribuf
 flatten
 synth
-equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check
+equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 select -assert-count 2 t:inpad
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/.gitignore b/yosys/tests/arch/quicklogic/qlf_k6n10f/.gitignore
new file mode 100644
index 00000000000..fb232f235f3
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/.gitignore
@@ -0,0 +1 @@
+t_*.ys
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/add_sub.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/add_sub.ys
new file mode 100644
index 00000000000..30d9bbc9dc3
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/add_sub.ys
@@ -0,0 +1,8 @@
+read_verilog ../../common/add_sub.v
+hierarchy -top top
+equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 9 t:$lut # OOT flow has 8
+select -assert-count 8 t:adder_carry
+select -assert-none t:$lut t:adder_carry %% t:* %D
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/adffs.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/adffs.ys
new file mode 100644
index 00000000000..475355d2bd0
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/adffs.ys
@@ -0,0 +1,48 @@
+read_verilog ../../common/adffs.v
+design -save read
+
+hierarchy -top adff
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:$lut r:WIDTH=1 %i
+select -assert-none r:WIDTH>1
+select -assert-count 1 t:dffsre
+
+select -assert-none t:$lut t:dffsre %% t:* %D
+
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:dffsre
+
+select -assert-none t:dffsre %% t:* %D
+
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:$lut r:WIDTH=1 %i
+select -assert-none r:WIDTH>1
+select -assert-count 1 t:sdffsre
+
+select -assert-none t:$lut t:sdffsre %% t:* %D
+
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:sdffnsre
+
+select -assert-none t:sdffnsre %% t:* %D
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/counter.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/counter.ys
new file mode 100644
index 00000000000..ebb6ce243eb
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/counter.ys
@@ -0,0 +1,12 @@
+read_verilog ../../common/counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -multiclock -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 4 t:$lut
+select -assert-count 8 t:adder_carry
+select -assert-count 8 t:dffsre
+
+select -assert-none t:$lut t:adder_carry t:dffsre %% t:* %D
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/dffs.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/dffs.ys
new file mode 100644
index 00000000000..79a16c9412b
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/dffs.ys
@@ -0,0 +1,21 @@
+read_verilog ../../common/dffs.v
+rename dff my_dff # Work around conflicting module names between test and vendor cells
+rename dffe my_dffe
+design -save read
+
+hierarchy -top my_dff
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd my_dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:sdffsre
+select -assert-none t:sdffsre %% t:* %D 
+
+design -load read
+hierarchy -top my_dffe
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd my_dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:sdffsre
+select -assert-none t:sdffsre %% t:* %D 
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/dsp.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/dsp.ys
new file mode 100644
index 00000000000..1e652855bbd
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/dsp.ys
@@ -0,0 +1,121 @@
+read_verilog <<EOF
+module top(a, b, y, batch, clk);
+parameter [31:0] OPER_WIDTH=8;
+parameter [31:0] ACC_WIDTH=8;
+input wire batch;
+input wire clk;
+input wire [OPER_WIDTH-1:0] a;
+input wire [OPER_WIDTH-1:0] b;
+output reg [ACC_WIDTH-1:0] y;
+wire [ACC_WIDTH-1:0] ab = a * b;
+
+always @(posedge clk) begin
+	if (batch)
+		y <= ab;
+	else
+		y <= ab + y;
+end
+endmodule
+EOF
+
+design -save ast
+proc
+wreduce
+#equiv_opt -async2sync -map +/quicklogic/qlf_k6n10f/dsp_sim.v synth_quicklogic -family qlf_k6n10f
+#design -load postopt
+synth_quicklogic -family qlf_k6n10f
+cd top
+select -assert-count 1 t:QL_DSP2_MULTACC
+select -assert-none t:QL_DSP2_MULTACC %n t:* %i
+
+design -load ast
+chparam -set OPER_WIDTH 18
+chparam -set ACC_WIDTH 16
+proc
+wreduce
+synth_quicklogic -family qlf_k6n10f
+cd top
+select -assert-count 1 t:QL_DSP2_MULTACC
+select -assert-none t:QL_DSP2_MULTACC %n t:* %i
+
+design -load ast
+chparam -set OPER_WIDTH 19 # <-- too wide, shouldn't map to multacc
+chparam -set ACC_WIDTH 16
+proc
+wreduce
+synth_quicklogic -family qlf_k6n10f
+cd top
+select -assert-none t:QL_DSP2_MULTACC
+select -assert-count 1 t:QL_DSP2_MULT
+
+
+design -load ast
+chparam -set OPER_WIDTH 16
+chparam -set ACC_WIDTH 32
+proc
+
+synth_quicklogic -family qlf_k6n10f
+
+read_verilog -sv <<EOF
+module testbench(clk);
+localparam OPER_WIDTH=16;
+localparam ACC_WIDTH=32;
+localparam VECTORLEN=16;
+parameter PRIME1 = 237481091;
+parameter PRIME2 = 1752239;
+reg [OPER_WIDTH-1:0] a_vector [VECTORLEN-1:0];
+reg [OPER_WIDTH-1:0] b_vector [VECTORLEN-1:0];
+reg [ACC_WIDTH-1:0] y_vector [VECTORLEN-1:0];
+reg [0:0] batch_vector [VECTORLEN-1:0];
+
+integer j;
+integer a_, b_, y_, batch_;
+initial begin
+	y_ = 0;
+	a_ = 0;
+	b_ = 0;
+	y_vector[0] = 0;
+	for (j = 0; j < VECTORLEN; j = j + 1) begin
+		batch_ = (j % 4) == 0;
+		a_ = (a_ ^ (PRIME1 * j)) & ((1 << OPER_WIDTH) - 1);
+		b_ = (b_ ^ (PRIME2 * j)) & ((1 << OPER_WIDTH) - 1);
+		if (batch_)
+			y_ = a_ * b_;
+		else
+			y_ = a_ * b_ + y_;
+		a_vector[j] = a_;
+		b_vector[j] = b_;
+		y_vector[j + 1] = y_;
+		batch_vector[j] = batch_;
+	end
+end
+
+input wire clk;
+wire batch = batch_vector[i];
+wire [OPER_WIDTH-1:0] a = a_vector[i];
+wire [OPER_WIDTH-1:0] b = b_vector[i];
+wire [ACC_WIDTH-1:0] y_expected = y_vector[i];
+wire [ACC_WIDTH-1:0] y;
+top uut_top(
+	.batch(batch),
+	.clk(clk),
+	.a(a),
+	.b(b),
+	.y(y)
+);
+reg [7:0] i = 0;
+always @(posedge clk) begin
+	if (i < VECTORLEN) begin
+		// FIXME: for some reason the first assert fails (despite comparing zero to zero)
+		if (i > 0)
+			assert(y == y_expected);
+		i <= i + 1;
+	end
+end
+endmodule
+EOF
+read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v
+hierarchy -top testbench
+proc
+async2sync
+sim -assert -q -clock clk -n 20
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/fsm.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/fsm.ys
new file mode 100644
index 00000000000..e7a9d962d6e
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/fsm.ys
@@ -0,0 +1,17 @@
+read_verilog ../../common/fsm.v
+hierarchy -top fsm
+proc
+flatten
+
+equiv_opt -run :prove -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f
+async2sync
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+
+select -assert-count 9 t:$lut
+select -assert-count 6 t:sdffsre
+
+select -assert-none t:$lut t:sdffsre %% t:* %D
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/latches.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/latches.ys
new file mode 100644
index 00000000000..59574a1fb77
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/latches.ys
@@ -0,0 +1,29 @@
+read_verilog ../../common/latches.v
+design -save read
+
+hierarchy -top latchp
+proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f
+design -load postopt
+cd latchp
+select -assert-count 1 t:latchsre
+select -assert-none t:latchsre %% t:* %D
+
+design -load read
+hierarchy -top latchn
+proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f
+design -load postopt
+cd latchn
+select -assert-count 1 t:latchnsre
+select -assert-none t:latchnsre %% t:* %D
+
+design -load read
+hierarchy -top latchsr
+proc
+equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f
+design -load postopt
+cd latchsr
+select -assert-count 2 t:$lut
+select -assert-count 1 t:latchnsre
+select -assert-none t:$lut t:latchnsre %% t:* %D
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/logic.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/logic.ys
new file mode 100644
index 00000000000..a24d5a479f6
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/logic.ys
@@ -0,0 +1,10 @@
+read_verilog ../../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 9 t:$lut
+
+select -assert-none t:$lut %% t:* %D
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py b/yosys/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py
new file mode 100644
index 00000000000..b608e66eba9
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py
@@ -0,0 +1,463 @@
+from __future__ import annotations
+
+from dataclasses import dataclass
+
+
+blockram_template = """# ======================================
+log ** GENERATING TEST {top} WITH PARAMS{param_str}
+design -reset; read_verilog -defer ../../common/blockram.v
+chparam{param_str} {top}
+hierarchy -top {top}
+synth_quicklogic -family qlf_k6n10f -top {top}
+"""
+blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [
+    # TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH",  9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
+    # larger sizes need an extra ram
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 48)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 10)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
+    # 4096x20bit *can* fit in 3, albeit somewhat awkwardly
+    ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 20)], "sync_ram_*dp", ["-assert-min 3 t:TDP36K",
+                                                                   "-assert-max 4 t:TDP36K"]),
+
+    # smaller sizes can still fit in one, and assign the correct width (1, 2, 4, 8, 18 or 36)
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 32)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]),
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 24)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]),
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]),
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH",  9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]),
+    ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]),
+    ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH",  9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]),
+    ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH",  8)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]),
+    ([("ADDRESS_WIDTH", 13), ("DATA_WIDTH",  4)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=4 %i"]),
+    ([("ADDRESS_WIDTH", 14), ("DATA_WIDTH",  2)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=2 %i"]),
+    ([("ADDRESS_WIDTH", 15), ("DATA_WIDTH",  1)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=1 %i"]),
+
+    # 2x asymmetric (1024x36bit write / 2048x18bit read or vice versa = 1TDP36K)
+    ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH",  9), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH",  8), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
+
+    # 4x asymmetric (1024x36bit write / 4096x9bit read or vice versa = 1TDP36K)
+    ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH",  4), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH",  9), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH",  8), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
+
+    # can also use an extra TDP36K for higher width
+    ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH",  8), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 2 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 4 t:TDP36K"]),
+    ([("ADDRESS_WIDTH",  9), ("DATA_WIDTH", 36), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 4 t:TDP36K"]),
+
+    # # SHIFT=0 should be identical to sync_ram_sdp
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 0)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("SHIFT_VAL", 0)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]),
+
+    # asymmetric memories assign different port widths on a and b ports
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i a:port_b_width=18 %i"]),
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH",  9), ("SHIFT_VAL", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i a:port_b_width=9  %i"]),
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH",  9), ("SHIFT_VAL", 2)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i a:port_b_width=9  %i"]),
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i a:port_b_width=36 %i"]),
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH",  9), ("SHIFT_VAL", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9  %i a:port_b_width=18 %i"]),
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH",  9), ("SHIFT_VAL", 2)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9  %i a:port_b_width=36 %i"]),
+
+    # two disjoint 18K memories can share a single TDP36K
+    ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18),
+      ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16),
+      ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B",  8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH_A", 14), ("DATA_WIDTH_A",  1),
+      ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B",  8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]),
+    # but only if data width is <= 18
+    ([("ADDRESS_WIDTH_A",  9), ("DATA_WIDTH_A", 36),
+      ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B",  9)], "double_sync_ram_sdp", ["-assert-count 2 t:TDP36K"]),
+
+    # also for tdp
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 16)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH",  8)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH",  4)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 13), ("DATA_WIDTH",  2)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 14), ("DATA_WIDTH",  1)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]),
+    # still only if data width is <= 18
+    ([("ADDRESS_WIDTH",  9), ("DATA_WIDTH", 36)], "double_sync_ram_tdp", ["-assert-count 2 t:TDP36K"]),
+
+    # sharing a TDP36K sets is_split=1
+    ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18),
+      ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]),
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)],     "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]),
+    # an unshared TDP36K sets is_split=0
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)],     "sync_ram_*dp",        ["-assert-count 1 t:TDP36K a:is_split=0 %i"]),
+    ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)],     "sync_ram_sdp_w*r",    ["-assert-count 1 t:TDP36K a:is_split=0 %i"]),
+
+    # sharing a TDP36K sets correct port widths
+    ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ("DATA_WIDTH_B", 18), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp",
+     ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=18 %i",
+      "-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)],                                                    "double_sync_ram_tdp",
+     ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=18 %i",
+      "-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16), ("DATA_WIDTH_B", 8),  ("ADDRESS_WIDTH_B", 11)], "double_sync_ram_sdp",
+     ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=9  %i "
+                    + "t:TDP36K a:port_a2_width=18 %i a:port_a1_width=9  %i %u",
+      "-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH_A", 12), ("DATA_WIDTH_A", 4),  ("DATA_WIDTH_B", 12), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp",
+     ["-assert-count 1 t:TDP36K a:port_a1_width=4  %i a:port_a2_width=18 %i "
+                    + "t:TDP36K a:port_a2_width=4  %i a:port_a1_width=18 %i %u",
+      "-assert-count 1 t:TDP36K"]),
+    ([("ADDRESS_WIDTH_A", 13), ("DATA_WIDTH_A", 2),  ("DATA_WIDTH_B", 1),  ("ADDRESS_WIDTH_B", 14)], "double_sync_ram_sdp",
+     ["-assert-count 1 t:TDP36K a:port_a1_width=2  %i a:port_a2_width=1  %i "
+                    + "t:TDP36K a:port_a2_width=2  %i a:port_a1_width=1  %i %u",
+      "-assert-count 1 t:TDP36K"]),
+]
+
+sim_template = """\
+design -stash synthesized
+design -copy-from synthesized -as {top}_synth {top}
+design -delete synthesized
+read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
+read_verilog <<EOF
+`define MEM_TEST_VECTOR {mem_test_vector}
+
+`define UUT_SUBMODULE \\
+{uut_submodule}
+EOF
+read_verilog -defer -formal mem_tb.v
+chparam{param_str} -set VECTORLEN {vectorlen} TB
+hierarchy -top TB -check
+prep
+async2sync
+log ** CHECKING SIMULATION FOR TEST {top} WITH PARAMS{param_str}
+sim -clock clk -n {vectorlen} -assert
+"""
+
+sync_ram_sdp_submodule = """\
+sync_ram_sdp_synth uut (\\
+	.clk(clk),\\
+	.address_in_r(ra_a),\\
+	.data_out(rq_a),\\
+	.write_enable(wce_a),\\
+	.address_in_w(wa_a),\\
+	.data_in(wd_a)\\
+);\
+"""
+
+sync_ram_tdp_submodule = """\
+sync_ram_tdp_synth uut (\\
+	.clk_a(clk),\\
+	.clk_b(clk),\\
+	.write_enable_a(wce_a),\\
+	.write_enable_b(wce_b),\\
+	.read_enable_a(rce_a),\\
+	.read_enable_b(rce_b),\\
+	.addr_a(ra_a),\\
+	.addr_b(ra_b),\\
+	.read_data_a(rq_a),\\
+	.read_data_b(rq_b),\\
+	.write_data_a(wd_a),\\
+	.write_data_b(wd_b)\\
+);\
+"""
+
+sync_ram_sdp_wwr_submodule = """\
+sync_ram_sdp_wwr_synth uut (\\
+	.clk_w(clk),\\
+	.clk_r(clk),\\
+	.write_enable(wce_a),\\
+	.data_in(wd_a),\\
+	.address_in_w(wa_a),\\
+	.address_in_r(ra_a),\\
+	.data_out(rq_a)\\
+);\
+"""
+
+sync_ram_sdp_wrr_submodule = """\
+sync_ram_sdp_wrr_synth uut (\\
+	.clk_w(clk),\\
+	.clk_r(clk),\\
+	.write_enable(wce_a),\\
+	.data_in(wd_a),\\
+	.address_in_w(wa_a),\\
+	.address_in_r(ra_a),\\
+	.data_out(rq_a)\\
+);\
+"""
+
+double_sync_ram_sdp_submodule = """\
+double_sync_ram_sdp_synth uut (\\
+	.clk_a(clk),\\
+	.write_enable_a(wce_a),\\
+	.address_in_w_a(wa_a),\\
+	.address_in_r_a(ra_a),\\
+	.data_in_a(wd_a),\\
+	.data_out_a(rq_a),\\
+	.clk_b(clk),\\
+	.write_enable_b(wce_b),\\
+	.address_in_w_b(wa_b),\\
+	.address_in_r_b(ra_b),\\
+	.data_in_b(wd_b),\\
+	.data_out_b(rq_b)\\
+);\
+"""
+
+@dataclass
+class TestClass:
+    params: dict[str, int]
+    top: str
+    assertions: list[str]
+    test_steps: None | list[dict[str, int]]
+
+test_val_map = {
+    "rce_a": "rce_a_testvector",
+    "ra_a":  "ra_a_testvector",
+    "rq_a":  "rq_a_expected",
+    "wce_a": "wce_a_testvector",
+    "wa_a":  "wa_a_testvector",
+    "wd_a":  "wd_a_testvector",
+    "rce_b": "rce_b_testvector",
+    "ra_b":  "ra_b_testvector",
+    "rq_b":  "rq_b_expected",
+    "wce_b": "wce_b_testvector",
+    "wa_b":  "wa_b_testvector",
+    "wd_b":  "wd_b_testvector",
+}
+
+sim_tests: list[TestClass] = [
+    TestClass( # basic SDP test
+        # note that the common SDP model reads every cycle, but the testbench
+        # still uses the rce signal to check read assertions
+        params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 36},
+        top="sync_ram_sdp",
+        assertions=[],
+        test_steps=[
+            {"wce_a": 1, "wa_a": 0x0A, "wd_a": 0xdeadbeef},
+            {"wce_a": 1, "wa_a": 0xBA, "wd_a": 0x5a5a5a5a},
+            {"wce_a": 1, "wa_a": 0xFF, "wd_a": 0},
+            {"rce_a": 1, "ra_a": 0x0A},
+            {"rq_a": 0xdeadbeef},
+            {"rce_a": 1, "ra_a": 0xFF},
+            {"rq_a": 0},
+        ]
+    ),
+    TestClass( # SDP read before write
+        params={"ADDRESS_WIDTH": 4, "DATA_WIDTH": 16},
+        top="sync_ram_sdp",
+        assertions=[],
+        test_steps=[
+            {"wce_a": 1, "wa_a": 0xA, "wd_a": 0x1234},
+            {"wce_a": 1, "wa_a": 0xA, "wd_a": 0x5678, "rce_a": 1, "ra_a": 0xA},
+            {"rq_a": 0x1234, "rce_a": 1, "ra_a": 0xA},
+            {"rq_a": 0x5678},
+        ]
+    ),
+    TestClass( # basic TDP test
+        # note that the testbench uses ra and wa, while the common TDP model
+        # uses a shared address
+        params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 36},
+        top="sync_ram_tdp",
+        assertions=[],
+        test_steps=[
+            {"wce_a": 1, "ra_a": 0x0A,      "wce_b": 1, "ra_b": 0xBA,
+             "wd_a": 0xdeadbeef,            "wd_b": 0x5a5a5a5a},
+            {"wce_a": 1, "ra_a": 0xFF,
+             "wd_a": 0},
+            {"rce_a": 1, "ra_a": 0x0A,      "rce_b": 1, "ra_b": 0x0A},
+            {"rq_a": 0xdeadbeef,            "rq_b": 0xdeadbeef},
+            {"rce_a": 1, "ra_a": 0xFF,      "rce_b": 1, "ra_b": 0xBA},
+            {"rq_a": 0,                     "rq_b": 0x5a5a5a5a},
+        ]
+    ),
+    TestClass( # TDP with truncation
+        params={"ADDRESS_WIDTH": 4, "DATA_WIDTH": 16},
+        top="sync_ram_tdp",
+        assertions=[],
+        test_steps=[
+            {"wce_a": 1, "ra_a": 0x0F,      "wce_b": 1, "ra_b": 0xBA,
+             "wd_a": 0xdeadbeef,            "wd_b": 0x5a5a5a5a},
+            {"wce_a": 1, "ra_a": 0xFF,
+             "wd_a": 0},
+            {"rce_a": 1, "ra_a": 0x0F,      "rce_b": 1, "ra_b": 0x0A},
+            {"rq_a": 0,                     "rq_b": 0x00005a5a},
+        ]
+    ),
+    TestClass( # TDP read before write
+        # note that the testbench uses rce and wce, while the common TDP model
+        # uses a single enable for write, with reads on no write
+        params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 36},
+        top="sync_ram_tdp",
+        assertions=[],
+        test_steps=[
+            {"wce_a": 1, "ra_a": 0x0A,      "wce_b": 1, "ra_b": 0xBA,
+             "wd_a": 0xdeadbeef,            "wd_b": 0x5a5a5a5a},
+            {"wce_a": 1, "ra_a": 0xBA,      "rce_b": 1, "ra_b": 0xBA,
+             "wd_a": 0xa5a5a5a5},
+            {                               "rq_b": 0x5a5a5a5a},
+            {"rce_a": 1, "ra_a": 0x0A,      "rce_b": 1, "ra_b": 0x0A},
+            {"rq_a": 0xdeadbeef,            "rq_b": 0xdeadbeef},
+            {                               "rce_b": 1, "ra_b": 0xBA},
+            {                               "rq_b": 0xa5a5a5a5},
+        ]
+    ),
+    TestClass( # 2x wide write
+        params={"ADDRESS_WIDTH": 11, "DATA_WIDTH": 18, "SHIFT_VAL": 1},
+        top="sync_ram_sdp_wwr",
+        assertions=[],
+        test_steps=[
+            {"wce_a": 1, "wa_a": 0b0000000001, "wd_a": 0xdeadbeef},
+            {"rce_a": 0, "ra_a": 0b00000000010},
+            {"rq_a": 0xdead},
+            {"rce_a": 0, "ra_a": 0b00000000011},
+            {"rq_a": 0xbeef},
+        ]
+    ),
+    TestClass( # 4x wide write
+        params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 8, "SHIFT_VAL": 2},
+        top="sync_ram_sdp_wwr",
+        assertions=[],
+        test_steps=[
+            {"wce_a": 1, "wa_a": 0b000100001, "wd_a": 0xdeadbeef},
+            {"rce_a": 0, "ra_a": 0b00010000100},
+            {"rq_a": 0xde},
+            {"rce_a": 0, "ra_a": 0b00010000101},
+            {"rq_a": 0xad},
+            {"rce_a": 0, "ra_a": 0b00010000110},
+            {"rq_a": 0xbe},
+            {"rce_a": 0, "ra_a": 0b00010000111},
+            {"rq_a": 0xef},
+        ]
+    ),
+    TestClass( # 2x wide read
+        params={"ADDRESS_WIDTH": 11, "DATA_WIDTH": 18, "SHIFT_VAL": 1},
+        top="sync_ram_sdp_wrr",
+        assertions=[],
+        test_steps=[
+            {"wce_a": 1, "wa_a": 0b00000000010, "wd_a": 0xdead},
+            {"wce_a": 1, "wa_a": 0b00000000011, "wd_a": 0xbeef},
+            {"rce_a": 0, "ra_a": 0b0000000001},
+            {"rq_a": 0xdeadbeef},
+        ]
+    ),
+    TestClass( # 4x wide read
+        params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 8, "SHIFT_VAL": 2},
+        top="sync_ram_sdp_wrr",
+        assertions=[],
+        test_steps=[
+            {"wce_a": 1, "wa_a": 0b00010000100, "wd_a": 0xde},
+            {"wce_a": 1, "wa_a": 0b00010000101, "wd_a": 0xad},
+            {"wce_a": 1, "wa_a": 0b00010000110, "wd_a": 0xbe},
+            {"wce_a": 1, "wa_a": 0b00010000111, "wd_a": 0xef},
+            {"rce_a": 0, "ra_a": 0b000100001},
+            {"rq_a": 0xdeadbeef},
+        ]
+    ),
+    TestClass( # basic split SDP test
+        params={"ADDRESS_WIDTH_A": 10, "DATA_WIDTH_A": 16,
+                "ADDRESS_WIDTH_B": 10, "DATA_WIDTH_B": 16},
+        top="double_sync_ram_sdp",
+        assertions=[],
+        test_steps=[
+            {"wce_a": 1, "wa_a": 0x0A,      "wce_b": 1, "wa_b": 0xBA,
+            "wd_a": 0x1234,                 "wd_b": 0x4567},
+            {"wce_a": 1, "wa_a": 0xFF,      "wce_b": 1, "wa_b": 0x0A,
+            "wd_a": 0,                      "wd_b": 0xbeef},
+            {"rce_a": 1, "ra_a": 0x0A,      "rce_b": 1, "ra_b": 0x0A},
+            {"rq_a": 0x1234,                "rq_b": 0xbeef},
+        ]
+    ),
+]
+
+for (params, top, assertions) in blockram_tests:
+    sim_test = TestClass(
+        params=dict(params),
+        top=top,
+        assertions=assertions,
+        test_steps=None
+    )
+    sim_tests.append(sim_test)
+
+i = 0
+j = 0
+max_j = 16
+f = None
+for sim_test in sim_tests:
+    # format params
+    param_str = ""
+    for (key, val) in sim_test.params.items():
+        param_str += f" -set {key} {val}"
+
+    # resolve top module wildcards
+    top_list = [sim_test.top]
+    if "*dp" in sim_test.top:
+        top_list += [
+            sim_test.top.replace("*dp", dp_sub) for dp_sub in ["sdp", "tdp"]
+        ]
+    if "w*r" in sim_test.top:
+        top_list += [
+            sim_test.top.replace("w*r", wr_sub) for wr_sub in ["wwr", "wrr"]
+        ]
+    if len(top_list) > 1:
+        top_list.pop(0)
+
+    # iterate over string substitutions
+    for top in top_list:
+        # limit number of tests per file to allow parallel make
+        if not f:
+            fn = f"t_mem{i}.ys"
+            f = open(fn, mode="w")
+            j = 0
+
+        # output yosys script test file
+        print(
+            blockram_template.format(param_str=param_str, top=top),
+            file=f
+        )
+        for assertion in sim_test.assertions:
+            print("log ** CHECKING CELL COUNTS FOR TEST {top} WITH PARAMS{param_str}".format(param_str=param_str, top=top), file=f)
+            print("select {}".format(assertion), file=f)
+        print("", file=f)
+
+        # prepare simulation tests
+        test_steps = sim_test.test_steps
+        if test_steps:
+            if top == "sync_ram_sdp":
+                uut_submodule = sync_ram_sdp_submodule
+            elif top == "sync_ram_tdp":
+                uut_submodule = sync_ram_tdp_submodule
+            elif top == "sync_ram_sdp_wwr":
+                uut_submodule = sync_ram_sdp_wwr_submodule
+            elif top == "sync_ram_sdp_wrr":
+                uut_submodule = sync_ram_sdp_wrr_submodule
+            elif top == "double_sync_ram_sdp":
+                uut_submodule = double_sync_ram_sdp_submodule
+            else:
+                raise NotImplementedError(f"missing submodule header for {top}")
+            mem_test_vector = ""
+            for step, test in enumerate(test_steps):
+                for key, val in test.items():
+                    key = test_val_map[key]
+                    mem_test_vector += f"\\\n{key}[{step}] = 'h{val:x};"
+            print(
+                sim_template.format(
+                    top=top,
+                    mem_test_vector=mem_test_vector,
+                    uut_submodule=uut_submodule,
+                    param_str=param_str,
+                    vectorlen=len(test_steps) + 2
+                ), file=f
+            )
+            # simulation counts for 2 tests
+            j += 1
+
+        # increment test counter
+        j += 1
+        if j >= max_j:
+            f = f.close()
+            i += 1
+
+if f:
+    f.close()
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/yosys/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
new file mode 100644
index 00000000000..a0d15bd6222
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
@@ -0,0 +1,84 @@
+module TB(input clk);
+
+parameter ADDRESS_WIDTH = 10;
+parameter ADDRESS_WIDTH_A = ADDRESS_WIDTH;
+parameter ADDRESS_WIDTH_B = ADDRESS_WIDTH;
+parameter DATA_WIDTH = 36;
+parameter DATA_WIDTH_A = DATA_WIDTH;
+parameter DATA_WIDTH_B = DATA_WIDTH;
+parameter VECTORLEN = 16;
+parameter SHIFT_VAL = 0;
+
+// intentionally keep expected values at full width precision to allow testing
+// of truncation
+localparam MAX_WIDTH = 36;
+
+reg rce_a_testvector [VECTORLEN-1:0];
+reg [ADDRESS_WIDTH_A-1:0] ra_a_testvector [VECTORLEN-1:0];
+reg [MAX_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0];
+
+reg wce_a_testvector [VECTORLEN-1:0];
+reg [ADDRESS_WIDTH_A-1:0] wa_a_testvector [VECTORLEN-1:0];
+reg [DATA_WIDTH_A-1:0] wd_a_testvector [VECTORLEN-1:0];
+
+reg rce_b_testvector [VECTORLEN-1:0];
+reg [ADDRESS_WIDTH_B-1:0] ra_b_testvector [VECTORLEN-1:0];
+reg [MAX_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0];
+
+reg wce_b_testvector [VECTORLEN-1:0];
+reg [ADDRESS_WIDTH_B-1:0] wa_b_testvector [VECTORLEN-1:0];
+reg [DATA_WIDTH_B-1:0] wd_b_testvector [VECTORLEN-1:0];
+
+reg [$clog2(VECTORLEN)-1:0] i = 0;
+
+integer j;
+initial begin
+	for (j = 0; j < VECTORLEN; j = j + 1) begin
+		rce_a_testvector[j] = 1'b0;
+		ra_a_testvector[j] = 10'h0;
+		wce_a_testvector[j] = 1'b0;
+		wa_a_testvector[j] = 10'h0;
+		rce_b_testvector[j] = 1'b0;
+		ra_b_testvector[j] = 10'h0;
+		wce_b_testvector[j] = 1'b0;
+		wa_b_testvector[j] = 10'h0;
+
+	end
+
+	`MEM_TEST_VECTOR
+	
+end
+
+
+wire rce_a = rce_a_testvector[i];
+wire [ADDRESS_WIDTH_A-1:0] ra_a = ra_a_testvector[i];
+wire [MAX_WIDTH-1:0] rq_a_e = rq_a_expected[i];
+wire [DATA_WIDTH_A-1:0] rq_a;
+
+wire wce_a = wce_a_testvector[i];
+wire [ADDRESS_WIDTH_A-1:0] wa_a = wa_a_testvector[i];
+wire [DATA_WIDTH_A-1:0] wd_a = wd_a_testvector[i];
+
+wire rce_b = rce_b_testvector[i];
+wire [ADDRESS_WIDTH_B-1:0] ra_b = ra_b_testvector[i];
+wire [MAX_WIDTH-1:0] rq_b_e = rq_b_expected[i];
+wire [DATA_WIDTH_B-1:0] rq_b;
+
+wire wce_b = wce_b_testvector[i];
+wire [ADDRESS_WIDTH_B-1:0] wa_b = wa_b_testvector[i];
+wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i];
+
+`UUT_SUBMODULE
+
+always @(posedge clk) begin
+	if (i < VECTORLEN-1) begin
+		if (i > 0) begin
+			if($past(rce_a)) 
+				assert(rq_a == rq_a_e);
+			if($past(rce_b))
+				assert(rq_b == rq_b_e);
+		end
+		i <= i + 1;
+	end
+end
+endmodule
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/meminit.v b/yosys/tests/arch/quicklogic/qlf_k6n10f/meminit.v
new file mode 100644
index 00000000000..46a7dcac710
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/meminit.v
@@ -0,0 +1,50 @@
+module top(clk);
+parameter DEPTH_LOG2 = 10;
+parameter WIDTH = 36;
+parameter PRIME = 237481091;
+localparam DEPTH = 2**DEPTH_LOG2;
+
+input wire clk;
+
+(* syn_ramstyle = "block_ram" *)
+reg [WIDTH-1:0] mem [DEPTH-1:0];
+
+integer i;
+initial begin
+    for (i = 0; i < DEPTH; i = i + 1) begin
+        // Make up data by multiplying a large prime with the address,
+        // then cropping and retaining the lower bits
+        mem[i] = PRIME * i;
+    end
+end
+
+reg [DEPTH_LOG2-1:0] counter = 0;
+reg done = 1'b0;
+
+reg did_read = 1'b0;
+reg [DEPTH_LOG2-1:0] read_addr;
+reg [WIDTH-1:0] read_val;
+
+always @(posedge clk) begin
+    if (!done) begin
+        did_read <= 1'b1;
+        read_addr <= counter;
+        read_val <= mem[counter];
+    end else begin
+        did_read <= 1'b0; 
+    end
+
+    if (!done)
+        counter = counter + 1;
+    if (counter == 0)
+        done = 1;
+end
+
+wire [WIDTH-1:0] expect_val = PRIME * read_addr;
+always @(posedge clk) begin
+    if (did_read) begin
+        $display("addr %x expected %x actual %x", read_addr, expect_val, read_val);
+        assert(read_val == expect_val);
+    end
+end
+endmodule
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/meminit.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/meminit.ys
new file mode 100644
index 00000000000..8e9849c3b46
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/meminit.ys
@@ -0,0 +1,15 @@
+read_verilog -sv meminit.v
+chparam -set DEPTH_LOG2 3 -set WIDTH 36
+prep
+opt_dff
+prep -rdff
+synth_quicklogic -family qlf_k6n10f -run map_bram:map_bram
+select -assert-none t:$mem_v2 t:$mem
+select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K a:is_split=0 %i
+select -assert-count 1 t:TDP36K a:was_split_candidate=0 %i
+read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
+prep
+async2sync
+hierarchy -top top
+sim -assert -q -n 12 -clock clk
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/mux.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/mux.ys
new file mode 100644
index 00000000000..633b5fc8656
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/mux.ys
@@ -0,0 +1,40 @@
+read_verilog ../../common/mux.v
+design -save read
+
+hierarchy -top mux2
+proc
+equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:$lut r:WIDTH=3 %i
+select -assert-none t:$lut r:WIDTH=3 %i %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 1 t:$lut r:WIDTH=6 %i
+select -assert-none t:$lut r:WIDTH=6 %i %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 2 t:$lut r:WIDTH=6 %i
+select -assert-count 1 t:$lut r:WIDTH=3 %i
+select -assert-none t:$lut r:WIDTH=6 r:WIDTH=3 %u %i %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-max 5 t:$lut r:WIDTH=6 %i # OOT flow does 2
+select -assert-max 1 t:$lut r:WIDTH=3 %i # and here 1
+select -assert-max 1 t:$lut r:WIDTH=4 r:WIDTH=5 %u %i
+select -assert-none t:$lut r:WIDTH>2 %i %% t:* %D
diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/run-test.sh b/yosys/tests/arch/quicklogic/qlf_k6n10f/run-test.sh
new file mode 100755
index 00000000000..2fe33619418
--- /dev/null
+++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/run-test.sh
@@ -0,0 +1,5 @@
+#!/usr/bin/env bash
+set -eu
+python3 mem_gen.py
+source ../../../gen-tests-makefile.sh
+run_tests --yosys-scripts --bash
diff --git a/yosys/tests/arch/run-test.sh b/yosys/tests/arch/run-test.sh
index 5d923db560b..68f925b34d9 100755
--- a/yosys/tests/arch/run-test.sh
+++ b/yosys/tests/arch/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -e
 
@@ -16,7 +16,7 @@ for arch in ../../techlibs/*; do
 			done
 		else
 			echo -n "Test $path ->"
-			iverilog -t null -I$arch $path
+			iverilog -t null -I$arch -g2005-sv $path
 			echo " ok"
 		fi
 	done
diff --git a/yosys/tests/arch/xilinx/dsp_abc9.ys b/yosys/tests/arch/xilinx/dsp_abc9.ys
index ae4839d7f1f..1d74cfa89b2 100644
--- a/yosys/tests/arch/xilinx/dsp_abc9.ys
+++ b/yosys/tests/arch/xilinx/dsp_abc9.ys
@@ -30,6 +30,7 @@ module top(output [42:0] P);
 assert property (P == 42*42);
 endmodule
 EOT
+async2sync
 techmap -map +/xilinx/xc7_dsp_map.v
 verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1
 synth_xilinx -abc9
diff --git a/yosys/tests/asicworld/run-test.sh b/yosys/tests/asicworld/run-test.sh
index c22ab69281f..5131ed64688 100755
--- a/yosys/tests/asicworld/run-test.sh
+++ b/yosys/tests/asicworld/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 OPTIND=1
 seed=""    # default to no seed specified
diff --git a/yosys/tests/blif/run-test.sh b/yosys/tests/blif/run-test.sh
index 44ce7e6741f..e9698386e3a 100755
--- a/yosys/tests/blif/run-test.sh
+++ b/yosys/tests/blif/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
 for x in *.ys; do
   echo "Running $x.."
diff --git a/yosys/tests/bram/run-single.sh b/yosys/tests/bram/run-single.sh
index 429a79e3c6a..358423f3225 100644
--- a/yosys/tests/bram/run-single.sh
+++ b/yosys/tests/bram/run-single.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
 ../../yosys -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \
 		-l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v
diff --git a/yosys/tests/bram/run-test.sh b/yosys/tests/bram/run-test.sh
index d6ba0de4347..37fc91d0e56 100755
--- a/yosys/tests/bram/run-test.sh
+++ b/yosys/tests/bram/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 # run this test many times:
 # MAKE="make -j8" time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done'
diff --git a/yosys/tests/cxxrtl/.gitignore b/yosys/tests/cxxrtl/.gitignore
new file mode 100644
index 00000000000..91caee98625
--- /dev/null
+++ b/yosys/tests/cxxrtl/.gitignore
@@ -0,0 +1 @@
+cxxrtl-test-*
diff --git a/yosys/tests/cxxrtl/run-test.sh b/yosys/tests/cxxrtl/run-test.sh
new file mode 100755
index 00000000000..fd11a378379
--- /dev/null
+++ b/yosys/tests/cxxrtl/run-test.sh
@@ -0,0 +1,17 @@
+#!/bin/bash
+
+set -ex
+
+run_subtest () {
+    local subtest=$1; shift
+
+    ${CC:-gcc} -std=c++11 -O2 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++
+    ./cxxrtl-test-${subtest}
+}
+
+run_subtest value
+run_subtest value_fuzz
+
+# Compile-only test.
+../../yosys -p "read_verilog test_unconnected_output.v; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc"
+${CC:-gcc} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc
diff --git a/yosys/tests/cxxrtl/test_unconnected_output.v b/yosys/tests/cxxrtl/test_unconnected_output.v
new file mode 100644
index 00000000000..84d172bdbbf
--- /dev/null
+++ b/yosys/tests/cxxrtl/test_unconnected_output.v
@@ -0,0 +1,24 @@
+(* cxxrtl_blackbox *)
+module blackbox(...);
+    (* cxxrtl_edge = "p" *)
+    input clk;
+
+    (* cxxrtl_sync *)
+    output [7:0] out1;
+
+    (* cxxrtl_sync *)
+    output [7:0] out2;
+endmodule
+
+module unconnected_output(
+    input  clk,
+           in,
+    output out
+);
+    blackbox bb (
+        .clock (clock),
+        .in    (in),
+        .out1  (out),
+        .out2  (/* unconnected */),
+    );
+endmodule
diff --git a/yosys/tests/cxxrtl/test_value.cc b/yosys/tests/cxxrtl/test_value.cc
new file mode 100644
index 00000000000..0750d412e4e
--- /dev/null
+++ b/yosys/tests/cxxrtl/test_value.cc
@@ -0,0 +1,52 @@
+#include <cassert>
+#include <cstdint>
+
+#include "cxxrtl/cxxrtl.h"
+
+int main()
+{
+    {
+        // shl exceeding Bits should be masked
+        cxxrtl::value<6> a(1u);
+        cxxrtl::value<6> b(8u);
+        cxxrtl::value<6> c = a.shl(b);
+        assert(c.get<uint64_t>() == 0);
+    }
+
+    {
+        // sshr of unreasonably large size should sign extend correctly
+        cxxrtl::value<64> a(0u, 0x80000000u);
+        cxxrtl::value<64> b(0u, 1u);
+        cxxrtl::value<64> c = a.sshr(b);
+        assert(c.get<uint64_t>() == 0xffffffffffffffffu);
+    }
+
+    {
+        // sshr of exteeding Bits should sign extend correctly
+        cxxrtl::value<8> a(0x80u);
+        cxxrtl::value<8> b(10u);
+        cxxrtl::value<8> c = a.sshr(b);
+        assert(c.get<uint64_t>() == 0xffu);
+    }
+
+    {
+        // Sign extension should occur correctly
+        cxxrtl::value<64> a(0x23456789u, 0x8abcdef1u);
+        cxxrtl::value<8> b(32u);
+        cxxrtl::value<64> c = a.sshr(b);
+        assert(c.get<uint64_t>() == 0xffffffff8abcdef1u);
+    }
+
+    {
+        // ctlz should work with Bits that are a multiple of chunk size
+        cxxrtl::value<32> a(0x00040000u);
+        assert(a.ctlz() == 13);
+    }
+
+    {
+        // bmux clears top bits of result
+        cxxrtl::value<8> val(0x1fu);
+        cxxrtl::value<1> sel(0u);
+        assert(val.template bmux<4>(sel).get<uint64_t>() == 0xfu);
+    }
+}
diff --git a/yosys/tests/cxxrtl/test_value_fuzz.cc b/yosys/tests/cxxrtl/test_value_fuzz.cc
new file mode 100644
index 00000000000..7e8fbb0a926
--- /dev/null
+++ b/yosys/tests/cxxrtl/test_value_fuzz.cc
@@ -0,0 +1,357 @@
+#include <cinttypes>
+#include <cstddef>
+#include <cstdint>
+#include <cstdio>
+#include <exception>
+#include <limits>
+#include <random>
+#include <type_traits>
+
+#include "cxxrtl/cxxrtl.h"
+
+template<typename T>
+T rand_int(T min = std::numeric_limits<T>::min(), T max = std::numeric_limits<T>::max())
+{
+	static_assert(std::is_integral<T>::value, "T must be an integral type.");
+	static_assert(!std::is_same<T, signed char>::value && !std::is_same<T, unsigned char>::value,
+			  "Using char with uniform_int_distribution is undefined behavior.");
+
+	static std::mt19937 generator = [] {
+		std::random_device rd;
+		std::mt19937 mt{rd()};
+		return mt;
+	}();
+
+	std::uniform_int_distribution<T> dist(min, max);
+	return dist(generator);
+}
+
+int64_t sext(size_t bits, uint64_t value)
+{
+	return (int64_t)(value << (64 - bits)) >> (64 - bits);
+}
+
+struct BinaryOperationBase
+{
+	void tweak_input(uint64_t &a, uint64_t &b) {}
+};
+
+template<size_t Bits, typename Operation>
+void test_binary_operation_for_bitsize(Operation &op)
+{
+	constexpr int iteration_count = 10000000;
+
+	constexpr uint64_t mask = std::numeric_limits<uint64_t>::max() >> (64 - Bits);
+
+	using chunk_type = typename cxxrtl::value<Bits>::chunk::type;
+	constexpr size_t chunk_bits = cxxrtl::value<Bits>::chunk::bits;
+
+	for (int iteration = 0; iteration < iteration_count; iteration++) {
+		uint64_t ia = rand_int<uint64_t>() >> (64 - Bits);
+		uint64_t ib = rand_int<uint64_t>() >> (64 - Bits);
+		op.tweak_input(ia, ib);
+
+		cxxrtl::value<Bits> va, vb;
+		for (size_t i = 0; i * chunk_bits < Bits; i++) {
+			va.data[i] = (chunk_type)(ia >> (i * chunk_bits));
+			vb.data[i] = (chunk_type)(ib >> (i * chunk_bits));
+		}
+
+		uint64_t iresult = op.reference_impl(Bits, ia, ib) & mask;
+		cxxrtl::value<Bits> vresult = op.template testing_impl<Bits>(va, vb);
+
+		for (size_t i = 0; i * chunk_bits < Bits; i++) {
+			if ((chunk_type)(iresult >> (i * chunk_bits)) != vresult.data[i]) {
+				std::printf("Test failure:\n");
+				std::printf("Bits:    %zu\n", Bits);
+				std::printf("a:       %016" PRIx64 "\n", ia);
+				std::printf("b:       %016" PRIx64 "\n", ib);
+				std::printf("iresult: %016" PRIx64 "\n", iresult);
+				std::printf("vresult: %016" PRIx64 "\n", vresult.template get<uint64_t>());
+
+				std::terminate();
+			}
+		}
+	}
+	std::printf("Test passed @ Bits = %zu.\n", Bits);
+}
+
+template<typename Operation>
+void test_binary_operation(Operation &op)
+{
+	// Test at a variety of bitwidths
+	test_binary_operation_for_bitsize<8>(op);
+	test_binary_operation_for_bitsize<32>(op);
+	test_binary_operation_for_bitsize<42>(op);
+	test_binary_operation_for_bitsize<63>(op);
+	test_binary_operation_for_bitsize<64>(op);
+}
+
+template<typename Operation>
+struct UnaryOperationWrapper : BinaryOperationBase 
+{
+	Operation &op;
+
+	UnaryOperationWrapper(Operation &op) : op(op) {}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		return op.reference_impl(bits, a);
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return op.template testing_impl<Bits>(a);
+	}
+};
+
+template<typename Operation>
+void test_unary_operation(Operation &op)
+{
+	UnaryOperationWrapper<Operation> wrapped(op);
+	test_binary_operation(wrapped);
+}
+
+struct ShlTest : BinaryOperationBase 
+{
+	ShlTest()
+	{
+		std::printf("Randomized tests for value::shl:\n");
+		test_binary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		return b >= 64 ? 0 : a << b;
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return a.shl(b);
+	}
+
+	void tweak_input(uint64_t &, uint64_t &b)
+	{
+		b &= 0x7f;
+	}
+} shl;
+
+struct ShrTest : BinaryOperationBase 
+{
+	ShrTest()
+	{
+		std::printf("Randomized tests for value::shr:\n");
+		test_binary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		return b >= 64 ? 0 : a >> b;
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return a.shr(b);
+	}
+
+	void tweak_input(uint64_t &, uint64_t &b)
+	{
+		b &= 0x7f;
+	}
+} shr;
+
+struct SshrTest : BinaryOperationBase 
+{
+	SshrTest()
+	{
+		std::printf("Randomized tests for value::sshr:\n");
+		test_binary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		int64_t sa = (int64_t)(a << (64 - bits));
+		return sa >> (b >= bits ? 63 : (b + 64 - bits));
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return a.sshr(b);
+	}
+
+	void tweak_input(uint64_t &, uint64_t &b)
+	{
+		b &= 0x7f;
+	}
+} sshr;
+
+struct AddTest : BinaryOperationBase 
+{
+	AddTest()
+	{
+		std::printf("Randomized tests for value::add:\n");
+		test_binary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		return a + b;
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return a.add(b);
+	}
+} add;
+
+struct SubTest : BinaryOperationBase 
+{
+	SubTest()
+	{
+		std::printf("Randomized tests for value::sub:\n");
+		test_binary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		return a - b;
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return a.sub(b);
+	}
+} sub;
+
+struct CtlzTest
+{
+	CtlzTest()
+	{
+		std::printf("Randomized tests for value::ctlz:\n");
+		test_unary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a)
+	{
+		if (a == 0)
+			return bits;
+		return __builtin_clzl(a) - (64 - bits);
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a)
+	{
+		size_t result = a.ctlz();
+		return cxxrtl::value<Bits>((cxxrtl::chunk_t)result);
+	}
+} ctlz;
+
+struct UdivTest : BinaryOperationBase
+{
+	UdivTest()
+	{
+		std::printf("Randomized tests for value::udivmod (div):\n");
+		test_binary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		return a / b;
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return std::get<0>(a.udivmod(b));
+	}
+
+	void tweak_input(uint64_t &, uint64_t &b)
+	{
+		if (b == 0) b = 1; // Avoid divide by zero
+	}
+} udiv;
+
+struct UmodTest : BinaryOperationBase
+{
+	UmodTest()
+	{
+		std::printf("Randomized tests for value::udivmod (mod):\n");
+		test_binary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		return a % b;
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return std::get<1>(a.udivmod(b));
+	}
+
+	void tweak_input(uint64_t &, uint64_t &b)
+	{
+		if (b == 0) b = 1; // Avoid divide by zero
+	}
+} umod;
+
+struct SdivTest : BinaryOperationBase
+{
+	SdivTest()
+	{
+		std::printf("Randomized tests for value::sdivmod (div):\n");
+		test_binary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		return (uint64_t)(sext(bits, a) / sext(bits, b));
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return std::get<0>(a.sdivmod(b));
+	}
+
+	void tweak_input(uint64_t &, uint64_t &b)
+	{
+		if (b == 0) b = 1; // Avoid divide by zero
+	}
+} sdiv;
+
+struct SmodTest : BinaryOperationBase
+{
+	SmodTest()
+	{
+		std::printf("Randomized tests for value::sdivmod (mod):\n");
+		test_binary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		return (uint64_t)(sext(bits, a) % sext(bits, b));
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return std::get<1>(a.sdivmod(b));
+	}
+
+	void tweak_input(uint64_t &, uint64_t &b)
+	{
+		if (b == 0) b = 1; // Avoid divide by zero
+	}
+} smod;
+
+int main()
+{
+}
diff --git a/yosys/tests/fmt/.gitignore b/yosys/tests/fmt/.gitignore
new file mode 100644
index 00000000000..a36a15ec464
--- /dev/null
+++ b/yosys/tests/fmt/.gitignore
@@ -0,0 +1,3 @@
+*.log
+iverilog-*
+yosys-*
diff --git a/yosys/tests/fmt/always_comb.v b/yosys/tests/fmt/always_comb.v
new file mode 100644
index 00000000000..7147786bebf
--- /dev/null
+++ b/yosys/tests/fmt/always_comb.v
@@ -0,0 +1,24 @@
+module top(input clk);
+    reg a = 0;
+    reg b = 0;
+    wire y;
+
+    sub s (.a(a), .b(b), .y(y));
+
+	always @(posedge clk) begin
+        a <= (!a && !b) || (a && !b);
+        b <= (a && !b) || (a && b);
+    end
+endmodule
+
+module sub(input a, input b, output wire y);
+    assign y = a & b;
+
+    // Not fit for our purposes: always @* if (a) $display(a, b, y);
+    //
+    // We compare output against iverilog, but async iverilog $display fires
+    // even before values have propagated -- i.e. combinations of a/b/y will be
+    // shown where a & b are both 1, but y has not yet taken the value 1.  We
+    // don't, so we specify it in the conditional.
+    always @* if (y & (y == (a & b))) $display(a, b, y);
+endmodule
diff --git a/yosys/tests/fmt/always_comb_tb.cc b/yosys/tests/fmt/always_comb_tb.cc
new file mode 100644
index 00000000000..5812500535a
--- /dev/null
+++ b/yosys/tests/fmt/always_comb_tb.cc
@@ -0,0 +1,16 @@
+#include "yosys-always_comb.cc"
+
+int main()
+{
+	cxxrtl_design::p_top uut1, uut2;
+
+	for (int i = 0; i < 20; ++i) {
+		uut1.p_clk.set(!uut1.p_clk);
+		uut1.step();
+
+		uut2.p_clk.set(!uut2.p_clk);
+		uut2.step();
+	}
+
+	return 0;
+}
diff --git a/yosys/tests/fmt/always_comb_tb.v b/yosys/tests/fmt/always_comb_tb.v
new file mode 100644
index 00000000000..3cc4496a04f
--- /dev/null
+++ b/yosys/tests/fmt/always_comb_tb.v
@@ -0,0 +1,9 @@
+module tb;
+    reg clk = 0;
+
+    top uut1 (.clk(clk));
+    top uut2 (.clk(clk));
+
+    always #1 clk <= ~clk;
+    initial #20 $finish;
+endmodule
diff --git a/yosys/tests/fmt/always_display.v b/yosys/tests/fmt/always_display.v
new file mode 100644
index 00000000000..593c5afc08c
--- /dev/null
+++ b/yosys/tests/fmt/always_display.v
@@ -0,0 +1,17 @@
+module m(input clk, rst, en, input [31:0] data);
+
+`ifdef EVENT_CLK
+	always @(posedge clk)
+`endif
+`ifdef EVENT_CLK_RST
+	always @(posedge clk or negedge rst)
+`endif
+`ifdef EVENT_STAR
+	always @(*)
+`endif
+`ifdef COND_EN
+		if (en)
+`endif
+			$display("data=%d", data);
+
+endmodule
diff --git a/yosys/tests/fmt/always_full.v b/yosys/tests/fmt/always_full.v
new file mode 100644
index 00000000000..4d3df7a615c
--- /dev/null
+++ b/yosys/tests/fmt/always_full.v
@@ -0,0 +1,236 @@
+module always_full(input clk);
+
+	always @(posedge clk) begin
+
+		$display("==> small unsigned %%d");
+		$display(":%d:",      16'haa);
+		$display(":%-d:",     16'haa);
+		$display(":%+d:",     16'haa);
+		$display(":%+-d:",    16'haa);
+		$display(":%0d:",     16'haa);
+		$display(":%-0d:",    16'haa);
+		$display(":%+0d:",    16'haa);
+		$display(":%+-0d:",   16'haa);
+		$display(":%20d:",    16'haa);
+		$display(":%-20d:",   16'haa);
+		$display(":%+20d:",   16'haa);
+		$display(":%+-20d:",  16'haa);
+		$display(":%020d:",   16'haa);
+		$display(":%-020d:",  16'haa);
+		$display(":%+020d:",  16'haa);
+		$display(":%+-020d:", 16'haa);
+
+		$display("==> big unsigned %%d");
+		$display(":%d:",      16'haaaa);
+		$display(":%-d:",     16'haaaa);
+		$display(":%+d:",     16'haaaa);
+		$display(":%+-d:",    16'haaaa);
+		$display(":%0d:",     16'haaaa);
+		$display(":%-0d:",    16'haaaa);
+		$display(":%+0d:",    16'haaaa);
+		$display(":%+-0d:",   16'haaaa);
+		$display(":%20d:",    16'haaaa);
+		$display(":%-20d:",   16'haaaa);
+		$display(":%+20d:",   16'haaaa);
+		$display(":%+-20d:",  16'haaaa);
+		$display(":%020d:",   16'haaaa);
+		$display(":%-020d:",  16'haaaa);
+		$display(":%+020d:",  16'haaaa);
+		$display(":%+-020d:", 16'haaaa);
+
+		$display("==> small signed %%d");
+		$display(":%d:",      16'shaa);
+		$display(":%-d:",     16'shaa);
+		$display(":%+d:",     16'shaa);
+		$display(":%+-d:",    16'shaa);
+		$display(":%0d:",     16'shaa);
+		$display(":%-0d:",    16'shaa);
+		$display(":%+0d:",    16'shaa);
+		$display(":%+-0d:",   16'shaa);
+		$display(":%20d:",    16'shaa);
+		$display(":%-20d:",   16'shaa);
+		$display(":%+20d:",   16'shaa);
+		$display(":%+-20d:",  16'shaa);
+		$display(":%020d:",   16'shaa);
+		$display(":%-020d:",  16'shaa);
+		$display(":%+020d:",  16'shaa);
+		$display(":%+-020d:", 16'shaa);
+
+		$display("==> big signed %%d");
+		$display(":%d:",      16'shaaaa);
+		$display(":%-d:",     16'shaaaa);
+		$display(":%+d:",     16'shaaaa);
+		$display(":%+-d:",    16'shaaaa);
+		$display(":%0d:",     16'shaaaa);
+		$display(":%-0d:",    16'shaaaa);
+		$display(":%+0d:",    16'shaaaa);
+		$display(":%+-0d:",   16'shaaaa);
+		$display(":%20d:",    16'shaaaa);
+		$display(":%-20d:",   16'shaaaa);
+		$display(":%+20d:",   16'shaaaa);
+		$display(":%+-20d:",  16'shaaaa);
+		$display(":%020d:",   16'shaaaa);
+		$display(":%-020d:",  16'shaaaa);
+		$display(":%+020d:",  16'shaaaa);
+		$display(":%+-020d:", 16'shaaaa);
+
+		$display("==> small unsigned %%h");
+		$display(":%h:",      16'haa);
+		$display(":%-h:",     16'haa);
+		$display(":%0h:",     16'haa);
+		$display(":%-0h:",    16'haa);
+		$display(":%20h:",    16'haa);
+		$display(":%-20h:",   16'haa);
+		$display(":%020h:",   16'haa);
+		$display(":%-020h:",  16'haa);
+
+		$display("==> big unsigned %%h");
+		$display(":%h:",      16'haaaa);
+		$display(":%-h:",     16'haaaa);
+		$display(":%0h:",     16'haaaa);
+		$display(":%-0h:",    16'haaaa);
+		$display(":%20h:",    16'haaaa);
+		$display(":%-20h:",   16'haaaa);
+		$display(":%020h:",   16'haaaa);
+		$display(":%-020h:",  16'haaaa);
+
+		$display("==> small signed %%h");
+		$display(":%h:",      16'shaa);
+		$display(":%-h:",     16'shaa);
+		$display(":%0h:",     16'shaa);
+		$display(":%-0h:",    16'shaa);
+		$display(":%20h:",    16'shaa);
+		$display(":%-20h:",   16'shaa);
+		$display(":%020h:",   16'shaa);
+		$display(":%-020h:",  16'shaa);
+
+		$display("==> big signed %%h");
+		$display(":%h:",      16'shaaaa);
+		$display(":%-h:",     16'shaaaa);
+		$display(":%0h:",     16'shaaaa);
+		$display(":%-0h:",    16'shaaaa);
+		$display(":%20h:",    16'shaaaa);
+		$display(":%-20h:",   16'shaaaa);
+		$display(":%020h:",   16'shaaaa);
+		$display(":%-020h:",  16'shaaaa);
+
+		$display("==> small unsigned %%o");
+		$display(":%o:",      16'haa);
+		$display(":%-o:",     16'haa);
+		$display(":%0o:",     16'haa);
+		$display(":%-0o:",    16'haa);
+		$display(":%20o:",    16'haa);
+		$display(":%-20o:",   16'haa);
+		$display(":%020o:",   16'haa);
+		$display(":%-020o:",  16'haa);
+
+		$display("==> big unsigned %%o");
+		$display(":%o:",      16'haaaa);
+		$display(":%-o:",     16'haaaa);
+		$display(":%0o:",     16'haaaa);
+		$display(":%-0o:",    16'haaaa);
+		$display(":%20o:",    16'haaaa);
+		$display(":%-20o:",   16'haaaa);
+		$display(":%020o:",   16'haaaa);
+		$display(":%-020o:",  16'haaaa);
+
+		$display("==> small signed %%o");
+		$display(":%o:",      16'shaa);
+		$display(":%-o:",     16'shaa);
+		$display(":%0o:",     16'shaa);
+		$display(":%-0o:",    16'shaa);
+		$display(":%20o:",    16'shaa);
+		$display(":%-20o:",   16'shaa);
+		$display(":%020o:",   16'shaa);
+		$display(":%-020o:",  16'shaa);
+
+		$display("==> big signed %%o");
+		$display(":%o:",      16'shaaaa);
+		$display(":%-o:",     16'shaaaa);
+		$display(":%0o:",     16'shaaaa);
+		$display(":%-0o:",    16'shaaaa);
+		$display(":%20o:",    16'shaaaa);
+		$display(":%-20o:",   16'shaaaa);
+		$display(":%020o:",   16'shaaaa);
+		$display(":%-020o:",  16'shaaaa);
+
+		$display("==> small unsigned %%b");
+		$display(":%b:",      16'haa);
+		$display(":%-b:",     16'haa);
+		$display(":%0b:",     16'haa);
+		$display(":%-0b:",    16'haa);
+		$display(":%20b:",    16'haa);
+		$display(":%-20b:",   16'haa);
+		$display(":%020b:",   16'haa);
+		$display(":%-020b:",  16'haa);
+
+		$display("==> big unsigned %%b");
+		$display(":%b:",      16'haaaa);
+		$display(":%-b:",     16'haaaa);
+		$display(":%0b:",     16'haaaa);
+		$display(":%-0b:",    16'haaaa);
+		$display(":%20b:",    16'haaaa);
+		$display(":%-20b:",   16'haaaa);
+		$display(":%020b:",   16'haaaa);
+		$display(":%-020b:",  16'haaaa);
+
+		$display("==> small signed %%b");
+		$display(":%b:",      16'shaa);
+		$display(":%-b:",     16'shaa);
+		$display(":%0b:",     16'shaa);
+		$display(":%-0b:",    16'shaa);
+		$display(":%20b:",    16'shaa);
+		$display(":%-20b:",   16'shaa);
+		$display(":%020b:",   16'shaa);
+		$display(":%-020b:",  16'shaa);
+
+		$display("==> big signed %%b");
+		$display(":%b:",      16'shaaaa);
+		$display(":%-b:",     16'shaaaa);
+		$display(":%0b:",     16'shaaaa);
+		$display(":%-0b:",    16'shaaaa);
+		$display(":%20b:",    16'shaaaa);
+		$display(":%-20b:",   16'shaaaa);
+		$display(":%020b:",   16'shaaaa);
+		$display(":%-020b:",  16'shaaaa);
+
+		$display("==> time %%t");
+		$display(":%t:",      $time);
+		$display(":%-t:",     $time);
+		$display(":%0t:",     $time);
+		$display(":%-0t:",    $time);
+		$display(":%10t:",    $time);
+		$display(":%-10t:",   $time);
+		$display(":%015t:",   $time);
+		$display(":%-015t:",  $time);
+
+		$display("===> %%s");
+		$display(":%10s:", "foo");
+		$display(":%010s:", "foo");
+		$display(":%-10s:", "foo");
+		$display(":%-010s:", "foo");
+
+		$display("===> %%c");
+		$display(":%10c:", "foo");
+		$display(":%010c:", "foo");
+		$display(":%-10c:", "foo");
+		$display(":%-010c:", "foo");
+
+		$display("==> aliases");
+		$display(":%x:",      16'shaa);
+		$display(":%X:",      16'shaa);
+		$display(":%H:",      16'shaa);
+		$display(":%O:",      16'shaa);
+		$display(":%B:",      16'shaa);
+
+		$display("==> default base");
+		$displayh(16'haa);
+		$displayo(16'haa);
+		$displayb(16'haa);
+
+		$display("==> write/format");
+		$display("%d", 1, "%d", 1);
+
+	end
+
+endmodule
diff --git a/yosys/tests/fmt/always_full_tb.cc b/yosys/tests/fmt/always_full_tb.cc
new file mode 100644
index 00000000000..94991ca25b5
--- /dev/null
+++ b/yosys/tests/fmt/always_full_tb.cc
@@ -0,0 +1,14 @@
+#include "yosys-always_full.cc"
+
+int main()
+{
+	struct : public performer {
+		int64_t vlog_time() const override { return 1; }
+		void on_print(const lazy_fmt &output, const cxxrtl::metadata_map &) override { std::cerr << output(); }
+	} performer;
+
+	cxxrtl_design::p_always__full uut;
+	uut.p_clk.set(!uut.p_clk);
+	uut.step(&performer);
+	return 0;
+}
diff --git a/yosys/tests/fmt/always_full_tb.v b/yosys/tests/fmt/always_full_tb.v
new file mode 100644
index 00000000000..0c2599cc263
--- /dev/null
+++ b/yosys/tests/fmt/always_full_tb.v
@@ -0,0 +1,12 @@
+module always_full_tb;
+
+    reg clk = 0;
+
+    always_full uut (.clk(clk));
+
+    always begin
+        #1 clk <= ~clk;
+        #1 $finish;
+    end
+
+endmodule
diff --git a/yosys/tests/fmt/display_lm.v b/yosys/tests/fmt/display_lm.v
new file mode 100644
index 00000000000..d96f233f064
--- /dev/null
+++ b/yosys/tests/fmt/display_lm.v
@@ -0,0 +1,12 @@
+module top;
+    mid mid_uut ();
+endmodule
+
+module mid ();
+    bot bot_uut ();
+endmodule
+
+module bot ();
+    initial $display("%%l: %l\n%%m: %m");
+    always $display("%%l: %l\n%%m: %m");
+endmodule
diff --git a/yosys/tests/fmt/display_lm_tb.cc b/yosys/tests/fmt/display_lm_tb.cc
new file mode 100644
index 00000000000..7a593d72919
--- /dev/null
+++ b/yosys/tests/fmt/display_lm_tb.cc
@@ -0,0 +1,9 @@
+#include "yosys-display_lm.cc"
+
+int main()
+{
+	cxxrtl_design::p_top uut;
+
+	uut.step();
+	return 0;
+}
diff --git a/yosys/tests/fmt/fuzz/.gitignore b/yosys/tests/fmt/fuzz/.gitignore
new file mode 100644
index 00000000000..88ea7e2ef91
--- /dev/null
+++ b/yosys/tests/fmt/fuzz/.gitignore
@@ -0,0 +1,2 @@
+fuzztest
+build
diff --git a/yosys/tests/fmt/fuzz/CMakeLists.txt b/yosys/tests/fmt/fuzz/CMakeLists.txt
new file mode 100644
index 00000000000..6f7c43da888
--- /dev/null
+++ b/yosys/tests/fmt/fuzz/CMakeLists.txt
@@ -0,0 +1,23 @@
+cmake_minimum_required(VERSION 3.14)
+project(cxxrtl_division_fuzz)
+
+set(CMAKE_CXX_STANDARD 17)
+
+add_subdirectory(fuzztest)
+
+enable_testing()
+
+include(GoogleTest)
+
+fuzztest_setup_fuzzing_flags()
+
+include_directories(../../..)
+
+add_executable(
+    x_test
+    x_test.cc
+    ../../../libs/bigint/BigUnsigned.cc
+)
+
+link_fuzztest(x_test)
+gtest_discover_tests(x_test)
diff --git a/yosys/tests/fmt/fuzz/x_test.cc b/yosys/tests/fmt/fuzz/x_test.cc
new file mode 100644
index 00000000000..ee061861f90
--- /dev/null
+++ b/yosys/tests/fmt/fuzz/x_test.cc
@@ -0,0 +1,44 @@
+#include "fuzztest/fuzztest.h"
+#include "gtest/gtest.h"
+
+#include <sstream>
+#include "backends/cxxrtl/cxxrtl.h"
+#include "libs/bigint/BigUnsigned.hh"
+
+using namespace cxxrtl_yosys;
+
+void Formats128BitIntegers(chunk_t x0, chunk_t x1, chunk_t x2, chunk_t x3, bool signed_)
+{
+  // Compare output to BigUnsigned.
+  value<128> v;
+  v = v.blit<127, 64>(value<64>{x1, x0});
+  v = v.blit<63, 0>(value<64>{x3, x2});
+
+  std::ostringstream oss;
+  oss << value_formatted<128>(v, false, false, ' ', 0, 10, signed_, false, false);
+  auto actual = oss.str();
+
+  BigUnsigned u;
+  bool negative = signed_ && v.is_neg();
+  if (negative)
+    v = v.neg();
+  u.bitShiftLeft(v.slice<127, 64>().val().get<uint64_t>(), 64);
+  u.bitOr(u, v.slice<63, 0>().val().get<uint64_t>());
+
+  std::string expected;
+
+  if (u.isZero()) {
+    expected = "0";
+  } else {
+    while (!u.isZero()) {
+      expected += '0' + (u % 10).toInt();
+      u /= 10;
+    }
+    if (negative)
+      expected += '-';
+    std::reverse(expected.begin(), expected.end());
+  }
+
+  EXPECT_EQ(actual, expected);
+}
+FUZZ_TEST(CxxrtlDivisionFuzz, Formats128BitIntegers);
diff --git a/yosys/tests/fmt/initial_display.v b/yosys/tests/fmt/initial_display.v
new file mode 100644
index 00000000000..d3ef9ed7691
--- /dev/null
+++ b/yosys/tests/fmt/initial_display.v
@@ -0,0 +1,255 @@
+module m;
+	initial $display("<<<BEGIN>>>");
+
+	initial $display("==> small unsigned %%d");
+	initial $display(":%d:",      16'haa);
+	initial $display(":%-d:",     16'haa);
+	initial $display(":%+d:",     16'haa);
+	initial $display(":%+-d:",    16'haa);
+	initial $display(":%0d:",     16'haa);
+	initial $display(":%-0d:",    16'haa);
+	initial $display(":%+0d:",    16'haa);
+	initial $display(":%+-0d:",   16'haa);
+	initial $display(":%20d:",    16'haa);
+	initial $display(":%-20d:",   16'haa);
+	initial $display(":%+20d:",   16'haa);
+	initial $display(":%+-20d:",  16'haa);
+	initial $display(":%020d:",   16'haa);
+	initial $display(":%-020d:",  16'haa);
+	initial $display(":%+020d:",  16'haa);
+	initial $display(":%+-020d:", 16'haa);
+
+	initial $display("==> big unsigned %%d");
+	initial $display(":%d:",      16'haaaa);
+	initial $display(":%-d:",     16'haaaa);
+	initial $display(":%+d:",     16'haaaa);
+	initial $display(":%+-d:",    16'haaaa);
+	initial $display(":%0d:",     16'haaaa);
+	initial $display(":%-0d:",    16'haaaa);
+	initial $display(":%+0d:",    16'haaaa);
+	initial $display(":%+-0d:",   16'haaaa);
+	initial $display(":%20d:",    16'haaaa);
+	initial $display(":%-20d:",   16'haaaa);
+	initial $display(":%+20d:",   16'haaaa);
+	initial $display(":%+-20d:",  16'haaaa);
+	initial $display(":%020d:",   16'haaaa);
+	initial $display(":%-020d:",  16'haaaa);
+	initial $display(":%+020d:",  16'haaaa);
+	initial $display(":%+-020d:", 16'haaaa);
+
+	initial $display("==> small signed %%d");
+	initial $display(":%d:",      16'shaa);
+	initial $display(":%-d:",     16'shaa);
+	initial $display(":%+d:",     16'shaa);
+	initial $display(":%+-d:",    16'shaa);
+	initial $display(":%0d:",     16'shaa);
+	initial $display(":%-0d:",    16'shaa);
+	initial $display(":%+0d:",    16'shaa);
+	initial $display(":%+-0d:",   16'shaa);
+	initial $display(":%20d:",    16'shaa);
+	initial $display(":%-20d:",   16'shaa);
+	initial $display(":%+20d:",   16'shaa);
+	initial $display(":%+-20d:",  16'shaa);
+	initial $display(":%020d:",   16'shaa);
+	initial $display(":%-020d:",  16'shaa);
+	initial $display(":%+020d:",  16'shaa);
+	initial $display(":%+-020d:", 16'shaa);
+
+	initial $display("==> big signed %%d");
+	initial $display(":%d:",      16'shaaaa);
+	initial $display(":%-d:",     16'shaaaa);
+	initial $display(":%+d:",     16'shaaaa);
+	initial $display(":%+-d:",    16'shaaaa);
+	initial $display(":%0d:",     16'shaaaa);
+	initial $display(":%-0d:",    16'shaaaa);
+	initial $display(":%+0d:",    16'shaaaa);
+	initial $display(":%+-0d:",   16'shaaaa);
+	initial $display(":%20d:",    16'shaaaa);
+	initial $display(":%-20d:",   16'shaaaa);
+	initial $display(":%+20d:",   16'shaaaa);
+	initial $display(":%+-20d:",  16'shaaaa);
+	initial $display(":%020d:",   16'shaaaa);
+	initial $display(":%-020d:",  16'shaaaa);
+	initial $display(":%+020d:",  16'shaaaa);
+	initial $display(":%+-020d:", 16'shaaaa);
+
+	initial $display("==> small unsigned %%h");
+	initial $display(":%h:",      16'haa);
+	initial $display(":%-h:",     16'haa);
+	initial $display(":%0h:",     16'haa);
+	initial $display(":%-0h:",    16'haa);
+	initial $display(":%20h:",    16'haa);
+	initial $display(":%-20h:",   16'haa);
+	initial $display(":%020h:",   16'haa);
+	initial $display(":%-020h:",  16'haa);
+
+	initial $display("==> big unsigned %%h");
+	initial $display(":%h:",      16'haaaa);
+	initial $display(":%-h:",     16'haaaa);
+	initial $display(":%0h:",     16'haaaa);
+	initial $display(":%-0h:",    16'haaaa);
+	initial $display(":%20h:",    16'haaaa);
+	initial $display(":%-20h:",   16'haaaa);
+	initial $display(":%020h:",   16'haaaa);
+	initial $display(":%-020h:",  16'haaaa);
+
+	initial $display("==> small signed %%h");
+	initial $display(":%h:",      16'shaa);
+	initial $display(":%-h:",     16'shaa);
+	initial $display(":%0h:",     16'shaa);
+	initial $display(":%-0h:",    16'shaa);
+	initial $display(":%20h:",    16'shaa);
+	initial $display(":%-20h:",   16'shaa);
+	initial $display(":%020h:",   16'shaa);
+	initial $display(":%-020h:",  16'shaa);
+
+	initial $display("==> big signed %%h");
+	initial $display(":%h:",      16'shaaaa);
+	initial $display(":%-h:",     16'shaaaa);
+	initial $display(":%0h:",     16'shaaaa);
+	initial $display(":%-0h:",    16'shaaaa);
+	initial $display(":%20h:",    16'shaaaa);
+	initial $display(":%-20h:",   16'shaaaa);
+	initial $display(":%020h:",   16'shaaaa);
+	initial $display(":%-020h:",  16'shaaaa);
+
+	initial $display("==> small unsigned %%o");
+	initial $display(":%o:",      16'haa);
+	initial $display(":%-o:",     16'haa);
+	initial $display(":%0o:",     16'haa);
+	initial $display(":%-0o:",    16'haa);
+	initial $display(":%20o:",    16'haa);
+	initial $display(":%-20o:",   16'haa);
+	initial $display(":%020o:",   16'haa);
+	initial $display(":%-020o:",  16'haa);
+
+	initial $display("==> big unsigned %%o");
+	initial $display(":%o:",      16'haaaa);
+	initial $display(":%-o:",     16'haaaa);
+	initial $display(":%0o:",     16'haaaa);
+	initial $display(":%-0o:",    16'haaaa);
+	initial $display(":%20o:",    16'haaaa);
+	initial $display(":%-20o:",   16'haaaa);
+	initial $display(":%020o:",   16'haaaa);
+	initial $display(":%-020o:",  16'haaaa);
+
+	initial $display("==> small signed %%o");
+	initial $display(":%o:",      16'shaa);
+	initial $display(":%-o:",     16'shaa);
+	initial $display(":%0o:",     16'shaa);
+	initial $display(":%-0o:",    16'shaa);
+	initial $display(":%20o:",    16'shaa);
+	initial $display(":%-20o:",   16'shaa);
+	initial $display(":%020o:",   16'shaa);
+	initial $display(":%-020o:",  16'shaa);
+
+	initial $display("==> big signed %%o");
+	initial $display(":%o:",      16'shaaaa);
+	initial $display(":%-o:",     16'shaaaa);
+	initial $display(":%0o:",     16'shaaaa);
+	initial $display(":%-0o:",    16'shaaaa);
+	initial $display(":%20o:",    16'shaaaa);
+	initial $display(":%-20o:",   16'shaaaa);
+	initial $display(":%020o:",   16'shaaaa);
+	initial $display(":%-020o:",  16'shaaaa);
+
+	initial $display("==> small unsigned %%b");
+	initial $display(":%b:",      16'haa);
+	initial $display(":%-b:",     16'haa);
+	initial $display(":%0b:",     16'haa);
+	initial $display(":%-0b:",    16'haa);
+	initial $display(":%20b:",    16'haa);
+	initial $display(":%-20b:",   16'haa);
+	initial $display(":%020b:",   16'haa);
+	initial $display(":%-020b:",  16'haa);
+
+	initial $display("==> big unsigned %%b");
+	initial $display(":%b:",      16'haaaa);
+	initial $display(":%-b:",     16'haaaa);
+	initial $display(":%0b:",     16'haaaa);
+	initial $display(":%-0b:",    16'haaaa);
+	initial $display(":%20b:",    16'haaaa);
+	initial $display(":%-20b:",   16'haaaa);
+	initial $display(":%020b:",   16'haaaa);
+	initial $display(":%-020b:",  16'haaaa);
+
+	initial $display("==> small signed %%b");
+	initial $display(":%b:",      16'shaa);
+	initial $display(":%-b:",     16'shaa);
+	initial $display(":%0b:",     16'shaa);
+	initial $display(":%-0b:",    16'shaa);
+	initial $display(":%20b:",    16'shaa);
+	initial $display(":%-20b:",   16'shaa);
+	initial $display(":%020b:",   16'shaa);
+	initial $display(":%-020b:",  16'shaa);
+
+	initial $display("==> big signed %%b");
+	initial $display(":%b:",      16'shaaaa);
+	initial $display(":%-b:",     16'shaaaa);
+	initial $display(":%0b:",     16'shaaaa);
+	initial $display(":%-0b:",    16'shaaaa);
+	initial $display(":%20b:",    16'shaaaa);
+	initial $display(":%-20b:",   16'shaaaa);
+	initial $display(":%020b:",   16'shaaaa);
+	initial $display(":%-020b:",  16'shaaaa);
+
+	initial $display("==> time %%t");
+	initial $display(":%t:",      $time);
+	initial $display(":%-t:",     $time);
+	initial $display(":%0t:",     $time);
+	initial $display(":%-0t:",    $time);
+	initial $display(":%10t:",    $time);
+	initial $display(":%-10t:",   $time);
+	initial $display(":%015t:",   $time);
+	initial $display(":%-015t:",  $time);
+
+	initial $display("===> %%s");
+	initial $display(":%10s:", "foo");
+	initial $display(":%010s:", "foo");
+	initial $display(":%-10s:", "foo");
+	initial $display(":%-010s:", "foo");
+
+	initial $display("===> %%c");
+	initial $display(":%10c:", "foo");
+	initial $display(":%010c:", "foo");
+	initial $display(":%-10c:", "foo");
+	initial $display(":%-010c:", "foo");
+
+	initial $display("==> aliases");
+	initial $display(":%x:",      16'shaa);
+	initial $display(":%X:",      16'shaa);
+	initial $display(":%H:",      16'shaa);
+	initial $display(":%O:",      16'shaa);
+	initial $display(":%B:",      16'shaa);
+
+	initial $display("==> x/z");
+	initial $display(":%d:", 16'b1010101010101010);
+	initial $display(":%d:", 16'b101010101010101x);
+	initial $display(":%d:", 16'b101010101010101z);
+	initial $display(":%x:", 16'b1010101010101010);
+	initial $display(":%x:", 16'b101010101010101x);
+	initial $display(":%x:", 16'b101010101010101z);
+	initial $display(":%x:", 16'b101010101010xxxx);
+	initial $display(":%x:", 16'b101010101010zzzz);
+	initial $display(":%o:", 16'b1010101010101010);
+	initial $display(":%o:", 16'b101010101010101x);
+	initial $display(":%o:", 16'b101010101010101z);
+	initial $display(":%o:", 16'b1010101010101xxx);
+	initial $display(":%o:", 16'b1010101010101zzz);
+	initial $display(":%b:", 16'b1010101010101010);
+	initial $display(":%b:", 16'b101010101010101x);
+	initial $display(":%b:", 16'b101010101010101z);
+
+	initial $display("==> default base");
+	initial $displayh(16'haa);
+	initial $displayo(16'haa);
+	initial $displayb(16'haa);
+
+	initial $display("==> write/format");
+	initial $display("%d", 1, "%d", 1);
+	// this one hits a bug in iverilog:
+	// initial $display("%s", $sformatf("%d", 1, "%d", 1));
+
+	initial $display("<<<END>>>");
+
+endmodule
diff --git a/yosys/tests/fmt/roundtrip.v b/yosys/tests/fmt/roundtrip.v
new file mode 100644
index 00000000000..7b50039cd26
--- /dev/null
+++ b/yosys/tests/fmt/roundtrip.v
@@ -0,0 +1,22 @@
+module m(input clk, input `SIGN [31:0] data);
+
+	always @(posedge clk)
+		// All on a single line to avoid order effects.
+`ifdef BASE_DEC
+		$display(":%d:%-d:%+d:%+-d:%0d:%-0d:%+0d:%+-0d:%20d:%-20d:%+20d:%+-20d:%020d:%-020d:%+020d:%+-020d:",
+		         data, data, data, data, data, data, data, data, data, data, data, data, data, data, data, data);
+`endif
+`ifdef BASE_HEX
+		$display(":%h:%-h:%0h:%-0h:%20h:%-20h:%020h:%-020h:",
+		         data, data, data, data, data, data, data, data);
+`endif
+`ifdef BASE_OCT
+		$display(":%o:%-o:%0o:%-0o:%20o:%-20o:%020o:%-020o:",
+		         data, data, data, data, data, data, data, data);
+`endif
+`ifdef BASE_BIN
+		$display(":%b:%-b:%0b:%-0b:%20b:%-20b:%020b:%-020b:",
+		         data, data, data, data, data, data, data, data);
+`endif
+
+endmodule
diff --git a/yosys/tests/fmt/roundtrip_tb.v b/yosys/tests/fmt/roundtrip_tb.v
new file mode 100644
index 00000000000..988b8d8c2c0
--- /dev/null
+++ b/yosys/tests/fmt/roundtrip_tb.v
@@ -0,0 +1,13 @@
+module tb;
+	reg clk = 1'b0;
+	reg [31:0] data;
+
+	m dut(.clk(clk), .data(data));
+
+	initial begin
+		data = 32'haa;
+		#10; clk = 1; #10; clk = 0;
+		data = 32'haaaa;
+		#10; clk = 1; #10; clk = 0;
+	end
+endmodule
diff --git a/yosys/tests/fmt/run-test.sh b/yosys/tests/fmt/run-test.sh
new file mode 100644
index 00000000000..998047f830c
--- /dev/null
+++ b/yosys/tests/fmt/run-test.sh
@@ -0,0 +1,77 @@
+#!/usr/bin/env bash
+
+set -ex
+
+../../yosys -p 'read_verilog initial_display.v' | awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}' >yosys-initial_display.log
+iverilog -o iverilog-initial_display initial_display.v
+./iverilog-initial_display >iverilog-initial_display.log
+diff yosys-initial_display.log iverilog-initial_display.log
+
+test_always_display () {
+	local subtest=$1; shift
+	../../yosys -p "read_verilog $* always_display.v; proc; opt_expr -mux_bool; clean" -o yosys-always_display-${subtest}-1.v
+	../../yosys -p "read_verilog yosys-always_display-${subtest}-1.v; proc; opt_expr -mux_bool; clean" -o yosys-always_display-${subtest}-2.v
+	diff yosys-always_display-${subtest}-1.v yosys-always_display-${subtest}-2.v
+}
+
+test_always_display clk -DEVENT_CLK
+test_always_display clk_rst -DEVENT_CLK_RST
+test_always_display star -DEVENT_STAR
+
+test_always_display clk_en -DEVENT_CLK -DCOND_EN
+test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN
+test_always_display star_en -DEVENT_STAR -DCOND_EN
+
+test_roundtrip () {
+	local subtest=$1; shift
+	../../yosys -p "read_verilog $* roundtrip.v; proc; clean" -o yosys-roundtrip-${subtest}-1.v
+	../../yosys -p "read_verilog yosys-roundtrip-${subtest}-1.v; proc; clean" -o yosys-roundtrip-${subtest}-2.v
+	diff yosys-roundtrip-${subtest}-1.v yosys-roundtrip-${subtest}-2.v
+
+	iverilog $* -o iverilog-roundtrip-${subtest} roundtrip.v roundtrip_tb.v
+	./iverilog-roundtrip-${subtest} >iverilog-roundtrip-${subtest}.log
+	iverilog $* -o iverilog-roundtrip-${subtest}-1 yosys-roundtrip-${subtest}-1.v roundtrip_tb.v
+	./iverilog-roundtrip-${subtest}-1 >iverilog-roundtrip-${subtest}-1.log
+	iverilog $* -o iverilog-roundtrip-${subtest}-2 yosys-roundtrip-${subtest}-2.v roundtrip_tb.v
+	./iverilog-roundtrip-${subtest}-1 >iverilog-roundtrip-${subtest}-2.log
+	diff iverilog-roundtrip-${subtest}.log iverilog-roundtrip-${subtest}-1.log
+	diff iverilog-roundtrip-${subtest}-1.log iverilog-roundtrip-${subtest}-2.log
+}
+
+test_roundtrip dec_unsigned -DBASE_DEC -DSIGN=""
+test_roundtrip dec_signed -DBASE_DEC -DSIGN="signed"
+test_roundtrip hex_unsigned -DBASE_HEX -DSIGN=""
+test_roundtrip hex_signed -DBASE_HEX -DSIGN="signed"
+test_roundtrip oct_unsigned -DBASE_HEX -DSIGN=""
+test_roundtrip oct_signed -DBASE_HEX -DSIGN="signed"
+test_roundtrip bin_unsigned -DBASE_HEX -DSIGN=""
+test_roundtrip bin_signed -DBASE_HEX -DSIGN="signed"
+
+test_cxxrtl () {
+	local subtest=$1; shift
+
+	../../yosys -p "read_verilog ${subtest}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-${subtest}.cc"
+	${CC:-gcc} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++
+	./yosys-${subtest} 2>yosys-${subtest}.log
+	iverilog -o iverilog-${subtest} ${subtest}.v ${subtest}_tb.v
+	./iverilog-${subtest} |grep -v '\$finish called' >iverilog-${subtest}.log
+	diff iverilog-${subtest}.log yosys-${subtest}.log
+}
+
+test_cxxrtl always_full
+test_cxxrtl always_comb
+
+# Ensure Verilog backend preserves behaviour of always block with multiple $displays.
+../../yosys -p "read_verilog always_full.v; prep; clean" -o yosys-always_full-1.v
+iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v
+./iverilog-always_full-1 |grep -v '\$finish called' >iverilog-always_full-1.log
+diff iverilog-always_full.log iverilog-always_full-1.log
+
+../../yosys -p "read_verilog display_lm.v" >yosys-display_lm.log
+../../yosys -p "read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc"
+${CC:-gcc} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++
+./yosys-display_lm_cc >yosys-display_lm_cc.log
+for log in yosys-display_lm.log yosys-display_lm_cc.log; do
+	grep "^%l: \\\\bot\$" "$log"
+	grep "^%m: \\\\bot\$" "$log"
+done
diff --git a/yosys/tests/fsm/run-test.sh b/yosys/tests/fsm/run-test.sh
index fbdcbf048f0..dc60c69c4ac 100755
--- a/yosys/tests/fsm/run-test.sh
+++ b/yosys/tests/fsm/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 # run this test many times:
 # time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done'
diff --git a/yosys/tests/gen-tests-makefile.sh b/yosys/tests/gen-tests-makefile.sh
index 3df36a963b1..2b26d8c981c 100755
--- a/yosys/tests/gen-tests-makefile.sh
+++ b/yosys/tests/gen-tests-makefile.sh
@@ -16,8 +16,8 @@ generate_target() {
 # $ generate_ys_test ys_file [yosys_args]
 generate_ys_test() {
 	ys_file=$1
-	yosys_args=${2:-}
-	generate_target "$ys_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${ys_file%.*}.log $yosys_args $ys_file"
+	yosys_args_=${2:-}
+	generate_target "$ys_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${ys_file%.*}.log $yosys_args_ $ys_file"
 }
 
 # $ generate_bash_test bash_file
@@ -75,7 +75,7 @@ generate_tests() {
 	if [[ $do_sv = true ]]; then
 		for x in *.sv; do
 			if [ ! -f "${x%.sv}.ys"  ]; then
-				generate_ys_test "$x" "-p \"prep -top top; sat -enable_undef -verify -prove-asserts\" $yosys_args"
+				generate_ys_test "$x" "-p \"prep -top top; async2sync; sat -enable_undef -verify -prove-asserts\" $yosys_args"
 			fi;
 		done
 	fi;
diff --git a/yosys/tests/hana/run-test.sh b/yosys/tests/hana/run-test.sh
index 878c80b3f06..99be37f5efb 100755
--- a/yosys/tests/hana/run-test.sh
+++ b/yosys/tests/hana/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 OPTIND=1
 seed=""    # default to no seed specified
diff --git a/yosys/tests/liberty/run-test.sh b/yosys/tests/liberty/run-test.sh
index 61f19b09bc7..19ce0667d51 100755
--- a/yosys/tests/liberty/run-test.sh
+++ b/yosys/tests/liberty/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
 
 for x in *.lib; do
diff --git a/yosys/tests/lut/run-test.sh b/yosys/tests/lut/run-test.sh
index f8964f146e5..a10559cac4b 100755
--- a/yosys/tests/lut/run-test.sh
+++ b/yosys/tests/lut/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
 for x in *.v; do
   echo "Running $x.."
diff --git a/yosys/tests/memfile/run-test.sh b/yosys/tests/memfile/run-test.sh
index e43ddd09374..db0ec54ee75 100755
--- a/yosys/tests/memfile/run-test.sh
+++ b/yosys/tests/memfile/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -e
 
diff --git a/yosys/tests/memlib/generate.py b/yosys/tests/memlib/generate.py
index f40210501db..46eff6b43e3 100644
--- a/yosys/tests/memlib/generate.py
+++ b/yosys/tests/memlib/generate.py
@@ -1513,6 +1513,28 @@ def __init__(self, name, src, libs, defs, cells):
 		["block_sp_full"], defs, 
 		{"RAM_BLOCK_SP": 1, "$*": add_logic}
 	))
+	
+ROM_CASE = """
+module rom(input clk, input [2:0] addr, {attr}output reg [7:0] data);
+
+always @(posedge clk) begin
+	case (addr)
+		3'b000: data <= 8'h12;
+		3'b001: data <= 8'hAB;
+		3'b010: data <= 8'h42;
+		3'b011: data <= 8'h23;
+		3'b100: data <= 8'h66;
+		3'b101: data <= 8'hC0;
+		3'b110: data <= 8'h3F;
+		3'b111: data <= 8'h95;
+	endcase
+end
+
+endmodule
+"""
+
+TESTS.append(Test("rom_case", ROM_CASE.format(attr=""), ["block_sdp"], [], {"RAM_BLOCK_SDP" : 0}))
+TESTS.append(Test("rom_case_block", ROM_CASE.format(attr="(* rom_style = \"block\" *) "), ["block_sdp"], [], {"RAM_BLOCK_SDP" : 1}))
 
 with open("run-test.mk", "w") as mf:
     mf.write("ifneq ($(strip $(SEED)),)\n")
diff --git a/yosys/tests/memlib/memlib_9b1B.v b/yosys/tests/memlib/memlib_9b1B.v
index 55545ebd4db..9a8246c9f19 100644
--- a/yosys/tests/memlib/memlib_9b1B.v
+++ b/yosys/tests/memlib/memlib_9b1B.v
@@ -1,4 +1,14 @@
-module RAM_9b1B (
+module RAM_9b1B 
+#(
+	parameter INIT = 0,
+	parameter OPTION_INIT = "UNDEFINED",
+	parameter PORT_R_WIDTH = 9,
+	parameter PORT_W_WIDTH = 9,
+	parameter PORT_R_CLK_POL = 0,
+	parameter PORT_W_CLK_POL = 0,
+	parameter PORT_W_WR_EN_WIDTH = 1
+)
+(
 	input PORT_R_CLK,
 	input [6:0] PORT_R_ADDR,
 	output reg [PORT_R_WIDTH-1:0] PORT_R_RD_DATA,
@@ -8,14 +18,6 @@ module RAM_9b1B (
 	input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA
 );
 
-parameter INIT = 0;
-parameter OPTION_INIT = "UNDEFINED";
-parameter PORT_R_WIDTH = 9;
-parameter PORT_W_WIDTH = 9;
-parameter PORT_R_CLK_POL = 0;
-parameter PORT_W_CLK_POL = 0;
-parameter PORT_W_WR_EN_WIDTH = 1;
-
 reg [8:0] mem [0:15];
 
 integer i;
diff --git a/yosys/tests/memlib/memlib_wren.v b/yosys/tests/memlib/memlib_wren.v
index b9433d42e66..c687184bdca 100644
--- a/yosys/tests/memlib/memlib_wren.v
+++ b/yosys/tests/memlib/memlib_wren.v
@@ -1,4 +1,11 @@
-module RAM_WREN (
+module RAM_WREN #(
+	parameter ABITS=4,
+	parameter WIDTH=8,
+	parameter PORT_A_WR_EN_WIDTH=1,
+	parameter PORT_A_WR_BE_WIDTH=0,
+	parameter OPTION_BYTESIZE=WIDTH,
+	parameter WB=OPTION_BYTESIZE
+)(
 	input PORT_A_CLK,
 	input [ABITS-1:0] PORT_A_ADDR,
 	input [WIDTH-1:0] PORT_A_WR_DATA,
@@ -7,13 +14,6 @@ module RAM_WREN (
 	input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE
 );
 
-parameter ABITS=4;
-parameter WIDTH=8;
-parameter PORT_A_WR_EN_WIDTH=1;
-parameter PORT_A_WR_BE_WIDTH=0;
-parameter OPTION_BYTESIZE=WIDTH;
-parameter WB=OPTION_BYTESIZE;
-
 reg [WIDTH-1:0] mem [0:2**ABITS-1];
 
 integer i;
diff --git a/yosys/tests/memlib/run-test.sh b/yosys/tests/memlib/run-test.sh
index abe88a6cbcd..5f230a03e57 100755
--- a/yosys/tests/memlib/run-test.sh
+++ b/yosys/tests/memlib/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -eu
 
 OPTIND=1
diff --git a/yosys/tests/memories/issue00335.v b/yosys/tests/memories/issue00335.v
index f3b6e5dfe28..305339dd959 100644
--- a/yosys/tests/memories/issue00335.v
+++ b/yosys/tests/memories/issue00335.v
@@ -2,13 +2,15 @@
 // expect-rd-ports 1
 // expect-rd-clk \clk
 
-module ram2 (input clk,
+module ram2 #(
+             parameter  SIZE = 5 // Address size
+          ) (input clk,
              input             sel,
              input             we, 
              input [SIZE-1:0]  adr, 
              input [63:0]      dat_i, 
              output reg [63:0] dat_o);
-   parameter  SIZE = 5; // Address size
+   
 
    reg [63:0] mem [0:(1 << SIZE)-1];
    integer    i;
diff --git a/yosys/tests/memories/run-test.sh b/yosys/tests/memories/run-test.sh
index c65066a9c95..4f1da7ce7c2 100755
--- a/yosys/tests/memories/run-test.sh
+++ b/yosys/tests/memories/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -e
 
diff --git a/yosys/tests/opt/opt_dff_qd.ys b/yosys/tests/opt/opt_dff_qd.ys
index 7b0b4c2242a..c6232643f1f 100644
--- a/yosys/tests/opt/opt_dff_qd.ys
+++ b/yosys/tests/opt/opt_dff_qd.ys
@@ -7,7 +7,7 @@ module top(...);
 input CLK;
 input EN;
 (* init = 24'h555555 *)
-output [19:0] Q;
+output [17:0] Q;
 input SRST;
 input ARST;
 input [1:0] CLR;
@@ -23,26 +23,20 @@ $sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_V
 $dffsr #(.CLK_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.CLK(CLK), .SET(SET), .CLR(CLR), .D(Q[15:14]), .Q(Q[15:14]));
 $dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff8 (.CLK(CLK), .EN(EN), .SET(SET), .CLR(CLR), .D(Q[17:16]), .Q(Q[17:16]));
 
-$dlatch #(.EN_POLARITY(1'b1), .WIDTH(2)) ff9 (.EN(EN), .D(Q[19:18]), .Q(Q[19:18]));
-$adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff10 (.EN(EN), .ARST(ARST), .D(Q[21:20]), .Q(Q[21:20]));
-$dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff11 (.EN(EN), .SET(SET), .CLR(CLR), .D(Q[23:22]), .Q(Q[23:22]));
-
 endmodule
 
 EOT
 
 design -save orig
 
-# Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack.
-delete top/ff10 top/ff11
 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 
 design -load orig
 opt_dff -keepdc
 select -assert-count 1 t:$and
 select -assert-count 3 t:$dffe
-select -assert-count 3 t:$dlatch
-select -assert-count 3 t:$sr
+select -assert-count 2 t:$dlatch
+select -assert-count 2 t:$sr
 select -assert-none t:$and t:$dffe t:$dlatch t:$sr %% %n t:* %i
 
 design -load orig
@@ -50,7 +44,7 @@ simplemap
 opt_dff -keepdc
 select -assert-count 2 t:$_AND_
 select -assert-count 6 t:$_DFFE_??_
-select -assert-count 6 t:$_DLATCH_?_
-select -assert-count 6 t:$_SR_??_
+select -assert-count 4 t:$_DLATCH_?_
+select -assert-count 4 t:$_SR_??_
 select -assert-none t:$_AND_ t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
 
diff --git a/yosys/tests/opt/run-test.sh b/yosys/tests/opt/run-test.sh
index 2007cd6e4cc..74589dfeb57 100755
--- a/yosys/tests/opt/run-test.sh
+++ b/yosys/tests/opt/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -eu
 source ../gen-tests-makefile.sh
 run_tests --yosys-scripts
diff --git a/yosys/tests/opt_share/run-test.sh b/yosys/tests/opt_share/run-test.sh
index e0008a259b2..e80cd4214d0 100755
--- a/yosys/tests/opt_share/run-test.sh
+++ b/yosys/tests/opt_share/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 # run this test many times:
 # time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done'
diff --git a/yosys/tests/proc/clean_undef_case.ys b/yosys/tests/proc/clean_undef_case.ys
new file mode 100644
index 00000000000..c874b08c017
--- /dev/null
+++ b/yosys/tests/proc/clean_undef_case.ys
@@ -0,0 +1,37 @@
+read_rtlil <<EOT
+
+module \a
+  wire width 1 \w
+  process $p
+    switch 3'001
+      case 3'--1
+        assign \w 3'001
+      case 3'-1-
+        assign \w 3'010
+      case 3'1--
+        assign \w 3'100
+    end
+  end
+end
+
+module \b
+  wire width 1 \w
+  process $p
+    switch 3'--1
+      case 3'001
+        assign \w 3'001
+      case 3'010
+        assign \w 3'010
+      case 3'100
+        assign \w 3'100
+    end
+  end
+end
+
+EOT
+
+proc_clean  # Bug: removes the cases.
+proc_clean  # Removes the now-empty switch and its containing process.
+
+select -assert-count 1 a/p:*
+select -assert-count 1 b/p:*
diff --git a/yosys/tests/proc/proc_rom.ys b/yosys/tests/proc/proc_rom.ys
index 0ef2e2c6119..93fd5002bd8 100644
--- a/yosys/tests/proc/proc_rom.ys
+++ b/yosys/tests/proc/proc_rom.ys
@@ -186,4 +186,27 @@ design -stash preopt
 equiv_opt -assert -run prepare: dummy
 
 
+design -reset
+
+read_ilang <<EOT
+
+module \m
+  wire width 3 input 1 \a
+
+  process \p
+    switch \a
+      case 3'000
+      case 3'001
+      case 3'010
+      case 3'011
+      case 3'100
+      case 3'101
+      case 3'110
+      case 3'111
+    end
+  end
+end
+
+EOT
 
+proc_rom
diff --git a/yosys/tests/proc/run-test.sh b/yosys/tests/proc/run-test.sh
index 44ce7e6741f..e9698386e3a 100755
--- a/yosys/tests/proc/run-test.sh
+++ b/yosys/tests/proc/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
 for x in *.ys; do
   echo "Running $x.."
diff --git a/yosys/tests/realmath/run-test.sh b/yosys/tests/realmath/run-test.sh
index e1a36c694f2..833e8c3f43c 100755
--- a/yosys/tests/realmath/run-test.sh
+++ b/yosys/tests/realmath/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
 
 OPTIND=1
diff --git a/yosys/tests/rpc/run-test.sh b/yosys/tests/rpc/run-test.sh
index eeb309347cf..62404375055 100755
--- a/yosys/tests/rpc/run-test.sh
+++ b/yosys/tests/rpc/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
 for x in *.ys; do
   echo "Running $x.."
diff --git a/yosys/tests/sat/asserts.ys b/yosys/tests/sat/asserts.ys
index d8f9949257f..7df8dade38c 100644
--- a/yosys/tests/sat/asserts.ys
+++ b/yosys/tests/sat/asserts.ys
@@ -1,3 +1,3 @@
 read_verilog -sv asserts.v
-hierarchy; proc; opt
+hierarchy; proc; opt; async2sync
 sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts
diff --git a/yosys/tests/sat/asserts_seq.ys b/yosys/tests/sat/asserts_seq.ys
index e97686644c6..db94f94ea69 100644
--- a/yosys/tests/sat/asserts_seq.ys
+++ b/yosys/tests/sat/asserts_seq.ys
@@ -1,5 +1,5 @@
 read_verilog -sv asserts_seq.v
-hierarchy; proc; opt
+hierarchy; proc; opt; async2sync
 
 sat -verify  -prove-asserts -tempinduct -seq 1 test_001
 sat -falsify -prove-asserts -tempinduct -seq 1 test_002
diff --git a/yosys/tests/sat/initval.ys b/yosys/tests/sat/initval.ys
index 1436724b0d3..6fa94d52bc8 100644
--- a/yosys/tests/sat/initval.ys
+++ b/yosys/tests/sat/initval.ys
@@ -1,5 +1,5 @@
 read_verilog -sv initval.v
-proc;;
+proc; async2sync;;
 
 sat -seq 10 -prove-asserts
 
diff --git a/yosys/tests/sat/sizebits.sv b/yosys/tests/sat/sizebits.sv
index 87fa08f8924..a28f7ebb284 100644
--- a/yosys/tests/sat/sizebits.sv
+++ b/yosys/tests/sat/sizebits.sv
@@ -10,23 +10,41 @@ wire [3:0]z[7:2][2:9];
 //wire [$size(y)-1:0]y_size;
 //wire [$size(z)-1:0]z_size;
 
+assert property ($dimensions(t) == 1);
+assert property ($dimensions(x) == 1);
+assert property ($dimensions({3{x}}) == 1);
+assert property ($dimensions(y) == 2);
+assert property ($dimensions(y[2]) == 1);
+assert property ($dimensions(z) == 3);
+assert property ($dimensions(z[3]) == 2);
+assert property ($dimensions(z[3][3]) == 1);
+
+assert property ($unpacked_dimensions(t) == 0);
+assert property ($unpacked_dimensions(x) == 0);
+assert property ($unpacked_dimensions({3{x}}) == 0);
+assert property ($unpacked_dimensions(y) == 1);
+assert property ($unpacked_dimensions(y[2]) == 0);
+assert property ($unpacked_dimensions(z) == 2);
+assert property ($unpacked_dimensions(z[3]) == 1);
+assert property ($unpacked_dimensions(z[3][3]) == 0);
+
 assert property ($size(t) == 1);
 assert property ($size(x) == 4);
 assert property ($size({3{x}}) == 3*4);
 assert property ($size(y) == 6);
 assert property ($size(y, 1) == 6);
 assert property ($size(y, (1+1)) == 4);
+assert property ($size(y[2], 1) == 4);
 // This is unsupported at the moment
-//assert property ($size(y[2], 1) == 4);
 //assert property ($size(y[2][1], 1) == 1);
 
 assert property ($size(z) == 6);
 assert property ($size(z, 1) == 6);
 assert property ($size(z, 2) == 8);
 assert property ($size(z, 3) == 4);
-// This is unsupported at the moment
 assert property ($size(z[3], 1) == 8);
 assert property ($size(z[3][3], 1) == 4);
+// This is unsupported at the moment
 //assert property ($size(z[3][3][3], 1) == 1);
 // This should trigger an error if enabled (it does).
 //assert property ($size(z, 4) == 4);
@@ -90,4 +108,17 @@ assert property ($right(z, 3) == 0);
 assert property ($right(z[3]) == 9);
 assert property ($right(z[3][3]) == 0);
 assert property ($right(z[3], 2) == 0);
+
+assert property ($increment(x) == 1);
+assert property ($increment(y) == -1);
+assert property ($increment(y, 1) == -1);
+assert property ($increment(y, (1+1)) == 1);
+
+assert property ($increment(z) == 1);
+assert property ($increment(z, 1) == 1);
+assert property ($increment(z, 2) == -1);
+assert property ($increment(z, 3) == 1);
+assert property ($increment(z[3]) == -1);
+assert property ($increment(z[3][3]) == 1);
+assert property ($increment(z[3], 2) == 1);
 endmodule
diff --git a/yosys/tests/sat/sizebits.ys b/yosys/tests/sat/sizebits.ys
index 689227a4177..61e1d6f7097 100644
--- a/yosys/tests/sat/sizebits.ys
+++ b/yosys/tests/sat/sizebits.ys
@@ -1,2 +1,2 @@
 read_verilog -sv sizebits.sv
-prep; sat -verify -prove-asserts
+prep; async2sync; sat -verify -prove-asserts
diff --git a/yosys/tests/select/run-test.sh b/yosys/tests/select/run-test.sh
index 44ce7e6741f..e9698386e3a 100755
--- a/yosys/tests/select/run-test.sh
+++ b/yosys/tests/select/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
 for x in *.ys; do
   echo "Running $x.."
diff --git a/yosys/tests/share/run-test.sh b/yosys/tests/share/run-test.sh
index 1bcd8e423b8..a7b5fc4a0eb 100755
--- a/yosys/tests/share/run-test.sh
+++ b/yosys/tests/share/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 # run this test many times:
 # time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done'
diff --git a/yosys/tests/simple/.gitignore b/yosys/tests/simple/.gitignore
index 073f46157e1..5daaadbd734 100644
--- a/yosys/tests/simple/.gitignore
+++ b/yosys/tests/simple/.gitignore
@@ -1,2 +1,3 @@
 *.log
 *.out
+*.err
diff --git a/yosys/tests/simple/arrays03.sv b/yosys/tests/simple/arrays03.sv
new file mode 100644
index 00000000000..f7718c9948e
--- /dev/null
+++ b/yosys/tests/simple/arrays03.sv
@@ -0,0 +1,49 @@
+// Test multidimensional packed arrays
+
+typedef logic [0:3][7:0] reg2dim_t;
+typedef logic  [7:0] reg8_t;
+typedef reg8_t [0:3] reg2dim1_t;
+
+module pcktest1 (
+    input  logic  clk,
+    input  logic [0:3][7:0] in,
+    input  logic [1:0] ix,
+    output reg8_t out
+);
+    always_ff @(posedge clk) begin
+        out <= in[ix];
+    end
+endmodule
+
+module pcktest2 (
+    input  logic  clk,
+    input  reg8_t [0:3] in,
+    input  logic [1:0] ix,
+    output reg8_t out
+);
+    always_ff @(posedge clk) begin
+        out <= in[ix];
+    end
+endmodule
+
+module pcktest3 (
+    input  logic  clk,
+    input  reg2dim_t in,
+    input  logic [1:0] ix,
+    output reg8_t out
+);
+    always_ff @(posedge clk) begin
+        out <= in[ix];
+    end
+endmodule
+
+module pcktest4 (
+    input  logic  clk,
+    input  reg2dim1_t in,
+    input  logic [1:0] ix,
+    output reg8_t out
+);
+    always_ff @(posedge clk) begin
+        out <= in[ix];
+    end
+endmodule
diff --git a/yosys/tests/simple/memory.v b/yosys/tests/simple/memory.v
index b478d94092b..a6a280992f7 100644
--- a/yosys/tests/simple/memory.v
+++ b/yosys/tests/simple/memory.v
@@ -44,6 +44,7 @@ input [2:0] bit;
 output reg y1, y2;
 output y3, y4;
 
+(* nomem2reg *)
 reg [7:0] mem1 [3:0];
 
 (* mem2reg *)
diff --git a/yosys/tests/simple/partsel.v b/yosys/tests/simple/partsel.v
index 5e9730d6bd1..722ed7b1bd9 100644
--- a/yosys/tests/simple/partsel.v
+++ b/yosys/tests/simple/partsel.v
@@ -110,3 +110,42 @@ module partsel_test007 (
 		dout[n+1] = din[n];
 	end
 endmodule
+
+
+module partsel_test008 (
+	input [127:0] din,
+	input [3:0] idx,
+	input        [4:0] uoffset,
+	input signed [4:0] soffset,
+	output [ 7:0] dout0,
+	output [ 7:0] dout1,
+	output [ 7:0] dout2,
+	output [ 7:0] dout3,
+	output [ 3:0] dout4,
+	output [ 3:0] dout5,
+	output [ 3:0] dout6,
+	output [ 3:0] dout7,
+	output [ 3:0] dout8,
+	output [11:0] dout9,
+	output [11:0] dout10,
+	output [11:0] dout11
+);
+
+// common: block-select with offsets
+assign dout0  = din[idx*8 +uoffset +:8];
+assign dout1  = din[idx*8 -uoffset +:8];
+assign dout2  = din[idx*8 +soffset +:8];
+assign dout3  = din[idx*8 -soffset +:8];
+
+// only partial block used
+assign dout4  = din[idx*8 +uoffset +:4];
+assign dout5  = din[idx*8 -uoffset +:4];
+assign dout6  = din[idx*8 +soffset +:4];
+assign dout7  = din[idx*8 -soffset +:4];
+
+// uncommon: more than one block used
+assign dout8  = din[idx*8 +uoffset +:12];
+assign dout9  = din[idx*8 -uoffset +:12];
+assign dout10 = din[idx*8 +soffset +:12];
+assign dout11 = din[idx*8 -soffset +:12];
+endmodule
diff --git a/yosys/tests/simple/run-test.sh b/yosys/tests/simple/run-test.sh
index 47bcfd6da4b..b9e79f34a22 100755
--- a/yosys/tests/simple/run-test.sh
+++ b/yosys/tests/simple/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 OPTIND=1
 seed=""    # default to no seed specified
diff --git a/yosys/tests/simple/sign_part_assign.v b/yosys/tests/simple/sign_part_assign.v
new file mode 100644
index 00000000000..5f65ac28402
--- /dev/null
+++ b/yosys/tests/simple/sign_part_assign.v
@@ -0,0 +1,20 @@
+module test (
+	offset_i,
+	data_o,
+	data_ref_o
+);
+input wire  [ 2:0] offset_i;
+output reg  [15:0] data_o;
+output reg  [15:0] data_ref_o;
+
+always @(*) begin
+	// defaults
+	data_o = '0;
+	data_ref_o = '0;
+
+	// partial assigns
+	data_ref_o[offset_i+:4] = 4'b1111; // unsigned
+	data_o[offset_i+:4] 	= 1'sb1;   // sign extension to 4'b1111
+end
+
+endmodule
diff --git a/yosys/tests/simple_abc9/run-test.sh b/yosys/tests/simple_abc9/run-test.sh
index 4a5bf01a33c..b75e54dd3fe 100755
--- a/yosys/tests/simple_abc9/run-test.sh
+++ b/yosys/tests/simple_abc9/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 OPTIND=1
 seed=""    # default to no seed specified
diff --git a/yosys/tests/smv/run-single.sh b/yosys/tests/smv/run-single.sh
index a261f4ea653..a0a6eba0af2 100644
--- a/yosys/tests/smv/run-single.sh
+++ b/yosys/tests/smv/run-single.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 cat > $1.tpl <<EOT
 %module main
diff --git a/yosys/tests/smv/run-test.sh b/yosys/tests/smv/run-test.sh
index 74a54486d95..c8264ac8a7e 100755
--- a/yosys/tests/smv/run-test.sh
+++ b/yosys/tests/smv/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -ex
 
diff --git a/yosys/tests/sva/runtest.sh b/yosys/tests/sva/runtest.sh
index 2ecc9780c5d..7692a5f9ad9 100644
--- a/yosys/tests/sva/runtest.sh
+++ b/yosys/tests/sva/runtest.sh
@@ -1,6 +1,6 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
-set -ex
+set -e
 
 prefix=${1%.ok}
 prefix=${prefix%.sv}
@@ -58,16 +58,33 @@ generate_sby() {
 }
 
 if [ -f $prefix.ys ]; then
+	set -x
 	$PWD/../../yosys -q -e "Assert .* failed." -s $prefix.ys
 elif [ -f $prefix.sv ]; then
 	generate_sby pass > ${prefix}_pass.sby
 	generate_sby fail > ${prefix}_fail.sby
-	sby --yosys $PWD/../../yosys -f ${prefix}_pass.sby
-	sby --yosys $PWD/../../yosys -f ${prefix}_fail.sby
+
+	# Check that SBY is up to date enough for this yosys version
+	if sby --help | grep -q -e '--status'; then
+		set -x
+		sby --yosys $PWD/../../yosys -f ${prefix}_pass.sby
+		sby --yosys $PWD/../../yosys -f ${prefix}_fail.sby
+	else
+		echo "sva test '${prefix}' requires an up to date SBY, skipping"
+	fi
 else
 	generate_sby pass > ${prefix}.sby
-	sby --yosys $PWD/../../yosys -f ${prefix}.sby
+
+	# Check that SBY is up to date enough for this yosys version
+	if sby --help | grep -q -e '--status'; then
+		set -x
+		sby --yosys $PWD/../../yosys -f ${prefix}.sby
+	else
+		echo "sva test '${prefix}' requires an up to date SBY, skipping"
+	fi
 fi
 
+{ set +x; } &>/dev/null
+
 touch $prefix.ok
 
diff --git a/yosys/tests/sva/sva_value_change_changed.sv b/yosys/tests/sva/sva_value_change_changed.sv
index 8f3a05a2f2e..3ce2078500c 100644
--- a/yosys/tests/sva/sva_value_change_changed.sv
+++ b/yosys/tests/sva/sva_value_change_changed.sv
@@ -8,9 +8,11 @@ module top (
 		$changed(b)
 	);
 
+	wire x = 'x;
+
 `ifndef FAIL
 	assume property (
-		b !== 'x ##1 $changed(b)
+		b !== x ##1 $changed(b)
 	);
 `endif
 
diff --git a/yosys/tests/svinterfaces/run_simple.sh b/yosys/tests/svinterfaces/run_simple.sh
index bce9944439c..5bf04437337 100755
--- a/yosys/tests/svinterfaces/run_simple.sh
+++ b/yosys/tests/svinterfaces/run_simple.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 # Run a simple test with a .ys file
 
diff --git a/yosys/tests/svinterfaces/runone.sh b/yosys/tests/svinterfaces/runone.sh
index 54cf5f2ec37..2d6e0463d43 100755
--- a/yosys/tests/svinterfaces/runone.sh
+++ b/yosys/tests/svinterfaces/runone.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 
 TESTNAME=$1
diff --git a/yosys/tests/svtypes/enum_simple.ys b/yosys/tests/svtypes/enum_simple.ys
index 79981657b6f..36922f5e09f 100644
--- a/yosys/tests/svtypes/enum_simple.ys
+++ b/yosys/tests/svtypes/enum_simple.ys
@@ -1,5 +1,5 @@
 
 read_verilog -sv enum_simple.sv
-hierarchy; proc; opt
+hierarchy; proc; opt; async2sync
 sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts -show-all
 
diff --git a/yosys/tests/svtypes/multirange_array.sv b/yosys/tests/svtypes/multirange_array.sv
index be0d3dfc2c0..29e4559abae 100644
--- a/yosys/tests/svtypes/multirange_array.sv
+++ b/yosys/tests/svtypes/multirange_array.sv
@@ -8,9 +8,21 @@ module top;
 	logic a [3];
 	logic b [3][5];
 	logic c [3][5][7];
+	logic [2:0] d;
+	logic [2:0][4:0] e;
+	logic [2:0][4:0][6:0] f;
+	logic [2:0] g [3];
+	logic [2:0][4:0] h [3][5];
+	logic [2:0][4:0][6:0] i [3][5][7];
 
 	`STATIC_ASSERT($bits(a) == 3);
 	`STATIC_ASSERT($bits(b) == 15);
 	`STATIC_ASSERT($bits(c) == 105);
+	`STATIC_ASSERT($bits(d) == 3);
+	`STATIC_ASSERT($bits(e) == 15);
+	`STATIC_ASSERT($bits(f) == 105);
+	`STATIC_ASSERT($bits(g) == 9);
+	`STATIC_ASSERT($bits(h) == 225);
+	`STATIC_ASSERT($bits(i) == 11025);
 
 endmodule
diff --git a/yosys/tests/svtypes/struct_array.sv b/yosys/tests/svtypes/struct_array.sv
index bedc05b6f26..e07c9b2321e 100644
--- a/yosys/tests/svtypes/struct_array.sv
+++ b/yosys/tests/svtypes/struct_array.sv
@@ -23,6 +23,29 @@ module top;
 	always_comb assert(s.b[23:16]===8'hxx);
 	always_comb assert(s.b[19:12]===8'hxf);
 
+	// Same as s, but defining dimensions in stages with typedef
+	typedef bit [7:0] bit8_t;
+	struct packed {
+		bit8_t [5:0] a;		// 6 element packed array of bytes
+		bit [15:0] b;		// filler for non-zero offset
+	} s_s;
+
+	initial begin
+		s_s = '0;
+
+		s_s.a[2:1] = 16'h1234;
+		s_s.a[5] = 8'h42;
+		s_s.a[-1] = '0;
+
+		s_s.b = '1;
+		s_s.b[1:0] = '0;
+	end
+
+	always_comb assert(s_s==64'h4200_0012_3400_FFFC);
+	always_comb assert(s_s.a[0][3:-4]===8'h0x);
+	always_comb assert(s_s.b[23:16]===8'hxx);
+	always_comb assert(s_s.b[19:12]===8'hxf);
+
 	struct packed {
 		bit [7:0] [7:0] a;	// 8 element packed array of bytes
 		bit [15:0] b;		// filler for non-zero offset
@@ -125,6 +148,28 @@ module top;
 
 	always_comb assert(s3_lbl==80'hFC00_4200_0012_3400_FFFC);
 
+	// Same as s3_lbl, but defining dimensions in stages with typedef
+	typedef bit [0:3] bit3l_t;
+	struct packed {
+		bit3l_t [0:7] [1:0] a;
+		bit [0:15] b;		// filler for non-zero offset
+	} s3_lbl_s;
+
+	initial begin
+		s3_lbl_s = '0;
+
+		s3_lbl_s.a[5:6] = 16'h1234;
+		s3_lbl_s.a[2] = 8'h42;
+
+		s3_lbl_s.a[0] = '1;
+		s3_lbl_s.a[0][0][2:3] = '0;
+
+		s3_lbl_s.b = '1;
+		s3_lbl_s.b[14:15] = '0;
+	end
+
+	always_comb assert(s3_lbl_s==80'hFC00_4200_0012_3400_FFFC);
+
 	struct packed {
 		bit [0:7] [0:1] [3:0] a;
 		bit [0:15] b;		// filler for non-zero offset
diff --git a/yosys/tests/svtypes/struct_dynamic_range.ys b/yosys/tests/svtypes/struct_dynamic_range.ys
index 9606e73840c..c090b6e7c9b 100644
--- a/yosys/tests/svtypes/struct_dynamic_range.ys
+++ b/yosys/tests/svtypes/struct_dynamic_range.ys
@@ -4,4 +4,5 @@ select -assert-count 2 t:$shift
 select -assert-count 2 t:$shiftx
 prep -top top
 flatten
+async2sync
 sat -enable_undef -verify -prove-asserts
diff --git a/yosys/tests/svtypes/struct_sizebits.sv b/yosys/tests/svtypes/struct_sizebits.sv
index 092d9ecef63..aceec84b31e 100644
--- a/yosys/tests/svtypes/struct_sizebits.sv
+++ b/yosys/tests/svtypes/struct_sizebits.sv
@@ -25,6 +25,18 @@ struct packed {
 //wire [$bits({s.x, s.x})-1:0]xx_bits;
 
 always_comb begin
+	assert ($dimensions(s) == 1);
+	assert ($dimensions(s.x) == 1);
+`ifndef VERIFIC
+	assert ($dimensions(s.t) == 1);
+	assert ($dimensions({3{s.x}}) == 1);
+`endif
+	assert ($dimensions(s.sy.y) == 2);
+	assert ($dimensions(s.sy.y[2]) == 1);
+	assert ($dimensions(s.sz.z) == 3);
+	assert ($dimensions(s.sz.z[3]) == 2);
+	assert ($dimensions(s.sz.z[3][3]) == 1);
+
 	assert ($size(s) == $size(s.t) + $size(s.x) + $size(s.sy) + $size(s.sz));
 	assert ($size(s) == 1 + 4 + 6*4 + 6*8*4);
 
@@ -107,6 +119,19 @@ always_comb begin
 	assert ($right(s.sz.z[3]) == 9);
 	assert ($right(s.sz.z[3][3]) == 4);
 	assert ($right(s.sz.z[3], 2) == 4);
+
+	assert ($increment(s.x) == 1);
+	assert ($increment(s.sy.y) == -1);
+	assert ($increment(s.sy.y, 1) == -1);
+	assert ($increment(s.sy.y, (1+1)) == 1);
+
+	assert ($increment(s.sz.z) == 1);
+	assert ($increment(s.sz.z, 1) == 1);
+	assert ($increment(s.sz.z, 2) == -1);
+	assert ($increment(s.sz.z, 3) == -1);
+	assert ($increment(s.sz.z[3]) == -1);
+	assert ($increment(s.sz.z[3][3]) == -1);
+	assert ($increment(s.sz.z[3], 2) == -1);
 end
 
 endmodule
diff --git a/yosys/tests/svtypes/typedef_initial_and_assign.ys b/yosys/tests/svtypes/typedef_initial_and_assign.ys
index de456bb82bd..e778a49bb01 100644
--- a/yosys/tests/svtypes/typedef_initial_and_assign.ys
+++ b/yosys/tests/svtypes/typedef_initial_and_assign.ys
@@ -9,6 +9,6 @@ logger -expect warning "reg '\\var_18' is assigned in a continuous assignment" 1
 logger -expect warning "reg '\\var_19' is assigned in a continuous assignment" 1
 
 read_verilog -sv typedef_initial_and_assign.sv
-hierarchy; proc; opt
+hierarchy; proc; opt; async2sync
 select -module top
-sat -verify -seq 1 -tempinduct -prove-asserts -show-all
\ No newline at end of file
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/yosys/tests/svtypes/typedef_scopes.sv b/yosys/tests/svtypes/typedef_scopes.sv
index 5ac9a4664c4..cd7b7953e03 100644
--- a/yosys/tests/svtypes/typedef_scopes.sv
+++ b/yosys/tests/svtypes/typedef_scopes.sv
@@ -45,12 +45,12 @@ module top;
 		localparam W = 10;
 		typedef T U;
 		typedef logic [W-1:0] V;
-		struct packed {
+		typedef struct packed {
 			logic [W-1:0] x; // width 10
 			U y; // width 5
 			V z; // width 10
-		} shadow;
-		// This currently only works as long as long as shadow is not typedef'ed
+		} shadow_t;
+		shadow_t shadow;
 		always @(*) assert($bits(shadow.x) == 10);
 		always @(*) assert($bits(shadow.y) == 5);
 		always @(*) assert($bits(shadow.z) == 10);
diff --git a/yosys/tests/svtypes/typedef_struct_port.ys b/yosys/tests/svtypes/typedef_struct_port.ys
index 5b75c310551..dd0775b9ff9 100644
--- a/yosys/tests/svtypes/typedef_struct_port.ys
+++ b/yosys/tests/svtypes/typedef_struct_port.ys
@@ -1,5 +1,5 @@
 read_verilog -sv typedef_struct_port.sv
-hierarchy; proc; opt
+hierarchy; proc; opt; async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
 select -module test_parser
diff --git a/yosys/tests/techmap/booth.ys b/yosys/tests/techmap/booth.ys
new file mode 100644
index 00000000000..55dfdb8e9cd
--- /dev/null
+++ b/yosys/tests/techmap/booth.ys
@@ -0,0 +1,15 @@
+read_verilog <<EOF
+module test(clk, a, b, y);
+	input wire clk;
+	input wire [9:0] a;
+	input wire [6:0] b;
+	output wire [20:0] y;
+
+	assign y = a * b;
+endmodule
+EOF
+booth
+sat -verify -set a 0 -set b 0 -prove y 0
+design -reset
+
+test_cell -s 1694091355 -n 100 -script booth_map_script.ys_ $mul
\ No newline at end of file
diff --git a/yosys/tests/techmap/booth_map_script.ys_ b/yosys/tests/techmap/booth_map_script.ys_
new file mode 100644
index 00000000000..d2fe5d3f0a3
--- /dev/null
+++ b/yosys/tests/techmap/booth_map_script.ys_
@@ -0,0 +1 @@
+booth
diff --git a/yosys/tests/techmap/cellmatch.ys b/yosys/tests/techmap/cellmatch.ys
new file mode 100644
index 00000000000..bea2f598d94
--- /dev/null
+++ b/yosys/tests/techmap/cellmatch.ys
@@ -0,0 +1,79 @@
+read_verilog <<EOF
+module bufgate(A, Y);
+	input wire A;
+	output wire Y = A;
+endmodule
+
+module reducegate(A, B, C, X, Y);
+	input wire A;
+	input wire B;
+	input wire C;
+	output wire X = &{A, B, C};
+	output wire Y = |{A, B, C};
+endmodule
+
+module fagate(A, B, C, X, Y);
+	input wire A;
+	input wire B;
+	input wire C;
+	wire t1 = A ^ B;
+	wire t2 = A & B;
+	wire t3 = C & t1;
+	output wire X = t1 ^ C;
+	output wire Y = t2 | t3;
+endmodule
+EOF
+design -stash gatelib
+
+read_verilog <<EOF
+module ripple_carry(A, B, Y);
+	parameter WIDTH = 4;
+
+	input wire [WIDTH-1:0] A;
+	input wire [WIDTH-1:0] B;
+	output wire [WIDTH-1:0] Y;
+
+	wire [WIDTH:0] carry;
+	assign carry[0] = 0;
+
+	generate
+		genvar i;
+
+		for (i = 0; i < WIDTH; i = i + 1) begin
+			FA fa(
+				.A(A[i]),
+				.B(B[i]), .Y(Y[i]),
+				.CI(carry[i]), .CO(carry[i + 1]),
+			);
+		end
+	endgenerate
+endmodule
+
+(* gate *)
+module FA(A, B, CI, CO, Y);
+	input wire A, B, CI;
+	output wire CO, Y;
+	assign {CO, Y} = A + B + CI;
+endmodule
+EOF
+
+prep
+cellmatch -lib gatelib FA A:gate
+
+design -save gold
+techmap -map %$cellmatch
+design -save gate
+
+select -assert-none ripple_carry/t:FA
+
+design -reset
+design -copy-from gold -as gold ripple_carry
+design -copy-from gate -as gate ripple_carry
+opt_clean
+equiv_make gold gate equiv
+hierarchy -top equiv
+flatten
+opt_clean
+equiv_induct equiv
+equiv_status -assert
+
diff --git a/yosys/tests/techmap/dfflibmap.ys b/yosys/tests/techmap/dfflibmap.ys
index b0a7d6b7e20..e8b12545670 100644
--- a/yosys/tests/techmap/dfflibmap.ys
+++ b/yosys/tests/techmap/dfflibmap.ys
@@ -58,3 +58,10 @@ select -assert-count 4 t:$_NOT_
 select -assert-count 1 t:dffn
 select -assert-count 4 t:dffsr
 select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i
+
+design -load orig
+dfflibmap -liberty dfflibmap.lib -dont_use *ffn
+clean
+
+select -assert-count 0 t:dffn
+select -assert-count 5 t:dffsr
diff --git a/yosys/tests/techmap/kogge-stone.ys b/yosys/tests/techmap/kogge-stone.ys
new file mode 100644
index 00000000000..fc3637f10b0
--- /dev/null
+++ b/yosys/tests/techmap/kogge-stone.ys
@@ -0,0 +1 @@
+test_cell -s 1711533949 -n 10 -map +/techmap.v -map +/choices/kogge-stone.v $lcu
diff --git a/yosys/tests/techmap/mem_simple_4x1_runtest.sh b/yosys/tests/techmap/mem_simple_4x1_runtest.sh
index 5b5838b9da4..d7738aafbc2 100644
--- a/yosys/tests/techmap/mem_simple_4x1_runtest.sh
+++ b/yosys/tests/techmap/mem_simple_4x1_runtest.sh
@@ -1,3 +1,3 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 exec ../tools/autotest.sh -G -j $@ -p 'proc; opt; memory -nomap; techmap -map ../mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
diff --git a/yosys/tests/techmap/techmap_chtype.ys b/yosys/tests/techmap/techmap_chtype.ys
new file mode 100644
index 00000000000..7c339842013
--- /dev/null
+++ b/yosys/tests/techmap/techmap_chtype.ys
@@ -0,0 +1,33 @@
+read_verilog <<EOT
+
+(* techmap_celltype="foo" *)
+module _80_lcu_primitive(P, G, CI, CO);
+	parameter WIDTH = 10;
+
+	(* force_downto *)
+	input wire [WIDTH-1:0] P;
+	(* force_downto *)
+	input wire [WIDTH-1:0] G;
+	input wire CI;
+	(* force_downto *)
+	output wire [WIDTH-1:0] CO;
+
+	(* techmap_chtype=$sformatf("LCU_%0d", WIDTH) *)
+	_TECHMAP_PLACEHOLDER_ #(.WIDTH(WIDTH)) _TECHMAP_REPLACE_(.P(P), .G(G), .CI(CI), .CO(CO));
+endmodule
+
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+module top(input [3:0] pi, input [3:0] gi, input ci, output [3:0] co);
+foo #(.WIDTH(8)) suuuub(pi, gi, ci, co);
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+opt
+techmap -map %techmap
+
+select -assert-count 1 t:LCU_8
diff --git a/yosys/tests/unit/Makefile b/yosys/tests/unit/Makefile
index 9f1e5c99ec9..b4a752f8f47 100644
--- a/yosys/tests/unit/Makefile
+++ b/yosys/tests/unit/Makefile
@@ -15,7 +15,7 @@ TESTS := $(addprefix $(BINTEST)/, $(basename $(ALLTESTFILE:%Test.cc=%Test.o)))
 all: prepare $(TESTS) run-tests
 
 $(BINTEST)/%: $(OBJTEST)/%.o
-	$(CXX) -L$(ROOTPATH) $(RPATH)=$(ROOTPATH) -o $@ $^ $(LDLIBS) \
+	$(CXX) -L$(ROOTPATH) $(RPATH)=$(ROOTPATH) -o $@ $^ $(LIBS) \
 		$(GTESTFLAG) $(EXTRAFLAGS)
 
 $(OBJTEST)/%.o: $(basename $(subst $(OBJTEST),.,%)).cc
diff --git a/yosys/tests/various/async.sh b/yosys/tests/various/async.sh
index e83935d02e5..9d956c1cd9d 100644
--- a/yosys/tests/various/async.sh
+++ b/yosys/tests/various/async.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -ex
 ../../yosys -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v
 ../../yosys -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v
diff --git a/yosys/tests/various/box_derive.ys b/yosys/tests/various/box_derive.ys
new file mode 100644
index 00000000000..f02e133603d
--- /dev/null
+++ b/yosys/tests/various/box_derive.ys
@@ -0,0 +1,53 @@
+read_verilog <<EOF
+(* whitebox *)
+(* final_name=$sformatf("aa%d", X) *)
+module aa(input wire d, output wire q);
+  parameter [1:0] X = 0;
+  assign q = X[d];
+endmodule
+
+(* whitebox *)
+(* final_name=$sformatf("bb%d", X) *)
+module bb(input wire d, output wire q);
+  parameter [1:0] X = 0;
+  assign q = X[~d];
+endmodule
+
+(* whitebox *)
+(* final_name=$sformatf("cc%d", X) *)
+module cc(input wire d, output wire q);
+  parameter [1:0] X = 0;
+  assign q = ~X[d];
+endmodule
+
+module top;
+	wire d, q1, q2, q3, q3, q4, q5, q6;
+
+	aa #(.X(1)) aa1(.d(d), .q(q1));
+	aa #(.X(2)) aa2(.d(d), .q(q2));
+
+	bb #(.X(1)) bb1(.d(d), .q(q3));
+	bb #(.X(3)) bb2(.d(d), .q(q4));
+
+	cc #(.X(1)) cc1(.d(d), .q(q5));
+	cc #(.X(1)) cc2(.d(d), .q(q6));
+endmodule
+EOF
+
+box_derive -naming_attr final_name top
+
+select -assert-mod-count 1 =aa1
+select -assert-mod-count 1 =aa2
+select -assert-mod-count 0 =aa3
+
+select -assert-mod-count 1 =bb1
+select -assert-mod-count 0 =bb2
+select -assert-mod-count 1 =bb3
+
+select -assert-mod-count 1 =cc1
+select -assert-mod-count 0 =cc2
+select -assert-mod-count 0 =cc3
+
+# we are expecting the original aa, bb, cc modules
+# and 5 specializations generated by box_derive
+select -assert-mod-count 8 =A:whitebox
diff --git a/yosys/tests/various/bug4082.ys b/yosys/tests/various/bug4082.ys
new file mode 100644
index 00000000000..272be2fad27
--- /dev/null
+++ b/yosys/tests/various/bug4082.ys
@@ -0,0 +1,8 @@
+read_verilog <<EOF
+module top;
+  wire a;
+  wire b;
+  assign a = b;
+endmodule
+EOF
+delete w:a
diff --git a/yosys/tests/various/celledges_shift.ys b/yosys/tests/various/celledges_shift.ys
new file mode 100644
index 00000000000..753c8641e58
--- /dev/null
+++ b/yosys/tests/various/celledges_shift.ys
@@ -0,0 +1 @@
+test_cell -s 1705659041 -n 100 -edges $shift $shiftx $shl $shr $sshl $sshr
diff --git a/yosys/tests/various/check.ys b/yosys/tests/various/check.ys
new file mode 100644
index 00000000000..41b9960911f
--- /dev/null
+++ b/yosys/tests/various/check.ys
@@ -0,0 +1,43 @@
+design -reset
+read -vlog2k <<EOF
+module top(input clk, input a, input b, output [9:0] x);
+	wire [9:0] ripple;
+	reg [9:0] prev_ripple = 9'b0;
+
+	always @(posedge clk) prev_ripple <= ripple;
+	assign ripple = {ripple[8:0], a} ^ prev_ripple; // only cyclic at the coarse-grain level
+	assign x = ripple[9] + b;
+endmodule
+EOF
+hierarchy -top top
+prep
+check -assert
+
+design -reset
+read -vlog2k <<EOF
+module top(clk, y, sideread_addr, sideread_data);
+	input wire clk;
+
+	reg [7:0] mem [255:0];
+	reg [8:0] i;
+	initial begin
+		for (i = 0; i < 256; i = i + 1)
+			mem[i] = i * 371;
+	end
+
+	output reg [7:0] y = 1;
+	always @(posedge clk)
+		y <= mem[y];
+
+	input wire [7:0] sideread_addr;
+	output wire [7:0] sideread_data;
+	assign sideread_data = mem[sideread_addr];
+endmodule
+EOF
+hierarchy -top top
+prep -rdff
+select -assert-count 1 t:$mem_v2
+check -assert
+memory_unpack
+select -assert-count 2 t:$memrd_v2
+check -assert
diff --git a/yosys/tests/various/check_2.ys b/yosys/tests/various/check_2.ys
new file mode 100644
index 00000000000..b63ea683734
--- /dev/null
+++ b/yosys/tests/various/check_2.ys
@@ -0,0 +1,17 @@
+# just so slightly adjust the example from check.ys to induce a loop
+design -reset
+read -vlog2k <<EOF
+module top(input clk, input a, input b, output [9:0] x);
+	wire [9:0] ripple;
+	reg [9:0] prev_ripple = 9'b0;
+
+	always @(posedge clk) prev_ripple <= ripple;
+	assign ripple = {ripple[8:1], a, ripple[0]} ^ prev_ripple;
+	assign x = ripple[9] + b;
+endmodule
+EOF
+hierarchy -top top
+prep
+logger -expect warning "found logic loop in module top:" 1
+logger -expect error "Found 1 problems in 'check -assert'" 1
+check -assert
diff --git a/yosys/tests/various/check_3.ys b/yosys/tests/various/check_3.ys
new file mode 100644
index 00000000000..14915ab8d4d
--- /dev/null
+++ b/yosys/tests/various/check_3.ys
@@ -0,0 +1,20 @@
+# loop involving asynchronous memory ports
+design -reset
+read -vlog2k <<EOF
+module pingpong(input wire [1:0] x, output wire [3:0] y1, output wire [3:0] y2);
+	reg [3:0] mem [15:0];
+	reg [5:0] i;
+	initial begin
+		for (i = 0; i < 16; i = i + 1)
+			mem[i] = i * 371;
+	end
+
+	assign y1 = mem[{y2[3:2], x}];
+	assign y2 = mem[y1];
+endmodule
+EOF
+hierarchy -top pingpong
+prep
+logger -nowarn "found logic loop in module pingpong:"
+logger -expect error "Found [0-9]+ problems in 'check -assert'" 1
+check -assert
diff --git a/yosys/tests/various/check_4.ys b/yosys/tests/various/check_4.ys
new file mode 100644
index 00000000000..010cd01fd53
--- /dev/null
+++ b/yosys/tests/various/check_4.ys
@@ -0,0 +1,29 @@
+# loop involving the asynchronous reset on a memory port
+design -reset
+read -vlog2k <<EOF
+module top(input wire clk, input wire [3:0] addr, output reg [3:0] data);
+	reg [3:0] mem [15:0];
+	reg [5:0] i;
+	initial begin
+		for (i = 0; i < 16; i = i + 1)
+			mem[i] = i * 371;
+	end
+
+	wire arst = !data[0];
+
+	always @(posedge arst, posedge clk) begin
+		if (arst)		
+			data <= 4'hx;
+		else
+			data <= mem[addr];
+	end
+endmodule
+EOF
+hierarchy -top top
+proc
+opt -keepdc
+memory_dff
+opt_clean
+logger -nowarn "found logic loop in module pingpong:"
+logger -expect error "Found [0-9]+ problems in 'check -assert'" 1
+check -assert
diff --git a/yosys/tests/various/chformal_check.ys b/yosys/tests/various/chformal_check.ys
new file mode 100644
index 00000000000..951543fa5e5
--- /dev/null
+++ b/yosys/tests/various/chformal_check.ys
@@ -0,0 +1,68 @@
+read_verilog -formal <<EOT
+
+module top(input clk, a, en);
+    wire a_q = '0;
+    wire en_q = '0;
+
+    always @(posedge clk) begin
+        a_q <= a;
+        en_q <= en;
+    end
+
+    always @(posedge clk)
+        if (en_q)
+            assert(a_q);
+endmodule
+EOT
+
+prep
+
+design -save prep
+
+select -assert-count 1 t:$check r:FLAVOR=assert %i
+
+chformal -assert2assume
+
+select -assert-count 1 t:$check r:FLAVOR=assume %i
+
+chformal -assume2assert
+
+select -assert-count 1 t:$check r:FLAVOR=assert %i
+
+async2sync
+
+chformal -lower
+select -assert-count 1 t:$assert
+
+design -load prep
+
+chformal -assert2assume
+async2sync
+chformal -lower
+chformal -assume -early
+
+rename -enumerate -pattern assume_% t:$assume
+expose -evert t:$assume
+
+design -save gold
+
+design -load prep
+
+chformal -assert2assume
+chformal -assume -early
+async2sync
+chformal -lower
+
+rename -enumerate -pattern assume_% t:$assume
+expose -evert t:$assume
+
+design -save gate
+
+design -reset
+
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+
+miter -equiv -flatten -make_assert gold gate miter
+
+sat -verify -prove-asserts -tempinduct miter
diff --git a/yosys/tests/various/chformal_coverenable.ys b/yosys/tests/various/chformal_coverenable.ys
index 52b3ee6bf60..705322df9c0 100644
--- a/yosys/tests/various/chformal_coverenable.ys
+++ b/yosys/tests/various/chformal_coverenable.ys
@@ -2,10 +2,10 @@ read_verilog -formal <<EOT
 module top(input a, b, c, d);
 
     always @* begin
-        if (a) assert (b == c);
-        if (!a) assert (b != c);
-        if (b) assume (c);
-        if (c) cover (d);
+        if (a) c0: assert (b == c);
+        if (!a) c1: assert (b != c);
+        if (b) c2: assume (c);
+        if (c) c3: cover (d);
     end
 
 endmodule
@@ -13,6 +13,10 @@ EOT
 
 prep -top top
 
+design -save prep
+
+async2sync
+
 select -assert-count 1 t:$cover
 
 chformal -cover -coverenable
@@ -23,3 +27,36 @@ select -assert-count 4 t:$cover
 
 chformal -assume -coverenable
 select -assert-count 5 t:$cover
+
+autoname */t:$cover
+expose -evert */c? */c?_EN_$cover_*
+
+design -save a2s_first
+
+design -load prep
+select -assert-count 1 r:FLAVOR=cover
+
+chformal -cover -coverenable
+select -assert-count 2 r:FLAVOR=cover
+
+chformal -assert -coverenable
+select -assert-count 4 r:FLAVOR=cover
+
+chformal -assume -coverenable
+select -assert-count 5 r:FLAVOR=cover
+
+async2sync
+
+autoname */t:$cover
+expose -evert */c? */c?_EN_$cover_*
+
+design -save a2s_last
+
+design -reset
+
+design -copy-from a2s_first -as gold top
+design -copy-from a2s_last -as gate top
+
+miter -equiv -flatten -make_assert gold gate miter
+
+sat -verify -prove-asserts -tempinduct miter
diff --git a/yosys/tests/various/chparam.sh b/yosys/tests/various/chparam.sh
index 9bb8d81db6a..0c237112e09 100644
--- a/yosys/tests/various/chparam.sh
+++ b/yosys/tests/various/chparam.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 trap 'echo "ERROR in chparam.sh" >&2; exit 1' ERR
 
@@ -37,14 +37,17 @@ EOT
 
 if ../../yosys -q -p 'verific -sv chparam1.sv'; then
 	../../yosys -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
+			-p 'async2sync' \
 			-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
 			-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
 
 	../../yosys -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
+			-p 'async2sync' \
 			-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
 			-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
 fi
 ../../yosys -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
+		-p 'async2sync' \
 		-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
 		-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
 
diff --git a/yosys/tests/various/clk2fflogic_effects.sh b/yosys/tests/various/clk2fflogic_effects.sh
new file mode 100755
index 00000000000..0d133ffddbb
--- /dev/null
+++ b/yosys/tests/various/clk2fflogic_effects.sh
@@ -0,0 +1,35 @@
+#!/usr/bin/env bash
+set -e
+
+# TODO: when sim gets native $check support, remove the -DNO_ASSERT here
+echo Running yosys sim
+../../yosys -q -p "
+read_verilog -formal -DNO_ASSERT clk2fflogic_effects.sv
+hierarchy -top top; proc;;
+
+tee -q -o clk2fflogic_effects.sim.log sim -q -n 32
+"
+echo Running yosys clk2fflogic sim
+../../yosys -q -p "
+read_verilog -formal clk2fflogic_effects.sv
+hierarchy -top top; proc;;
+clk2fflogic;;
+
+logger -nowarn ^Assertion
+tee -q -o clk2fflogic_effects.clk2fflogic.log sim -q -n 32
+"
+
+echo Running iverilog sim
+iverilog -g2012 -DNO_ASSERT -o clk2fflogic_effects.iv.out clk2fflogic_effects.sv
+
+
+./clk2fflogic_effects.iv.out > clk2fflogic_effects.iv.log
+
+gawk '/([0-9]+):/{T=$1;print};/^Failed/{print T,$0}' clk2fflogic_effects.iv.log | sort > clk2fflogic_effects.iv.sorted.log
+gawk '/([0-9]+):/{T=$1;print};/^Failed/{print T,$0}' clk2fflogic_effects.sim.log | sort > clk2fflogic_effects.sim.sorted.log
+gawk '/([0-9]+):/{T=$1;print};/^Failed/{print T,$0}' clk2fflogic_effects.clk2fflogic.log | sort > clk2fflogic_effects.clk2fflogic.sorted.log
+
+echo Comparing iverilog sim vs yosys sim
+cmp clk2fflogic_effects.iv.sorted.log clk2fflogic_effects.sim.sorted.log
+echo Comparing iverilog sim vs yosys clk2fflogic sim
+cmp clk2fflogic_effects.iv.sorted.log clk2fflogic_effects.clk2fflogic.sorted.log
diff --git a/yosys/tests/various/clk2fflogic_effects.sv b/yosys/tests/various/clk2fflogic_effects.sv
new file mode 100644
index 00000000000..b38aba3c9bb
--- /dev/null
+++ b/yosys/tests/various/clk2fflogic_effects.sv
@@ -0,0 +1,101 @@
+module top;
+
+(* gclk *)
+reg gclk;
+
+reg clk = 0;
+always @(posedge gclk)
+    clk <= !clk;
+
+reg [5:0] counter = 0;
+
+reg eff_0_trg = '0;
+reg eff_0_en = '0;
+
+reg eff_1_trgA = '0;
+reg eff_1_trgB = '0;
+reg eff_1_en = '0;
+
+reg eff_2_trgA = '0;
+reg eff_2_trgB = '0;
+reg eff_2_en = '0;
+
+reg eff_3_trg = '0;
+reg eff_3_en = '0;
+reg eff_3_a = '0;
+
+`ifdef FAST
+always @(posedge gclk) begin
+`else
+always @(posedge clk) begin
+`endif
+    counter <= counter + 1;
+
+    eff_0_trg = 32'b00000000000000110011001100101010 >> counter;
+    eff_0_en <= 32'b00000000000001100000110110110110 >> counter;
+
+    eff_1_trgA = 32'b00000000000000000011110000011110 >> counter;
+    eff_1_trgB = 32'b00000000000000001111000001111000 >> counter;
+    eff_1_en  <= 32'b00000000000000001010101010101010 >> counter;
+
+    eff_2_trgA = counter[0];
+    eff_2_trgB = !counter[0];
+    eff_2_en  <= 32'b00000000000000000000001111111100 >> counter;
+
+    eff_3_trg  = 32'b10101010101010101010101010101010 >> counter;
+    eff_3_en  <= 32'b11101110010001001110111001000100 >> counter;
+    eff_3_a   <= 32'b11111010111110100101000001010000 >> counter;
+end
+
+always @(posedge eff_0_trg)
+    if (eff_0_en)
+        $display("%02d: eff0 +", counter);
+
+always @(negedge eff_0_trg)
+    if (eff_0_en)
+        $display("%02d: eff0 -", counter);
+
+always @(posedge eff_0_trg, negedge eff_0_trg)
+    if (eff_0_en)
+        $display("%02d: eff0 *", counter);
+
+always @(posedge eff_1_trgA, posedge eff_1_trgB)
+    if (eff_1_en)
+        $display("%02d: eff1 ++", counter);
+
+always @(posedge eff_1_trgA, negedge eff_1_trgB)
+    if (eff_1_en)
+        $display("%02d: eff1 +-", counter);
+
+always @(negedge eff_1_trgA, posedge eff_1_trgB)
+    if (eff_1_en)
+        $display("%02d: eff1 -+", counter);
+
+always @(negedge eff_1_trgA, negedge eff_1_trgB)
+    if (eff_1_en)
+        $display("%02d: eff1 --", counter);
+
+always @(posedge eff_2_trgA, posedge eff_2_trgB)
+    if (eff_2_en)
+        $display("repeated");
+
+always @(posedge eff_3_trg)
+    if (eff_3_en) begin
+        $display("%02d: eff3 vvv", counter);
+`ifdef NO_ASSERT
+        if (!eff_3_a)
+            $display("Failed assertion eff3 at");
+`else
+        eff3: assert(eff_3_a);
+`endif
+    end
+
+`ifdef __ICARUS__
+initial gclk = 0;
+always @(gclk) gclk <= #5 !gclk;
+always @(posedge gclk)
+    if (counter == 32)
+        $finish(0);
+`endif
+
+endmodule
diff --git a/yosys/tests/various/const_arg_loop.ys b/yosys/tests/various/const_arg_loop.ys
index 392532213b4..01bea704499 100644
--- a/yosys/tests/various/const_arg_loop.ys
+++ b/yosys/tests/various/const_arg_loop.ys
@@ -3,4 +3,5 @@ hierarchy
 proc
 opt -full
 select -module top
+async2sync
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/yosys/tests/various/const_func.ys b/yosys/tests/various/const_func.ys
index 2f60acfe670..d982c3a43fa 100644
--- a/yosys/tests/various/const_func.ys
+++ b/yosys/tests/various/const_func.ys
@@ -4,4 +4,5 @@ proc
 flatten
 opt -full
 select -module top
+async2sync
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/yosys/tests/various/countbits.ys b/yosys/tests/various/countbits.ys
index a556f7c5d83..f2db9cfe1f6 100644
--- a/yosys/tests/various/countbits.ys
+++ b/yosys/tests/various/countbits.ys
@@ -4,4 +4,5 @@ proc
 flatten
 opt -full
 select -module top
+async2sync
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/yosys/tests/various/dynamic_part_select.ys b/yosys/tests/various/dynamic_part_select.ys
index 2dc061e899b..9e303b9db2e 100644
--- a/yosys/tests/various/dynamic_part_select.ys
+++ b/yosys/tests/various/dynamic_part_select.ys
@@ -69,6 +69,24 @@ design -copy-from gate -as gate gate
 miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
 sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
 
+### For-loop select, one dynamic input, (* nowrshmsk *)
+design -reset
+read_verilog ./dynamic_part_select/forloop_select_nowrshmsk.v
+proc
+rename -top gold
+design -stash gold
+
+read_verilog ./dynamic_part_select/forloop_select_gate.v
+proc
+rename -top gate
+design -stash gate
+
+design -copy-from gold -as gold gold
+design -copy-from gate -as gate gate
+
+miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
+sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
+
 #### Double loop (part-select, reset) ### 
 design -reset
 read_verilog ./dynamic_part_select/reset_test.v
diff --git a/yosys/tests/various/dynamic_part_select/forloop_select_nowrshmsk.v b/yosys/tests/various/dynamic_part_select/forloop_select_nowrshmsk.v
new file mode 100644
index 00000000000..75415c3130e
--- /dev/null
+++ b/yosys/tests/various/dynamic_part_select/forloop_select_nowrshmsk.v
@@ -0,0 +1,20 @@
+`default_nettype none
+module forloop_select #(parameter WIDTH=16, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW)
+   (input wire             clk,
+    input wire [CTRLW-1:0] ctrl,
+    input wire [DINW-1:0]  din,
+    input wire             en,
+    (* nowrshmsk *)
+    output reg [WIDTH-1:0] dout);
+
+   reg [SELW:0]            sel;
+   localparam SLICE = WIDTH/(SELW**2);
+
+   always @(posedge clk)
+     begin
+        if (en) begin
+           for (sel = 0; sel <= 4'hf; sel=sel+1'b1)
+             dout[(ctrl*sel)+:SLICE] <= din;
+        end
+     end
+endmodule
diff --git a/yosys/tests/various/hierarchy_generate.ys b/yosys/tests/various/hierarchy_generate.ys
new file mode 100644
index 00000000000..9c01afb6499
--- /dev/null
+++ b/yosys/tests/various/hierarchy_generate.ys
@@ -0,0 +1,20 @@
+read_verilog -icells <<EOF
+module top(input [2:0] a, input [2:0] b, output [2:0] y);
+
+sub sub_i (.a(a[0]), .b(b[0]), .y(y[0]));
+
+unknown_sub sub_ii (.a(a[1]), .b(b[1]), .y(y[1]));
+
+$__dunder_sub sub_iii (.a(a[2]), .b(b[2]), .y(y[2]));
+
+endmodule
+
+module sub(input a, input b, output y);
+    assign y = a ^ b;
+endmodule
+EOF
+hierarchy -generate unknown_sub i:a i:b o:y
+hierarchy -generate $__dunder_sub i:a i:b o:y
+hierarchy -generate $xor i:A i:B o:Y # this one is ignored
+hierarchy -top top -check
+check -assert
diff --git a/yosys/tests/various/logger_fail.sh b/yosys/tests/various/logger_fail.sh
index 19b65000718..c318b648d11 100755
--- a/yosys/tests/various/logger_fail.sh
+++ b/yosys/tests/various/logger_fail.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 fail() {
 	echo "$1" >&2
diff --git a/yosys/tests/various/param_struct.ys b/yosys/tests/various/param_struct.ys
index b8de67968d5..bb26b61d586 100644
--- a/yosys/tests/various/param_struct.ys
+++ b/yosys/tests/various/param_struct.ys
@@ -47,4 +47,5 @@ end
 endmodule
 EOF
 hierarchy; proc; opt
+async2sync
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/yosys/tests/various/peepopt.ys b/yosys/tests/various/peepopt.ys
index 45e936a21e6..cbbd477e8b1 100644
--- a/yosys/tests/various/peepopt.ys
+++ b/yosys/tests/various/peepopt.ys
@@ -46,7 +46,31 @@ design -import gold -as gold peepopt_shiftmul_2
 design -import gate -as gate peepopt_shiftmul_2
 
 miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
-sat -show-public -enable_undef -prove-asserts miter
+sat -verify -show-public -enable_undef -prove-asserts miter
+cd gate
+select -assert-count 1 t:$shr
+select -assert-count 1 t:$mul
+select -assert-count 0 t:$shr t:$mul %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_shiftmul_3 (input [7:0] D, input [0:0] S, output [3:0] Y);
+	assign Y = D >> (S*5);
+endmodule
+EOT
+
+prep
+design -save gold
+peepopt
+design -stash gate
+
+design -import gold -as gold peepopt_shiftmul_3
+design -import gate -as gate peepopt_shiftmul_3
+
+miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
+sat -verify -show-public -enable_undef -prove-asserts miter
 cd gate
 select -assert-count 1 t:$shr
 select -assert-count 1 t:$mul
diff --git a/yosys/tests/various/scopeinfo.ys b/yosys/tests/various/scopeinfo.ys
new file mode 100644
index 00000000000..f8d4ca31b7f
--- /dev/null
+++ b/yosys/tests/various/scopeinfo.ys
@@ -0,0 +1,110 @@
+read_verilog <<EOT
+(* module_attr = "module_attr" *)
+module some_mod(input a, output y);
+    assign y = a;
+endmodule
+
+module top(input a, output y);
+    (* inst_attr = "inst_attr" *)
+    some_mod some_inst(.a(a), .y(y));
+endmodule
+EOT
+
+hierarchy -top top
+flatten
+
+select -assert-count 1 top/n:some_inst top/t:$scopeinfo %i
+select -assert-count 1 top/n:some_inst top/r:TYPE=module %i
+select -assert-count 1 top/n:some_inst top/a:cell_inst_attr=inst_attr %i
+select -assert-count 1 top/n:some_inst top/a:module_module_attr=module_attr %i
+select -assert-count 1 top/n:some_inst top/a:cell_src %i
+select -assert-count 1 top/n:some_inst top/a:module_src %i
+
+opt_clean
+select -assert-count 1 top/t:$scopeinfo
+opt_clean -purge
+select -assert-count 0 top/t:$scopeinfo
+
+design -reset
+
+read_verilog <<EOT
+(* module_attr = "module_attr_deep" *)
+module some_mod_deep(input a, output y);
+    assign y = a;
+endmodule
+
+(* module_attr = "module_attr" *)
+module some_mod(input a, output y);
+    (* inst_attr = "inst_attr_deep" *)
+    some_mod_deep some_inst_deep(.a(a), .y(y));
+endmodule
+
+module top(input a, output y);
+    (* inst_attr = "inst_attr" *)
+    some_mod some_inst(.a(a), .y(y));
+endmodule
+EOT
+
+hierarchy -top top
+flatten
+
+select -assert-count 2 top/t:$scopeinfo
+select -assert-count 1 top/n:some_inst top/t:$scopeinfo %i
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep
+
+select -assert-count 1 top/n:some_inst top/r:TYPE=module %i
+select -assert-count 1 top/n:some_inst top/a:cell_inst_attr=inst_attr %i
+select -assert-count 1 top/n:some_inst top/a:module_module_attr=module_attr %i
+select -assert-count 1 top/n:some_inst top/a:cell_src %i
+select -assert-count 1 top/n:some_inst top/a:module_src %i
+
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/r:TYPE=module %i
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_inst_attr=inst_attr_deep %i
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_module_attr=module_attr_deep %i
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_src %i
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_src %i
+
+
+design -reset
+
+read_verilog <<EOT
+(* module_attr = "module_attr_deep" *)
+(* keep_hierarchy *)
+module some_mod_deep(input a, output y);
+    assign y = a;
+endmodule
+
+(* module_attr = "module_attr" *)
+module some_mod(input a, output y);
+    (* inst_attr = "inst_attr_deep" *)
+    some_mod_deep some_inst_deep(.a(a), .y(y));
+endmodule
+
+module top(input a, output y);
+    (* inst_attr = "inst_attr" *)
+    some_mod some_inst(.a(a), .y(y));
+endmodule
+EOT
+
+hierarchy -top top
+flatten top
+
+select -assert-count 1 top/t:$scopeinfo
+setattr -mod -unset keep_hierarchy *
+flatten
+
+select -assert-count 2 top/t:$scopeinfo
+select -assert-count 1 top/n:some_inst top/t:$scopeinfo %i
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep
+
+select -assert-count 1 top/n:some_inst top/r:TYPE=module %i
+select -assert-count 1 top/n:some_inst top/a:cell_inst_attr=inst_attr %i
+select -assert-count 1 top/n:some_inst top/a:module_module_attr=module_attr %i
+select -assert-count 1 top/n:some_inst top/a:cell_src %i
+select -assert-count 1 top/n:some_inst top/a:module_src %i
+
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/r:TYPE=module %i
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_inst_attr=inst_attr_deep %i
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_module_attr=module_attr_deep %i
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_src %i
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_src %i
\ No newline at end of file
diff --git a/yosys/tests/various/sformatf.ys b/yosys/tests/various/sformatf.ys
index 66d6b0dbe9e..f281a9cd530 100644
--- a/yosys/tests/various/sformatf.ys
+++ b/yosys/tests/various/sformatf.ys
@@ -5,7 +5,7 @@ module top;
 	localparam b = $sformatf("%d", 4'b011);
 	generate
 		if (a != "0x5a") $error("a incorrect!");
-		if (b != "3") $error("b incorrect!");
+		if (b != " 3") $error("b incorrect!");
 	endgenerate
 endmodule
 
diff --git a/yosys/tests/various/smtlib2_module-expected.smt2 b/yosys/tests/various/smtlib2_module-expected.smt2
deleted file mode 100644
index 494e7cda095..00000000000
--- a/yosys/tests/various/smtlib2_module-expected.smt2
+++ /dev/null
@@ -1,96 +0,0 @@
-; SMT-LIBv2 description generated by Yosys $VERSION
-; yosys-smt2-module smtlib2
-(declare-sort |smtlib2_s| 0)
-(declare-fun |smtlib2_is| (|smtlib2_s|) Bool)
-(declare-fun |smtlib2#0| (|smtlib2_s|) (_ BitVec 8)) ; \a
-; yosys-smt2-input a 8
-; yosys-smt2-witness {"offset": 0, "path": ["\\a"], "smtname": "a", "smtoffset": 0, "type": "input", "width": 8}
-(define-fun |smtlib2_n a| ((state |smtlib2_s|)) (_ BitVec 8) (|smtlib2#0| state))
-(declare-fun |smtlib2#1| (|smtlib2_s|) (_ BitVec 8)) ; \b
-; yosys-smt2-input b 8
-; yosys-smt2-witness {"offset": 0, "path": ["\\b"], "smtname": "b", "smtoffset": 0, "type": "input", "width": 8}
-(define-fun |smtlib2_n b| ((state |smtlib2_s|)) (_ BitVec 8) (|smtlib2#1| state))
-; yosys-smt2-output add 8
-; yosys-smt2-witness {"offset": 0, "path": ["\\add"], "smtname": "add", "smtoffset": 0, "type": "blackbox", "width": 8}
-(define-fun |smtlib2_n add| ((state |smtlib2_s|)) (_ BitVec 8) (let (
-(|a| (|smtlib2_n a| state))
-(|b| (|smtlib2_n b| state))
-)
-(bvadd a b)
-))
-; yosys-smt2-output eq 1
-; yosys-smt2-witness {"offset": 0, "path": ["\\eq"], "smtname": "eq", "smtoffset": 0, "type": "blackbox", "width": 1}
-(define-fun |smtlib2_n eq| ((state |smtlib2_s|)) Bool (let (
-(|a| (|smtlib2_n a| state))
-(|b| (|smtlib2_n b| state))
-)
-(= a b)
-))
-; yosys-smt2-output sub 8
-; yosys-smt2-witness {"offset": 0, "path": ["\\sub"], "smtname": "sub", "smtoffset": 0, "type": "blackbox", "width": 8}
-(define-fun |smtlib2_n sub| ((state |smtlib2_s|)) (_ BitVec 8) (let (
-(|a| (|smtlib2_n a| state))
-(|b| (|smtlib2_n b| state))
-)
-(bvadd a (bvneg b))
-))
-(define-fun |smtlib2_a| ((state |smtlib2_s|)) Bool true)
-(define-fun |smtlib2_u| ((state |smtlib2_s|)) Bool true)
-(define-fun |smtlib2_i| ((state |smtlib2_s|)) Bool true)
-(define-fun |smtlib2_h| ((state |smtlib2_s|)) Bool true)
-(define-fun |smtlib2_t| ((state |smtlib2_s|) (next_state |smtlib2_s|)) Bool true) ; end of module smtlib2
-; yosys-smt2-module uut
-(declare-sort |uut_s| 0)
-(declare-fun |uut_is| (|uut_s|) Bool)
-; yosys-smt2-cell smtlib2 s
-; yosys-smt2-witness {"path": ["\\s"], "smtname": "s", "type": "cell"}
-(declare-fun |uut#0| (|uut_s|) (_ BitVec 8)) ; \add
-(declare-fun |uut#1| (|uut_s|) Bool) ; \eq
-(declare-fun |uut#2| (|uut_s|) (_ BitVec 8)) ; \sub
-(declare-fun |uut_h s| (|uut_s|) |smtlib2_s|)
-; yosys-smt2-anyconst uut#3 8 smtlib2_module.v:14.17-14.26
-; yosys-smt2-witness {"offset": 0, "path": ["\\a"], "smtname": 3, "smtoffset": 0, "type": "init", "width": 8}
-(declare-fun |uut#3| (|uut_s|) (_ BitVec 8)) ; \a
-; yosys-smt2-anyconst uut#4 8 smtlib2_module.v:14.32-14.41
-; yosys-smt2-witness {"offset": 0, "path": ["\\b"], "smtname": 4, "smtoffset": 0, "type": "init", "width": 8}
-(declare-fun |uut#4| (|uut_s|) (_ BitVec 8)) ; \b
-(define-fun |uut#5| ((state |uut_s|)) (_ BitVec 8) (bvadd (|uut#3| state) (|uut#4| state))) ; \add2
-(define-fun |uut#6| ((state |uut_s|)) Bool (= (|uut#0| state) (|uut#5| state))) ; $0$formal$smtlib2_module.v:28$1_CHECK[0:0]$9
-; yosys-smt2-assert 0 $assert$smtlib2_module.v:28$19 smtlib2_module.v:28.17-29.22
-(define-fun |uut_a 0| ((state |uut_s|)) Bool (or (|uut#6| state) (not true))) ; $assert$smtlib2_module.v:28$19
-(define-fun |uut#7| ((state |uut_s|)) (_ BitVec 8) (bvsub (|uut#3| state) (|uut#4| state))) ; \sub2
-(define-fun |uut#8| ((state |uut_s|)) Bool (= (|uut#2| state) (|uut#7| state))) ; $0$formal$smtlib2_module.v:29$2_CHECK[0:0]$11
-; yosys-smt2-assert 1 $assert$smtlib2_module.v:29$20 smtlib2_module.v:29.23-30.22
-(define-fun |uut_a 1| ((state |uut_s|)) Bool (or (|uut#8| state) (not true))) ; $assert$smtlib2_module.v:29$20
-(define-fun |uut#9| ((state |uut_s|)) Bool (= (|uut#3| state) (|uut#4| state))) ; $eq$smtlib2_module.v:31$17_Y
-(define-fun |uut#10| ((state |uut_s|)) Bool (= (ite (|uut#1| state) #b1 #b0) (ite (|uut#9| state) #b1 #b0))) ; $0$formal$smtlib2_module.v:30$3_CHECK[0:0]$13
-; yosys-smt2-assert 2 $assert$smtlib2_module.v:30$21 smtlib2_module.v:30.23-31.25
-(define-fun |uut_a 2| ((state |uut_s|)) Bool (or (|uut#10| state) (not true))) ; $assert$smtlib2_module.v:30$21
-(define-fun |uut_a| ((state |uut_s|)) Bool (and
-  (|uut_a 0| state)
-  (|uut_a 1| state)
-  (|uut_a 2| state)
-  (|smtlib2_a| (|uut_h s| state))
-))
-(define-fun |uut_u| ((state |uut_s|)) Bool
-  (|smtlib2_u| (|uut_h s| state))
-)
-(define-fun |uut_i| ((state |uut_s|)) Bool
-  (|smtlib2_i| (|uut_h s| state))
-)
-(define-fun |uut_h| ((state |uut_s|)) Bool (and
-  (= (|uut_is| state) (|smtlib2_is| (|uut_h s| state)))
-  (= (|uut#3| state) (|smtlib2_n a| (|uut_h s| state))) ; smtlib2.a
-  (= (|uut#0| state) (|smtlib2_n add| (|uut_h s| state))) ; smtlib2.add
-  (= (|uut#4| state) (|smtlib2_n b| (|uut_h s| state))) ; smtlib2.b
-  (= (|uut#1| state) (|smtlib2_n eq| (|uut_h s| state))) ; smtlib2.eq
-  (= (|uut#2| state) (|smtlib2_n sub| (|uut_h s| state))) ; smtlib2.sub
-  (|smtlib2_h| (|uut_h s| state))
-))
-(define-fun |uut_t| ((state |uut_s|) (next_state |uut_s|)) Bool (and
-  (= (|uut#4| state) (|uut#4| next_state)) ; $anyconst$5 \b
-  (= (|uut#3| state) (|uut#3| next_state)) ; $anyconst$4 \a
-  (|smtlib2_t| (|uut_h s| state) (|uut_h s| next_state))
-)) ; end of module uut
-; yosys-smt2-topmod uut
-; end of yosys output
diff --git a/yosys/tests/various/smtlib2_module.sh b/yosys/tests/various/smtlib2_module.sh
deleted file mode 100755
index 491f6514877..00000000000
--- a/yosys/tests/various/smtlib2_module.sh
+++ /dev/null
@@ -1,5 +0,0 @@
-#!/bin/bash
-set -ex
-../../yosys -q -p 'read_verilog -formal smtlib2_module.v; prep; write_smt2 smtlib2_module.smt2'
-sed 's/; SMT-LIBv2 description generated by Yosys .*/; SMT-LIBv2 description generated by Yosys $VERSION/;s/  *$//' smtlib2_module.smt2 > smtlib2_module-filtered.smt2
-diff -au smtlib2_module-expected.smt2 smtlib2_module-filtered.smt2
diff --git a/yosys/tests/various/smtlib2_module.v b/yosys/tests/various/smtlib2_module.v
deleted file mode 100644
index 4aad8690527..00000000000
--- a/yosys/tests/various/smtlib2_module.v
+++ /dev/null
@@ -1,33 +0,0 @@
-(* smtlib2_module *)
-module smtlib2(a, b, add, sub, eq);
-	input [7:0] a, b;
-	(* smtlib2_comb_expr = "(bvadd a b)" *)
-	output [7:0] add;
-	(* smtlib2_comb_expr = "(bvadd a (bvneg b))" *)
-	output [7:0] sub;
-	(* smtlib2_comb_expr = "(= a b)" *)
-	output eq;
-endmodule
-
-(* top *)
-module uut;
-	wire [7:0] a = $anyconst, b = $anyconst, add, sub, add2, sub2;
-	wire eq;
-
-	assign add2 = a + b;
-	assign sub2 = a - b;
-
-	smtlib2 s (
-		.a(a),
-		.b(b),
-		.add(add),
-		.sub(sub),
-		.eq(eq)
-	);
-
-	always @* begin
-		assert(add == add2);
-		assert(sub == sub2);
-		assert(eq == (a == b));
-	end
-endmodule
diff --git a/yosys/tests/various/struct_access.ys b/yosys/tests/various/struct_access.ys
index 2282edd9246..43a2ac8b827 100644
--- a/yosys/tests/various/struct_access.ys
+++ b/yosys/tests/various/struct_access.ys
@@ -2,4 +2,5 @@ read_verilog -sv struct_access.sv
 hierarchy
 proc
 opt
+async2sync
 sat -verify -seq 1 -prove-asserts -show-all
diff --git a/yosys/tests/various/sv_implicit_ports.sh b/yosys/tests/various/sv_implicit_ports.sh
index 9a01447f7cf..5266fffe516 100755
--- a/yosys/tests/various/sv_implicit_ports.sh
+++ b/yosys/tests/various/sv_implicit_ports.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 trap 'echo "ERROR in sv_implicit_ports.sh" >&2; exit 1' ERR
 
diff --git a/yosys/tests/various/svalways.sh b/yosys/tests/various/svalways.sh
index 2cc09f801ba..7765907c708 100755
--- a/yosys/tests/various/svalways.sh
+++ b/yosys/tests/various/svalways.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 trap 'echo "ERROR in svalways.sh" >&2; exit 1' ERR
 
diff --git a/yosys/tests/verific/clocking.ys b/yosys/tests/verific/clocking.ys
new file mode 100644
index 00000000000..bfdbeb748c1
--- /dev/null
+++ b/yosys/tests/verific/clocking.ys
@@ -0,0 +1,10 @@
+read -sv <<EOT
+module test(input foo);
+always @(*) assert(foo);
+endmodule
+EOT
+
+verific -import test
+prep
+
+select -assert-count 1 t:$assert
diff --git a/yosys/tests/verific/memory_semantics.ys b/yosys/tests/verific/memory_semantics.ys
new file mode 100644
index 00000000000..7287f847ff6
--- /dev/null
+++ b/yosys/tests/verific/memory_semantics.ys
@@ -0,0 +1,94 @@
+verific -sv <<EOF
+
+module top(clk);
+input wire clk;
+
+parameter DEPTH_LOG2 = 4;
+parameter DEPTH = 2**DEPTH_LOG2;
+parameter BYTEWIDTH = 8;
+parameter WIDTH = BYTEWIDTH*4;
+parameter PRIME1 = 237481091;
+parameter PRIME2 = 296851369;
+
+(* ram_style = "block" *)
+reg [WIDTH-1:0] mem [DEPTH-1:0];
+
+integer i;
+initial begin
+    for (i = 0; i < DEPTH; i = i + 1) begin
+        // Make up data by multiplying a large prime with the address,
+        // then cropping and retaining the lower bits
+        mem[i] = PRIME1 * i;
+    end
+end
+
+reg [DEPTH_LOG2-1:0] counter = 0;
+reg done = 1'b0;
+always @(posedge clk) begin
+    if (!done)
+        counter = counter + 1'b1;
+    if (counter == 0)
+        done = 1'b1;
+end
+
+wire [WIDTH-1:0] old_data = PRIME1 * counter;
+wire [WIDTH-1:0] new_data = PRIME2 * counter;
+
+reg [WIDTH-1:0] expect_old_data;
+reg [WIDTH-1:0] expect_mixed_data;
+
+always @(posedge clk) begin
+    if (!done) begin
+        expect_old_data <= mem[counter];
+        mem[counter][31:24] <= new_data[31:24];
+        mem[counter][23:16] = new_data[23:16]; // !!! is blocking
+        mem[counter][15:8] <= new_data[15:8];
+        mem[counter][7:0] <= new_data[7:0];
+        expect_mixed_data <= mem[counter];
+    end
+end
+
+reg done_delay1 = 1'b1;
+reg [WIDTH-1:0] new_data_delay1 = 1'b1;
+reg [WIDTH-1:0] old_data_delay1 = 1'b1;
+
+always @(posedge clk) begin
+    if (!done_delay1) begin
+        assert(expect_old_data == old_data_delay1);
+        assert(expect_mixed_data[31:24] == old_data_delay1[31:24]);
+        assert(expect_mixed_data[23:16] == new_data_delay1[23:16]);
+        assert(expect_mixed_data[15:0] == old_data_delay1[15:0]);
+    end
+end
+
+reg [DEPTH_LOG2-1:0] counter_delay1;
+always @(posedge clk) begin
+    counter_delay1 <= counter;
+    done_delay1 <= done;
+    new_data_delay1 <= new_data;
+    old_data_delay1 <= old_data;
+end
+
+reg [DEPTH_LOG2-1:0] counter_delay2;
+reg done_delay2 = 1'b1;
+reg [WIDTH-1:0] new_data_delay2 = 1'b1;
+always @(posedge clk) begin
+    counter_delay2 <= counter_delay1;
+    done_delay2 <= done_delay1;
+    new_data_delay2 <= new_data_delay1;
+end
+
+always @(posedge clk) begin
+    if (!done_delay2)
+        assert(mem[counter_delay2] == new_data_delay2);
+end
+
+endmodule
+EOF
+
+hierarchy -top top
+proc
+opt_clean
+memory -nomap -nordff
+select -assert-count 1 t:$mem_v2
+sim -assert -clock clk -n 20
diff --git a/yosys/tests/verific/rom_case.ys b/yosys/tests/verific/rom_case.ys
new file mode 100644
index 00000000000..253cc0766ef
--- /dev/null
+++ b/yosys/tests/verific/rom_case.ys
@@ -0,0 +1,78 @@
+verific -sv <<EOF
+module rom(input clk, input [2:0] addr, (* ram_style = "block" *) output reg [7:0] data);
+
+always @(posedge clk) begin
+	case (addr)
+		3'b000: data <= 8'h12;
+		3'b001: data <= 8'hAB;
+		3'b010: data <= 8'h42;
+		3'b011: data <= 8'h23;
+		3'b100: data <= 8'h66;
+		3'b101: data <= 8'hC0;
+		3'b110: data <= 8'h3F;
+		3'b111: data <= 8'h95;
+	endcase
+end
+
+endmodule
+EOF
+hierarchy -top rom
+proc
+opt
+opt -full
+memory -nomap
+dump
+memory_libmap -lib ../memlib/memlib_block_sdp.txt
+memory_map
+stat
+select -assert-count 1 t:RAM_BLOCK_SDP
+
+
+design -reset
+
+verific -vhdl <<EOF
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity rom_example is
+	port (
+		clk : in std_logic;
+		addr : in std_logic_vector(2 downto 0);
+		data : out std_logic_vector (7 downto 0)
+	);
+end entity rom_example;
+
+architecture rtl of rom_example is
+	attribute rom_style : string;
+	attribute rom_style of data : signal is "block";
+begin
+	
+	p_rom : process(clk)
+	begin
+		if rising_edge(clk) then
+			case addr is
+				when "000" => data <= X"12";
+				when "001" => data <= X"AB";
+				when "010" => data <= X"42";
+				when "011" => data <= X"23";
+				when "100" => data <= X"66";
+				when "101" => data <= X"C0";
+				when "110" => data <= X"3F";
+				when others => data <= X"95";
+			end case;
+		end if;
+	end process p_rom;
+	
+end architecture rtl;
+EOF
+hierarchy -top rom_example
+proc
+opt
+opt -full
+memory -nomap
+dump
+memory_libmap -lib ../memlib/memlib_block_sdp.txt
+memory_map
+stat
+select -assert-count 1 t:RAM_BLOCK_SDP
\ No newline at end of file
diff --git a/yosys/tests/verilog/.gitignore b/yosys/tests/verilog/.gitignore
index 96ebe20ba26..cfd72076e4e 100644
--- a/yosys/tests/verilog/.gitignore
+++ b/yosys/tests/verilog/.gitignore
@@ -1,6 +1,10 @@
 /*.log
 /*.out
+/*.err
 /run-test.mk
 /const_arst.v
 /const_sr.v
 /doubleslash.v
+/roundtrip_proc_1.v
+/roundtrip_proc_2.v
+/assign_to_reg.v
diff --git a/yosys/tests/verilog/asgn_expr.sv b/yosys/tests/verilog/asgn_expr.sv
new file mode 100644
index 00000000000..25f9caa33d1
--- /dev/null
+++ b/yosys/tests/verilog/asgn_expr.sv
@@ -0,0 +1,73 @@
+module top;
+    integer x, y, z;
+    task check;
+        input integer a, b, c;
+        assert (x == a);
+        assert (y == b);
+        assert (z == c);
+    endtask
+    always_comb begin
+        x = 0; y = 0; z = 0;
+        check(0, 0, 0);
+
+        // post-increment/decrement statements
+        x++;
+        check(1, 0, 0);
+        (* bar *) y (* foo *) ++;
+        check(1, 1, 0);
+        z--;
+        check(1, 1, -1);
+        (* bar *) z (* foo *) --;
+        check(1, 1, -2);
+
+        // pre-increment/decrement statements are equivalent
+        ++z;
+        check(1, 1, -1);
+        (* bar *) ++ (* foo *) z;
+        check(1, 1, 0);
+        --x;
+        check(0, 1, 0);
+        (* bar *) -- (* foo *) y;
+        check(0, 0, 0);
+
+        // procedural pre-increment/decrement expressions
+        z = ++x;
+        check(1, 0, 1);
+        z = ++ (* foo *) x;
+        check(2, 0, 2);
+        y = --x;
+        check(1, 1, 2);
+        y = -- (* foo *) x;
+
+        // procedural post-increment/decrement expressions
+        // TODO: support attributes on post-increment/decrement
+        check(0, 0, 2);
+        y = x++;
+        check(1, 0, 2);
+        y = x--;
+        check(0, 1, 2);
+
+        // procedural assignment expressions
+        x = (y = (z = 99) + 1) + 1;
+        check(101, 100, 99);
+        x = (y *= 2);
+        check(200, 200, 99);
+        x = (z >>= 2) * 4;
+        check(96, 200, 24);
+        y = (z >>= 1'sb1) * 2; // shift is implicitly cast to unsigned
+        check(96, 24, 12);
+
+        // check width of post-increment expressions
+        z = (y = 0);
+        begin
+            byte w;
+            w = 0;
+            x = {1'b1, ++w};
+            check(257, 0, 0);
+            assert (w == 1);
+            x = {2'b10, w++};
+            check(513, 0, 0);
+            assert (w == 2);
+        end
+    end
+endmodule
diff --git a/yosys/tests/verilog/asgn_expr.ys b/yosys/tests/verilog/asgn_expr.ys
new file mode 100644
index 00000000000..78c005228f4
--- /dev/null
+++ b/yosys/tests/verilog/asgn_expr.ys
@@ -0,0 +1,4 @@
+read_verilog -sv asgn_expr.sv
+proc
+async2sync
+sat -verify -prove-asserts -show-all
diff --git a/yosys/tests/verilog/asgn_expr_not_proc_1.ys b/yosys/tests/verilog/asgn_expr_not_proc_1.ys
new file mode 100644
index 00000000000..72ba0bd89dc
--- /dev/null
+++ b/yosys/tests/verilog/asgn_expr_not_proc_1.ys
@@ -0,0 +1,7 @@
+logger -expect error "Assignments within expressions are only permitted within procedures." 1
+read_verilog -sv <<EOF
+module top;
+integer x, y;
+assign x = y++;
+endmodule
+EOF
diff --git a/yosys/tests/verilog/asgn_expr_not_proc_2.ys b/yosys/tests/verilog/asgn_expr_not_proc_2.ys
new file mode 100644
index 00000000000..309f34ad73c
--- /dev/null
+++ b/yosys/tests/verilog/asgn_expr_not_proc_2.ys
@@ -0,0 +1,7 @@
+logger -expect error "Assignments within expressions are only permitted within procedures." 1
+read_verilog -sv <<EOF
+module top;
+integer x;
+wire [++x:0] y;
+endmodule
+EOF
diff --git a/yosys/tests/verilog/asgn_expr_not_proc_3.ys b/yosys/tests/verilog/asgn_expr_not_proc_3.ys
new file mode 100644
index 00000000000..476edd0bf04
--- /dev/null
+++ b/yosys/tests/verilog/asgn_expr_not_proc_3.ys
@@ -0,0 +1,7 @@
+logger -expect error "Assignments within expressions are only permitted within procedures." 1
+read_verilog -sv <<EOF
+module top;
+integer x;
+integer y = --x;
+endmodule
+EOF
diff --git a/yosys/tests/verilog/asgn_expr_not_proc_4.ys b/yosys/tests/verilog/asgn_expr_not_proc_4.ys
new file mode 100644
index 00000000000..3a7769ac997
--- /dev/null
+++ b/yosys/tests/verilog/asgn_expr_not_proc_4.ys
@@ -0,0 +1,7 @@
+logger -expect error "Assignments within expressions are only permitted within procedures." 1
+read_verilog -sv <<EOF
+module top;
+integer x, y;
+assign x = (y = 1);
+endmodule
+EOF
diff --git a/yosys/tests/verilog/asgn_expr_not_proc_5.ys b/yosys/tests/verilog/asgn_expr_not_proc_5.ys
new file mode 100644
index 00000000000..71ab973dd07
--- /dev/null
+++ b/yosys/tests/verilog/asgn_expr_not_proc_5.ys
@@ -0,0 +1,7 @@
+logger -expect error "Assignments within expressions are only permitted within procedures." 1
+read_verilog -sv <<EOF
+module top;
+integer x, y;
+assign x = (y += 2);
+endmodule
+EOF
diff --git a/yosys/tests/verilog/asgn_expr_not_sv_1.ys b/yosys/tests/verilog/asgn_expr_not_sv_1.ys
new file mode 100644
index 00000000000..e6cb9e84fc9
--- /dev/null
+++ b/yosys/tests/verilog/asgn_expr_not_sv_1.ys
@@ -0,0 +1,7 @@
+logger -expect error "Assignments within expressions are only supported in SystemVerilog mode." 1
+read_verilog <<EOF
+module top;
+integer x, y;
+initial y = ++x;
+endmodule
+EOF
diff --git a/yosys/tests/verilog/asgn_expr_not_sv_2.ys b/yosys/tests/verilog/asgn_expr_not_sv_2.ys
new file mode 100644
index 00000000000..c6cc18aaa70
--- /dev/null
+++ b/yosys/tests/verilog/asgn_expr_not_sv_2.ys
@@ -0,0 +1,7 @@
+logger -expect error "Assignments within expressions are only supported in SystemVerilog mode." 1
+read_verilog <<EOF
+module top;
+integer x, y;
+initial y = x++;
+endmodule
+EOF
diff --git a/yosys/tests/verilog/asgn_expr_not_sv_3.ys b/yosys/tests/verilog/asgn_expr_not_sv_3.ys
new file mode 100644
index 00000000000..8ad95c83c78
--- /dev/null
+++ b/yosys/tests/verilog/asgn_expr_not_sv_3.ys
@@ -0,0 +1,7 @@
+logger -expect error "Assignments within expressions are only supported in SystemVerilog mode." 1
+read_verilog <<EOF
+module top;
+integer x, y;
+initial y = (x = 1);
+endmodule
+EOF
diff --git a/yosys/tests/verilog/asgn_expr_not_sv_4.ys b/yosys/tests/verilog/asgn_expr_not_sv_4.ys
new file mode 100644
index 00000000000..bc97e6c0d74
--- /dev/null
+++ b/yosys/tests/verilog/asgn_expr_not_sv_4.ys
@@ -0,0 +1,15 @@
+read_verilog -sv <<EOF
+module top;
+integer x, y;
+initial y = (x += 1);
+endmodule
+EOF
+design -reset
+
+logger -expect error "syntax error, unexpected TOK_ID" 1
+read_verilog <<EOF
+module top;
+integer x, y;
+initial y = (x += 1);
+endmodule
+EOF
diff --git a/yosys/tests/verilog/assign_to_reg.ys b/yosys/tests/verilog/assign_to_reg.ys
new file mode 100644
index 00000000000..80080e9f372
--- /dev/null
+++ b/yosys/tests/verilog/assign_to_reg.ys
@@ -0,0 +1,22 @@
+# https://github.com/yosyshq/yosys/issues/2035
+
+read_ilang <<END
+module \top
+  wire width 1 input 0 \halfbrite
+  wire width 2 output 1 \r_on
+  process $1
+    assign \r_on [1:0] 2'00
+    assign \r_on [1:0] 2'11
+    switch \halfbrite [0]
+      case 1'1
+        assign \r_on [1] 1'0
+    end
+  end
+end
+END
+proc_prune
+write_verilog assign_to_reg.v
+design -reset
+
+logger -expect-no-warnings
+read_verilog assign_to_reg.v
diff --git a/yosys/tests/verilog/atom_type_signedness.ys b/yosys/tests/verilog/atom_type_signedness.ys
index 22bbe6efc2f..c8a82f993c5 100644
--- a/yosys/tests/verilog/atom_type_signedness.ys
+++ b/yosys/tests/verilog/atom_type_signedness.ys
@@ -14,6 +14,6 @@ always_comb begin
 end
 endmodule
 EOT
-hierarchy; proc; opt
+hierarchy; proc; opt; async2sync
 select -module dut
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/yosys/tests/verilog/bug2042-sv.ys b/yosys/tests/verilog/bug2042-sv.ys
index 91989f412c5..c3b904eb4ac 100644
--- a/yosys/tests/verilog/bug2042-sv.ys
+++ b/yosys/tests/verilog/bug2042-sv.ys
@@ -17,6 +17,7 @@ output reg b
 endmodule
 EOT
 proc
+async2sync
 sat -verify -prove-asserts
 
 
@@ -42,6 +43,7 @@ output b, c
 endmodule
 EOT
 proc
+async2sync
 sat -verify -prove-asserts
 
 
diff --git a/yosys/tests/verilog/dynamic_range_lhs.sh b/yosys/tests/verilog/dynamic_range_lhs.sh
index 618204aed5f..f36c74bd2c8 100755
--- a/yosys/tests/verilog/dynamic_range_lhs.sh
+++ b/yosys/tests/verilog/dynamic_range_lhs.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 run() {
     alt=$1
@@ -15,7 +15,7 @@ run() {
         -p "read_verilog dynamic_range_lhs.v" \
         -p "proc" \
         -p "equiv_make gold gate equiv" \
-        -p "equiv_simple" \
+        -p "equiv_simple -undef" \
         -p "equiv_status -assert"
 }
 
diff --git a/yosys/tests/verilog/dynamic_range_lhs.v b/yosys/tests/verilog/dynamic_range_lhs.v
index ae291374db9..6eb95216571 100644
--- a/yosys/tests/verilog/dynamic_range_lhs.v
+++ b/yosys/tests/verilog/dynamic_range_lhs.v
@@ -1,12 +1,12 @@
 module gate(
-    output reg [`LEFT:`RIGHT] out_u, out_s,
     (* nowrshmsk = `ALT *)
+    output reg [`LEFT:`RIGHT] out_u, out_s,
     input wire data,
     input wire [1:0] sel1, sel2
 );
 always @* begin
-    out_u = 0;
-    out_s = 0;
+    out_u = 'x;
+    out_s = 'x;
     case (`SPAN)
     1: begin
         out_u[sel1*sel2] = data;
@@ -43,8 +43,8 @@ task set;
         out_s[b] = data;
 endtask
 always @* begin
-    out_u = 0;
-    out_s = 0;
+    out_u = 'x;
+    out_s = 'x;
     case (sel1*sel2)
         2'b00: set(0, 0);
         2'b01: set(1, 1);
diff --git a/yosys/tests/verilog/func_tern_hint.ys b/yosys/tests/verilog/func_tern_hint.ys
index ab8a1e032ed..dfbd13bdf39 100644
--- a/yosys/tests/verilog/func_tern_hint.ys
+++ b/yosys/tests/verilog/func_tern_hint.ys
@@ -1,4 +1,5 @@
 read_verilog -sv func_tern_hint.sv
 proc
 opt
+async2sync
 sat -verify -seq 1 -prove-asserts -show-all
diff --git a/yosys/tests/verilog/func_upto.ys b/yosys/tests/verilog/func_upto.ys
index 7a8c5350649..df986a0ba26 100644
--- a/yosys/tests/verilog/func_upto.ys
+++ b/yosys/tests/verilog/func_upto.ys
@@ -3,5 +3,6 @@ hierarchy -top top
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -prove-asserts -enable_undef
diff --git a/yosys/tests/verilog/int_types.ys b/yosys/tests/verilog/int_types.ys
index c17c44b4ce0..344f3ee09aa 100644
--- a/yosys/tests/verilog/int_types.ys
+++ b/yosys/tests/verilog/int_types.ys
@@ -3,5 +3,6 @@ hierarchy
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/yosys/tests/verilog/mem_bounds.ys b/yosys/tests/verilog/mem_bounds.ys
index 42623ad097b..146a6f43302 100644
--- a/yosys/tests/verilog/mem_bounds.ys
+++ b/yosys/tests/verilog/mem_bounds.ys
@@ -3,4 +3,5 @@ proc
 flatten
 opt -full
 select -module top
+async2sync
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all -enable_undef
diff --git a/yosys/tests/verilog/net_types.ys b/yosys/tests/verilog/net_types.ys
index 9f75812ea4a..b3a0b2b38f3 100644
--- a/yosys/tests/verilog/net_types.ys
+++ b/yosys/tests/verilog/net_types.ys
@@ -2,4 +2,5 @@ read_verilog -sv net_types.sv
 hierarchy
 proc
 opt -full
+async2sync
 sat -verify -prove-asserts -show-all
diff --git a/yosys/tests/verilog/package_task_func.ys b/yosys/tests/verilog/package_task_func.ys
index c94cc2acb26..0066946aed8 100644
--- a/yosys/tests/verilog/package_task_func.ys
+++ b/yosys/tests/verilog/package_task_func.ys
@@ -1,4 +1,5 @@
 read_verilog -sv package_task_func.sv
 proc
 opt -full
+async2sync
 sat -verify -seq 1 -prove-asserts -show-all
diff --git a/yosys/tests/verilog/param_no_default.ys b/yosys/tests/verilog/param_no_default.ys
index 7f161a909b7..0509f6a1aa5 100644
--- a/yosys/tests/verilog/param_no_default.ys
+++ b/yosys/tests/verilog/param_no_default.ys
@@ -1,7 +1,8 @@
 read_verilog -sv param_no_default.sv
-hierarchy
+hierarchy -top top
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/yosys/tests/verilog/parameters_across_files.ys b/yosys/tests/verilog/parameters_across_files.ys
index c53e4017930..94565eb6703 100644
--- a/yosys/tests/verilog/parameters_across_files.ys
+++ b/yosys/tests/verilog/parameters_across_files.ys
@@ -16,5 +16,6 @@ hierarchy
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/yosys/tests/verilog/past_signedness.ys b/yosys/tests/verilog/past_signedness.ys
index 91f32328b43..65b9f69e478 100644
--- a/yosys/tests/verilog/past_signedness.ys
+++ b/yosys/tests/verilog/past_signedness.ys
@@ -14,6 +14,7 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk
 
 design -reset
@@ -32,4 +33,5 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk
diff --git a/yosys/tests/verilog/prefix.ys b/yosys/tests/verilog/prefix.ys
index ed3b3a111a6..399a985aef0 100644
--- a/yosys/tests/verilog/prefix.ys
+++ b/yosys/tests/verilog/prefix.ys
@@ -2,4 +2,5 @@ read_verilog -sv prefix.sv
 hierarchy
 proc
 select -module top
+async2sync
 sat -verify -seq 1 -prove-asserts -show-all
diff --git a/yosys/tests/verilog/roundtrip_proc.ys b/yosys/tests/verilog/roundtrip_proc.ys
new file mode 100644
index 00000000000..7a57ed3100e
--- /dev/null
+++ b/yosys/tests/verilog/roundtrip_proc.ys
@@ -0,0 +1,65 @@
+# Test "casez to if/elif/else conversion" in backend
+
+read_verilog <<EOT
+module top(a, b, c, out);
+	input wire a, b, c;
+	output reg [3:0] out;
+	always @(*) begin
+		casez ({c, b, a})
+			3'b??1: begin
+				out = 0;
+			end
+			3'b?1?: begin
+				out = 1;
+			end
+			3'b1??: begin
+				out = 2;
+			end
+			default: begin
+				out = 3;
+			end
+		endcase
+	end
+endmodule
+EOT
+write_verilog roundtrip_proc_1.v
+design -stash gold
+read_verilog roundtrip_proc_1.v
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+prep
+miter -equiv -flatten -make_assert gold gate miter
+hierarchy -top miter
+sat -prove-asserts -verify
+
+design -reset
+read_verilog <<EOT
+module top(a, b, c, out);
+	input wire a, b, c;
+	output reg [3:0] out;
+	always @(*) begin
+		out <= 0;
+		if (a) begin
+			if (b)
+				out <= 1;
+		end else begin
+			if (c)
+				out <= 2;
+			else
+				out <= 3;
+		end
+	end
+endmodule
+EOT
+proc_clean
+write_verilog roundtrip_proc_2.v
+design -stash gold
+read_verilog roundtrip_proc_2.v
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+prep
+miter -equiv -flatten -make_assert gold gate miter
+hierarchy -top miter
+sat -prove-asserts -verify
diff --git a/yosys/tests/verilog/sign_array_query.ys b/yosys/tests/verilog/sign_array_query.ys
index f955450b793..b545b401516 100644
--- a/yosys/tests/verilog/sign_array_query.ys
+++ b/yosys/tests/verilog/sign_array_query.ys
@@ -14,6 +14,7 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk
 
 design -reset
@@ -32,6 +33,7 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk
 
 design -reset
@@ -49,4 +51,5 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk
diff --git a/yosys/tests/verilog/size_cast.ys b/yosys/tests/verilog/size_cast.ys
index 6890cd2d5b5..e3fb4b0c7ca 100644
--- a/yosys/tests/verilog/size_cast.ys
+++ b/yosys/tests/verilog/size_cast.ys
@@ -2,4 +2,5 @@ read_verilog -sv size_cast.sv
 proc
 opt -full
 select -module top
+async2sync
 sat -verify -prove-asserts -show-all
diff --git a/yosys/tests/verilog/struct_access.ys b/yosys/tests/verilog/struct_access.ys
index 29d569c010a..c115f4ede96 100644
--- a/yosys/tests/verilog/struct_access.ys
+++ b/yosys/tests/verilog/struct_access.ys
@@ -1,4 +1,5 @@
 read_verilog -formal -sv struct_access.sv
 proc
 opt -full
+async2sync
 sat -verify -seq 1 -prove-asserts -show-all
diff --git a/yosys/tests/verilog/task_attr.ys b/yosys/tests/verilog/task_attr.ys
index d6e75f85fea..56e964169e6 100644
--- a/yosys/tests/verilog/task_attr.ys
+++ b/yosys/tests/verilog/task_attr.ys
@@ -15,7 +15,7 @@ EOT
 select -assert-none a:* a:src %d
 
 
-logger -expect error "syntax error, unexpected ATTR_BEGIN" 1
+logger -expect error "syntax error, unexpected ';', expecting ATTR_BEGIN or TOK_INCREMENT or TOK_DECREMENT" 1
 design -reset
 read_verilog <<EOT
 module top;
diff --git a/yosys/tests/verilog/typedef_across_files.ys b/yosys/tests/verilog/typedef_across_files.ys
index ca9bba7361c..baa4b7919dd 100644
--- a/yosys/tests/verilog/typedef_across_files.ys
+++ b/yosys/tests/verilog/typedef_across_files.ys
@@ -19,5 +19,6 @@ EOF
 
 proc
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/yosys/tests/verilog/typedef_legacy_conflict.ys b/yosys/tests/verilog/typedef_legacy_conflict.ys
index 8dff4ec5f4e..dd1503a852c 100644
--- a/yosys/tests/verilog/typedef_legacy_conflict.ys
+++ b/yosys/tests/verilog/typedef_legacy_conflict.ys
@@ -33,5 +33,6 @@ hierarchy
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/yosys/tests/verilog/unbased_unsized.ys b/yosys/tests/verilog/unbased_unsized.ys
index e1bc99c64a7..75d1bf5e4b5 100644
--- a/yosys/tests/verilog/unbased_unsized.ys
+++ b/yosys/tests/verilog/unbased_unsized.ys
@@ -3,5 +3,6 @@ hierarchy
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/yosys/tests/verilog/unbased_unsized_shift.ys b/yosys/tests/verilog/unbased_unsized_shift.ys
index c36049600fd..2b5b9d8d082 100644
--- a/yosys/tests/verilog/unbased_unsized_shift.ys
+++ b/yosys/tests/verilog/unbased_unsized_shift.ys
@@ -3,5 +3,6 @@ hierarchy
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/yosys/tests/verilog/unreachable_case_sign.ys b/yosys/tests/verilog/unreachable_case_sign.ys
index 25bc0c6f040..569c8a313c8 100644
--- a/yosys/tests/verilog/unreachable_case_sign.ys
+++ b/yosys/tests/verilog/unreachable_case_sign.ys
@@ -12,6 +12,7 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk
 
 design -reset
@@ -29,5 +30,6 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk
 
diff --git a/yosys/tests/vloghtb/run-test.sh b/yosys/tests/vloghtb/run-test.sh
index 3c068961991..29f7c26805d 100755
--- a/yosys/tests/vloghtb/run-test.sh
+++ b/yosys/tests/vloghtb/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -ex
 
diff --git a/yosys/tests/vloghtb/test_febe.sh b/yosys/tests/vloghtb/test_febe.sh
index 482d44d9aa2..af0fe1b986e 100644
--- a/yosys/tests/vloghtb/test_febe.sh
+++ b/yosys/tests/vloghtb/test_febe.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -e
 source common.sh
diff --git a/yosys/tests/vloghtb/test_mapopt.sh b/yosys/tests/vloghtb/test_mapopt.sh
index 61528c2b4fd..c76e036a39c 100644
--- a/yosys/tests/vloghtb/test_mapopt.sh
+++ b/yosys/tests/vloghtb/test_mapopt.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -e
 source common.sh
diff --git a/yosys/tests/vloghtb/test_share.sh b/yosys/tests/vloghtb/test_share.sh
index 67cfe44e8de..87fac67fe39 100644
--- a/yosys/tests/vloghtb/test_share.sh
+++ b/yosys/tests/vloghtb/test_share.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -e
 source common.sh
diff --git a/yosys/tests/xprop/run-test.sh b/yosys/tests/xprop/run-test.sh
index db4b7ca82dd..84b7c4ac4ab 100755
--- a/yosys/tests/xprop/run-test.sh
+++ b/yosys/tests/xprop/run-test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
 
 python3 generate.py $@
diff --git a/yosys/tests/xprop/test.py b/yosys/tests/xprop/test.py
index a275b0d93f2..e2cddf67919 100644
--- a/yosys/tests/xprop/test.py
+++ b/yosys/tests/xprop/test.py
@@ -270,8 +270,9 @@ def vcdextract(signals, on_change, file, output, limit=None):
         print("initial begin", file=tb_file)
 
         for pattern in patterns:
+            # A[0] might be the clock which requires special sequencing
             print(
-                f'    gclk = 1; #0; A[0] = 1\'b{pattern[-1]}; #0; A = {input_width}\'b{pattern}; #5; gclk = 0; $display("%b %b", A, Y); #5',
+                f'    #0; gclk = 1; #0; A[0] = 1\'b{pattern[-1]}; #0; A = {input_width}\'b{pattern}; #5; gclk = 0; $display("%b %b", A, Y); #5',
                 file=tb_file,
             )