diff --git a/libs/librrgraph/src/io/gen/README.gen.md b/libs/librrgraph/src/io/gen/README.gen.md index 96af5520fca..e27331817ab 100644 --- a/libs/librrgraph/src/io/gen/README.gen.md +++ b/libs/librrgraph/src/io/gen/README.gen.md @@ -2,4 +2,4 @@ `rr_graph_uxsdcxx_interface.h` are generated via uxsdcxx and are checked in to avoid requiring python3 and the uxsdcxx depedencies to build VPR. -See `vpr/src/route/gen/SCHEMA_GENERATOR.md` for details. +See `$VTR_DIR/libs/librrgraph/src/base/SCHEMA_GENERATOR.md` for details. diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h index e276ba29f1a..cfb34f754ec 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: /home/talaeikh/uxsdcxx/uxsdcxx.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6 + * Cmdline: uxsdcxx/uxsdcxx.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821 */ #include @@ -247,8 +247,8 @@ constexpr const char *atok_lookup_t_segment_timing[] = {"C_per_meter", "R_per_me enum class gtok_t_segment {TIMING}; constexpr const char *gtok_lookup_t_segment[] = {"timing"}; -enum class atok_t_segment {ID, NAME, RES_TYPE}; -constexpr const char *atok_lookup_t_segment[] = {"id", "name", "res_type"}; +enum class atok_t_segment {ID, LENGTH, NAME, RES_TYPE}; +constexpr const char *atok_lookup_t_segment[] = {"id", "length", "name", "res_type"}; enum class gtok_t_segments {SEGMENT}; constexpr const char *gtok_lookup_t_segments[] = {"segment"}; @@ -792,6 +792,24 @@ inline atok_t_segment lex_attr_t_segment(const char *in, const std::function * report_error){ - std::bitset<3> astate = 0; + std::bitset<4> astate = 0; for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){ atok_t_segment in = lex_attr_t_segment(attr.name(), report_error); if(astate[(int)in] == 0) astate[(int)in] = 1; @@ -2334,6 +2352,9 @@ inline void load_segment_required_attributes(const pugi::xml_node &root, int * i case atok_t_segment::ID: *id = load_int(attr.value(), report_error); break; + case atok_t_segment::LENGTH: + /* Attribute length set after element init */ + break; case atok_t_segment::NAME: /* Attribute name set after element init */ break; @@ -2343,7 +2364,7 @@ inline void load_segment_required_attributes(const pugi::xml_node &root, int * i default: break; /* Not possible. */ } } - std::bitset<3> test_astate = astate | std::bitset<3>(0b100); + std::bitset<4> test_astate = astate | std::bitset<4>(0b1010); if(!test_astate.all()) attr_error(test_astate, atok_lookup_t_segment, report_error); } @@ -2936,6 +2957,9 @@ inline void load_segment(const pugi::xml_node &root, T &out, Context &context, c case atok_t_segment::ID: /* Attribute id is already set */ break; + case atok_t_segment::LENGTH: + out.set_segment_length(load_int(attr.value(), report_error), context); + break; case atok_t_segment::NAME: out.set_segment_name(attr.value(), context); break; @@ -4006,6 +4030,8 @@ inline void write_segments(T &in, std::ostream &os, Context &context){ auto child_context = in.get_segments_segment(i, context); os << " @@ -601,6 +601,7 @@ inline void load_segment_capnp_type(const ucap::Segment::Reader &root, T &out, C (void)report_error; (void)stack; + out.set_segment_length(root.getLength(), context); out.set_segment_name(root.getName().cStr(), context); out.set_segment_res_type(conv_enum_segment_res_type(root.getResType(), report_error), context); stack->push_back(std::make_pair("getTiming", 0)); @@ -1101,6 +1102,8 @@ inline void write_segments_capnp_type(T &in, ucap::Segments::Builder &root, Cont auto segments_segment = segments_segments[i]; auto child_context = in.get_segments_segment(i, context); segments_segment.setId(in.get_segment_id(child_context)); + if((bool)in.get_segment_length(child_context)) + segments_segment.setLength(in.get_segment_length(child_context)); segments_segment.setName(in.get_segment_name(child_context)); if((bool)in.get_segment_res_type(child_context)) segments_segment.setResType(conv_to_enum_segment_res_type(in.get_segment_res_type(child_context))); diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h index 4edff09238b..ac0e16d1418 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: /home/talaeikh/uxsdcxx/uxsdcxx.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6 + * Cmdline: uxsdcxx/uxsdcxx.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821 */ #include @@ -245,11 +245,14 @@ class RrGraphBase { * * * + * * * * */ virtual inline int get_segment_id(typename ContextTypes::SegmentReadContext &ctx) = 0; + virtual inline int get_segment_length(typename ContextTypes::SegmentReadContext &ctx) = 0; + virtual inline void set_segment_length(int length, typename ContextTypes::SegmentWriteContext &ctx) = 0; virtual inline const char * get_segment_name(typename ContextTypes::SegmentReadContext &ctx) = 0; virtual inline void set_segment_name(const char * name, typename ContextTypes::SegmentWriteContext &ctx) = 0; virtual inline enum_segment_res_type get_segment_res_type(typename ContextTypes::SegmentReadContext &ctx) = 0; diff --git a/libs/librrgraph/src/io/rr_graph.xsd b/libs/librrgraph/src/io/rr_graph.xsd index b990c488682..cea5a0f7b22 100644 --- a/libs/librrgraph/src/io/rr_graph.xsd +++ b/libs/librrgraph/src/io/rr_graph.xsd @@ -155,6 +155,7 @@ + diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 53d365b24e6..35ec9171ebb 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -1347,6 +1347,9 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { inline const char* get_segment_name(const t_segment_inf*& segment) final { return segment->name.c_str(); } + inline int get_segment_length(const t_segment_inf*& segment) final { + return segment->length; + } inline void set_segment_name(const char* name, const t_segment_inf*& segment) final { if (segment->name != name) { report_error( @@ -1354,6 +1357,13 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { segment->name.c_str(), name); } } + inline void set_segment_length(int length, const t_segment_inf*& segment) final { + if (segment->length != length) { + report_error( + "Architecture file does not match RR graph's length: arch uses %d, RR graph uses %d", + segment->length, length); + } + } inline uxsd::enum_segment_res_type get_segment_res_type(const t_segment_inf*& segment) final { return to_uxsd_segment_res_type(segment->res_type); } diff --git a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp index b8ae564a385..4ea37de3f7e 100644 --- a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp +++ b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp @@ -2,11 +2,11 @@ # https://github.com/duck2/uxsdcxx # Modify only if your build process doesn't involve regenerating this file. # -# Cmdline: /home/talaeikh/uxsdcxx/uxsdcap.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd -# Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd -# md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6 +# Cmdline: uxsdcxx/uxsdcap.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd +# Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd +# md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821 -@0xa136dd28cdc8783b; +@0xe787bf7696810419; using Cxx = import "/capnp/c++.capnp"; $Cxx.namespace("ucap"); @@ -129,9 +129,10 @@ struct SegmentTiming { struct Segment { id @0 :Int32; - name @1 :Text; - resType @2 :SegmentResType; - timing @3 :SegmentTiming; + length @1 :Int32; + name @2 :Text; + resType @3 :SegmentResType; + timing @4 :SegmentTiming; } struct Segments {