added tests

vtr_flow/parse/pass_requirements/pass_requirements_vpr_xilinx_fixed_width.txt

@@ -0,0 +1,19 @@
+# Xilinx specific requirements for VTR pass
+%include "common/pass_requirements.vpr_status.txt"
+%include "timing/pass_requirements.vpr_pack_place.txt"
+
+#Routing Metrics
+routed_wirelength;RangeAbs(0.50,1.50,5)
+
+#Area metrics
+logic_block_area_total;Range(0.5,1.6)
+logic_block_area_used;Range(0.5,1.6)
+min_chan_width_routing_area_total;Range(0.5,1.6)
+min_chan_width_routing_area_per_tile;Range(0.5,1.6)
+
+#Run-time metrics
+crit_path_route_time;RangeAbs(0.10,10.0,2)
+
+
+#Peak memory
+max_vpr_mem;RangeAbs(0.5,2.0,102400)

vtr_flow/parse/qor_config/qor_vpr_xilinx.txt

@@ -0,0 +1,12 @@
+vpr_status;output.txt;vpr_status=(.*)
+total_wirelength;vpr.out;\s*Total wirelength: (\d+)
+#total_wirelength_(mcw);vpr.out;Total wirelength:\s*(\d+)
+#total_wirelength_(1.3mcw);vpr.crit_path.out;Total wirelength:\s*(\d+)
+total_runtime;vpr.out;The entire flow of VPR took (.*) seconds
+#pack_time;vpr.out;Packing took (.*) seconds
+#place_time;vpr.out;Placement took (.*) seconds
+#route_time;vpr.out;Routing took (.*) seconds
+#num_pre_packed_nets;vpr.out;Total Nets: (\d+)
+#num_post_packed_nets;vpr.out;Netlist num_nets:\s*(\d+)
+crit_path_delay;vpr.crit_path.out;Final critical path: (.*) ns
+

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/config.txt

@@ -0,0 +1,34 @@
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of architectures to use
+archs_dir=arch/xilinx
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/verilog
+
+# Add architectures to list
+arch_list_add=7series_BRAM_DSP_carry.xml
+
+# Add circuits to list to sweep
+circuit_list_add=LU32PEEng.v
+circuit_list_add=LU8PEEng.v
+circuit_list_add=bgm.v
+circuit_list_add=stereovision0.v
+circuit_list_add=stereovision1.v
+circuit_list_add=stereovision2.v
+
+# Parse info and how to parse
+parse_file=vpr_standard.txt
+
+# How to parse QoR info
+qor_parse_file=qor_vpr_xilinx.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements_vpr_xilinx_fixed_width.txt
+
+# Xilinx Benchmarks route at the physical channel 
+# width of the chip which is 190. Flat routing is
+# also enabled.
+script_params=--route_chan_width 190 --flat_routing on