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ALU_map.mrp
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Release 14.7 Map P.20131013 (nt64)
Xilinx Mapping Report File for Design 'ALU'
Design Information
------------------
Command Line : map -intstyle ise -p xc7a100t-csg324-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off
-power off -o ALU_map.ncd ALU.ngd ALU.pcf
Target Device : xc7a100t
Target Package : csg324
Target Speed : -3
Mapper Version : artix7 -- $Revision: 1.55 $
Mapped Date : Sat Oct 29 12:18:35 2016
Design Summary
--------------
Number of errors: 0
Number of warnings: 46
Slice Logic Utilization:
Number of Slice Registers: 0 out of 126,800 0%
Number of Slice LUTs: 198 out of 63,400 1%
Number used as logic: 198 out of 63,400 1%
Number using O6 output only: 184
Number using O5 output only: 0
Number using O5 and O6: 14
Number used as ROM: 0
Number used as Memory: 0 out of 19,000 0%
Number used exclusively as route-thrus: 0
Slice Logic Distribution:
Number of occupied Slices: 69 out of 15,850 1%
Number of LUT Flip Flop pairs used: 198
Number with an unused Flip Flop: 198 out of 198 100%
Number with an unused LUT: 0 out of 198 0%
Number of fully used LUT-FF pairs: 0 out of 198 0%
Number of slice register sites lost
to control set restrictions: 0 out of 126,800 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 44 out of 210 20%
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 0 out of 135 0%
Number of RAMB18E1/FIFO18E1s: 0 out of 270 0%
Number of BUFG/BUFGCTRLs: 0 out of 32 0%
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 300 0%
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 0 out of 300 0%
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 300 0%
Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 24 0%
Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 24 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHCEs: 0 out of 96 0%
Number of BUFRs: 0 out of 24 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 0 out of 240 0%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of IBUFDS_GTE2s: 0 out of 4 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 0 out of 6 0%
Number of IN_FIFOs: 0 out of 24 0%
Number of MMCME2_ADVs: 0 out of 6 0%
Number of OUT_FIFOs: 0 out of 24 0%
Number of PCIE_2_1s: 0 out of 1 0%
Number of PHASER_REFs: 0 out of 6 0%
Number of PHY_CONTROLs: 0 out of 6 0%
Number of PLLE2_ADVs: 0 out of 6 0%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.87
Peak Memory Usage: 801 MB
Total REAL time to MAP completion: 48 secs
Total CPU time to MAP completion: 36 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:LIT:701 - PAD symbol "intop1<7>" has an undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "intop1<7>" is not constrained (LOC) to a specific
location.
WARNING:PhysDesignRules:2452 - The IOB intop1<0> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop1<6> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop1<5> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop1<7> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB carry is either not constrained (LOC) to
a specific location and/or has an undefined I/O Standard (IOSTANDARD). This
condition may seriously affect the device and will be an error in bitstream
creation. It should be corrected by properly specifying the pin location and
I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB opcode<1> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB opcode<0> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop2<2> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop2<1> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop2<4> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop2<3> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop2<0> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop2<6> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop2<5> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop2<7> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<15> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<10> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB result<5> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<14> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB result<6> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<13> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB result<7> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<12> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<11> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB result<1> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB result<2> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB result<3> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB result<4> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB result<0> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB overflow is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<2> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<1> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<4> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<3> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<0> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<9> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<6> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<5> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<8> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB product<7> is either not constrained
(LOC) to a specific location and/or has an undefined I/O Standard
(IOSTANDARD). This condition may seriously affect the device and will be an
error in bitstream creation. It should be corrected by properly specifying
the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop1<2> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop1<1> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop1<4> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB intop1<3> is either not constrained (LOC)
to a specific location and/or has an undefined I/O Standard (IOSTANDARD).
This condition may seriously affect the device and will be an error in
bitstream creation. It should be corrected by properly specifying the pin
location and I/O Standard.
Section 3 - Informational
-------------------------
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to
1.050 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| carry | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| intop1<0> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop1<1> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop1<2> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop1<3> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop1<4> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop1<5> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop1<6> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop1<7> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop2<0> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop2<1> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop2<2> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop2<3> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop2<4> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop2<5> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop2<6> | IOB | INPUT | LVCMOS18 | | | | | | |
| intop2<7> | IOB | INPUT | LVCMOS18 | | | | | | |
| opcode<0> | IOB | INPUT | LVCMOS18 | | | | | | |
| opcode<1> | IOB | INPUT | LVCMOS18 | | | | | | |
| overflow | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<0> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<1> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<2> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<3> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<4> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<5> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<6> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<7> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<8> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<9> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<10> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<11> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<12> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<13> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<14> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| product<15> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| result<0> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| result<1> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| result<2> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| result<3> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| result<4> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| result<5> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| result<6> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| result<7> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.