final_test_beh.prj

verilog work "fulladder.v"
verilog work "booth_step_mult.v"
verilog work "xor8bit.v"
verilog work "ripple8bit.v"
verilog work "mult8bit.v"
verilog work "and8bit.v"
verilog work "ALU.v"
verilog work "register_file.v"
verilog work "final_test.v"
verilog work "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"