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Level-1 Design-1

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Bugs

1. Select Case 5'b01100 is misssing

Case 5'b01100 is not present due to which outpin for case 5'b01100 takes default value.

Python Test and Terminal Bug in verilog

Bug Screenshot with Python test

2. Select Case 5'b01101 is Unreachable

Case 5'b01101 is appeared twice for inp12 and inp13, due to this inp13 is unreachable. Beacuse the first case which match with 5'b01101 is assigned for output i.e. inp12

Python Test and Terminal Bug in verilog

Bug Screenshot with Python test

3. Select Case 5'b01110 is misssing

Case 5'b01110 is not present due to which outpin for case 5'b01110 takes default value.

Python Test and Terminal Bug in verilog

Bug Screenshot with Python test