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README.md

Level-1 Design-2

Note - For Better Experience click on image

Bugs

0. Without Overlapping Basic Sequence 1011

The Verilog Code works well without overlapping sequence. When overlapping sequence occurs, verilog code fails to detect the sequence in particular cases

1. State SEQ_1

When bit 1 is arrived on SEQ_1 then State SEQ_1 is reseting the state, Due to which Overlapping sequence is not detected.
SEQ_1 -> 1 -> SEQ_1 (Remain on current state only)
Bug Detected Bug Fixed

2. State SEQ_101

When bit 0 is arrived on SEQ_101 then State SEQ_101 is reseting the state to IDLE state, Due to which Overlapping sequence is not detected.
SEQ_101 -> 0 -> SEQ_10
Bug Detected Bug Fixed

3. State SEQ_1011

When bit 0 or 1 is arrived on SEQ_1011 then State SEQ_1011 is reseting the state to IDLE state, Due to which Overlapping sequence is not detected.
SEQ_1011 -> 0 -> SEQ_10
SEQ_1011 -> 1 -> SEQ_1
Bug Detected Bug Fixed