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WS2812Driver.qsf
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WS2812Driver.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
# Date created = 13:57:47 November 16, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# WS2812Driver_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSXFC6D6F31C6
set_global_assignment -name TOP_LEVEL_ENTITY WS2812Driver
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:57:47 NOVEMBER 16, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name VHDL_FILE WS2812.vhd
set_global_assignment -name VHDL_FILE WS2812Driver.vhd
set_location_assignment PIN_AA24 -to fpga_led_pio[0]
set_location_assignment PIN_AC22 -to fpga_led_pio[9]
set_location_assignment PIN_AB23 -to fpga_led_pio[1]
set_location_assignment PIN_AF14 -to fpga_clk_50
set_location_assignment PIN_AB22 -to fpga_led_pio[8]
set_location_assignment PIN_AF24 -to fpga_led_pio[7]
set_location_assignment PIN_AE24 -to fpga_led_pio[6]
set_location_assignment PIN_AF25 -to fpga_led_pio[5]
set_location_assignment PIN_AG25 -to fpga_led_pio[4]
set_location_assignment PIN_AD24 -to fpga_led_pio[3]
set_location_assignment PIN_AC23 -to fpga_led_pio[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_clk_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_data_out
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led_pio[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led_pio[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led_pio[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led_pio[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led_pio[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led_pio[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led_pio[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led_pio[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led_pio[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_led_pio[0]
set_location_assignment PIN_W15 -to fpga_data_out
set_global_assignment -name SDC_FILE WS2812Driver.sdc
set_global_assignment -name QIP_FILE pll.qip
set_global_assignment -name SIP_FILE pll.sip
set_global_assignment -name MIF_FILE WS2812Driver.mif
set_global_assignment -name QIP_FILE vram.qip
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top