After convertion using vcd2fsdb, the width of regs are not shown explictly.

[stephen0921]

Hi all,

I have used pyvcd in my env. It is very excellent.
Verdi is my waveform tool. So I have to change vcd file to fsdb file. After convertion, in the waveform, the regs for example "a[7:0]" are shown "a". I have to click on "a" to show its width.

I found that the code "var_str = '$var {var_type} {size} {ident} {name} $end'.format(var_type=var_type, size=var_size, ident=ident, name=name)" in "def register_var" of writer if be changed to '$var {var_type} {size} {ident} {name} [h_pos:l_pos] $end'.format(var_type=var_type, size=var_size, ident=ident, name=name, h_pos=h_pos, l_pos=l_pos)" can meet my demand.

Can I change the code?

[jpgrayson]

I'm glad pyvcd is working for you! And thank you for identifying this issue.

The name parameter to register_var() corresponds to the "reference" in the IEEE 1364-2005 specification (see BNF below). There are three different ways that the reference can be spelled. Pyvcd currently orients to the first spelling where just an identifier is used.

vcd_declaration_vars ::=
    $var var_type size identifier_code reference $end
var_type ::=
    event | integer | parameter | real | realtime | reg | supply0 | supply1 | time
    | tri | triand | trior | trireg | tri0 | tri1 | wand | wire | wor
size ::=
    decimal_number
reference ::=
      identifier
    | identifier [ bit_select_index ]
    | identifier [ msb_index : lsb_index ]
index ::=
    decimal_number

Without any change to pyvcd, I believe it would be possible to pass a name string with the bit selection embedded. For example:

writer.register_var('x.y', 'a [ 7 : 0 ]', ...)
writer.register_var('x.y', 'b [ 3 ]', ...)

It is perhaps worth trying that in your application.

However, even if that works, it may be preferable to add an optional bit_select parameter. I'm imagining this bit_select parameter could be either None (the default), an int, or a 2-tuple of int. The above examples would thus become:

writer.register_var('x.y', 'a', bit_select=(7, 0), ...)
writer.register_var('x.y', 'b', bit_select=3, ...)

In my primary pyvcd application, I do not use bit selections. I am interested in your thoughts on these various options for supporting bit selections in variable declarations.

[stephen0921]

Thank you for your immediate reply. I will give it a try.

[stephen0921]

It works as what you said.
I think the bit_select option is not needed as long as readme.md show how to use it in this situation.
Great job!
This is my project based on yours.
gen_wave
I think I should update my readme file in it. So someone can understand what is used for.