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Use FPGAs inside other FPGAs #25

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chexo3 opened this issue Jun 4, 2022 · 1 comment
Open

Use FPGAs inside other FPGAs #25

chexo3 opened this issue Jun 4, 2022 · 1 comment

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@chexo3
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chexo3 commented Jun 4, 2022

Not sure if this is already possible. Basically, it'd be nice to be able to turn my FPGAs into gates to be used inside other FPGAs. There may be specific considerations for this, so for sub-gates may have to share the execution speed of the gate they're a part of, or trigger when inputs change.

One simple example I can think of for something I would use with this, is a clamped increment/decrement gate.

Inputs
A
Increment
Decrement
Min
Max
Reset

Outputs
Out

It may also be useful to have non-changing inputs. If you've ever done shader programming, it's the difference between a varying and a uniform, or a static variable in many other languages. Basically, these inputs would be set when the gate is created, rather than being able to change. This is convenient for setting stuff up, no messing with constant values.

As individual gates in the world, this would be set up with a menu in the FPGA spawner menu, generated from the inputs. In the node editor, you'd set these values by editing the node. And you can also set them to mock/dummy values within the editor for that node itself, so while you're designing a new gate, you can test it with different inputs. Mock/dummy values should also be useable for inputs that change during execution.

It may also be useful to design test suites for gates, similar to tests for higher level programming. Basically, a test is a truth table, with a given input and an expected output. And it should be able to test in multiple ticks, so that you can test that a gate doesn't have unintended side effects. For instance an increment/decrement system in a gate should be affected by the previous value, but another gate shouldn't remember what happened in previous ticks, maybe.

@VirgilCore
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I know this post is old, and the addon doesn't seem to be in active development, but I have a feeling that having nested FPGAs could cause a performance hit. As much as I agree of its usefulness.

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