RZ/G3S board Release v1.02 #101
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Add job for building relese notes pdf in CI Signed-off-by: Dmytro Semenets <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
During early boot PRE_KERNEL_1 the SysTick driver is not ready yet, which causes k_busy_wait() to stuck. Fix it by switching to simple loop. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Update RZ G2S SoC series defconfig such way that configs SYS_CLOCK_HW_CYCLES_PER_SEC FLASH_SIZE FLASH_BASE_ADDRESS are retrieved from DT. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Update RZ G3S DT for miniaml boot supporting. - add cpu 'clock-frequency' - add DT node for internal SRAM to place Zephyr binary. Zephyr binary has to plased starting from address 0x23000 as specified by ATF-A for this SoC. The IRQ vector tables placed starting from this address. The current target is to boot Core-A first which then loads Zephyr on Cortex-M33 core. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Update RZ/G3S SMARC Evaluation Board Kit defconfig for minimal Zephyr boot support through JLink debugger. Tested with "hello_world" sample application which can reach main()/idle. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Update board doc. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
RZ/G3S board has SEGGER J-Link on board. Add configuration files to flash and debug the board using west standart tools. Signed-off-by: Dmytro Semenets <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Add Renesas RZ G3S bindings. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Add Renesas RZ G3S pin-controller node and enable pinctrl nodes in board files for rz_g3s platform. Add scif0, scif1 and scif3 pinmux nodes for now. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Add pinctrl driver for Renesas RZ G3S SoC series. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Enable CONFIG_PINCTRL for Renesas rz_g3s platform Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Add skeleton for RZ/G3S documentation to add Supported Features detailed information which will include supported Driver overview and test cases that can be used to test supported functionality Signed-off-by: Oleksii Moisieiev <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Use clocks by name in uart_scif driver. Signed-off-by: Dmytro Semenets <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Adaptation scif driver for RZ/G3S. Signed-off-by: Dmytro Semenets <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Add nodes for scif on secure address space. Signed-off-by: Dmytro Semenets <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Add scif1 device as default as Zephyr console. Signed-off-by: Dmytro Semenets <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
The RZ G3S CPG reset controller driver was originally the part of the RZ G3S clock controller driver, but this makes Zephyr build system unhappy. Hence, there are no reasons to keep CPG reset and clock control functionality in the same driver, this patch adds standalone RZ G3S CPG reset controller bindings and DT nodes. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by Vitalii Livnov <[email protected]> Acked-by: Dmytro Semenets <[email protected]>
The RZ G3S CPG reset controller driver was originally the part of the RZ G3S clock controller driver, but this makes Zephyr build system unhappy. Hence, there are no reasons to keep CPG reset and clock control functionality in the same driver, this patch adds standalone RZ G3S CPG reset controller driver by moving CPG Reset control code out of the RZ G3S clock controller driver. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by Vitalii Livnov <[email protected]> Acked-by: Dmytro Semenets <[email protected]>
Add DT bindings for Renesas RZ G3S SoC GPIO controller. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Add RZ G3S GPIO DT nodes. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Add Renesas RZ G3S GPIO driver. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Enable GPIO for rz_g3s board. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
The Renesas RZ/G3S SMARC Evaluation Board Kit has 3 user buttons installed SW1 : P18_0 SW2 : P0_1 SW3 : P0_3 P18_0 pin routing depends on GPIO4_SEL switch. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Enable gpio_basic_api test for rz_g3s board. For this test to work following hw pin connection has to be done: connector PMOD1 - Type-3A pin9:PMOD1_GPIO12:P8_2 - out-gpios - to - pin10:PMOD1_GPIO13:P8_3 - in-gpios Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
Add initial GPIO doc with test results. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]>
DT bindings adaptation for Renesas RZ/G3S SPI Interface. Signed-off-by: Vitalii Livnov <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Add SPI DT nodes for RZ/G3S SoC. Signed-off-by: Vitalii Livnov <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Add basic SPI support to RZ SMARC Series Carrier Board II. RSPI0:SPI1: routed to PMOD0 - Type-2A conector. Signed-off-by: Vitalii Livnov <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Adaptation SPI driver source code for RZ/G3S Signed-off-by: Vitalii Livnov <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Enable spi_loopback test for RZ/G3S board. The DMA and SPI ASYNC API related tests are disabled for now. Will be enabled after DMA support implementing. Signed-off-by: Vitalii Livnov <[email protected]> Reviewed-by: Oleksii Moisieiev <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Set the correct configuration of the SW_OPT_MUX in the Release Notes. SW_OPT_MUX[1] shoudl be OFF to make SD card work from u-boot. According to the documentation when SW_OPT_MUX[1] is OFF the SMARC SDIO signals are routed to the uSD on the Carrier. Signed-off-by: Oleksii Moisieiev <[email protected]> Reviewed-by: Dmytro Semenets <[email protected]>
Add support for HW test loopback mode for Renesas SCIF driver. The test loopback can be enabled in DT by using "renesas,loopback" property. It's enabled for the RZ G3S "uart_async_api" test. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Dmytro Semenets <[email protected]> Acked-by: Oleksii Moisieiev <[email protected]>
The CONFIG_BOARD_RZ_G3S is defined for non-fpu platform only, so use CONFIG_SOC_SERIES_RZ_G instead. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Dmytro Semenets <[email protected]> Acked-by: Oleksii Moisieiev <[email protected]>
The async test is running in loopback mode now, so update the uart/scif doc. Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Dmytro Semenets <[email protected]> Acked-by: Oleksii Moisieiev <[email protected]>
Updating the Release Notes to v1.0. Signed-off-by: Oleksii Moisieiev <[email protected]>
Update documentation with tips for flashing to board. Signed-off-by: Dmytro Semenets <[email protected]>
Add snippet for use i2c with dma on rz_g3s Signed-off-by: Dmytro Semenets <[email protected]> Acked-by: Oleksii Moisieiev <[email protected]>
Add overlay for rz_g3s_fpu (Cortex-M33 with FPU) board Signed-off-by: Dmytro Semenets <[email protected]> Acked-by: Oleksii Moisieiev <[email protected]>
Fixes for support dma mode for rg_g3s Signed-off-by: Dmytro Semenets <[email protected]> Acked-by: Oleksii Moisieiev <[email protected]>
Add DMA support description to I2C chaprer Signed-off-by: Dmytro Semenets <[email protected]> Acked-by: Oleksii Moisieiev <[email protected]>
Add rz_g3s_fpu overlay to the spi_loopback test. Signed-off-by: Oleksii Moisieiev <[email protected]> Acked-by: Dmytro Semenets <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Add rz_g3s_fpu overlay to start test on CM33_FPU core. Signed-off-by: Oleksii Moisieiev <[email protected]> Acked-by: Dmytro Semenets <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Add rz_g3s_fpu overlay to start test on the CM33_FPU core. Signed-off-by: Oleksii Moisieiev <[email protected]> Acked-by: Dmytro Semenets <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Add support for CM33_FPU core to start adc_api test. Signed-off-by: Oleksii Moisieiev <[email protected]> Acked-by: Dmytro Semenets <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Add overlay for rz_g3s_fpu core. Signed-off-by: Oleksii Moisieiev <[email protected]> Acked-by: Dmytro Semenets <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Introducing rz-g3s-fpu_scif1 snippet which was designed to switch CM33_FPU core to scif1 from scif3. That's needed for the testing purposes because scif3 works on 1.8v which is uncommon to USBUART connectors. Signed-off-by: Oleksii Moisieiev <[email protected]> Acked-by: Dmytro Semenets <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Add documentation about how Cortex-M33 core can be configured to use SCIF3(PMOD) as console. Signed-off-by: Oleksii Moisieiev <[email protected]> Acked-by: Dmytro Semenets <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
Put correct sample name to the release notes. Signed-off-by: Oleksii Moisieiev <[email protected]>
Add SD card connection schema to the Release Notes. Signed-off-by: Oleksii Moisieiev <[email protected]>
For Cortex-M33_FPU core the connection schema is different. Added note that indicates that. Signed-off-by: Oleksii Moisieiev <[email protected]>
Add note about input from console to uart_basic_api. Signed-off-by: Oleksii Moisieiev <[email protected]>
Fixed typo in fpu_snippet documentation file. Signed-off-by: Oleksii Moisieiev <[email protected]>
Fixed warnings appears during the Release Notes pdf generation. Signed-off-by: Oleksii Moisieiev <[email protected]>
Update Release information to v1.0.1. Signed-off-by: Oleksii Moisieiev <[email protected]>
Add a picture that shows jumper settings of the USB-Serial connector for CM33_FPU console. Signed-off-by: Oleksii Moisieiev <[email protected]>
Add rz_g3s_fpu overlay dts file to support irq_keys sample on CM33_FPU core. Signed-off-by: Oleksii Moisieiev <[email protected]>
WAIT flag should be set on riic_dma_read start to wait for the Read operation after each transfer. This is necessary to avoid receiving garbage in the last bytes. I2C controller will automatically low-hold clock after each receiving operation to prevent receive failures. Also there is no need to call dma_stop directly after transmission, because DMA is already stopped after receiving all data chunk. Signed-off-by: Dmytro Semenets <[email protected]> Signed-off-by: Oleksii Moisieiev <[email protected]>
Update release to v1.0.2. Signed-off-by: Oleksii Moisieiev <[email protected]>
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Uploading RZ/G3S core to release v1.0.2