RZ/G3S board Release v1.02

.gitlab-ci.yml

@@ -1,12 +1,17 @@
 stages:
   - compliance
   - guidlines
+  - doc
+  - twister-build
+
+variables:
+  BOARD: rz_g3s
 
 comliance-job:
   stage: compliance
   script:
     - echo "Starting compliance check"
-    - cd /builds/rec-rzzp
+    - cd /builds/${CI_PROJECT_NAMESPACE}
     - west init -l zephyr > /dev/null 2>&1 || true
     - cd zephyr
     # WA to skip undef config checks because it fails with errors about
@@ -15,16 +20,47 @@ comliance-job:
     - sed -i "s/self.check_no_undef_outside_kconfig(kconf)/print(\"skip\")/g"
       ./scripts/ci/check_compliance.py
     - export ZEPHYR_BASE=$PWD
-    - ./scripts/ci/check_compliance.py --annotate -e KconfigBasic -c ${CI_DEFAULT_BRANCH}..
+    - ./scripts/ci/check_compliance.py --annotate -e KconfigBasic -c origin/${CI_DEFAULT_BRANCH}..
 
 guidlines-job:
   stage: guidlines
   script:
     - echo "Starting guidlines check"
-    - cd /builds/rec-rzzp
+    - cd /builds/${CI_PROJECT_NAMESPACE}
     - west init -l zephyr > /dev/null 2>&1 || true
     - cd ./zephyr
     - source zephyr-env.sh
-    - export ZEPHYR_BASE=/builds/rec-rzzp/zephyr
-    - ./scripts/ci/guideline_check.py --output output.txt -c ${CI_DEFAULT_BRANCH}.. ||
+    - export ZEPHYR_BASE=/builds/${CI_PROJECT_NAMESPACE}/zephyr
+    - ./scripts/ci/guideline_check.py --output output.txt -c origin/${CI_DEFAULT_BRANCH}.. ||
       cat ./output.txt
+
+doc-job:
+  stage: doc
+  script:
+    - echo "Generating release notes"
+    - cd /builds/${CI_PROJECT_NAMESPACE}
+    - west init -l zephyr > /dev/null 2>&1 || true
+    - cd ./zephyr
+    - source zephyr-env.sh
+    - export ZEPHYR_BASE=/builds/${CI_PROJECT_NAMESPACE}/zephyr
+    - west build -b ${BOARD} -t doc samples/basic/hash_map
+  artifacts:
+    paths:
+      - /builds/${CI_PROJECT_NAMESPACE}/zephyr/build/zephyr/rzg3s_release_notes.pdf
+
+twister-build-job:
+  stage: twister-build
+  when: manual
+  script:
+    - echo "Twister check"
+    - cd /builds/${CI_PROJECT_NAMESPACE}
+    - west init -l zephyr > /dev/null 2>&1 || true
+    - cd ./zephyr
+    - source zephyr-env.sh
+    - export ZEPHYR_BASE=/builds/${CI_PROJECT_NAMESPACE}/zephyr
+    - scripts/twister -p ${BOARD} --enable-slow
+  artifacts:
+    paths:
+      - twister-out/twister_report.xml
+      - twister-out/twister.xml
+      - twister-out/twister.json

arch/arm/Kconfig

@@ -16,10 +16,9 @@ config CPU_CORTEX
 
 config ARM_CUSTOM_INTERRUPT_CONTROLLER
 	bool
-	depends on !CPU_CORTEX_M
 	help
 	  This option indicates that the ARM CPU is connected to a custom (i.e.
-	  non-GIC) interrupt controller.
+	  non-GIC, NVIC) interrupt controller or required MULTI_LEVEL_INTERRUPTS support.
 
 	  A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
 	  allow interfacing to a custom external interrupt controller and this
@@ -30,9 +29,10 @@ config ARM_CUSTOM_INTERRUPT_CONTROLLER
 	  functions are mapped to the SoC interrupt control interface, which is
 	  implemented at the SoC level.
 
-	  N.B. This option is only applicable to the Cortex-A and Cortex-R
-	       family cores. The Cortex-M family cores are always equipped with
-	       the ARM Nested Vectored Interrupt Controller (NVIC).
+	  For MULTI_LEVEL_INTERRUPTS support the architecture interrupt control
+	  functions also has to be mapped to the SoC interrupt control interface to
+	  perform proper interrupt control calls dispatch to the irq_nextlevel or
+	  ARCH IRQ control API.
 
 config CODE_DATA_RELOCATION_SRAM
 	bool "Relocate code/data sections to SRAM"

arch/arm/core/cortex_m/irq_manage.c

@@ -28,6 +28,8 @@
 
 extern void z_arm_reserved(void);
 
+#if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
+
 #define NUM_IRQS_PER_REG 32
 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
 #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)
@@ -89,6 +91,7 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
 	NVIC_SetPriority((IRQn_Type)irq, prio);
 }
+#endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
 
 void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf);
 

arch/arm/core/mpu/arm_mpu.c

@@ -469,8 +469,10 @@ int z_arm_mpu_init(void)
 	 * dereferencing detection (debug feature)
 	 */
 #if defined(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_MPU)
+
 #if (defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)) && \
-	(CONFIG_FLASH_BASE_ADDRESS > CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE)
+	(CONFIG_FLASH_BASE_ADDRESS > CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE) && \
+	!defined(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_MPU_RZ_G)
 #pragma message "Null-Pointer exception detection cannot be configured on un-mapped flash areas"
 #else
 	const struct z_arm_mpu_partition unmap_region =	{

boards/arm/rz_a2m/board.cmake

@@ -2,3 +2,9 @@
 
 board_runner_args(jlink "--device=R7S921053VCBG" "--speed=15000")
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+
+set(RELEASE_NOTES_SRC rza2m_release_notes.tex)
+add_custom_target(doc
+    WORKING_DIRECTORY ${ZEPHYR_BASE}/boards/${ARCH}/${BOARD}/release_notes
+    COMMAND pdflatex -output-directory=${ZEPHYR_BINARY_DIR} ${RELEASE_NOTES_SRC}
+)

boards/arm/rz_a2m/rz_a2m.dts

@@ -132,6 +132,7 @@
 };
 
 &ostm1 {
+	compatible = "renesas,ostm-timer";
 	status = "okay";
 };
 

boards/arm/rz_a2m/rz_a2m_defconfig

@@ -31,6 +31,3 @@ CONFIG_CACHE_MANAGEMENT=y
 
 # Enable BSC
 CONFIG_BSC=y
-
-# Enable RSPI
-CONFIG_SPI_RZA2M=y

boards/arm/rz_g3s/Kconfig.board

@@ -0,0 +1,11 @@
+# Copyright (c) 2024 EPAM Systems
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RZ_G3S
+	bool "Cortex-M33 for Renesas RZ G3S"
+	depends on SOC_R9A08G045
+
+config BOARD_RZ_G3S_FPU
+	bool "Cortex-M33 with FPU for Renesas RZ G3S"
+	select CPU_HAS_FPU
+	depends on SOC_R9A08G045

boards/arm/rz_g3s/Kconfig.defconfig

@@ -0,0 +1,19 @@
+# Copyright (c) 2024 EPAM Systems
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_RZ_G3S
+config BOARD
+	default "rz_g3s"
+
+endif # BOARD_RZ_G3S
+
+if BOARD_RZ_G3S_FPU
+config BOARD
+	default "rz_g3s_fpu"
+
+config FPU
+	default y
+
+config FPU_SHARING
+	default y
+endif # BOARD_RZ_G3S_FPU

boards/arm/rz_g3s/board.cmake

@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if (CONFIG_BOARD_RZ_G3S_FPU)
+	board_runner_args(jlink "--device=R9A08G045S33_M33_1" "--speed=15000")
+else ()
+	board_runner_args(jlink "--device=R9A08G045S33_M33_0" "--speed=15000")
+endif ()
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+
+set(RELEASE_NOTES_SRC .)
+set(RELEASE_NOTES_OUT rzg3s_release_notes.pdf)
+
+set(KERNEL_SREC_NAME   ${KERNEL_NAME}.srec)
+
+add_custom_target(doc
+    WORKING_DIRECTORY ${ZEPHYR_BASE}/boards/${ARCH}/${BOARD}/doc
+    COMMAND sphinx-build -M latexpdf ${RELEASE_NOTES_SRC} ${ZEPHYR_BINARY_DIR}
+    COMMAND cp ${ZEPHYR_BINARY_DIR}/latex/rzg3s_release_notes.pdf  ${ZEPHYR_BINARY_DIR}/${RELEASE_NOTES_OUT}
+    COMMAND rm -Rf ${ZEPHYR_BINARY_DIR}/latex
+    COMMAND rm -Rf ${ZEPHYR_BINARY_DIR}/doctrees
+)
+
+set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+    COMMAND ${CMAKE_OBJCOPY} -I binary -O srec --srec-forceS --adjust-vma 0x23000 ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.bin ${ZEPHYR_BINARY_DIR}/${KERNEL_SREC_NAME}
+)

boards/arm/rz_g3s/doc/_extensions/zephyr/__init__.py

@@ -0,0 +1,4 @@
+# Copyright (c) 2021 Zephyr Project members and individual contributors
+# SPDX-License-Identifier: Apache-2.0
+
+# File intentionally empty