From d573fb9e332e0ccf873ee85fd569f4517f18f031 Mon Sep 17 00:00:00 2001
From: xinhecuican <lizilin268646@gmail.com>
Date: Fri, 3 Jan 2025 10:56:18 +0800
Subject: [PATCH 1/3] chore: append perf counters

---
 src/core/backend/issue/CsrIssueQueue.sv   |   2 +
 src/core/backend/lsu/dcache/DCacheMiss.sv |   1 +
 src/core/frontend/BranchPredictor.sv      |  14 +-
 src/core/frontend/FSQ.sv                  |   9 +-
 src/core/frontend/HistoryControl.sv       |  28 ++-
 src/core/frontend/RAS.sv                  | 230 +---------------------
 src/core/frontend/UBTB.sv                 |   2 +
 src/core/mmu/PTW.sv                       |   2 +
 src/defines/arch.svh                      |   1 -
 src/defines/bundles.svh                   |  15 +-
 src/defines/global.svh                    |   5 +-
 11 files changed, 58 insertions(+), 251 deletions(-)

diff --git a/src/core/backend/issue/CsrIssueQueue.sv b/src/core/backend/issue/CsrIssueQueue.sv
index f36b503..c49a88b 100644
--- a/src/core/backend/issue/CsrIssueQueue.sv
+++ b/src/core/backend/issue/CsrIssueQueue.sv
@@ -329,4 +329,6 @@ generate
         end
     end
 endgenerate
+
+    `PERF(redirect_fence, fenceBus.fence_end)
 endmodule
\ No newline at end of file
diff --git a/src/core/backend/lsu/dcache/DCacheMiss.sv b/src/core/backend/lsu/dcache/DCacheMiss.sv
index 2ff9567..99607ff 100644
--- a/src/core/backend/lsu/dcache/DCacheMiss.sv
+++ b/src/core/backend/lsu/dcache/DCacheMiss.sv
@@ -474,5 +474,6 @@ endgenerate
     assign r_axi_io.r_ready = 1'b1;
 
     `PERF(load_miss, rlast & (|mshr_hit_combine))
+    `PERF(dcache_miss, r_axi_io.ar_valid & r_axi_io.ar_ready)
 
 endmodule
\ No newline at end of file
diff --git a/src/core/frontend/BranchPredictor.sv b/src/core/frontend/BranchPredictor.sv
index 76ac357..f0e0209 100644
--- a/src/core/frontend/BranchPredictor.sv
+++ b/src/core/frontend/BranchPredictor.sv
@@ -30,6 +30,7 @@ module BranchPredictor(
     RasRedirectInfo ras_info_s3;
     logic ras_valid_s2, ras_valid_s3_in, ras_valid_s3_out;
     BTBUpdateInfo entry_s2;
+    logic `N(`SLOT_NUM) tage_pred_s3;
 
     assign squash = bpu_fsq_io.squash;
     assign squashInfo = bpu_fsq_io.squashInfo;
@@ -40,10 +41,12 @@ module BranchPredictor(
     BTB btb(.*);
     assign tage_io.pc = pc;
     Tage tage(.*);
+`ifdef FEAT_SC
     assign sc_io.pc = pc;
     assign sc_io.tage_prediction = tage_io.prediction;
     assign sc_io.tage_ctrs = tage_io.provider_ctr;
     SC sc(.*, .io(sc_io));
+`endif
     assign ittage_io.pc = pc;
 `ifdef FEAT_ITTAGE_REGION
     assign ittage_io.region_idx = entry_s2.tailSlot.target[`ITTAGE_REGION_WIDTH-1: 0];
@@ -77,11 +80,7 @@ module BranchPredictor(
     assign ras_io.lastStage = s3_result_out.en  & ~redirect.flush;
     assign ras_io.lastStageIdx = s3_result_out.stream_idx;
 `endif
-`ifdef FEAT_LINKRAS
-    LinkRAS ras(.*);
-`else
     RAS ras(.*);
-`endif
     
     assign redirect.s2_redirect = s2_result_out.en && s2_result_out.redirect;
     assign redirect.s3_redirect = s3_result_out.en && s3_result_out.redirect;
@@ -132,6 +131,7 @@ module BranchPredictor(
         end
         ras_addr_s3 <= ras_io.entry.pc;
         ras_info_s3 <= ras_io.rasInfo;
+        tage_pred_s3 <= tage_io.prediction;
     end
 
     assign bpu_fsq_io.en = bpu_fsq_io.prediction.en & ~redirect.flush;
@@ -185,13 +185,19 @@ module BranchPredictor(
         s2_meta_out = s2_meta_in;
         s2_meta_out.tage = tage_io.meta;
         s3_meta_out = s3_meta_in;
+`ifdef FEAT_SC
         s3_meta_out.sc = sc_io.meta;
+`endif
         s3_meta_out.ittage = ittage_io.meta;
     end
 
     S3Control s3_control(
         .pc(s3_result_in.stream.start_addr),
+`ifdef FEAT_SC
         .prediction(sc_io.prediction),
+`else
+        .prediction(tage_pred_s3),
+`endif
         .ras_addr(ras_addr_s3),
         .ind_addr(ittage_io.target),
         .ras_info(ras_info_s3),
diff --git a/src/core/frontend/FSQ.sv b/src/core/frontend/FSQ.sv
index daa8f7a..bbb4b7a 100644
--- a/src/core/frontend/FSQ.sv
+++ b/src/core/frontend/FSQ.sv
@@ -605,7 +605,7 @@ endgenerate
         update_tail_taken <= pred_error ? (commitWBInfo.br_type != CONDITION) & ~commitWBInfo.exception :
                             ~(|u_predInfo.condHist) & commitStream.taken;
         update_indirect <= pred_error ? commitWBInfo.br_type == INDIRECT || commitWBInfo.br_type == INDIRECT_CALL : 
-                            ~(|u_predInfo.condHist) & commitStream.taken & (oldEntry.tailSlot.br_type == INDIRECT) | (oldEntry.tailSlot.br_type == INDIRECT_CALL);
+                            ~(|u_predInfo.condHist) & commitStream.taken & ((oldEntry.tailSlot.br_type == INDIRECT) | (oldEntry.tailSlot.br_type == INDIRECT_CALL));
     end
     always_comb begin
         update_btb_entry = update_btb_entry_pre;
@@ -616,7 +616,7 @@ endgenerate
 `endif
     end
 
-    logic `N(`FSQ_WIDTH) exception_head, exception_head_n;
+    logic `N(`FSQ_WIDTH) exception_head, exception_head_n, exception_head_pre;
     logic `ARRAY(`COMMIT_WIDTH, `FSQ_WIDTH) commitFsqIdx;
     logic commit_exc_valid;
     logic `N(`COMMIT_WIDTH) commit_older;
@@ -639,6 +639,7 @@ endgenerate
         exc_widx <= pd_redirect.fsqIdx.idx;
         exc_waddr <= pd_redirect.stream.start_addr;
         pd_size <= pd_redirect.size;
+        exception_head_pre <= exception_head;
     end
     always_ff @(posedge clk, posedge rst)begin
         if(rst == `RST)begin
@@ -693,7 +694,7 @@ endgenerate
         .ready()
     );
     logic `N($clog2(`COMMIT_WIDTH)) exc_stream_idx;
-    assign exc_stream_idx = commitBus.fsqInfo[0].idx - exception_head;
+    assign exc_stream_idx = commitBus.fsqInfo[0].idx - exception_head_pre;
     assign fsq_back_io.commitStreamSize = exception_addrs[exc_stream_idx][`VADDR_SIZE +: `PREDICTION_WIDTH];
 
 `ifdef RVC
@@ -736,7 +737,7 @@ endgenerate
 `endif
 
     logic `N($clog2(`COMMIT_WIDTH)) exc_ridx;
-    assign exc_ridx = fsq_back_io.redirect.fsqInfo.idx - exception_head;
+    assign exc_ridx = fsq_back_io.redirect.fsqInfo.idx - exception_head_pre;
     assign fsq_back_io.exc_pc = exception_addrs[exc_ridx][`VADDR_SIZE-1: 0] + {fsq_back_io.redirect.fsqInfo.offset, {`INST_OFFSET{1'b0}}};
 
 `ifdef DIFFTEST
diff --git a/src/core/frontend/HistoryControl.sv b/src/core/frontend/HistoryControl.sv
index 209dc15..4b4824b 100644
--- a/src/core/frontend/HistoryControl.sv
+++ b/src/core/frontend/HistoryControl.sv
@@ -12,7 +12,9 @@ module HistoryControl(
     logic `N(`GHIST_SIZE) ghist;
     TageFoldHistory tage_history, tage_input_history, tage_update_history;
     logic `N(`SC_GHIST_WIDTH) sc_ghist, sc_ghist_red;
+`ifdef IMLI_VALID
     logic `N(`SC_IMLI_WIDTH) imli, imli_red;
+`endif
     logic `N(`GHIST_WIDTH) pos;
     logic `ARRAY(`SLOT_NUM, `GHIST_WIDTH) we_idx;
     logic `N(`SLOT_NUM) ghist_we;
@@ -36,7 +38,9 @@ module HistoryControl(
     assign we_idx[1] = redirect.flush ? squashInfo.redirectInfo.ghistIdx + 1 : 
                                         result.redirect_info.ghistIdx + 1;
     assign sc_ghist_red = result.en & result.redirect ? result.redirect_info.sc_ghist : sc_ghist;
+`ifdef IMLI_VALID
     assign imli_red = result.en & result.redirect ? result.redirect_info.imli : imli;
+`endif
 generate
     for(genvar i=0; i<`SLOT_NUM; i++)begin
         assign cond_result[i] = (condNum == (i+1)) & taken;
@@ -47,7 +51,9 @@ endgenerate
     assign history.ghistIdx = pos;
     assign history.tage_history = tage_history;
     assign history.sc_ghist = sc_ghist;
+`ifdef IMLI_VALID
     assign history.imli = imli;
+`endif
     localparam [`TAGE_BANK*16-1: 0] tage_hist_length = `TAGE_HIST_LENGTH;
 generate;
     for(genvar i=0; i<`TAGE_BANK; i++)begin
@@ -99,7 +105,9 @@ endgenerate
             pos <= 0;
             tage_history <= 0;
             sc_ghist <= 0;
+`ifdef IMLI_VALID
             imli <= 0;
+`endif
         end
         else begin
             pos <= squash ? squashCondNum + squashInfo.redirectInfo.ghistIdx :
@@ -116,26 +124,40 @@ endgenerate
             if(squash)begin
                 if(squashCondNum == 2)begin
                     sc_ghist <= {squashInfo.redirectInfo.sc_ghist[`SC_GHIST_WIDTH-3: 0], 1'b0, squashInfo.predInfo.taken};
-                    imli <= squashInfo.predInfo.taken;
                 end
                 else if(squashCondNum == 1)begin
                     sc_ghist <= {squashInfo.redirectInfo.sc_ghist[`SC_GHIST_WIDTH-2: 0], squashInfo.predInfo.taken};
-                    imli <= squashInfo.predInfo.taken ? squashInfo.redirectInfo.imli + 1 : 0;
                 end
                 else begin
                     sc_ghist <= squashInfo.redirectInfo.sc_ghist;
+                end
+`ifdef IMLI_VALID
+                if(squashCondNum == 2)begin
+                    imli <= squashInfo.predInfo.taken;
+                end
+                else if(squashCondNum == 1)begin
+                    imli <= squashInfo.predInfo.taken ? squashInfo.redirectInfo.imli + 1 : 0;
+                end
+                else begin
                     imli <= squashInfo.redirectInfo.imli;
                 end
+`endif
             end
             else if(result.en)begin
                 if(result.cond_num == 2)begin
                     sc_ghist <= {sc_ghist_red[`SC_GHIST_WIDTH-3: 0], 1'b0, |result.predTaken};
-                    imli <= |result.predTaken;
                 end
                 else if(result.cond_num == 1)begin
                     sc_ghist <= {sc_ghist_red[`SC_GHIST_WIDTH-2: 0], |result.predTaken};
+                end
+`ifdef IMLI_VALID
+                if(result.cond_Num == 2)begin
+                    imli <= |result.predTaken;
+                end
+                else if(result.cond_num == 1)begin
                     imli <= |result.predTaken ? imli_red + 1 : 0;
                 end
+`endif
             end
         end
     end
diff --git a/src/core/frontend/RAS.sv b/src/core/frontend/RAS.sv
index 247063e..fde261c 100644
--- a/src/core/frontend/RAS.sv
+++ b/src/core/frontend/RAS.sv
@@ -5,8 +5,7 @@
 // 一种方法为在commit时写入来修复错误，但是在squash后commit前这一段时间读取会导致错误
 // 并且commit会影响推测更新的结果    
 // 下面是另一种方法，记录所有inflight的push地址，这样当redirect时不会因为pop-push操作导致覆盖
-`ifdef FEAT_LINKRAS
-module LinkRAS(
+module RAS(
     input logic clk,
     input logic rst,
     BpuRASIO.ras ras_io
@@ -251,229 +250,4 @@ module LinkRAS(
     $sformatf("ras commit top mismatch"))
 `endif
 `endif
-endmodule
-`else
-module RAS(
-    input logic clk,
-    input logic rst,
-    BpuRASIO.ras ras_io
-);
-    logic `N(`RAS_WIDTH) top, top_p1, top_n1;
-    logic `N(`RAS_WIDTH) bottom, bottom_n1, redirect_bottom_n1;
-    logic `N(`RAS_WIDTH) redirect_p1, redirect_n1;
-    logic `N(`RAS_WIDTH) commit_top;
-    logic bdir, tdir, bdir_n, rbdir_n;
-    logic `N(`RAS_WIDTH) waddr, commit_waddr;
-    logic `N(`RAS_SIZE) speculate, spec_pop, spec_push, speculate_mask;
-    logic `N(`RAS_SIZE) redirect_valid_mask, redirect_top_mask, redirect_bottom_mask;
-    logic `N(`RAS_SIZE) commit_mask;
-    RasEntry entry, updateEntry, commitUpdateEntry, commitEntry;
-    logic [1: 0] squashType;
-    RasRedirectInfo r;
-    BTBUpdateInfo btbEntry;
-    logic we, commit_we;
-    logic commit_update;
-    logic full, empty, redirect_full, redirect_empty;
-    logic `VADDR_BUS squash_target;
-
-    assign top_p1 = top - 1;
-    assign top_n1 = top + 1;
-    assign redirect_p1 = r.rasTop - 1;
-    assign redirect_n1 = r.rasTop + 1;
-    LoopAdder #(`RAS_WIDTH, 1) adder_bottom(1'b1, {bottom, bdir}, {bottom_n1, bdir_n});
-    LoopAdder #(`RAS_WIDTH, 1) adder_rbottom(1'b1, {r.rasBottom, r.ras_bdir}, {redirect_bottom_n1, rbdir_n});
-    assign full = (bdir ^ tdir) & (top == bottom);
-    assign empty = (bdir == tdir) & (top == bottom);
-    assign r = ras_io.squashInfo.redirectInfo.rasInfo;
-    assign btbEntry = ras_io.updateInfo.btbEntry;
-    assign redirect_full = (r.ras_bdir ^ r.ras_tdir) & (r.rasTop == r.rasBottom);
-    assign redirect_empty = (r.ras_bdir == r.ras_tdir) & (r.rasTop == r.rasBottom);
-    MaskGen #(`RAS_SIZE) mask_gen_top (r.rasTop, redirect_top_mask);
-    MaskGen #(`RAS_SIZE) mask_gen_bottom (r.rasBottom, redirect_bottom_mask);
-    Decoder #(`RAS_SIZE) decoder_commit_top (commit_top, commit_mask);
-    assign redirect_valid_mask = redirect_full ? {`RAS_SIZE{1'b1}} :
-                                 redirect_empty ? {`RAS_SIZE{1'b0}} :
-            redirect_top_mask ^ redirect_bottom_mask ^ {`RAS_SIZE{r.ras_bdir ^ r.ras_tdir}};
-    assign speculate_mask = redirect_valid_mask & spec_pop & spec_push;
-    assign waddr = ras_io.squash && squashType == POP_PUSH ? r.rasTop - 1 :
-                   ras_io.squash ? r.rasTop :
-                   ras_io.ras_type == POP_PUSH ? top_p1 : top;
-    assign commit_waddr = btbEntry.tailSlot.ras_type == POP_PUSH ? commit_top - 1 : commit_top;
-
-`ifdef RVC
-    assign squash_target = ras_io.squashInfo.start_addr + {ras_io.squashInfo.offset, {`INST_OFFSET{1'b0}}} + {~ras_io.squashInfo.rvc, ras_io.squashInfo.rvc, 1'b0};
-    assign commitUpdateEntry.pc = ras_io.updateInfo.start_addr + {btbEntry.tailSlot.offset, {`INST_OFFSET{1'b0}}} + {~btbEntry.tailSlot.rvc, btbEntry.tailSlot.rvc, 1'b0};
-`else
-    assign squash_target = ras_io.squashInfo.start_addr + {ras_io.squashInfo.offset, {`INST_OFFSET{1'b0}}} + 4;
-    assign commitUpdateEntry.pc = ras_io.updateInfo.start_addr + {btbEntry.tailSlot.offset, {`INST_OFFSET{1'b0}}} + 4;
-`endif
-    assign updateEntry.pc = ras_io.squash ? squash_target : ras_io.target;
-    assign squashType = ras_io.squashInfo.ras_type;
-    assign we = ~ras_io.squash & ras_io.request & ras_io.ras_type[1] | 
-                ras_io.squash & squashType[1];
-    assign commit_we = ras_io.update & ras_io.updateInfo.tailTaken & 
-                        (btbEntry.tailSlot.br_type == CALL) &
-                        btbEntry.tailSlot.ras_type[1];
-    assign commit_update = ras_io.update & ras_io.updateInfo.tailTaken & (btbEntry.tailSlot.br_type == CALL);
-
-
-    assign ras_io.en = ~empty;
-    assign ras_io.rasInfo.rasTop = top;
-    assign ras_io.rasInfo.ras_tdir = tdir;
-    assign ras_io.rasInfo.rasBottom = bottom;
-    assign ras_io.rasInfo.ras_bdir = bdir;
-    assign ras_io.entry = speculate[top_p1] & ~spec_push[top_p1] ? commitEntry : entry;
-
-    MPRAM #(
-        .WIDTH($bits(RasEntry)),
-        .DEPTH(`RAS_SIZE),
-        .READ_PORT(1),
-        .WRITE_PORT(1),
-        .READ_LATENCY(0)
-    ) ras (
-        .clk(clk),
-        .rst(rst),
-        .rst_sync(0),
-        .en(1'b1),
-        .we(we),
-        .waddr(waddr),
-        .raddr(top_p1),
-        .wdata(updateEntry),
-        .rdata(entry),
-        .ready()
-    );
-
-    MPRAM #(
-        .WIDTH($bits(RasEntry)),
-        .DEPTH(`RAS_SIZE),
-        .READ_PORT(1),
-        .WRITE_PORT(1),
-        .READ_LATENCY(0)
-    ) commit_ras (
-        .clk,
-        .rst,
-        .rst_sync(0),
-        .en(1'b1),
-        .we(commit_we),
-        .waddr(commit_waddr),
-        .raddr(top_p1),
-        .wdata(commitUpdateEntry),
-        .rdata(commitEntry),
-        .ready()
-    );
-
-    always_ff @(posedge clk or posedge rst)begin
-        if(rst == `RST)begin
-            top <= 0;
-            bottom <= 0;
-            bdir <= 0;
-            tdir <= 0;
-            speculate <= 0;
-            spec_pop <= 0;
-            spec_push <= 0;
-            commit_top <= 0;
-        end
-        else begin
-            if(ras_io.squash)begin
-                if(!ras_io.squashInfo.squash_front)begin
-                    spec_pop <= 0;
-                    spec_push <= 0;
-                end
-                if(squashType == POP && !redirect_empty)begin
-                    top <= r.rasTop - 1;
-                    tdir <= redirect_p1[`RAS_WIDTH-1] & ~r.rasTop[`RAS_WIDTH-1] ? ~r.ras_tdir : r.ras_bdir;
-                end
-                else if(squashType == PUSH)begin
-                    top <= r.rasTop + 1;
-                    tdir <= r.rasTop[`RAS_WIDTH-1] & ~redirect_n1[`RAS_WIDTH-1] ? ~r.ras_tdir : r.ras_bdir;
-                end
-                else begin
-                    top <= r.rasTop;
-                    tdir <= r.ras_tdir;
-                end
-                if(squashType == PUSH && redirect_full)begin
-                    bottom <= redirect_bottom_n1;
-                    bdir <= rbdir_n;
-                end
-                else begin
-                    bottom <= r.rasBottom;
-                    bdir <= r.ras_bdir;
-                end
-            end
-            else if(ras_io.request)begin
-                if(ras_io.ras_type == POP && !empty)begin
-                    top <= top_p1;
-                    tdir <= top_p1[`RAS_WIDTH-1] & ~top[`RAS_WIDTH-1] ? ~tdir : tdir;
-                end
-                else if(ras_io.ras_type == PUSH)begin
-                    top <= top_n1;
-                    tdir <= top[`RAS_WIDTH-1] & ~top_n1[`RAS_WIDTH-1] ? ~tdir : tdir;
-                    if(full)begin
-                        bottom <= bottom_n1;
-                        bdir <= bdir_n;
-                    end
-                end
-            end
-
-            if(ras_io.squashInfo.squash_front & squashType[0] & ~redirect_empty)begin
-                spec_pop[redirect_p1] <= 1'b1;
-            end
-            else if(ras_io.request & ras_io.ras_type[0] & ~empty)begin
-                spec_pop[top_p1] <= 1'b1;
-            end
-            
-            if(ras_io.squashInfo.squash_front & squashType[1])begin
-                if(squashType[0])begin
-                    spec_push[redirect_p1] <= 1'b1;
-                end
-                else begin
-                    spec_push[r.rasTop] <= 1'b1;
-                end
-            end
-            else if(ras_io.request & ras_io.ras_type[1])begin
-                if(ras_io.ras_type[0])begin
-                    spec_push[top_p1] <= 1'b1;
-                end
-                else begin
-                    spec_push[top] <= 1'b1;
-                end
-            end
-
-            for(int i=0; i<`RAS_SIZE; i++)begin
-                speculate[i] <= (speculate[i] | speculate_mask[i] & ras_io.squash & ~ras_io.squashInfo.squash_front) &
-                                ~(commit_we & commit_mask[i]);
-            end
-
-            if(commit_update)begin
-                if(btbEntry.tailSlot.ras_type == POP)begin
-                    commit_top <= commit_top - 1;
-                end
-                else if(btbEntry.tailSlot.ras_type == PUSH)begin
-                    commit_top <= commit_top + 1;
-                end
-            end
-        end
-    end
-
-    `Log(DLog::Debug, T_RAS, ~ras_io.squash & ras_io.request & ras_io.ras_type != NONE,
-        $sformatf("ras lookup. %d %d %b %b %h %h", top, bottom, tdir, bdir, ras_io.target, ras_io.ras_type))
-    `Log(DLog::Debug, T_RAS, ras_io.squash & squashType != NONE,
-        $sformatf("ras squash. %h %h", squash_target, squashType))
-
-`ifdef T_DEBUG
-    logic `ARRAY(`FSQ_SIZE, `RAS_WIDTH) lookup_idx;
-    logic update_n;
-    logic `N(`FSQ_WIDTH) fsqIdx;
-    always_ff @(posedge clk)begin
-        update_n <= ras_io.update;
-        fsqIdx <= ras_io.updateInfo.fsqIdx;
-        if(ras_io.lastStage)begin
-            lookup_idx[ras_io.lastStageIdx] <= top;
-        end
-    end
-    `Log(DLog::Debug, T_DEBUG, update_n && (commit_top != lookup_idx[fsqIdx]),
-    $sformatf("ras commit top mismatch"))
-`endif
-
-endmodule
-`endif
\ No newline at end of file
+endmodule
\ No newline at end of file
diff --git a/src/core/frontend/UBTB.sv b/src/core/frontend/UBTB.sv
index a82156f..3693faf 100644
--- a/src/core/frontend/UBTB.sv
+++ b/src/core/frontend/UBTB.sv
@@ -74,7 +74,9 @@ endgenerate
         result_i.redirect_info.tage_history = ubtb_io.history.tage_history;
         result_i.redirect_info.rasInfo = 0;
         result_i.redirect_info.sc_ghist = ubtb_io.history.sc_ghist;
+`ifdef IMLI_VALID
         result_i.redirect_info.imli = ubtb_io.history.imli;
+`endif
         result_i.stream.target = ubtb_io.pc + `BLOCK_SIZE;
 `ifdef RVC
         result_i.stream.size = `BLOCK_INST_SIZE - 2;
diff --git a/src/core/mmu/PTW.sv b/src/core/mmu/PTW.sv
index 301d698..87a455d 100644
--- a/src/core/mmu/PTW.sv
+++ b/src/core/mmu/PTW.sv
@@ -349,6 +349,8 @@ module PTW(
             endcase
         end
     end
+
+    `PERF(ptw_miss, axi_io.ar_valid & axi_io.ar_ready)
 endmodule
 
 interface PTBufferIO #(
diff --git a/src/defines/arch.svh b/src/defines/arch.svh
index 8945762..4212859 100644
--- a/src/defines/arch.svh
+++ b/src/defines/arch.svh
@@ -10,7 +10,6 @@
 
 `define EXT_FENCEI
 
-`define FEAT_LINKRAS
 `define FEAT_SC
 `define FEAT_ITTAGE_REGION
 
diff --git a/src/defines/bundles.svh b/src/defines/bundles.svh
index 1a0aa21..e4e438c 100644
--- a/src/defines/bundles.svh
+++ b/src/defines/bundles.svh
@@ -105,7 +105,9 @@ typedef struct packed {
 typedef struct packed {
     TageMeta tage;
     UBTBMeta ubtb;
+`ifdef FEAT_SC
     SCMeta sc;
+`endif
     ITTageMeta ittage;
 } PredictionMeta;
 
@@ -130,28 +132,21 @@ typedef struct packed {
     logic `ARRAY(`TAGE_BANK, `TAGE_TAG_COMPRESS2) fold_tag2;
 } TageFoldHistory;
 
-`ifdef FEAT_LINKRAS
 typedef struct packed {
     RasInflightIdx rasTop;
     RasInflightIdx listTop;
     logic `N(`RAS_WIDTH) inflightTop;
     logic topInvalid;
 } RasRedirectInfo;
-`else
-typedef struct packed {
-    logic `N(`RAS_WIDTH) rasTop;
-    logic `N(`RAS_WIDTH) rasBottom;
-    logic ras_tdir;
-    logic ras_bdir;
-} RasRedirectInfo;
-`endif
 
 typedef struct packed {
     logic `N(`GHIST_WIDTH) ghistIdx;
     TageFoldHistory tage_history;
     RasRedirectInfo rasInfo;
     logic `N(`SC_GHIST_WIDTH) sc_ghist;
+`ifdef IMLI_VALID
     logic `N(`SC_IMLI_WIDTH) imli;
+`endif
     // logic `N(`RAS_CTR_SIZE) ras_ctr;
 } RedirectInfo;
 
@@ -160,7 +155,9 @@ typedef struct packed {
     // logic `N(`GHIST_SIZE) ghist;
     // logic `N(`PHIST_SIZE) phist;
     logic `N(`SC_GHIST_WIDTH) sc_ghist;
+`ifdef IMLI_VALID
     logic `N(`SC_IMLI_WIDTH) imli;
+`endif
     TageFoldHistory tage_history;
 } BranchHistory;
 
diff --git a/src/defines/global.svh b/src/defines/global.svh
index a75b24e..1b48569 100644
--- a/src/defines/global.svh
+++ b/src/defines/global.svh
@@ -89,11 +89,12 @@
 `define SC_HIST_NUM 4
 `define SC_SET_WIDTH 9
 `define SC_COMMIT_SIZE 4
-`define SC_HIST_DEPTH 64'h0100_0100_0100_0100
-`define SC_HIST_LENGTH 64'h000f_0008_0004_0000
+`define SC_HIST_DEPTH 64'h0200_0200_0200_0200
+`define SC_HIST_LENGTH 64'h000f_000b_0008_0004 // better than 000f_0008_0004_0000
 `define SC_HIST_THRESH_DEPTH 64'h0020_0020_0020_0020
 `define SC_HIST_INIT 6'b100000
 `define SC_IMLI_NUM 0
+// `define IMLI_VALID
 `define SC_IMLI_DEPTH 16'h0200
 `define SC_IMLI_THRESH_DEPTH 16'h0020
 `define SC_IMLI_INIT 6'b100000

From 9b2e8dc35f302842315dfd9c7e32747e90c5a4a3 Mon Sep 17 00:00:00 2001
From: xinhecuican <lizilin268646@gmail.com>
Date: Fri, 31 Jan 2025 14:22:24 +0800
Subject: [PATCH 2/3] impl l2 cache

---
 Makefile                                    |    2 +-
 src/core/AxiInterface.sv                    |  340 ------
 src/core/CPUCore.sv                         |   38 +-
 src/core/backend/Backend.sv                 |    2 +-
 src/core/backend/lsu/LSU.sv                 |    6 +-
 src/core/backend/lsu/dcache/DCacheMiss.sv   |   51 +-
 src/core/backend/lsu/dcache/DCacheWay.sv    |   84 +-
 src/core/backend/lsu/dcache/ReplaceQueue.sv |  138 +--
 src/core/backend/lsu/dcache/dcache.sv       |  176 ++-
 src/core/mem/cache/Directory.sv             |  204 ++++
 src/core/mem/cache/L2Cache.sv               |  101 ++
 src/core/mem/cache/L2CacheData.sv           |  139 +++
 src/core/mem/cache/L2CacheWrapper.sv        |  151 +++
 src/core/mem/cache/L2MSHR.sv                | 1161 +++++++++++++++++++
 src/core/{ => mem}/mmu/DTLB.sv              |    2 +-
 src/core/{ => mem}/mmu/ITLB.sv              |    2 +-
 src/core/{ => mem}/mmu/L2TLB.sv             |    2 +-
 src/core/{ => mem}/mmu/PMPCheck.sv          |    2 +-
 src/core/{ => mem}/mmu/PTW.sv               |    2 +-
 src/core/{ => mem}/mmu/TLB.sv               |    2 +-
 src/core/{ => mem}/mmu/TLBCache.sv          |    2 +-
 src/core/{ => mem}/mmu/TLBRepeater.sv       |    2 +-
 src/defines/arch.svh                        |    1 +
 src/defines/bundles.svh                     |   18 +-
 src/defines/bus/ace.svh                     |   82 +-
 src/defines/bus/mem.svh                     |   29 +-
 src/defines/global.svh                      |   19 +-
 src/defines/interfaces.svh                  |   95 ++
 src/sim/SimTop.sv                           |   16 +-
 src/soc/Soc.sv                              |   14 +-
 src/utils/axi/axi_convert/ace_ccu_top.sv    |  241 ----
 src/utils/utils.sv                          |   48 +-
 32 files changed, 2278 insertions(+), 894 deletions(-)
 delete mode 100644 src/core/AxiInterface.sv
 create mode 100644 src/core/mem/cache/Directory.sv
 create mode 100644 src/core/mem/cache/L2Cache.sv
 create mode 100644 src/core/mem/cache/L2CacheData.sv
 create mode 100644 src/core/mem/cache/L2CacheWrapper.sv
 create mode 100644 src/core/mem/cache/L2MSHR.sv
 rename src/core/{ => mem}/mmu/DTLB.sv (99%)
 rename src/core/{ => mem}/mmu/ITLB.sv (99%)
 rename src/core/{ => mem}/mmu/L2TLB.sv (98%)
 rename src/core/{ => mem}/mmu/PMPCheck.sv (98%)
 rename src/core/{ => mem}/mmu/PTW.sv (99%)
 rename src/core/{ => mem}/mmu/TLB.sv (99%)
 rename src/core/{ => mem}/mmu/TLBCache.sv (99%)
 rename src/core/{ => mem}/mmu/TLBRepeater.sv (95%)
 delete mode 100644 src/utils/axi/axi_convert/ace_ccu_top.sv

diff --git a/Makefile b/Makefile
index 4916622..55de446 100644
--- a/Makefile
+++ b/Makefile
@@ -73,7 +73,7 @@ emu:
 
 emu-run: emu
 	mkdir -p $(LOG_PATH)
-	build/emu -i "${I}" -s 1168 -b ${S} -e ${E} -B $(WB) -E $(WE) ${TRACE_ARGS} --log-path=${LOG_PATH}
+	riscv64-unknown-linux-gnu-gdb --args build/emu -i "${I}" -s 1168 -b ${S} -e ${E} -B $(WB) -E $(WE) ${TRACE_ARGS} --log-path=${LOG_PATH}
 
 sbi:
 	make -C utils/opensbi ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- PLATFORM_RISCV_XLEN=32 PLATFORM=generic FW_PAYLOAD_PATH=${CURDIR}/utils/rv-linux/arch/riscv/boot/Image FW_FDT_PATH=${CURDIR}/utils/opensbi/dts/custom.dtb FW_PAYLOAD_OFFSET=0x400000
diff --git a/src/core/AxiInterface.sv b/src/core/AxiInterface.sv
deleted file mode 100644
index 770d676..0000000
--- a/src/core/AxiInterface.sv
+++ /dev/null
@@ -1,340 +0,0 @@
-`include "../defines/defines.svh"
-
-module AxiInterface(
-    input logic clk,
-    input logic rst,
-    CacheBus.slaver icache_io,
-    CacheBus.slaver tlb_io,
-    CacheBus.slave dcache_io,
-    CacheBus.slave ducache_io,
-    AxiIO.master axi,
-    NativeSnoopIO.slave dcache_snoop_io
-);
-
-    typedef logic [`PADDR_SIZE-1: 0] addr_t;
-    typedef logic [`CORE_WIDTH-1: 0] id_t;
-    typedef logic user_t;
-    typedef logic [`CORE_WIDTH+2-1: 0] mst_id_t;
-    typedef logic [`XLEN-1: 0] data_t;
-    typedef logic [`XLEN/8-1: 0] strb_t;
-    `CACHE_TYPEDEF_AW_CHAN_T(AxiAW, addr_t, id_t, user_t)
-    `CACHE_TYPEDEF_W_CHAN_T(AxiW, data_t, strb_t, user_t)
-    `CACHE_TYPEDEF_B_CHAN_T(AxiB, id_t, user_t)
-    `CACHE_TYPEDEF_AR_CHAN_T(AxiAR, addr_t, id_t, user_t)
-    `CACHE_TYPEDEF_R_CHAN_T(AxiR, data_t, id_t, user_t)
-    `CACHE_TYPEDEF_REQ_T(AxiReq, AxiAW, AxiW, AxiAR)
-    `CACHE_TYPEDEF_RESP_T(AxiResp, AxiB, AxiR)
-
-    `CACHE_TYPEDEF_AW_CHAN_T(AxiMAW, addr_t, mst_id_t, user_t)
-    `CACHE_TYPEDEF_B_CHAN_T(AxiMB, mst_id_t, user_t)
-    `CACHE_TYPEDEF_AR_CHAN_T(AxiMAR, addr_t, mst_id_t, user_t)
-    `CACHE_TYPEDEF_R_CHAN_T(AxiMR, data_t, mst_id_t, user_t)
-    `CACHE_TYPEDEF_REQ_T(AxiMReq, AxiMAW, AxiW, AxiMAR)
-    `CACHE_TYPEDEF_RESP_T(AxiMResp, AxiMB, AxiMR)
-    AxiReq ireq, dreq, du_req, tlb_req;
-    AxiResp iresp, dresp, du_resp, tlb_resp;
-    AxiMReq req_o, co_req_o;
-    AxiMResp resp_i, co_resp_i;
-
-    `CACHE_ASSIGN_TO_AR(ireq.ar, icache_io)
-    assign ireq.ar_valid = icache_io.ar_valid;
-    assign ireq.r_ready = icache_io.r_ready;
-    assign ireq.aw = 0;
-    assign ireq.w = 0;
-    assign ireq.aw_valid = 0;
-    assign ireq.w_valid = 0;
-    assign ireq.b_ready = 0;
-    `CACHE_ASSIGN_FROM_R(icache_io, iresp.r)
-    assign icache_io.ar_ready = iresp.ar_ready;
-    assign icache_io.r_valid = iresp.r_valid;
-
-    `CACHE_ASSIGN_TO_AR(tlb_req.ar, tlb_io)
-    assign tlb_req.ar_valid = tlb_io.ar_valid;
-    assign tlb_req.r_ready = icache_io.r_ready;
-    assign tlb_req.aw = 0;
-    assign tlb_req.w = 0;
-    assign tlb_req.aw_valid = 0;
-    assign tlb_req.w_valid = 0;
-    assign tlb_req.b_ready = 0;
-    `CACHE_ASSIGN_FROM_R(tlb_io, tlb_resp.r)
-    assign tlb_io.ar_ready = tlb_resp.ar_ready;
-    assign tlb_io.r_valid = tlb_resp.r_valid;
-
-    `CACHE_ASSIGN_TO_REQ(dreq, dcache_io)
-    `CACHE_ASSIGN_FROM_RESP(dcache_io, dresp)
-
-    `CACHE_ASSIGN_TO_REQ(du_req, ducache_io)
-    `CACHE_ASSIGN_FROM_RESP(ducache_io, du_resp)
-
-    `__CACHE_TO_W(assign, axi.w, _, co_req_o.w, .)
-    assign axi.ar_valid = co_req_o.ar_valid;
-    assign axi.w_valid = co_req_o.w_valid;
-    assign axi.b_ready = co_req_o.b_ready;
-    assign axi.r_ready = co_req_o.r_ready;
-    assign axi.aw_valid = co_req_o.aw_valid;
-    assign axi.ar_id = co_req_o.ar.id;
-    assign axi.ar_addr = co_req_o.ar.addr;
-    assign axi.ar_len = co_req_o.ar.len;
-    assign axi.ar_size = co_req_o.ar.size;
-    assign axi.ar_burst = co_req_o.ar.burst;
-    assign axi.ar_user = co_req_o.ar.user;
-    assign axi.aw_id = co_req_o.aw.id;
-    assign axi.aw_addr = co_req_o.aw.addr;
-    assign axi.aw_len = co_req_o.aw.len;
-    assign axi.aw_size = co_req_o.aw.size;
-    assign axi.aw_burst = co_req_o.aw.burst;
-    assign axi.aw_user = co_req_o.aw.user;
-    assign axi.aw_cache = 0;
-    assign axi.aw_prot = 0;
-    assign axi.aw_qos = 0;
-    assign axi.aw_region = 0;
-    assign axi.ar_cache = 0;
-    assign axi.ar_prot = 0;
-    assign axi.ar_qos = 0;
-    assign axi.ar_region = 0;
-    `__CACHE_TO_B(assign, co_resp_i.b, ., axi.b, _)
-    `__CACHE_TO_R(assign, co_resp_i.r, ., axi.r, _)
-    assign co_resp_i.aw_ready = axi.aw_ready;
-    assign co_resp_i.ar_ready = axi.ar_ready;
-    assign co_resp_i.w_ready = axi.w_ready;
-    assign co_resp_i.b_valid = axi.b_valid;
-    assign co_resp_i.r_valid = axi.r_valid;
-
-    axi_mux #(
-        .SlvAxiIDWidth(`CORE_WIDTH),
-        .slv_aw_chan_t(AxiAW),
-        .mst_aw_chan_t(AxiMAW),
-        .w_chan_t(AxiW),
-        .slv_b_chan_t(AxiB),
-        .mst_b_chan_t(AxiMB),
-        .slv_ar_chan_t(AxiAR),
-        .mst_ar_chan_t(AxiMAR),
-        .slv_r_chan_t(AxiR),
-        .mst_r_chan_t(AxiMR),
-        .slv_req_t(AxiReq),
-        .slv_resp_t(AxiResp),
-        .mst_req_t(AxiMReq),
-        .mst_resp_t(AxiMResp),
-        .MaxWTrans(1), // 只有DCache有写
-        .NoSlvPorts(4)
-    ) axi_mux_inst(
-        .clk_i(clk),
-        .rst_ni(~rst),
-        .test_i(1'b0),
-        .slv_reqs_i({dreq, du_req, tlb_req, ireq}),
-        .slv_resps_o({dresp, du_resp, tlb_resp, iresp}),
-        .mst_req_o(req_o),
-        .mst_resp_i(resp_i)
-    );
-
-    logic `N(`DCACHE_WAY_WIDTH) wway;
-    always_ff @(posedge clk)begin
-        wway <= dcache_io.ar_user;
-    end
-
-    DCacheCoherence #(
-        .aw_chan_t(AxiMAW),
-        .w_chan_t(AxiW),
-        .b_chan_t(AxiMB),
-        .ar_chan_t(AxiMAR),
-        .r_chan_t(AxiMR),
-        .axi_req_t(AxiMReq),
-        .axi_resp_t(AxiMResp)
-    ) dcache_coherence (
-        .clk,
-        .rst(rst),
-        .wway_i(wway),
-        .slv_req_i(req_o),
-        .slv_resp_o(resp_i),
-        .mst_req_o(co_req_o),
-        .mst_resp_i(co_resp_i),
-        .dcache_snoop_io(dcache_snoop_io)
-    );
-
-endmodule
-
-module DCacheCoherence #(
-    // AXI channel structs
-    parameter type  aw_chan_t = logic,
-    parameter type   w_chan_t = logic,
-    parameter type   b_chan_t = logic,
-    parameter type  ar_chan_t = logic,
-    parameter type   r_chan_t = logic,
-    // AXI request & response structs
-    parameter type  axi_req_t = logic,
-    parameter type axi_resp_t = logic
-)(
-    input logic clk,
-    input logic rst,
-    input logic `N(`DCACHE_WAY_WIDTH) wway_i,
-    input axi_req_t slv_req_i,
-    output axi_resp_t slv_resp_o,
-
-    output axi_req_t mst_req_o,
-    input axi_resp_t mst_resp_i,
-    NativeSnoopIO.slave dcache_snoop_io
-);
-    logic `N(`DCACHE_SET_WIDTH) widx, widx_n;
-    logic `N(`DCACHE_TAG) wtag;
-    logic `ARRAY(`DCACHE_WAY, `DCACHE_TAG+1) w_tagv, tagv;
-    logic w_valid;
-    logic `N(`DCACHE_WAY_WIDTH) w_way_idx;
-    logic `N(`DCACHE_WAY) w_way;
-    logic `N(`DCACHE_WAY) tagv_hits;
-    logic `N(`PADDR_SIZE) ac_addr;
-    logic tagv_hit;
-    logic `N(`DCACHE_TAG) rtag;
-    logic r_dcache;
-    r_chan_t snoop_r;
-
-    logic `N(`DCACHE_REPLACE_SIZE) replace_valid;
-    logic `N(`DCACHE_BLOCK_SIZE) replace_tag `N(`DCACHE_REPLACE_SIZE);
-    logic replace_en;
-    logic `N(`DCACHE_WAY_WIDTH) replace_way;
-    logic `N(`DCACHE_REPLACE_WIDTH) replace_free_idx;
-    logic `N(`PADDR_SIZE) replace_clear_addr;
-    logic `N(`DCACHE_REPLACE_SIZE) replace_hits, replace_clear_hits;
-    logic `N(`DCACHE_REPLACE_WIDTH) replace_idx, replace_clear_idx;
-    logic replace_hit, replace_clear_en;
-    logic aw_writeEvict, ar_makeUnique;
-
-    axi_req_t slv_req_i_s2;
-    axi_resp_t slv_resp_o_s2;
-
-    assign w_valid = (slv_resp_o.r.last & slv_resp_o.r_valid & slv_req_i.r_ready & 
-                     (slv_resp_o.r.id[`CORE_WIDTH+1: `CORE_WIDTH] == 2'b11)) |
-                     ar_makeUnique;
-    Decoder #(`DCACHE_WAY) decoder_way (w_way_idx, w_way);
-    MPRAM #(
-        .WIDTH(`DCACHE_WAY * (`DCACHE_TAG+1)),
-        .DEPTH(`DCACHE_SET),
-        .READ_PORT(1),
-        .WRITE_PORT(0),
-        .RW_PORT(1),
-        .READ_LATENCY(1),
-        .RESET(1),
-        .BYTE_WRITE(1),
-        .BYTES(`DCACHE_WAY)
-    ) tagv_ram (
-        .clk,
-        .rst,
-        .rst_sync(0),
-        .en({w_valid, slv_req_i.ar_valid}),
-        .we(w_way & {`DCACHE_WAY{w_valid}}),
-        .raddr(slv_req_i.ar.addr`DCACHE_SET_BUS),
-        .rdata({w_tagv, tagv}),
-        .waddr(widx),
-        .wdata({`DCACHE_WAY{wtag, 1'b1}}),
-        .ready()
-    );
-
-    assign tagv_hit = |tagv_hits;
-generate
-    for(genvar i=0; i<`DCACHE_REPLACE_SIZE; i++)begin
-        assign replace_hits[i] = replace_valid[i] & (slv_req_i.ar.addr`DCACHE_BLOCK_BUS == replace_tag[i]);
-        assign replace_clear_hits[i] = replace_valid[i] & (replace_clear_addr`DCACHE_BLOCK_BUS == replace_tag[i]);
-    end
-    for(genvar i=0; i<`DCACHE_WAY; i++)begin
-        assign tagv_hits[i] = tagv[i][0] & (rtag == tagv[i][`DCACHE_TAG: 1]);
-    end
-endgenerate
-    PEncoder #(`DCACHE_REPLACE_SIZE) encoder_replace_free_idx (~replace_valid, replace_free_idx);
-    Encoder #(`DCACHE_REPLACE_SIZE) encoder_replace_idx (replace_clear_hits, replace_idx);
-    always_ff @(posedge clk)begin
-        replace_en <= w_valid;
-        replace_way <= w_way_idx;
-        replace_hit <= |replace_hits;
-        rtag <= slv_req_i.ar.addr`DCACHE_TAG_BUS;
-        ac_addr <= slv_req_i.ar.addr;
-        r_dcache <= slv_req_i.ar.id[`CORE_WIDTH+1: `CORE_WIDTH] == 2'b11;
-        aw_writeEvict <= slv_req_i.aw_valid & (slv_req_i.aw.snoop == `ACEOP_WRITE_EVICT) & 
-                         (slv_req_i.aw.id[`CORE_WIDTH+1: `CORE_WIDTH] == 2'b11);
-        ar_makeUnique <= slv_req_i.ar_valid & (slv_req_i.ar.snoop == `ACEOP_MAKE_UNIQUE) &
-                        (slv_req_i.ar.id[`CORE_WIDTH+1: `CORE_WIDTH] == 2'b11);
-        if(slv_req_i.ar_valid & (slv_req_i.ar.id[`CORE_WIDTH+1: `CORE_WIDTH] == 2'b11))begin
-            wtag <= slv_req_i.ar.addr`DCACHE_TAG_BUS;
-            widx <= slv_req_i.ar.addr`DCACHE_SET_BUS;
-            w_way_idx <= wway_i;
-        end
-        widx_n <= widx;
-    end
-    always_ff @(posedge clk, posedge rst)begin
-        if(rst == `RST)begin
-            replace_valid <= 0;
-            replace_tag <= '{default: 0};
-            replace_clear_en <= 1'b0;
-            replace_clear_idx <= 0;
-            replace_clear_addr <= 0;
-        end
-        else begin
-            if(replace_en)begin
-                replace_valid[replace_free_idx] <= 1'b1;
-                replace_tag[replace_free_idx] <= {w_tagv[replace_way][`DCACHE_TAG: 1], widx_n};
-            end
-            if(slv_req_i.aw_valid & slv_resp_o.aw_ready & slv_req_i.aw.user)begin
-                replace_clear_en <= 1'b1;
-            end
-            if(slv_req_i.aw_valid)begin
-                replace_clear_addr <= slv_req_i.aw.addr;
-            end
-            if(replace_clear_en & ~slv_req_i.ar_valid)begin
-                replace_clear_en <= 1'b0;
-                replace_clear_idx <= replace_idx;
-            end
-            if(slv_resp_o.b_valid & slv_req_i.b_ready & 
-              (slv_resp_o.b.id[`CORE_WIDTH+1: `CORE_WIDTH] == 2'b11))begin
-                replace_valid[replace_clear_idx] <= 1'b0;
-            end
-            if(aw_writeEvict)begin
-                replace_valid[replace_idx] <= 1'b0;
-            end
-        end
-    end
-
-    axi_cut #(
-        .aw_chan_t(aw_chan_t),
-        .w_chan_t(w_chan_t),
-        .b_chan_t(b_chan_t),
-        .ar_chan_t(ar_chan_t),
-        .r_chan_t(r_chan_t),
-        .axi_req_t(axi_req_t),
-        .axi_resp_t(axi_resp_t)
-    ) axi_cut_inst (
-        .clk_i(clk),
-        .rst_ni(~rst),
-        .slv_req_i(slv_req_i),
-        .slv_resp_o(slv_resp_o),
-        .mst_req_o(slv_req_i_s2),
-        .mst_resp_i(slv_resp_o_s2)
-    );
-
-    assign mst_req_o.aw = slv_req_i_s2.aw;
-    assign mst_req_o.aw_valid = ~aw_writeEvict & slv_req_i_s2.aw_valid;
-    assign mst_req_o.w = slv_req_i_s2.w;
-    assign mst_req_o.w_valid = slv_req_i_s2.w_valid;
-    assign mst_req_o.b_ready = slv_req_i_s2.b_ready;
-    assign mst_req_o.ar = slv_req_i_s2.ar;
-    assign mst_req_o.ar_valid = (~replace_hit & ~tagv_hit | r_dcache) & ~ar_makeUnique & slv_req_i_s2.ar_valid;
-    assign mst_req_o.r_ready = slv_req_i_s2.r_ready;
-
-    assign slv_resp_o_s2.aw_ready = mst_resp_i.aw_ready | aw_writeEvict;
-    assign slv_resp_o_s2.ar_ready = ar_makeUnique ? 1'b1 : 
-             (~replace_hit & ~tagv_hit | r_dcache) ? mst_resp_i.ar_ready :
-                                                     dcache_snoop_io.ac_ready;
-    assign slv_resp_o_s2.w_ready = mst_resp_i.w_ready;
-    assign slv_resp_o_s2.b_valid = mst_resp_i.b_valid;
-    assign slv_resp_o_s2.b = mst_resp_i.b;
-    assign slv_resp_o_s2.r_valid = dcache_snoop_io.cd_valid | mst_resp_i.r_valid;
-    assign slv_resp_o_s2.r = mst_resp_i.r_valid ? mst_resp_i.r : snoop_r;
-
-    assign dcache_snoop_io.ac_addr = ac_addr;
-    assign dcache_snoop_io.ac_valid = (replace_hit | tagv_hit) & ~r_dcache & slv_req_i_s2.ar_valid;
-    assign dcache_snoop_io.ac_user = slv_req_i_s2.ar.id;
-    assign dcache_snoop_io.cd_ready = ~mst_resp_i.r_valid;
-    assign snoop_r.id = dcache_snoop_io.cd_user;
-    assign snoop_r.data = dcache_snoop_io.cd_data;
-    assign snoop_r.resp = 0;
-    assign snoop_r.last = dcache_snoop_io.cd_last;
-    assign snoop_r.user = 0;
-
-endmodule
\ No newline at end of file
diff --git a/src/core/CPUCore.sv b/src/core/CPUCore.sv
index a22eacb..b485ca4 100644
--- a/src/core/CPUCore.sv
+++ b/src/core/CPUCore.sv
@@ -9,20 +9,42 @@ module CPUCore (
 );
 
     CacheBus #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH, 1
+        `PADDR_SIZE, `XLEN, 1, 1
     ) icache_io();
     CacheBus #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH, `DCACHE_WAY_WIDTH
+        `PADDR_SIZE, `XLEN, 1, `DCACHE_WAY_WIDTH
     ) dcache_io();
     CacheBus #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH, 1
+        `PADDR_SIZE, `XLEN, 1, 1
     ) ducache_io();
     CacheBus #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH, 1
+        `PADDR_SIZE, `XLEN, 1, 1
     ) tlb_io();
-    NativeSnoopIO #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH+2
+    CacheBus #(
+        `PADDR_SIZE, `XLEN, 2, 1
+    ) master_io();
+    SnoopIO #(
+        `PADDR_SIZE, `XLEN, `L2MSHR_WIDTH
     ) dcache_snoop_io();
+    typedef logic [`PADDR_SIZE-1: 0] addr_t;
+    typedef logic [`XLEN-1: 0] data_t;
+    typedef logic [$clog2(`L2MSHR_SIZE)-1: 0] snoop_ack_id_t;
+    `SNOOP_TYPEDEF_AC_CHAN_T(snoop_ac_chan_t, addr_t)
+    `SNOOP_TYPEDEF_CD_CHAN_T(snoop_cd_chan_t, data_t)
+    `SNOOP_TYPEDEF_CR_CHAN_T(snoop_cr_chan_t)
+    `SNOOP_TYPEDEF_REQ_T(snoop_req_t, snoop_ac_chan_t, snoop_ack_id_t)
+    `SNOOP_TYPEDEF_RESP_T(snoop_resp_t, snoop_cd_chan_t, snoop_cr_chan_t, snoop_ack_id_t)
+    `SNOOP_TYPEDEF_REQ_T(mst_snoop_req_t, snoop_ac_chan_t, snoop_ack_id_t)
+    `SNOOP_TYPEDEF_RESP_T(mst_snoop_resp_t, snoop_cd_chan_t, snoop_cr_chan_t, snoop_ack_id_t)
+    snoop_req_t snoop_req;
+    snoop_resp_t snoop_resp;
+    mst_snoop_req_t mst_snoop_req;
+    mst_snoop_resp_t mst_snoop_resp;
+    `SNOOP_ASSIGN_FROM_REQ(dcache_snoop_io, snoop_req)
+    `SNOOP_ASSIGN_TO_RESP(snoop_resp, dcache_snoop_io)
+    `CACHE_ASSIGN_TO_AXI(axi, master_io)
+    assign mst_snoop_req = 0;
+
     IfuBackendIO ifu_backend_io();
     FsqBackendIO fsq_back_io();
     CommitBus commitBus();
@@ -43,7 +65,9 @@ module CPUCore (
                     .commitBus_out(commitBus),
                     .axi_io(dcache_io),
                     .fenceBus_o(fenceBus));
-    AxiInterface axi_interface(.*);
+    L2CacheWrapper #(
+        snoop_req_t, snoop_resp_t, mst_snoop_req_t, mst_snoop_resp_t
+    ) l2cache_wrapper (.*, .master_io(master_io.master));
     L2TLB l2_tlb(.*,
                 .csr_io(csr_l2_io), 
                 .flush(fsq_back_io.redirect.en), 
diff --git a/src/core/backend/Backend.sv b/src/core/backend/Backend.sv
index ce1ba68..e4bf2fb 100644
--- a/src/core/backend/Backend.sv
+++ b/src/core/backend/Backend.sv
@@ -11,7 +11,7 @@ module Backend(
     CsrTlbIO.csr csr_itlb_io,
     CsrL2IO.csr csr_l2_io,
     TlbL2IO.tlb dtlb_io,
-    NativeSnoopIO.master dcache_snoop_io,
+    SnoopIO.master dcache_snoop_io,
     ClintIO.cpu clint_io,
     FenceBus.backend fenceBus_o
 );
diff --git a/src/core/backend/lsu/LSU.sv b/src/core/backend/lsu/LSU.sv
index 378da8e..9041258 100644
--- a/src/core/backend/lsu/LSU.sv
+++ b/src/core/backend/lsu/LSU.sv
@@ -49,7 +49,7 @@ module LSU(
     input BackendCtrl backendCtrl,
     CacheBus.master axi_io,
     CacheBus.master ducache_io,
-    NativeSnoopIO.master snoop_io,
+    SnoopIO.master snoop_io,
     BackendRedirectIO.mem redirect_io,
     CsrTlbIO.tlb csr_ltlb_io,
     CsrTlbIO.tlb csr_stlb_io,
@@ -74,12 +74,12 @@ module LSU(
     LoadQueueIO load_queue_io();
 
     CacheBus #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH, 1
+        `PADDR_SIZE, `XLEN, 1, 1
     ) laxi_io();
     StoreUnitIO store_io();
     StoreQueueIO store_queue_io();
     CacheBus #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH, 1
+        `PADDR_SIZE, `XLEN, 1, 1
     ) saxi_io();
     StoreCommitIO store_commit_io();
     ViolationIO violation_io();
diff --git a/src/core/backend/lsu/dcache/DCacheMiss.sv b/src/core/backend/lsu/dcache/DCacheMiss.sv
index 99607ff..cb69044 100644
--- a/src/core/backend/lsu/dcache/DCacheMiss.sv
+++ b/src/core/backend/lsu/dcache/DCacheMiss.sv
@@ -9,6 +9,7 @@ interface DCacheMissIO;
     logic `N(`LOAD_PIPELINE) rfull;
 
     logic wen;
+    logic wdata_valid;
     logic `N(`PADDR_SIZE) waddr;
     logic `N(`PADDR_SIZE) waddr_pre;
     logic `N(`STORE_COMMIT_WIDTH) scIdx;
@@ -33,19 +34,19 @@ interface DCacheMissIO;
     logic `N(`PADDR_SIZE) refillAddr;
     logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) refillData;
     logic `N(`STORE_COMMIT_WIDTH) refill_scIdx;
+    DirectoryState refill_state;
 
     logic `N(`LOAD_REFILL_SIZE) lq_en;
     logic `ARRAY(`LOAD_REFILL_SIZE, `DCACHE_BITS) lqData;
     logic `ARRAY(`LOAD_REFILL_SIZE, `LOAD_QUEUE_WIDTH) lqIdx_o;
 
     modport miss (input ren, raddr, lqIdx, robIdx, req_success, replaceWay, refill_valid,
-                        wen, waddr, scIdx, wdata, wmask, raddr_pre, waddr_pre,
+                        wen, waddr, scIdx, wdata, wmask, raddr_pre, waddr_pre, wdata_valid,
 `ifdef RVA
                   input amo_en, output amo_refill,
 `endif
-                  output rfull, req, req_addr, wfull, 
-                        refill_en, refill_dirty, refillWay, refillAddr, refillData, refill_scIdx,
-                        lq_en, lqData, lqIdx_o);
+                  output rfull, req, req_addr, wfull, lq_en, lqData, lqIdx_o,
+        refill_en, refill_dirty, refillWay, refillAddr, refillData, refill_scIdx, refill_state);
 endinterface
 
 module DCacheMiss(
@@ -89,6 +90,16 @@ module DCacheMiss(
     logic refill_eq;
     logic w_invalid;
 
+    logic req_cache;
+    logic `N(`PADDR_SIZE) cache_addr;
+    logic `N($clog2(`DCACHE_LINE / `DATA_BYTE)) cacheIdx;
+    logic `ARRAY(`DCACHE_LINE / `DATA_BYTE, `XLEN) cacheData, req_data;
+    logic `ARRAY(`DCACHE_LINE / `DATA_BYTE, `DATA_BYTE) req_mask;
+    logic `N(`XLEN) expandMask;
+    logic `N(`XLEN) combine_cache_data;
+    logic `N(`DCACHE_WAY_WIDTH) req_way;
+    DirectoryState req_state;
+
 //load enqueue
     // 有三种情况
     // 1. 没有命中, 需要mshr_en和en有空闲
@@ -206,7 +217,7 @@ endgenerate
 
 // refill
     assign io.refill_en = en[head] & dataValid[head];
-    assign io.refill_dirty = |mask[head];
+    assign io.refill_state = req_state;
     assign io.refillWay = way[head];
     assign io.refillAddr = {addr[head], {`DCACHE_BANK_WIDTH{1'b0}}, 2'b0};
     assign io.refillData = data[head];
@@ -336,7 +347,7 @@ endgenerate
             end
             if(io.wen & ~w_invalid & (write_remain_valid | whit_combine))begin
                 scIdxs[widx] <= io.scIdx;
-                data_valid_all[widx] <= &wmask_all;
+                data_valid_all[widx] <= &wmask_all | io.wdata_valid;
                 wvalid[widx] <= 1'b1;
             end
             if(rlast)begin
@@ -363,9 +374,11 @@ endgenerate
 
 `ifdef RVA
     logic `N(`DCACHE_MSHR_SIZE) amo;
+    logic amo_req;
     always_ff @(posedge clk, posedge rst)begin
         if(rst == `RST)begin
             amo <= 0;
+            amo_req <= 0;
         end
         else begin
             if(io.amo_en & ~w_invalid & (write_remain_valid | whit_combine))begin
@@ -374,6 +387,9 @@ endgenerate
             if(io.refill_en & io.refill_valid)begin
                 amo[head] <= 1'b0;
             end
+            if(req_next & io.req_success)begin
+                amo_req <= amo[head];
+            end
         end
     end
 
@@ -384,15 +400,6 @@ endgenerate
 `endif
 
 // req
-    logic req_cache;
-    logic `N(`PADDR_SIZE) cache_addr;
-    logic `N($clog2(`DCACHE_LINE / `DATA_BYTE)) cacheIdx;
-    logic `ARRAY(`DCACHE_LINE / `DATA_BYTE, `XLEN) cacheData, req_data;
-    logic `ARRAY(`DCACHE_LINE / `DATA_BYTE, `DATA_BYTE) req_mask;
-    logic `N(`XLEN) expandMask;
-    logic `N(`XLEN) combine_cache_data;
-    logic `N(`DCACHE_WAY_WIDTH) req_way;
-
     assign io.req = en[head] & ~req_start;
     assign io.req_addr = {addr[head], {`DCACHE_BANK_WIDTH{1'b0}}, 2'b0};
     assign rlast = r_axi_io.r_valid & r_axi_io.r_last;
@@ -418,6 +425,7 @@ endgenerate
             req_way <= 0;
             req_valid_all <= 0;
             req_wvalid <= 0;
+            req_state <= 0;
         end
         else begin
             if(io.req)begin
@@ -458,6 +466,11 @@ endgenerate
         if(rlast)begin
             req_data <= data[head];
             req_mask <= mask[head];
+            req_state <= req_wvalid | req_valid_all 
+`ifdef RVA
+                        | amo_req
+`endif
+            ? 3'b111 : r_axi_io.r_resp[4: 2];
         end
     end
 
@@ -467,8 +480,12 @@ endgenerate
     assign r_axi_io.ar_len = `DCACHE_LINE / `DATA_BYTE - 1;
     assign r_axi_io.ar_size = $clog2(`DATA_BYTE);
     assign r_axi_io.ar_burst = 2'b01;
-    assign r_axi_io.ar_user = req_way;
-    assign r_axi_io.ar_snoop = req_valid_all ? `ACEOP_MAKE_UNIQUE :
+    assign r_axi_io.ar_user = 0;
+    assign r_axi_io.ar_snoop = 
+`ifdef RVA
+                               amo_req ? `ACEOP_READ_UNIQUE :
+`endif
+                               req_valid_all ? `ACEOP_MAKE_UNIQUE :
                                req_wvalid ? `ACEOP_READ_UNIQUE : `ACEOP_READ_SHARED;
 
     assign r_axi_io.r_ready = 1'b1;
diff --git a/src/core/backend/lsu/dcache/DCacheWay.sv b/src/core/backend/lsu/dcache/DCacheWay.sv
index 481581e..03979e1 100644
--- a/src/core/backend/lsu/dcache/DCacheWay.sv
+++ b/src/core/backend/lsu/dcache/DCacheWay.sv
@@ -4,56 +4,90 @@ module DCacheData(
     input logic clk,
     input logic rst,
     input logic `N(`LOAD_PIPELINE+1) tagv_en,
-    input logic `N(`DCACHE_WAY) tagv_we,
+    input logic `N(`DCACHE_WAY) tag_we,
+    input logic `N(`DCACHE_WAY) valid_we,
     input logic `ARRAY(`LOAD_PIPELINE+1, `DCACHE_SET_WIDTH) tagv_index,
+    input logic `ARRAY(`LOAD_PIPELINE+1, `DCACHE_SET_WIDTH) tagv_windex,
     input logic `N(`DCACHE_TAG+1) tagv_wdata,
     output logic `TENSOR(`LOAD_PIPELINE+1, `DCACHE_WAY, `DCACHE_TAG+1) tagv,
+    output DCacheMeta `N(`DCACHE_WAY) meta,
+    input DCacheMeta wmeta,
     input logic `N(`DCACHE_BANK) en,
     input logic `ARRAY(`DCACHE_BANK, `DCACHE_WAY * `DCACHE_BYTE) we,
     input logic `ARRAY(`DCACHE_BANK, `DCACHE_SET_WIDTH) index,
     input logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) wdata,
-    output logic `TENSOR(`DCACHE_BANK, `DCACHE_WAY, `DCACHE_BITS) data,
-    input logic dirty_en,
-    input logic `N(`DCACHE_SET_WIDTH) dirty_index,
-    output logic `N(`DCACHE_WAY) dirty,
-    input logic `N(`DCACHE_WAY) dirty_we,
-    input logic `N(`DCACHE_SET_WIDTH) dirty_windex,
-    input logic `N(`DCACHE_WAY) dirty_wdata
+    output logic `TENSOR(`DCACHE_BANK, `DCACHE_WAY, `DCACHE_BITS) data
 );
+    logic `TENSOR(`LOAD_PIPELINE+1, `DCACHE_WAY, `DCACHE_TAG) tag;
+    logic `ARRAY(`LOAD_PIPELINE+1, `DCACHE_WAY) valid;
 generate
     for(genvar i=0; i<`LOAD_PIPELINE+1; i++)begin
+        for(genvar j=0; j<`DCACHE_WAY; j++)begin
+            assign tagv[i][j][`DCACHE_TAG: 1] = tag[i][j];
+            assign tagv[i][j][0] = valid[i][j];
+        end
         SPRAM #(
-            .WIDTH(`DCACHE_WAY * (`DCACHE_TAG+1)),
+            .WIDTH(`DCACHE_WAY * `DCACHE_TAG),
             .DEPTH(`DCACHE_SET),
             .RESET(1),
             .BYTE_WRITE(1),
             .READ_LATENCY(1),
             .BYTES(`DCACHE_WAY)
-        ) tagv_ram (
+        ) tag_ram (
             .clk(clk),
             .rst(rst),
             .rst_sync(0),
             .en(tagv_en[i]),
             .addr(tagv_index[i]),
-            .rdata(tagv[i]),
-            .we(tagv_we),
-            .wdata({`DCACHE_WAY{tagv_wdata}}),
+            .rdata(tag[i]),
+            .we(tag_we),
+            .wdata({`DCACHE_WAY{tagv_wdata[`DCACHE_TAG: 1]}}),
             .ready()
         );
     end
-endgenerate
-
-    logic `N(`DCACHE_WAY) dirty_ram `N(`DCACHE_SET);
-    always_ff @(posedge clk)begin
-        if(dirty_en)begin
-            dirty <= dirty_ram[dirty_index];
-        end
-        for(int i=0; i<`DCACHE_WAY; i++)begin
-            if(dirty_we[i])begin
-                dirty_ram[dirty_windex][i] <= dirty_wdata[i];
-            end
-        end
+    for(genvar i=0; i<`LOAD_PIPELINE; i++)begin
+        MPRAM #(
+            .WIDTH(`DCACHE_WAY),
+            .DEPTH(`DCACHE_SET),
+            .READ_PORT(1),
+            .WRITE_PORT(1),
+            .RESET(1),
+            .BYTE_WRITE(1),
+            .BYTES(`DCACHE_WAY)
+        ) valid_ram (
+            .clk,
+            .rst,
+            .rst_sync(0),
+            .en(tagv_en[i]),
+            .raddr(tagv_index[i]),
+            .rdata(valid[i]),
+            .we(valid_we[i]),
+            .waddr(tagv_windex[i]),
+            .wdata({`DCACHE_WAY{tagv_wdata[0]}}),
+            .ready()
+        );
     end
+    MPRAM #(
+        .WIDTH(`DCACHE_WAY * $bits(DCacheMeta)),
+        .DEPTH(`DCACHE_SET),
+        .READ_PORT(1),
+        .WRITE_PORT(1),
+        .RESET(1),
+        .BYTE_WRITE(1),
+        .BYTES(`DCACHE_WAY)
+    ) meta_ram (
+        .clk,
+        .rst,
+        .rst_sync(0),
+        .en(tagv_en[`LOAD_PIPELINE]),
+        .raddr(tagv_index[`LOAD_PIPELINE]),
+        .rdata(meta),
+        .we(valid_we[`LOAD_PIPELINE]),
+        .waddr(tagv_windex[`LOAD_PIPELINE]),
+        .wdata({`DCACHE_WAY{wmeta}}),
+        .ready()
+    );
+endgenerate
 
 generate
     for(genvar i=0; i<`DCACHE_BANK; i++)begin
diff --git a/src/core/backend/lsu/dcache/ReplaceQueue.sv b/src/core/backend/lsu/dcache/ReplaceQueue.sv
index 14b0cd2..e17f3ce 100644
--- a/src/core/backend/lsu/dcache/ReplaceQueue.sv
+++ b/src/core/backend/lsu/dcache/ReplaceQueue.sv
@@ -3,7 +3,7 @@
 interface ReplaceQueueIO;
     logic en;
     logic refill_en;
-    logic refill_dirty;
+    DirectoryState refill_state;
     logic `N(`DCACHE_TAG+`DCACHE_SET_WIDTH) addr;
     logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) data;
     logic `N(`DCACHE_REPLACE_WIDTH) idx;
@@ -15,12 +15,13 @@ interface ReplaceQueueIO;
     logic `N(`DCACHE_REPLACE_WIDTH) replace_idx;
 
     logic snoop_en;
-    logic snoop_ready;
+    logic snoop_clean;
     logic snoop_hit;
+    DirectoryState snoop_state;
     logic `N(`PADDR_SIZE) snoop_addr;
     logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) snoop_data;
 
-    modport queue (input en, refill_en, refill_dirty, addr, data, replace_idx, waddr, snoop_data, snoop_ready, output idx, whit,  full, snoop_en, snoop_addr);
+    modport queue (input en, refill_en, refill_state, addr, data, replace_idx, waddr, snoop_en, snoop_clean, snoop_addr, output idx, whit, full, snoop_data, snoop_hit, snoop_state);
     modport miss (input full, idx, output replace_idx);
 endinterface
 
@@ -28,8 +29,7 @@ module ReplaceQueue(
     input logic clk,
     input logic rst,
     ReplaceQueueIO.queue io,
-    CacheBus.masterw w_axi_io,
-    NativeSnoopIO.master snoop_io
+    CacheBus.masterw w_axi_io
 );
     localparam TRANSFER_BANK = `DCACHE_LINE / `DATA_BYTE;
     typedef struct packed {
@@ -40,7 +40,8 @@ module ReplaceQueue(
     ReplaceState replace_state;
 
     ReplaceEntry entrys `N(`DCACHE_REPLACE_SIZE);
-    logic `N(`DCACHE_REPLACE_SIZE) en, dataValid, dirty, prior;
+    logic `N(`DCACHE_REPLACE_SIZE) en, dataValid, prior;
+    DirectoryState `N(`DCACHE_REPLACE_SIZE) state;
     logic `N(`DCACHE_REPLACE_SIZE) valid, prior_valid;
     logic `N(`DCACHE_REPLACE_WIDTH) freeIdx, validIdx, priorIdx, processIdx, processIdx_pre;
     logic full;
@@ -64,7 +65,7 @@ module ReplaceQueue(
             dataValid <= 0;
             prior <= 0;
             en <= 0;
-            dirty <= 0;
+            state <= 0;
         end
         else begin
             if(io.en & ~(|hit) & ~(&en))begin
@@ -74,9 +75,13 @@ module ReplaceQueue(
                 prior[freeIdx] <= 1'b1;
             end
 
+            if(io.snoop_en & io.snoop_clean & (|snoop_hit))begin
+                en[snoop_hit_idx] <= 1'b0;
+            end
+
             if(io.refill_en)begin
                 dataValid[io.replace_idx] <= 1'b1;
-                dirty[io.replace_idx] <= io.refill_dirty;
+                state[io.replace_idx] <= io.refill_state;
             end
 
             if(retire_last)begin
@@ -130,7 +135,7 @@ endgenerate
             IDLE: begin
                 if(|valid)begin
                     aw_valid <= 1'b1;
-                    aw_dirty <= dirty[processIdx_pre];
+                    aw_dirty <= state[processIdx_pre].dirty;
                     replace_state <= ADDRESS;
                     processEntry <= entrys[processIdx_pre];
                     processIdx <= processIdx_pre;
@@ -184,11 +189,11 @@ endgenerate
     assign w_axi_io.aw_valid = aw_valid;
     assign w_axi_io.aw_id = 0;
     assign w_axi_io.aw_addr = {processEntry.addr, {`DCACHE_LINE_WIDTH{1'b0}}};
-    assign w_axi_io.aw_len = ~aw_dirty ? 0 : `DCACHE_LINE / `DATA_BYTE - 1;
+    assign w_axi_io.aw_len = `DCACHE_LINE / `DATA_BYTE - 1;
     assign w_axi_io.aw_size = $clog2(`DATA_BYTE);
     assign w_axi_io.aw_burst = 2'b01;
-    assign w_axi_io.aw_user = aw_dirty;
-    assign w_axi_io.aw_snoop = aw_dirty ? `ACEOP_WRITE_BACK : `ACEOP_WRITE_EVICT;
+    assign w_axi_io.aw_user = 0;
+    assign w_axi_io.aw_snoop = aw_dirty ? `ACEOP_WRITE_CLEAN : `ACEOP_WRITE_EVICT;
 
     assign w_axi_io.w_data = processEntry.data[widx];
     assign w_axi_io.w_strb = {`DATA_BYTE{1'b1}};
@@ -199,103 +204,30 @@ endgenerate
     assign w_axi_io.b_ready = 1'b1;
 
 // snoop
-    typedef struct packed {
-        logic `N(`DCACHE_SNOOP_ID_WIDTH) id;
-        logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) data;
-    } SnoopEntry;
-    logic `N(`DCACHE_SNOOP_SIZE) snoop_en, snoop_data_valid, snoop_valid, snoop_issue;
-    logic `N(`PADDR_SIZE) snoop_addr `N(`DCACHE_SNOOP_SIZE);
-    SnoopEntry `N(`DCACHE_SNOOP_SIZE) snoopEntrys;
-    logic snoop_en_s2, snoop_en_s3;
-    logic snoop_replace_hit;
-    logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) snoop_replace_data;
-    logic `N(`DCACHE_SNOOP_WIDTH) snoop_valid_idx, snoop_process_idx, snoop_free_idx, snoop_busy_idx;
-    logic `N(`DCACHE_SNOOP_WIDTH) snoop_busy_idx_s2, snoop_busy_idx_s3;
-    logic snoop_process;
-    logic cd_valid, cd_last;
-    logic `N(`DCACHE_SNOOP_ID_WIDTH) cd_user;
+    logic `N(`DCACHE_REPLACE_SIZE) snoop_hit;
+    logic `N(`DCACHE_REPLACE_WIDTH) snoop_hit_idx;
+    logic `TENSOR(`DCACHE_REPLACE_SIZE, `DCACHE_BANK, `DCACHE_BITS) replace_data;
     logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) snoop_data;
-    logic `N($clog2(TRANSFER_BANK)) snoopIdx;
-
-    assign snoop_valid = snoop_en & snoop_data_valid;
-    PEncoder #(`DCACHE_SNOOP_SIZE) encoder_snoop_idx (snoop_valid, snoop_valid_idx);
-    PEncoder #(`DCACHE_SNOOP_SIZE) encoder_snoop_free_idx (~snoop_en, snoop_free_idx);
-    PEncoder #(`DCACHE_SNOOP_SIZE) encoder_snoop_busy_idx (snoop_en & ~snoop_issue, snoop_busy_idx);
-    assign io.snoop_en = |(snoop_en & ~snoop_issue);
-    assign io.snoop_addr = snoop_addr[snoop_busy_idx];
+    DirectoryState snoop_state;
 
-    always_ff @(posedge clk)begin
-        snoop_en_s2 <= io.snoop_en & io.snoop_ready;
-        snoop_en_s3 <= snoop_en_s2;
-        snoop_busy_idx_s2 <= snoop_busy_idx;
-        snoop_busy_idx_s3 <= snoop_busy_idx_s2;
-        snoop_replace_hit <= io.whit;
-        snoop_replace_data <= entrys[io.idx].data;
-    end
-    always_ff @(posedge clk, posedge rst)begin
-        if(rst == `RST)begin
-            snoop_en <= 0;
-            snoop_data_valid <= 0;
-            snoop_issue <= 0;
-        end
-        else begin
-            if(snoop_io.ac_valid & snoop_io.ac_ready)begin
-                snoop_en[snoop_free_idx] <= 1'b1;
-                snoopEntrys[snoop_free_idx].id <= snoop_io.ac_user;
-                snoop_issue[snoop_free_idx] <= 1'b0;
-                snoop_addr[snoop_free_idx] <= snoop_io.ac_addr;
-            end
-            if(snoop_en_s3)begin
-                snoop_data_valid[snoop_busy_idx_s3] <= 1'b1;
-                snoopEntrys[snoop_busy_idx_s3].data <= snoop_replace_hit ? snoop_replace_data : io.snoop_data;
-            end
-            if(io.snoop_en & io.snoop_ready)begin
-                snoop_issue[snoop_busy_idx] <= 1'b1;
-            end
-            if(cd_last)begin
-                snoop_en[snoop_process_idx] <= 1'b0;
-                snoop_data_valid[snoop_process_idx] <= 1'b0;
-            end
-        end
+generate
+    for(genvar i=0; i<`DCACHE_REPLACE_SIZE; i++)begin
+        assign snoop_hit[i] = en[i] & dataValid[i] & (entrys[i].addr == io.snoop_addr`DCACHE_BLOCK_BUS);
+        assign replace_data[i] = entrys[i].data;
     end
-    always_ff @(posedge clk, posedge rst)begin
-        if(rst == `RST)begin
-            cd_valid <= 1'b0;
-            cd_last <= 1'b0;
-            snoopIdx <= 0;
-            cd_user <= 0;
-            snoop_process <= 1'b0;
-            snoop_data <= 0;
-            snoop_process_idx <= 0;
-        end
-        else begin
-            if(!snoop_process && (|snoop_valid))begin
-                snoop_data <= snoopEntrys[snoop_valid_idx].data;
-                snoop_process_idx <= snoop_valid_idx;
-                cd_valid <= 1'b1;
-                cd_user <= snoopEntrys[snoop_valid_idx].id;
-            end
-            if(snoop_io.cd_valid & snoop_io.cd_ready)begin
-                snoopIdx <= snoopIdx + 1;
-                if(snoopIdx == TRANSFER_BANK - 2)begin
-                    cd_last <= 1'b1;
-                end
-                else begin
-                    cd_last <= 1'b0;
-                end
-                if(cd_last)begin
-                    snoop_process <= 1'b0;
-                    cd_valid <= 1'b0;
-                end
-            end
+endgenerate
+    Encoder #(`DCACHE_REPLACE_SIZE) encoder_snoop (snoop_hit, snoop_hit_idx);
+    OldestSelect #(`DCACHE_REPLACE_SIZE, 1, `DCACHE_BANK * `DCACHE_BITS) select_snoop_data (snoop_hit, replace_data, , snoop_data);
+    OldestSelect #(`DCACHE_REPLACE_SIZE, 1, $bits(DirectoryState)) select_snoop_state (snoop_hit, state, , snoop_state);
+    always_ff @(posedge clk)begin
+        if (io.snoop_en)begin
+            io.snoop_hit <= |snoop_hit;
+            io.snoop_data <= snoop_data;
+            io.snoop_state <= snoop_state;
         end
     end
 
-    assign snoop_io.ac_ready = ~(&snoop_en);
-    assign snoop_io.cd_valid = cd_valid;
-    assign snoop_io.cd_last = cd_last;
-    assign snoop_io.cd_data = snoop_data[snoopIdx];
-    assign snoop_io.cd_user = cd_user;
+
 
 `ifdef DIFFTEST
     `LOG_ARRAY(T_DCACHE, dbg_data, newEntry.data, TRANSFER_BANK)
diff --git a/src/core/backend/lsu/dcache/dcache.sv b/src/core/backend/lsu/dcache/dcache.sv
index 6a0a35f..104d471 100644
--- a/src/core/backend/lsu/dcache/dcache.sv
+++ b/src/core/backend/lsu/dcache/dcache.sv
@@ -9,12 +9,13 @@ module DCache(
     DCacheAmoIO.dcache amo_io,
 `endif
     CacheBus.master axi_io,
-    NativeSnoopIO.master snoop_io,
+    SnoopIO.master snoop_io,
     input BackendCtrl backendCtrl
 );
 
     logic `ARRAY(`LOAD_PIPELINE, `DCACHE_SET_WIDTH) loadIdx;
     logic `ARRAY(`LOAD_PIPELINE+1, `DCACHE_SET_WIDTH) tagvIdx;
+    logic `ARRAY(`LOAD_PIPELINE+1, `DCACHE_SET_WIDTH) tagvWIdx;
     logic `ARRAY(`LOAD_PIPELINE, `DCACHE_LINE_WIDTH-2) loadOffset;
     logic `ARRAY(`LOAD_PIPELINE, `DCACHE_BANK) loadBankDecode;
     logic `N(`DCACHE_BANK) loadBank;
@@ -37,6 +38,11 @@ module DCache(
     logic whit;
     logic `N(`DCACHE_WAY_WIDTH) w_wayIdx, missWay_encode;
     logic `N(`LOAD_PIPELINE) write_valid;
+    logic write_invalid;
+    logic snoop_invalid; // CLEAN_INVALID, READ_UNIQUE
+    logic snoop_share; // READ_SHARED
+    logic `N(`DCACHE_WAY) w_state_errors;
+    DCacheMeta select_meta;
 
     logic refill_en_n;
     logic `N(`DCACHE_WAY) refill_way;
@@ -44,8 +50,14 @@ module DCache(
     logic `N(`PADDR_SIZE) refill_addr_n;
     logic `N(`DCACHE_BLOCK_SIZE) replace_addr;
 
-    logic snoop_req;
-    logic `N(`PADDR_SIZE) snoop_addr;
+    logic ac_ready, cr_valid, cd_valid, cd_last;
+    DirectoryState cr_state;
+    logic snoop_req, snoop_req_n;
+    logic `N(`PADDR_SIZE) snoop_addr, snoop_addr_n;
+    logic snoop_hit, snoop_cache_hit, snoop_replace_hit;
+    logic snoop_share_n, snoop_invalid_n;
+    logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) snoop_replace_data, snoop_data;
+    logic `N(`DCACHE_BANK_WIDTH) snoop_data_idx;
     logic `N(`DCACHE_WAY) way_dirty;
 
 `ifdef RVA
@@ -69,7 +81,7 @@ module DCache(
     DCacheMissIO miss_io();
     ReplaceQueueIO replace_queue_io();
     CacheBus #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH, `DCACHE_WAY_WIDTH
+        `PADDR_SIZE, `XLEN, 1, 1
     ) dcache_axi_io();
     ReplaceIO #(
         .DEPTH(`DCACHE_SET),
@@ -102,8 +114,10 @@ endgenerate
     ParallelOR #(.WIDTH(`DCACHE_BANK), .DEPTH(`LOAD_PIPELINE)) or_bank(loadBankDecode, loadBank);
 
     logic `N(`LOAD_PIPELINE+1) tagv_en;
-    logic `N(`DCACHE_WAY) tagv_we;
+    logic `N(`DCACHE_WAY) tag_we, valid_we;
     logic `TENSOR(`LOAD_PIPELINE+1, `DCACHE_WAY, `DCACHE_TAG+1) tagv;
+    DCacheMeta `N(`DCACHE_WAY) meta;
+    DCacheMeta wmeta;
     logic `TENSOR(`DCACHE_BANK, `DCACHE_WAY, `DCACHE_BYTE) data_we;
     logic `ARRAY(`DCACHE_BANK, `DCACHE_SET_WIDTH) data_index;
     logic `N(`DCACHE_SET_WIDTH) refillIdx;
@@ -112,22 +126,30 @@ endgenerate
     logic `N(`DCACHE_WAY) dirty_we, dirty_wdata;
 
 generate
-    
+    // TODO: 每个way使用单独的index，refill和snoop不同way时可以同时写入
     for(genvar i=0; i<`LOAD_PIPELINE; i++)begin
         assign tagv_en[i] = rio.req[i];
-        assign tagvIdx[i] = miss_io.refill_en & miss_io.refill_valid ? miss_io.refillAddr`DCACHE_SET_BUS :
-                            loadIdx[i];
+        assign tagvIdx[i] = loadIdx[i];
+        assign tagvWIdx[i] = snoop_invalid & (|w_wayhit) ? widx : miss_io.refillAddr`DCACHE_SET_BUS;
     end
     assign tagv_en[`LOAD_PIPELINE] = wreq | miss_io.refill_en;
     assign tagvIdx[`LOAD_PIPELINE] = wreq ? widx : miss_io.refillAddr`DCACHE_SET_BUS;
-    assign tagv_we = {`DCACHE_WAY{miss_io.refill_valid & miss_io.refill_en}} & refill_way;
+    assign tagvWIdx[`LOAD_PIPELINE] = snoop_invalid & (|w_wayhit) ? widx : miss_io.refillAddr`DCACHE_SET_BUS;
+    // TODO: 只有原来不是share才需要写入(snoop_share)
+    assign tag_we = {`DCACHE_WAY{miss_io.refill_valid & miss_io.refill_en}} & refill_way;
+    assign valid_we = {`DCACHE_WAY{miss_io.refill_valid & miss_io.refill_en}} & refill_way |
+                      {`DCACHE_WAY{snoop_invalid | snoop_share}} & w_wayhit;
+    assign wmeta.v = miss_io.refill_valid & miss_io.refill_en & ~snoop_invalid | snoop_share;
+    assign wmeta.share = snoop_share | miss_io.refill_state.share;
+    assign wmeta.owned = snoop_share & whit ? select_meta.owned : miss_io.refill_state.owner;
+    assign wmeta.dirty = snoop_share & whit ? select_meta.dirty : miss_io.refill_state.dirty;
     for(genvar i=0; i<`DCACHE_BANK; i++)begin
         for(genvar j=0; j<`DCACHE_WAY; j++)begin
             assign data_we[i][j] = {`DCACHE_BYTE{cache_wreq & cache_wway[j]}} & wmask_n[i] |
                                    {`DCACHE_BYTE{miss_io.refill_valid & miss_io.refill_en & refill_way[j]}};
             assign rdata[j][i] = data_rdata[i][j];
         end
-        assign data_index[i] = snoop_req ? snoop_addr`DCACHE_SET_BUS : 
+        assign data_index[i] = snoop_share & whit ? snoop_addr`DCACHE_SET_BUS : 
                                |data_we[i] ? refillIdx : 
 `ifdef RVA
                                amo_en[i] ? amo_io.paddr`DCACHE_SET_BUS :
@@ -149,25 +171,23 @@ endgenerate
         .clk,
         .rst,
         .tagv_en,
-        .tagv_we,
+        .tag_we,
+        .valid_we,
         .tagv_index(tagvIdx),
+        .tagv_windex(tagvWIdx),
         .tagv_wdata({miss_io.refillAddr`DCACHE_TAG_BUS, 1'b1}),
         .tagv,
+        .meta,
+        .wmeta,
 `ifdef RVA
-        .en((loadBank | amo_en | {`DCACHE_BANK{miss_io.refill_en | snoop_req}})),
+        .en((loadBank | amo_en | {`DCACHE_BANK{miss_io.refill_en | snoop_req_n}})),
 `else
-        .en((loadBank | {`DCACHE_BANK{miss_io.refill_en | snoop_req}})),
+        .en((loadBank | {`DCACHE_BANK{miss_io.refill_en | snoop_req_n}})),
 `endif
         .we(data_we),
         .index(data_index),
         .wdata(refillData),
-        .data(data_rdata),
-        .dirty_en(miss_io.refill_en),
-        .dirty_index(miss_io.refillAddr`DCACHE_SET_BUS),
-        .dirty(way_dirty),
-        .dirty_we,
-        .dirty_windex(refillIdx),
-        .dirty_wdata
+        .data(data_rdata)
     );
 generate
     for(genvar i=0; i<`LOAD_PIPELINE; i++)begin
@@ -185,9 +205,9 @@ generate
 
         logic `N(`DCACHE_BYTE) load_wmask;
         assign load_wmask = wmask_n[loadOffset[i]];
-        assign write_valid[i] = miss_io.refill_en & ~(cache_wreq & (|w_wayhit)) & ~wio.req |
-                                snoop_req |
-                                cache_wreq & (|w_wayhit) & (|load_wmask)
+        assign write_valid[i] = miss_io.refill_en & ~(cache_wreq & whit) & ~wio.req |
+                                snoop_req_n & whit |
+                                cache_wreq & whit & (|load_wmask)
 `ifdef RVA
                                 | amo_en[loadOffset[i]]
 `endif
@@ -250,14 +270,13 @@ endgenerate
     assign rio.lqIdx_o = miss_io.lqIdx_o;
 
 // write
-    logic write_invalid;
 `ifdef RVA
-    assign wreq = (wio.req | replace_queue_io.snoop_en | amo_io.req) & ~amo_req;
-    assign waddr = replace_queue_io.snoop_en ? replace_queue_io.snoop_addr : 
+    assign wreq = (wio.req | snoop_req | amo_io.req) & ~amo_req;
+    assign waddr = snoop_req ? replace_queue_io.snoop_addr : 
                    wio.req ? wio.paddr : amo_io.paddr;
 `else
-    assign wreq = wio.req | replace_queue_io.snoop_en;
-    assign waddr = replace_queue_io.snoop_en ? replace_queue_io.snoop_addr : wio.paddr;
+    assign wreq = wio.req | snoop_req;
+    assign waddr = snoop_req ? replace_queue_io.snoop_addr : wio.paddr;
 `endif
     assign wdata = wio.data;
     assign wmask = wio.mask;
@@ -265,20 +284,21 @@ endgenerate
     
     assign replace_io.miss_index = miss_io.req_addr`DCACHE_SET_BUS;
 `ifdef RVA
-    assign wio.valid = ~replace_queue_io.snoop_en & ~amo_req;
+    assign wio.valid = ~snoop_req & ~amo_req;
 `else
-    assign wio.valid = ~replace_queue_io.snoop_en;
+    assign wio.valid = ~snoop_req;
 `endif
 
 generate
     for(genvar i=0; i<`DCACHE_WAY; i++)begin
         assign wtagv[i] = tagv[`LOAD_PIPELINE][i];
         assign w_wayhit[i] = wtagv[i][0] & (wtagv[i][`DCACHE_TAG: 1] == waddr_n`DCACHE_TAG_BUS);
+        assign w_state_errors[i] = meta[i].share | ~meta[i].owned;
     end
 endgenerate
     logic `N(`STORE_COMMIT_WIDTH) scIdx_n;
     always_ff @(posedge clk)begin
-        wreq_n <= wio.req & ~replace_queue_io.snoop_en & ~amo_req;
+        wreq_n <= wio.req & ~snoop_req & ~amo_req;
         miss_req_n <= miss_io.req;
         waddr_n <= waddr;
 `ifdef RVA
@@ -294,6 +314,10 @@ endgenerate
         end
 `endif
         scIdx_n <= wio.scIdx;
+        snoop_invalid <= snoop_io.ac_valid & snoop_io.ac_ready &
+                         ((snoop_io.ac_snoop == `ACEOP_READ_UNIQUE) | 
+                        (snoop_io.ac_snoop == `ACEOP_CLEAN_INVALID));
+        snoop_share <= snoop_io.ac_valid & snoop_io.ac_ready & (snoop_io.ac_snoop == `ACEOP_READ_SHARED);
         // write_invalid <= miss_req_n && (waddr_n`DCACHE_BLOCK_BUS == waddr`DCACHE_BLOCK_BUS);
     end
 `ifdef RVA
@@ -308,9 +332,10 @@ endgenerate
     assign replace_queue_io.waddr = miss_io.req_addr;
 
     // write miss
-    assign whit = (|w_wayhit);
+    assign whit = (|(w_wayhit & ~w_state_errors));
     Encoder #(`DCACHE_WAY) encoder_way (w_wayhit, w_wayIdx);
     Encoder #(`DCACHE_WAY) encoder_miss_way (replace_io.miss_way, missWay_encode);
+    OldestSelect #(`DCACHE_WAY, 1, $bits(DCacheMeta)) selector_meta (w_wayhit, meta, , select_meta);
     assign miss_io.wen = ~whit & wreq_n;
     assign miss_io.waddr = waddr_n;
     assign miss_io.waddr_pre = waddr;
@@ -332,7 +357,7 @@ endgenerate
     Decoder #(`DCACHE_WAY) decoder_refill_way (miss_io.refillWay, refill_way);
 
     // refill
-    assign miss_io.refill_valid = ~(cache_wreq & (|cache_wway)) & ~wio.req & ~snoop_req & ~replace_queue_io.snoop_en
+    assign miss_io.refill_valid = ~(cache_wreq & whit) & ~wio.req & ~snoop_req & ~snoop_req_n
 `ifdef RVA
     & ~amo_io.req
 `endif
@@ -350,29 +375,88 @@ endgenerate
         refill_addr_n <= miss_io.refillAddr;
     end
     assign replace_queue_io.refill_en = refill_en_n;
-    assign replace_queue_io.refill_dirty = wtagv[refill_way_n][0] & way_dirty[refill_way_n];
+    assign replace_queue_io.refill_state = meta[refill_way_n].v ? meta[refill_way_n][2: 0] : 0;
     assign replace_queue_io.addr = replace_addr;
     assign replace_queue_io.data = rdata[refill_way_n];
 
-    // BUG: rlast但是没有refill进dcache时snoop访问不到该项
-    assign replace_queue_io.snoop_data = rdata[refill_way_n];
-`ifdef RVA
-    assign replace_queue_io.snoop_ready = ~amo_req;
-`else
-    assign replace_queue_io.snoop_ready = 1'b1;
-`endif
+// snoop
     always_ff @(posedge clk)begin
-        snoop_req <= replace_queue_io.snoop_en;
-        snoop_addr <= replace_queue_io.snoop_addr;
+        snoop_addr <= snoop_io.ac_addr;
+        snoop_addr_n <= snoop_addr;
+        snoop_req_n <= snoop_io.ac_valid & snoop_io.ac_ready;
+        snoop_replace_data <= replace_queue_io.snoop_data;
+        snoop_cache_hit <= snoop_req_n & whit;
+        snoop_replace_hit <= snoop_req_n & replace_queue_io.snoop_hit;
+        snoop_hit <= snoop_cache_hit | snoop_replace_hit;
+        snoop_share_n <= snoop_share;
     end
+    always_ff @(posedge clk, posedge rst)begin
+        if (rst == `RST)begin
+            ac_ready <= 1'b1;
+            cr_valid <= 1'b0;
+            cd_valid <= 1'b0;
+            cd_last <= 1'b0;
+            cr_state <= 0;
+            snoop_data <= 0;
+            snoop_data_idx <= 0;
+            snoop_invalid_n <= 0;
+        end
+        else begin
+            if(snoop_io.ac_valid & ac_ready)begin
+                ac_ready <= 1'b0;
+            end
+            if(snoop_invalid_n & snoop_io.cr_valid & snoop_io.cr_ready |
+               snoop_io.cd_valid & snoop_io.cd_ready & snoop_io.cd_last)begin
+                ac_ready <= 1'b1;
+            end
+
+            if(snoop_req_n)begin
+                cr_valid <= 1'b1;
+                cr_state <= whit ? select_meta[2: 0] : replace_queue_io.snoop_state;
+                snoop_invalid_n <= snoop_invalid;
+            end
+            if(cr_valid & snoop_io.cr_ready)begin
+                cr_valid <= 1'b0;
+            end
+
+            if((snoop_cache_hit | snoop_replace_hit) & snoop_share_n)begin
+                cd_valid <= 1'b1;
+                snoop_data <= snoop_cache_hit ? rdata[w_wayIdx] : snoop_replace_data;
+            end
+            if(cd_valid & snoop_io.cd_ready & snoop_io.cd_last)begin
+                cd_valid <= 1'b0;
+            end
 
-    // amo
+            if(cd_valid & snoop_io.cd_ready)begin
+                snoop_data_idx <= snoop_data_idx + 1;
+                if(snoop_data_idx == `DCACHE_BANK - 2)begin
+                    cd_last <= 1'b1;
+                end
+                else begin
+                    cd_last <= 1'b0;
+                end
+            end
+        end
+    end
+    assign snoop_req = snoop_io.ac_valid & snoop_io.ac_ready;
+    assign replace_queue_io.snoop_en = snoop_req;
+    assign replace_queue_io.snoop_clean = snoop_io.ac_snoop == `ACEOP_CLEAN_INVALID;
+    assign replace_queue_io.snoop_addr = snoop_io.ac_addr;
+    assign snoop_io.ac_ready = ac_ready;
+    assign snoop_io.cr_valid = cr_valid;
+    assign snoop_io.cr_resp = {cr_state, 2'b00};
+    assign snoop_io.cd_valid = cd_valid;
+    assign snoop_io.cd_data = snoop_data[snoop_data_idx];
+    assign snoop_io.cd_last = cd_last;
+
+
+// amo
 `ifdef RVA
     // TODO: currently only one core, not implement lr/sc
     Decoder #(`DCACHE_BANK) decoder_amo_bank(amo_io.paddr`DCACHE_BANK_BUS, amo_bank);
     assign amo_en = {`DCACHE_BANK{amo_io.req}} & amo_bank;
     always_ff @(posedge clk)begin
-        amo_req <= amo_io.req & ~wio.req & ~replace_queue_io.snoop_en;
+        amo_req <= amo_io.req & ~wio.req & ~snoop_req;
         amo_addr <= amo_io.paddr;
         amo_mask <= amo_io.mask;
         amo_data <= amo_io.data;
@@ -384,7 +468,7 @@ endgenerate
     end
     assign amo_rdata = rdata[w_wayIdx][amo_addr`DCACHE_BANK_BUS];
 
-    assign amo_io.ready = ~wio.req & ~replace_queue_io.snoop_en;
+    assign amo_io.ready = ~wio.req & ~snoop_req;
     assign amo_io.success = amo_req & whit;
     assign amo_io.rdata = issc ? !sc_match : amo_rdata;
     assign miss_io.amo_en = amo_req & ~whit;
diff --git a/src/core/mem/cache/Directory.sv b/src/core/mem/cache/Directory.sv
new file mode 100644
index 0000000..b005c7b
--- /dev/null
+++ b/src/core/mem/cache/Directory.sv
@@ -0,0 +1,204 @@
+`include "../../../defines/defines.svh"
+
+// 目录写入时机:
+// 在读目录后实际上便可以进行目录更新，因为同时mshr不会更新同一个set
+// slave读: 
+// 如果读slave hit,则更新local为shared,
+// 如果l2 hit, 如果是L2 Cache且来自dcache，则更新local并且删除l2
+// 如果来自icache则不改变目录
+// 如果slave miss且l2 miss, 则更新l2和local(根据dcache)
+// slave写:
+// 如果是ReadUnique,并且命中l2(此时以l2中的状态为准,忽略dcache提供的SU信息)且当前状态为S,
+// 那么需要转发给L3,请求变更为CleanUnique。如果是L2并且当前状态为U,则省略转发的步骤
+// 无论是否命中l2,都需要更新local,并且删除l2 Directory(因为只有dcache会发ReadUnique)
+// 如果是MakeUnique, 省略实际读数据的过程，但是仍然需要按照ReadUnique的过程转发请求和更新目录
+// slave替换:
+// 如果是l2并且命中那么写入l2 Directory,并且Shared状态根据l2,Dirty状态根据dcache
+// 如果miss，那么正常写入替换路即可
+// 如果是l3,正常写入Directory
+// 所有替换都需要删除local，因为只有owner才会发出替换请求  
+
+// 写入local时机:
+// 当读取时，local命中，状态变为shared，directory命中，状态根据directory的状态
+// 都没命中，根据master传过来的状态
+// 如果local没有命中，则需要进行替换，根据替换路的信息决定是否要发送snoop，并且如果是owner还需要进行替换
+// 当替换时，删除local
+module LocalDirectory #(
+    parameter SLAVE_NUM = 1,
+    parameter WAY = 4,
+    parameter SET = 64,
+    parameter OFFSET = 32,
+    parameter LLC = 1,
+    parameter OFFSET_WIDTH = $clog2(OFFSET),
+    parameter SET_WIDTH = $clog2(SET),
+    parameter TAG_WIDTH = `PADDR_SIZE - OFFSET_WIDTH - SET_WIDTH,
+    parameter SLAVE_WIDTH = idxWidth(SLAVE_NUM)
+)(
+    input logic clk,
+    input logic rst,
+    L2MSHRSlaveIO.slaver mshr_slave_io
+);
+
+    typedef struct packed {
+        logic owned; // not llc
+        logic `N(SLAVE_WIDTH) owner;
+        logic `N(SLAVE_NUM) valid;
+        logic share;
+        logic `N(TAG_WIDTH) tag;
+    } Entry;
+
+    parameter ENTRY_SIZE = TAG_WIDTH + 1 + (LLC ? 0 : 1) + SLAVE_NUM + SLAVE_WIDTH;
+    logic `ARRAY(WAY, ENTRY_SIZE) lookup_entry;
+    logic `N(ENTRY_SIZE) select_entry, replace_data;
+    logic select_hit;
+    logic `N(WAY) tag_hits, wway_dec;
+    logic en_n;
+    logic `N(`PADDR_SIZE) raddr_n;
+
+    always_ff @(posedge clk)begin
+        raddr_n <= mshr_slave_io.raddr;
+        en_n <= mshr_slave_io.request;
+    end
+
+
+    ReplaceIO #(.DEPTH(SET), .WAY_NUM(WAY)) replace_io();
+    Replace #(
+        .DEPTH(SET),
+        .WAY_NUM(WAY)
+    ) replace (.*);
+    assign replace_io.miss_index = mshr_slave_io.raddr[OFFSET_WIDTH +: SET_WIDTH];
+    assign replace_io.hit_en = select_hit & en_n | mshr_slave_io.we & ~mshr_slave_io.request;
+    assign replace_io.hit_way = mshr_slave_io.we & ~mshr_slave_io.request ? 
+        (|mshr_slave_io.wdata[TAG_WIDTH+1 +: SLAVE_NUM] ? mshr_slave_io.wway : ~mshr_slave_io.wway) : tag_hits;
+    assign replace_io.hit_index = raddr_n[OFFSET_WIDTH +: SET_WIDTH];
+
+generate
+    for(genvar i=0; i<WAY; i++)begin
+        logic `N(SET_WIDTH) addr;
+        assign addr = mshr_slave_io.request ? mshr_slave_io.raddr[OFFSET_WIDTH +: SET_WIDTH] : mshr_slave_io.waddr[OFFSET_WIDTH +: SET_WIDTH];
+        SPRAM #(
+            .WIDTH(ENTRY_SIZE),
+            .DEPTH(SET),
+            .RESET(1),
+            .READ_LATENCY(1)
+        ) ram (
+            .clk,
+            .rst,
+            .rst_sync(0),
+            .en(mshr_slave_io.request),
+            .addr(addr),
+            .rdata(lookup_entry[i]),
+            .we(~mshr_slave_io.request & mshr_slave_io.we & wway_dec[i]),
+            .wdata(mshr_slave_io.wdata),
+            .ready()
+        );
+        assign tag_hits[i] = (|lookup_entry[i][TAG_WIDTH+1 +: SLAVE_NUM]) & (lookup_entry[i][TAG_WIDTH-1: 0] == raddr_n[`PADDR_SIZE-1 -: TAG_WIDTH]);
+    end
+
+    FairSelect #(WAY, ENTRY_SIZE) select_lookup (tag_hits, lookup_entry, select_hit, select_entry);
+    FairSelect #(WAY, ENTRY_SIZE) select_replace (replace_io.miss_way, lookup_entry, , replace_data);
+    assign mshr_slave_io.hit = select_hit;
+    assign mshr_slave_io.share = select_entry[TAG_WIDTH];
+    assign mshr_slave_io.slave = select_entry[TAG_WIDTH + 1 +: SLAVE_NUM];
+    if(LLC)begin
+        assign mshr_slave_io.owned = select_entry[ENTRY_SIZE-1];
+        assign mshr_slave_io.owner = select_entry[ENTRY_SIZE-2 -: SLAVE_WIDTH];
+        assign mshr_slave_io.replace_owned = replace_data[ENTRY_SIZE-1];
+    end
+    else begin
+        assign mshr_slave_io.owned = 1'b1;
+        assign mshr_slave_io.owner = select_entry[ENTRY_SIZE-1 -: SLAVE_WIDTH];
+        assign mshr_slave_io.owned = 1'b1;
+    end
+    Encoder #(WAY) encoder_hit (tag_hits, mshr_slave_io.hit_way);
+    Encoder #(WAY) encoder_miss (replace_io.miss_way, mshr_slave_io.replace_way);
+    assign mshr_slave_io.replace_hit = (|replace_data[TAG_WIDTH+1 +: SLAVE_NUM]);
+    
+
+    Decoder #(WAY) decoder_wway (mshr_slave_io.wway, wway_dec);
+    assign mshr_slave_io.wready = ~mshr_slave_io.request;
+endgenerate
+
+endmodule
+
+
+// 写入时机:
+// L2 READ_ONCE并且需要从master中获得时或L2替换时
+module L2Directory #(
+    parameter SET = 64,
+    parameter WAY_NUM = 8,
+    parameter OFFSET = 32,
+    parameter OFFSET_WIDTH = $clog2(OFFSET),
+    parameter ISL2 = 1,
+    parameter SET_WIDTH = $clog2(SET),
+    parameter TAG_WIDTH = `PADDR_SIZE - OFFSET_WIDTH - SET_WIDTH,
+    parameter WAY_WIDTH = $clog2(WAY_NUM),
+    parameter DIRECTORY_SIZE = TAG_WIDTH+1+$bits(DirectoryState)
+)(
+    input logic clk,
+    input logic rst,
+    L2MSHRDirIO.dir mshr_dir_io
+);
+    logic `ARRAY(WAY_NUM, TAG_WIDTH+1) tagvs;
+    DirectoryState `N(WAY_NUM) dir_states;
+    logic `N(TAG_WIDTH) cmp_tag;
+    logic `N(WAY_NUM) tagv_hits;
+    logic `N(SET_WIDTH) lookup_idx;
+    logic `ARRAY(WAY_NUM, DIRECTORY_SIZE) rdata;
+    logic `N(DIRECTORY_SIZE) replace_data;
+    logic en_n;
+    logic `N(WAY_NUM) wway_dec;
+
+    ReplaceIO #(.DEPTH(SET), .WAY_NUM(WAY_NUM)) replace_io();
+    Replace #(
+        .DEPTH(SET),
+        .WAY_NUM(WAY_NUM)
+    ) replace (.*);
+    assign replace_io.miss_index = mshr_dir_io.raddr[OFFSET_WIDTH +: SET_WIDTH];
+    assign replace_io.hit_en = mshr_dir_io.hit & en_n | mshr_dir_io.we & ~mshr_dir_io.request;
+    assign replace_io.hit_way = mshr_dir_io.we & ~mshr_dir_io.request ? 
+                    (mshr_dir_io.wdata[0] ? mshr_dir_io.wway : ~mshr_dir_io.wway) : tagv_hits;
+    assign replace_io.hit_index = mshr_dir_io.we & ~mshr_dir_io.request ? mshr_dir_io.waddr[OFFSET_WIDTH +: SET_WIDTH] : lookup_idx;
+    always_ff @(posedge clk)begin
+        if(mshr_dir_io.request)begin
+            cmp_tag <= mshr_dir_io.raddr[`PADDR_SIZE-1 -: TAG_WIDTH];
+            lookup_idx <= mshr_dir_io.raddr[OFFSET_WIDTH +: SET_WIDTH];
+        end
+        en_n <= mshr_dir_io.request;
+    end
+generate
+    for(genvar i=0; i<WAY_NUM; i++)begin
+        logic `N(SET_WIDTH) addr;
+        assign addr = mshr_dir_io.request ? mshr_dir_io.raddr[OFFSET_WIDTH +: SET_WIDTH] : mshr_dir_io.waddr[OFFSET_WIDTH +: SET_WIDTH];
+        SPRAM #(
+            .WIDTH(DIRECTORY_SIZE),
+            .DEPTH(SET),
+            .READ_LATENCY(1),
+            .RESET(1)
+        ) directory (
+            .clk,
+            .rst,
+            .rst_sync(0),
+            .en(mshr_dir_io.request),
+            .addr(addr),
+            .rdata(rdata[i]),
+            .we(mshr_dir_io.we & ~mshr_dir_io.request & wway_dec[i]),
+            .wdata(mshr_dir_io.wdata),
+            .ready()
+        );
+        assign tagvs[i] = rdata[i][TAG_WIDTH: 0];
+        assign dir_states[i] = rdata[i][TAG_WIDTH+1 +: $bits(DirectoryState)];
+        assign tagv_hits[i] = tagvs[i][0] & (tagvs[i][TAG_WIDTH: 1] == cmp_tag);
+    end
+endgenerate
+
+    Encoder #(WAY_NUM) encoder_hit (tagv_hits, mshr_dir_io.hit_way);
+    Encoder #(WAY_NUM) encoder_miss (replace_io.miss_way, mshr_dir_io.replace_way);
+    FairSelect #(WAY_NUM, $bits(DirectoryState)) select_hit (tagv_hits, dir_states, mshr_dir_io.hit, mshr_dir_io.hit_state);
+    FairSelect #(WAY_NUM, DIRECTORY_SIZE) select_replace (replace_io.miss_way, rdata, , replace_data);
+    assign mshr_dir_io.replace_tagv = replace_data[TAG_WIDTH: 0];
+    assign mshr_dir_io.replace_state = replace_data[TAG_WIDTH+1 +: $bits(DirectoryState)];
+
+    Decoder #(WAY_NUM) decoder_wway (mshr_slave_io.wway, wway_dec);
+    assign mshr_dir_io.wready = ~mshr_dir_io.request;
+endmodule
\ No newline at end of file
diff --git a/src/core/mem/cache/L2Cache.sv b/src/core/mem/cache/L2Cache.sv
new file mode 100644
index 0000000..6932b89
--- /dev/null
+++ b/src/core/mem/cache/L2Cache.sv
@@ -0,0 +1,101 @@
+`include "../../../defines/defines.svh"
+
+module L2Cache #(
+    parameter MSHR_SIZE = 8,
+    parameter SLAVE_BANK = 16,
+    parameter CACHE_BANK = 16, // CACHELINE BANK
+    parameter DATA_BANK = 1, // CACHE SET BANK
+    parameter ID_WIDTH=2,
+    parameter ID_OFFSET=1,
+    parameter SLAVE = 1,
+    parameter WAY_NUM = 4,
+    parameter SET = 64,
+    parameter OFFSET = 32,
+    parameter ISL2 = 1,
+    parameter LLC = 1,
+    parameter PREPEND_PIPE = 0,
+    parameter APPEND_PIPE = 0,
+    parameter SLAVE_DIR_SET = 64,
+    parameter SLAVE_DIR_WAY = 4,
+    parameter type snoop_ac_chan_t = logic,
+    parameter type snoop_cd_chan_t = logic,
+    parameter type snoop_req_t = logic,
+    parameter type snoop_resp_t = logic,
+    parameter type mst_snoop_req_t = logic,
+    parameter type mst_snoop_resp_t = logic,
+    parameter MST_SNOOP_ID_WIDTH = 1
+)(
+    input logic clk,
+    input logic rst,
+    CacheBus.slave slave_io, // to l1
+    CacheBus.master master_io, // to mem
+    output snoop_req_t `N(SLAVE) snoop_req,
+    input snoop_resp_t `N(SLAVE) snoop_resp,
+    input snoop_req_t mst_snoop_req,
+    output snoop_resp_t mst_snoop_resp
+);
+    L2MSHRSlaveIO #(
+        .SLAVE(SLAVE),
+        .LLC(LLC),
+        .WAY(SLAVE_DIR_WAY),
+        .OFFSET(OFFSET),
+        .SET(SLAVE_DIR_SET)
+    ) mshr_slave_io();
+    L2MSHRDirIO #(
+        .WAY(WAY_NUM),
+        .OFFSET(OFFSET),
+        .SET(SET)
+    ) mshr_dir_io();
+    L2MSHRDataIO #(
+        .MSHR_SIZE(MSHR_SIZE),
+        .DATA_BANK(DATA_BANK),
+        .SET_SIZE(SET),
+        .WAY_NUM(WAY_NUM)
+    ) mshr_data_io();
+
+    LocalDirectory #(
+        .SLAVE_NUM(SLAVE),
+        .WAY(SLAVE_DIR_WAY),
+        .SET(SLAVE_DIR_SET),
+        .OFFSET(OFFSET),
+        .LLC(LLC)
+    ) local_dir(.*);
+    L2Directory #(
+        .SET(SET),
+        .WAY_NUM(WAY_NUM),
+        .OFFSET(OFFSET),
+        .ISL2(ISL2)
+    ) l2_dir(.*);
+    L2CacheData #(
+        .MSHR_SIZE(MSHR_SIZE),
+        .DATA_BANK(DATA_BANK),
+        .WAY_NUM(WAY_NUM),
+        .SET_SIZE(SET),
+        .CACHE_BANK(CACHE_BANK),
+        .PREPEND_PIPE(`L2PREPEND_PIPE),
+        .APPEND_PIPE(`L2APPEND_PIPE)
+    ) l2_data(.*);
+    L2MSHR #(
+        .MSHR_SIZE(MSHR_SIZE),
+        .SLAVE_BANK(SLAVE_BANK),
+        .CACHE_BANK(CACHE_BANK),
+        .DATA_BANK(DATA_BANK),
+        .ID_WIDTH(ID_WIDTH),
+        .ID_OFFSET(ID_OFFSET),
+        .SLAVE(SLAVE),
+        .WAY_NUM(WAY_NUM),
+        .SET(SET),
+        .OFFSET(OFFSET),
+        .ISL2(ISL2),
+        .LLC(LLC),
+        .SLAVE_DIR_SET(SLAVE_DIR_SET),
+        .SLAVE_DIR_WAY(SLAVE_DIR_WAY),
+        .snoop_ac_chan_t(snoop_ac_chan_t),
+        .snoop_cd_chan_t(snoop_cd_chan_t),
+        .snoop_req_t(snoop_req_t),
+        .snoop_resp_t(snoop_resp_t),
+        .mst_snoop_req_t(mst_snoop_req_t),
+        .mst_snoop_resp_t(mst_snoop_resp_t),
+        .MST_SNOOP_ID_WIDTH(MST_SNOOP_ID_WIDTH)
+    ) mshr(.*);
+endmodule
\ No newline at end of file
diff --git a/src/core/mem/cache/L2CacheData.sv b/src/core/mem/cache/L2CacheData.sv
new file mode 100644
index 0000000..3e91e0f
--- /dev/null
+++ b/src/core/mem/cache/L2CacheData.sv
@@ -0,0 +1,139 @@
+`include "../../../defines/defines.svh"
+
+module L2CacheData #(
+    parameter MSHR_SIZE=4,
+    parameter DATA_BANK = 1,
+    parameter WAY_NUM = 4,
+    parameter SET_SIZE = 64,
+    parameter CACHE_BANK = 16,
+    parameter PREPEND_PIPE = 0,
+    parameter APPEND_PIPE = 0,
+    parameter MSHR_WIDTH=$clog2(MSHR_SIZE)
+)(
+    input logic clk,
+    input logic rst,
+    L2MSHRDataIO.data mshr_data_io
+);
+
+generate
+    for(genvar i=0; i<DATA_BANK; i++)begin
+        L2DataBank #(
+            .MSHR_SIZE(MSHR_SIZE),
+            .WAY_NUM(WAY_NUM),
+            .CACHE_BANK(CACHE_BANK),
+            .SET_SIZE(SET_SIZE / DATA_BANK),
+            .PREPEND_PIPE(PREPEND_PIPE),
+            .APPEND_PIPE(APPEND_PIPE)
+        ) bank (
+            .clk,
+            .rst,
+            .req(mshr_data_io.req[i]),
+            .rway(mshr_data_io.rway[i]),
+            .raddr(mshr_data_io.raddr[i]),
+            .mshr_idx(mshr_data_io.mshr_idx[i]),
+            .ready(mshr_data_io.ready[i]),
+            .rvalid(mshr_data_io.rvalid[i]),
+            .mshr_idx_o(mshr_data_io.mshr_idx_o[i]),
+            .rdata(mshr_data_io.rdata[i]),
+            .we(mshr_data_io.we[i]),
+            .wway(mshr_data_io.wway[i]),
+            .wmshr_idx(mshr_data_io.wmshr_idx[i]),
+            .waddr(mshr_data_io.waddr[i]),
+            .wvalid(mshr_data_io.wvalid[i]),
+            .wmshr_idx_o(mshr_data_io.wmshr_idx_o[i]),
+            .wdata(mshr_data_io.wdata[i])
+        );
+    end
+endgenerate
+
+endmodule
+
+module L2DataBank #(
+    parameter MSHR_SIZE = 4,
+    parameter WAY_NUM = 4,
+    parameter SET_SIZE = 64,
+    parameter CACHE_BANK = 16,
+    parameter PREPEND_PIPE = 0,
+    parameter APPEND_PIPE = 0,
+    parameter MSHR_WIDTH = $clog2(MSHR_SIZE),
+    parameter SET_WIDTH = $clog2(SET_SIZE),
+    parameter WAY_WIDTH = $clog2(WAY_NUM),
+    parameter CACHE_BITS = (`CACHELINE_SIZE / CACHE_BANK) * 8
+)(
+    input logic clk,
+    input logic rst,
+    input logic req,
+    input logic `N(MSHR_WIDTH) mshr_idx,
+    input logic `N(WAY_WIDTH) rway,
+    input logic `N(SET_WIDTH) raddr,
+    output logic ready,
+    output logic rvalid,
+    output logic `N(MSHR_WIDTH) mshr_idx_o,
+    output logic `ARRAY(CACHE_BANK, CACHE_BITS) rdata,
+    input logic we,
+    input logic `N(WAY_WIDTH) wway,
+    input logic `N(MSHR_WIDTH) wmshr_idx,
+    input logic `N(SET_WIDTH) waddr,
+    output logic wvalid,
+    output logic `N(MSHR_WIDTH) wmshr_idx_o,
+    input logic `ARRAY(CACHE_BANK, CACHE_BITS) wdata
+);
+    logic `ARRAY(PREPEND_PIPE+1, SET_WIDTH) ridx/*verilator split_var*/;
+    logic `TENSOR(PREPEND_PIPE+1, CACHE_BANK, CACHE_BITS) wdata_r/*verilator split_var*/;
+    logic `ARRAY(PREPEND_PIPE+APPEND_PIPE+2, MSHR_WIDTH+2) mshr_idx_r/*verilator split_var*/;
+    logic `ARRAY(PREPEND_PIPE+2, WAY_WIDTH) rway_r/*verilator split_var*/;
+    logic `N(SET_WIDTH) idx;
+    logic `ARRAY(WAY_NUM, CACHE_BANK * CACHE_BITS) rdata_ram;
+    logic `ARRAY(APPEND_PIPE+1, CACHE_BANK * CACHE_BITS) rdata_append/*verilator split_var*/;
+
+    assign idx = ridx[PREPEND_PIPE];
+    assign mshr_idx_r[0] = we ? {wmshr_idx, 1'b1, 1'b0} : {mshr_idx, 1'b0, req & ready};
+    assign rway_r[0] = we ? wway : rway;
+    assign wdata_r[0] = wdata;
+    assign rdata_append[0] = rdata_ram[rway_r[PREPEND_PIPE+1]];
+    always_ff @(posedge clk)begin
+        mshr_idx_r[PREPEND_PIPE+1] <= mshr_idx_r[PREPEND_PIPE]; // data read cycle
+        rway_r[PREPEND_PIPE+1] <= rway_r[PREPEND_PIPE];
+    end
+
+    assign rvalid = mshr_idx_r[PREPEND_PIPE+APPEND_PIPE+1][0];
+    assign wvalid = mshr_idx_r[PREPEND_PIPE+APPEND_PIPE+1][1];
+    assign mshr_idx_o = mshr_idx_r[PREPEND_PIPE+APPEND_PIPE+1][2 +: MSHR_WIDTH];
+    assign wmshr_idx_o = mshr_idx_r[PREPEND_PIPE+APPEND_PIPE+1][2 +: MSHR_WIDTH];
+    assign rdata = rdata_append[APPEND_PIPE];
+    assign ridx[0] = we ? waddr : raddr;
+    assign ready = ~we;
+generate
+    for(genvar i=0; i<PREPEND_PIPE; i++)begin
+        always_ff @(posedge clk)begin
+            ridx[i+1] <= ridx[i];
+            mshr_idx_r[i+1] <= mshr_idx_r[i];
+            rway_r[i+1] <= rway_r[i];
+            wdata_r[i+1] <= wdata_r[i];
+        end
+    end
+    for(genvar i=0; i<APPEND_PIPE; i++)begin
+        always_ff @(posedge clk)begin
+            rdata_append[i+1] <= rdata_append[i];
+            mshr_idx_r[PREPEND_PIPE+2+i] <= mshr_idx_r[PREPEND_PIPE+1+i];
+        end
+    end
+    for(genvar i=0; i<WAY_NUM; i++)begin
+        SPRAM #(
+            .WIDTH(`DCACHE_BANK * `DCACHE_BITS),
+            .DEPTH(SET_SIZE),
+            .READ_LATENCY(1)
+        ) ram (
+            .clk,
+            .rst,
+            .rst_sync(0),
+            .en(mshr_idx_r[PREPEND_PIPE][0]),
+            .we(mshr_idx_r[PREPEND_PIPE][1]),
+            .addr(idx),
+            .rdata(rdata_ram[i]),
+            .wdata(wdata_r[PREPEND_PIPE]),
+            .ready()
+        );
+    end
+endgenerate
+endmodule
\ No newline at end of file
diff --git a/src/core/mem/cache/L2CacheWrapper.sv b/src/core/mem/cache/L2CacheWrapper.sv
new file mode 100644
index 0000000..90b4f74
--- /dev/null
+++ b/src/core/mem/cache/L2CacheWrapper.sv
@@ -0,0 +1,151 @@
+`include "../../../defines/defines.svh"
+
+module L2CacheWrapper #(
+    parameter type snoop_req_t = logic,
+    parameter type snoop_resp_t = logic,
+    parameter type mst_snoop_req_t = logic,
+    parameter type mst_snoop_resp_t = logic,
+    parameter MST_SNOOP_ID_WIDTH = 1
+)(
+    input logic clk,
+    input logic rst,
+    CacheBus.slave icache_io,
+    CacheBus.slave tlb_io,
+    CacheBus.slave dcache_io,
+    CacheBus.slave ducache_io,
+    CacheBus.master master_io, // to mem
+    output snoop_req_t snoop_req,
+    input snoop_resp_t snoop_resp,
+    input mst_snoop_req_t mst_snoop_req,
+    output mst_snoop_resp_t mst_snoop_resp
+);
+    typedef logic [`PADDR_SIZE-1: 0] addr_t;
+    typedef logic [0: 0] id_t;
+    typedef logic user_t;
+    typedef logic [2: 0] mst_id_t;
+    typedef logic [`XLEN-1: 0] data_t;
+    typedef logic [`XLEN/8-1: 0] strb_t;
+    typedef logic [$clog2(`L2MSHR_SIZE)-1: 0] snoop_ack_id_t;
+
+    `CACHE_TYPEDEF_AW_CHAN_T(AxiAW, addr_t, id_t, user_t)
+    `CACHE_TYPEDEF_W_CHAN_T(AxiW, data_t, strb_t, user_t)
+    `CACHE_TYPEDEF_B_CHAN_T(AxiB, id_t, user_t)
+    `CACHE_TYPEDEF_AR_CHAN_T(AxiAR, addr_t, id_t, user_t)
+    `CACHE_TYPEDEF_R_CHAN_T(AxiR, data_t, id_t, user_t)
+    `CACHE_TYPEDEF_REQ_T(AxiReq, AxiAW, AxiW, AxiAR)
+    `CACHE_TYPEDEF_RESP_T(AxiResp, AxiB, AxiR)
+
+    `CACHE_TYPEDEF_AW_CHAN_T(AxiMAW, addr_t, mst_id_t, user_t)
+    `CACHE_TYPEDEF_B_CHAN_T(AxiMB, mst_id_t, user_t)
+    `CACHE_TYPEDEF_AR_CHAN_T(AxiMAR, addr_t, mst_id_t, user_t)
+    `CACHE_TYPEDEF_R_CHAN_T(AxiMR, data_t, mst_id_t, user_t)
+    `CACHE_TYPEDEF_REQ_T(AxiMReq, AxiMAW, AxiW, AxiMAR)
+    `CACHE_TYPEDEF_RESP_T(AxiMResp, AxiMB, AxiMR)
+
+    `SNOOP_TYPEDEF_AC_CHAN_T(snoop_ac_chan_t, addr_t)
+    `SNOOP_TYPEDEF_CD_CHAN_T(snoop_cd_chan_t, data_t)
+    `SNOOP_TYPEDEF_CR_CHAN_T(snoop_cr_chan_t)
+
+    AxiReq ireq, dreq, du_req, tlb_req;
+    AxiResp iresp, dresp, du_resp, tlb_resp;
+    AxiMReq req_o;
+    AxiMResp resp_i;
+    CacheBus #(
+        `PADDR_SIZE, `XLEN, 3, 1
+    ) l2_cache_io();
+
+    `CACHE_ASSIGN_TO_AR(ireq.ar, icache_io)
+    assign ireq.ar_valid = icache_io.ar_valid;
+    assign ireq.r_ready = icache_io.r_ready;
+    assign ireq.aw = 0;
+    assign ireq.w = 0;
+    assign ireq.aw_valid = 0;
+    assign ireq.w_valid = 0;
+    assign ireq.b_ready = 0;
+    `CACHE_ASSIGN_FROM_R(icache_io, iresp.r)
+    assign icache_io.ar_ready = iresp.ar_ready;
+    assign icache_io.r_valid = iresp.r_valid;
+
+    `CACHE_ASSIGN_TO_AR(tlb_req.ar, tlb_io)
+    assign tlb_req.ar_valid = tlb_io.ar_valid;
+    assign tlb_req.r_ready = icache_io.r_ready;
+    assign tlb_req.aw = 0;
+    assign tlb_req.w = 0;
+    assign tlb_req.aw_valid = 0;
+    assign tlb_req.w_valid = 0;
+    assign tlb_req.b_ready = 0;
+    `CACHE_ASSIGN_FROM_R(tlb_io, tlb_resp.r)
+    assign tlb_io.ar_ready = tlb_resp.ar_ready;
+    assign tlb_io.r_valid = tlb_resp.r_valid;
+
+    `CACHE_ASSIGN_TO_REQ(dreq, dcache_io)
+    `CACHE_ASSIGN_FROM_RESP(dcache_io, dresp)
+
+    `CACHE_ASSIGN_TO_REQ(du_req, ducache_io)
+    `CACHE_ASSIGN_FROM_RESP(ducache_io, du_resp)
+
+    `CACHE_ASSIGN_FROM_REQ(l2_cache_io, req_o)
+    `CACHE_ASSIGN_TO_RESP(resp_i, l2_cache_io)
+
+    axi_mux #(
+        .SlvAxiIDWidth(1),
+        .slv_aw_chan_t(AxiAW),
+        .mst_aw_chan_t(AxiMAW),
+        .w_chan_t(AxiW),
+        .slv_b_chan_t(AxiB),
+        .mst_b_chan_t(AxiMB),
+        .slv_ar_chan_t(AxiAR),
+        .mst_ar_chan_t(AxiMAR),
+        .slv_r_chan_t(AxiR),
+        .mst_r_chan_t(AxiMR),
+        .slv_req_t(AxiReq),
+        .slv_resp_t(AxiResp),
+        .mst_req_t(AxiMReq),
+        .mst_resp_t(AxiMResp),
+        .MaxWTrans(1),
+        .NoSlvPorts(4)
+    ) axi_mux_inst(
+        .clk_i(clk),
+        .rst_ni(~rst),
+        .test_i(1'b0),
+        .slv_reqs_i({dreq, du_req, tlb_req, ireq}),
+        .slv_resps_o({dresp, du_resp, tlb_resp, iresp}),
+        .mst_req_o(req_o),
+        .mst_resp_i(resp_i)
+    );
+
+    L2Cache #(
+        .MSHR_SIZE(`L2MSHR_SIZE),
+        .SLAVE_BANK(`DCACHE_BANK),
+        .CACHE_BANK(`L2CACHE_BANK),
+        .DATA_BANK(`L2DATA_BANK),
+        .ID_WIDTH(2),
+        .ID_OFFSET(1),
+        .SLAVE(1),
+        .WAY_NUM(`L2WAY_NUM),
+        .SET(`L2SET),
+        .OFFSET(`L2OFFSET),
+        .ISL2(1),
+        .LLC(1),
+        .SLAVE_DIR_SET(`L2SLAVE_SET),
+        .SLAVE_DIR_WAY(`L2SLAVE_WAY),
+        .PREPEND_PIPE(`L2PREPEND_PIPE),
+        .APPEND_PIPE(`L2APPEND_PIPE),
+        .snoop_ac_chan_t(snoop_ac_chan_t),
+        .snoop_cd_chan_t(snoop_cd_chan_t),
+        .snoop_req_t(snoop_req_t),
+        .snoop_resp_t(snoop_resp_t),
+        .mst_snoop_req_t(mst_snoop_req_t),
+        .mst_snoop_resp_t(mst_snoop_resp_t),
+        .MST_SNOOP_ID_WIDTH(MST_SNOOP_ID_WIDTH)
+    ) l2_cache(
+        .clk,
+        .rst,
+        .slave_io(l2_cache_io.slave),
+        .master_io(master_io),
+        .snoop_req,
+        .snoop_resp,
+        .mst_snoop_req,
+        .mst_snoop_resp
+    );
+endmodule
\ No newline at end of file
diff --git a/src/core/mem/cache/L2MSHR.sv b/src/core/mem/cache/L2MSHR.sv
new file mode 100644
index 0000000..b1c9d11
--- /dev/null
+++ b/src/core/mem/cache/L2MSHR.sv
@@ -0,0 +1,1161 @@
+`include "../../../defines/defines.svh"
+
+// 替换：如果是LLC，那么dirty写回即可
+// 如果不是，并且不是拥有者，则直接丢弃
+// 如果是拥有者则写入下一级
+
+// READ:
+// READ_ONCE: icache tlb
+// READ_SHARED: mem read
+// READ_UNIQUE: mem write, don't owned
+// MAKE_UNIQUE: mem full write or owned
+// CLEAN_INVALID: snoop clean
+// WRITE:
+// WRITE_CLEAN: mem write and cache line is dirty
+// WRITE_EVICT: mem write and cache line is clean
+// SNOOP:
+// READ_SHARED
+// READ_UNIQUE
+// CLEAN_INVALID
+module L2MSHR #(
+    parameter MSHR_SIZE = 8,
+    parameter SLAVE_BANK = 16,
+    parameter CACHE_BANK = 16, // CACHELINE BANK
+    parameter DATA_BANK = 1, // CACHE SET BANK
+    parameter ID_WIDTH=2,
+    parameter ID_OFFSET=1,
+    parameter SLAVE = 1,
+    parameter WAY_NUM = 4,
+    parameter SET = 64,
+    parameter OFFSET = 32,
+    parameter ISL2 = 1,
+    parameter LLC = 1,
+    parameter SLAVE_DIR_SET = 64,
+    parameter SLAVE_DIR_WAY = 4,
+    parameter type snoop_ac_chan_t = logic,
+    parameter type snoop_cd_chan_t = logic,
+    parameter type snoop_req_t = logic,
+    parameter type snoop_resp_t = logic,
+    parameter type mst_snoop_req_t = logic,
+    parameter type mst_snoop_resp_t = logic,
+    parameter MST_SNOOP_ID_WIDTH = 4,
+    parameter MSHR_WIDTH = $clog2(MSHR_SIZE),
+    parameter SLAVE_BITS = (`CACHELINE_SIZE / SLAVE_BANK) * 4,
+    parameter CACHE_BITS = (`CACHELINE_SIZE / CACHE_BANK) * 4,
+    parameter SLAVE_WIDTH = idxWidth(SLAVE),
+    parameter SLAVE_BANK_WIDTH = $clog2(SLAVE_BANK),
+    parameter CACHE_BANK_WIDTH = $clog2(CACHE_BANK),
+    parameter DATA_BANK_WIDTH = idxWidth(DATA_BANK),
+    parameter WAY_WIDTH = $clog2(WAY_NUM),
+    parameter SET_WIDTH = $clog2(SET),
+    parameter OFFSET_WIDTH = $clog2(OFFSET),
+    parameter SLAVE_WAY_WIDTH = $clog2(SLAVE_DIR_WAY),
+    parameter SLAVE_TAG_WIDTH = `PADDR_SIZE - OFFSET_WIDTH - $clog2(SLAVE_DIR_SET),
+    parameter TAG_WIDTH = `PADDR_SIZE - OFFSET_WIDTH - SET_WIDTH
+)(
+    input logic clk,
+    input logic rst,
+    CacheBus.slave slave_io,
+    CacheBus.master master_io,
+    output snoop_req_t `N(SLAVE) snoop_req,
+    input snoop_resp_t `N(SLAVE) snoop_resp,
+
+    input mst_snoop_req_t mst_snoop_req,
+    output mst_snoop_resp_t mst_snoop_resp,
+
+    L2MSHRSlaveIO.mshr mshr_slave_io,
+    L2MSHRDirIO.mshr mshr_dir_io,
+    L2MSHRDataIO.mshr mshr_data_io
+);
+
+    typedef struct packed {
+        logic write;
+        logic snoop;
+        logic `N(ID_WIDTH) id;
+        logic `N(4) op;
+        logic `N(`PADDR_SIZE) paddr;
+    } MSHREntry;
+
+    // for snoop
+    typedef struct packed {
+        logic `N(SLAVE) slave;
+        logic `N(SLAVE_WIDTH) slave_owner;
+    } DirInfo;
+
+    // for dir write
+    typedef struct packed {
+        logic `N(`PADDR_SIZE) waddr;
+        logic `N(SLAVE_WAY_WIDTH) slave_replace_way;
+        logic `N(WAY_WIDTH) replace_way;
+        logic `N(SLAVE) slave;
+        logic write;
+        logic write_dirty;
+        logic owned;
+        logic require_owned; // READ_UNIQUE, MAKE_UNIQUE
+        logic slave_share;
+        logic slave_hit;
+        logic dir_hit;
+        logic `N(SLAVE_WIDTH) owner;
+    } DirWInfo;
+
+    MSHREntry `N(MSHR_SIZE) entrys;
+    logic `N(MSHR_SIZE) entry_waiting;
+    DirInfo `N(MSHR_SIZE) dir_infos;
+    logic `ARRAY(MSHR_SIZE, WAY_WIDTH) lookup_ways;
+    logic `ARRAY(MSHR_SIZE, `PADDR_SIZE) paddrs;
+    logic `N(MSHR_SIZE) entry_snoop;
+    logic `N(MSHR_SIZE) en, dir_valid, require_data, op_valid, data_valid;
+    logic `N(MSHR_SIZE) req_ll, req_ll_op_valid; // needed if ISL2 == 1
+    logic `N(MSHR_SIZE) snoop_request, snoop_replace_request;
+
+    logic `N(MSHR_SIZE) free_en1, free_en2;
+    logic `N(MSHR_SIZE) free_idx1, free_idx2;
+    logic free_conflict, full, ar_free_conflict;
+    logic `N(MSHR_SIZE) dir_requests, dir_request_select;
+    logic `N(MSHR_SIZE) dir_resp_reqs;
+    logic `N(MSHR_WIDTH) dir_select_idx, dir_select_idx_n;
+    logic dir_request, dir_request_n;
+    DirWInfo `N(MSHR_SIZE) dir_winfos;
+
+    logic `ARRAY(MSHR_SIZE, SLAVE_BANK) refill_valids, refill_valids_select;
+    logic `ARRAY(SLAVE_BANK, SLAVE_BITS) refill_data;
+    logic `ARRAY(MSHR_SIZE, ID_WIDTH) refill_ids;
+    DirectoryState `N(MSHR_SIZE) refill_resps;
+    logic refill_snoop_resp_req, refill_l3_resp_req;
+    logic `N(MSHR_SIZE) refill_valid, refill_valid_select;
+    logic `N(SLAVE_BANK) refill_bank_select;
+    logic `N(MSHR_WIDTH) refill_idx;
+    logic refill_snoop;
+    logic refill_r_valid;
+    logic `N(SLAVE_BITS) refill_r_data;
+    logic `ARRAY(DATA_BANK, MSHR_SIZE) data_bank_valids;
+    logic `ARRAY(MSHR_SIZE, DATA_BANK) data_bank_valids_rev;
+    logic `N(MSHR_SIZE) snoop_idx_dec, refill_idx_dec;
+
+    typedef enum {SNOOP_IDLE, SNOOP_REQUEST} SnoopState;
+    typedef struct packed {
+        logic `N(MSHR_WIDTH) idx;
+        logic `N(SLAVE) target_slave;
+        logic `N(SLAVE) slave_request;
+        logic `N(`PADDR_SIZE) snoop_addr;
+        logic `N(4) op;
+        logic `N(SLAVE) response;
+        DirectoryState response_state;
+        logic require_data;
+        logic slave_replace;
+        logic `N(SLAVE_BANK_WIDTH) data_index;
+        logic data_valid;
+    } SnoopBuffer;
+    SnoopState snoop_state;
+    MSHREntry snoop_entry;
+    DirInfo snoop_dir_info;
+    SnoopBuffer snoop_buffer;
+    logic snoop_valid;
+    logic `N(MSHR_WIDTH) snoop_idx;
+    logic `N(SLAVE) owner_decode;
+    logic `N(SLAVE) snoop_cd_valids;
+    snoop_cd_chan_t `N(SLAVE) snoop_cd_datas;
+    logic snoop_cd_valid;
+    snoop_cd_chan_t snoop_cd_data;
+
+    logic `N(MSHR_SIZE) lookup_requests;
+    logic `ARRAY(MSHR_SIZE, DATA_BANK) lookup_bank;
+    logic `ARRAY(DATA_BANK, MSHR_SIZE) lookup_bank_rev;
+    logic `N(DATA_BANK) lookup_data_req, write_bank_req;
+    logic `ARRAY(MSHR_SIZE, SET_WIDTH) lookup_addrs;
+
+    typedef enum {L3_IDLE, L3_REQUEST} L3State;
+    typedef struct packed {
+        logic request;
+        logic `N(MSHR_SIZE) idx;
+        logic `N(ID_WIDTH) id;
+        logic `N(4) op;
+        logic `N(`PADDR_SIZE) addr;
+        logic `N(DATA_BANK_WIDTH) data_index;
+    } L3Buffer;
+    L3State l3_state;
+    MSHREntry l3_entry;
+    L3Buffer l3_buffer;
+    logic `N(MSHR_SIZE) l3_requests;
+    logic `N(MSHR_SIZE) l3_idx_dec;
+    logic `N(MSHR_WIDTH) l3_idx;
+    logic l3_request;
+
+    logic `TENSOR(MSHR_SIZE, SLAVE_BANK, SLAVE_BITS) write_buffer;
+    logic `N(MSHR_SIZE) write_data_valid;
+    logic `N(MSHR_WIDTH) write_idx;
+    logic `N(ID_WIDTH) write_id, slave_b_id;
+    logic `N(SLAVE_BANK_WIDTH) write_data_index;
+    logic write_waiting, slave_b_valid;
+
+    typedef struct packed {
+        logic aw_valid;
+        logic dirty;
+        logic `N(`PADDR_SIZE) addr;
+        logic replace_data_valid;
+        logic `ARRAY(CACHE_BANK, CACHE_BITS) replace_data;
+        logic `N(ID_WIDTH) id;
+        logic `N(MSHR_WIDTH) idx;
+        logic `N(WAY_WIDTH) way;
+        logic `N(DATA_BANK) data_bank;
+        logic `N(CACHE_BANK_WIDTH) data_index;
+        logic w_last;
+    } ReplaceBuffer;
+    ReplaceBuffer replace_buffer;
+    logic replace_busy;
+    logic `N(MSHR_SIZE) replace_reqs, replace_data_valids;
+    logic replace_req;
+    logic `ARRAY(MSHR_SIZE, WAY_WIDTH) replace_ways;
+    logic `ARRAY(WAY_WIDTH, TAG_WIDTH+1) replace_tags; // tag, dirty
+    MSHREntry replace_entry;
+    logic `N(TAG_WIDTH+1) replace_tag;
+    logic `N(MSHR_WIDTH) replace_idx;
+    logic write_replace_cond, read_replace_cond, replace_cond_valid;
+    logic replace_read_req, replace_read_conflict;
+    logic `N(WAY_WIDTH) replace_way_select;
+    logic `N(DATA_BANK) replace_data_bank;
+    logic `N(DATA_BANK) replace_data_hits;
+    logic replace_data_hit;
+    logic `ARRAY(CACHE_BANK, CACHE_BITS) replace_read_data;
+
+// enqueue
+    logic renq_en;
+    logic wenq_en;
+    logic snoop_enq_en;
+    logic `N(MSHR_SIZE) renq_conflict, wenq_conflict, snoop_enq_conflict;
+    logic `N(MSHR_SIZE) mshr_finish, dir_finish;
+    logic `N(MSHR_WIDTH) mshr_widx, mshr_widx_n;
+    logic `N(SET_WIDTH) mshr_wpaddr;
+    logic `N(MSHR_SIZE) waiting_conflict, waiting_select;
+    logic `N(MSHR_WIDTH) waiting_select_idx;
+    PSelector #(MSHR_SIZE) select_free_en1 (~en, free_en1);
+    PRSelector #(MSHR_SIZE) select_free_en2 (~en, free_en2);
+    PEncoder #(MSHR_SIZE) encoder_free_idx1 (~en, free_idx1);
+    PREncoder #(MSHR_SIZE) encoder_free_idx2 (~en, free_idx2);
+    assign free_conflict = (|(free_en1 & free_en2));
+    assign full = &en;
+
+    assign ar_free_conflict = free_conflict;
+    assign slave_io.ar_ready = ~full & ~ar_free_conflict;
+    assign slave_io.aw_ready = ~full & ~write_waiting;
+    assign mst_snoop_resp.ac_ready = ~full & ~(slave_io.aw_valid & ~write_waiting);
+
+    assign renq_en = ~full & ~free_conflict & slave_io.ar_valid;
+    assign wenq_en = ~full & slave_io.aw_valid & ~write_waiting;
+    assign snoop_enq_en = ~full & mst_snoop_req.ac_valid;
+generate
+    for(genvar i=0; i<MSHR_SIZE; i++)begin
+        assign renq_conflict[i] = en[i] & (slave_io.ar_addr[OFFSET_WIDTH +: SET_WIDTH] == paddrs[i][OFFSET_WIDTH +: SET_WIDTH]);
+        assign wenq_conflict[i] = en[i] & (slave_io.aw_addr[OFFSET_WIDTH +: SET_WIDTH] == paddrs[i][OFFSET_WIDTH +: SET_WIDTH]);
+        assign snoop_enq_conflict[i] = en[i] & (mst_snoop_req.ac.addr[OFFSET_WIDTH +: SET_WIDTH] == paddrs[i][OFFSET_WIDTH +: SET_WIDTH]);
+        assign waiting_conflict[i] = entry_waiting[i] & (paddrs[i][OFFSET_WIDTH +: SET_WIDTH] == mshr_wpaddr);
+    end
+endgenerate
+
+    assign mshr_finish = en & dir_finish & ~dir_slave_wreq & ~dir_wreq & ~snoop_request &
+                         (~require_data | refill_finish) & ~replace_reqs & ~lookup_requests;
+    PEncoder #(MSHR_SIZE) encoder_mshr_widx (mshr_finish, mshr_widx);
+    always_ff @(posedge clk)begin
+        mshr_widx_n <= mshr_widx;
+        if(mshr_finish)begin
+            mshr_wpaddr <= paddrs[mshr_widx][OFFSET_WIDTH +: SET_WIDTH];
+        end
+    end
+    DirectionSelector #(MSHR_SIZE, 2) selector_mshr_waiting (
+        .clk,
+        .rst,
+        .en({renq_en, wenq_en | snoop_enq_en}),
+        .idx({free_idx2, free_idx1}),
+        .ready(waiting_conflict),
+        .select(waiting_select)
+    );
+    Encoder #(MSHR_SIZE) encoder_waiting_select (waiting_select, waiting_select_idx);
+
+    always_ff @(posedge clk, posedge rst)begin
+        if(rst == `RST)begin
+            en <= 0;
+            dir_requests <= 0;
+            entrys <= 0;
+            entry_waiting <= 0;
+        end
+        else begin
+            if(wenq_en | snoop_enq_en)begin
+                en[free_idx1] <= 1'b1;
+            end
+            if(renq_en)begin
+                en[free_idx2] <= 1'b1;
+            end
+            if(wenq_en)begin
+                entrys[free_idx1] <= {1'b1, 1'b0, slave_io.aw_id[ID_OFFSET +: ID_WIDTH], 1'b0, slave_io.aw_snoop, slave_io.aw_addr};
+                dir_requests[free_idx1] <= ~(|wenq_conflict);
+                entry_waiting[free_idx1] <= |wenq_conflict;
+            end
+            else if(snoop_enq_en)begin
+                entrys[free_idx1] <= {1'b0, 1'b1, {ID_WIDTH{1'b0}}, mst_snoop_req.ac.snoop, mst_snoop_req.ac.addr};
+                dir_requests[free_idx1] <= ~(|snoop_enq_conflict);
+                entry_waiting[free_idx1] <= |snoop_enq_conflict;
+            end
+            if(renq_en)begin
+                entrys[free_idx2] <= {1'b0, 1'b0, slave_io.ar_id[ID_OFFSET +: ID_WIDTH], slave_io.ar_snoop, slave_io.ar_addr};
+                dir_requests[free_idx2] <= ~(|renq_conflict);
+                entry_waiting[free_idx2] <= |renq_conflict;
+            end
+
+            if(|dir_requests)begin
+                dir_requests[dir_select_idx] <= 1'b0;
+            end
+
+            if(|waiting_conflict)begin
+                dir_valid[waiting_select_idx] <= 1'b1;
+                entry_waiting[waiting_select_idx] <= 1'b0;
+            end
+
+            if(|mshr_finish)begin
+                en[mshr_widx] <= 1'b0;
+            end
+        end
+    end
+
+// refill buffer
+    logic `N(MSHR_SIZE) refill_finish, refill_no_rack;
+generate
+    for(genvar i=0; i<DATA_BANK; i++)begin
+        logic `N(MSHR_SIZE) mshr_idx_dec;
+        Decoder #(MSHR_SIZE) decoder_data_valid (mshr_data_io.mshr_idx_o[i], mshr_idx_dec);
+        assign data_bank_valids[i] = {MSHR_SIZE{mshr_data_io.rvalid[i]}} & mshr_idx_dec;
+        for(genvar j=0; j<MSHR_SIZE; j++)begin
+            assign data_bank_valids_rev[j][i] = data_bank_valids[i][j];
+        end
+    end
+    Decoder #(MSHR_SIZE) decoder_snoop_idx (snoop_buffer.data_index, snoop_idx_dec);
+    for(genvar i=0; i<SLAVE_BANK; i++)begin : refill_buffer
+        logic `ARRAY(MSHR_SIZE, SLAVE_BITS) data, cache_data;
+        logic `ARRAY(DATA_BANK, CACHE_BITS) bank_data;
+        logic `N(MSHR_SIZE) data_valid;
+        logic `N(MSHR_SIZE) we;
+        logic `N(MSHR_SIZE) data_we, snoop_we;
+        logic `ARRAY(MSHR_SIZE, SLAVE_BITS) wdata;
+        assign snoop_we = {MSHR_SIZE{snoop_cd_valid & ~snoop_buffer.slave_replace}} & snoop_idx_dec;
+        assign we = data_we | snoop_we |
+                    {MSHR_SIZE{master_io.r_valid}} & l3_buffer.idx;
+        for(genvar j=0; j<DATA_BANK; j++)begin
+            assign bank_data[j] = mshr_data_io.rdata[j][i];
+        end
+        for(genvar j=0; j<MSHR_SIZE; j++)begin
+            localparam PARTITION = CACHE_BITS / SLAVE_BITS;
+            logic `N(CACHE_BITS) bank_select_data;
+            logic `ARRAY(PARTITION, SLAVE_BITS) bank_select_data_part, mst_data_part;
+            assign refill_valids[j][i] = data_valid[j];
+            assign wdata[j] = data_we[j] ? bank_select_data[i % PARTITION] : 
+                            snoop_we[j] ? snoop_cd_data.data : mst_data_part[i % PARTITION];
+            FairSelect #(DATA_BANK, CACHE_BITS) select_data (data_bank_valids_rev[j], bank_data, data_we[j], bank_select_data);
+            assign bank_select_data_part = bank_select_data;
+            assign mst_data_part = master_io.r_data;
+        end
+        OldestSelect #(MSHR_SIZE, 1, SLAVE_BITS) select_data (data_valid, data, , refill_data[i]);
+
+        always_ff @(posedge clk, posedge rst)begin
+            if(rst == `RST)begin
+                data <= 0;
+                data_valid <= 0;
+            end
+            else begin
+                for(int j=0; j<MSHR_SIZE; j++)begin
+                    if(we[j])begin
+                        data[j] <= wdata[j];
+                    end
+                end
+                data_valid <= (data_valid | we & ~entry_snoop) & 
+                              ~(refill_valid_select & {MSHR_SIZE{refill_bank_select[i] & (slave_io.r_valid & slave_io.r_ready | 
+                              mst_snoop_resp.cd_valid & mst_snoop_req.cd_ready)}});
+
+            end
+        end
+    end
+    for(genvar i=0; i<MSHR_SIZE; i++)begin
+        assign refill_valid[i] = |refill_valids[i];
+        PRSelector #(SLAVE_BANK) select_refill_bank (refill_valids[i], refill_valids_select[i]);
+    end
+    PEncoder #(MSHR_SIZE) encoder_refill_idx(refill_valid, refill_idx);
+    PSelector #(MSHR_SIZE) selector_refill_valid(refill_valid, refill_valid_select);
+    assign refill_bank_select = refill_valids_select[refill_idx];
+endgenerate
+    always_ff @(posedge clk, posedge rst)begin
+        if(rst == `RST)begin
+            refill_ids <= 0;
+            refill_resps <= 0;
+            refill_snoop_resp_req <= 0;
+            refill_l3_resp_req <= 0;
+            dir_resp_reqs <= 0;
+            refill_finish <= 0;
+            refill_no_rack <= 0;
+        end
+        else begin
+            if(dir_request_n)begin
+                refill_ids[dir_select_idx_n] <= dir_entry_n.id;
+                dir_resp_reqs[dir_select_idx_n] <= ~mshr_dir_io.hit & ~dir_entry_n.write;
+                refill_no_rack[dir_select_idx_n] <= dir_read_once | dir_entry_n.snoop;
+            end
+
+            if(dir_request_n & mshr_dir_io.hit & ~dir_entry_n.write)begin
+                refill_resps[dir_select_idx_n] <= mshr_dir_io.hit_state;
+            end
+
+            if((snoop_state == SNOOP_IDLE) & (|snoop_request) & (snoop_entry.op != `ACEOP_MAKE_UNIQUE))begin
+                refill_snoop_resp_req <= 1'b1;
+            end
+            if(|snoop_buffer.response & refill_snoop_resp_req)begin
+                refill_resps[snoop_buffer.idx] <= snoop_buffer.response_state;
+                dir_resp_reqs[snoop_buffer.idx] <= 1'b0;
+                refill_snoop_resp_req <= 1'b0;
+            end
+
+            if((l3_state == L3_IDLE) & (l3_request))begin
+                refill_l3_resp_req <= 1'b1;
+            end
+            if(master_io.r_valid & refill_l3_resp_req)begin
+                refill_l3_resp_req <= 1'b0;
+                refill_resps[l3_buffer.idx] <= master_io.r_resp[4: 2];
+                dir_resp_reqs[l3_buffer.idx] <= 1'b0;
+            end
+
+            if(ISL2 & slave_io.r_valid & slave_io.r_last & refill_no_rack[refill_idx])begin
+                refill_finish[refill_idx] <= 1'b1;
+            end
+
+            for(int i=0; i<SLAVE; i++)begin
+                if(snoop_resp[i].rack)begin
+                    refill_finish[snoop_resp[i].r_snoop_id] <= 1'b1;
+                end
+            end
+
+        end
+    end
+    OldestSelect #(MSHR_SIZE, 1, SLAVE_BITS) select_refill_data (refill_valid, refill_data, refill_r_valid, refill_r_data);
+    assign slave_io.r_valid = refill_r_valid;
+    assign slave_io.r_id = {refill_ids[refill_idx], 1'b0};
+    assign slave_io.r_data = refill_r_data;
+    assign slave_io.r_resp = {refill_resps[refill_idx], 2'b00};
+    assign slave_io.r_last = refill_valids_select[refill_idx][SLAVE_BANK-1];
+    assign slave_io.r_user = 0;
+generate
+    for(genvar i=0; i<SLAVE; i++)begin
+        assign snoop_req[i].ar_snoop_id = refill_idx;
+    end
+endgenerate
+
+
+// dir request
+    MSHREntry dir_entry, dir_entry_n;
+    logic dir_read_once, dir_read_share, dir_read_unique, dir_make_unique, dir_clean_invalid;
+    logic dir_clean_req, dir_write_clean;
+    logic `N(MSHR_SIZE) dir_slave_wreq, dir_slave_we;
+    logic `N(MSHR_SIZE) dir_wreq, dir_we;
+    logic dir_slave_wvalid, dir_wvalid;
+    logic `N(SLAVE) dir_lookup_owner;
+    logic `N(SLAVE) dir_lookup_owner_dec;
+    DirectoryState dir_slave_state, dir_state, dir_wstate;
+    DirWInfo dir_slave_winfo, dir_winfo;
+    logic `N(MSHR_WIDTH) dir_slave_widx, dir_widx;
+generate
+    for(genvar i=0; i<MSHR_SIZE; i++)begin
+        assign paddrs[i] = entrys[i].paddr;
+        assign entry_snoop[i] = entrys[i].snoop;
+    end
+    if(ISL2)begin
+        always_ff @(posedge clk)begin
+            dir_lookup_owner <= dir_entry.id[ID_WIDTH-1 -: 2] == 2'b01;
+            dir_lookup_owner_dec <= dir_entry.id[ID_WIDTH-1 -: 2] == 2'b01;
+        end
+    end
+    else begin
+        logic `N(SLAVE) dir_id_dec;
+        Decoder #(SLAVE) decode_dir_id (dir_entry.id[ID_WIDTH-1 -: SLAVE_WIDTH], dir_id_dec);
+        always_ff @(posedge clk)begin
+            dir_lookup_owner <= dir_entry.id[ID_WIDTH-1 -: SLAVE_WIDTH];
+            dir_lookup_owner_dec <= dir_id_dec;
+        end
+    end
+endgenerate
+    OldestSelect #(MSHR_SIZE, 1, $bits(MSHREntry)) select_dir_paddr (dir_requests, entrys, dir_request, dir_entry);
+    assign mshr_slave_io.request = dir_request;
+    assign mshr_slave_io.raddr = dir_entry.paddr;
+    assign mshr_dir_io.request = dir_request;
+    assign mshr_dir_io.raddr = dir_entry.paddr;
+    PSelector #(MSHR_SIZE) select_dir_request (dir_requests, dir_request_select);
+    PEncoder #(MSHR_SIZE) encoder_dir_request (dir_requests, dir_select_idx);
+    `SIG_N(dir_request, dir_request_n)
+    `SIG_N(dir_entry, dir_entry_n)
+    `SIG_N(dir_select_idx, dir_select_idx_n)
+    always_ff @(posedge clk)begin
+        if(dir_request_n)begin
+            dir_infos[dir_select_idx_n] <= {mshr_slave_io.slave, mshr_slave_io.owner};
+            lookup_ways[dir_select_idx_n] <= mshr_dir_io.hit_way;
+        end
+        dir_read_once <= ~dir_entry.write & (dir_entry.op == `ACEOP_READ_ONCE);
+        dir_read_share <= ~dir_entry.write & (dir_entry.op == `ACEOP_READ_SHARED);
+        dir_read_unique <= ~dir_entry.write & (dir_entry.op == `ACEOP_READ_UNIQUE);
+        dir_make_unique <= ~dir_entry.write & (dir_entry.op == `ACEOP_MAKE_UNIQUE);
+        dir_clean_invalid <= ~dir_entry.write & (dir_entry.op == `ACEOP_CLEAN_INVALID);
+        dir_write_clean <= dir_entry.write & (dir_entry.op == `ACEOP_WRITE_CLEAN);
+        dir_clean_req <= ~dir_entry.write & ((dir_entry.op == `ACEOP_CLEAN_INVALID) | (dir_entry.op == `ACEOP_MAKE_UNIQUE));
+    end
+    always_ff @(posedge clk, posedge rst)begin
+        if(rst == `RST)begin
+            require_data <= 0;
+            dir_slave_wreq <= 0;
+            dir_winfos <= 0;
+            dir_wreq <= 0;
+            dir_finish <= 0;
+        end
+        else begin
+            if(dir_request_n)begin
+                dir_finish[dir_select_idx_n] <= 1'b1;
+                require_data[dir_select_idx_n] <= ~dir_entry_n.write & ~dir_clean_req;
+                dir_slave_wreq[dir_select_idx_n] <= ~dir_read_once & ~((dir_clean_invalid | dir_read_unique & dir_entry_n.snoop) & ~mshr_slave_io.hit);
+                dir_wreq[dir_select_idx_n] <= dir_entry_n.write | dir_read_once & ~mshr_dir_io.hit & ~mshr_slave_io.hit | 
+                                              (dir_clean_req | dir_read_unique & dir_entry_n.snoop) & mshr_dir_io.hit;
+                dir_winfos[dir_select_idx_n] <= '{
+                    waddr: dir_entry_n.paddr,
+                    slave_replace_way: mshr_slave_io.hit ? mshr_slave_io.hit_way : mshr_slave_io.replace_way,
+                    replace_way: mshr_dir_io.hit ? mshr_dir_io.hit_way : mshr_dir_io.replace_way,
+                    slave: dir_entry_n.write | dir_read_unique & dir_entry_n.snoop | dir_clean_invalid ? 0 : // only owner will write
+                           dir_read_share & mshr_slave_io.hit ? mshr_slave_io.slave | dir_lookup_owner_dec : 
+                           dir_read_unique | dir_make_unique ? dir_lookup_owner_dec : mshr_slave_io.slave,
+                    slave_share: mshr_slave_io.share,
+                    write: dir_entry_n.write,
+                    write_dirty: dir_write_clean,       
+                    require_owned: dir_read_unique | dir_make_unique,
+                    slave_hit: mshr_slave_io.hit,
+                    dir_hit: mshr_dir_io.hit,
+                    owned: (dir_read_unique | dir_make_unique | mshr_slave_io.owned),
+                    owner: mshr_slave_io.hit ? mshr_slave_io.owner : dir_lookup_owner
+                };
+            end
+
+            if(|mshr_finish)begin
+                dir_finish[mshr_widx] <= 1'b0;
+            end
+
+            if(mshr_slave_io.we & mshr_slave_io.wready)begin
+                dir_slave_wreq[dir_slave_widx] <= 1'b0;
+            end
+            if(mshr_dir_io.we & mshr_dir_io.wready)begin
+                dir_wreq[dir_widx] <= 1'b0;
+            end
+        end
+    end
+
+    PEncoder #(MSHR_SIZE) encoder_slave_widx (dir_slave_we, dir_slave_widx);
+    assign dir_slave_we = dir_slave_wreq & ~dir_resp_reqs;
+    OldestSelect #(MSHR_SIZE, 1, $bits(DirectoryState)) select_slave_dir_resp (dir_slave_we, refill_resps, dir_slave_wvalid, dir_slave_state);
+    OldestSelect #(MSHR_SIZE, 1, $bits(DirWInfo)) select_slave_winfo (dir_slave_we, dir_winfos, , dir_slave_winfo);
+    assign mshr_slave_io.we = dir_slave_wvalid;
+    assign mshr_slave_io.waddr = dir_slave_winfo.waddr[OFFSET_WIDTH +: $clog2(SLAVE_DIR_SET)];
+    assign mshr_slave_io.wway = dir_slave_winfo.slave_replace_way;
+    assign mshr_slave_io.wdata[SLAVE_TAG_WIDTH-1: 0] = dir_slave_winfo.waddr[OFFSET_WIDTH + $clog2(SLAVE_DIR_SET) +: SLAVE_TAG_WIDTH]; // tag
+    assign mshr_slave_io.wdata[SLAVE_TAG_WIDTH] = ~dir_slave_winfo.require_owned & (dir_slave_winfo.slave_hit | dir_slave_state.share); // share
+    // if write, slave must hit. if read and slave not hit, valid num is 1
+    assign mshr_slave_io.wdata[SLAVE_TAG_WIDTH + 1 +: SLAVE] = dir_slave_winfo.slave; // valid
+    assign mshr_slave_io.wdata[SLAVE_TAG_WIDTH + 1 + SLAVE +: SLAVE_WIDTH] = dir_slave_winfo.owner; // owner
+generate
+    if(!LLC)begin
+        assign mshr_slave_io.wdata[SLAVE_TAG_WIDTH + 1 + SLAVE + SLAVE_WIDTH - 1] = 
+        ~dir_slave_winfo.slave_hit ? dir_slave_state.owned : dir_slave_winfo.owned; // owned
+    end
+endgenerate
+
+    assign dir_we = dir_wreq & ~dir_resp_reqs;
+    PEncoder #(MSHR_SIZE) encoder_dir_widx (dir_we, dir_widx);
+    OldestSelect #(MSHR_SIZE, 1, $bits(DirectoryState)) select_dir_resp (dir_we, refill_resps, dir_wvalid, dir_state);
+    OldestSelect #(MSHR_SIZE, 1, $bits(DirWInfo)) select_dir_winfo (dir_we, dir_winfos, , dir_winfo);
+    assign mshr_dir_io.we = dir_wvalid;
+    assign mshr_dir_io.waddr = dir_winfo.waddr[OFFSET_WIDTH +: SET_WIDTH];
+    assign mshr_dir_io.wway = dir_winfo.replace_way;
+    assign mshr_dir_io.wdata[0] = 1'b1; // valid
+    assign mshr_dir_io.wdata[TAG_WIDTH: 1] = dir_winfo.waddr[OFFSET_WIDTH + SET_WIDTH +: TAG_WIDTH]; // tag
+    assign dir_wstate.dirty = dir_winfo.write ? dir_winfo.write_dirty : dir_state.dirty;
+    assign dir_wstate.share = dir_winfo.write ? dir_winfo.slave_share : dir_state.share;
+    assign dir_wstate.owner = dir_winfo.write ? dir_winfo.owned : dir_state.owner;
+    assign mshr_dir_io.wdata[TAG_WIDTH + 1 +: $bits(DirectoryState)] = dir_wstate; // state
+
+
+// snoop
+    OldestSelect #(MSHR_SIZE, 1, $bits(MSHREntry)) select_snoop_entry (snoop_request, entrys, snoop_valid, snoop_entry);
+    OldestSelect #(MSHR_SIZE, 1, $bits(DirInfo)) select_snoop_dir (snoop_request, dir_infos, , snoop_dir_info);
+    PEncoder #(MSHR_SIZE) encoder_snoop_idx (snoop_request, snoop_idx);
+generate
+    if(SLAVE == 1)begin
+        assign owner_decode = 1'b1;
+    end
+    else begin
+        Decoder #(SLAVE) decode_owner (snoop_dir_info.slave_owner, owner_decode);
+    end
+
+    for(genvar i=0; i<SLAVE; i++)begin
+        assign snoop_req[i].ac_valid = snoop_buffer.slave_request[i];
+        assign snoop_req[i].ac.snoop = snoop_buffer.op;
+        assign snoop_req[i].ac.addr = snoop_buffer.snoop_addr;
+        assign snoop_req[i].ac.prot = 0;
+        assign snoop_req[i].cr_ready = 1'b1;
+        assign snoop_req[i].cd_ready = 1'b1;
+        assign snoop_cd_valids[i] = snoop_resp[i].cd_valid;
+        assign snoop_cd_datas[i] = snoop_resp[i].cd;
+    end
+endgenerate
+    OldestSelect #(SLAVE, 1, $bits(snoop_cd_chan_t)) select_cd (
+        snoop_cd_valids, snoop_cd_datas, snoop_cd_valid, snoop_cd_data
+    );
+
+    always_ff @(posedge clk, posedge rst)begin
+        if(rst == `RST)begin
+            snoop_request <= 0;
+            snoop_replace_request <= 0;
+            snoop_state <= SNOOP_IDLE;
+            snoop_buffer <= 0;
+        end
+        else begin
+            if(dir_request_n & ~dir_entry_n.write & ~dir_clean_req &
+              (mshr_slave_io.hit | ~mshr_slave_io.hit & mshr_slave_io.replace_hit & mshr_slave_io.replace_owned))begin
+                snoop_request[dir_select_idx_n] <= 1'b1;
+            end
+            if(dir_request_n)begin
+                snoop_replace_request[dir_select_idx_n] <= ~dir_entry_n.write & ~dir_clean_req & 
+                                    ~mshr_slave_io.hit & mshr_slave_io.replace_hit & mshr_slave_io.replace_owned;
+            end
+
+            for(int i=0; i<DATA_BANK; i++)begin
+                if(mshr_data_io.wvalid[i])begin
+                    snoop_replace_request[mshr_data_io.wmshr_idx_o[i]] <= 1'b0;
+                end
+            end
+            case(snoop_state)
+            SNOOP_IDLE:begin
+                if(|snoop_request)begin
+                    snoop_state <= SNOOP_REQUEST;
+                    snoop_buffer.idx <= snoop_idx;
+                    snoop_buffer.target_slave <= snoop_entry.op != `ACEOP_MAKE_UNIQUE ? owner_decode : snoop_dir_info.slave;
+                    snoop_buffer.slave_request <= snoop_entry.op != `ACEOP_MAKE_UNIQUE ? owner_decode : snoop_dir_info.slave;
+                    snoop_buffer.snoop_addr <= snoop_entry.paddr;
+                    snoop_buffer.op <= snoop_entry.op == `ACEOP_MAKE_UNIQUE ? `ACEOP_CLEAN_INVALID : snoop_entry.op;
+                    snoop_buffer.response <= 0;
+                    snoop_buffer.require_data <= snoop_entry.op != `ACEOP_MAKE_UNIQUE;
+                    snoop_buffer.slave_replace <= snoop_replace_request[snoop_idx];
+                    snoop_buffer.data_valid <= 0;
+                    snoop_buffer.data_index <= 0;
+                end
+            end
+            SNOOP_REQUEST:begin
+                for(int i=0; i<SLAVE; i++)begin
+                    if(snoop_req[i].ac_valid & snoop_resp[i].ac_ready)begin
+                        snoop_buffer.slave_request[i] <= 1'b0;
+                    end
+                    if(snoop_req[i].cr_ready & snoop_resp[i].cr_valid)begin
+                        snoop_buffer.response[i] <= 1'b1;
+                        if (snoop_buffer.require_data)begin
+                            snoop_buffer.response_state <= snoop_resp[i].cr_resp[4: 2];
+                        end
+                    end
+                end
+                if(snoop_cd_valid)begin
+                    snoop_buffer.data_index <= snoop_buffer.data_index + 1;
+                end
+                if(snoop_cd_valid & snoop_cd_data.last)begin
+                    snoop_buffer.data_valid <= 1'b1;
+                end
+                if((snoop_buffer.require_data & snoop_buffer.data_valid | ~snoop_buffer.require_data) & 
+                ((snoop_buffer.response & snoop_buffer.slave_request) == snoop_buffer.slave_request))begin
+                    snoop_state <= SNOOP_IDLE;
+                    snoop_request[snoop_buffer.idx] <= 1'b0;
+                end
+            end
+            endcase
+        end
+    end
+
+// mst snoop
+    logic mst_snoop_busy, mst_snoop_need_data;
+    logic mst_cr_valid, mst_cd_valid;
+    logic mst_snoop_data_valid;
+    logic `N(MSHR_SIZE) mst_snoop_reqs;
+    logic `N(MSHR_WIDTH) mst_snoop_idx;
+    logic `N(4) mst_snoop_op;
+    logic `N(CACHE_BANK_WIDTH) mst_snoop_data_idx;
+    logic `ARRAY(CACHE_BANK, CACHE_BITS) mst_snoop_data;
+
+    always_ff @(posedge clk, posedge rst)begin
+        if(rst == `RST)begin
+            mst_snoop_op <= 0;
+            mst_snoop_idx <= 0;
+            mst_snoop_reqs <= 0;
+            mst_snoop_need_data <= 0;
+            mst_cr_valid <= 0;
+            mst_cd_valid <= 0;
+            mst_snoop_data_idx <= 0;
+            mst_snoop_data <= 0;
+            mst_snoop_data_valid <= 0;
+        end
+        else begin
+            if(mst_snoop_req.ac_valid & mst_snoop_resp.ac_ready)begin
+                mst_snoop_op <= mst_snoop_req.ac.snoop;
+                mst_snoop_idx <= free_idx1;
+                mst_snoop_reqs[free_idx1] <= 1'b1;
+                mst_snoop_need_data <= mst_snoop_req.ac.snoop != `ACEOP_CLEAN_INVALID;
+                mst_cr_valid <= 1'b1;
+                mst_snoop_data_valid <= 1'b0;
+            end
+            if(mst_snoop_resp.cr_valid & mst_snoop_req.cr_ready)begin
+                mst_cr_valid <= 1'b0;
+                mst_cd_valid <= mst_snoop_need_data;
+                mst_snoop_data_idx <= mst_snoop_data_idx + 1;
+            end
+
+            if(mst_snoop_resp.cd_valid & mst_snoop_req.cd_ready & mst_snoop_resp.cd.last)begin
+                mst_cd_valid <= 1'b0;
+            end
+
+            for(int i=0; i<DATA_BANK; i++)begin
+                if(mshr_data_io.wvalid[i] & mshr_data_io.wmshr_idx_o[i] == mst_snoop_idx)begin
+                    mst_snoop_data <= mshr_data_io.wdata[i];
+                end
+            end
+
+        end
+    end
+
+    assign mst_snoop_resp.cr_valid = mst_cr_valid & (mst_snoop_need_data & ~dir_resp_reqs[mst_snoop_idx] | ~mst_snoop_need_data & ~dir_slave_wreq[mst_snoop_idx] & ~dir_wreq[mst_snoop_idx]);
+    assign mst_snoop_resp.cr_resp = {refill_resps[mst_snoop_idx], 1'b0, mst_snoop_need_data};
+    assign mst_snoop_resp.cd_valid = mst_cd_valid & mst_snoop_data_valid;
+    assign mst_snoop_resp.cd.data = mst_snoop_data[mst_snoop_data_idx];
+    assign mst_snoop_resp.cd.last = mst_snoop_data_idx == CACHE_BANK - 1;
+
+// to l3
+    logic l3_req_last, l3_req_write, l3_req_write_end, l3_data_valid;
+    logic `ARRAY(CACHE_BANK, CACHE_BITS) l3_data;
+    logic `N(DATA_BANK) l3_data_bank, l3_write_data_bank;
+    logic `N(MST_SNOOP_ID_WIDTH) mst_r_id;
+    logic mst_r_ack;
+    OldestSelect #(MSHR_SIZE, 1, $bits(MSHREntry)) select_l3_entry (l3_requests, entrys, l3_request, l3_entry);
+    PSelector #(MSHR_SIZE) selector_l3_idx (l3_requests, l3_idx_dec);
+    PEncoder #(MSHR_SIZE) encoder_l3_idx (l3_requests, l3_idx);
+
+generate
+    if(ISL2)begin
+        always_ff @(posedge clk, posedge rst)begin
+            if(master_io.r_valid & master_io.r_ready)begin
+                l3_data[l3_buffer.data_index] <= master_io.r_data;
+            end
+        end
+        always_ff @(posedge clk, posedge rst)begin
+            if(rst == `RST)begin
+                l3_req_write <= 0;
+                l3_req_write_end <= 0;
+                l3_data_valid <= 0;
+                mst_r_id <= 0;
+                mst_r_ack <= 0;
+            end
+            else begin
+                if((l3_state == L3_REQUEST) & l3_data_valid &
+                   (~replace_reqs[l3_buffer.idx] | replace_busy & 
+                   replace_buffer.replace_data_valid & (replace_buffer.idx == l3_buffer.idx)))begin
+                    l3_req_write <= 1'b1;
+                end
+                if(~(|(l3_data_bank & write_bank_req)) & l3_req_write)begin
+                    l3_req_write <= 1'b0;
+                end
+                if(l3_state == L3_IDLE && l3_request)begin
+                    l3_req_write_end <= 1'b0;
+                end
+                else if(|l3_write_data_bank)begin
+                    l3_req_write_end <= 1'b1;
+                end
+                if(master_io.r_valid & master_io.r_last)begin
+                    l3_data_valid <= 1'b1;
+                    mst_r_id <= mst_snoop_req.ar_snoop_id;
+                    mst_r_ack <= 1'b1;
+                end
+                if(mst_r_ack)begin
+                    mst_r_ack <= 1'b0;
+                end
+                else if(l3_state == L3_IDLE)begin
+                    l3_data_valid <= 1'b0;
+                end
+            end
+        end
+
+        for(genvar i=0; i<DATA_BANK; i++)begin
+            assign l3_write_data_bank[i] = mshr_data_io.wvalid[i] & (mshr_data_io.wmshr_idx_o[i] == l3_buffer.idx);
+        end
+    end
+endgenerate
+    always_ff @(posedge clk, posedge rst)begin
+        if(rst == `RST)begin
+            l3_requests <= 0;
+            l3_state <= L3_IDLE;
+            l3_req_last <= 1'b0;
+            l3_buffer <= 0;
+        end
+        else begin
+            if(dir_request_n & (~mshr_dir_io.hit & ~mshr_slave_io.hit | dir_make_unique & ~LLC) & 
+              ~dir_entry_n.write & ~dir_clean_invalid)begin
+                l3_requests[dir_select_idx_n] <= 1'b1;
+            end
+            case(l3_state)
+            L3_IDLE: begin
+                if(l3_request)begin
+                    l3_state <= L3_REQUEST;
+                    l3_buffer.idx <= l3_idx_dec;
+                    l3_buffer.addr <= l3_entry.paddr;
+                    l3_buffer.request <= 1'b1;
+                    l3_buffer.id <= l3_entry.id;
+                    l3_buffer.op <= l3_entry.op == `ACEOP_READ_ONCE ? `ACEOP_READ_SHARED : l3_entry.op;
+                    l3_buffer.data_index <= 0;
+                end
+            end
+            L3_REQUEST: begin
+                if(master_io.ar_valid & master_io.ar_ready)begin
+                    l3_buffer.request <= 1'b0;
+                end
+                if(master_io.r_valid)begin
+                    l3_buffer.data_index <= l3_buffer.data_index + 1;
+                end
+                if(master_io.r_valid & master_io.r_last & ISL2)begin
+                    l3_req_last <= 1'b1;
+                end
+                if((master_io.r_valid & master_io.r_last | l3_req_last & ISL2) &
+                   (~ISL2 | ISL2 & ~replace_reqs[l3_buffer.idx] & l3_req_write_end))begin
+                    l3_state <= L3_IDLE;
+                    l3_requests[l3_idx] <= 1'b0;
+                end
+            end
+            endcase
+        end
+    end
+
+    assign master_io.ar_valid = l3_buffer.request;
+    assign master_io.ar_id = l3_buffer.id;
+    assign master_io.ar_addr = l3_buffer.addr;
+    assign master_io.ar_len = DATA_BANK - 1;
+    assign master_io.ar_size = $clog2(`CACHELINE_SIZE / DATA_BANK);
+    assign master_io.ar_burst = 2'b01;
+    assign master_io.ar_user = 0;
+    assign master_io.ar_snoop = l3_buffer.op;
+    assign master_io.r_ready = 1'b1;
+    assign mst_snoop_resp.r_snoop_id = mst_r_id;
+    assign mst_snoop_resp.rack = mst_r_ack;
+
+// write
+    logic `N(MSHR_SIZE) write_req, write_data_finish;
+    logic `N(MSHR_WIDTH) write_b_idx, write_data_finish_idx;
+    logic `ARRAY(MSHR_SIZE, ID_WIDTH) write_b_ids;
+    logic `N(ID_WIDTH) write_b_id;
+    logic write_b_req;
+    always_ff @(posedge clk)begin
+        if(slave_io.w_valid & slave_io.w_ready)begin
+            write_buffer[write_idx][write_data_index] <= slave_io.w_data;
+        end
+        if(snoop_cd_valid & snoop_buffer.slave_replace)begin
+            write_buffer[snoop_buffer.idx][snoop_buffer.data_index] <= snoop_cd_data.data;
+        end
+    end
+
+    PEncoder #(MSHR_SIZE) encoder_write_b_idx(write_data_finish, write_data_finish_idx);
+    OldestSelect #(MSHR_SIZE, 1, ID_WIDTH) select_b_id (write_data_finish, write_b_ids, write_b_req, write_b_id);
+
+    always_ff @(posedge clk, posedge rst)begin
+        if(rst == `RST)begin
+            write_idx <= 0;
+            write_data_index <= 0;
+            write_waiting <= 0;
+            slave_b_valid <= 1'b0;
+            write_id <= 0;
+            slave_b_id <= 0;
+            write_data_valid <= 0;
+            write_req <= 0;
+            write_b_idx <= 0;
+            write_data_finish <= 0;
+            write_b_ids <= 0;
+        end
+        else begin
+            if(slave_io.aw_valid & slave_io.aw_ready)begin
+                write_idx <= free_idx1;
+                write_waiting <= 1'b1;
+                write_id <= slave_io.aw_id[ID_OFFSET +: ID_WIDTH];
+                write_data_index <= 0;
+                write_req[free_idx1] <= 1'b1;
+                write_data_valid[free_idx1] <= 1'b0;
+            end
+
+            if(dir_request_n & ~dir_entry_n.write)begin
+                write_data_valid[dir_select_idx_n] <= 1'b0;
+            end
+            
+            if(slave_io.w_valid)begin
+                write_data_index <= write_data_index + 1;
+            end
+            if(slave_io.w_valid & slave_io.w_last)begin
+                write_data_valid[write_idx] <= 1'b1;
+            end
+            if(snoop_cd_valid & snoop_cd_data.last & snoop_buffer.slave_replace)begin
+                write_data_valid[snoop_buffer.idx] <= 1'b1;
+            end
+            if(slave_io.w_valid & slave_io.w_last)begin
+                write_waiting <= 1'b0;
+                write_b_ids[write_idx] <= write_id;
+            end
+
+            if(write_b_req & ~slave_b_valid)begin
+                slave_b_valid <= 1'b1;
+                slave_b_id <= write_b_id;
+                write_b_idx <= write_data_finish_idx;
+            end
+
+            if(slave_io.b_valid & slave_io.b_ready)begin
+                slave_b_valid <= 1'b0;
+                write_req[write_b_idx] <= 1'b0;
+                write_data_finish[write_b_idx] <= 1'b0;
+            end
+
+            for(int i=0; i<DATA_BANK; i++)begin
+                if(mshr_data_io.wvalid[i] & (entrys[mshr_data_io.wmshr_idx_o[i]].write))begin
+                    write_data_finish[mshr_data_io.wmshr_idx_o[i]] <= 1'b1;
+                end
+            end
+        end
+    end
+    assign slave_io.w_ready = 1'b1;
+    assign slave_io.b_valid = slave_b_valid;
+    assign slave_io.b_id = {slave_b_id, 1'b0};
+    assign slave_io.b_resp = 0;
+    assign slave_io.b_user = 0;
+
+
+// lookup
+    always_ff @(posedge clk, posedge rst)begin
+        if(rst == `RST)begin
+            lookup_addrs <= 0;
+        end
+        else begin
+            for(int i=0; i<MSHR_SIZE; i++)begin
+                if(free_en1[i] & slave_io.aw_valid | free_en2[i] & slave_io.ar_valid & ~ar_free_conflict)begin
+                    lookup_addrs[i] <= free_en1[i] & slave_io.aw_valid ? slave_io.aw_addr[OFFSET_WIDTH +: SET_WIDTH] : slave_io.ar_addr[OFFSET_WIDTH +: SET_WIDTH];
+                end
+            end
+        end
+    end
+    
+generate
+    if(DATA_BANK == 1)begin
+        assign lookup_bank = {MSHR_SIZE{1'b1}};
+        assign lookup_bank_rev = lookup_bank;
+        assign l3_data_bank = 1;
+    end
+    else begin
+        for(genvar i=0; i<MSHR_SIZE; i++)begin
+            Decoder #(DATA_BANK) decoder_bank (lookup_addrs[i][0 +: DATA_BANK_WIDTH], lookup_bank[i]);
+            for(genvar j=0; j<DATA_BANK; j++)begin
+                assign lookup_bank_rev[j][i] = lookup_bank[i][j];
+            end
+        end
+        Decoder #(DATA_BANK) decoder_l3_bank (l3_buffer.addr[OFFSET_WIDTH +: DATA_BANK_WIDTH], l3_data_bank);
+    end
+
+    for(genvar i=0; i<DATA_BANK; i++)begin
+        logic `N(MSHR_SIZE) lookup_bank_request;
+        logic `N(SET_WIDTH) lookup_data_addr;
+        logic `N(WAY_WIDTH) lookup_way;
+        logic `N(MSHR_WIDTH) lookup_idx;
+
+        assign lookup_bank_request = lookup_requests & lookup_bank_rev[i];
+        OldestSelect #(MSHR_SIZE, 1, SET_WIDTH) select_lookup (lookup_bank_request, lookup_addrs, lookup_data_req[i], lookup_data_addr);
+        OldestSelect #(MSHR_SIZE, 1, WAY_WIDTH) select_rway (lookup_bank_request, lookup_ways, , lookup_way);
+        PEncoder #(MSHR_SIZE) encoder_lookup_idx (lookup_bank_request, lookup_idx);
+
+        assign mshr_data_io.req = lookup_data_req[i] | replace_read_req & replace_buffer.data_bank[i];
+        assign mshr_data_io.rway = lookup_data_req[i] ? lookup_way : replace_buffer.way;
+        if(DATA_BANK == 1)begin
+            assign mshr_data_io.raddr = lookup_data_req[i] ? lookup_data_addr : replace_buffer.addr[`CACHELINE_WIDTH +: SET_WIDTH];
+        end
+        else begin
+            assign mshr_data_io.raddr = lookup_data_req[i] ? lookup_data_addr[SET_WIDTH-1: DATA_BANK_WIDTH] : replace_buffer.addr[`CACHELINE_WIDTH +: SET_WIDTH - DATA_BANK_WIDTH];
+        end
+        assign mshr_data_io.mshr_idx = lookup_data_req[i] ? lookup_idx : replace_buffer.idx;
+
+        logic `N(MSHR_SIZE) write_bank_requests;
+        logic `N(MSHR_WIDTH) write_bank_idx;
+        logic `N(SET_WIDTH) write_addr;
+        logic `N(WAY_WIDTH) write_way;
+        logic `ARRAY(SLAVE_BANK, SLAVE_BITS) write_data;
+        assign write_bank_requests = write_data_valid & (~replace_reqs | replace_data_valids) & lookup_bank_rev[i];
+        PEncoder #(MSHR_SIZE) encoder_write_bank_idx (write_bank_requests, write_bank_idx);
+        OldestSelect #(MSHR_SIZE, 1, SET_WIDTH) select_write_addr (write_bank_requests, lookup_addrs, write_bank_req[i], write_addr);
+        OldestSelect #(MSHR_SIZE, 1, SET_WIDTH) select_write_way (write_bank_requests, lookup_ways, , write_way);
+        assign write_data = write_buffer[write_bank_idx];
+
+        if(ISL2)begin
+            assign mshr_data_io.we[i] = write_bank_req[i];
+            assign mshr_data_io.wway[i] = write_way;
+            assign mshr_data_io.wmshr_idx[i] = write_bank_idx;
+            if(DATA_BANK == 1)begin
+                assign mshr_data_io.waddr[i] = write_addr;
+            end
+            else begin
+                assign mshr_data_io.waddr[i] = write_addr[SET_WIDTH-1: DATA_BANK_WIDTH];
+            end
+            assign mshr_data_io.wdata[i] = write_data;
+        end
+        else begin
+            assign mshr_data_io.we[i] = write_bank_req[i] | l3_req_write & l3_data_bank[i];
+            assign mshr_data_io.wway[i] = write_bank_req[i] ? write_way : replace_ways[l3_buffer.idx];
+            assign mshr_data_io.wmshr_idx[i] = write_bank_req[i] ? write_bank_idx : l3_buffer.idx;
+            if(DATA_BANK == 1)begin
+                assign mshr_data_io.waddr[i] = write_bank_req[i] ? write_addr : l3_buffer.addr[OFFSET_WIDTH +: SET_WIDTH];
+            end
+            else begin
+                assign mshr_data_io.waddr[i] = write_bank_req[i] ? write_addr[SET_WIDTH-1: DATA_BANK_WIDTH] : l3_buffer.addr[OFFSET_WIDTH +: SET_WIDTH - DATA_BANK_WIDTH];
+            end
+            assign mshr_data_io.wdata[i] = write_bank_req[i] ? write_data : l3_data;
+        end
+    end
+endgenerate
+
+    always_ff @(posedge clk, posedge rst)begin
+        if(rst == `RST)begin
+            lookup_requests <= 0;
+        end
+        else begin
+            if(dir_request_n & mshr_dir_io.hit & ~dir_entry_n.write & ~dir_clean_req)begin
+                lookup_requests[dir_select_idx_n] <= 1'b1;
+            end
+            for(int i=0; i<DATA_BANK; i++)begin
+                if(mshr_data_io.req[i] & mshr_data_io.ready[i])begin
+                    lookup_requests[mshr_data_io.mshr_idx[i]] <= 1'b0;
+                end
+            end
+        end
+    end
+
+
+// replace
+    always_ff @(posedge clk)begin
+        if(dir_request_n)begin
+            replace_ways[dir_select_idx_n] <= mshr_dir_io.hit ? mshr_dir_io.hit_way : mshr_dir_io.replace_way;
+            replace_tags[dir_select_idx_n] <= {mshr_dir_io.replace_tagv[TAG_WIDTH: 1], mshr_dir_io.replace_state.dirty};
+        end
+    end
+generate
+    if(LLC)begin
+        assign replace_cond_valid = mshr_dir_io.replace_tagv[0] & mshr_dir_io.replace_state.dirty; // dirty
+    end
+    else begin
+        assign replace_cond_valid = mshr_dir_io.replace_tagv[0] & mshr_dir_io.replace_state.owner; // owner
+    end
+    assign write_replace_cond = dir_request_n & ~mshr_dir_io.hit & dir_entry_n.write & replace_cond_valid;
+    if(ISL2)begin
+        // icache is inclusive, replace is needed, and it doesn't affect slave directory
+        assign read_replace_cond = dir_request_n & ~mshr_dir_io.hit & ~dir_entry_n.write & 
+                                replace_cond_valid & ~mshr_slave_io.hit & (dir_read_once | 
+        (~dir_clean_req & mshr_slave_io.replace_hit & mshr_slave_io.replace_owned));
+    end
+    else begin
+        // if slave directory need replace, slave data is replaced to l2
+        // so l2 also need to replace
+        assign read_replace_cond = dir_request_n & ~mshr_dir_io.hit & ~mshr_slave_io.hit & 
+                                ~dir_entry_n.write & ~dir_clean_req &
+                    mshr_slave_io.replace_hit & mshr_slave_io.replace_owned & replace_cond_valid;
+    end
+
+    if(DATA_BANK == 1)begin
+        assign replace_data_bank = 1;
+    end
+    else begin
+        Decoder #(DATA_BANK) decoder_replace_bank (replace_entry.paddr[`DCACHE_LINE_WIDTH +: DATA_BANK_WIDTH], replace_data_bank);
+    end
+
+    for(genvar i=0; i<DATA_BANK; i++)begin
+        assign replace_data_hits[i] = mshr_data_io.rvalid[i] & (mshr_data_io.mshr_idx_o == replace_buffer.idx);
+    end
+endgenerate
+    OldestSelect #(MSHR_SIZE, 1, $bits(MSHREntry)) select_replace_entry (replace_reqs, entrys, replace_req, replace_entry);
+    OldestSelect #(MSHR_SIZE, 1, TAG_WIDTH+1) select_replace_tag (replace_reqs, replace_tags, , replace_tag);
+    PEncoder #(MSHR_SIZE) encoder_replace_idx (replace_reqs, replace_idx);
+    OldestSelect #(MSHR_SIZE, 1, WAY_NUM) select_replace_way(replace_reqs, replace_ways, , replace_way_select);
+    assign replace_read_conflict = |(replace_buffer.data_bank & lookup_data_req);
+    FairSelect #(DATA_BANK, `DCACHE_BITS * `DCACHE_BANK) select_replace_data (replace_data_hits, mshr_data_io.rdata, replace_data_hit, replace_read_data);
+
+    always_ff @(posedge clk, posedge rst)begin
+        if(rst == `RST)begin
+            replace_reqs <= 0;
+            replace_data_valids <= 0;
+            replace_busy <= 0;
+            replace_buffer <= 0;
+            replace_read_req <= 0;
+        end
+        else begin
+            if(write_replace_cond | read_replace_cond)begin
+                replace_reqs[dir_select_idx_n] <= 1'b1;
+            end
+
+            if(~replace_busy)begin
+                if(replace_req)begin
+                    replace_busy <= 1'b1;
+                    replace_buffer.aw_valid <= 1'b1;
+                    replace_buffer.addr <= {replace_tag[TAG_WIDTH: 1], replace_entry.paddr[TAG_WIDTH-1: 0]};
+                    replace_buffer.id <= replace_entry.id;
+                    replace_buffer.dirty <= replace_tag[0];
+                    replace_buffer.idx <= replace_idx;
+                    replace_buffer.way <= replace_way_select;
+                    replace_buffer.data_bank <= replace_data_bank;
+                    replace_buffer.replace_data_valid <= 1'b0;
+                    replace_buffer.data_index <= 0;
+                    replace_read_req <= 1'b1;
+                    replace_data_valids[replace_idx] <= 1'b0;
+                end
+            end
+            else begin
+                if(master_io.aw_valid & master_io.aw_ready)begin
+                    replace_buffer.aw_valid <= 1'b0;
+                end
+                if(replace_read_req & ~replace_read_conflict)begin
+                    replace_read_req <= 1'b0;
+                end
+                if(replace_data_hit)begin
+                    replace_buffer.replace_data_valid <= 1'b1;
+                    replace_buffer.replace_data <= replace_read_data;
+                    replace_data_valids[replace_buffer.idx] <= 1'b1;
+                end
+                if(master_io.w_valid & master_io.w_ready)begin
+                    replace_buffer.data_index <= replace_buffer.data_index + 1;
+                    if(replace_buffer.w_last)begin
+                        replace_buffer.w_last <= 1'b0;
+                        replace_buffer.replace_data_valid <= 1'b0;
+                    end
+                    else if(replace_buffer.data_index == `DCACHE_BANK - 2)begin
+                        replace_buffer.w_last <= 1'b1;
+                    end
+                end
+                if(master_io.b_valid & master_io.b_ready)begin
+                    replace_busy <= 1'b0;
+                    replace_reqs[replace_buffer.idx] <= 1'b0;
+                end
+            end
+        end
+    end
+
+    assign master_io.aw_valid = replace_buffer.aw_valid;
+    assign master_io.aw_id = replace_buffer.id;
+    assign master_io.aw_addr = replace_buffer.addr;
+    assign master_io.aw_burst = 2'b01;
+    assign master_io.aw_size = $clog2(`DCACHE_BYTE);
+    assign master_io.aw_len = `DCACHE_BANK - 1;
+    assign master_io.aw_user = 0;
+    assign master_io.aw_snoop = replace_buffer.dirty ? `ACEOP_WRITE_CLEAN : `ACEOP_WRITE_EVICT;
+
+    assign master_io.w_valid = replace_busy & ~replace_buffer.aw_valid & replace_buffer.replace_data_valid;
+    assign master_io.w_data = replace_buffer.replace_data[replace_buffer.data_index];
+    assign master_io.w_strb = {`DCACHE_BYTE{1'b1}};
+    assign master_io.w_last = replace_buffer.w_last;
+    assign master_io.w_user = 0;
+
+    assign master_io.b_ready = 1'b1;
+endmodule
\ No newline at end of file
diff --git a/src/core/mmu/DTLB.sv b/src/core/mem/mmu/DTLB.sv
similarity index 99%
rename from src/core/mmu/DTLB.sv
rename to src/core/mem/mmu/DTLB.sv
index a02fdec..7e8567a 100644
--- a/src/core/mmu/DTLB.sv
+++ b/src/core/mem/mmu/DTLB.sv
@@ -1,4 +1,4 @@
-`include "../../defines/defines.svh"
+`include "../../../defines/defines.svh"
 
 module DTLB(
     input logic clk,
diff --git a/src/core/mmu/ITLB.sv b/src/core/mem/mmu/ITLB.sv
similarity index 99%
rename from src/core/mmu/ITLB.sv
rename to src/core/mem/mmu/ITLB.sv
index e2fdf27..afad54d 100644
--- a/src/core/mmu/ITLB.sv
+++ b/src/core/mem/mmu/ITLB.sv
@@ -1,4 +1,4 @@
-`include "../../defines/defines.svh"
+`include "../../../defines/defines.svh"
 
 module ITLB(
     input logic clk,
diff --git a/src/core/mmu/L2TLB.sv b/src/core/mem/mmu/L2TLB.sv
similarity index 98%
rename from src/core/mmu/L2TLB.sv
rename to src/core/mem/mmu/L2TLB.sv
index eb8c5db..b260fed 100644
--- a/src/core/mmu/L2TLB.sv
+++ b/src/core/mem/mmu/L2TLB.sv
@@ -1,4 +1,4 @@
-`include "../../defines/defines.svh"
+`include "../../../defines/defines.svh"
 
 module L2TLB(
     input logic clk,
diff --git a/src/core/mmu/PMPCheck.sv b/src/core/mem/mmu/PMPCheck.sv
similarity index 98%
rename from src/core/mmu/PMPCheck.sv
rename to src/core/mem/mmu/PMPCheck.sv
index ab5940d..e193a6e 100644
--- a/src/core/mmu/PMPCheck.sv
+++ b/src/core/mem/mmu/PMPCheck.sv
@@ -1,4 +1,4 @@
-`include "../../defines/defines.svh"
+`include "../../../defines/defines.svh"
 
 module PMPCheck (
     input logic `N(`PADDR_SIZE-`TLB_OFFSET) paddr,
diff --git a/src/core/mmu/PTW.sv b/src/core/mem/mmu/PTW.sv
similarity index 99%
rename from src/core/mmu/PTW.sv
rename to src/core/mem/mmu/PTW.sv
index 87a455d..d5ce260 100644
--- a/src/core/mmu/PTW.sv
+++ b/src/core/mem/mmu/PTW.sv
@@ -1,4 +1,4 @@
-`include "../../defines/defines.svh"
+`include "../../../defines/defines.svh"
 
 interface PTWL2IO;
     logic valid;
diff --git a/src/core/mmu/TLB.sv b/src/core/mem/mmu/TLB.sv
similarity index 99%
rename from src/core/mmu/TLB.sv
rename to src/core/mem/mmu/TLB.sv
index aab53d0..6c97e83 100644
--- a/src/core/mmu/TLB.sv
+++ b/src/core/mem/mmu/TLB.sv
@@ -1,4 +1,4 @@
-`include "../../defines/defines.svh"
+`include "../../../defines/defines.svh"
 
 interface TLBIO #(
     parameter DEPTH=16,
diff --git a/src/core/mmu/TLBCache.sv b/src/core/mem/mmu/TLBCache.sv
similarity index 99%
rename from src/core/mmu/TLBCache.sv
rename to src/core/mem/mmu/TLBCache.sv
index 3054ff0..26fd83c 100644
--- a/src/core/mmu/TLBCache.sv
+++ b/src/core/mem/mmu/TLBCache.sv
@@ -1,4 +1,4 @@
-`include "../../defines/defines.svh"
+`include "../../../defines/defines.svh"
 
 interface TLBCacheIO;
     logic req;
diff --git a/src/core/mmu/TLBRepeater.sv b/src/core/mem/mmu/TLBRepeater.sv
similarity index 95%
rename from src/core/mmu/TLBRepeater.sv
rename to src/core/mem/mmu/TLBRepeater.sv
index 2a77dc7..090905a 100644
--- a/src/core/mmu/TLBRepeater.sv
+++ b/src/core/mem/mmu/TLBRepeater.sv
@@ -1,4 +1,4 @@
-`include "../../defines/defines.svh"
+`include "../../../defines/defines.svh"
 
 module TLBRepeater #(
     parameter FRONT=0
diff --git a/src/defines/arch.svh b/src/defines/arch.svh
index 4212859..f67e6bc 100644
--- a/src/defines/arch.svh
+++ b/src/defines/arch.svh
@@ -12,6 +12,7 @@
 
 `define FEAT_SC
 `define FEAT_ITTAGE_REGION
+`define FEAT_L2CACHE
 
 // `define SYNTH_VIVADO
 
diff --git a/src/defines/bundles.svh b/src/defines/bundles.svh
index e4e438c..12cbacd 100644
--- a/src/defines/bundles.svh
+++ b/src/defines/bundles.svh
@@ -633,13 +633,17 @@ typedef struct packed {
     logic `ARRAY(`WALK_WIDTH, `PREG_WIDTH) old_prd;
 } CommitWalk;
 
-`define DIRECTORY_ENTRY_DEF(NUM_ENTRY)  \
-typedef struct packed { \
-    logic en; \
-    CoherentState state; \
-    logic `N($clog2(NUM_ENTRY+1)) owner; \
-    logic `N(NUM_ENTRY) sharers; \
-} DirectoryEntry;
+typedef struct packed {
+    logic owner;
+    logic share;
+    logic dirty;
+} DirectoryState;
 
+typedef struct packed {
+    logic v;
+    logic owned;
+    logic share;
+    logic dirty;
+} DCacheMeta;
 
 `endif
\ No newline at end of file
diff --git a/src/defines/bus/ace.svh b/src/defines/bus/ace.svh
index 1b69c42..d4d33e0 100644
--- a/src/defines/bus/ace.svh
+++ b/src/defines/bus/ace.svh
@@ -134,11 +134,13 @@ endinterface
 // Snoop bus interafces
 interface SnoopIO #(
   parameter int SNOOP_ADDR_WIDTH = 0,
-  parameter int SNOOP_DATA_WIDTH = 0
+  parameter int SNOOP_DATA_WIDTH = 0,
+  parameter int SNOOP_ID_WIDTH   = 0
 );
 
   typedef logic [SNOOP_ADDR_WIDTH-1:0] addr_t;
   typedef logic [SNOOP_DATA_WIDTH-1:0] data_t;
+  typedef logic [SNOOP_ID_WIDTH-1:0] ack_id_t;
 
   addr_t                ac_addr;
   logic [2: 0]   ac_prot;
@@ -155,16 +157,24 @@ interface SnoopIO #(
   logic                 cd_valid;
   logic                 cd_ready;
 
+  // same as rack in ace
+  // but here add id to support outstanding
+  ack_id_t        ar_snoop_id;
+  ack_id_t        r_snoop_id;
+  logic rack;
+
   modport master (
     input   ac_addr, ac_prot, ac_snoop, ac_valid, output ac_ready,
     input   cr_ready, output cr_valid, cr_resp,
-    input   cd_ready, output cd_data, cd_last, cd_valid
+    input   cd_ready, output cd_data, cd_last, cd_valid,
+    output ar_snoop_id, input r_snoop_id, rack
   );
 
- modport slave (
+  modport slave (
     output   ac_addr, ac_prot, ac_snoop, ac_valid, input ac_ready,
     output   cr_ready, input cr_valid, cr_resp,
-    output   cd_ready, input cd_data, cd_last, cd_valid
+    output   cd_ready, input cd_data, cd_last, cd_valid,
+    input ar_snoop_id, output r_snoop_id, rack
   );
 
 endinterface
@@ -200,61 +210,6 @@ interface NativeSnoopIO #(
   );
 endinterface
 
-  /// Slice on Demux AW channel.
-  localparam logic [9:0] DemuxAw = (1 << 9);
-  /// Slice on Demux W channel.
-  localparam logic [9:0] DemuxW  = (1 << 8);
-  /// Slice on Demux B channel.
-  localparam logic [9:0] DemuxB  = (1 << 7);
-  /// Slice on Demux AR channel.
-  localparam logic [9:0] DemuxAr = (1 << 6);
-  /// Slice on Demux R channel.
-  localparam logic [9:0] DemuxR  = (1 << 5);
-  /// Slice on Mux AW channel.
-  localparam logic [9:0] MuxAw   = (1 << 4);
-  /// Slice on Mux W channel.
-  localparam logic [9:0] MuxW    = (1 << 3);
-  /// Slice on Mux B channel.
-  localparam logic [9:0] MuxB    = (1 << 2);
-  /// Slice on Mux AR channel.
-  localparam logic [9:0] MuxAr   = (1 << 1);
-  /// Slice on Mux R channel.
-  localparam logic [9:0] MuxR    = (1 << 0);
-  /// Latency configuration for `ace_xbar`.
-  typedef enum logic [9:0] {
-    NO_LATENCY    = 10'b000_00_000_00,
-    CUT_SLV_AX    = DemuxAw | DemuxAr,
-    CUT_MST_AX    = MuxAw | MuxAr,
-    CUT_ALL_AX    = DemuxAw | DemuxAr | MuxAw | MuxAr,
-    CUT_SLV_PORTS = DemuxAw | DemuxW | DemuxB | DemuxAr | DemuxR,
-    CUT_MST_PORTS = MuxAw | MuxW | MuxB | MuxAr | MuxR,
-    CUT_ALL_PORTS = 10'b111_11_111_11
-  } ccu_latency_e;
-
-  /// Configuration for `ace_ccu`.
-  typedef struct packed {
-    int  NoSlvPorts;
-    int  MaxMstTrans;
-    int  MaxSlvTrans;
-    bit           FallThrough;
-    ccu_latency_e LatencyMode;
-    int  AxiIdWidthSlvPorts;
-    int  AxiIdUsedSlvPorts;
-    bit           UniqueIds;
-    int  AxiAddrWidth;
-    int  AxiDataWidth;
-    int  AxiUserWidth;
-    int  DcacheLineWidth;
-  } ccu_cfg_t;
-
-  typedef struct packed {
-    logic        wasUnique;
-    logic        isShared;
-    logic        passDirty;
-    logic        error;
-    logic        dataTransfer;
-  } crresp_t;
-
   `define ACEOP_READ_ONCE  4'b0000
   `define ACEOP_READ_SHARED 4'b0001
   `define ACEOP_READ_CLEAN 4'b0010
@@ -356,21 +311,24 @@ endinterface
     logic                 last;                                 \
   } cd_chan_t;
 `define SNOOP_TYPEDEF_CR_CHAN_T(cr_chan_t)                      \
-   typedef crresp_t     cr_chan_t;
-`define SNOOP_TYPEDEF_REQ_T(req_t, ac_chan_t)      \
+   typedef logic [4: 0]     cr_chan_t;
+`define SNOOP_TYPEDEF_REQ_T(req_t, ac_chan_t, ack_id_t)      \
   typedef struct packed {                                       \
     logic     ac_valid;                                         \
     logic     cd_ready;                                         \
     ac_chan_t ac;                                               \
     logic     cr_ready;                                         \
+    ack_id_t ar_snoop_id;                                       \
   } req_t;
-`define SNOOP_TYPEDEF_RESP_T(resp_t, cd_chan_t, cr_chan_t)      \
+`define SNOOP_TYPEDEF_RESP_T(resp_t, cd_chan_t, cr_chan_t, ack_id_t)      \
   typedef struct packed {                                       \
     logic     ac_ready;                                         \
     logic     cd_valid;                                         \
     cd_chan_t cd;                                               \
     logic     cr_valid;                                         \
     cr_chan_t cr_resp;                                          \
+    ack_id_t  r_snoop_id;                                       \
+    logic     rack;                                             \
   } resp_t;
 `define __ACE_TO_AW(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep)   \
   __opt_as __lhs``__lhs_sep``id     = __rhs``__rhs_sep``id;         \
diff --git a/src/defines/bus/mem.svh b/src/defines/bus/mem.svh
index 17c2a42..48f8257 100644
--- a/src/defines/bus/mem.svh
+++ b/src/defines/bus/mem.svh
@@ -50,7 +50,7 @@ interface CacheBus #(
 
     id_t         r_id;
     data_t       r_data;
-    logic  [3:0] r_resp;
+    logic  [4:0] r_resp;
     logic        r_last;
     user_t       r_user;
     logic        r_valid;
@@ -253,5 +253,32 @@ endinterface //CacheBus
     assign rhs.aw_ready = lhs.aw_ready; \
     assign rhs.w_ready = lhs.w_ready; \
     assign rhs.b_valid = lhs.b_valid;
+`define CACHE_ASSIGN_TO_AXI(axi_if, cache_if) \
+    assign axi_if.ar_id     = cache_if.ar_id; \
+    assign axi_if.ar_addr   = cache_if.ar_addr; \
+    assign axi_if.ar_len    = cache_if.ar_len; \
+    assign axi_if.ar_size   = cache_if.ar_size; \
+    assign axi_if.ar_burst  = cache_if.ar_burst; \
+    assign axi_if.ar_user   = cache_if.ar_user; \
+    `__CACHE_TO_R(assign, cache_if.r, _, axi_if.r, _) \
+    assign axi_if.aw_id     = cache_if.aw_id; \
+    assign axi_if.aw_addr   = cache_if.aw_addr; \
+    assign axi_if.aw_len    = cache_if.aw_len; \
+    assign axi_if.aw_size   = cache_if.aw_size; \
+    assign axi_if.aw_burst  = cache_if.aw_burst; \
+    assign axi_if.aw_user   = cache_if.aw_user; \
+    `__CACHE_TO_W(assign, axi_if.w, _, cache_if.w, _) \
+    `__CACHE_TO_B(assign, cache_if.b, _, axi_if.b, _) \
+    assign axi_if.ar_valid = cache_if.ar_valid; \
+    assign cache_if.ar_ready = axi_if.ar_ready; \
+    assign cache_if.r_valid = axi_if.r_valid; \
+    assign axi_if.r_ready = cache_if.r_ready; \
+    assign axi_if.aw_valid = cache_if.aw_valid; \
+    assign axi_if.w_valid = cache_if.w_valid; \
+    assign axi_if.b_ready = cache_if.b_ready; \
+    assign cache_if.aw_ready = axi_if.aw_ready; \
+    assign cache_if.w_ready = axi_if.w_ready; \
+    assign cache_if.b_valid = axi_if.b_valid;
+
 
 `endif
\ No newline at end of file
diff --git a/src/defines/global.svh b/src/defines/global.svh
index 1b48569..e6779a5 100644
--- a/src/defines/global.svh
+++ b/src/defines/global.svh
@@ -12,7 +12,7 @@
 
 
 `define NUM_CORE 1
-`define CORE_WIDTH $clog2(`NUM_CORE + 1)
+`define CORE_WIDTH $clog2(`NUM_CORE)
 
 `define RST 1'b1
 `ifdef RV32I
@@ -149,6 +149,9 @@ typedef enum logic [1:0] {
 `define FSQ_SIZE 32
 `define FSQ_WIDTH $clog2(`FSQ_SIZE)
 
+`define CACHELINE_SIZE 64
+`define CACHELINE_WIDTH $clog2(`CACHELINE_SIZE)
+
 // icache
 `define ICACHE_ID 4'b0
 `define ICACHE_SET 64
@@ -299,7 +302,6 @@ typedef enum logic [1:0] {
 `define DCACHE_REPLACE_WIDTH $clog2(`DCACHE_REPLACE_SIZE)
 `define DCACHE_SNOOP_SIZE 4
 `define DCACHE_SNOOP_WIDTH $clog2(`DCACHE_SNOOP_SIZE)
-`define DCACHE_SNOOP_ID_WIDTH `CORE_WIDTH + 2
 
 // exccode
 `define EXC_WIDTH 5
@@ -378,4 +380,17 @@ typedef enum logic [1:0] {
     SC,
     SD
 } CoherentState;
+
+// l2 cache
+`define L2MSHR_SIZE 4
+`define L2MSHR_WIDTH $clog2(`L2MSHR_SIZE)
+`define L2CACHE_BANK 16
+`define L2DATA_BANK 1
+`define L2WAY_NUM 8
+`define L2SET 64
+`define L2OFFSET `CACHELINE_SIZE
+`define L2SLAVE_SET 64
+`define L2SLAVE_WAY 8
+`define L2PREPEND_PIPE 1
+`define L2APPEND_PIPE 1
 `endif
diff --git a/src/defines/interfaces.svh b/src/defines/interfaces.svh
index 469b5c3..4d834ac 100644
--- a/src/defines/interfaces.svh
+++ b/src/defines/interfaces.svh
@@ -842,6 +842,101 @@ interface RobFCsrIO;
     modport rob(input valid, output we, flag_we, flags);
 endinterface
 
+interface L2MSHRSlaveIO #(
+    parameter SLAVE = 1,
+    parameter LLC = 1,
+    parameter WAY = 4,
+    parameter SET = 64,
+    parameter OFFSET = 32,
+    parameter OFFSET_WIDTH = $clog2(OFFSET),
+    parameter SLAVE_WIDTH = idxWidth(SLAVE),
+    parameter SET_WIDTH = $clog2(SET),
+    parameter WAY_WIDTH = $clog2(WAY),
+    parameter TAG_WIDTH = `PADDR_SIZE - OFFSET_WIDTH - SET_WIDTH,
+    parameter ENTRY_SIZE = TAG_WIDTH + 1 + (LLC ? 0 : 1) + SLAVE + SLAVE_WIDTH
+);
+    logic request;
+    logic `N(`PADDR_SIZE) raddr;
+    logic hit;
+    logic `N(WAY_WIDTH) hit_way;
+    logic share;
+    logic owned;
+    logic `N(SLAVE) slave;
+    logic `N(SLAVE_WIDTH) owner;
+    logic replace_hit;
+    logic `N(WAY_WIDTH) replace_way;
+    logic replace_owned;
+
+    logic we;
+    logic wready;
+    logic `N(`PADDR_SIZE) waddr;
+    logic `N(WAY_WIDTH) wway;
+    logic `N(ENTRY_SIZE) wdata;
+
+    modport mshr (output request, raddr, we, waddr, wway, wdata, input hit, hit_way, share, owned, slave, owner, replace_hit, replace_way, replace_owned, wready);
+    modport slaver (input request, raddr, we, waddr, wway, wdata, output hit, hit_way, share, owned, slave, owner, replace_hit, replace_way, replace_owned, wready);
+endinterface
+
+interface L2MSHRDirIO #(
+    parameter WAY = 4,
+    parameter OFFSET = 32,
+    parameter SET = 64,
+    parameter WAY_WIDTH = $clog2(WAY),
+    parameter OFFSET_WIDTH = $clog2(OFFSET),
+    parameter SET_WIDTH = $clog2(SET),
+    parameter TAG_WIDTH = `PADDR_SIZE - OFFSET_WIDTH - SET_WIDTH
+);
+    logic request;
+    logic `N(`PADDR_SIZE) raddr;
+    logic hit;
+    DirectoryState hit_state;
+    logic `N(WAY_WIDTH) hit_way;
+    logic `N(TAG_WIDTH+1) replace_tagv;
+    logic `N(WAY_WIDTH) replace_way;
+    DirectoryState replace_state;
+
+    logic we;
+    logic wready;
+    logic `N(`PADDR_SIZE) waddr;
+    logic `N(WAY_WIDTH) wway;
+    logic `N(TAG_WIDTH+1+$bits(DirectoryState)) wdata;
+
+    modport mshr (output request, raddr, we, waddr, wway, wdata, input hit, hit_way, hit_state, replace_tagv, replace_way, replace_state, wready);
+    modport dir (input request, raddr, we, waddr, wway, wdata, output hit, hit_way, hit_state, replace_tagv, replace_way, replace_state, wready);
+endinterface
+
+interface L2MSHRDataIO #(
+    parameter MSHR_SIZE = 4,
+    parameter DATA_BANK = 1,
+    parameter SET_SIZE = 64,
+    parameter WAY_NUM = 4,
+    parameter WAY_WIDTH = $clog2(WAY_NUM),
+    parameter MSHR_WIDTH = $clog2(MSHR_SIZE),
+    parameter SET_WIDTH = $clog2(SET_SIZE / DATA_BANK)
+);
+    logic `N(DATA_BANK) req;
+    logic `ARRAY(DATA_BANK, WAY_WIDTH) rway;
+    logic `N(DATA_BANK) ready;
+    logic `ARRAY(DATA_BANK, MSHR_WIDTH) mshr_idx;
+    logic `ARRAY(DATA_BANK, SET_WIDTH) raddr;
+    logic `N(DATA_BANK) rvalid;
+    logic `ARRAY(DATA_BANK, MSHR_WIDTH) mshr_idx_o;
+    logic `TENSOR(DATA_BANK, `DCACHE_BANK, `DCACHE_BITS) rdata;
+
+    logic `N(DATA_BANK) we;
+    logic `ARRAY(DATA_BANK, WAY_WIDTH) wway;
+    logic `ARRAY(DATA_BANK, MSHR_WIDTH) wmshr_idx;
+    logic `ARRAY(DATA_BANK, SET_WIDTH) waddr;
+    logic `N(DATA_BANK) wvalid;
+    logic `ARRAY(DATA_BANK, MSHR_WIDTH) wmshr_idx_o;
+    logic `TENSOR(DATA_BANK, `DCACHE_BANK, `DCACHE_BITS) wdata;
+
+    modport mshr(output req, rway, mshr_idx, raddr, input ready, rvalid, mshr_idx_o, rdata,
+                output we, wway, wmshr_idx, waddr, wdata, input wvalid, wmshr_idx_o);
+    modport data(input req, rway, mshr_idx, raddr, output ready, rvalid, mshr_idx_o, rdata,
+                input we, wway, wmshr_idx, waddr, wdata, output wvalid, wmshr_idx_o);
+endinterface
+
 `ifdef DIFFTEST
 interface DiffRAT;
     logic `ARRAY(32, `PREG_WIDTH) map_reg;
diff --git a/src/sim/SimTop.sv b/src/sim/SimTop.sv
index e2a36a3..7d0445e 100644
--- a/src/sim/SimTop.sv
+++ b/src/sim/SimTop.sv
@@ -70,16 +70,16 @@ module SimTop(
     end
 
     AxiIO #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH+2, 1
+        `PADDR_SIZE, `XLEN, 2, 1
     ) mem_axi();
     AxiIO #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH+2, 1
+        `PADDR_SIZE, `XLEN, 2, 1
     ) core_axi();
     AxiIO #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH+2, 1
+        `PADDR_SIZE, `XLEN, 2, 1
     ) peri_axi();
     AxiIO #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH+2, 1
+        `PADDR_SIZE, `XLEN, 2, 1
     ) irq_axi();
 
     ClintIO clint_io();
@@ -105,7 +105,7 @@ module SimTop(
         FallThrough: 0,
         LatencyMode: 10'b11111_11111,
         PipelineStages: 1,
-        AxiIdWidthSlvPorts: `CORE_WIDTH+2,
+        AxiIdWidthSlvPorts: 2,
         UniqueIds: 1,
         AxiAddrWidth: `PADDR_SIZE,
         AxiDataWidth: `XLEN,
@@ -114,7 +114,7 @@ module SimTop(
     };
     typedef logic [`PADDR_SIZE-1: 0] addr_t;
     typedef logic user_t;
-    typedef logic [`CORE_WIDTH+2-1: 0] id_t;
+    typedef logic [1: 0] id_t;
     typedef logic [`XLEN-1: 0] data_t;
     typedef logic [`XLEN/8-1: 0] strb_t;
     `AXI_TYPEDEF_AW_CHAN_T(AxiAW, addr_t, id_t, user_t)
@@ -216,7 +216,7 @@ module SimTop(
         .NoRules(2),
         .AxiAddrWidth(`PADDR_SIZE),
         .AxiDataWidth(`XLEN),
-        .AxiIdWidth(`CORE_WIDTH+2),
+        .AxiIdWidth(2),
         .AxiUserWidth(1),
         .PipelineRequest(1),
         .PipelineResponse(1),
@@ -285,7 +285,7 @@ module SimTop(
         .NoRules(`PERIPHERAL_SIZE),
         .AxiAddrWidth(`PADDR_SIZE),
         .AxiDataWidth(`XLEN),
-        .AxiIdWidth(`CORE_WIDTH+2),
+        .AxiIdWidth(2),
         .AxiUserWidth(1),
         .PipelineRequest(1),
         .PipelineResponse(1),
diff --git a/src/soc/Soc.sv b/src/soc/Soc.sv
index 289a8f0..f9f06fa 100644
--- a/src/soc/Soc.sv
+++ b/src/soc/Soc.sv
@@ -10,13 +10,13 @@ module Soc(
     output logic txd
 );
     AxiIO #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH+2, 1
+        `PADDR_SIZE, `XLEN, 2, 1
     ) core_axi();
     AxiIO #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH+2, 1
+        `PADDR_SIZE, `XLEN, 2, 1
     ) peri_axi();
     AxiIO #(
-        `PADDR_SIZE, `XLEN, `CORE_WIDTH+2, 1
+        `PADDR_SIZE, `XLEN, 2, 1
     ) irq_axi();
 
     ClintIO clint_io();
@@ -56,7 +56,7 @@ module Soc(
         FallThrough: 0,
         LatencyMode: 10'b11111_11111,
         PipelineStages: 1,
-        AxiIdWidthSlvPorts: `CORE_WIDTH+2,
+        AxiIdWidthSlvPorts: 2,
         UniqueIds: 1,
         AxiAddrWidth: `PADDR_SIZE,
         AxiDataWidth: `XLEN,
@@ -65,7 +65,7 @@ module Soc(
     };
     typedef logic [`PADDR_SIZE-1: 0] addr_t;
     typedef logic user_t;
-    typedef logic [`CORE_WIDTH+2-1: 0] id_t;
+    typedef logic [1: 0] id_t;
     typedef logic [`XLEN-1: 0] data_t;
     typedef logic [`XLEN/8-1: 0] strb_t;
     `AXI_TYPEDEF_AW_CHAN_T(AxiAW, addr_t, id_t, user_t)
@@ -160,7 +160,7 @@ module Soc(
         .NoRules(2),
         .AxiAddrWidth(`PADDR_SIZE),
         .AxiDataWidth(`XLEN),
-        .AxiIdWidth(`CORE_WIDTH+2),
+        .AxiIdWidth(2),
         .AxiUserWidth(1),
         .PipelineRequest(1),
         .PipelineResponse(1),
@@ -232,7 +232,7 @@ module Soc(
         .AxiDataWidth(`XLEN),
         .PipelineRequest(1),
         .PipelineResponse(1),
-        .AxiIdWidth(`CORE_WIDTH+2),
+        .AxiIdWidth(2),
         .AxiUserWidth(1),
         .AxiMaxWriteTxns((`NUM_CORE < 2 ? 2 : `NUM_CORE)),
         .AxiMaxReadTxns((`NUM_CORE < 2 ? 2 : `NUM_CORE)),
diff --git a/src/utils/axi/axi_convert/ace_ccu_top.sv b/src/utils/axi/axi_convert/ace_ccu_top.sv
deleted file mode 100644
index ef1be4d..0000000
--- a/src/utils/axi/axi_convert/ace_ccu_top.sv
+++ /dev/null
@@ -1,241 +0,0 @@
-// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
-// Copyright (c) 2023 PlanV GmbH
-//
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License.  You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-
-// ace_ccu_top: Top level module for closely coupled cache coherency protocol
-`include "../../../defines/defines.svh"
-
-
-module ace_ccu_top
-#(
-    parameter ccu_cfg_t Cfg               = '0,
-    parameter bit                ATOPs             = 1'b1,
-    parameter type               slv_aw_chan_t     = logic,
-    parameter type               mst_aw_chan_t     = logic,
-    parameter type               mst_stg_aw_chan_t = logic,
-    parameter type               w_chan_t          = logic,
-    parameter type               slv_b_chan_t      = logic,
-    parameter type               mst_b_chan_t      = logic,
-    parameter type               mst_stg_b_chan_t  = logic,
-    parameter type               slv_ar_chan_t     = logic,
-    parameter type               mst_ar_chan_t     = logic,
-    parameter type               mst_stg_ar_chan_t = logic,
-    parameter type               slv_r_chan_t      = logic,
-    parameter type               mst_r_chan_t      = logic,
-    parameter type               mst_stg_r_chan_t  = logic,
-    parameter type               slv_req_t         = logic,
-    parameter type               slv_resp_t        = logic,
-    parameter type               mst_req_t         = logic,
-    parameter type               mst_resp_t        = logic,
-    parameter type               mst_stg_req_t     = logic,
-    parameter type               mst_stg_resp_t    = logic,
-    parameter type               snoop_req_t       = logic,
-    parameter type               snoop_resp_t      = logic
-
-) (
-    input  logic                             clk_i,
-    input  logic                             rst_ni,
-    input  logic                             test_i,
-    input  slv_req_t    [Cfg.NoSlvPorts-1:0] slv_ports_req_i,
-    output slv_resp_t   [Cfg.NoSlvPorts-1:0] slv_ports_resp_o,
-    output snoop_req_t  [Cfg.NoSlvPorts-1:0] slv_snp_req_o,
-    input  snoop_resp_t [Cfg.NoSlvPorts-1:0] slv_snp_resp_i,
-    output mst_req_t                         mst_ports_req_o,
-    input  mst_resp_t                        mst_ports_resp_i
-);
-
-    // signals from the ace_demuxes
-    slv_req_t  [Cfg.NoSlvPorts-1:0] [1:0]      slv_reqs;   // one for non-shareable and one for shareable req
-    slv_resp_t [Cfg.NoSlvPorts-1:0][1:0] slv_resps;
-    // signals into the ace_muxes
-    mst_stg_req_t [Cfg.NoSlvPorts:0] mst_reqs;  // one extra port for CCU
-    mst_stg_resp_t [Cfg.NoSlvPorts:0] mst_resps;
-    mst_stg_req_t [Cfg.NoSlvPorts:0] mst_reqs_tmp;
-    // signals into the CCU
-    slv_req_t [Cfg.NoSlvPorts-1:0] ccu_reqs_i;
-    slv_resp_t [Cfg.NoSlvPorts-1:0] ccu_resps_o;
-    // signals from the CCU
-    mst_stg_req_t ccu_reqs_mux_o;
-    mst_stg_resp_t ccu_resps_mux_i;
-    mst_stg_req_t ccu_reqs_o;
-    mst_stg_resp_t ccu_resps_i;
-
-    // selection lines for mux and demuxes
-    logic [Cfg.NoSlvPorts-1:0] slv_aw_select, slv_ar_select;
-
-
-    for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux
-
-        // routing of incoming request through transaction type
-        ace_trs_dec #(
-            .slv_ace_req_t(slv_req_t)
-        ) i_ace_trs_dec (
-            .slv_reqs_i  (slv_ports_req_i[i]),
-            .snoop_aw_trs(slv_aw_select[i]),
-            .snoop_ar_trs(slv_ar_select[i])
-        );
-
-        // demux
-        axi_demux #(
-            .AxiIdWidth (Cfg.AxiIdWidthSlvPorts),  // ID Width
-            .AtopSupport(ATOPs),
-            .aw_chan_t  (slv_aw_chan_t),           // AW Channel Type
-            .w_chan_t   (w_chan_t),                //  W Channel Type
-            .b_chan_t   (slv_b_chan_t),            //  B Channel Type
-            .ar_chan_t  (slv_ar_chan_t),           // AR Channel Type
-            .r_chan_t   (slv_r_chan_t),            //  R Channel Type
-            .axi_req_t  (slv_req_t),
-            .axi_resp_t (slv_resp_t),
-            .NoMstPorts (2),                       // one for CCU module and one for mux
-            .MaxTrans   (Cfg.MaxMstTrans),
-            .AxiLookBits(Cfg.AxiIdUsedSlvPorts),
-            .UniqueIds  (Cfg.UniqueIds),
-            //.FallThrough    ( Cfg.FallThrough        ),
-            .SpillAw    (Cfg.LatencyMode[9]),
-            .SpillW     (Cfg.LatencyMode[8]),
-            .SpillB     (Cfg.LatencyMode[7]),
-            .SpillAr    (Cfg.LatencyMode[6]),
-            .SpillR     (Cfg.LatencyMode[5])
-        ) i_axi_demux (
-            .clk_i,  // Clock
-            .rst_ni,  // Asynchronous reset active low
-            .test_i,  // Testmode enable
-            .slv_req_i      (slv_ports_req_i[i]),
-            .slv_aw_select_i(slv_aw_select[i]),
-            .slv_ar_select_i(slv_ar_select[i]),
-            .slv_resp_o     (slv_ports_resp_o[i]),
-            .mst_reqs_o     (slv_reqs[i]),
-            .mst_resps_i    (slv_resps[i])
-        );
-    end
-
-    axi_mux #(
-        .SlvAxiIDWidth(Cfg.AxiIdWidthSlvPorts + $clog2(
-            Cfg.NoSlvPorts
-        )),  // ID width of the slave ports
-        .slv_aw_chan_t(mst_stg_aw_chan_t),  // AW Channel Type, slave ports
-        .mst_aw_chan_t(mst_aw_chan_t),  // AW Channel Type, master port
-        .w_chan_t(w_chan_t),  //  W Channel Type, all ports
-        .slv_b_chan_t(mst_stg_b_chan_t),  //  B Channel Type, slave ports
-        .mst_b_chan_t(mst_b_chan_t),  //  B Channel Type, master port
-        .slv_ar_chan_t(mst_stg_ar_chan_t),  // AR Channel Type, slave ports
-        .mst_ar_chan_t(mst_ar_chan_t),  // AR Channel Type, master port
-        .slv_r_chan_t(mst_stg_r_chan_t),  //  R Channel Type, slave ports
-        .mst_r_chan_t(mst_r_chan_t),  //  R Channel Type, master port
-        .slv_req_t(mst_stg_req_t),
-        .slv_resp_t(mst_stg_resp_t),
-        .mst_req_t(mst_req_t),
-        .mst_resp_t(mst_resp_t),
-        .NoSlvPorts(Cfg.NoSlvPorts + 1),  // Number of Masters for the modules
-        .MaxWTrans(Cfg.MaxMstTrans),
-        .FallThrough(Cfg.FallThrough),
-        .SpillAw(Cfg.LatencyMode[4]),
-        .SpillW(Cfg.LatencyMode[3]),
-        .SpillB(Cfg.LatencyMode[2]),
-        .SpillAr(Cfg.LatencyMode[1]),
-        .SpillR(Cfg.LatencyMode[0])
-    ) i_axi_mux (
-        .clk_i,  // Clock
-        .rst_ni,  // Asynchronous reset active low
-        .test_i,  // Test Mode enable
-        .slv_reqs_i (mst_reqs),
-        .slv_resps_o(mst_resps),
-        .mst_req_o  (mst_ports_req_o),
-        .mst_resp_i (mst_ports_resp_i)
-    );
-
-
-    // connection reqs and resps for non-shareable transactions with axi_mux
-    for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_non_shared_conn
-        `ACE_ASSIGN_REQ_STRUCT(mst_reqs_tmp[i], slv_reqs[i][0])
-        `ACE_ASSIGN_RESP_STRUCT(slv_resps[i][0], mst_resps[i])
-
-        always_comb begin
-            mst_reqs[i] = mst_reqs_tmp[i];
-            mst_reqs[i].aw.user[$clog2(Cfg.NoSlvPorts)-1:0] = i[$clog2(Cfg.NoSlvPorts)-1:0];
-            mst_reqs[i].ar.user[$clog2(Cfg.NoSlvPorts)-1:0] = i[$clog2(Cfg.NoSlvPorts)-1:0];
-
-        end
-    end
-
-    // connect CCU reqs and resps to mux
-    always_comb begin
-        mst_reqs[Cfg.NoSlvPorts] = mst_reqs_tmp[Cfg.NoSlvPorts];
-        mst_reqs[Cfg.NoSlvPorts].aw.user[$clog2(Cfg.NoSlvPorts)-1:0] =
-            mst_reqs_tmp[Cfg.NoSlvPorts].aw.id[Cfg.AxiIdWidthSlvPorts+:$clog2(Cfg.NoSlvPorts)];
-        mst_reqs[Cfg.NoSlvPorts].ar.user[$clog2(Cfg.NoSlvPorts)-1:0] =
-            mst_reqs_tmp[Cfg.NoSlvPorts].ar.id[Cfg.AxiIdWidthSlvPorts+:$clog2(Cfg.NoSlvPorts)];
-    end
-    `ACE_ASSIGN_REQ_STRUCT(mst_reqs_tmp[Cfg.NoSlvPorts], ccu_reqs_o)
-    `ACE_ASSIGN_RESP_STRUCT(ccu_resps_i, mst_resps[Cfg.NoSlvPorts])
-
-    // connection reqs and resps for shareable transactions with CCU
-    for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_shared_conn
-        `ACE_ASSIGN_REQ_STRUCT(ccu_reqs_i[i], slv_reqs[i][1])
-        `ACE_ASSIGN_RESP_STRUCT(slv_resps[i][1], ccu_resps_o[i])
-    end
-
-
-    axi_mux #(
-        .SlvAxiIDWidth(Cfg.AxiIdWidthSlvPorts),  // ID width of the slave ports
-        .slv_aw_chan_t(slv_aw_chan_t),           // AW Channel Type, slave ports
-        .mst_aw_chan_t(mst_stg_aw_chan_t),       // AW Channel Type, master port
-        .w_chan_t     (w_chan_t),                //  W Channel Type, all ports
-        .slv_b_chan_t (slv_b_chan_t),            //  B Channel Type, slave ports
-        .mst_b_chan_t (mst_stg_b_chan_t),        //  B Channel Type, master port
-        .slv_ar_chan_t(slv_ar_chan_t),           // AR Channel Type, slave ports
-        .mst_ar_chan_t(mst_stg_ar_chan_t),       // AR Channel Type, master port
-        .slv_r_chan_t (slv_r_chan_t),            //  R Channel Type, slave ports
-        .mst_r_chan_t (mst_stg_r_chan_t),        //  R Channel Type, master port
-        .slv_req_t    (slv_req_t),
-        .slv_resp_t   (slv_resp_t),
-        .mst_req_t    (mst_stg_req_t),
-        .mst_resp_t   (mst_stg_resp_t),
-        .NoSlvPorts   (Cfg.NoSlvPorts),          // Number of Masters for the modules
-        .MaxWTrans    (Cfg.MaxMstTrans),
-        .FallThrough  (Cfg.FallThrough),
-        .SpillAw      (Cfg.LatencyMode[4]),
-        .SpillW       (Cfg.LatencyMode[3]),
-        .SpillB       (Cfg.LatencyMode[2]),
-        .SpillAr      (Cfg.LatencyMode[1]),
-        .SpillR       (Cfg.LatencyMode[0])
-    ) i_ace_mux (
-        .clk_i,  // Clock
-        .rst_ni,  // Asynchronous reset active low
-        .test_i,  // Test Mode enable
-        .slv_reqs_i (ccu_reqs_i),
-        .slv_resps_o(ccu_resps_o),
-        .mst_req_o  (ccu_reqs_mux_o),
-        .mst_resp_i (ccu_resps_mux_i)
-    );
-
-    ccu_fsm #(
-        .DcacheLineWidth(Cfg.DcacheLineWidth),
-        .AxiDataWidth   (Cfg.AxiDataWidth),
-        .NoMstPorts     (Cfg.NoSlvPorts),
-        .SlvAxiIDWidth  (Cfg.AxiIdWidthSlvPorts),  // ID width of the slave ports
-        .mst_req_t      (mst_stg_req_t),
-        .mst_resp_t     (mst_stg_resp_t),
-        .snoop_req_t    (snoop_req_t),
-        .snoop_resp_t   (snoop_resp_t)
-
-    ) fsm (
-        .clk_i,
-        .rst_ni,
-        .ccu_req_i (ccu_reqs_mux_o),
-        .ccu_resp_o(ccu_resps_mux_i),
-        .ccu_req_o (ccu_reqs_o),
-        .ccu_resp_i(ccu_resps_i),
-        .s2m_req_o (slv_snp_req_o),
-        .m2s_resp_i(slv_snp_resp_i)
-    );
-
-endmodule
diff --git a/src/utils/utils.sv b/src/utils/utils.sv
index 2b3409d..7339aaa 100644
--- a/src/utils/utils.sv
+++ b/src/utils/utils.sv
@@ -34,22 +34,40 @@ module Encoder #(
 	input logic [RADIX-1: 0] in,
 	output logic [WIDTH-1: 0] out
 );
-	generate;
-		case(RADIX)
-		2: Encoder2 encoder(in, out);
-		4: Encoder4 encoder(in, out);
-		8: Encoder8 encoder(in, out);
-		16: Encoder16 encoder(in, out);
-		32: Encoder32 encoder(in, out);
-		64: Encoder64 encoder(in, out);
-		default: begin
-			Encoder2 encoder(in, out);
-			always_comb begin
-				$display("unimpl Encoder");
-			end
+generate
+	for(genvar i=0; i<WIDTH; i++)begin
+		localparam STEP = 2 << i;
+		localparam STEP_NUM = 1 << i;
+		localparam FULL_STEP_NUM = RADIX / STEP;
+		localparam REMAIN = RADIX % STEP;
+		localparam REMAIN_NUM = REMAIN < STEP_NUM ? 0 : STEP_NUM - REMAIN;
+		localparam ALL_NUM = FULL_STEP_NUM * STEP_NUM + REMAIN_NUM;
+		logic [ALL_NUM-1: 0] out_t;
+		for(genvar j=0; j<FULL_STEP_NUM; j++)begin
+			assign out_t[j*STEP_NUM +: STEP_NUM] = in[j*STEP+STEP_NUM +: STEP_NUM];
 		end
-		endcase
-	endgenerate
+		for(genvar j=0; j<REMAIN_NUM; j++)begin
+			assign out_t[ALL_NUM-1-j] = in[RADIX-1-j];
+		end
+		assign out[i] = |out_t;
+	end
+endgenerate
+	// generate;
+	// 	case(RADIX)
+	// 	2: Encoder2 encoder(in, out);
+	// 	4: Encoder4 encoder(in, out);
+	// 	8: Encoder8 encoder(in, out);
+	// 	16: Encoder16 encoder(in, out);
+	// 	32: Encoder32 encoder(in, out);
+	// 	64: Encoder64 encoder(in, out);
+	// 	default: begin
+	// 		Encoder2 encoder(in, out);
+	// 		always_comb begin
+	// 			$display("unimpl Encoder");
+	// 		end
+	// 	end
+	// 	endcase
+	// endgenerate
 endmodule
 
 module PEncoder #(

From 29e9e25fd01a7f94216cc88c4bb0e4b71b41c9cd Mon Sep 17 00:00:00 2001
From: xinhecuican <lizilin2686462757@gmail.com>
Date: Tue, 4 Feb 2025 11:00:46 +0800
Subject: [PATCH 3/3] fix(l2cache): fix some bugs

- add snoop pipline, add w, b, r pipe
- fix l2 refill buffer data select
- fix l2 data write before replace
- add CLEAN_UNIQUE when cache write and state is share and owned
- fix slave dir write bugs
---
 Makefile                                      |   2 +-
 src/core/CPUCore.sv                           |   6 +-
 src/core/backend/lsu/dcache/DCacheMiss.sv     |  71 ++++--
 src/core/backend/lsu/dcache/DCacheWay.sv      |  21 +-
 src/core/backend/lsu/dcache/ReplaceQueue.sv   |  61 +++--
 src/core/backend/lsu/dcache/dcache.sv         |  32 +--
 src/core/frontend/icache/Icache.sv            |   2 +-
 src/core/mem/cache/Directory.sv               |  10 +-
 src/core/mem/cache/L2CacheWrapper.sv          |  42 +++-
 src/core/mem/cache/L2MSHR.sv                  | 234 +++++++++++-------
 src/defines/bus/ace.svh                       |   9 +-
 src/defines/bus/mem.svh                       |   7 +-
 src/defines/debug.svh                         |   4 +-
 src/defines/interfaces.svh                    |   4 +-
 src/sim/SimTop.sv                             |  70 ++++--
 src/soc/Soc.sv                                |  26 +-
 src/utils/axi/{axi_convert => }/LICENSE       |   0
 .../axi/{axi_convert => }/ace_trs_dec.sv      |   0
 .../axi/{axi_convert => }/addr_decode.sv      |   0
 .../axi/{axi_convert => }/addr_decode_dync.sv |   0
 .../axi/{axi_convert => }/axi_atop_filter.sv  |   0
 .../{axi_convert => }/axi_burst_splitter.sv   |   0
 src/utils/axi/{axi_convert => }/axi_cdc.sv    |   0
 .../axi/{axi_convert => }/axi_cdc_dst.sv      |   0
 .../axi/{axi_convert => }/axi_cdc_src.sv      |   0
 src/utils/axi/{axi_convert => }/axi_cut.sv    |   0
 src/utils/axi/{axi_convert => }/axi_demux.sv  |   0
 .../axi/{axi_convert => }/axi_demux_simple.sv |   0
 .../axi/{axi_convert => }/axi_err_slv.sv      |   0
 .../axi/{axi_convert => }/axi_id_prepend.sv   |   0
 .../axi/{axi_convert => }/axi_lite_to_apb.sv  |   0
 .../axi/{axi_convert => }/axi_multicut.sv     |   0
 src/utils/axi/{axi_convert => }/axi_mux.sv    |   0
 src/utils/axi/{axi_convert => }/axi_to_apb.sv |   0
 .../axi/{axi_convert => }/axi_to_axi_lite.sv  |   0
 src/utils/axi/{axi_convert => }/axi_xbar.sv   |   0
 .../axi/{axi_convert => }/axi_xbar_unmuxed.sv |   0
 .../axi/{axi_convert => }/binary_to_gray.sv   |   0
 src/utils/axi/{axi_convert => }/ccu_fsm.sv    |   0
 .../axi/{axi_convert => }/cdc_fifo_gray.sv    |   0
 src/utils/axi/{axi_convert => }/counter.sv    |   0
 .../axi/{axi_convert => }/delta_counter.sv    |   0
 .../fall_through_register.sv                  |   0
 src/utils/axi/{axi_convert => }/fifo_v3.sv    |   0
 .../axi/{axi_convert => }/gray_to_binary.sv   |   0
 src/utils/axi/{axi_convert => }/id_queue.sv   |   0
 .../axi/{axi_convert => }/onehot_to_bin.sv    |   0
 .../axi/{axi_convert => }/rr_arb_tree.sv      |   0
 src/utils/axi/snoop_cut.sv                    | 144 +++++++++++
 .../axi/{axi_convert => }/spill_register.sv   |   0
 .../spill_register_flushable.sv               |   0
 .../axi/{axi_convert => }/stream_register.sv  |   0
 src/utils/axi/{axi_convert => }/sync.sv       |   0
 src/utils/utils.sv                            |  23 +-
 54 files changed, 546 insertions(+), 222 deletions(-)
 rename src/utils/axi/{axi_convert => }/LICENSE (100%)
 rename src/utils/axi/{axi_convert => }/ace_trs_dec.sv (100%)
 rename src/utils/axi/{axi_convert => }/addr_decode.sv (100%)
 rename src/utils/axi/{axi_convert => }/addr_decode_dync.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_atop_filter.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_burst_splitter.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_cdc.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_cdc_dst.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_cdc_src.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_cut.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_demux.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_demux_simple.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_err_slv.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_id_prepend.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_lite_to_apb.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_multicut.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_mux.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_to_apb.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_to_axi_lite.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_xbar.sv (100%)
 rename src/utils/axi/{axi_convert => }/axi_xbar_unmuxed.sv (100%)
 rename src/utils/axi/{axi_convert => }/binary_to_gray.sv (100%)
 rename src/utils/axi/{axi_convert => }/ccu_fsm.sv (100%)
 rename src/utils/axi/{axi_convert => }/cdc_fifo_gray.sv (100%)
 rename src/utils/axi/{axi_convert => }/counter.sv (100%)
 rename src/utils/axi/{axi_convert => }/delta_counter.sv (100%)
 rename src/utils/axi/{axi_convert => }/fall_through_register.sv (100%)
 rename src/utils/axi/{axi_convert => }/fifo_v3.sv (100%)
 rename src/utils/axi/{axi_convert => }/gray_to_binary.sv (100%)
 rename src/utils/axi/{axi_convert => }/id_queue.sv (100%)
 rename src/utils/axi/{axi_convert => }/onehot_to_bin.sv (100%)
 rename src/utils/axi/{axi_convert => }/rr_arb_tree.sv (100%)
 create mode 100644 src/utils/axi/snoop_cut.sv
 rename src/utils/axi/{axi_convert => }/spill_register.sv (100%)
 rename src/utils/axi/{axi_convert => }/spill_register_flushable.sv (100%)
 rename src/utils/axi/{axi_convert => }/stream_register.sv (100%)
 rename src/utils/axi/{axi_convert => }/sync.sv (100%)

diff --git a/Makefile b/Makefile
index 55de446..4916622 100644
--- a/Makefile
+++ b/Makefile
@@ -73,7 +73,7 @@ emu:
 
 emu-run: emu
 	mkdir -p $(LOG_PATH)
-	riscv64-unknown-linux-gnu-gdb --args build/emu -i "${I}" -s 1168 -b ${S} -e ${E} -B $(WB) -E $(WE) ${TRACE_ARGS} --log-path=${LOG_PATH}
+	build/emu -i "${I}" -s 1168 -b ${S} -e ${E} -B $(WB) -E $(WE) ${TRACE_ARGS} --log-path=${LOG_PATH}
 
 sbi:
 	make -C utils/opensbi ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- PLATFORM_RISCV_XLEN=32 PLATFORM=generic FW_PAYLOAD_PATH=${CURDIR}/utils/rv-linux/arch/riscv/boot/Image FW_FDT_PATH=${CURDIR}/utils/opensbi/dts/custom.dtb FW_PAYLOAD_OFFSET=0x400000
diff --git a/src/core/CPUCore.sv b/src/core/CPUCore.sv
index b485ca4..648b881 100644
--- a/src/core/CPUCore.sv
+++ b/src/core/CPUCore.sv
@@ -4,7 +4,8 @@
 module CPUCore (
     input logic clk,
     input logic rst,
-    AxiIO.master axi,
+    AxiIO.master  mem_axi,
+    AxiIO.master peri_axi,
     ClintIO.cpu clint_io
 );
 
@@ -42,7 +43,8 @@ module CPUCore (
     mst_snoop_resp_t mst_snoop_resp;
     `SNOOP_ASSIGN_FROM_REQ(dcache_snoop_io, snoop_req)
     `SNOOP_ASSIGN_TO_RESP(snoop_resp, dcache_snoop_io)
-    `CACHE_ASSIGN_TO_AXI(axi, master_io)
+    `CACHE_ASSIGN_TO_AXI(mem_axi, master_io)
+    `CACHE_ASSIGN_TO_AXI(peri_axi, ducache_io)
     assign mst_snoop_req = 0;
 
     IfuBackendIO ifu_backend_io();
diff --git a/src/core/backend/lsu/dcache/DCacheMiss.sv b/src/core/backend/lsu/dcache/DCacheMiss.sv
index cb69044..c9a7c61 100644
--- a/src/core/backend/lsu/dcache/DCacheMiss.sv
+++ b/src/core/backend/lsu/dcache/DCacheMiss.sv
@@ -16,6 +16,9 @@ interface DCacheMissIO;
     logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) wdata;
     logic `ARRAY(`DCACHE_BANK, `DCACHE_BYTE) wmask;
     logic wfull;
+    logic wowned;
+    logic replaceHit;
+    logic `N(`DCACHE_WAY_WIDTH) replaceHitWay;
 
 `ifdef RVA
     logic amo_en;
@@ -26,13 +29,17 @@ interface DCacheMissIO;
     logic `N(`PADDR_SIZE) req_addr;
     logic req_success;
     logic `N(`DCACHE_WAY_WIDTH) replaceWay;
+    logic `N(`L2MSHR_WIDTH) l2_idx;
 
     logic refill_en;
     logic refill_valid;
-    logic refill_dirty;
+    logic refill_write;
+    logic refill_replace_hit;
     logic `N(`DCACHE_WAY_WIDTH) refillWay;
     logic `N(`PADDR_SIZE) refillAddr;
+    logic `ARRAY(`DCACHE_BANK, `DCACHE_BYTE) refillMask;
     logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) refillData;
+    logic `N(`L2MSHR_WIDTH) refill_l2idx;
     logic `N(`STORE_COMMIT_WIDTH) refill_scIdx;
     DirectoryState refill_state;
 
@@ -40,13 +47,13 @@ interface DCacheMissIO;
     logic `ARRAY(`LOAD_REFILL_SIZE, `DCACHE_BITS) lqData;
     logic `ARRAY(`LOAD_REFILL_SIZE, `LOAD_QUEUE_WIDTH) lqIdx_o;
 
-    modport miss (input ren, raddr, lqIdx, robIdx, req_success, replaceWay, refill_valid,
-                        wen, waddr, scIdx, wdata, wmask, raddr_pre, waddr_pre, wdata_valid,
+    modport miss (input ren, raddr, lqIdx, robIdx, req_success, replaceHit, replaceHitWay, replaceWay, refill_valid, l2_idx,
+                wen, waddr, scIdx, wdata, wmask, raddr_pre, waddr_pre, wdata_valid, wowned,
 `ifdef RVA
                   input amo_en, output amo_refill,
 `endif
-                  output rfull, req, req_addr, wfull, lq_en, lqData, lqIdx_o,
-        refill_en, refill_dirty, refillWay, refillAddr, refillData, refill_scIdx, refill_state);
+                  output rfull, req, req_addr, wfull, lq_en, lqData, lqIdx_o, refill_l2idx,
+        refill_en, refill_write, refill_replace_hit, refillWay, refillAddr, refillMask, refillData, refill_scIdx, refill_state);
 endinterface
 
 module DCacheMiss(
@@ -73,6 +80,9 @@ module DCacheMiss(
     logic `ARRAY(`DCACHE_BANK, `DCACHE_BYTE) mask `N(`DCACHE_MISS_SIZE);
     logic `N(`DCACHE_MISS_SIZE) data_valid_all, wvalid;
     logic `N(`STORE_COMMIT_WIDTH) scIdxs `N(`DCACHE_MISS_SIZE);
+    logic `ARRAY(`DCACHE_MISS_SIZE, `L2MSHR_WIDTH) l2_idxs;
+    logic `N(`DCACHE_MISS_SIZE) replaceHit, wowned;
+    logic `ARRAY(`DCACHE_MISS_SIZE, `DCACHE_WAY_WIDTH) replaceHitWay;
 
     logic `N(`DCACHE_MISS_WIDTH) mshr_head, head, tail;
     logic `N(`DCACHE_MISS_WIDTH+1) remain_count;
@@ -99,6 +109,7 @@ module DCacheMiss(
     logic `N(`XLEN) combine_cache_data;
     logic `N(`DCACHE_WAY_WIDTH) req_way;
     DirectoryState req_state;
+    logic req_replace_hit, req_owned, req_owned_after;
 
 //load enqueue
     // 有三种情况
@@ -220,8 +231,12 @@ endgenerate
     assign io.refill_state = req_state;
     assign io.refillWay = way[head];
     assign io.refillAddr = {addr[head], {`DCACHE_BANK_WIDTH{1'b0}}, 2'b0};
+    assign io.refillMask = req_mask | {`DCACHE_BANK*`DCACHE_BYTE{~req_owned_after}};
     assign io.refillData = data[head];
     assign io.refill_scIdx = scIdxs[head];
+    assign io.refill_l2idx = l2_idxs[head];
+    assign io.refill_write = wvalid[head];
+    assign io.refill_replace_hit = req_replace_hit;
 
     Decoder #(`DCACHE_MISS_SIZE) decoder_head (head, head_decode);
     assign w_refill_eq = {`DCACHE_MISS_SIZE{data_refilled}} & whit & head_decode;
@@ -307,6 +322,9 @@ endgenerate
             data_refilled <= 0;
             data_valid_all <= 0;
             wvalid <= 0;
+            replaceHit <= 0;
+            replaceHitWay <= 0;
+            wowned <= 0;
         end
         else begin
             head <= head + (io.refill_en & io.refill_valid);
@@ -344,6 +362,9 @@ endgenerate
                 en[freeIdx[`LOAD_PIPELINE]] <= 1'b1;
                 addr[freeIdx[`LOAD_PIPELINE]] <= io.waddr`DCACHE_BLOCK_BUS;
                 dataValid[freeIdx[`LOAD_PIPELINE]] <= 1'b0;
+                replaceHit[freeIdx[`LOAD_PIPELINE]] <= io.replaceHit;
+                replaceHitWay[freeIdx[`LOAD_PIPELINE]] <= io.replaceHitWay;
+                wowned[freeIdx[`LOAD_PIPELINE]] <= io.wowned;
             end
             if(io.wen & ~w_invalid & (write_remain_valid | whit_combine))begin
                 scIdxs[widx] <= io.scIdx;
@@ -353,7 +374,7 @@ endgenerate
             if(rlast)begin
                 data_refilled <= 1'b1;
             end
-            if(req_last | r_axi_io.ar_valid & r_axi_io.ar_ready & req_valid_all)begin
+            if(req_last)begin
                 dataValid[head] <= 1'b1;
             end
             if(req_next & io.req_success)begin
@@ -365,6 +386,7 @@ endgenerate
                 data_refilled <= 1'b0;
                 data_valid_all[head] <= 1'b0;
                 wvalid[head] <= 1'b0;
+                replaceHit[head] <= 1'b0;
             end
             if(refilled[mshr_head] & ~(mshr_hit_valid))begin
                 refilled[mshr_head] <= 1'b0;
@@ -387,7 +409,7 @@ endgenerate
             if(io.refill_en & io.refill_valid)begin
                 amo[head] <= 1'b0;
             end
-            if(req_next & io.req_success)begin
+            if(req_next & io.req_success | replaceHit[head] & ~req_start)begin
                 amo_req <= amo[head];
             end
         end
@@ -400,7 +422,7 @@ endgenerate
 `endif
 
 // req
-    assign io.req = en[head] & ~req_start;
+    assign io.req = en[head] & ~replaceHit[head] & ~req_start;
     assign io.req_addr = {addr[head], {`DCACHE_BANK_WIDTH{1'b0}}, 2'b0};
     assign rlast = r_axi_io.r_valid & r_axi_io.r_last;
 
@@ -426,10 +448,16 @@ endgenerate
             req_valid_all <= 0;
             req_wvalid <= 0;
             req_state <= 0;
+            l2_idxs <= 0;
+            req_replace_hit <= 1'b0;
+            req_owned <= 0;
+            req_owned_after <= 0;
         end
         else begin
-            if(io.req)begin
+            if(io.req | replaceHit[head] & ~req_start)begin
                 req_start <= 1'b1;
+                req_replace_hit <= replaceHit[head];
+                req_owned <= wowned[head];
             end
 
             if(req_next & ~io.req_success)begin
@@ -440,29 +468,37 @@ endgenerate
                 req_start <= 1'b0;
             end
 
-            if(req_next & io.req_success)begin
+            if(req_next & io.req_success | replaceHit[head] & ~req_start)begin
                 req_cache <= 1'b1;
                 cache_addr <= io.req_addr;
                 req_way <= io.replaceWay;
                 req_valid_all <= data_valid_all[head];
                 req_wvalid <= wvalid[head];
-            end
-
-            if(req_next & io.req_success)begin
-                way[head] <= io.replaceWay;
+                way[head] <= replaceHit[head] ? replaceHitWay[head] : io.replaceWay;
             end
 
             if(r_axi_io.ar_valid & r_axi_io.ar_ready)begin
                 req_cache <= 1'b0;
             end
 
-            if(r_axi_io.r_valid)begin
+            // MAKE_UNIQUE OR CLEAN_UNIQUE
+            if(r_axi_io.r_valid & ~(r_axi_io.r_last & (cacheIdx == 0)))begin
                 cacheIdx <= cacheIdx + 1;
             end
+            if(r_axi_io.r_valid & (cacheIdx == 0))begin
+                l2_idxs[head] <= io.l2_idx;
+            end
         end
-        if(r_axi_io.r_valid)begin
+        if(r_axi_io.r_valid & ~(r_axi_io.r_last & (cacheIdx == 0)))begin
             cacheData[cacheIdx] <= r_axi_io.r_data;
         end
+        if(r_axi_io.r_valid & r_axi_io.r_last & (cacheIdx == 0) & req_owned & req_replace_hit)begin
+            req_owned_after <= 1'b1;
+        end
+        else if(r_axi_io.r_valid & r_axi_io.r_last)begin
+            req_owned_after <= 1'b0;
+        end
+    
         if(rlast)begin
             req_data <= data[head];
             req_mask <= mask[head];
@@ -470,7 +506,7 @@ endgenerate
 `ifdef RVA
                         | amo_req
 `endif
-            ? 3'b111 : r_axi_io.r_resp[4: 2];
+            ? 3'b101 : r_axi_io.r_resp[4: 2];
         end
     end
 
@@ -486,6 +522,7 @@ endgenerate
                                amo_req ? `ACEOP_READ_UNIQUE :
 `endif
                                req_valid_all ? `ACEOP_MAKE_UNIQUE :
+                               req_wvalid & req_replace_hit & req_owned ? `ACEOP_CLEAN_UNIQUE :
                                req_wvalid ? `ACEOP_READ_UNIQUE : `ACEOP_READ_SHARED;
 
     assign r_axi_io.r_ready = 1'b1;
diff --git a/src/core/backend/lsu/dcache/DCacheWay.sv b/src/core/backend/lsu/dcache/DCacheWay.sv
index 03979e1..8b54e55 100644
--- a/src/core/backend/lsu/dcache/DCacheWay.sv
+++ b/src/core/backend/lsu/dcache/DCacheWay.sv
@@ -7,8 +7,8 @@ module DCacheData(
     input logic `N(`DCACHE_WAY) tag_we,
     input logic `N(`DCACHE_WAY) valid_we,
     input logic `ARRAY(`LOAD_PIPELINE+1, `DCACHE_SET_WIDTH) tagv_index,
-    input logic `ARRAY(`LOAD_PIPELINE+1, `DCACHE_SET_WIDTH) tagv_windex,
-    input logic `N(`DCACHE_TAG+1) tagv_wdata,
+    input logic `N(`DCACHE_SET_WIDTH) tagv_windex,
+    input logic `N(`DCACHE_TAG) tag_wdata,
     output logic `TENSOR(`LOAD_PIPELINE+1, `DCACHE_WAY, `DCACHE_TAG+1) tagv,
     output DCacheMeta `N(`DCACHE_WAY) meta,
     input DCacheMeta wmeta,
@@ -21,6 +21,9 @@ module DCacheData(
     logic `TENSOR(`LOAD_PIPELINE+1, `DCACHE_WAY, `DCACHE_TAG) tag;
     logic `ARRAY(`LOAD_PIPELINE+1, `DCACHE_WAY) valid;
 generate
+    for(genvar i=0; i<`DCACHE_WAY; i++)begin
+        assign valid[`LOAD_PIPELINE][i] = meta[i].v;
+    end
     for(genvar i=0; i<`LOAD_PIPELINE+1; i++)begin
         for(genvar j=0; j<`DCACHE_WAY; j++)begin
             assign tagv[i][j][`DCACHE_TAG: 1] = tag[i][j];
@@ -38,10 +41,10 @@ generate
             .rst(rst),
             .rst_sync(0),
             .en(tagv_en[i]),
-            .addr(tagv_index[i]),
+            .addr(|tag_we ? tagv_windex : tagv_index[i]),
             .rdata(tag[i]),
             .we(tag_we),
-            .wdata({`DCACHE_WAY{tagv_wdata[`DCACHE_TAG: 1]}}),
+            .wdata({`DCACHE_WAY{tag_wdata}}),
             .ready()
         );
     end
@@ -61,9 +64,9 @@ generate
             .en(tagv_en[i]),
             .raddr(tagv_index[i]),
             .rdata(valid[i]),
-            .we(valid_we[i]),
-            .waddr(tagv_windex[i]),
-            .wdata({`DCACHE_WAY{tagv_wdata[0]}}),
+            .we(valid_we),
+            .waddr(tagv_windex),
+            .wdata({`DCACHE_WAY{wmeta.v}}),
             .ready()
         );
     end
@@ -82,8 +85,8 @@ generate
         .en(tagv_en[`LOAD_PIPELINE]),
         .raddr(tagv_index[`LOAD_PIPELINE]),
         .rdata(meta),
-        .we(valid_we[`LOAD_PIPELINE]),
-        .waddr(tagv_windex[`LOAD_PIPELINE]),
+        .we(valid_we),
+        .waddr(tagv_windex),
         .wdata({`DCACHE_WAY{wmeta}}),
         .ready()
     );
diff --git a/src/core/backend/lsu/dcache/ReplaceQueue.sv b/src/core/backend/lsu/dcache/ReplaceQueue.sv
index e17f3ce..3b8bbda 100644
--- a/src/core/backend/lsu/dcache/ReplaceQueue.sv
+++ b/src/core/backend/lsu/dcache/ReplaceQueue.sv
@@ -4,6 +4,7 @@ interface ReplaceQueueIO;
     logic en;
     logic refill_en;
     DirectoryState refill_state;
+    logic entry_en;
     logic `N(`DCACHE_TAG+`DCACHE_SET_WIDTH) addr;
     logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) data;
     logic `N(`DCACHE_REPLACE_WIDTH) idx;
@@ -21,7 +22,7 @@ interface ReplaceQueueIO;
     logic `N(`PADDR_SIZE) snoop_addr;
     logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) snoop_data;
 
-    modport queue (input en, refill_en, refill_state, addr, data, replace_idx, waddr, snoop_en, snoop_clean, snoop_addr, output idx, whit, full, snoop_data, snoop_hit, snoop_state);
+    modport queue (input en, refill_en, refill_state, entry_en, addr, data, replace_idx, waddr, snoop_en, snoop_clean, snoop_addr, output idx, whit, full, snoop_data, snoop_hit, snoop_state);
     modport miss (input full, idx, output replace_idx);
 endinterface
 
@@ -33,10 +34,11 @@ module ReplaceQueue(
 );
     localparam TRANSFER_BANK = `DCACHE_LINE / `DATA_BYTE;
     typedef struct packed {
+        logic en;
         logic `N(`DCACHE_TAG+`DCACHE_SET_WIDTH) addr;
         logic `ARRAY(TRANSFER_BANK, `XLEN) data;
     } ReplaceEntry;
-    typedef enum { IDLE, ADDRESS, WRITE, WAIT_B, RETIRE } ReplaceState;
+    typedef enum { IDLE, ADDRESS, WRITE, WAIT_B } ReplaceState;
     ReplaceState replace_state;
 
     ReplaceEntry entrys `N(`DCACHE_REPLACE_SIZE);
@@ -47,10 +49,18 @@ module ReplaceQueue(
     logic full;
     logic `N(`DCACHE_REPLACE_SIZE) hit;
     logic `N(`PADDR_SIZE) waddr;
-    logic retire_last;
     ReplaceEntry newEntry;
 
+    logic aw_valid;
+    logic `N($clog2(TRANSFER_BANK)) widx;
+    logic wvalid;
+    logic wlast;
+    logic aw_dirty;
+    logic refill_invalid;
+    ReplaceEntry processEntry;
+
     assign io.full = full;
+    assign newEntry.en = io.entry_en;
     assign newEntry.addr = io.addr;
     assign newEntry.data = io.data;
     PEncoder #(`DCACHE_REPLACE_SIZE) encoder_free_idx (~en, freeIdx);
@@ -84,7 +94,7 @@ module ReplaceQueue(
                 state[io.replace_idx] <= io.refill_state;
             end
 
-            if(retire_last)begin
+            if(w_axi_io.b_valid | refill_invalid)begin
                 en[processIdx] <= 1'b0;
                 dataValid[processIdx] <= 1'b0;
                 prior[processIdx] <= 1'b0;
@@ -96,7 +106,7 @@ module ReplaceQueue(
     assign waddr = io.snoop_en ? io.snoop_addr : io.waddr;
 generate
     for(genvar i=0; i<`DCACHE_REPLACE_SIZE; i++)begin
-        assign hit[i] = dataValid[i] & (waddr`DCACHE_BLOCK_BUS == entrys[i].addr);
+        assign hit[i] = dataValid[i] & entrys[i].en & (waddr`DCACHE_BLOCK_BUS == entrys[i].addr);
     end
     logic `N(`DCACHE_REPLACE_WIDTH) whit_idx;
     Encoder #(`DCACHE_REPLACE_SIZE) encoder_hit (hit, whit_idx);
@@ -107,12 +117,6 @@ generate
 endgenerate
 
 // axi
-    logic aw_valid;
-    logic `N($clog2(TRANSFER_BANK)) widx;
-    logic wvalid;
-    logic wlast;
-    logic aw_dirty;
-    ReplaceEntry processEntry;
 
     assign valid = en & dataValid;
     assign prior_valid = en & dataValid & prior;
@@ -128,15 +132,21 @@ endgenerate
             processEntry <= 0;
             processIdx <= 0;
             replace_state <= IDLE;
-            retire_last <= 1'b0;
+            refill_invalid <= 1'b0;
         end
         else begin
             case(replace_state)
             IDLE: begin
                 if(|valid)begin
-                    aw_valid <= 1'b1;
                     aw_dirty <= state[processIdx_pre].dirty;
-                    replace_state <= ADDRESS;
+                    if (entrys[processIdx_pre].en)begin
+                        replace_state <= ADDRESS;
+                        aw_valid <= 1'b1;
+                    end
+                    else begin
+                        replace_state <= WAIT_B;
+                        refill_invalid <= 1'b1;
+                    end
                     processEntry <= entrys[processIdx_pre];
                     processIdx <= processIdx_pre;
                 end
@@ -144,13 +154,8 @@ endgenerate
             ADDRESS: begin
                 if(w_axi_io.aw_valid & w_axi_io.aw_ready)begin
                     aw_valid <= 1'b0;
-                    if(aw_dirty)begin
-                        replace_state <= WRITE;
-                        wvalid <= 1'b1;
-                    end
-                    else begin
-                        replace_state <= RETIRE;
-                    end
+                    replace_state <= WRITE;
+                    wvalid <= 1'b1;
                 end
             end
             WRITE: begin
@@ -169,17 +174,9 @@ endgenerate
                 end
             end
             WAIT_B: begin
-                if(w_axi_io.b_valid)begin
-                    replace_state <= RETIRE;
-                end
-            end
-            RETIRE: begin
-                if(retire_last)begin
+                if(w_axi_io.b_valid | refill_invalid)begin
                     replace_state <= IDLE;
-                    retire_last <= 1'b0;
-                end
-                else begin
-                    retire_last <= 1'b1;
+                    refill_invalid <= 1'b0;
                 end
             end
             endcase
@@ -231,7 +228,7 @@ endgenerate
 
 `ifdef DIFFTEST
     `LOG_ARRAY(T_DCACHE, dbg_data, newEntry.data, TRANSFER_BANK)
-    `Log(DLog::Debug, T_DCACHE, io.refill_en & io.refill_dirty,
+    `Log(DLog::Debug, T_DCACHE, io.refill_en & io.entry_en,
         $sformatf("dcache replace. [%h] %s", newEntry.addr << `DCACHE_LINE_WIDTH, dbg_data))
 `endif
 endmodule
\ No newline at end of file
diff --git a/src/core/backend/lsu/dcache/dcache.sv b/src/core/backend/lsu/dcache/dcache.sv
index 104d471..1570610 100644
--- a/src/core/backend/lsu/dcache/dcache.sv
+++ b/src/core/backend/lsu/dcache/dcache.sv
@@ -15,7 +15,7 @@ module DCache(
 
     logic `ARRAY(`LOAD_PIPELINE, `DCACHE_SET_WIDTH) loadIdx;
     logic `ARRAY(`LOAD_PIPELINE+1, `DCACHE_SET_WIDTH) tagvIdx;
-    logic `ARRAY(`LOAD_PIPELINE+1, `DCACHE_SET_WIDTH) tagvWIdx;
+    logic `N(`DCACHE_SET_WIDTH) tagvWIdx;
     logic `ARRAY(`LOAD_PIPELINE, `DCACHE_LINE_WIDTH-2) loadOffset;
     logic `ARRAY(`LOAD_PIPELINE, `DCACHE_BANK) loadBankDecode;
     logic `N(`DCACHE_BANK) loadBank;
@@ -59,6 +59,8 @@ module DCache(
     logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) snoop_replace_data, snoop_data;
     logic `N(`DCACHE_BANK_WIDTH) snoop_data_idx;
     logic `N(`DCACHE_WAY) way_dirty;
+    logic snoop_rack;
+    logic `N(`L2MSHR_WIDTH) snoop_rid;
 
 `ifdef RVA
     logic amo_req, islr, issc, amo_req_n;
@@ -123,18 +125,16 @@ endgenerate
     logic `N(`DCACHE_SET_WIDTH) refillIdx;
     logic `ARRAY(`DCACHE_BANK, `DCACHE_BITS) refillData;
     logic `TENSOR(`DCACHE_BANK, `DCACHE_WAY, `DCACHE_BITS) data_rdata;
-    logic `N(`DCACHE_WAY) dirty_we, dirty_wdata;
 
 generate
     // TODO: 每个way使用单独的index，refill和snoop不同way时可以同时写入
     for(genvar i=0; i<`LOAD_PIPELINE; i++)begin
         assign tagv_en[i] = rio.req[i];
         assign tagvIdx[i] = loadIdx[i];
-        assign tagvWIdx[i] = snoop_invalid & (|w_wayhit) ? widx : miss_io.refillAddr`DCACHE_SET_BUS;
     end
     assign tagv_en[`LOAD_PIPELINE] = wreq | miss_io.refill_en;
     assign tagvIdx[`LOAD_PIPELINE] = wreq ? widx : miss_io.refillAddr`DCACHE_SET_BUS;
-    assign tagvWIdx[`LOAD_PIPELINE] = snoop_invalid & (|w_wayhit) ? widx : miss_io.refillAddr`DCACHE_SET_BUS;
+    assign tagvWIdx = snoop_invalid & (|w_wayhit) ? widx : miss_io.refillAddr`DCACHE_SET_BUS;
     // TODO: 只有原来不是share才需要写入(snoop_share)
     assign tag_we = {`DCACHE_WAY{miss_io.refill_valid & miss_io.refill_en}} & refill_way;
     assign valid_we = {`DCACHE_WAY{miss_io.refill_valid & miss_io.refill_en}} & refill_way |
@@ -146,7 +146,7 @@ generate
     for(genvar i=0; i<`DCACHE_BANK; i++)begin
         for(genvar j=0; j<`DCACHE_WAY; j++)begin
             assign data_we[i][j] = {`DCACHE_BYTE{cache_wreq & cache_wway[j]}} & wmask_n[i] |
-                                   {`DCACHE_BYTE{miss_io.refill_valid & miss_io.refill_en & refill_way[j]}};
+                                   {`DCACHE_BYTE{miss_io.refill_valid & miss_io.refill_en & refill_way[j]}} & miss_io.refillMask[i];
             assign rdata[j][i] = data_rdata[i][j];
         end
         assign data_index[i] = snoop_share & whit ? snoop_addr`DCACHE_SET_BUS : 
@@ -162,10 +162,6 @@ endgenerate
     assign refillIdx = cache_wreq & (|cache_wway) ? waddr_n`DCACHE_SET_BUS :
                                                 miss_io.refillAddr`DCACHE_SET_BUS;
     assign refillData = cache_wreq & (|cache_wway) ? wdata_n : miss_io.refillData;
-    assign dirty_we = {`DCACHE_WAY{cache_wreq}} & cache_wway | 
-                      {`DCACHE_WAY{miss_io.refill_valid & miss_io.refill_en}} & refill_way;
-    assign dirty_wdata = ({`DCACHE_WAY{cache_wreq}} & cache_wway) |
-                         ({`DCACHE_WAY{miss_io.refill_valid & miss_io.refill_en & miss_io.refill_dirty}} & refill_way);
 
     DCacheData cache_data (
         .clk,
@@ -175,7 +171,7 @@ endgenerate
         .valid_we,
         .tagv_index(tagvIdx),
         .tagv_windex(tagvWIdx),
-        .tagv_wdata({miss_io.refillAddr`DCACHE_TAG_BUS, 1'b1}),
+        .tag_wdata(miss_io.refillAddr`DCACHE_TAG_BUS),
         .tagv,
         .meta,
         .wmeta,
@@ -343,6 +339,8 @@ endgenerate
     assign miss_io.wmask = wmask_n;
     assign miss_io.req_success = ~snoop_req & miss_req_n & 
                                  ~replace_queue_io.full & ~replace_queue_io.whit;
+    assign miss_io.replaceHit = |w_wayhit;
+    assign miss_io.replaceHitWay = w_wayIdx;
     assign miss_io.replaceWay = missWay_encode;
     assign miss_io.scIdx = scIdx_n;
     assign wio.conflict = miss_io.wfull;
@@ -363,18 +361,19 @@ endgenerate
 `endif
     ;
     always_ff @(posedge clk)begin
-        wio.refill <= miss_io.refill_en & miss_io.refill_valid & miss_io.refill_dirty;
+        wio.refill <= miss_io.refill_en & miss_io.refill_valid & miss_io.refill_write;
         wio.refillIdx <= miss_io.refill_scIdx;
     end
 
     // replace enqueue
     assign replace_addr = {wtagv[refill_way_n][`DCACHE_TAG: 1], refill_addr_n`DCACHE_SET_BUS};
     always_ff @(posedge clk)begin
-        refill_en_n <= miss_io.refill_en & miss_io.refill_valid;
+        refill_en_n <= miss_io.refill_en & miss_io.refill_valid & ~miss_io.refill_replace_hit;
         refill_way_n <= snoop_req ? w_wayIdx : miss_io.refillWay;
         refill_addr_n <= miss_io.refillAddr;
     end
     assign replace_queue_io.refill_en = refill_en_n;
+    assign replace_queue_io.entry_en = meta[refill_way_n].v;
     assign replace_queue_io.refill_state = meta[refill_way_n].v ? meta[refill_way_n][2: 0] : 0;
     assign replace_queue_io.addr = replace_addr;
     assign replace_queue_io.data = rdata[refill_way_n];
@@ -389,6 +388,8 @@ endgenerate
         snoop_replace_hit <= snoop_req_n & replace_queue_io.snoop_hit;
         snoop_hit <= snoop_cache_hit | snoop_replace_hit;
         snoop_share_n <= snoop_share;
+        snoop_rack <= miss_io.refill_en & miss_io.refill_valid;
+        snoop_rid <= miss_io.refill_l2idx;
     end
     always_ff @(posedge clk, posedge rst)begin
         if (rst == `RST)begin
@@ -412,7 +413,7 @@ endgenerate
 
             if(snoop_req_n)begin
                 cr_valid <= 1'b1;
-                cr_state <= whit ? select_meta[2: 0] : replace_queue_io.snoop_state;
+                cr_state <= |w_wayhit ? select_meta[2: 0] : replace_queue_io.snoop_state;
                 snoop_invalid_n <= snoop_invalid;
             end
             if(cr_valid & snoop_io.cr_ready)begin
@@ -442,12 +443,15 @@ endgenerate
     assign replace_queue_io.snoop_en = snoop_req;
     assign replace_queue_io.snoop_clean = snoop_io.ac_snoop == `ACEOP_CLEAN_INVALID;
     assign replace_queue_io.snoop_addr = snoop_io.ac_addr;
+    assign miss_io.l2_idx = snoop_io.ar_snoop_id;
     assign snoop_io.ac_ready = ac_ready;
     assign snoop_io.cr_valid = cr_valid;
     assign snoop_io.cr_resp = {cr_state, 2'b00};
     assign snoop_io.cd_valid = cd_valid;
     assign snoop_io.cd_data = snoop_data[snoop_data_idx];
     assign snoop_io.cd_last = cd_last;
+    assign snoop_io.rack = snoop_rack;
+    assign snoop_io.r_snoop_id = snoop_rid;
 
 
 // amo
@@ -514,7 +518,7 @@ endgenerate
     `LOG_ARRAY(T_DCACHE, dbg_refillData, miss_io.refillData, `DCACHE_BANK)
     `LOG_ARRAY(T_DCACHE, dbg_wdata, dbg_wdatan, `DCACHE_BANK)
     `Log(DLog::Debug, T_DCACHE, miss_io.refill_en & miss_io.refill_valid,
-        $sformatf("dcache refill. [%8h %d %b] %s", miss_io.refillAddr, miss_io.refillWay, miss_io.refill_dirty, dbg_refillData))
+        $sformatf("dcache refill. [%8h %d %b] %s", miss_io.refillAddr, miss_io.refillWay, miss_io.refill_write, dbg_refillData))
     `Log(DLog::Debug, T_DCACHE, wreq_n & whit,
         $sformatf("dcache write. [%h %d] %s", waddr_n, w_wayIdx, dbg_wdata))
 `endif
diff --git a/src/core/frontend/icache/Icache.sv b/src/core/frontend/icache/Icache.sv
index e1b28e4..42d2e41 100644
--- a/src/core/frontend/icache/Icache.sv
+++ b/src/core/frontend/icache/Icache.sv
@@ -273,7 +273,7 @@ endgenerate
     assign axi_io.ar_burst = 2'b01;
     assign axi_io.ar_valid = main_state == MISS;
     assign axi_io.ar_user = 0;
-    assign axi_io.ar_snoop = `ACEOP_READ_SHARED;
+    assign axi_io.ar_snoop = `ACEOP_READ_ONCE;
     assign axi_io.r_ready = 1'b1;
 
 `define REQ_DEF \
diff --git a/src/core/mem/cache/Directory.sv b/src/core/mem/cache/Directory.sv
index b005c7b..60a3951 100644
--- a/src/core/mem/cache/Directory.sv
+++ b/src/core/mem/cache/Directory.sv
@@ -75,7 +75,7 @@ module LocalDirectory #(
 generate
     for(genvar i=0; i<WAY; i++)begin
         logic `N(SET_WIDTH) addr;
-        assign addr = mshr_slave_io.request ? mshr_slave_io.raddr[OFFSET_WIDTH +: SET_WIDTH] : mshr_slave_io.waddr[OFFSET_WIDTH +: SET_WIDTH];
+        assign addr = mshr_slave_io.request ? mshr_slave_io.raddr[OFFSET_WIDTH +: SET_WIDTH] : mshr_slave_io.waddr;
         SPRAM #(
             .WIDTH(ENTRY_SIZE),
             .DEPTH(SET),
@@ -100,7 +100,7 @@ generate
     assign mshr_slave_io.hit = select_hit;
     assign mshr_slave_io.share = select_entry[TAG_WIDTH];
     assign mshr_slave_io.slave = select_entry[TAG_WIDTH + 1 +: SLAVE_NUM];
-    if(LLC)begin
+    if(!LLC)begin
         assign mshr_slave_io.owned = select_entry[ENTRY_SIZE-1];
         assign mshr_slave_io.owner = select_entry[ENTRY_SIZE-2 -: SLAVE_WIDTH];
         assign mshr_slave_io.replace_owned = replace_data[ENTRY_SIZE-1];
@@ -158,7 +158,7 @@ module L2Directory #(
     assign replace_io.hit_en = mshr_dir_io.hit & en_n | mshr_dir_io.we & ~mshr_dir_io.request;
     assign replace_io.hit_way = mshr_dir_io.we & ~mshr_dir_io.request ? 
                     (mshr_dir_io.wdata[0] ? mshr_dir_io.wway : ~mshr_dir_io.wway) : tagv_hits;
-    assign replace_io.hit_index = mshr_dir_io.we & ~mshr_dir_io.request ? mshr_dir_io.waddr[OFFSET_WIDTH +: SET_WIDTH] : lookup_idx;
+    assign replace_io.hit_index = mshr_dir_io.we & ~mshr_dir_io.request ? mshr_dir_io.waddr : lookup_idx;
     always_ff @(posedge clk)begin
         if(mshr_dir_io.request)begin
             cmp_tag <= mshr_dir_io.raddr[`PADDR_SIZE-1 -: TAG_WIDTH];
@@ -169,7 +169,7 @@ module L2Directory #(
 generate
     for(genvar i=0; i<WAY_NUM; i++)begin
         logic `N(SET_WIDTH) addr;
-        assign addr = mshr_dir_io.request ? mshr_dir_io.raddr[OFFSET_WIDTH +: SET_WIDTH] : mshr_dir_io.waddr[OFFSET_WIDTH +: SET_WIDTH];
+        assign addr = mshr_dir_io.request ? mshr_dir_io.raddr[OFFSET_WIDTH +: SET_WIDTH] : mshr_dir_io.waddr;
         SPRAM #(
             .WIDTH(DIRECTORY_SIZE),
             .DEPTH(SET),
@@ -199,6 +199,6 @@ endgenerate
     assign mshr_dir_io.replace_tagv = replace_data[TAG_WIDTH: 0];
     assign mshr_dir_io.replace_state = replace_data[TAG_WIDTH+1 +: $bits(DirectoryState)];
 
-    Decoder #(WAY_NUM) decoder_wway (mshr_slave_io.wway, wway_dec);
+    Decoder #(WAY_NUM) decoder_wway (mshr_dir_io.wway, wway_dec);
     assign mshr_dir_io.wready = ~mshr_dir_io.request;
 endmodule
\ No newline at end of file
diff --git a/src/core/mem/cache/L2CacheWrapper.sv b/src/core/mem/cache/L2CacheWrapper.sv
index 90b4f74..46c657c 100644
--- a/src/core/mem/cache/L2CacheWrapper.sv
+++ b/src/core/mem/cache/L2CacheWrapper.sv
@@ -12,7 +12,6 @@ module L2CacheWrapper #(
     CacheBus.slave icache_io,
     CacheBus.slave tlb_io,
     CacheBus.slave dcache_io,
-    CacheBus.slave ducache_io,
     CacheBus.master master_io, // to mem
     output snoop_req_t snoop_req,
     input snoop_resp_t snoop_resp,
@@ -45,9 +44,13 @@ module L2CacheWrapper #(
     `SNOOP_TYPEDEF_AC_CHAN_T(snoop_ac_chan_t, addr_t)
     `SNOOP_TYPEDEF_CD_CHAN_T(snoop_cd_chan_t, data_t)
     `SNOOP_TYPEDEF_CR_CHAN_T(snoop_cr_chan_t)
+    typedef logic [`L2MSHR_WIDTH-1: 0] snoop_id_t;
 
-    AxiReq ireq, dreq, du_req, tlb_req;
-    AxiResp iresp, dresp, du_resp, tlb_resp;
+    snoop_req_t l2_snoop_req;
+    snoop_resp_t l2_snoop_resp;
+
+    AxiReq ireq, dreq, tlb_req;
+    AxiResp iresp, dresp, tlb_resp;
     AxiMReq req_o;
     AxiMResp resp_i;
     CacheBus #(
@@ -81,9 +84,6 @@ module L2CacheWrapper #(
     `CACHE_ASSIGN_TO_REQ(dreq, dcache_io)
     `CACHE_ASSIGN_FROM_RESP(dcache_io, dresp)
 
-    `CACHE_ASSIGN_TO_REQ(du_req, ducache_io)
-    `CACHE_ASSIGN_FROM_RESP(ducache_io, du_resp)
-
     `CACHE_ASSIGN_FROM_REQ(l2_cache_io, req_o)
     `CACHE_ASSIGN_TO_RESP(resp_i, l2_cache_io)
 
@@ -103,17 +103,37 @@ module L2CacheWrapper #(
         .mst_req_t(AxiMReq),
         .mst_resp_t(AxiMResp),
         .MaxWTrans(1),
-        .NoSlvPorts(4)
+        .NoSlvPorts(3),
+        .SpillW(1),
+        .SpillB(1), 
+        .SpillR(1)
     ) axi_mux_inst(
         .clk_i(clk),
         .rst_ni(~rst),
         .test_i(1'b0),
-        .slv_reqs_i({dreq, du_req, tlb_req, ireq}),
-        .slv_resps_o({dresp, du_resp, tlb_resp, iresp}),
+        .slv_reqs_i({dreq, tlb_req, ireq}),
+        .slv_resps_o({dresp, tlb_resp, iresp}),
         .mst_req_o(req_o),
         .mst_resp_i(resp_i)
     );
 
+    snoop_multicut #(
+        .NoCuts(1),
+        .ac_chan_t(snoop_ac_chan_t),
+        .cr_chan_t(snoop_cr_chan_t),
+        .cd_chan_t(snoop_cd_chan_t),
+        .snoop_id_t(snoop_id_t),
+        .req_t(snoop_req_t),
+        .resp_t(snoop_resp_t)
+    ) snoop_cut (
+        .clk_i(clk),
+        .rst_ni(~rst),
+        .slv_req_i(l2_snoop_req),
+        .slv_resp_o(l2_snoop_resp),
+        .mst_req_o(snoop_req),
+        .mst_resp_i(snoop_resp)
+    );
+
     L2Cache #(
         .MSHR_SIZE(`L2MSHR_SIZE),
         .SLAVE_BANK(`DCACHE_BANK),
@@ -143,8 +163,8 @@ module L2CacheWrapper #(
         .rst,
         .slave_io(l2_cache_io.slave),
         .master_io(master_io),
-        .snoop_req,
-        .snoop_resp,
+        .snoop_req(l2_snoop_req),
+        .snoop_resp(l2_snoop_resp),
         .mst_snoop_req,
         .mst_snoop_resp
     );
diff --git a/src/core/mem/cache/L2MSHR.sv b/src/core/mem/cache/L2MSHR.sv
index b1c9d11..2580e43 100644
--- a/src/core/mem/cache/L2MSHR.sv
+++ b/src/core/mem/cache/L2MSHR.sv
@@ -9,6 +9,8 @@
 // READ_SHARED: mem read
 // READ_UNIQUE: mem write, don't owned
 // MAKE_UNIQUE: mem full write or owned
+// CLEAN_UNIQUE: mem write and owned, if owned after slave dir read, treat as MAKE_UNIQUE
+//               otherwise, treat as READ_UNIQUE
 // CLEAN_INVALID: snoop clean
 // WRITE:
 // WRITE_CLEAN: mem write and cache line is dirty
@@ -40,8 +42,8 @@ module L2MSHR #(
     parameter type mst_snoop_resp_t = logic,
     parameter MST_SNOOP_ID_WIDTH = 4,
     parameter MSHR_WIDTH = $clog2(MSHR_SIZE),
-    parameter SLAVE_BITS = (`CACHELINE_SIZE / SLAVE_BANK) * 4,
-    parameter CACHE_BITS = (`CACHELINE_SIZE / CACHE_BANK) * 4,
+    parameter SLAVE_BITS = (`CACHELINE_SIZE / SLAVE_BANK) * 8,
+    parameter CACHE_BITS = (`CACHELINE_SIZE / CACHE_BANK) * 8,
     parameter SLAVE_WIDTH = idxWidth(SLAVE),
     parameter SLAVE_BANK_WIDTH = $clog2(SLAVE_BANK),
     parameter CACHE_BANK_WIDTH = $clog2(CACHE_BANK),
@@ -91,6 +93,7 @@ module L2MSHR #(
         logic write;
         logic write_dirty;
         logic owned;
+        logic dir_clean;
         logic require_owned; // READ_UNIQUE, MAKE_UNIQUE
         logic slave_share;
         logic slave_hit;
@@ -104,7 +107,7 @@ module L2MSHR #(
     logic `ARRAY(MSHR_SIZE, WAY_WIDTH) lookup_ways;
     logic `ARRAY(MSHR_SIZE, `PADDR_SIZE) paddrs;
     logic `N(MSHR_SIZE) entry_snoop;
-    logic `N(MSHR_SIZE) en, dir_valid, require_data, op_valid, data_valid;
+    logic `N(MSHR_SIZE) en, require_data, op_valid, data_valid;
     logic `N(MSHR_SIZE) req_ll, req_ll_op_valid; // needed if ISL2 == 1
     logic `N(MSHR_SIZE) snoop_request, snoop_replace_request;
 
@@ -112,25 +115,31 @@ module L2MSHR #(
     logic `N(MSHR_SIZE) free_idx1, free_idx2;
     logic free_conflict, full, ar_free_conflict;
     logic `N(MSHR_SIZE) dir_requests, dir_request_select;
-    logic `N(MSHR_SIZE) dir_resp_reqs;
+    logic `N(MSHR_SIZE) dir_resp_reqs; // need response state to fill directory
     logic `N(MSHR_WIDTH) dir_select_idx, dir_select_idx_n;
     logic dir_request, dir_request_n;
     DirWInfo `N(MSHR_SIZE) dir_winfos;
+    logic `ARRAY(MSHR_SIZE, 4) dir_op;
 
-    logic `ARRAY(MSHR_SIZE, SLAVE_BANK) refill_valids, refill_valids_select;
+    logic `ARRAY(MSHR_SIZE, SLAVE_BANK) refill_valids;
+    logic `ARRAY(SLAVE_BANK, MSHR_SIZE) refill_valids_rev;
+    logic `N(SLAVE_BANK) refill_valids_bank;
+    logic `N(SLAVE_BANK_WIDTH) refill_bank_idx;
     logic `ARRAY(SLAVE_BANK, SLAVE_BITS) refill_data;
     logic `ARRAY(MSHR_SIZE, ID_WIDTH) refill_ids;
     DirectoryState `N(MSHR_SIZE) refill_resps;
     logic refill_snoop_resp_req, refill_l3_resp_req;
-    logic `N(MSHR_SIZE) refill_valid, refill_valid_select;
+    logic `ARRAY(SLAVE_BANK, MSHR_SIZE) refill_valid;
+    logic `N(MSHR_SIZE) refill_valid_select;
     logic `N(SLAVE_BANK) refill_bank_select;
-    logic `N(MSHR_WIDTH) refill_idx;
+    logic `N(MSHR_WIDTH) refill_idx, refill_direct_idx, refill_data_idx;
     logic refill_snoop;
     logic refill_r_valid;
     logic `N(SLAVE_BITS) refill_r_data;
     logic `ARRAY(DATA_BANK, MSHR_SIZE) data_bank_valids;
     logic `ARRAY(MSHR_SIZE, DATA_BANK) data_bank_valids_rev;
     logic `N(MSHR_SIZE) snoop_idx_dec, refill_idx_dec;
+    logic `N(MSHR_SIZE) refill_finish, refill_no_rack, refill_direct;
 
     typedef enum {SNOOP_IDLE, SNOOP_REQUEST} SnoopState;
     typedef struct packed {
@@ -148,6 +157,7 @@ module L2MSHR #(
     } SnoopBuffer;
     SnoopState snoop_state;
     MSHREntry snoop_entry;
+    logic `N(4) snoop_op;
     DirInfo snoop_dir_info;
     SnoopBuffer snoop_buffer;
     logic snoop_valid;
@@ -161,23 +171,23 @@ module L2MSHR #(
     logic `N(MSHR_SIZE) lookup_requests;
     logic `ARRAY(MSHR_SIZE, DATA_BANK) lookup_bank;
     logic `ARRAY(DATA_BANK, MSHR_SIZE) lookup_bank_rev;
-    logic `N(DATA_BANK) lookup_data_req, write_bank_req;
+    logic `N(DATA_BANK) lookup_data_req;
     logic `ARRAY(MSHR_SIZE, SET_WIDTH) lookup_addrs;
 
     typedef enum {L3_IDLE, L3_REQUEST} L3State;
     typedef struct packed {
         logic request;
-        logic `N(MSHR_SIZE) idx;
+        logic `N(MSHR_WIDTH) idx;
         logic `N(ID_WIDTH) id;
         logic `N(4) op;
         logic `N(`PADDR_SIZE) addr;
-        logic `N(DATA_BANK_WIDTH) data_index;
+        logic `N(CACHE_BANK_WIDTH) data_index;
     } L3Buffer;
     L3State l3_state;
     MSHREntry l3_entry;
     L3Buffer l3_buffer;
     logic `N(MSHR_SIZE) l3_requests;
-    logic `N(MSHR_SIZE) l3_idx_dec;
+    logic `N(MSHR_SIZE) l3_idx_dec, l3_buffer_idx_dec;
     logic `N(MSHR_WIDTH) l3_idx;
     logic l3_request;
 
@@ -187,6 +197,14 @@ module L2MSHR #(
     logic `N(ID_WIDTH) write_id, slave_b_id;
     logic `N(SLAVE_BANK_WIDTH) write_data_index;
     logic write_waiting, slave_b_valid;
+    logic `N(DATA_BANK) write_bank_req;
+    logic `ARRAY(DATA_BANK, MSHR_WIDTH) write_bank_idx;
+    logic `N(MSHR_SIZE) entry_write;
+    logic `N(MSHR_SIZE) write_req, write_data_finish, write_finish;
+    logic `N(MSHR_WIDTH) write_b_idx, write_data_finish_idx;
+    logic `ARRAY(MSHR_SIZE, ID_WIDTH) write_b_ids;
+    logic `N(ID_WIDTH) write_b_id;
+    logic write_b_req;
 
     typedef struct packed {
         logic aw_valid;
@@ -206,7 +224,7 @@ module L2MSHR #(
     logic `N(MSHR_SIZE) replace_reqs, replace_data_valids;
     logic replace_req;
     logic `ARRAY(MSHR_SIZE, WAY_WIDTH) replace_ways;
-    logic `ARRAY(WAY_WIDTH, TAG_WIDTH+1) replace_tags; // tag, dirty
+    logic `ARRAY(MSHR_SIZE, TAG_WIDTH+1) replace_tags; // tag, dirty
     MSHREntry replace_entry;
     logic `N(TAG_WIDTH+1) replace_tag;
     logic `N(MSHR_WIDTH) replace_idx;
@@ -219,11 +237,11 @@ module L2MSHR #(
     logic `ARRAY(CACHE_BANK, CACHE_BITS) replace_read_data;
 
 // enqueue
-    logic renq_en;
+    logic renq_en, rw_conflict, rsnoop_conflict;
     logic wenq_en;
     logic snoop_enq_en;
     logic `N(MSHR_SIZE) renq_conflict, wenq_conflict, snoop_enq_conflict;
-    logic `N(MSHR_SIZE) mshr_finish, dir_finish;
+    logic `N(MSHR_SIZE) mshr_finish, dir_finish, mshr_finish_n, mshr_finish_select;
     logic `N(MSHR_WIDTH) mshr_widx, mshr_widx_n;
     logic `N(SET_WIDTH) mshr_wpaddr;
     logic `N(MSHR_SIZE) waiting_conflict, waiting_select;
@@ -240,23 +258,29 @@ module L2MSHR #(
     assign slave_io.aw_ready = ~full & ~write_waiting;
     assign mst_snoop_resp.ac_ready = ~full & ~(slave_io.aw_valid & ~write_waiting);
 
+    // write > snoop > read
     assign renq_en = ~full & ~free_conflict & slave_io.ar_valid;
     assign wenq_en = ~full & slave_io.aw_valid & ~write_waiting;
     assign snoop_enq_en = ~full & mst_snoop_req.ac_valid;
+    assign rw_conflict = slave_io.aw_valid & ~write_waiting & (slave_io.ar_addr[OFFSET_WIDTH +: SET_WIDTH] == slave_io.aw_addr[OFFSET_WIDTH +: SET_WIDTH]);
+    assign rsnoop_conflict = mst_snoop_req.ac_valid & (mst_snoop_req.ac.addr[OFFSET_WIDTH +: SET_WIDTH] == slave_io.ar_addr[OFFSET_WIDTH +: SET_WIDTH]);
 generate
     for(genvar i=0; i<MSHR_SIZE; i++)begin
         assign renq_conflict[i] = en[i] & (slave_io.ar_addr[OFFSET_WIDTH +: SET_WIDTH] == paddrs[i][OFFSET_WIDTH +: SET_WIDTH]);
         assign wenq_conflict[i] = en[i] & (slave_io.aw_addr[OFFSET_WIDTH +: SET_WIDTH] == paddrs[i][OFFSET_WIDTH +: SET_WIDTH]);
         assign snoop_enq_conflict[i] = en[i] & (mst_snoop_req.ac.addr[OFFSET_WIDTH +: SET_WIDTH] == paddrs[i][OFFSET_WIDTH +: SET_WIDTH]);
-        assign waiting_conflict[i] = entry_waiting[i] & (paddrs[i][OFFSET_WIDTH +: SET_WIDTH] == mshr_wpaddr);
+        assign waiting_conflict[i] = entry_waiting[i] & (|mshr_finish_n) & (paddrs[i][OFFSET_WIDTH +: SET_WIDTH] == mshr_wpaddr);
     end
 endgenerate
 
     assign mshr_finish = en & dir_finish & ~dir_slave_wreq & ~dir_wreq & ~snoop_request &
-                         (~require_data | refill_finish) & ~replace_reqs & ~lookup_requests;
+        ~l3_requests & (~require_data | refill_finish) & ~replace_reqs & ~lookup_requests &
+        (~entry_write | write_finish);
     PEncoder #(MSHR_SIZE) encoder_mshr_widx (mshr_finish, mshr_widx);
+    PSelector #(MSHR_SIZE) selector_mshr_finish (mshr_finish, mshr_finish_select);
     always_ff @(posedge clk)begin
         mshr_widx_n <= mshr_widx;
+        mshr_finish_n <= mshr_finish_select;
         if(mshr_finish)begin
             mshr_wpaddr <= paddrs[mshr_widx][OFFSET_WIDTH +: SET_WIDTH];
         end
@@ -297,8 +321,8 @@ endgenerate
             end
             if(renq_en)begin
                 entrys[free_idx2] <= {1'b0, 1'b0, slave_io.ar_id[ID_OFFSET +: ID_WIDTH], slave_io.ar_snoop, slave_io.ar_addr};
-                dir_requests[free_idx2] <= ~(|renq_conflict);
-                entry_waiting[free_idx2] <= |renq_conflict;
+                dir_requests[free_idx2] <= ~(|renq_conflict) & ~rw_conflict & ~rsnoop_conflict;
+                entry_waiting[free_idx2] <= (|renq_conflict) | rw_conflict | rsnoop_conflict;
             end
 
             if(|dir_requests)begin
@@ -306,7 +330,7 @@ endgenerate
             end
 
             if(|waiting_conflict)begin
-                dir_valid[waiting_select_idx] <= 1'b1;
+                dir_requests[waiting_select_idx] <= 1'b1;
                 entry_waiting[waiting_select_idx] <= 1'b0;
             end
 
@@ -317,17 +341,19 @@ endgenerate
     end
 
 // refill buffer
-    logic `N(MSHR_SIZE) refill_finish, refill_no_rack;
 generate
     for(genvar i=0; i<DATA_BANK; i++)begin
         logic `N(MSHR_SIZE) mshr_idx_dec;
         Decoder #(MSHR_SIZE) decoder_data_valid (mshr_data_io.mshr_idx_o[i], mshr_idx_dec);
-        assign data_bank_valids[i] = {MSHR_SIZE{mshr_data_io.rvalid[i]}} & mshr_idx_dec;
+        assign data_bank_valids[i] = {MSHR_SIZE{mshr_data_io.rvalid[i] & ~(replace_busy & replace_data_hits[i])}} & mshr_idx_dec;
         for(genvar j=0; j<MSHR_SIZE; j++)begin
             assign data_bank_valids_rev[j][i] = data_bank_valids[i][j];
         end
     end
-    Decoder #(MSHR_SIZE) decoder_snoop_idx (snoop_buffer.data_index, snoop_idx_dec);
+    Decoder #(MSHR_SIZE) decoder_snoop_idx (snoop_buffer.idx, snoop_idx_dec);
+    Decoder #(MSHR_SIZE) decoder_l3_buffer_idx (l3_buffer.idx, l3_buffer_idx_dec);
+    
+    localparam PARTITION = CACHE_BITS / SLAVE_BITS;
     for(genvar i=0; i<SLAVE_BANK; i++)begin : refill_buffer
         logic `ARRAY(MSHR_SIZE, SLAVE_BITS) data, cache_data;
         logic `ARRAY(DATA_BANK, CACHE_BITS) bank_data;
@@ -335,18 +361,18 @@ generate
         logic `N(MSHR_SIZE) we;
         logic `N(MSHR_SIZE) data_we, snoop_we;
         logic `ARRAY(MSHR_SIZE, SLAVE_BITS) wdata;
-        assign snoop_we = {MSHR_SIZE{snoop_cd_valid & ~snoop_buffer.slave_replace}} & snoop_idx_dec;
+        assign snoop_we = {MSHR_SIZE{snoop_cd_valid & ~snoop_buffer.slave_replace}} & snoop_idx_dec & (snoop_buffer.data_index == i);
         assign we = data_we | snoop_we |
-                    {MSHR_SIZE{master_io.r_valid}} & l3_buffer.idx;
+                    {MSHR_SIZE{master_io.r_valid & (l3_buffer.data_index == (i / PARTITION))}} & l3_buffer_idx_dec;
         for(genvar j=0; j<DATA_BANK; j++)begin
             assign bank_data[j] = mshr_data_io.rdata[j][i];
         end
         for(genvar j=0; j<MSHR_SIZE; j++)begin
-            localparam PARTITION = CACHE_BITS / SLAVE_BITS;
             logic `N(CACHE_BITS) bank_select_data;
             logic `ARRAY(PARTITION, SLAVE_BITS) bank_select_data_part, mst_data_part;
             assign refill_valids[j][i] = data_valid[j];
-            assign wdata[j] = data_we[j] ? bank_select_data[i % PARTITION] : 
+            assign refill_valids_rev[i][j] = data_valid[j];
+            assign wdata[j] = data_we[j] ? bank_select_data_part[i % PARTITION] : 
                             snoop_we[j] ? snoop_cd_data.data : mst_data_part[i % PARTITION];
             FairSelect #(DATA_BANK, CACHE_BITS) select_data (data_bank_valids_rev[j], bank_data, data_we[j], bank_select_data);
             assign bank_select_data_part = bank_select_data;
@@ -366,19 +392,19 @@ generate
                     end
                 end
                 data_valid <= (data_valid | we & ~entry_snoop) & 
-                              ~(refill_valid_select & {MSHR_SIZE{refill_bank_select[i] & (slave_io.r_valid & slave_io.r_ready | 
-                              mst_snoop_resp.cd_valid & mst_snoop_req.cd_ready)}});
+                              ~(refill_valid_select & {MSHR_SIZE{refill_bank_select[i] & (slave_io.r_valid & slave_io.r_ready) & ~(|refill_direct)}});
 
             end
         end
+        PSelector #(MSHR_SIZE) encoder_refill_valid (refill_valids_rev[i], refill_valid[i]);
     end
-    for(genvar i=0; i<MSHR_SIZE; i++)begin
-        assign refill_valid[i] = |refill_valids[i];
-        PRSelector #(SLAVE_BANK) select_refill_bank (refill_valids[i], refill_valids_select[i]);
-    end
-    PEncoder #(MSHR_SIZE) encoder_refill_idx(refill_valid, refill_idx);
-    PSelector #(MSHR_SIZE) selector_refill_valid(refill_valid, refill_valid_select);
-    assign refill_bank_select = refill_valids_select[refill_idx];
+    ParallelOR #(SLAVE_BANK, MSHR_SIZE) or_refill_valids(refill_valids, refill_valids_bank);
+    PRSelector #(SLAVE_BANK) selector_refill_bank (refill_valids_bank, refill_bank_select);
+    PREncoder #(SLAVE_BANK) encoder_refill_bank (refill_valids_bank, refill_bank_idx);
+    assign refill_valid_select = refill_valid[refill_bank_idx];
+    Encoder #(MSHR_SIZE) encoder_refill_idx(refill_valid_select, refill_data_idx);
+    PEncoder #(MSHR_SIZE) encoder_direct_idx(refill_direct, refill_direct_idx);
+    assign refill_idx = |refill_direct ? refill_direct_idx : refill_data_idx;
 endgenerate
     always_ff @(posedge clk, posedge rst)begin
         if(rst == `RST)begin
@@ -389,22 +415,25 @@ endgenerate
             dir_resp_reqs <= 0;
             refill_finish <= 0;
             refill_no_rack <= 0;
+            refill_direct <= 0;
         end
         else begin
             if(dir_request_n)begin
                 refill_ids[dir_select_idx_n] <= dir_entry_n.id;
-                dir_resp_reqs[dir_select_idx_n] <= ~mshr_dir_io.hit & ~dir_entry_n.write;
+                dir_resp_reqs[dir_select_idx_n] <= ~mshr_dir_io.hit & ~dir_entry_n.write & ~dir_make_unique & ~dir_clean_unique_nodata;
                 refill_no_rack[dir_select_idx_n] <= dir_read_once | dir_entry_n.snoop;
+                refill_finish[dir_select_idx_n] <= 1'b0;
+                refill_direct[dir_select_idx_n] <= dir_make_unique | dir_clean_unique_nodata;
             end
 
             if(dir_request_n & mshr_dir_io.hit & ~dir_entry_n.write)begin
                 refill_resps[dir_select_idx_n] <= mshr_dir_io.hit_state;
             end
 
-            if((snoop_state == SNOOP_IDLE) & (|snoop_request) & (snoop_entry.op != `ACEOP_MAKE_UNIQUE))begin
+            if((snoop_state == SNOOP_IDLE) & (|snoop_request) & (snoop_op != `ACEOP_MAKE_UNIQUE))begin
                 refill_snoop_resp_req <= 1'b1;
             end
-            if(|snoop_buffer.response & refill_snoop_resp_req)begin
+            if((|snoop_buffer.response) & refill_snoop_resp_req)begin
                 refill_resps[snoop_buffer.idx] <= snoop_buffer.response_state;
                 dir_resp_reqs[snoop_buffer.idx] <= 1'b0;
                 refill_snoop_resp_req <= 1'b0;
@@ -415,11 +444,21 @@ endgenerate
             end
             if(master_io.r_valid & refill_l3_resp_req)begin
                 refill_l3_resp_req <= 1'b0;
-                refill_resps[l3_buffer.idx] <= master_io.r_resp[4: 2];
+                if(LLC)begin
+                    refill_resps[l3_buffer.idx] <= 3'b100;
+                end
+                else begin
+                    refill_resps[l3_buffer.idx] <= master_io.r_resp[4: 2];
+                end
                 dir_resp_reqs[l3_buffer.idx] <= 1'b0;
             end
 
-            if(ISL2 & slave_io.r_valid & slave_io.r_last & refill_no_rack[refill_idx])begin
+            if(slave_io.r_valid & slave_io.r_ready & slave_io.r_last & (|refill_direct))begin
+                refill_direct[refill_direct_idx] <= 1'b0;
+            end
+
+            if(ISL2 & slave_io.r_valid &  slave_io.r_ready & 
+                slave_io.r_last & refill_no_rack[refill_idx])begin
                 refill_finish[refill_idx] <= 1'b1;
             end
 
@@ -431,12 +470,12 @@ endgenerate
 
         end
     end
-    OldestSelect #(MSHR_SIZE, 1, SLAVE_BITS) select_refill_data (refill_valid, refill_data, refill_r_valid, refill_r_data);
-    assign slave_io.r_valid = refill_r_valid;
+    OldestSelect #(SLAVE_BANK, 1, SLAVE_BITS, 1) select_refill_data (refill_valids_bank, refill_data, refill_r_valid, refill_r_data);
+    assign slave_io.r_valid = (|refill_direct) | (|refill_valids_bank);
     assign slave_io.r_id = {refill_ids[refill_idx], 1'b0};
     assign slave_io.r_data = refill_r_data;
     assign slave_io.r_resp = {refill_resps[refill_idx], 2'b00};
-    assign slave_io.r_last = refill_valids_select[refill_idx][SLAVE_BANK-1];
+    assign slave_io.r_last = (|refill_direct) | refill_bank_select[SLAVE_BANK-1];
     assign slave_io.r_user = 0;
 generate
     for(genvar i=0; i<SLAVE; i++)begin
@@ -448,6 +487,7 @@ endgenerate
 // dir request
     MSHREntry dir_entry, dir_entry_n;
     logic dir_read_once, dir_read_share, dir_read_unique, dir_make_unique, dir_clean_invalid;
+    logic dir_clean_unique, dir_unique_req, dir_clean_unique_nodata, dir_clean_read;
     logic dir_clean_req, dir_write_clean;
     logic `N(MSHR_SIZE) dir_slave_wreq, dir_slave_we;
     logic `N(MSHR_SIZE) dir_wreq, dir_we;
@@ -490,16 +530,25 @@ endgenerate
     always_ff @(posedge clk)begin
         if(dir_request_n)begin
             dir_infos[dir_select_idx_n] <= {mshr_slave_io.slave, mshr_slave_io.owner};
-            lookup_ways[dir_select_idx_n] <= mshr_dir_io.hit_way;
+            lookup_ways[dir_select_idx_n] <= mshr_dir_io.hit ? mshr_dir_io.hit_way : mshr_dir_io.replace_way;
         end
         dir_read_once <= ~dir_entry.write & (dir_entry.op == `ACEOP_READ_ONCE);
         dir_read_share <= ~dir_entry.write & (dir_entry.op == `ACEOP_READ_SHARED);
         dir_read_unique <= ~dir_entry.write & (dir_entry.op == `ACEOP_READ_UNIQUE);
         dir_make_unique <= ~dir_entry.write & (dir_entry.op == `ACEOP_MAKE_UNIQUE);
+        dir_clean_unique <= ~dir_entry.write & (dir_entry.op == `ACEOP_CLEAN_UNIQUE);
+        dir_unique_req <= ~dir_entry.write & ((dir_entry.op == `ACEOP_READ_UNIQUE) | 
+                            (dir_entry.op == `ACEOP_CLEAN_UNIQUE) | 
+                            (dir_entry.op == `ACEOP_MAKE_UNIQUE));
         dir_clean_invalid <= ~dir_entry.write & (dir_entry.op == `ACEOP_CLEAN_INVALID);
         dir_write_clean <= dir_entry.write & (dir_entry.op == `ACEOP_WRITE_CLEAN);
-        dir_clean_req <= ~dir_entry.write & ((dir_entry.op == `ACEOP_CLEAN_INVALID) | (dir_entry.op == `ACEOP_MAKE_UNIQUE));
+        dir_clean_req <= ~dir_entry.write & ((dir_entry.op == `ACEOP_CLEAN_INVALID) | 
+                        (dir_entry.op == `ACEOP_MAKE_UNIQUE));
     end
+    assign dir_clean_unique_nodata = dir_clean_unique & (mshr_slave_io.hit & mshr_slave_io.owned & 
+                                    (mshr_slave_io.owner == dir_lookup_owner));
+    assign dir_clean_read = dir_clean_unique & ~dir_clean_unique_nodata;
+
     always_ff @(posedge clk, posedge rst)begin
         if(rst == `RST)begin
             require_data <= 0;
@@ -507,30 +556,37 @@ endgenerate
             dir_winfos <= 0;
             dir_wreq <= 0;
             dir_finish <= 0;
+            dir_op <= 0;
         end
         else begin
             if(dir_request_n)begin
                 dir_finish[dir_select_idx_n] <= 1'b1;
-                require_data[dir_select_idx_n] <= ~dir_entry_n.write & ~dir_clean_req;
+                require_data[dir_select_idx_n] <= ~dir_entry_n.write & ~dir_clean_req & ~dir_clean_unique_nodata;
                 dir_slave_wreq[dir_select_idx_n] <= ~dir_read_once & ~((dir_clean_invalid | dir_read_unique & dir_entry_n.snoop) & ~mshr_slave_io.hit);
-                dir_wreq[dir_select_idx_n] <= dir_entry_n.write | dir_read_once & ~mshr_dir_io.hit & ~mshr_slave_io.hit | 
-                                              (dir_clean_req | dir_read_unique & dir_entry_n.snoop) & mshr_dir_io.hit;
+                dir_wreq[dir_select_idx_n] <= dir_entry_n.write | 
+                    dir_read_once & ~mshr_dir_io.hit & ~mshr_slave_io.hit | 
+                    (dir_clean_req | dir_clean_unique | dir_read_unique |
+                    dir_read_share & ~dir_entry_n.snoop) & mshr_dir_io.hit;
                 dir_winfos[dir_select_idx_n] <= '{
                     waddr: dir_entry_n.paddr,
                     slave_replace_way: mshr_slave_io.hit ? mshr_slave_io.hit_way : mshr_slave_io.replace_way,
                     replace_way: mshr_dir_io.hit ? mshr_dir_io.hit_way : mshr_dir_io.replace_way,
                     slave: dir_entry_n.write | dir_read_unique & dir_entry_n.snoop | dir_clean_invalid ? 0 : // only owner will write
                            dir_read_share & mshr_slave_io.hit ? mshr_slave_io.slave | dir_lookup_owner_dec : 
-                           dir_read_unique | dir_make_unique ? dir_lookup_owner_dec : mshr_slave_io.slave,
+                           dir_unique_req ? dir_lookup_owner_dec : mshr_slave_io.slave,
+                    dir_clean: dir_clean_req | dir_clean_unique | dir_read_unique | 
+                               dir_read_share & ~dir_entry_n.snoop,
                     slave_share: mshr_slave_io.share,
                     write: dir_entry_n.write,
                     write_dirty: dir_write_clean,       
-                    require_owned: dir_read_unique | dir_make_unique,
+                    require_owned: dir_unique_req,
                     slave_hit: mshr_slave_io.hit,
                     dir_hit: mshr_dir_io.hit,
-                    owned: (dir_read_unique | dir_make_unique | mshr_slave_io.owned),
+                    owned: (dir_unique_req | mshr_slave_io.owned),
                     owner: mshr_slave_io.hit ? mshr_slave_io.owner : dir_lookup_owner
                 };
+                dir_op[dir_select_idx_n] <= dir_clean_unique_nodata ? `ACEOP_MAKE_UNIQUE : 
+                                        dir_clean_read ? `ACEOP_READ_UNIQUE : dir_entry_n.op;
             end
 
             if(|mshr_finish)begin
@@ -572,7 +628,7 @@ endgenerate
     assign mshr_dir_io.we = dir_wvalid;
     assign mshr_dir_io.waddr = dir_winfo.waddr[OFFSET_WIDTH +: SET_WIDTH];
     assign mshr_dir_io.wway = dir_winfo.replace_way;
-    assign mshr_dir_io.wdata[0] = 1'b1; // valid
+    assign mshr_dir_io.wdata[0] = ~dir_winfo.dir_clean; // valid
     assign mshr_dir_io.wdata[TAG_WIDTH: 1] = dir_winfo.waddr[OFFSET_WIDTH + SET_WIDTH +: TAG_WIDTH]; // tag
     assign dir_wstate.dirty = dir_winfo.write ? dir_winfo.write_dirty : dir_state.dirty;
     assign dir_wstate.share = dir_winfo.write ? dir_winfo.slave_share : dir_state.share;
@@ -582,6 +638,7 @@ endgenerate
 
 // snoop
     OldestSelect #(MSHR_SIZE, 1, $bits(MSHREntry)) select_snoop_entry (snoop_request, entrys, snoop_valid, snoop_entry);
+    OldestSelect #(MSHR_SIZE, 1, 4) select_snoop_op(snoop_request, dir_op, , snoop_op);
     OldestSelect #(MSHR_SIZE, 1, $bits(DirInfo)) select_snoop_dir (snoop_request, dir_infos, , snoop_dir_info);
     PEncoder #(MSHR_SIZE) encoder_snoop_idx (snoop_request, snoop_idx);
 generate
@@ -634,12 +691,12 @@ endgenerate
                 if(|snoop_request)begin
                     snoop_state <= SNOOP_REQUEST;
                     snoop_buffer.idx <= snoop_idx;
-                    snoop_buffer.target_slave <= snoop_entry.op != `ACEOP_MAKE_UNIQUE ? owner_decode : snoop_dir_info.slave;
-                    snoop_buffer.slave_request <= snoop_entry.op != `ACEOP_MAKE_UNIQUE ? owner_decode : snoop_dir_info.slave;
+                    snoop_buffer.target_slave <= snoop_op != `ACEOP_MAKE_UNIQUE ? owner_decode : snoop_dir_info.slave;
+                    snoop_buffer.slave_request <= snoop_op != `ACEOP_MAKE_UNIQUE ? owner_decode : snoop_dir_info.slave;
                     snoop_buffer.snoop_addr <= snoop_entry.paddr;
-                    snoop_buffer.op <= snoop_entry.op == `ACEOP_MAKE_UNIQUE ? `ACEOP_CLEAN_INVALID : snoop_entry.op;
+                    snoop_buffer.op <= snoop_op == `ACEOP_MAKE_UNIQUE ? `ACEOP_CLEAN_INVALID : snoop_op;
                     snoop_buffer.response <= 0;
-                    snoop_buffer.require_data <= snoop_entry.op != `ACEOP_MAKE_UNIQUE;
+                    snoop_buffer.require_data <= snoop_op != `ACEOP_MAKE_UNIQUE;
                     snoop_buffer.slave_replace <= snoop_replace_request[snoop_idx];
                     snoop_buffer.data_valid <= 0;
                     snoop_buffer.data_index <= 0;
@@ -731,11 +788,14 @@ endgenerate
 
 // to l3
     logic l3_req_last, l3_req_write, l3_req_write_end, l3_data_valid;
+    logic l3_read_once;
     logic `ARRAY(CACHE_BANK, CACHE_BITS) l3_data;
     logic `N(DATA_BANK) l3_data_bank, l3_write_data_bank;
     logic `N(MST_SNOOP_ID_WIDTH) mst_r_id;
     logic mst_r_ack;
+    logic `N(4) l3_op;
     OldestSelect #(MSHR_SIZE, 1, $bits(MSHREntry)) select_l3_entry (l3_requests, entrys, l3_request, l3_entry);
+    OldestSelect #(MSHR_SIZE, 1, 4) select_l3_op (l3_requests, dir_op, , l3_op);
     PSelector #(MSHR_SIZE) selector_l3_idx (l3_requests, l3_idx_dec);
     PEncoder #(MSHR_SIZE) encoder_l3_idx (l3_requests, l3_idx);
 
@@ -755,18 +815,19 @@ generate
                 mst_r_ack <= 0;
             end
             else begin
-                if((l3_state == L3_REQUEST) & l3_data_valid &
+                if((l3_state == L3_REQUEST) & l3_data_valid & l3_read_once &
                    (~replace_reqs[l3_buffer.idx] | replace_busy & 
                    replace_buffer.replace_data_valid & (replace_buffer.idx == l3_buffer.idx)))begin
                     l3_req_write <= 1'b1;
                 end
                 if(~(|(l3_data_bank & write_bank_req)) & l3_req_write)begin
                     l3_req_write <= 1'b0;
+                    l3_data_valid <= 1'b0;
                 end
                 if(l3_state == L3_IDLE && l3_request)begin
                     l3_req_write_end <= 1'b0;
                 end
-                else if(|l3_write_data_bank)begin
+                else if(|l3_write_data_bank | (l3_state == L3_REQUEST) & ~l3_read_once)begin
                     l3_req_write_end <= 1'b1;
                 end
                 if(master_io.r_valid & master_io.r_last)begin
@@ -777,9 +838,6 @@ generate
                 if(mst_r_ack)begin
                     mst_r_ack <= 1'b0;
                 end
-                else if(l3_state == L3_IDLE)begin
-                    l3_data_valid <= 1'b0;
-                end
             end
         end
 
@@ -794,9 +852,11 @@ endgenerate
             l3_state <= L3_IDLE;
             l3_req_last <= 1'b0;
             l3_buffer <= 0;
+            l3_read_once <= 1'b0;
         end
         else begin
-            if(dir_request_n & (~mshr_dir_io.hit & ~mshr_slave_io.hit | dir_make_unique & ~LLC) & 
+            if(dir_request_n & (~mshr_dir_io.hit & ~mshr_slave_io.hit & 
+            ~((dir_make_unique | dir_clean_unique_nodata) & LLC)) & 
               ~dir_entry_n.write & ~dir_clean_invalid)begin
                 l3_requests[dir_select_idx_n] <= 1'b1;
             end
@@ -804,12 +864,14 @@ endgenerate
             L3_IDLE: begin
                 if(l3_request)begin
                     l3_state <= L3_REQUEST;
-                    l3_buffer.idx <= l3_idx_dec;
+                    l3_buffer.idx <= l3_idx;
                     l3_buffer.addr <= l3_entry.paddr;
                     l3_buffer.request <= 1'b1;
                     l3_buffer.id <= l3_entry.id;
-                    l3_buffer.op <= l3_entry.op == `ACEOP_READ_ONCE ? `ACEOP_READ_SHARED : l3_entry.op;
+                    l3_buffer.op <= l3_op == `ACEOP_READ_ONCE ? `ACEOP_READ_SHARED : l3_op;
                     l3_buffer.data_index <= 0;
+                    l3_read_once <= l3_op == `ACEOP_READ_ONCE;
+                    l3_req_last <= 1'b0;
                 end
             end
             L3_REQUEST: begin
@@ -822,10 +884,11 @@ endgenerate
                 if(master_io.r_valid & master_io.r_last & ISL2)begin
                     l3_req_last <= 1'b1;
                 end
+                // if is l2 and req from icache, then we need to place data to data bank
                 if((master_io.r_valid & master_io.r_last | l3_req_last & ISL2) &
                    (~ISL2 | ISL2 & ~replace_reqs[l3_buffer.idx] & l3_req_write_end))begin
                     l3_state <= L3_IDLE;
-                    l3_requests[l3_idx] <= 1'b0;
+                    l3_requests[l3_buffer.idx] <= 1'b0;
                 end
             end
             endcase
@@ -835,8 +898,8 @@ endgenerate
     assign master_io.ar_valid = l3_buffer.request;
     assign master_io.ar_id = l3_buffer.id;
     assign master_io.ar_addr = l3_buffer.addr;
-    assign master_io.ar_len = DATA_BANK - 1;
-    assign master_io.ar_size = $clog2(`CACHELINE_SIZE / DATA_BANK);
+    assign master_io.ar_len = CACHE_BANK - 1;
+    assign master_io.ar_size = $clog2(`CACHELINE_SIZE / CACHE_BANK);
     assign master_io.ar_burst = 2'b01;
     assign master_io.ar_user = 0;
     assign master_io.ar_snoop = l3_buffer.op;
@@ -845,11 +908,6 @@ endgenerate
     assign mst_snoop_resp.rack = mst_r_ack;
 
 // write
-    logic `N(MSHR_SIZE) write_req, write_data_finish;
-    logic `N(MSHR_WIDTH) write_b_idx, write_data_finish_idx;
-    logic `ARRAY(MSHR_SIZE, ID_WIDTH) write_b_ids;
-    logic `N(ID_WIDTH) write_b_id;
-    logic write_b_req;
     always_ff @(posedge clk)begin
         if(slave_io.w_valid & slave_io.w_ready)begin
             write_buffer[write_idx][write_data_index] <= slave_io.w_data;
@@ -875,6 +933,8 @@ endgenerate
             write_b_idx <= 0;
             write_data_finish <= 0;
             write_b_ids <= 0;
+            entry_write <= 0;
+            write_finish <= 0;
         end
         else begin
             if(slave_io.aw_valid & slave_io.aw_ready)begin
@@ -883,11 +943,10 @@ endgenerate
                 write_id <= slave_io.aw_id[ID_OFFSET +: ID_WIDTH];
                 write_data_index <= 0;
                 write_req[free_idx1] <= 1'b1;
-                write_data_valid[free_idx1] <= 1'b0;
+                write_finish[free_idx1] <= 1'b0;
             end
-
-            if(dir_request_n & ~dir_entry_n.write)begin
-                write_data_valid[dir_select_idx_n] <= 1'b0;
+            if(dir_request_n)begin
+                entry_write[dir_select_idx_n] <= dir_entry_n.write;
             end
             
             if(slave_io.w_valid)begin
@@ -914,12 +973,16 @@ endgenerate
                 slave_b_valid <= 1'b0;
                 write_req[write_b_idx] <= 1'b0;
                 write_data_finish[write_b_idx] <= 1'b0;
+                write_finish[write_b_idx] <= 1'b1;
             end
 
             for(int i=0; i<DATA_BANK; i++)begin
                 if(mshr_data_io.wvalid[i] & (entrys[mshr_data_io.wmshr_idx_o[i]].write))begin
                     write_data_finish[mshr_data_io.wmshr_idx_o[i]] <= 1'b1;
                 end
+                if(write_bank_req[i])begin
+                    write_data_valid[write_bank_idx[i]] <= 1'b0;
+                end
             end
         end
     end
@@ -960,7 +1023,7 @@ generate
         Decoder #(DATA_BANK) decoder_l3_bank (l3_buffer.addr[OFFSET_WIDTH +: DATA_BANK_WIDTH], l3_data_bank);
     end
 
-    for(genvar i=0; i<DATA_BANK; i++)begin
+    for(genvar i=0; i<DATA_BANK; i++)begin : lookup
         logic `N(MSHR_SIZE) lookup_bank_request;
         logic `N(SET_WIDTH) lookup_data_addr;
         logic `N(WAY_WIDTH) lookup_way;
@@ -982,20 +1045,19 @@ generate
         assign mshr_data_io.mshr_idx = lookup_data_req[i] ? lookup_idx : replace_buffer.idx;
 
         logic `N(MSHR_SIZE) write_bank_requests;
-        logic `N(MSHR_WIDTH) write_bank_idx;
         logic `N(SET_WIDTH) write_addr;
         logic `N(WAY_WIDTH) write_way;
         logic `ARRAY(SLAVE_BANK, SLAVE_BITS) write_data;
         assign write_bank_requests = write_data_valid & (~replace_reqs | replace_data_valids) & lookup_bank_rev[i];
-        PEncoder #(MSHR_SIZE) encoder_write_bank_idx (write_bank_requests, write_bank_idx);
+        PEncoder #(MSHR_SIZE) encoder_write_bank_idx (write_bank_requests, write_bank_idx[i]);
         OldestSelect #(MSHR_SIZE, 1, SET_WIDTH) select_write_addr (write_bank_requests, lookup_addrs, write_bank_req[i], write_addr);
-        OldestSelect #(MSHR_SIZE, 1, SET_WIDTH) select_write_way (write_bank_requests, lookup_ways, , write_way);
-        assign write_data = write_buffer[write_bank_idx];
+        OldestSelect #(MSHR_SIZE, 1, WAY_WIDTH) select_write_way (write_bank_requests, lookup_ways, , write_way);
+        assign write_data = write_buffer[write_bank_idx[i]];
 
-        if(ISL2)begin
+        if(!ISL2)begin
             assign mshr_data_io.we[i] = write_bank_req[i];
             assign mshr_data_io.wway[i] = write_way;
-            assign mshr_data_io.wmshr_idx[i] = write_bank_idx;
+            assign mshr_data_io.wmshr_idx[i] = write_bank_idx[i];
             if(DATA_BANK == 1)begin
                 assign mshr_data_io.waddr[i] = write_addr;
             end
@@ -1007,7 +1069,7 @@ generate
         else begin
             assign mshr_data_io.we[i] = write_bank_req[i] | l3_req_write & l3_data_bank[i];
             assign mshr_data_io.wway[i] = write_bank_req[i] ? write_way : replace_ways[l3_buffer.idx];
-            assign mshr_data_io.wmshr_idx[i] = write_bank_req[i] ? write_bank_idx : l3_buffer.idx;
+            assign mshr_data_io.wmshr_idx[i] = write_bank_req[i] ? write_bank_idx[i] : l3_buffer.idx;
             if(DATA_BANK == 1)begin
                 assign mshr_data_io.waddr[i] = write_bank_req[i] ? write_addr : l3_buffer.addr[OFFSET_WIDTH +: SET_WIDTH];
             end
@@ -1100,7 +1162,7 @@ endgenerate
                 if(replace_req)begin
                     replace_busy <= 1'b1;
                     replace_buffer.aw_valid <= 1'b1;
-                    replace_buffer.addr <= {replace_tag[TAG_WIDTH: 1], replace_entry.paddr[TAG_WIDTH-1: 0]};
+                    replace_buffer.addr <= {replace_tag[TAG_WIDTH: 1], replace_entry.paddr[OFFSET_WIDTH +: SET_WIDTH], {OFFSET_WIDTH{1'b0}}};
                     replace_buffer.id <= replace_entry.id;
                     replace_buffer.dirty <= replace_tag[0];
                     replace_buffer.idx <= replace_idx;
@@ -1109,7 +1171,6 @@ endgenerate
                     replace_buffer.replace_data_valid <= 1'b0;
                     replace_buffer.data_index <= 0;
                     replace_read_req <= 1'b1;
-                    replace_data_valids[replace_idx] <= 1'b0;
                 end
             end
             else begin
@@ -1137,6 +1198,7 @@ endgenerate
                 if(master_io.b_valid & master_io.b_ready)begin
                     replace_busy <= 1'b0;
                     replace_reqs[replace_buffer.idx] <= 1'b0;
+                    replace_data_valids[replace_buffer.idx] <= 1'b0;
                 end
             end
         end
diff --git a/src/defines/bus/ace.svh b/src/defines/bus/ace.svh
index d4d33e0..bc8224e 100644
--- a/src/defines/bus/ace.svh
+++ b/src/defines/bus/ace.svh
@@ -167,14 +167,14 @@ interface SnoopIO #(
     input   ac_addr, ac_prot, ac_snoop, ac_valid, output ac_ready,
     input   cr_ready, output cr_valid, cr_resp,
     input   cd_ready, output cd_data, cd_last, cd_valid,
-    output ar_snoop_id, input r_snoop_id, rack
+    input ar_snoop_id, output r_snoop_id, rack
   );
 
   modport slave (
     output   ac_addr, ac_prot, ac_snoop, ac_valid, input ac_ready,
     output   cr_ready, input cr_valid, cr_resp,
     output   cd_ready, input cd_data, cd_last, cd_valid,
-    input ar_snoop_id, output r_snoop_id, rack
+    output ar_snoop_id, input r_snoop_id, rack
   );
 
 endinterface
@@ -470,10 +470,13 @@ endinterface
   `__SNOOP_TO_AC(__opt_as, __lhs.ac, __lhs_sep, __rhs.ac, __rhs_sep)      \
   __opt_as __lhs.ac_valid = __rhs.ac_valid;                               \
   __opt_as __lhs.cd_ready = __rhs.cd_ready;                               \
-  __opt_as __lhs.cr_ready = __rhs.cr_ready;
+  __opt_as __lhs.cr_ready = __rhs.cr_ready;                               \
+  __opt_as __lhs.ar_snoop_id = __rhs.ar_snoop_id;
 `define __SNOOP_TO_RESP(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep)     \
   __opt_as __lhs.ac_ready = __rhs.ac_ready;                               \
   __opt_as __lhs.cd_valid = __rhs.cd_valid;                               \
+  __opt_as __lhs.rack = __rhs.rack;                                       \
+  __opt_as __lhs.r_snoop_id  = __rhs.r_snoop_id;                          \
   `__SNOOP_TO_CD(__opt_as, __lhs.cd, __lhs_sep, __rhs.cd, __rhs_sep)      \
   __opt_as __lhs.cr_valid = __rhs.cr_valid;                               \
   __opt_as __lhs.cr_resp = __rhs.cr_resp;
diff --git a/src/defines/bus/mem.svh b/src/defines/bus/mem.svh
index 48f8257..689359b 100644
--- a/src/defines/bus/mem.svh
+++ b/src/defines/bus/mem.svh
@@ -260,7 +260,12 @@ endinterface //CacheBus
     assign axi_if.ar_size   = cache_if.ar_size; \
     assign axi_if.ar_burst  = cache_if.ar_burst; \
     assign axi_if.ar_user   = cache_if.ar_user; \
-    `__CACHE_TO_R(assign, cache_if.r, _, axi_if.r, _) \
+    assign cache_if.r_data = axi_if.r_data; \
+    assign cache_if.r_resp[4: 2] = 3'b001; \
+    assign cache_if.r_resp[1: 0] = axi_if.r_resp[1: 0]; \
+    assign cache_if.r_id = axi_if.r_id; \
+    assign cache_if.r_last = axi_if.r_last; \
+    assign cache_if.r_user = axi_if.r_user; \
     assign axi_if.aw_id     = cache_if.aw_id; \
     assign axi_if.aw_addr   = cache_if.aw_addr; \
     assign axi_if.aw_len    = cache_if.aw_len; \
diff --git a/src/defines/debug.svh b/src/defines/debug.svh
index c2a6b6c..db884c8 100644
--- a/src/defines/debug.svh
+++ b/src/defines/debug.svh
@@ -9,8 +9,8 @@
 // `define T_RAS
 // `define T_TAGE
 // `define T_BR_HIST
-// `define T_DCACHE
-// `define T_SCB
+`define T_DCACHE
+`define T_SCB
 // `define T_ICACHE
 // `define T_COMMIT
 
diff --git a/src/defines/interfaces.svh b/src/defines/interfaces.svh
index 4d834ac..3a3608a 100644
--- a/src/defines/interfaces.svh
+++ b/src/defines/interfaces.svh
@@ -869,7 +869,7 @@ interface L2MSHRSlaveIO #(
 
     logic we;
     logic wready;
-    logic `N(`PADDR_SIZE) waddr;
+    logic `N(SET_WIDTH) waddr;
     logic `N(WAY_WIDTH) wway;
     logic `N(ENTRY_SIZE) wdata;
 
@@ -897,7 +897,7 @@ interface L2MSHRDirIO #(
 
     logic we;
     logic wready;
-    logic `N(`PADDR_SIZE) waddr;
+    logic `N(SET_WIDTH) waddr;
     logic `N(WAY_WIDTH) wway;
     logic `N(TAG_WIDTH+1+$bits(DirectoryState)) wdata;
 
diff --git a/src/sim/SimTop.sv b/src/sim/SimTop.sv
index 7d0445e..a16894c 100644
--- a/src/sim/SimTop.sv
+++ b/src/sim/SimTop.sv
@@ -74,12 +74,15 @@ module SimTop(
     ) mem_axi();
     AxiIO #(
         `PADDR_SIZE, `XLEN, 2, 1
-    ) core_axi();
+    ) core_mem_axi();
     AxiIO #(
-        `PADDR_SIZE, `XLEN, 2, 1
+        `PADDR_SIZE, `XLEN, 1, 1
+    ) core_peri_axi();
+    AxiIO #(
+        `PADDR_SIZE, `XLEN, 1, 1
     ) peri_axi();
     AxiIO #(
-        `PADDR_SIZE, `XLEN, 2, 1
+        `PADDR_SIZE, `XLEN, 1, 1
     ) irq_axi();
 
     ClintIO clint_io();
@@ -89,14 +92,15 @@ module SimTop(
     CPUCore core(
         .clk(clock),
         .rst(core_rst),
-        .axi(core_axi.master),
+        .mem_axi(core_mem_axi.master),
+        .peri_axi(core_peri_axi.master),
         .clint_io(clint_io.cpu)
     );
     assign clint_io.meip = meip[0];
     assign clint_io.seip = seip[0];
 
 
-    localparam [2: 0] AXI_SLAVE_NUM = 3;
+    localparam [2: 0] AXI_SLAVE_NUM = 2;
     localparam xbar_cfg_t crossbar_cfg = '{
         NoSlvPorts: 1,
         NoMstPorts: AXI_SLAVE_NUM,
@@ -105,7 +109,7 @@ module SimTop(
         FallThrough: 0,
         LatencyMode: 10'b11111_11111,
         PipelineStages: 1,
-        AxiIdWidthSlvPorts: 2,
+        AxiIdWidthSlvPorts: 1,
         UniqueIds: 1,
         AxiAddrWidth: `PADDR_SIZE,
         AxiDataWidth: `XLEN,
@@ -114,7 +118,7 @@ module SimTop(
     };
     typedef logic [`PADDR_SIZE-1: 0] addr_t;
     typedef logic user_t;
-    typedef logic [1: 0] id_t;
+    typedef logic [0: 0] id_t;
     typedef logic [`XLEN-1: 0] data_t;
     typedef logic [`XLEN/8-1: 0] strb_t;
     `AXI_TYPEDEF_AW_CHAN_T(AxiAW, addr_t, id_t, user_t)
@@ -138,14 +142,12 @@ module SimTop(
     AxiResp `N(AXI_SLAVE_NUM) mst_resp_i;
     addr_rule_t `N(AXI_SLAVE_NUM) addr_map;
 
-    `AXI_ASSIGN_TO_REQ(slv_req_i, core_axi)
-    `AXI_ASSIGN_FROM_RESP(core_axi, slv_resp_o)
+    `AXI_ASSIGN_TO_REQ(slv_req_i, core_peri_axi)
+    `AXI_ASSIGN_FROM_RESP(core_peri_axi, slv_resp_o)
     `AXI_ASSIGN_FROM_REQ(peri_axi, mst_req_o[0])
     `AXI_ASSIGN_TO_RESP(mst_resp_i[0], peri_axi)
-    `AXI_ASSIGN_FROM_REQ(mem_axi, mst_req_o[1])
-    `AXI_ASSIGN_TO_RESP(mst_resp_i[1], mem_axi)
-    `AXI_ASSIGN_FROM_REQ(irq_axi, mst_req_o[2])
-    `AXI_ASSIGN_TO_RESP(mst_resp_i[2], irq_axi)
+    `AXI_ASSIGN_FROM_REQ(irq_axi, mst_req_o[1])
+    `AXI_ASSIGN_TO_RESP(mst_resp_i[1], irq_axi)
 
     assign addr_map[0] = '{
         idx: 0,
@@ -154,11 +156,6 @@ module SimTop(
     };
     assign addr_map[1] = '{
         idx: 1,
-        start_addr: `MEM_START,
-        end_addr: `MEM_END
-    };
-    assign addr_map[2] = '{
-        idx: 2,
         start_addr: `IRQ_START,
         end_addr: `IRQ_END
     };
@@ -216,7 +213,7 @@ module SimTop(
         .NoRules(2),
         .AxiAddrWidth(`PADDR_SIZE),
         .AxiDataWidth(`XLEN),
-        .AxiIdWidth(2),
+        .AxiIdWidth(1),
         .AxiUserWidth(1),
         .PipelineRequest(1),
         .PipelineResponse(1),
@@ -285,7 +282,7 @@ module SimTop(
         .NoRules(`PERIPHERAL_SIZE),
         .AxiAddrWidth(`PADDR_SIZE),
         .AxiDataWidth(`XLEN),
-        .AxiIdWidth(2),
+        .AxiIdWidth(1),
         .AxiUserWidth(1),
         .PipelineRequest(1),
         .PipelineResponse(1),
@@ -324,6 +321,39 @@ module SimTop(
         .io_uart_in_ch(io_uart_in_ch)
     );
 
+// mem
+    typedef logic [1: 0] mem_id_t;
+    `AXI_TYPEDEF_AW_CHAN_T(AxiMemAW, addr_t, mem_id_t, user_t)
+    `AXI_TYPEDEF_W_CHAN_T(AxiMemW, data_t, strb_t, user_t)
+    `AXI_TYPEDEF_B_CHAN_T(AxiMemB, mem_id_t, user_t)
+    `AXI_TYPEDEF_AR_CHAN_T(AxiMemAR, addr_t, mem_id_t, user_t)
+    `AXI_TYPEDEF_R_CHAN_T(AxiMemR, data_t, mem_id_t, user_t)
+    `AXI_TYPEDEF_REQ_T(AxiMemReq, AxiMemAW, AxiMemW, AxiMemAR)
+    `AXI_TYPEDEF_RESP_T(AxiMemResp, AxiMemB, AxiMemR)
+    AxiMemReq core_mem_req, mem_req;
+    AxiMemResp core_mem_resp, mem_resp;
+    `AXI_ASSIGN_TO_REQ(core_mem_req, core_mem_axi)
+    `AXI_ASSIGN_FROM_RESP(core_mem_axi, core_mem_resp)
+    `AXI_ASSIGN_FROM_REQ(mem_axi, mem_req)
+    `AXI_ASSIGN_TO_RESP(mem_resp, mem_axi)
+    axi_multicut #(
+        .NoCuts(1),
+        .aw_chan_t(AxiMemAW),
+        .w_chan_t(AxiMemW),
+        .b_chan_t(AxiMemB),
+        .ar_chan_t(AxiMemAR),
+        .r_chan_t(AxiMemR),
+        .axi_req_t(AxiMemReq),
+        .axi_resp_t(AxiMemResp)
+    ) mem_cut (
+        .clk_i(clock),
+        .rst_ni(~peri_rst),
+        .slv_req_i(core_mem_req),
+        .slv_resp_o(core_mem_resp),
+        .mst_req_o(mem_req),
+        .mst_resp_i(mem_resp)
+    );
+
 `ifdef DRAMSIM3
     assign mem_axi.aw_ready = io_memAXI_0_aw_ready;
     assign io_memAXI_0_aw_valid = mem_axi.aw_valid;
diff --git a/src/soc/Soc.sv b/src/soc/Soc.sv
index f9f06fa..5e75428 100644
--- a/src/soc/Soc.sv
+++ b/src/soc/Soc.sv
@@ -11,12 +11,15 @@ module Soc(
 );
     AxiIO #(
         `PADDR_SIZE, `XLEN, 2, 1
-    ) core_axi();
+    ) core_mem_axi();
     AxiIO #(
-        `PADDR_SIZE, `XLEN, 2, 1
+        `PADDR_SIZE, `XLEN, 1, 1
+    ) core_peri_axi();
+    AxiIO #(
+        `PADDR_SIZE, `XLEN, 1, 1
     ) peri_axi();
     AxiIO #(
-        `PADDR_SIZE, `XLEN, 2, 1
+        `PADDR_SIZE, `XLEN, 1, 1
     ) irq_axi();
 
     ClintIO clint_io();
@@ -38,9 +41,10 @@ module Soc(
     SyncRst rst_clint (clk, clint_rst_s1, clint_rst);
 
     CPUCore core(
-        .clk(clk),
+        .clk(clock),
         .rst(core_rst),
-        .axi(core_axi.master),
+        .mem_axi(core_mem_axi.master),
+        .peri_axi(core_peri_axi.master),
         .clint_io(clint_io.cpu)
     );
     assign clint_io.meip = meip[0];
@@ -56,7 +60,7 @@ module Soc(
         FallThrough: 0,
         LatencyMode: 10'b11111_11111,
         PipelineStages: 1,
-        AxiIdWidthSlvPorts: 2,
+        AxiIdWidthSlvPorts: 1,
         UniqueIds: 1,
         AxiAddrWidth: `PADDR_SIZE,
         AxiDataWidth: `XLEN,
@@ -65,7 +69,7 @@ module Soc(
     };
     typedef logic [`PADDR_SIZE-1: 0] addr_t;
     typedef logic user_t;
-    typedef logic [1: 0] id_t;
+    typedef logic [0: 0] id_t;
     typedef logic [`XLEN-1: 0] data_t;
     typedef logic [`XLEN/8-1: 0] strb_t;
     `AXI_TYPEDEF_AW_CHAN_T(AxiAW, addr_t, id_t, user_t)
@@ -89,8 +93,8 @@ module Soc(
     AxiResp `N(AXI_SLAVE_NUM) mst_resp_i;
     addr_rule_t `N(AXI_SLAVE_NUM) addr_map;
 
-    `AXI_ASSIGN_TO_REQ(slv_req_i, core_axi)
-    `AXI_ASSIGN_FROM_RESP(core_axi, slv_resp_o)
+    `AXI_ASSIGN_TO_REQ(slv_req_i, core_peri_axi)
+    `AXI_ASSIGN_FROM_RESP(core_peri_axi, slv_resp_o)
     `AXI_ASSIGN_FROM_REQ(peri_axi, mst_req_o[0])
     `AXI_ASSIGN_TO_RESP(mst_resp_i[0], peri_axi)
     `AXI_ASSIGN_FROM_REQ(irq_axi, mst_req_o[1])
@@ -160,7 +164,7 @@ module Soc(
         .NoRules(2),
         .AxiAddrWidth(`PADDR_SIZE),
         .AxiDataWidth(`XLEN),
-        .AxiIdWidth(2),
+        .AxiIdWidth(1),
         .AxiUserWidth(1),
         .PipelineRequest(1),
         .PipelineResponse(1),
@@ -232,7 +236,7 @@ module Soc(
         .AxiDataWidth(`XLEN),
         .PipelineRequest(1),
         .PipelineResponse(1),
-        .AxiIdWidth(2),
+        .AxiIdWidth(1),
         .AxiUserWidth(1),
         .AxiMaxWriteTxns((`NUM_CORE < 2 ? 2 : `NUM_CORE)),
         .AxiMaxReadTxns((`NUM_CORE < 2 ? 2 : `NUM_CORE)),
diff --git a/src/utils/axi/axi_convert/LICENSE b/src/utils/axi/LICENSE
similarity index 100%
rename from src/utils/axi/axi_convert/LICENSE
rename to src/utils/axi/LICENSE
diff --git a/src/utils/axi/axi_convert/ace_trs_dec.sv b/src/utils/axi/ace_trs_dec.sv
similarity index 100%
rename from src/utils/axi/axi_convert/ace_trs_dec.sv
rename to src/utils/axi/ace_trs_dec.sv
diff --git a/src/utils/axi/axi_convert/addr_decode.sv b/src/utils/axi/addr_decode.sv
similarity index 100%
rename from src/utils/axi/axi_convert/addr_decode.sv
rename to src/utils/axi/addr_decode.sv
diff --git a/src/utils/axi/axi_convert/addr_decode_dync.sv b/src/utils/axi/addr_decode_dync.sv
similarity index 100%
rename from src/utils/axi/axi_convert/addr_decode_dync.sv
rename to src/utils/axi/addr_decode_dync.sv
diff --git a/src/utils/axi/axi_convert/axi_atop_filter.sv b/src/utils/axi/axi_atop_filter.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_atop_filter.sv
rename to src/utils/axi/axi_atop_filter.sv
diff --git a/src/utils/axi/axi_convert/axi_burst_splitter.sv b/src/utils/axi/axi_burst_splitter.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_burst_splitter.sv
rename to src/utils/axi/axi_burst_splitter.sv
diff --git a/src/utils/axi/axi_convert/axi_cdc.sv b/src/utils/axi/axi_cdc.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_cdc.sv
rename to src/utils/axi/axi_cdc.sv
diff --git a/src/utils/axi/axi_convert/axi_cdc_dst.sv b/src/utils/axi/axi_cdc_dst.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_cdc_dst.sv
rename to src/utils/axi/axi_cdc_dst.sv
diff --git a/src/utils/axi/axi_convert/axi_cdc_src.sv b/src/utils/axi/axi_cdc_src.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_cdc_src.sv
rename to src/utils/axi/axi_cdc_src.sv
diff --git a/src/utils/axi/axi_convert/axi_cut.sv b/src/utils/axi/axi_cut.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_cut.sv
rename to src/utils/axi/axi_cut.sv
diff --git a/src/utils/axi/axi_convert/axi_demux.sv b/src/utils/axi/axi_demux.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_demux.sv
rename to src/utils/axi/axi_demux.sv
diff --git a/src/utils/axi/axi_convert/axi_demux_simple.sv b/src/utils/axi/axi_demux_simple.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_demux_simple.sv
rename to src/utils/axi/axi_demux_simple.sv
diff --git a/src/utils/axi/axi_convert/axi_err_slv.sv b/src/utils/axi/axi_err_slv.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_err_slv.sv
rename to src/utils/axi/axi_err_slv.sv
diff --git a/src/utils/axi/axi_convert/axi_id_prepend.sv b/src/utils/axi/axi_id_prepend.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_id_prepend.sv
rename to src/utils/axi/axi_id_prepend.sv
diff --git a/src/utils/axi/axi_convert/axi_lite_to_apb.sv b/src/utils/axi/axi_lite_to_apb.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_lite_to_apb.sv
rename to src/utils/axi/axi_lite_to_apb.sv
diff --git a/src/utils/axi/axi_convert/axi_multicut.sv b/src/utils/axi/axi_multicut.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_multicut.sv
rename to src/utils/axi/axi_multicut.sv
diff --git a/src/utils/axi/axi_convert/axi_mux.sv b/src/utils/axi/axi_mux.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_mux.sv
rename to src/utils/axi/axi_mux.sv
diff --git a/src/utils/axi/axi_convert/axi_to_apb.sv b/src/utils/axi/axi_to_apb.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_to_apb.sv
rename to src/utils/axi/axi_to_apb.sv
diff --git a/src/utils/axi/axi_convert/axi_to_axi_lite.sv b/src/utils/axi/axi_to_axi_lite.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_to_axi_lite.sv
rename to src/utils/axi/axi_to_axi_lite.sv
diff --git a/src/utils/axi/axi_convert/axi_xbar.sv b/src/utils/axi/axi_xbar.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_xbar.sv
rename to src/utils/axi/axi_xbar.sv
diff --git a/src/utils/axi/axi_convert/axi_xbar_unmuxed.sv b/src/utils/axi/axi_xbar_unmuxed.sv
similarity index 100%
rename from src/utils/axi/axi_convert/axi_xbar_unmuxed.sv
rename to src/utils/axi/axi_xbar_unmuxed.sv
diff --git a/src/utils/axi/axi_convert/binary_to_gray.sv b/src/utils/axi/binary_to_gray.sv
similarity index 100%
rename from src/utils/axi/axi_convert/binary_to_gray.sv
rename to src/utils/axi/binary_to_gray.sv
diff --git a/src/utils/axi/axi_convert/ccu_fsm.sv b/src/utils/axi/ccu_fsm.sv
similarity index 100%
rename from src/utils/axi/axi_convert/ccu_fsm.sv
rename to src/utils/axi/ccu_fsm.sv
diff --git a/src/utils/axi/axi_convert/cdc_fifo_gray.sv b/src/utils/axi/cdc_fifo_gray.sv
similarity index 100%
rename from src/utils/axi/axi_convert/cdc_fifo_gray.sv
rename to src/utils/axi/cdc_fifo_gray.sv
diff --git a/src/utils/axi/axi_convert/counter.sv b/src/utils/axi/counter.sv
similarity index 100%
rename from src/utils/axi/axi_convert/counter.sv
rename to src/utils/axi/counter.sv
diff --git a/src/utils/axi/axi_convert/delta_counter.sv b/src/utils/axi/delta_counter.sv
similarity index 100%
rename from src/utils/axi/axi_convert/delta_counter.sv
rename to src/utils/axi/delta_counter.sv
diff --git a/src/utils/axi/axi_convert/fall_through_register.sv b/src/utils/axi/fall_through_register.sv
similarity index 100%
rename from src/utils/axi/axi_convert/fall_through_register.sv
rename to src/utils/axi/fall_through_register.sv
diff --git a/src/utils/axi/axi_convert/fifo_v3.sv b/src/utils/axi/fifo_v3.sv
similarity index 100%
rename from src/utils/axi/axi_convert/fifo_v3.sv
rename to src/utils/axi/fifo_v3.sv
diff --git a/src/utils/axi/axi_convert/gray_to_binary.sv b/src/utils/axi/gray_to_binary.sv
similarity index 100%
rename from src/utils/axi/axi_convert/gray_to_binary.sv
rename to src/utils/axi/gray_to_binary.sv
diff --git a/src/utils/axi/axi_convert/id_queue.sv b/src/utils/axi/id_queue.sv
similarity index 100%
rename from src/utils/axi/axi_convert/id_queue.sv
rename to src/utils/axi/id_queue.sv
diff --git a/src/utils/axi/axi_convert/onehot_to_bin.sv b/src/utils/axi/onehot_to_bin.sv
similarity index 100%
rename from src/utils/axi/axi_convert/onehot_to_bin.sv
rename to src/utils/axi/onehot_to_bin.sv
diff --git a/src/utils/axi/axi_convert/rr_arb_tree.sv b/src/utils/axi/rr_arb_tree.sv
similarity index 100%
rename from src/utils/axi/axi_convert/rr_arb_tree.sv
rename to src/utils/axi/rr_arb_tree.sv
diff --git a/src/utils/axi/snoop_cut.sv b/src/utils/axi/snoop_cut.sv
new file mode 100644
index 0000000..16ea823
--- /dev/null
+++ b/src/utils/axi/snoop_cut.sv
@@ -0,0 +1,144 @@
+module snoop_cut #(
+    parameter bit Bypass = 1'b0,
+    parameter type ac_chan_t = logic,
+    parameter type cr_chan_t = logic,
+    parameter type cd_chan_t = logic,
+    parameter type snoop_id_t = logic,
+    parameter type req_t = logic,
+    parameter type resp_t = logic
+)(
+    input logic clk_i,
+    input logic rst_ni,
+    input req_t slv_req_i,
+    output resp_t slv_resp_o,
+    output req_t mst_req_o,
+    input resp_t mst_resp_i
+);
+  spill_register #(
+    .T       ( ac_chan_t ),
+    .Bypass  ( Bypass    )
+  ) i_reg_ac (
+    .clk_i   ( clk_i               ),
+    .rst_ni  ( rst_ni              ),
+    .valid_i ( slv_req_i.ac_valid  ),
+    .ready_o ( slv_resp_o.ac_ready ),
+    .data_i  ( slv_req_i.ac        ),
+    .valid_o ( mst_req_o.ac_valid  ),
+    .ready_i ( mst_resp_i.ac_ready ),
+    .data_o  ( mst_req_o.ac        )
+  );
+  
+  spill_register #(
+    .T       ( cr_chan_t ),
+    .Bypass  ( Bypass    )
+  ) i_reg_cr (
+    .clk_i   ( clk_i               ),
+    .rst_ni  ( rst_ni              ),
+    .valid_i ( mst_resp_i.cr_valid  ),
+    .ready_o ( mst_req_o.cr_ready ),
+    .data_i  ( mst_resp_i.cr_resp        ),
+    .valid_o ( slv_resp_o.cr_valid  ),
+    .ready_i ( slv_req_i.cr_ready ),
+    .data_o  ( slv_resp_o.cr_resp        )
+  );
+  
+  spill_register #(
+    .T       ( cd_chan_t ),
+    .Bypass  ( Bypass    )
+  ) i_reg_cd (
+    .clk_i   ( clk_i               ),
+    .rst_ni  ( rst_ni              ),
+    .valid_i ( mst_resp_i.cd_valid  ),
+    .ready_o ( mst_req_o.cd_ready ),
+    .data_i  ( mst_resp_i.cd        ),
+    .valid_o ( slv_resp_o.cd_valid  ),
+    .ready_i ( slv_req_i.cd_ready ),
+    .data_o  ( slv_resp_o.cd        )
+  );
+
+generate
+    if(Bypass)begin
+        assign mst_req_o.ar_snoop_id = slv_req_i.ar_snoop_id;
+        assign slv_resp_o.r_snoop_id = mst_resp_i.r_snoop_id;
+        assign slv_resp_o.rack = mst_resp_i.rack;
+    end
+    else begin
+        snoop_id_t ar_snoop_id, r_snoop_id;
+        logic rack;
+        always_ff @(posedge clk_i, negedge rst_ni) begin
+            if(~rst_ni)begin
+                ar_snoop_id <= 0;
+                r_snoop_id <= 0;
+                rack <= 0;
+            end
+            else begin
+                ar_snoop_id <= slv_req_i.ar_snoop_id;
+                r_snoop_id <= mst_resp_i.r_snoop_id;
+                rack <= mst_resp_i.rack;
+            end
+        end
+        assign mst_req_o.ar_snoop_id = ar_snoop_id;
+        assign slv_resp_o.r_snoop_id = r_snoop_id;
+        assign slv_resp_o.rack = rack;
+    end
+endgenerate
+
+endmodule
+
+module snoop_multicut #(
+    parameter int unsigned NoCuts = 32'd1,
+    parameter type ac_chan_t = logic,
+    parameter type cr_chan_t = logic,
+    parameter type cd_chan_t = logic,
+    parameter type snoop_id_t = logic,
+    parameter type req_t = logic,
+    parameter type resp_t = logic
+)(
+  input  logic      clk_i,   // Clock
+  input  logic      rst_ni,  // Asynchronous reset active low
+  // slave port
+  input  req_t  slv_req_i,
+  output resp_t slv_resp_o,
+  // master port
+  output req_t  mst_req_o,
+  input  resp_t mst_resp_i
+);
+generate
+    if(NoCuts == '0)begin
+        assign mst_req_o  = slv_req_i;
+        assign slv_resp_o = mst_resp_i;
+    end
+    else begin
+        req_t  [NoCuts:0] cut_req;
+        resp_t [NoCuts:0] cut_resp;
+
+        // connect slave to the lowest index
+        assign cut_req[0] = slv_req_i;
+        assign slv_resp_o = cut_resp[0];
+
+        // AXI cuts
+        for (genvar i = 0; i < NoCuts; i++) begin : gen_snoop_cuts
+        snoop_cut #(
+            .Bypass     (       1'b0 ),
+            .ac_chan_t  (  ac_chan_t ),
+            .cr_chan_t   (   cr_chan_t ),
+            .cd_chan_t   (   cd_chan_t ),
+            .snoop_id_t ( snoop_id_t ),
+            .req_t       (    req_t ),
+            .resp_t      (  resp_t )
+        ) i_cut (
+            .clk_i,
+            .rst_ni,
+            .slv_req_i  ( cut_req[i]    ),
+            .slv_resp_o ( cut_resp[i]   ),
+            .mst_req_o  ( cut_req[i+1]  ),
+            .mst_resp_i ( cut_resp[i+1] )
+        );
+        end
+
+        // connect master to the highest index
+        assign mst_req_o        = cut_req[NoCuts];
+        assign cut_resp[NoCuts] = mst_resp_i;
+    end
+endgenerate
+endmodule
\ No newline at end of file
diff --git a/src/utils/axi/axi_convert/spill_register.sv b/src/utils/axi/spill_register.sv
similarity index 100%
rename from src/utils/axi/axi_convert/spill_register.sv
rename to src/utils/axi/spill_register.sv
diff --git a/src/utils/axi/axi_convert/spill_register_flushable.sv b/src/utils/axi/spill_register_flushable.sv
similarity index 100%
rename from src/utils/axi/axi_convert/spill_register_flushable.sv
rename to src/utils/axi/spill_register_flushable.sv
diff --git a/src/utils/axi/axi_convert/stream_register.sv b/src/utils/axi/stream_register.sv
similarity index 100%
rename from src/utils/axi/axi_convert/stream_register.sv
rename to src/utils/axi/stream_register.sv
diff --git a/src/utils/axi/axi_convert/sync.sv b/src/utils/axi/sync.sv
similarity index 100%
rename from src/utils/axi/axi_convert/sync.sv
rename to src/utils/axi/sync.sv
diff --git a/src/utils/utils.sv b/src/utils/utils.sv
index 7339aaa..9521d3c 100644
--- a/src/utils/utils.sv
+++ b/src/utils/utils.sv
@@ -264,7 +264,8 @@ endmodule
 module OldestSelect #(
 	parameter RADIX = 2,
 	parameter WIDTH = 4,
-	parameter DATA_WIDTH = 4
+	parameter DATA_WIDTH = 4,
+	parameter DIRECTION = 0
 )(
 	input logic [RADIX-1: 0][WIDTH-1: 0] cmp,
 	input logic [RADIX-1: 0][DATA_WIDTH-1: 0] data_i,
@@ -279,7 +280,12 @@ generate
 	else if(RADIX == 2)begin
 		if(WIDTH == 1)begin
 			assign cmp_o = cmp[1] | cmp[0];
-			assign data_o = cmp[1] ? data_i[1] : data_i[0];
+			if (DIRECTION == 1)begin
+				assign data_o = cmp[0] ? data_i[0] : data_i[1];
+			end
+			else begin
+				assign data_o = cmp[1] ? data_i[1] : data_i[0];
+			end
 		end
 		else begin
 			assign cmp_o = cmp[1] > cmp[0] ? cmp[1] : cmp[0];
@@ -292,7 +298,8 @@ generate
 		OldestSelect #(
 			.RADIX(RADIX/2),
 			.WIDTH(WIDTH),
-			.DATA_WIDTH(DATA_WIDTH)
+			.DATA_WIDTH(DATA_WIDTH),
+			.DIRECTION(DIRECTION)
 		) select1 (
 			.cmp(cmp[RADIX/2-1: 0]),
 			.data_i(data_i[RADIX/2-1: 0]),
@@ -302,7 +309,8 @@ generate
 		OldestSelect #(
 			.RADIX(RADIX-RADIX/2),
 			.WIDTH(WIDTH),
-			.DATA_WIDTH(DATA_WIDTH)
+			.DATA_WIDTH(DATA_WIDTH),
+			.DIRECTION(DIRECTION)
 		) select2 (
 			.cmp(cmp[RADIX-1: RADIX/2]),
 			.data_i(data_i[RADIX-1: RADIX/2]),
@@ -311,7 +319,12 @@ generate
 		);
 		if(WIDTH == 1)begin
 			assign cmp_o = cmp1 | cmp2;
-			assign data_o = cmp2 ? data2 : data1;
+			if(DIRECTION == 1)begin
+				assign data_o = cmp1 ? data1 : data2;
+			end
+			else begin
+				assign data_o = cmp2 ? data2 : data1;
+			end
 		end
 		else begin
 			assign cmp_o = cmp2 > cmp1 ? cmp2 : cmp1;