Buttons and clock on XDC Constraints

[jay20162016]

I recently set up my board and got a LED to light up via vivado. However, I cannot find any buttons in the XDC. Adding the following doesn't work, Cannot set LOC property of ports:

##BUTTONS
set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { buttonR }];  
set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { buttonL }]; 

Additionally, I have the board without the crystal soldered on. Is there a easy way to create a clock for my logic?

Any help would be appreciated. Thanks in advance!

[DavidJRichards]

Greetings Jay,

The chip pins connected to the button(s) are not accessible by the PL, they connect to the PS only. All of the connections brought out onto the three expansions connectors are available to use in the PL side. In addition the fan connectors each have two pins connected to the PL. Sadly many pins of the PL are not available to use on the ebaz4205 as they are not connected to anything at all.

To enable the ethernet clock you can add a 25MHz output from the fabric clock section of the PS7 configuration and output it to pin U18 which is connected to the phi clock input.

A starting point for a PS7 configuration for the ebaz4205 can be found here: https://github.com/nightseas/ebit_z7010

Kind regards, David.

[nic3-14159]

The PS (the ARM processing cores) provides clock signals that can be used in the PL (the FPGA logic). There are a few ways to use them, but the easiest is probably using the block design feature in Vivado. I found a tutorial that goes over how to use those clocks to produce a 1Hz square wave:
https://numato.com/kb/styx-use-xilinx-zynq-ps-pll-clocks-fpga-fabric/

Some notes about that tutorial after testing it with my board:

• If you are on a more recent version of Vivado, the Processing System will have a port called "M_AXI_GP0_ACLK", which needs to be connected to a clock source. At Step 9, you can just connect that pin to FCLK_CLK0.
• In Step 11, "sq_wave" needs to be changed to "sq_wave_0", which is what newer versions of Vivado name the pin after the "make external" part in Step 9. I also changed the PACKAGE_PIN to W13, which is the green LED between the button and the ethernet port.
• The steps from 13 onwards are only if you want to change the frequency of FCLK_CLK0. It also might be outdated, as it references the Xilinx SDK, which has been replaced by Xilinx Vitis from version 2019.2 onwards. I believe from previous testing that FCLK_CLK0 is set to 125MHz by the original image on the NAND of the EBAZ4205 board, whereas that tutorial assumes a 100MHz clock