Add support for TLB with different page size

[siyuanchai1999]

Now TLB in simulator-radix branch only supports 4KB granularity.
In real CPU, TLB have separate entries for 4KB, 2MB, and 1GB pages. Example configuration: ECPT ASPLOS 2020 paper Table 2

• Add configuration knob for size and associativity of 4KB 2MB, and 1GB pages
• Change TLB initialization: https://github.com/xlab-uiuc/dynamorio/blob/e67cec300842d7b134db6f4bafda6486e6bc4cea/clients/drcachesim/simulator/cache_simulator.cpp#L117C5-L117C12
• Check and fill TLB entries in order of granularity:

  dynamorio/clients/drcachesim/simulator/cache_simulator.cpp

  Line 839 in e67cec3

  std::pair<bool, bool> res = tlb_sim->process_memref_tlb(memref);

  
  Note: TLB for huge page can only be filled if the walk leads to a huge page.
  Note: Also have to apply changes to ECPT after done with radix