App PLL magic values

[xross]

Ideally defines such as

lib_sw_pll/lib_sw_pll/src/sw_pll_common.c

Line 63 in 321c7ce

#define APP_PLL_CTL_24M 0x0A006500

Would be built up from the required values using macros such as:

#define XS1_SS_FRAC_N_PERIOD_CYC_CNT_SHIFT 0x0
#define XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SHIFT 0x8
#define XS1_SS_FRAC_N_ENABLE_SHIFT 0x1f

etc.

This would go some way for the code to self document, also means code should work on future device if bits are moved around in registers.

Also, it would be nice if these values were exposed in a header (rather than internal c file) such that other code can inspect/use. For example, the feedback code in USB Audio.

[xross]

Looks like someone started trying to tidy up in sw_usb_audio: https://github.com/xmos/sw_usb_audio/blob/5978e3b8b8886f0003941c5885739f2b5628773e/app_usb_aud_xk_evk_xu316/src/extensions/audiohw.xc#L33

[ed-xmos]

Agree this should be improved. These values are obtained from pll_calc.py and so it would make sense for this script to generate the broken down bitfields since it has awareness of these values anyway.

lib_sw_pll/python/sw_pll/pll_calc.py

Line 62 in 4f6e932

app_pll_ctl_reg = (1 << 27) | (((op_div)-1) << 23) | ((int(fb_div[0])-1) << 8) | (ref_div-1)