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tx_done，tx_state需要被引出到外层模块 #3

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wujingbang opened this issue Jul 2, 2016 · 1 comment
Open

tx_done，tx_state需要被引出到外层模块 #3

wujingbang opened this issue Jul 2, 2016 · 1 comment

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@wujingbang
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这是一个奇怪的问题，起因是持续发送数据会频繁的触发tx超时导致重启。逻辑分析仪发现问题为有时候TX发送中断后tx_done没有置位；或是中断入口判断tx_state（短包版本）不为“TX”状态（异常）。注：tx_state判断在长包版本中已经移到了判断FIFO中断，没有引出tx_state前发现有未知错误出现（修改完竞争问题后），引出后问题消失。

猜测是综合器优化产生的速度问题。
@wujingbang
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Current_State lines of SRAM_ctrl should be wired out

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