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student_projects.md

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MYTH RISC-V (RV32I) CPU Cores

Many students who have taken part in this MYTH Workshop have released their work as open-source cores. These are some good ones:

These cores are significant in that:

  • They were created by students with limited logic design experience in a 5-day Workshop.
  • They implement a 4-stage pipelined RV32I in < 200 lines of code.
  • They are documented to help others create cores of their own.

All these cores can be compiled and simulated by cut-n-pasting into the makerchip.com IDE.

Workshop info, including slides.