ecu2.ptf

SYSTEM sp
{
   System_Wizard_Version = "9.00";
   System_Wizard_Build = "132";
   Builder_Application = "sopc_builder_ca";
   WIZARD_SCRIPT_ARGUMENTS 
   {
      hdl_language = "verilog";
      device_family = "STRATIXIIGX";
      device_family_id = "STRATIXIIGX";
      generate_sdk = "0";
      do_build_sim = "0";
      hardcopy_compatible = "0";
      CLOCKS 
      {
         CLOCK spclk
         {
            frequency = "100000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "spclk";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "spclk.clk";
         }
         CLOCK clk_50MHz
         {
            frequency = "50000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "clk_50MHz";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "clk_50MHz.clk";
         }
         CLOCK usb_hr_clk
         {
            frequency = "60000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "usb_hr_clk";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "usb_hr_clk.clk";
         }
         CLOCK usb_hc_0_clk
         {
            frequency = "60000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "usb_hc_0_clk";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "usb_hc_0_clk.clk";
         }
         CLOCK usb_hc_1_clk
         {
            frequency = "60000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "usb_hc_1_clk";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "usb_hc_1_clk.clk";
         }
      }
      clock_freq = "100000000";
      clock_freq = "100000000";
      board_class = "";
      view_master_columns = "1";
      view_master_priorities = "0";
      generate_hdl = "";
      bustype_column_width = "0";
      clock_column_width = "80";
      name_column_width = "75";
      desc_column_width = "75";
      base_column_width = "75";
      end_column_width = "75";
      BOARD_INFO 
      {
         altera_avalon_cfi_flash 
         {
            reference_designators = "";
         }
      }
      do_log_history = "0";
   }
   MODULE cpu
   {
      MASTER instruction_master
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT i_address
            {
               type = "address";
               width = "28";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT i_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT i_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT i_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT i_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "28";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "";
            Linewrap_Bursts = "";
            Burst_On_Burst_Boundaries_Only = "";
            Always_Burst_Max_Burst = "";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Address_Group = "0";
            Has_IRQ = "0";
            Irq_Scheme = "individual_requests";
            Interrupt_Range = "0-0";
         }
         MEMORY_MAP 
         {
            Entry pipeline_bridge/s1
            {
               address = "0x0c000000";
               span = "0x04000000";
               is_bridge = "1";
            }
            Entry sysid/control_slave
            {
               address = "0x0e001300";
               span = "0x00000008";
               is_bridge = "0";
            }
            Entry cpu/jtag_debug_module
            {
               address = "0x0e000000";
               span = "0x00000800";
               is_bridge = "0";
            }
            Entry jtag_uart/avalon_jtag_slave
            {
               address = "0x0e001340";
               span = "0x00000008";
               is_bridge = "0";
            }
            Entry cfi_flash/s1
            {
               address = "0x0c000000";
               span = "0x02000000";
               is_bridge = "0";
            }
            Entry timer/s1
            {
               address = "0x0e001100";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry sgdma_tx/csr
            {
               address = "0x0e000800";
               span = "0x00000400";
               is_bridge = "0";
            }
            Entry sgdma_rx/csr
            {
               address = "0x0e000c00";
               span = "0x00000400";
               is_bridge = "0";
            }
            Entry int_i2c/avalon_slave_0
            {
               address = "0x0e001380";
               span = "0x00000008";
               is_bridge = "0";
            }
            Entry ds1822/s1
            {
               address = "0x0e001800";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry rs232_uart/s1
            {
               address = "0x0e001000";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry i2c_sensor_sel_pio/s1
            {
               address = "0x0e001600";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry remote_uart/s1
            {
               address = "0x0e001020";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry rs232_dbg_uart/s1
            {
               address = "0x0e001040";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hc_pio_0/s1
            {
               address = "0x0e001060";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry hc_pio_1/s1
            {
               address = "0x0e001070";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      MASTER custom_instruction_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "8";
            Is_Custom_Instruction = "1";
            Is_Enabled = "0";
            Max_Address_Width = "8";
            Base_Address = "N/A";
            Is_Visible = "0";
         }
         PORT_WIRING 
         {
            PORT dataa
            {
               type = "dataa";
               width = "32";
               direction = "output";
            }
            PORT datab
            {
               type = "datab";
               width = "32";
               direction = "output";
            }
            PORT result
            {
               type = "result";
               width = "32";
               direction = "input";
            }
            PORT clk_en
            {
               type = "clk_en";
               width = "1";
               direction = "output";
            }
            PORT reset
            {
               type = "reset";
               width = "1";
               direction = "output";
            }
            PORT start
            {
               type = "start";
               width = "1";
               direction = "output";
            }
            PORT done
            {
               type = "done";
               width = "1";
               direction = "input";
            }
            PORT n
            {
               type = "n";
               width = "8";
               direction = "output";
            }
            PORT a
            {
               type = "a";
               width = "5";
               direction = "output";
            }
            PORT b
            {
               type = "b";
               width = "5";
               direction = "output";
            }
            PORT c
            {
               type = "c";
               width = "5";
               direction = "output";
            }
            PORT readra
            {
               type = "readra";
               width = "1";
               direction = "output";
            }
            PORT readrb
            {
               type = "readrb";
               width = "1";
               direction = "output";
            }
            PORT writerc
            {
               type = "writerc";
               width = "1";
               direction = "output";
            }
         }
      }
      SLAVE jtag_debug_module
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "2048";
            Read_Latency = "0";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "9";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Accepts_External_Connections = "1";
            Requires_Internal_Connections = "";
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02000000";
            }
            Base_Address = "0x0e000000";
            Is_Readable = "1";
            Is_Writeable = "1";
            Uses_Tri_State_Data_Bus = "0";
            Has_IRQ = "0";
            JTAG_Hub_Base_Id = "1118278";
            JTAG_Hub_Instance_Id = "0";
            Address_Group = "0";
         }
         PORT_WIRING 
         {
            PORT jtag_debug_module_address
            {
               type = "address";
               width = "9";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_begintransfer
            {
               type = "begintransfer";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_debugaccess
            {
               type = "debugaccess";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_resetrequest
            {
               type = "resetrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_select
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT jtag_debug_module_reset
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
      }
      MASTER data_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Irq_Scheme = "individual_requests";
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "28";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Is_Data_Master = "1";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writeable = "1";
            Interrupt_Range = "0-31";
         }
         PORT_WIRING 
         {
            PORT d_irq
            {
               type = "irq";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_address
            {
               type = "address";
               width = "28";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_debugaccess_to_roms
            {
               type = "debugaccess";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sgdma_m2s_ch1/csr
            {
               address = "0x08000000";
               span = "0x00000400";
               is_bridge = "0";
            }
            Entry sgdma_s2m_ch1/csr
            {
               address = "0x08000400";
               span = "0x00000400";
               is_bridge = "0";
            }
            Entry sgdma_m2s_ch2/csr
            {
               address = "0x08000800";
               span = "0x00000400";
               is_bridge = "0";
            }
            Entry sgdma_s2m_ch2/csr
            {
               address = "0x08000c00";
               span = "0x00000400";
               is_bridge = "0";
            }
            Entry pipeline_bridge/s1
            {
               address = "0x0c000000";
               span = "0x04000000";
               is_bridge = "1";
            }
            Entry sysid/control_slave
            {
               address = "0x0e001300";
               span = "0x00000008";
               is_bridge = "0";
            }
            Entry cpu/jtag_debug_module
            {
               address = "0x0e000000";
               span = "0x00000800";
               is_bridge = "0";
            }
            Entry jtag_uart/avalon_jtag_slave
            {
               address = "0x0e001340";
               span = "0x00000008";
               is_bridge = "0";
            }
            Entry cfi_flash/s1
            {
               address = "0x0c000000";
               span = "0x02000000";
               is_bridge = "0";
            }
            Entry timer/s1
            {
               address = "0x0e001100";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry sgdma_tx/csr
            {
               address = "0x0e000800";
               span = "0x00000400";
               is_bridge = "0";
            }
            Entry sgdma_rx/csr
            {
               address = "0x0e000c00";
               span = "0x00000400";
               is_bridge = "0";
            }
            Entry int_i2c/avalon_slave_0
            {
               address = "0x0e001380";
               span = "0x00000008";
               is_bridge = "0";
            }
            Entry ds1822/s1
            {
               address = "0x0e001800";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry rs232_uart/s1
            {
               address = "0x0e001000";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry i2c_sensor_sel_pio/s1
            {
               address = "0x0e001600";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry remote_uart/s1
            {
               address = "0x0e001020";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry rs232_dbg_uart/s1
            {
               address = "0x0e001040";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hc_pio_0/s1
            {
               address = "0x0e001060";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry hc_pio_1/s1
            {
               address = "0x0e001070";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry tse_mac/control_port
            {
               address = "0x08001000";
               span = "0x00000400";
               is_bridge = "0";
            }
            Entry spri/sp_2spri
            {
               address = "0x08040000";
               span = "0x00010000";
               is_bridge = "0";
            }
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
            Entry usb_hr/avalon_slave_0
            {
               address = "0x08200000";
               span = "0x00200000";
               is_bridge = "0";
            }
            Entry usb_hc_0/avalon_slave_0
            {
               address = "0x08004000";
               span = "0x00004000";
               is_bridge = "0";
            }
            Entry usb_hc_1/avalon_slave_0
            {
               address = "0x08008000";
               span = "0x00004000";
               is_bridge = "0";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         cache_has_dcache = "1";
         cache_dcache_size = "8192";
         cache_dcache_line_size = "32";
         cache_dcache_bursts = "0";
         cache_dcache_ram_block_type = "AUTO";
         num_tightly_coupled_data_masters = "0";
         gui_num_tightly_coupled_data_masters = "0";
         gui_include_tightly_coupled_data_masters = "0";
         gui_omit_avalon_data_master = "0";
         cache_has_icache = "1";
         cache_icache_size = "8192";
         cache_icache_line_size = "32";
         cache_icache_ram_block_type = "AUTO";
         cache_icache_bursts = "0";
         num_tightly_coupled_instruction_masters = "0";
         gui_num_tightly_coupled_instruction_masters = "0";
         gui_include_tightly_coupled_instruction_masters = "0";
         debug_level = "2";
         include_oci = "1";
         oci_num_xbrk = "0";
         oci_num_dbrk = "0";
         oci_dbrk_trace = "0";
         oci_dbrk_pairs = "0";
         oci_onchip_trace = "0";
         oci_offchip_trace = "0";
         oci_data_trace = "0";
         include_third_party_debug_port = "0";
         oci_trace_addr_width = "7";
         oci_debugreq_signals = "0";
         oci_trigger_arming = "1";
         oci_embedded_pll = "0";
         oci_assign_jtag_instance_id = "0";
         oci_jtag_instance_id = "0";
         oci_num_pm = "0";
         oci_pm_width = "32";
         performance_counters_present = "0";
         performance_counters_width = "32";
         always_encrypt = "1";
         debug_simgen = "0";
         activate_model_checker = "0";
         activate_test_end_checker = "0";
         activate_trace = "1";
         activate_monitors = "1";
         clear_x_bits_ld_non_bypass = "1";
         bit_31_bypass_dcache = "1";
         hdl_sim_caches_cleared = "1";
         hbreak_test = "0";
         allow_full_address_range = "0";
         extra_exc_info = "0";
         branch_prediction_type = "Dynamic";
         bht_ptr_sz = "8";
         bht_index_pc_only = "0";
         gui_branch_prediction_type = "Automatic";
         full_waveform_signals = "0";
         export_pcb = "0";
         avalon_debug_port_present = "0";
         illegal_instructions_trap = "0";
         illegal_memory_access_detection = "0";
         illegal_mem_exc = "0";
         slave_access_error_exc = "0";
         division_error_exc = "0";
         eic_present = "0";
         num_shadow_reg_sets = "0";
         gui_mmu_present = "0";
         mmu_present = "0";
         process_id_num_bits = "8";
         tlb_ptr_sz = "7";
         tlb_num_ways = "16";
         udtlb_num_entries = "6";
         uitlb_num_entries = "4";
         fast_tlb_miss_exc_slave = "";
         fast_tlb_miss_exc_offset = "0x00000000";
         mpu_present = "0";
         mpu_num_data_regions = "8";
         mpu_num_inst_regions = "8";
         mpu_min_data_region_size_log2 = "12";
         mpu_min_inst_region_size_log2 = "12";
         mpu_use_limit = "0";
         hardware_divide_present = "0";
         gui_hardware_divide_setting = "0";
         hardware_multiply_present = "1";
         hardware_multiply_impl = "dsp_mul";
         shift_rot_impl = "dsp_shift";
         gui_hardware_multiply_setting = "dsp_mul_dsp_shift";
         reset_slave = "cfi_flash/s1";
         break_slave = "cpu/jtag_debug_module";
         exc_slave = "sdram/sp_2fb";
         reset_offset = "0x00000000";
         break_offset = "0x00000020";
         exc_offset = "0x00000020";
         cpu_reset = "0";
         CPU_Implementation = "fast";
         cpu_selection = "f";
         device_family_id = "STRATIXIIGX";
         address_stall_present = "1";
         dsp_block_supports_shift = "0";
         mrams_present = "1";
         cpuid_value = "0";
         dont_overwrite_cpuid = "1";
         allow_legacy_sdk = "1";
         legacy_sdk_support = "1";
         inst_addr_width = "28";
         data_addr_width = "28";
         CPU_Architecture = "nios2";
         cache_icache_burst_type = "none";
         oci_sync_depth = "2";
         hardware_multiply_omits_msw = "0";
         big_endian = "0";
         break_slave_override = "";
         break_offset_override = "0x20";
         altera_show_unreleased_features = "0";
         altera_show_unpublished_features = "0";
         altera_internal_test = "0";
         alt_log_port_base = "";
         alt_log_port_type = "";
         cpuid_sz = "1";
         gui_illegal_instructions_trap = "0";
         advanced_exc = "0";
         gui_illegal_memory_access_detection = "0";
         cache_omit_dcache = "0";
         cache_omit_icache = "0";
         omit_instruction_master = "0";
         omit_data_master = "0";
         ras_ptr_sz = "4";
         jtb_ptr_sz = "5";
         ibuf_ptr_sz = "4";
         always_bypass_dcache = "0";
         iss_trace_on = "0";
         iss_trace_warning = "1";
         iss_trace_info = "1";
         iss_trace_disassembly = "0";
         iss_trace_registers = "0";
         iss_trace_instr_count = "0";
         iss_software_debug = "0";
         iss_software_debug_port = "9996";
         iss_memory_dump_start = "";
         iss_memory_dump_end = "";
         Boot_Copier = "boot_loader_cfi.srec";
         Boot_Copier_EPCS = "boot_loader_epcs.srec";
         Boot_Copier_EPCS_SII_SIII_CIII = "boot_loader_epcs_sii_siii_ciii.srec";
         Boot_Copier_BE = "boot_loader_cfi_be.srec";
         Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";
         Boot_Copier_EPCS_SII_SIII_CIII_BE = "boot_loader_epcs_sii_siii_ciii_be.srec";
         CONSTANTS 
         {
            CONSTANT __nios_catch_irqs__
            {
               value = "1";
               comment = "Include panic handler for all irqs (needs uart)";
            }
            CONSTANT __nios_use_constructors__
            {
               value = "1";
               comment = "Call c++ static constructors";
            }
            CONSTANT __nios_use_small_printf__
            {
               value = "1";
               comment = "Smaller non-ANSI printf, with no floating point";
            }
            CONSTANT nasys_has_icache
            {
               value = "1";
               comment = "True if instruction cache present";
            }
            CONSTANT nasys_icache_size
            {
               value = "8192";
               comment = "Size in bytes of instruction cache";
            }
            CONSTANT nasys_icache_line_size
            {
               value = "32";
               comment = "Size in bytes of each icache line";
            }
            CONSTANT nasys_icache_line_size_log2
            {
               value = "5";
               comment = "Log2 size in bytes of each icache line";
            }
            CONSTANT nasys_has_dcache
            {
               value = "1";
               comment = "True if instruction cache present";
            }
            CONSTANT nasys_dcache_size
            {
               value = "8192";
               comment = "Size in bytes of data cache";
            }
            CONSTANT nasys_dcache_line_size
            {
               value = "32";
               comment = "Size in bytes of each dcache line";
            }
            CONSTANT nasys_dcache_line_size_log2
            {
               value = "5";
               comment = "Log2 size in bytes of each dcache line";
            }
         }
         license_status = "encrypted";
         mainmem_slave = "sdram/sp_2fb";
         datamem_slave = "sdram/sp_2fb";
         maincomm_slave = "";
         germs_monitor_id = "";
      }
      class = "altera_nios2";
      class_version = "7.080900";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         Parameters_Signature = "";
         Is_CPU = "1";
         Instantiate_In_System_Module = "1";
         Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,STRATIXIV,CYCLONE,CYCLONEII,CYCLONEIII,HARDCOPYIII,ARRIAII,TARPON,HARDCOPYIV";
         Default_Module_Name = "cpu";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = "Nios II/f
            <br>&nbsp;&nbsp;8-Kbyte Instruction Cache
            <br>&nbsp;&nbsp;8-Kbyte Data Cache
            <br>&nbsp;&nbsp;JTAG Debug Module
            ";
            MESSAGES 
            {
            }
         }
      }
      iss_model_name = "altera_nios2";
      HDL_INFO 
      {
         PLI_Files = "";
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_test_bench.v, __PROJECT_DIRECTORY__/cpu_mult_cell.v, __PROJECT_DIRECTORY__/cpu_oci_test_bench.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_tck.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_sysclk.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu.v";
         Synthesis_Only_Files = "";
      }
      MASTER tightly_coupled_instruction_master_0
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_1
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_2
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_3
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER data_master2
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
         }
      }
      MASTER tightly_coupled_data_master_0
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_1
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_2
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_3
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Big_Endian = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      PORT_WIRING 
      {
         PORT jtag_debug_trigout
         {
            width = "1";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_clk
         {
            width = "1";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_data
         {
            width = "18";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT clkx2
         {
            width = "1";
            direction = "input";
            Is_Enabled = "0";
            visible = "0";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL aaa
            {
               format = "Logic";
               name = "i_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aab
            {
               format = "Logic";
               name = "i_readdatavalid";
               radix = "hexadecimal";
            }
            SIGNAL aac
            {
               format = "Logic";
               name = "i_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aad
            {
               format = "Logic";
               name = "i_address";
               radix = "hexadecimal";
            }
            SIGNAL aae
            {
               format = "Logic";
               name = "i_read";
               radix = "hexadecimal";
            }
            SIGNAL aaf
            {
               format = "Logic";
               name = "clk";
               radix = "hexadecimal";
            }
            SIGNAL aag
            {
               format = "Logic";
               name = "reset_n";
               radix = "hexadecimal";
            }
            SIGNAL aah
            {
               format = "Logic";
               name = "d_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aai
            {
               format = "Logic";
               name = "d_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aaj
            {
               format = "Logic";
               name = "d_irq";
               radix = "hexadecimal";
            }
            SIGNAL aak
            {
               format = "Logic";
               name = "d_address";
               radix = "hexadecimal";
            }
            SIGNAL aal
            {
               format = "Logic";
               name = "d_byteenable";
               radix = "hexadecimal";
            }
            SIGNAL aam
            {
               format = "Logic";
               name = "d_read";
               radix = "hexadecimal";
            }
            SIGNAL aan
            {
               format = "Logic";
               name = "d_write";
               radix = "hexadecimal";
            }
            SIGNAL aao
            {
               format = "Logic";
               name = "d_writedata";
               radix = "hexadecimal";
            }
            SIGNAL aap
            {
               format = "Logic";
               name = "d_readdatavalid";
               radix = "hexadecimal";
            }
            SIGNAL aaq
            {
               format = "Divider";
               name = "base pipeline";
               radix = "";
            }
            SIGNAL aar
            {
               format = "Logic";
               name = "clk";
               radix = "hexadecimal";
            }
            SIGNAL aas
            {
               format = "Logic";
               name = "reset_n";
               radix = "hexadecimal";
            }
            SIGNAL aat
            {
               format = "Logic";
               name = "D_stall";
               radix = "hexadecimal";
            }
            SIGNAL aau
            {
               format = "Logic";
               name = "A_stall";
               radix = "hexadecimal";
            }
            SIGNAL aav
            {
               format = "Logic";
               name = "F_pcb_nxt";
               radix = "hexadecimal";
            }
            SIGNAL aaw
            {
               format = "Logic";
               name = "F_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aax
            {
               format = "Logic";
               name = "D_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aay
            {
               format = "Logic";
               name = "E_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aaz
            {
               format = "Logic";
               name = "M_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aba
            {
               format = "Logic";
               name = "A_pcb";
               radix = "hexadecimal";
            }
            SIGNAL abb
            {
               format = "Logic";
               name = "W_pcb";
               radix = "hexadecimal";
            }
            SIGNAL abc
            {
               format = "Logic";
               name = "F_vinst";
               radix = "ascii";
            }
            SIGNAL abd
            {
               format = "Logic";
               name = "D_vinst";
               radix = "ascii";
            }
            SIGNAL abe
            {
               format = "Logic";
               name = "E_vinst";
               radix = "ascii";
            }
            SIGNAL abf
            {
               format = "Logic";
               name = "M_vinst";
               radix = "ascii";
            }
            SIGNAL abg
            {
               format = "Logic";
               name = "A_vinst";
               radix = "ascii";
            }
            SIGNAL abh
            {
               format = "Logic";
               name = "W_vinst";
               radix = "ascii";
            }
            SIGNAL abi
            {
               format = "Logic";
               name = "F_inst_ram_hit";
               radix = "hexadecimal";
            }
            SIGNAL abj
            {
               format = "Logic";
               name = "F_issue";
               radix = "hexadecimal";
            }
            SIGNAL abk
            {
               format = "Logic";
               name = "F_kill";
               radix = "hexadecimal";
            }
            SIGNAL abl
            {
               format = "Logic";
               name = "D_kill";
               radix = "hexadecimal";
            }
            SIGNAL abm
            {
               format = "Logic";
               name = "D_refetch";
               radix = "hexadecimal";
            }
            SIGNAL abn
            {
               format = "Logic";
               name = "D_issue";
               radix = "hexadecimal";
            }
            SIGNAL abo
            {
               format = "Logic";
               name = "D_valid";
               radix = "hexadecimal";
            }
            SIGNAL abp
            {
               format = "Logic";
               name = "E_valid";
               radix = "hexadecimal";
            }
            SIGNAL abq
            {
               format = "Logic";
               name = "M_valid";
               radix = "hexadecimal";
            }
            SIGNAL abr
            {
               format = "Logic";
               name = "A_valid";
               radix = "hexadecimal";
            }
            SIGNAL abs
            {
               format = "Logic";
               name = "W_valid";
               radix = "hexadecimal";
            }
            SIGNAL abt
            {
               format = "Logic";
               name = "W_wr_dst_reg";
               radix = "hexadecimal";
            }
            SIGNAL abu
            {
               format = "Logic";
               name = "W_dst_regnum";
               radix = "hexadecimal";
            }
            SIGNAL abv
            {
               format = "Logic";
               name = "W_wr_data";
               radix = "hexadecimal";
            }
            SIGNAL abw
            {
               format = "Logic";
               name = "D_en";
               radix = "hexadecimal";
            }
            SIGNAL abx
            {
               format = "Logic";
               name = "E_en";
               radix = "hexadecimal";
            }
            SIGNAL aby
            {
               format = "Logic";
               name = "M_en";
               radix = "hexadecimal";
            }
            SIGNAL abz
            {
               format = "Logic";
               name = "A_en";
               radix = "hexadecimal";
            }
            SIGNAL aca
            {
               format = "Logic";
               name = "F_iw";
               radix = "hexadecimal";
            }
            SIGNAL acb
            {
               format = "Logic";
               name = "D_iw";
               radix = "hexadecimal";
            }
            SIGNAL acc
            {
               format = "Logic";
               name = "E_iw";
               radix = "hexadecimal";
            }
            SIGNAL acd
            {
               format = "Logic";
               name = "M_pipe_flush";
               radix = "hexadecimal";
            }
            SIGNAL ace
            {
               format = "Logic";
               name = "M_pipe_flush_baddr";
               radix = "hexadecimal";
            }
            SIGNAL acf
            {
               format = "Logic";
               name = "intr_req";
               radix = "hexadecimal";
            }
            SIGNAL acg
            {
               format = "Logic";
               name = "A_status_reg";
               radix = "hexadecimal";
            }
            SIGNAL ach
            {
               format = "Logic";
               name = "A_status_reg_pie";
               radix = "hexadecimal";
            }
            SIGNAL aci
            {
               format = "Logic";
               name = "A_estatus_reg";
               radix = "hexadecimal";
            }
            SIGNAL acj
            {
               format = "Logic";
               name = "A_estatus_reg_pie";
               radix = "hexadecimal";
            }
            SIGNAL ack
            {
               format = "Logic";
               name = "A_bstatus_reg";
               radix = "hexadecimal";
            }
            SIGNAL acl
            {
               format = "Logic";
               name = "A_bstatus_reg_pie";
               radix = "hexadecimal";
            }
            SIGNAL acm
            {
               format = "Logic";
               name = "A_ienable_reg";
               radix = "hexadecimal";
            }
            SIGNAL acn
            {
               format = "Logic";
               name = "A_ienable_reg_irq1";
               radix = "hexadecimal";
            }
            SIGNAL aco
            {
               format = "Logic";
               name = "A_ienable_reg_irq2";
               radix = "hexadecimal";
            }
            SIGNAL acp
            {
               format = "Logic";
               name = "A_ienable_reg_irq3";
               radix = "hexadecimal";
            }
            SIGNAL acq
            {
               format = "Logic";
               name = "A_ienable_reg_irq4";
               radix = "hexadecimal";
            }
            SIGNAL acr
            {
               format = "Logic";
               name = "A_ienable_reg_irq5";
               radix = "hexadecimal";
            }
            SIGNAL acs
            {
               format = "Logic";
               name = "A_ienable_reg_irq6";
               radix = "hexadecimal";
            }
            SIGNAL act
            {
               format = "Logic";
               name = "A_ienable_reg_irq7";
               radix = "hexadecimal";
            }
            SIGNAL acu
            {
               format = "Logic";
               name = "A_ienable_reg_irq8";
               radix = "hexadecimal";
            }
            SIGNAL acv
            {
               format = "Logic";
               name = "A_ienable_reg_irq9";
               radix = "hexadecimal";
            }
            SIGNAL acw
            {
               format = "Logic";
               name = "A_ienable_reg_irq10";
               radix = "hexadecimal";
            }
            SIGNAL acx
            {
               format = "Logic";
               name = "A_ienable_reg_irq11";
               radix = "hexadecimal";
            }
            SIGNAL acy
            {
               format = "Logic";
               name = "A_ienable_reg_irq12";
               radix = "hexadecimal";
            }
            SIGNAL acz
            {
               format = "Logic";
               name = "A_ienable_reg_irq13";
               radix = "hexadecimal";
            }
            SIGNAL ada
            {
               format = "Logic";
               name = "A_ienable_reg_irq14";
               radix = "hexadecimal";
            }
            SIGNAL adb
            {
               format = "Logic";
               name = "A_ienable_reg_irq15";
               radix = "hexadecimal";
            }
            SIGNAL adc
            {
               format = "Logic";
               name = "A_ienable_reg_irq16";
               radix = "hexadecimal";
            }
            SIGNAL add
            {
               format = "Logic";
               name = "A_ipending_reg";
               radix = "hexadecimal";
            }
            SIGNAL ade
            {
               format = "Logic";
               name = "A_ipending_reg_irq1";
               radix = "hexadecimal";
            }
            SIGNAL adf
            {
               format = "Logic";
               name = "A_ipending_reg_irq2";
               radix = "hexadecimal";
            }
            SIGNAL adg
            {
               format = "Logic";
               name = "A_ipending_reg_irq3";
               radix = "hexadecimal";
            }
            SIGNAL adh
            {
               format = "Logic";
               name = "A_ipending_reg_irq4";
               radix = "hexadecimal";
            }
            SIGNAL adi
            {
               format = "Logic";
               name = "A_ipending_reg_irq5";
               radix = "hexadecimal";
            }
            SIGNAL adj
            {
               format = "Logic";
               name = "A_ipending_reg_irq6";
               radix = "hexadecimal";
            }
            SIGNAL adk
            {
               format = "Logic";
               name = "A_ipending_reg_irq7";
               radix = "hexadecimal";
            }
            SIGNAL adl
            {
               format = "Logic";
               name = "A_ipending_reg_irq8";
               radix = "hexadecimal";
            }
            SIGNAL adm
            {
               format = "Logic";
               name = "A_ipending_reg_irq9";
               radix = "hexadecimal";
            }
            SIGNAL adn
            {
               format = "Logic";
               name = "A_ipending_reg_irq10";
               radix = "hexadecimal";
            }
            SIGNAL ado
            {
               format = "Logic";
               name = "A_ipending_reg_irq11";
               radix = "hexadecimal";
            }
            SIGNAL adp
            {
               format = "Logic";
               name = "A_ipending_reg_irq12";
               radix = "hexadecimal";
            }
            SIGNAL adq
            {
               format = "Logic";
               name = "A_ipending_reg_irq13";
               radix = "hexadecimal";
            }
            SIGNAL adr
            {
               format = "Logic";
               name = "A_ipending_reg_irq14";
               radix = "hexadecimal";
            }
            SIGNAL ads
            {
               format = "Logic";
               name = "A_ipending_reg_irq15";
               radix = "hexadecimal";
            }
            SIGNAL adt
            {
               format = "Logic";
               name = "A_ipending_reg_irq16";
               radix = "hexadecimal";
            }
            SIGNAL adu
            {
               format = "Logic";
               name = "A_cpuid_reg";
               radix = "hexadecimal";
            }
            SIGNAL adv
            {
               format = "Logic";
               name = "E_valid_prior_to_hbreak";
               radix = "hexadecimal";
            }
         }
      }
   }
   MODULE jtag_uart
   {
      SLAVE avalon_jtag_slave
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT av_irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT av_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_address
            {
               type = "address";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_read_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT av_write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT dataavailable
            {
               type = "dataavailable";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT readyfordata
            {
               type = "readyfordata";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT rst_n
            {
               type = "reset_n";
               direction = "input";
               width = "1";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "1";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "1";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            JTAG_Hub_Base_Id = "262254";
            JTAG_Hub_Instance_Id = "0";
            Connection_Limit = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "8";
            }
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02001340";
            }
            Base_Address = "0x0e001340";
            Address_Group = "0";
         }
      }
      class = "altera_avalon_jtag_uart";
      class_version = "7.080900";
      iss_model_name = "altera_avalon_jtag_uart";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         write_depth = "64";
         read_depth = "64";
         write_threshold = "8";
         read_threshold = "8";
         read_char_stream = "";
         showascii = "0";
         read_le = "0";
         write_le = "0";
         altera_show_unreleased_jtag_uart_features = "0";
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL av_chipselect
            {
               name = "av_chipselect";
            }
            SIGNAL av_address
            {
               name = "av_address";
               radix = "hexadecimal";
            }
            SIGNAL av_read_n
            {
               name = "av_read_n";
            }
            SIGNAL av_readdata
            {
               name = "av_readdata";
               radix = "hexadecimal";
            }
            SIGNAL av_write_n
            {
               name = "av_write_n";
            }
            SIGNAL av_writedata
            {
               name = "av_writedata";
               radix = "hexadecimal";
            }
            SIGNAL av_waitrequest
            {
               name = "av_waitrequest";
            }
            SIGNAL dataavailable
            {
               name = "dataavailable";
            }
            SIGNAL readyfordata
            {
               name = "readyfordata";
            }
            SIGNAL av_irq
            {
               name = "av_irq";
            }
         }
         INTERACTIVE_IN drive
         {
            enable = "0";
            file = "_input_data_stream.dat";
            mutex = "_input_data_mutex.dat";
            log = "_in.log";
            rate = "100";
            signals = "temp,list";
            exe = "nios2-terminal";
         }
         INTERACTIVE_OUT log
         {
            enable = "0";
            exe = "perl -- atail-f.pl";
            file = "_output_stream.dat";
            radix = "ascii";
            signals = "temp,list";
         }
         Fix_Me_Up = "";
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         Instantiate_In_System_Module = "1";
         Iss_Launch_Telnet = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
                <br>Read  Depth: 64; Read  IRQ Threshold: 8";
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE sysid
   {
      SLAVE control_slave
      {
         PORT_WIRING 
         {
            PORT clock
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT address
            {
               type = "address";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "1";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02001300";
            }
            Base_Address = "0x0e001300";
            Has_IRQ = "0";
            Address_Group = "0";
         }
      }
      class = "altera_avalon_sysid";
      class_version = "7.080900";
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Fixed_Module_Name = "sysid";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         View 
         {
            Settings_Summary = "System ID (at last Generate):<br> <b>1F09802F</b>    (unique ID tag) <br> <b>4D70188E</b> (timestamp: Thu Mar 3, 2011 @5:39 PM)";
            MESSAGES 
            {
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         id = "520716335u";
         timestamp = "1299191950u";
         regenerate_values = "0";
         MAKE 
         {
            TARGET verifysysid
            {
               verifysysid 
               {
                  All_Depends_On = "0";
                  Command = "nios2-download $(JTAG_CABLE)                                --sidp=0x0e001300 --id=520716335 --timestamp=1299191950";
                  Is_Phony = "1";
                  Target_File = "dummy_verifysysid_file";
               }
            }
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE timer
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "3";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "16";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "16";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "16";
            Address_Width = "3";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "2";
            }
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02001100";
            }
            Base_Address = "0x0e001100";
            Address_Group = "0";
         }
      }
      class = "altera_avalon_timer";
      class_version = "7.080900";
      iss_model_name = "altera_avalon_timer";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = "Timer with 1 ms timeout period.";
            Is_Collapsed = "1";
            MESSAGES 
            {
            }
         }
         Clock_Source = "spclk";
         Has_Clock = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         always_run = "0";
         fixed_period = "0";
         snapshot = "1";
         period = "1.0";
         period_units = "ms";
         reset_output = "0";
         timeout_pulse_output = "0";
         load_value = "99999";
         counter_size = "32";
         mult = "0.0010";
         ticks_per_sec = "1000";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/timer.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE cfi_flash
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT data
            {
               type = "data";
               width = "16";
               direction = "inout";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT address
            {
               type = "address";
               width = "24";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT read_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT select_n
            {
               type = "chipselect_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Write_Wait_States = "160ns";
            Read_Wait_States = "160ns";
            Hold_Time = "40ns";
            Setup_Time = "40ns";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "1";
            Address_Span = "33554432";
            Read_Latency = "0";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "1";
            Active_CS_Through_Read_Latency = "0";
            Data_Width = "16";
            Address_Width = "24";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY tristate_bridge/tristate_master
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            Base_Address = "0x0c000000";
            Has_IRQ = "0";
            Simulation_Num_Lanes = "1";
            Convert_Xs_To_0 = "1";
            Address_Group = "0";
         }
         WIZARD_SCRIPT_ARGUMENTS 
         {
            class = "altera_avalon_cfi_flash";
            Supports_Flash_File_System = "1";
            flash_reference_designator = "";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Setup_Value = "40";
         Wait_Value = "160";
         Hold_Value = "40";
         Timing_Units = "ns";
         Unit_Multiplier = "1";
         Size = "33554432";
         MAKE 
         {
            MACRO 
            {
               CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(CFI_FLASH_FLASHTARGET_TMP1:0=)";
               CFI_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
            }
            MASTER cpu
            {
               MACRO 
               {
                  BOOT_COPIER = "boot_loader_cfi.srec";
                  CPU_CLASS = "altera_nios2";
                  CPU_RESET_ADDRESS = "0xC000000";
               }
            }
            TARGET delete_placeholder_warning
            {
               cfi_flash 
               {
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
                  Is_Phony = "1";
                  Target_File = "do_delete_placeholder_warning";
               }
            }
            TARGET flashfiles
            {
               cfi_flash 
               {
                  Command1 = "@echo Post-processing to create $(notdir $@)";
                  Command2 = "elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)$(DBL_QUOTE) --outfile=$(CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0xC000000 --end=0xDFFFFFF --reset=$(CPU_RESET_ADDRESS) ";
                  Dependency = "$(ELF)";
                  Target_File = "$(CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash.flash";
               }
            }
            TARGET sim
            {
               cfi_flash 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
                  Command3 = "touch $(SIMDIR)/dummy_file";
                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/dummy_file";
               }
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Simulation_Num_Lanes = "2";
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         Make_Memory_Model = "1";
         Instantiate_In_System_Module = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      class = "altera_avalon_cfi_flash";
      class_version = "7.080900";
      iss_model_name = "altera_avalon_flash";
      HDL_INFO 
      {
      }
   }
   MODULE tristate_bridge
   {
      SLAVE avalon_slave
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "1";
            Register_Outgoing_Signals = "1";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "N/A";
               Base_Address = "N/A";
            }
            Bridges_To = "tristate_master";
            Base_Address = "N/A";
            Has_IRQ = "0";
            IRQ = "N/A";
            Address_Group = "0";
         }
      }
      MASTER tristate_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Bridges_To = "avalon_slave";
         }
         PORT_WIRING 
         {
         }
         MEMORY_MAP 
         {
            Entry cfi_flash/s1
            {
               address = "0x00000000";
               span = "0x02000000";
               is_bridge = "0";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
      class = "altera_avalon_tri_state_bridge";
      class_version = "7.080900";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         Instantiate_In_System_Module = "1";
         Is_Bridge = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
   }
   MODULE hssl_sink_ch1
   {
      SLAVE sp_2hssl
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2hssl_valid
            {
               type = "valid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2hssl_ready
            {
               type = "ready";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT sp_2hssl_data
            {
               type = "data";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2hssl_startofpacket
            {
               type = "startofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2hssl_endofpacket
            {
               type = "endofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2hssl_empty
            {
               type = "empty";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
            Accepts_Internal_Connections = "1";
            MASTERED_BY sgdma_m2s_ch1/out
            {
               priority = "0";
            }
            Address_Group = "0";
            Base_Address = "0x00000000";
         }
      }
      class = "no_legacy_module";
      class_version = "7.080900";
      gtf_class_name = "hssl_sink";
      gtf_class_version = "9.0";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "0";
         Is_Bridge = "0";
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         terminated_ports 
         {
         }
      }
   }
   MODULE hssl_source_ch1
   {
      MASTER hssl_2sp
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT hssl_2sp_valid
            {
               type = "valid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT hssl_2sp_ready
            {
               type = "ready";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT hssl_2sp_data
            {
               type = "data";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT hssl_2sp_startofpacket
            {
               type = "startofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT hssl_2sp_endofpacket
            {
               type = "endofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT hssl_2sp_empty
            {
               type = "empty";
               width = "2";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
         }
      }
      class = "no_legacy_module";
      class_version = "7.080900";
      gtf_class_name = "hssl_source";
      gtf_class_version = "9.0";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "0";
         Is_Bridge = "0";
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         terminated_ports 
         {
         }
      }
   }
   MODULE sgdma_m2s_ch1
   {
      SLAVE csr
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT csr_irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT csr_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_address
            {
               type = "address";
               width = "8";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT system_reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1024";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "8";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x08000000";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "4";
            }
            Base_Address = "0x08000000";
            Address_Group = "0";
         }
      }
      MASTER out
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
         }
         PORT_WIRING 
         {
            PORT out_data
            {
               type = "data";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT out_valid
            {
               type = "valid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT out_ready
            {
               type = "ready";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT out_eop
            {
               type = "endofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT out_sop
            {
               type = "startofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT out_empty
            {
               type = "empty";
               width = "2";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT out_endofpacket
            {
               Is_Enabled = "1";
               direction = "output";
               type = "endofpacket";
               width = "1";
            }
            PORT out_startofpacket
            {
               Is_Enabled = "1";
               direction = "output";
               type = "startofpacket";
               width = "1";
            }
         }
      }
      MASTER m_read
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT m_read_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m_read_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m_read_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m_read_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m_read_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      MASTER descriptor_write
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT descriptor_write_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_write_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_write_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_write_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      MASTER descriptor_read
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT descriptor_read_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_read_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      iss_model_name = "altera_avalon_sgdma";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         read_block_data_width = "32";
         write_block_data_width = "32";
         stream_data_width = "32";
         address_width = "32";
         has_read_block = "1";
         has_write_block = "0";
         read_burstcount_width = "4";
         write_burstcount_width = "4";
         burst_transfer = "0";
         always_do_max_burst = "1";
         descriptor_read_burst = "0";
         unaligned_transfer = "0";
         control_slave_data_width = "32";
         control_slave_address_width = "8";
         desc_data_width = "32";
         descriptor_writeback_data_width = "32";
         status_token_data_width = "24";
         bytes_to_transfer_data_width = "16";
         burst_data_width = "8";
         control_data_width = "8";
         status_data_width = "8";
         atlantic_channel_data_width = "4";
         command_fifo_data_width = "104";
         symbols_per_beat = "4";
         in_error_width = "0";
         out_error_width = "0";
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "csr_read";
               conditional = "1";
            }
            SIGNAL b
            {
               name = "csr_write";
               conditional = "1";
            }
            SIGNAL c
            {
               name = "csr_address";
               conditional = "1";
            }
            SIGNAL d
            {
               name = "csr_chipselect";
               conditional = "1";
            }
            SIGNAL e
            {
               name = "csr_writedata";
               conditional = "1";
            }
            SIGNAL f
            {
               name = "csr_readdata";
               conditional = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "sg_dma";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      class = "altera_avalon_sgdma";
      class_version = "7.080900";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sgdma_m2s_ch1.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE sgdma_s2m_ch1
   {
      SLAVE csr
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT csr_irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT csr_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_address
            {
               type = "address";
               width = "8";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT system_reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1024";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "8";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x08000400";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "3";
            }
            Base_Address = "0x08000400";
            Address_Group = "0";
         }
      }
      SLAVE in
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
            Accepts_Internal_Connections = "1";
            MASTERED_BY hssl_source_ch1/hssl_2sp
            {
               priority = "0";
            }
            Address_Group = "1";
            Base_Address = "0x00000000";
         }
         PORT_WIRING 
         {
            PORT in_sop
            {
               type = "startofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT in_eop
            {
               type = "endofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT in_empty
            {
               type = "empty";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT in_data
            {
               type = "data";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT in_valid
            {
               type = "valid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT in_ready
            {
               type = "ready";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT in_endofpacket
            {
               Is_Enabled = "1";
               direction = "input";
               type = "endofpacket";
               width = "1";
            }
            PORT in_startofpacket
            {
               Is_Enabled = "1";
               direction = "input";
               type = "startofpacket";
               width = "1";
            }
         }
      }
      MASTER m_write
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT m_write_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m_write_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m_write_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m_write_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT m_write_byteenable
            {
               Is_Enabled = "1";
               direction = "output";
               type = "byteenable";
               width = "4";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      MASTER descriptor_write
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT descriptor_write_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_write_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_write_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_write_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      MASTER descriptor_read
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT descriptor_read_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_read_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      iss_model_name = "altera_avalon_sgdma";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         read_block_data_width = "32";
         write_block_data_width = "32";
         stream_data_width = "32";
         address_width = "32";
         has_read_block = "0";
         has_write_block = "1";
         read_burstcount_width = "4";
         write_burstcount_width = "4";
         burst_transfer = "0";
         always_do_max_burst = "1";
         descriptor_read_burst = "0";
         unaligned_transfer = "0";
         control_slave_data_width = "32";
         control_slave_address_width = "8";
         desc_data_width = "32";
         descriptor_writeback_data_width = "32";
         status_token_data_width = "24";
         bytes_to_transfer_data_width = "16";
         burst_data_width = "8";
         control_data_width = "8";
         status_data_width = "8";
         atlantic_channel_data_width = "4";
         command_fifo_data_width = "104";
         symbols_per_beat = "4";
         in_error_width = "0";
         out_error_width = "0";
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "csr_read";
               conditional = "1";
            }
            SIGNAL b
            {
               name = "csr_write";
               conditional = "1";
            }
            SIGNAL c
            {
               name = "csr_address";
               conditional = "1";
            }
            SIGNAL d
            {
               name = "csr_chipselect";
               conditional = "1";
            }
            SIGNAL e
            {
               name = "csr_writedata";
               conditional = "1";
            }
            SIGNAL f
            {
               name = "csr_readdata";
               conditional = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "sg_dma";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      class = "altera_avalon_sgdma";
      class_version = "7.080900";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sgdma_s2m_ch1.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE hssl_source_ch2
   {
      MASTER hssl_2sp
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT hssl_2sp_valid
            {
               type = "valid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT hssl_2sp_ready
            {
               type = "ready";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT hssl_2sp_data
            {
               type = "data";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT hssl_2sp_startofpacket
            {
               type = "startofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT hssl_2sp_endofpacket
            {
               type = "endofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT hssl_2sp_empty
            {
               type = "empty";
               width = "2";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
         }
      }
      class = "no_legacy_module";
      class_version = "7.080900";
      gtf_class_name = "hssl_source";
      gtf_class_version = "9.0";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "0";
         Is_Bridge = "0";
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         terminated_ports 
         {
         }
      }
   }
   MODULE sgdma_m2s_ch2
   {
      SLAVE csr
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT csr_irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT csr_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_address
            {
               type = "address";
               width = "8";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT system_reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1024";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "8";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x08000800";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "6";
            }
            Base_Address = "0x08000800";
            Address_Group = "0";
         }
      }
      MASTER out
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
         }
         PORT_WIRING 
         {
            PORT out_data
            {
               type = "data";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT out_valid
            {
               type = "valid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT out_ready
            {
               type = "ready";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT out_eop
            {
               type = "endofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT out_sop
            {
               type = "startofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT out_empty
            {
               type = "empty";
               width = "2";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT out_endofpacket
            {
               Is_Enabled = "1";
               direction = "output";
               type = "endofpacket";
               width = "1";
            }
            PORT out_startofpacket
            {
               Is_Enabled = "1";
               direction = "output";
               type = "startofpacket";
               width = "1";
            }
         }
      }
      MASTER m_read
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT m_read_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m_read_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m_read_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m_read_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m_read_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      MASTER descriptor_write
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT descriptor_write_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_write_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_write_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_write_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      MASTER descriptor_read
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT descriptor_read_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_read_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      iss_model_name = "altera_avalon_sgdma";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         read_block_data_width = "32";
         write_block_data_width = "32";
         stream_data_width = "32";
         address_width = "32";
         has_read_block = "1";
         has_write_block = "0";
         read_burstcount_width = "4";
         write_burstcount_width = "4";
         burst_transfer = "0";
         always_do_max_burst = "1";
         descriptor_read_burst = "0";
         unaligned_transfer = "0";
         control_slave_data_width = "32";
         control_slave_address_width = "8";
         desc_data_width = "32";
         descriptor_writeback_data_width = "32";
         status_token_data_width = "24";
         bytes_to_transfer_data_width = "16";
         burst_data_width = "8";
         control_data_width = "8";
         status_data_width = "8";
         atlantic_channel_data_width = "4";
         command_fifo_data_width = "104";
         symbols_per_beat = "4";
         in_error_width = "0";
         out_error_width = "0";
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "csr_read";
               conditional = "1";
            }
            SIGNAL b
            {
               name = "csr_write";
               conditional = "1";
            }
            SIGNAL c
            {
               name = "csr_address";
               conditional = "1";
            }
            SIGNAL d
            {
               name = "csr_chipselect";
               conditional = "1";
            }
            SIGNAL e
            {
               name = "csr_writedata";
               conditional = "1";
            }
            SIGNAL f
            {
               name = "csr_readdata";
               conditional = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "sg_dma";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      class = "altera_avalon_sgdma";
      class_version = "7.080900";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sgdma_m2s_ch2.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE sgdma_s2m_ch2
   {
      SLAVE csr
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT csr_irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT csr_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_address
            {
               type = "address";
               width = "8";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT system_reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1024";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "8";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x08000c00";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "5";
            }
            Base_Address = "0x08000c00";
            Address_Group = "0";
         }
      }
      SLAVE in
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
            Accepts_Internal_Connections = "1";
            MASTERED_BY hssl_source_ch2/hssl_2sp
            {
               priority = "0";
            }
            Address_Group = "1";
            Base_Address = "0x00000000";
         }
         PORT_WIRING 
         {
            PORT in_sop
            {
               type = "startofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT in_eop
            {
               type = "endofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT in_empty
            {
               type = "empty";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT in_data
            {
               type = "data";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT in_valid
            {
               type = "valid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT in_ready
            {
               type = "ready";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT in_endofpacket
            {
               Is_Enabled = "1";
               direction = "input";
               type = "endofpacket";
               width = "1";
            }
            PORT in_startofpacket
            {
               Is_Enabled = "1";
               direction = "input";
               type = "startofpacket";
               width = "1";
            }
         }
      }
      MASTER m_write
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT m_write_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m_write_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m_write_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m_write_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT m_write_byteenable
            {
               Is_Enabled = "1";
               direction = "output";
               type = "byteenable";
               width = "4";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      MASTER descriptor_write
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT descriptor_write_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_write_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_write_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_write_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      MASTER descriptor_read
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT descriptor_read_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_read_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      iss_model_name = "altera_avalon_sgdma";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         read_block_data_width = "32";
         write_block_data_width = "32";
         stream_data_width = "32";
         address_width = "32";
         has_read_block = "0";
         has_write_block = "1";
         read_burstcount_width = "4";
         write_burstcount_width = "4";
         burst_transfer = "0";
         always_do_max_burst = "1";
         descriptor_read_burst = "0";
         unaligned_transfer = "0";
         control_slave_data_width = "32";
         control_slave_address_width = "8";
         desc_data_width = "32";
         descriptor_writeback_data_width = "32";
         status_token_data_width = "24";
         bytes_to_transfer_data_width = "16";
         burst_data_width = "8";
         control_data_width = "8";
         status_data_width = "8";
         atlantic_channel_data_width = "4";
         command_fifo_data_width = "104";
         symbols_per_beat = "4";
         in_error_width = "0";
         out_error_width = "0";
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "csr_read";
               conditional = "1";
            }
            SIGNAL b
            {
               name = "csr_write";
               conditional = "1";
            }
            SIGNAL c
            {
               name = "csr_address";
               conditional = "1";
            }
            SIGNAL d
            {
               name = "csr_chipselect";
               conditional = "1";
            }
            SIGNAL e
            {
               name = "csr_writedata";
               conditional = "1";
            }
            SIGNAL f
            {
               name = "csr_readdata";
               conditional = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "sg_dma";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      class = "altera_avalon_sgdma";
      class_version = "7.080900";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sgdma_s2m_ch2.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE hssl_sink_ch2
   {
      SLAVE sp_2hssl
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2hssl_valid
            {
               type = "valid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2hssl_ready
            {
               type = "ready";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT sp_2hssl_data
            {
               type = "data";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2hssl_startofpacket
            {
               type = "startofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2hssl_endofpacket
            {
               type = "endofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2hssl_empty
            {
               type = "empty";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
            Accepts_Internal_Connections = "1";
            MASTERED_BY sgdma_m2s_ch2/out
            {
               priority = "0";
            }
            Address_Group = "0";
            Base_Address = "0x00000000";
         }
      }
      class = "no_legacy_module";
      class_version = "7.080900";
      gtf_class_name = "hssl_sink";
      gtf_class_version = "9.0";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "0";
         Is_Bridge = "0";
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         terminated_ports 
         {
         }
      }
   }
   MODULE pipeline_bridge
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s1_address
            {
               type = "address";
               width = "24";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s1_nativeaddress
            {
               type = "nativeaddress";
               width = "24";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s1_burstcount
            {
               type = "burstcount";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s1_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s1_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s1_debugaccess
            {
               type = "debugaccess";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s1_read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s1_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s1_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s1_endofpacket
            {
               type = "endofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT s1_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT s1_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT s1_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT s1_arbiterlock
            {
               Is_Enabled = "1";
               direction = "input";
               type = "arbiterlock";
               width = "1";
            }
            PORT s1_arbiterlock2
            {
               Is_Enabled = "1";
               direction = "input";
               type = "arbiterlock2";
               width = "1";
            }
            PORT s1_clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT s1_flush
            {
               Is_Enabled = "0";
               direction = "input";
               type = "flush";
               width = "1";
            }
            PORT s1_reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "67108864";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "5";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "24";
            Opaque_Bridges_To = "m1";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
               Offset_Address = "0x0c000000";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x0c000000";
            }
            Base_Address = "0x0c000000";
            Has_IRQ = "0";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      MASTER m1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "26";
            Opaque_Bridges_To = "s1";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT m1_address
            {
               type = "address";
               width = "26";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m1_nativeaddress
            {
               type = "nativeaddress";
               width = "24";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT m1_burstcount
            {
               type = "burstcount";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m1_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m1_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m1_debugaccess
            {
               type = "debugaccess";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m1_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m1_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m1_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m1_endofpacket
            {
               type = "endofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m1_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m1_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m1_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m1_arbiterlock
            {
               Is_Enabled = "0";
               direction = "output";
               type = "arbiterlock";
               width = "1";
            }
            PORT m1_arbiterlock2
            {
               Is_Enabled = "0";
               direction = "output";
               type = "arbiterlock2";
               width = "1";
            }
            PORT m1_clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT m1_reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sysid/control_slave
            {
               address = "0x02001300";
               span = "0x00000008";
               is_bridge = "0";
            }
            Entry cpu/jtag_debug_module
            {
               address = "0x02000000";
               span = "0x00000800";
               is_bridge = "0";
            }
            Entry jtag_uart/avalon_jtag_slave
            {
               address = "0x02001340";
               span = "0x00000008";
               is_bridge = "0";
            }
            Entry cfi_flash/s1
            {
               address = "0x00000000";
               span = "0x02000000";
               is_bridge = "0";
            }
            Entry timer/s1
            {
               address = "0x02001100";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry sgdma_tx/csr
            {
               address = "0x02000800";
               span = "0x00000400";
               is_bridge = "0";
            }
            Entry sgdma_rx/csr
            {
               address = "0x02000c00";
               span = "0x00000400";
               is_bridge = "0";
            }
            Entry int_i2c/avalon_slave_0
            {
               address = "0x02001380";
               span = "0x00000008";
               is_bridge = "0";
            }
            Entry ds1822/s1
            {
               address = "0x02001800";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry rs232_uart/s1
            {
               address = "0x02001000";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry i2c_sensor_sel_pio/s1
            {
               address = "0x02001600";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry remote_uart/s1
            {
               address = "0x02001020";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry rs232_dbg_uart/s1
            {
               address = "0x02001040";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hc_pio_0/s1
            {
               address = "0x02001060";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry hc_pio_1/s1
            {
               address = "0x02001070";
               span = "0x00000010";
               is_bridge = "0";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Is_Downstream = "1";
         Is_Upstream = "1";
         Is_Waitrequest = "1";
         Enable_Arbiterlock = "0";
      }
      class = "altera_avalon_pipeline_bridge";
      class_version = "7.080900";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         Instantiate_In_System_Module = "1";
         Is_Bridge = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/pipeline_bridge.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE sgdma_tx
   {
      SLAVE csr
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT csr_irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT csr_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_address
            {
               type = "address";
               width = "8";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT system_reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1024";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "8";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "7";
            }
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02000800";
            }
            Base_Address = "0x0e000800";
            Address_Group = "0";
         }
      }
      MASTER out
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
         }
         PORT_WIRING 
         {
            PORT out_data
            {
               type = "data";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT out_valid
            {
               type = "valid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT out_ready
            {
               type = "ready";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT out_eop
            {
               type = "endofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT out_sop
            {
               type = "startofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT out_empty
            {
               type = "empty";
               width = "2";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT out_error
            {
               type = "error";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT out_endofpacket
            {
               Is_Enabled = "1";
               direction = "output";
               type = "endofpacket";
               width = "1";
            }
            PORT out_startofpacket
            {
               Is_Enabled = "1";
               direction = "output";
               type = "startofpacket";
               width = "1";
            }
         }
      }
      MASTER m_read
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT m_read_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m_read_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m_read_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m_read_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m_read_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      MASTER descriptor_write
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT descriptor_write_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_write_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_write_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_write_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      MASTER descriptor_read
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT descriptor_read_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_read_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      iss_model_name = "altera_avalon_sgdma";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         read_block_data_width = "32";
         write_block_data_width = "32";
         stream_data_width = "32";
         address_width = "32";
         has_read_block = "1";
         has_write_block = "0";
         read_burstcount_width = "4";
         write_burstcount_width = "4";
         burst_transfer = "0";
         always_do_max_burst = "1";
         descriptor_read_burst = "0";
         unaligned_transfer = "0";
         control_slave_data_width = "32";
         control_slave_address_width = "8";
         desc_data_width = "32";
         descriptor_writeback_data_width = "32";
         status_token_data_width = "24";
         bytes_to_transfer_data_width = "16";
         burst_data_width = "8";
         control_data_width = "8";
         status_data_width = "8";
         atlantic_channel_data_width = "4";
         command_fifo_data_width = "104";
         symbols_per_beat = "4";
         in_error_width = "0";
         out_error_width = "1";
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "csr_read";
               conditional = "1";
            }
            SIGNAL b
            {
               name = "csr_write";
               conditional = "1";
            }
            SIGNAL c
            {
               name = "csr_address";
               conditional = "1";
            }
            SIGNAL d
            {
               name = "csr_chipselect";
               conditional = "1";
            }
            SIGNAL e
            {
               name = "csr_writedata";
               conditional = "1";
            }
            SIGNAL f
            {
               name = "csr_readdata";
               conditional = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "sg_dma";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      class = "altera_avalon_sgdma";
      class_version = "7.080900";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sgdma_tx.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE sgdma_rx
   {
      SLAVE csr
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT csr_irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT csr_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_address
            {
               type = "address";
               width = "8";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT csr_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT system_reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1024";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "8";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "1";
            }
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02000c00";
            }
            Base_Address = "0x0e000c00";
            Address_Group = "0";
         }
      }
      SLAVE in
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
            Accepts_Internal_Connections = "1";
            MASTERED_BY tse_mac/receive
            {
               priority = "0";
            }
            Address_Group = "1";
            Base_Address = "0x00000000";
         }
         PORT_WIRING 
         {
            PORT in_sop
            {
               type = "startofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT in_eop
            {
               type = "endofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT in_empty
            {
               type = "empty";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT in_data
            {
               type = "data";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT in_valid
            {
               type = "valid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT in_ready
            {
               type = "ready";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT in_error
            {
               type = "error";
               width = "6";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT in_endofpacket
            {
               Is_Enabled = "1";
               direction = "input";
               type = "endofpacket";
               width = "1";
            }
            PORT in_startofpacket
            {
               Is_Enabled = "1";
               direction = "input";
               type = "startofpacket";
               width = "1";
            }
         }
      }
      MASTER m_write
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT m_write_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT m_write_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m_write_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT m_write_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT m_write_byteenable
            {
               Is_Enabled = "1";
               direction = "output";
               type = "byteenable";
               width = "4";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      MASTER descriptor_write
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT descriptor_write_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_write_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_write_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_write_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "0";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      MASTER descriptor_read
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT descriptor_read_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT descriptor_read_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT descriptor_read_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "0";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry sdram/sp_2fb
            {
               address = "0x00000000";
               span = "0x08000000";
               is_bridge = "0";
            }
         }
      }
      iss_model_name = "altera_avalon_sgdma";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         read_block_data_width = "32";
         write_block_data_width = "32";
         stream_data_width = "32";
         address_width = "32";
         has_read_block = "0";
         has_write_block = "1";
         read_burstcount_width = "4";
         write_burstcount_width = "4";
         burst_transfer = "0";
         always_do_max_burst = "1";
         descriptor_read_burst = "0";
         unaligned_transfer = "0";
         control_slave_data_width = "32";
         control_slave_address_width = "8";
         desc_data_width = "32";
         descriptor_writeback_data_width = "32";
         status_token_data_width = "24";
         bytes_to_transfer_data_width = "16";
         burst_data_width = "8";
         control_data_width = "8";
         status_data_width = "8";
         atlantic_channel_data_width = "4";
         command_fifo_data_width = "104";
         symbols_per_beat = "4";
         in_error_width = "6";
         out_error_width = "0";
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "csr_read";
               conditional = "1";
            }
            SIGNAL b
            {
               name = "csr_write";
               conditional = "1";
            }
            SIGNAL c
            {
               name = "csr_address";
               conditional = "1";
            }
            SIGNAL d
            {
               name = "csr_chipselect";
               conditional = "1";
            }
            SIGNAL e
            {
               name = "csr_writedata";
               conditional = "1";
            }
            SIGNAL f
            {
               name = "csr_readdata";
               conditional = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "sg_dma";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      class = "altera_avalon_sgdma";
      class_version = "7.080900";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sgdma_rx.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE tse_mac
   {
      SLAVE transmit
      {
         PORT_WIRING 
         {
            PORT ff_tx_clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT ff_tx_data
            {
               type = "data";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT ff_tx_eop
            {
               type = "endofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT ff_tx_err
            {
               type = "error";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT ff_tx_mod
            {
               type = "empty";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT ff_tx_rdy
            {
               type = "ready";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT ff_tx_sop
            {
               type = "startofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT ff_tx_wren
            {
               type = "valid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
            Accepts_Internal_Connections = "1";
            Clock_Source = "spclk";
            Has_Clock = "1";
            MASTERED_BY sgdma_tx/out
            {
               priority = "0";
            }
            Address_Group = "0";
            Base_Address = "0x00000000";
         }
      }
      MASTER receive
      {
         PORT_WIRING 
         {
            PORT ff_rx_clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT ff_rx_data
            {
               type = "data";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT ff_rx_dval
            {
               type = "valid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT ff_rx_eop
            {
               type = "endofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT ff_rx_mod
            {
               type = "empty";
               width = "2";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT ff_rx_rdy
            {
               type = "ready";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT ff_rx_sop
            {
               type = "startofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT rx_err
            {
               type = "error";
               width = "6";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
            Clock_Source = "spclk";
            Has_Clock = "1";
         }
      }
      SLAVE control_port
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset
            {
               type = "reset";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "8";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1024";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "8";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Clock_Source = "spclk";
            Has_Clock = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x08001000";
            }
            Base_Address = "0x08001000";
            Address_Group = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT gm_rx_d
         {
            type = "export";
            width = "8";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT gm_rx_dv
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT gm_rx_err
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT gm_tx_d
         {
            type = "export";
            width = "8";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT gm_tx_en
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT gm_tx_err
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT m_rx_d
         {
            type = "export";
            width = "4";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT m_rx_en
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT m_rx_err
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT m_tx_d
         {
            type = "export";
            width = "4";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT m_tx_en
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT m_tx_err
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT m_rx_col
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT m_rx_crs
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT tx_clk
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT rx_clk
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT set_10
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT set_1000
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT ena_10
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT eth_mode
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT mdio_out
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT mdio_oen
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT mdio_in
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT mdc
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         TRANSMIT = "sgdma_tx";
         RECEIVE = "sgdma_rx";
         TRANSMIT_FIFO_DEPTH = "1024";
         RECEIVE_FIFO_DEPTH = "1024";
         FIFO_WIDTH = "32";
         ENABLE_MACLITE = "0";
         MACLITE_GIGE = "0";
         USE_MDIO = "1";
         NUMBER_OF_CHANNEL = "1";
         NUMBER_OF_MAC_MDIO_SHARED = "1";
         IS_MULTICHANNEL_MAC = "0";
         MDIO_SHARED = "0";
         REGISTER_SHARED = "0";
         PCS = "0";
         PCS_SGMII = "0";
         PCS_ID = "0";
         Is_Ethernet_Mac = "1";
      }
      SIMULATION 
      {
         Module_Name = "tse_mac_loopback";
         DISPLAY 
         {
            SIGNAL gm_rx_d
            {
               name = "gm_rx_d";
               radix = "hexadecimal";
               conditional = "1";
            }
            SIGNAL gm_rx_dv
            {
               name = "gm_rx_dv";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL gm_rx_err
            {
               name = "gm_rx_err";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL gm_tx_d
            {
               name = "gm_tx_d";
               radix = "hexadecimal";
               conditional = "1";
            }
            SIGNAL gm_tx_en
            {
               name = "gm_tx_en";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL gm_tx_err
            {
               name = "gm_tx_err";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL m_rx_d
            {
               name = "m_rx_d";
               radix = "hexadecimal";
               conditional = "1";
            }
            SIGNAL m_rx_en
            {
               name = "m_rx_en";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL m_rx_err
            {
               name = "m_rx_err";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL m_tx_d
            {
               name = "m_tx_d";
               radix = "hexadecimal";
               conditional = "1";
            }
            SIGNAL m_tx_en
            {
               name = "m_tx_en";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL m_tx_err
            {
               name = "m_tx_err";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL m_rx_col
            {
               name = "m_rx_col";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL m_rx_crs
            {
               name = "m_rx_crs";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL tx_clk
            {
               name = "tx_clk";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL rx_clk
            {
               name = "rx_clk";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL set_10
            {
               name = "set_10";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL set_1000
            {
               name = "set_1000";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL ena_10
            {
               name = "ena_10";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL eth_mode
            {
               name = "eth_mode";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL mdio_out
            {
               name = "mdio_out";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL mdio_oen
            {
               name = "mdio_oen";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL mdio_in
            {
               name = "mdio_in";
               radix = "binary";
               conditional = "1";
            }
            SIGNAL mdc
            {
               name = "mdc";
               radix = "binary";
               conditional = "1";
            }
         }
         PORT_WIRING 
         {
            PORT tx_clk
            {
               type = "export";
               direction = "Output";
               width = "1";
               __exclusive_name = "tx_clk_to_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT rx_clk
            {
               type = "export";
               direction = "Output";
               width = "1";
               __exclusive_name = "rx_clk_to_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT set_10
            {
               type = "export";
               direction = "Output";
               width = "1";
               __exclusive_name = "set_10_to_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT set_1000
            {
               type = "export";
               direction = "Output";
               width = "1";
               __exclusive_name = "set_1000_to_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT m_rx_d
            {
               type = "export";
               direction = "Output";
               width = "4";
               __exclusive_name = "m_rx_d_to_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT m_rx_en
            {
               type = "export";
               direction = "Output";
               width = "1";
               __exclusive_name = "m_rx_en_to_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT m_rx_err
            {
               type = "export";
               direction = "Output";
               width = "1";
               __exclusive_name = "m_rx_err_to_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT m_tx_d
            {
               type = "export";
               direction = "Input";
               width = "4";
               __exclusive_name = "m_tx_d_from_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT m_tx_en
            {
               type = "export";
               direction = "Input";
               width = "1";
               __exclusive_name = "m_tx_en_from_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT m_tx_err
            {
               type = "export";
               direction = "Input";
               width = "1";
               __exclusive_name = "m_tx_err_from_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT m_rx_col
            {
               type = "export";
               direction = "Output";
               width = "1";
               __exclusive_name = "m_rx_col_to_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT m_rx_crs
            {
               type = "export";
               direction = "Output";
               width = "1";
               __exclusive_name = "m_rx_crs_to_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT gm_rx_d
            {
               type = "export";
               direction = "Output";
               width = "8";
               __exclusive_name = "gm_rx_d_to_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT gm_rx_dv
            {
               type = "export";
               direction = "Output";
               width = "1";
               __exclusive_name = "gm_rx_dv_to_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT gm_rx_err
            {
               type = "export";
               direction = "Output";
               width = "1";
               __exclusive_name = "gm_rx_err_to_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT gm_tx_d
            {
               type = "export";
               direction = "Input";
               width = "8";
               __exclusive_name = "gm_tx_d_from_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT gm_tx_en
            {
               type = "export";
               direction = "Input";
               width = "1";
               __exclusive_name = "gm_tx_en_from_the_tse_mac";
               Is_Enabled = "1";
            }
            PORT gm_tx_err
            {
               type = "export";
               direction = "Input";
               width = "1";
               __exclusive_name = "gm_tx_err_from_the_tse_mac";
               Is_Enabled = "1";
            }
         }
      }
      HDL_INFO 
      {
         Simulation_HDL_Files = "/app/tools/altera/quartus9.0/quartus/eda/sim_lib/stratixiigx_hssi_atoms.v,/app/tools/altera/quartus9.0/quartus/eda/sim_lib/stratixiv_hssi_atoms.v,tse_mac.vo,tse_mac_loopback.v";
      }
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Pins_Assigned_Automatically = "1";
         Clock_Source = "spclk";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      class = "triple_speed_ethernet";
      class_version = "9.0";
   }
   MODULE int_i2c
   {
      SLAVE avalon_slave_0
      {
         PORT_WIRING 
         {
            PORT wb_clk_i
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT arst_i
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT wb_inta_o
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT wb_adr_i
            {
               type = "address";
               width = "3";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT wb_dat_i
            {
               type = "writedata";
               width = "8";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT wb_dat_o
            {
               type = "readdata";
               width = "8";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT wb_we_i
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT wb_stb_i
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT wb_cyc_i
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT wb_ack_o
            {
               type = "waitrequest_n";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "8";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "8";
            Address_Width = "3";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "10";
            }
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02001380";
            }
            Base_Address = "0x0e001380";
            Address_Group = "0";
         }
      }
      PORT_WIRING 
      {
         PORT wb_rst_i
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT scl_pad_i
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT scl_pad_o
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT scl_padoen_o
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT sda_pad_i
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT sda_pad_o
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT sda_padoen_o
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
      }
      class = "no_legacy_module";
      class_version = "7.080900";
      gtf_class_name = "i2c";
      gtf_class_version = "9.0";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "1";
         Is_Bridge = "0";
         Is_Enabled = "1";
         Clock_Source = "clk_50MHz";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      HDL_INFO 
      {
         Simulation_HDL_Files = "__PROJECT_DIRECTORY__/int_i2c.v";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         terminated_ports 
         {
         }
      }
   }
   MODULE spri
   {
      SLAVE sp_2spri
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT irqctrl_2sp_irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT sp_2spri_valid
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2spri_busy
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT sp_2spri_read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2spri_address
            {
               type = "address";
               width = "14";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2spri_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2spri_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT spri_2sp_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "65536";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "14";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "11";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x08040000";
            }
            Base_Address = "0x08040000";
            Address_Group = "0";
         }
      }
      class = "no_legacy_module";
      class_version = "7.080900";
      gtf_class_name = "spri_iface";
      gtf_class_version = "9.0";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "0";
         Is_Bridge = "0";
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         terminated_ports 
         {
         }
      }
   }
   MODULE i2c_sensor_sel_pio
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "4";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "4";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02001600";
            }
            Base_Address = "0x0e001600";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "0";
            Is_Writable = "1";
         }
      }
      PORT_WIRING 
      {
         PORT out_port
         {
            type = "export";
            width = "4";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "4";
         }
         PORT bidir_port
         {
            direction = "inout";
            Is_Enabled = "0";
            width = "4";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.080900";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 4-bit PIO using <br>
					
					
					 output pins";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "0";
         Driven_Sim_Value = "0";
         has_tri = "0";
         has_out = "1";
         has_in = "0";
         capture = "0";
         Data_Width = "4";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/i2c_sensor_sel_pio.v";
         Synthesis_Only_Files = "";
      }
   }
   MODULE ds1822
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "1";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02001800";
            }
            Base_Address = "0x0e001800";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writable = "1";
         }
      }
      PORT_WIRING 
      {
         PORT bidir_port
         {
            type = "export";
            width = "1";
            direction = "inout";
            Is_Enabled = "1";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "1";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "1";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.080900";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 1-bit PIO using <br>
					 tri-state pins with edge type NONE and interrupt source NONE
					
					";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "0";
         Driven_Sim_Value = "0";
         has_tri = "1";
         has_out = "0";
         has_in = "0";
         capture = "0";
         Data_Width = "1";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/ds1822.v";
         Synthesis_Only_Files = "";
      }
   }
   MODULE sdram
   {
      SLAVE sp_2fb
      {
         PORT_WIRING 
         {
            PORT spclk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2fb_read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT fb_2sp_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT fb_2sp_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT sp_2fb_address
            {
               type = "address";
               width = "25";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2fb_valid
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2fb_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2fb_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT sp_2fb_busy
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT sp_2fb_burstcount
            {
               type = "burstcount";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "134217728";
            Read_Latency = "0";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "64";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "25";
            Maximum_Burst_Size = "8";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY sgdma_rx/descriptor_write
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_rx/descriptor_read
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_m2s_ch2/m_read
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_m2s_ch2/descriptor_write
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_m2s_ch2/descriptor_read
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_s2m_ch2/m_write
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_s2m_ch2/descriptor_write
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_s2m_ch2/descriptor_read
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_m2s_ch1/m_read
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_m2s_ch1/descriptor_write
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_m2s_ch1/descriptor_read
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_s2m_ch1/m_write
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_s2m_ch1/descriptor_write
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_s2m_ch1/descriptor_read
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_tx/m_read
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_tx/descriptor_write
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_tx/descriptor_read
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY sgdma_rx/m_write
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            Base_Address = "0x00000000";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      class = "no_legacy_module";
      class_version = "7.080900";
      gtf_class_name = "fb_iface";
      gtf_class_version = "9.0";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "0";
         Is_Bridge = "0";
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         terminated_ports 
         {
         }
      }
   }
   MODULE rs232_dbg_uart
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "3";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT begintransfer
            {
               type = "begintransfer";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT dataavailable
            {
               type = "dataavailable";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT read_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "16";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT readyfordata
            {
               type = "readyfordata";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "16";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "1cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "1";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "16";
            Address_Width = "3";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02001040";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "16";
            }
            Base_Address = "0x0e001040";
            Address_Group = "0";
         }
      }
      PORT_WIRING 
      {
         PORT rxd
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT txd
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
      }
      class = "fifoed_avalon_uart";
      class_version = "2.1";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         use_tx_fifo = "1";
         use_rx_fifo = "1";
         baud = "115200";
         data_bits = "8";
         fixed_baud = "1";
         parity = "N";
         stop_bits = "1";
         use_cts_rts = "0";
         use_eop_register = "0";
         sim_true_baud = "0";
         sim_char_stream = "";
         use_fifo = "0";
         fifo_size = "16";
         fifo_export_used = "0";
         export_irq = "0";
         hw_cts = "0";
         fifo_size_tx = "32";
         tx_fifo_LE = "0";
         fifo_size_rx = "32";
         rx_fifo_LE = "0";
         combine_fifo = "0";
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         Instantiate_In_System_Module = "1";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = "8-bit UART with 115200 baud, <br>
                    1 stop bits and N parity";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "  Bus Interface";
               format = "Divider";
            }
            SIGNAL b
            {
               name = "chipselect";
            }
            SIGNAL c
            {
               name = "address";
               radix = "hexadecimal";
            }
            SIGNAL d
            {
               name = "writedata";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "readdata";
               radix = "hexadecimal";
            }
            SIGNAL f
            {
               name = "  Internals";
               format = "Divider";
            }
            SIGNAL g
            {
               name = "tx_ready";
            }
            SIGNAL h
            {
               name = "tx_data";
               radix = "ascii";
            }
            SIGNAL i
            {
               name = "rx_char_ready";
            }
            SIGNAL j
            {
               name = "rx_data";
               radix = "ascii";
            }
         }
         INTERACTIVE_OUT log
         {
            enable = "0";
            file = "_log_module.txt";
            radix = "ascii";
            signals = "temp,list";
            exe = "perl -- tail-f.pl";
         }
         INTERACTIVE_IN drive
         {
            enable = "0";
            file = "_input_data_stream.dat";
            mutex = "_input_data_mutex.dat";
            log = "_in.log";
            rate = "100";
            signals = "temp,list";
            exe = "perl -- uart.pl";
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/rs232_dbg_uart.v";
         Synthesis_Only_Files = "";
      }
   }
   MODULE remote_uart
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "3";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT begintransfer
            {
               type = "begintransfer";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT dataavailable
            {
               type = "dataavailable";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT read_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "16";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT readyfordata
            {
               type = "readyfordata";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "16";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "1cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "1";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "16";
            Address_Width = "3";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02001020";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "15";
            }
            Base_Address = "0x0e001020";
            Address_Group = "0";
         }
      }
      PORT_WIRING 
      {
         PORT rxd
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT txd
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
      }
      class = "fifoed_avalon_uart";
      class_version = "2.1";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         use_tx_fifo = "1";
         use_rx_fifo = "1";
         baud = "115200";
         data_bits = "8";
         fixed_baud = "1";
         parity = "N";
         stop_bits = "1";
         use_cts_rts = "0";
         use_eop_register = "0";
         sim_true_baud = "0";
         sim_char_stream = "";
         use_fifo = "0";
         fifo_size = "16";
         fifo_export_used = "0";
         export_irq = "0";
         hw_cts = "0";
         fifo_size_tx = "32";
         tx_fifo_LE = "0";
         fifo_size_rx = "32";
         rx_fifo_LE = "0";
         combine_fifo = "0";
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         Instantiate_In_System_Module = "1";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = "8-bit UART with 115200 baud, <br>
                    1 stop bits and N parity";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "  Bus Interface";
               format = "Divider";
            }
            SIGNAL b
            {
               name = "chipselect";
            }
            SIGNAL c
            {
               name = "address";
               radix = "hexadecimal";
            }
            SIGNAL d
            {
               name = "writedata";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "readdata";
               radix = "hexadecimal";
            }
            SIGNAL f
            {
               name = "  Internals";
               format = "Divider";
            }
            SIGNAL g
            {
               name = "tx_ready";
            }
            SIGNAL h
            {
               name = "tx_data";
               radix = "ascii";
            }
            SIGNAL i
            {
               name = "rx_char_ready";
            }
            SIGNAL j
            {
               name = "rx_data";
               radix = "ascii";
            }
         }
         INTERACTIVE_OUT log
         {
            enable = "0";
            file = "_log_module.txt";
            radix = "ascii";
            signals = "temp,list";
            exe = "perl -- tail-f.pl";
         }
         INTERACTIVE_IN drive
         {
            enable = "0";
            file = "_input_data_stream.dat";
            mutex = "_input_data_mutex.dat";
            log = "_in.log";
            rate = "100";
            signals = "temp,list";
            exe = "perl -- uart.pl";
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/remote_uart.v";
         Synthesis_Only_Files = "";
      }
   }
   MODULE usb_hr
   {
      SLAVE avalon_slave_0
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "19";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT read_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT byteenable_n
            {
               type = "byteenable_n";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "2097152";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "1";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "19";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "12";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x08200000";
            }
            Base_Address = "0x08200000";
            Address_Group = "0";
         }
      }
      PORT_WIRING 
      {
         PORT Data
         {
            type = "export";
            width = "8";
            direction = "inout";
            Is_Enabled = "1";
         }
         PORT Stp
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT Dir
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT Nxt
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT phy_clk
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT phy_reset_n
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT phy_cs_n
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
      }
      class = "no_legacy_module";
      class_version = "7.080900";
      gtf_class_name = "sls_avalon_usb20hr";
      gtf_class_version = "2.4";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "1";
         Is_Bridge = "0";
         Is_Enabled = "1";
         Clock_Source = "usb_hr_clk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      HDL_INFO 
      {
         Simulation_HDL_Files = "__PROJECT_DIRECTORY__/usb_hr.v";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         terminated_ports 
         {
         }
      }
   }
   MODULE rs232_uart
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "3";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT begintransfer
            {
               type = "begintransfer";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT dataavailable
            {
               type = "dataavailable";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT read_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "16";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT readyfordata
            {
               type = "readyfordata";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "16";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "1cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "1";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "16";
            Address_Width = "3";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "9";
            }
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02001000";
            }
            Base_Address = "0x0e001000";
            Address_Group = "0";
         }
      }
      PORT_WIRING 
      {
         PORT rxd
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT txd
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
      }
      class = "fifoed_avalon_uart";
      class_version = "2.1";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         use_tx_fifo = "1";
         use_rx_fifo = "1";
         baud = "115200";
         data_bits = "8";
         fixed_baud = "1";
         parity = "N";
         stop_bits = "1";
         use_cts_rts = "0";
         use_eop_register = "0";
         sim_true_baud = "0";
         sim_char_stream = "";
         use_fifo = "0";
         fifo_size = "16";
         fifo_export_used = "0";
         export_irq = "0";
         hw_cts = "0";
         fifo_size_tx = "32";
         tx_fifo_LE = "0";
         fifo_size_rx = "32";
         rx_fifo_LE = "0";
         combine_fifo = "0";
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         Instantiate_In_System_Module = "1";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = "8-bit UART with 115200 baud, <br>
                    1 stop bits and N parity";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "  Bus Interface";
               format = "Divider";
            }
            SIGNAL b
            {
               name = "chipselect";
            }
            SIGNAL c
            {
               name = "address";
               radix = "hexadecimal";
            }
            SIGNAL d
            {
               name = "writedata";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "readdata";
               radix = "hexadecimal";
            }
            SIGNAL f
            {
               name = "  Internals";
               format = "Divider";
            }
            SIGNAL g
            {
               name = "tx_ready";
            }
            SIGNAL h
            {
               name = "tx_data";
               radix = "ascii";
            }
            SIGNAL i
            {
               name = "rx_char_ready";
            }
            SIGNAL j
            {
               name = "rx_data";
               radix = "ascii";
            }
         }
         INTERACTIVE_OUT log
         {
            enable = "0";
            file = "_log_module.txt";
            radix = "ascii";
            signals = "temp,list";
            exe = "perl -- tail-f.pl";
         }
         INTERACTIVE_IN drive
         {
            enable = "0";
            file = "_input_data_stream.dat";
            mutex = "_input_data_mutex.dat";
            log = "_in.log";
            rate = "100";
            signals = "temp,list";
            exe = "perl -- uart.pl";
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/rs232_uart.v";
         Synthesis_Only_Files = "";
      }
   }
   MODULE usb_hc_0
   {
      SLAVE avalon_slave_0
      {
         PORT_WIRING 
         {
            PORT Av_clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT Reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect_n
            {
               type = "chipselect_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "12";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT read_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "16384";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "12";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "13";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x08004000";
            }
            Base_Address = "0x08004000";
            Address_Group = "0";
         }
      }
      PORT_WIRING 
      {
         PORT phy_clk
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT Data
         {
            type = "export";
            width = "8";
            direction = "inout";
            Is_Enabled = "1";
         }
         PORT Dir
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT Nxt
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT Stp
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT ID_in
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
      }
      class = "no_legacy_module";
      class_version = "7.080900";
      gtf_class_name = "sls_avalon_usb20hc";
      gtf_class_version = "1.5";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "1";
         Is_Bridge = "0";
         Is_Enabled = "1";
         Clock_Source = "usb_hc_0_clk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      HDL_INFO 
      {
         Simulation_HDL_Files = "__PROJECT_DIRECTORY__/usb_hc_0.v";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         terminated_ports 
         {
         }
      }
   }
   MODULE usb_hc_1
   {
      SLAVE avalon_slave_0
      {
         PORT_WIRING 
         {
            PORT Av_clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT Reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect_n
            {
               type = "chipselect_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "12";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT read_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "16384";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "12";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "14";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x08008000";
            }
            Base_Address = "0x08008000";
            Address_Group = "0";
         }
      }
      PORT_WIRING 
      {
         PORT phy_clk
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT Data
         {
            type = "export";
            width = "8";
            direction = "inout";
            Is_Enabled = "1";
         }
         PORT Dir
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT Nxt
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT Stp
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT ID_in
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
      }
      class = "no_legacy_module";
      class_version = "7.080900";
      gtf_class_name = "sls_avalon_usb20hc";
      gtf_class_version = "1.5";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "1";
         Is_Bridge = "0";
         Is_Enabled = "1";
         Clock_Source = "usb_hc_1_clk";
         Has_Clock = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      HDL_INFO 
      {
         Simulation_HDL_Files = "__PROJECT_DIRECTORY__/usb_hc_1.v";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         terminated_ports 
         {
         }
      }
   }
   MODULE hc_pio_0
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "8";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "8";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "8";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02001060";
            }
            Base_Address = "0x0e001060";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "0";
            Is_Writable = "1";
         }
      }
      PORT_WIRING 
      {
         PORT out_port
         {
            type = "export";
            width = "8";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "8";
         }
         PORT bidir_port
         {
            direction = "inout";
            Is_Enabled = "0";
            width = "8";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.080900";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 8-bit PIO using <br>
					
					
					 output pins";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "0";
         Driven_Sim_Value = "0";
         has_tri = "0";
         has_out = "1";
         has_in = "0";
         capture = "0";
         Data_Width = "8";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/hc_pio_0.v";
         Synthesis_Only_Files = "";
      }
   }
   MODULE hc_pio_1
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "8";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "8";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "8";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pipeline_bridge/m1
            {
               priority = "1";
               Offset_Address = "0x02001070";
            }
            Base_Address = "0x0e001070";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "0";
            Is_Writable = "1";
         }
      }
      PORT_WIRING 
      {
         PORT out_port
         {
            type = "export";
            width = "8";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "8";
         }
         PORT bidir_port
         {
            direction = "inout";
            Is_Enabled = "0";
            width = "8";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.080900";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "spclk";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 8-bit PIO using <br>
					
					
					 output pins";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "0";
         Driven_Sim_Value = "0";
         has_tri = "0";
         has_out = "1";
         has_in = "0";
         capture = "0";
         Data_Width = "8";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/hc_pio_1.v";
         Synthesis_Only_Files = "";
      }
   }
}