diff --git a/stm32cube/stm32wbaxx/README b/stm32cube/stm32wbaxx/README index e21b109c7..563babc16 100644 --- a/stm32cube/stm32wbaxx/README +++ b/stm32cube/stm32wbaxx/README @@ -6,7 +6,7 @@ Origin: http://www.st.com/en/embedded-software/stm32cubewba.html Status: - version v1.1.0 + version v1.2.0 Purpose: ST Microelectronics official MCU package for STM32WBA series. @@ -23,7 +23,7 @@ URL: https://github.com/STMicroelectronics/STM32CubeWBA Commit: - dc0b81e36a2f00054b68dbf3a57cdea3d550bd1f + b489561c58eed1d7ef434fe31c1bd279aa1451d7 Maintained-by: External diff --git a/stm32cube/stm32wbaxx/Release_Notes.html b/stm32cube/stm32wbaxx/Release_Notes.html deleted file mode 100644 index 0ca15e54d..000000000 --- a/stm32cube/stm32wbaxx/Release_Notes.html +++ /dev/null @@ -1,94 +0,0 @@ - - - - - - - Release Notes for STM32WBAxx HAL Drivers - - - - - - -
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Release Notes for

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STM32WBAxx HAL Drivers

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Copyright © 2022 STMicroelectronics

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Purpose

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The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

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The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.

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The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:

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Update History

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Main Changes

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First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

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Contents

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First Official Release of HAL/LL Drivers for STM32WBAxx serie

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  • HAL/LL Drivers are available for all peripherals: -
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    • HAL: ADC, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
      • -
    • LL: ADC, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
      • -
    • -
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Supported Devices and boards

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  • STM32WBA52xx devices
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  • NUCLEO-WBA52CG board
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Backward compatibility

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  • Not applicable
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Known Limitations

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  • None
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Dependencies

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  • None
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Notes

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- - - diff --git a/stm32cube/stm32wbaxx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32wbaxx/drivers/include/Legacy/stm32_hal_legacy.h index 2fccdc7ae..aa00ff4d2 100644 --- a/stm32cube/stm32wbaxx/drivers/include/Legacy/stm32_hal_legacy.h +++ b/stm32cube/stm32wbaxx/drivers/include/Legacy/stm32_hal_legacy.h @@ -1595,6 +1595,8 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ +#define ETH_TxPacketConfig ETH_TxPacketConfig_t /* Transmit Packet Configuration structure definition */ + /** * @} */ @@ -3929,7 +3931,8 @@ extern "C" { #if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ defined (STM32H7) || \ - defined (STM32L0) || defined (STM32L1) + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) #define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG #endif diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal.h index 7af2e35fd..80e500bce 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal.h @@ -79,7 +79,7 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @brief STM32WBAxx HAL Driver version number */ #define __STM32WBAxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBAxx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32WBAxx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32WBAxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBAxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBAxx_HAL_VERSION ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\ @@ -113,6 +113,7 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ #define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ #define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ +#define SYSCFG_IT_FPU_ALL (SYSCFG_IT_FPU_IOC|SYSCFG_IT_FPU_DZC|SYSCFG_IT_FPU_UFC|SYSCFG_IT_FPU_OFC|SYSCFG_IT_FPU_IDC|SYSCFG_IT_FPU_IXC) /*!< All */ /** * @} @@ -139,6 +140,7 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define SYSCFG_FASTMODEPLUS_PA7 SYSCFG_CFGR1_PA7_FMP /*!< Enable Fast-mode Plus on PA7 */ #define SYSCFG_FASTMODEPLUS_PA15 SYSCFG_CFGR1_PA15_FMP /*!< Enable Fast-mode Plus on PA15 */ #define SYSCFG_FASTMODEPLUS_PB3 SYSCFG_CFGR1_PB3_FMP /*!< Enable Fast-mode Plus on PB3 */ +#define SYSCFG_FASTMODEPLUS_ALL (SYSCFG_FASTMODEPLUS_PA6|SYSCFG_FASTMODEPLUS_PA7|SYSCFG_FASTMODEPLUS_PA15|SYSCFG_FASTMODEPLUS_PB3) /*!< All */ /** * @} @@ -162,8 +164,7 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @} */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - +#if defined (SYSCFG_SECCFGR_SYSCFGSEC) /** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items * @brief SYSCFG items to configure secure or non-secure attributes on * @{ @@ -175,6 +176,7 @@ extern HAL_TickFreqTypeDef uwTickFreq; /** * @} */ +#endif /* SYSCFG_SECCFGR_SYSCFGSEC */ /** @defgroup SYSCFG_attributes SYSCFG attributes * @brief SYSCFG secure or non-secure attributes @@ -186,8 +188,6 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @} */ -#endif /* __ARM_FEATURE_CMSE */ - /** * @} */ @@ -388,48 +388,37 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @{ */ -#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) +#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_ALL) != 0x00U) && \ + (((__INTERRUPT__) & ~SYSCFG_IT_FPU_ALL) == 0x00U)) #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA6) == SYSCFG_FASTMODEPLUS_PA6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PA7) == SYSCFG_FASTMODEPLUS_PA7) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PA15) == SYSCFG_FASTMODEPLUS_PA15) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB3) == SYSCFG_FASTMODEPLUS_PB3)) +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_ALL) != 0x00U) && \ + (((__PIN__) & ~SYSCFG_FASTMODEPLUS_ALL) == 0x00U)) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ ((__ATTRIBUTES__) == SYSCFG_NSEC)) -#define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_CLK) == SYSCFG_CLK) || \ - (((__ITEM__) & SYSCFG_CLASSB) == SYSCFG_CLASSB) || \ - (((__ITEM__) & SYSCFG_FPU) == SYSCFG_FPU) || \ - (((__ITEM__) & ~(SYSCFG_ALL)) == 0U)) +#define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_ALL) != 0x00U) && \ + (((__ITEM__) & ~SYSCFG_ALL) == 0x00U)) -#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ - (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ - (((__ITEM__) & SYSCFG_SAU) == SYSCFG_SAU) || \ - (((__ITEM__) & SYSCFG_MPU_SEC) == SYSCFG_MPU_SEC) || \ - (((__ITEM__) & SYSCFG_VTOR_AIRCR_SEC) == SYSCFG_VTOR_AIRCR_SEC) || \ - (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) +#endif /* __ARM_FEATURE_CMSE */ -#else +#if defined (SYSCFG_SECCFGR_SYSCFGSEC) +#define IS_SYSCFG_SINGLE_ITEMS_ATTRIBUTES(__ITEM__) (((__ITEM__) == (SYSCFG_CLK)) || \ + ((__ITEM__) == (SYSCFG_CLASSB)) || \ + ((__ITEM__) == (SYSCFG_FPU))) +#endif /* SYSCFG_SECCFGR_SYSCFGSEC */ -#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ - (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ - (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) +#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_LOCK_ALL) != 0x00U) && \ + (((__ITEM__) & ~SYSCFG_LOCK_ALL) == 0x00U)) -#endif /* __ARM_FEATURE_CMSE */ /** * @} */ @@ -527,22 +516,23 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); * @} */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** @addtogroup HAL_Exported_Functions_Group6 * @{ */ +#if defined (SYSCFG_SECCFGR_SYSCFGSEC) /* SYSCFG Attributes functions ********************************************/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); +#endif /* __ARM_FEATURE_CMSE */ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); +#endif /* SYSCFG_SECCFGR_SYSCFGSEC */ /** * @} */ -#endif /* __ARM_FEATURE_CMSE */ - /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cortex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cortex.h index f1758bbb1..38b2480f1 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cortex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cortex.h @@ -40,7 +40,6 @@ extern "C" { * @{ */ -#if (__MPU_PRESENT == 1) /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition * @{ */ @@ -81,8 +80,6 @@ typedef struct * @} */ -#endif /* __MPU_PRESENT */ - /** * @} */ @@ -121,7 +118,6 @@ typedef struct * @} */ -#if (__MPU_PRESENT == 1) /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control * @{ */ @@ -225,8 +221,6 @@ typedef struct * @} */ -#endif /* __MPU_PRESENT */ - /** * @} */ @@ -235,7 +229,7 @@ typedef struct /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros * @{ */ -#if (__MPU_PRESENT == 1) + /** @defgroup CORTEX_MPU_Normal_Memory_Attributes CORTEX MPU Normal Memory Attributes * @{ */ @@ -245,7 +239,7 @@ typedef struct /** * @} */ -#endif /* __MPU_PRESENT */ + /** * @} */ @@ -282,10 +276,10 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +uint32_t HAL_SYSTICK_GetCLKSourceConfig(void); void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); -#if (__MPU_PRESENT == 1) void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit); @@ -296,7 +290,6 @@ void HAL_MPU_Disable_NS(void); void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit); void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit); #endif /* MPU_NS */ -#endif /* __MPU_PRESENT */ /** * @} */ @@ -318,9 +311,13 @@ void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_Attribute ((GROUP) == NVIC_PRIORITYGROUP_3) || \ ((GROUP) == NVIC_PRIORITYGROUP_4)) -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY, GROUP) (((0x07U - (GROUP)) < __NVIC_PRIO_BITS) ?\ + ((PRIORITY) < (0x1UL << (0x07U - (GROUP)))) :\ + ((PRIORITY) < (0x1UL << __NVIC_PRIO_BITS))) -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) +#define IS_NVIC_SUB_PRIORITY(PRIORITY, GROUP) (((GROUP) < (0x07U - __NVIC_PRIO_BITS)) ?\ + ((PRIORITY) < (0x1UL)): \ + ((PRIORITY) < (0x1UL << ((GROUP) - (0x07U - __NVIC_PRIO_BITS))))) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) @@ -329,7 +326,6 @@ void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_Attribute ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) -#if (__MPU_PRESENT == 1) #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ ((STATE) == MPU_REGION_DISABLE)) @@ -363,8 +359,6 @@ void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_Attribute ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) -#endif /* __MPU_PRESENT */ - /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_dma.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_dma.h index 2f8d85d50..d8c9946e3 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_dma.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_dma.h @@ -251,33 +251,33 @@ typedef struct __DMA_HandleTypeDef * @{ */ /* GPDMA1 requests */ -#define GPDMA1_REQUEST_ADC4 0U /*!< GPDMA1 HW request is ADC4 */ +#define GPDMA1_REQUEST_ADC4 0U /*!< GPDMA1 HW request is ADC4 */ #if defined (SPI1) -#define GPDMA1_REQUEST_SPI1_RX 1U /*!< GPDMA1 HW request is SPI1_RX */ -#define GPDMA1_REQUEST_SPI1_TX 2U /*!< GPDMA1 HW request is SPI1_TX */ -#endif /* defined (SPI1) */ -#define GPDMA1_REQUEST_SPI3_RX 3U /*!< GPDMA1 HW request is SPI3_RX */ -#define GPDMA1_REQUEST_SPI3_TX 4U /*!< GPDMA1 HW request is SPI3_TX */ +#define GPDMA1_REQUEST_SPI1_RX 1U /*!< GPDMA1 HW request is SPI1_RX */ +#define GPDMA1_REQUEST_SPI1_TX 2U /*!< GPDMA1 HW request is SPI1_TX */ +#endif /* SPI1 */ +#define GPDMA1_REQUEST_SPI3_RX 3U /*!< GPDMA1 HW request is SPI3_RX */ +#define GPDMA1_REQUEST_SPI3_TX 4U /*!< GPDMA1 HW request is SPI3_TX */ #if defined (I2C1) -#define GPDMA1_REQUEST_I2C1_RX 5U /*!< GPDMA1 HW request is I2C1_RX */ -#define GPDMA1_REQUEST_I2C1_TX 6U /*!< GPDMA1 HW request is I2C1_TX */ -#define GPDMA1_REQUEST_I2C1_EVC 7U /*!< GPDMA1 HW request is I2C1_EVC */ -#endif /* defined (I2C1) */ -#define GPDMA1_REQUEST_I2C3_RX 8U /*!< GPDMA1 HW request is I2C3_RX */ -#define GPDMA1_REQUEST_I2C3_TX 9U /*!< GPDMA1 HW request is I2C3_TX */ +#define GPDMA1_REQUEST_I2C1_RX 5U /*!< GPDMA1 HW request is I2C1_RX */ +#define GPDMA1_REQUEST_I2C1_TX 6U /*!< GPDMA1 HW request is I2C1_TX */ +#define GPDMA1_REQUEST_I2C1_EVC 7U /*!< GPDMA1 HW request is I2C1_EVC */ +#endif /* I2C1 */ +#define GPDMA1_REQUEST_I2C3_RX 8U /*!< GPDMA1 HW request is I2C3_RX */ +#define GPDMA1_REQUEST_I2C3_TX 9U /*!< GPDMA1 HW request is I2C3_TX */ #define GPDMA1_REQUEST_I2C3_EVC 10U /*!< GPDMA1 HW request is I2C3_EVC */ #define GPDMA1_REQUEST_USART1_RX 11U /*!< GPDMA1 HW request is USART1_RX */ #define GPDMA1_REQUEST_USART1_TX 12U /*!< GPDMA1 HW request is USART1_TX */ #if defined (USART2) #define GPDMA1_REQUEST_USART2_RX 13U /*!< GPDMA1 HW request is USART2_RX */ #define GPDMA1_REQUEST_USART2_TX 14U /*!< GPDMA1 HW request is USART2_TX */ -#endif /* defined (USART2) */ +#endif /* USART2 */ #define GPDMA1_REQUEST_LPUART1_RX 15U /*!< GPDMA1 HW request is LPUART1_RX */ #define GPDMA1_REQUEST_LPUART1_TX 16U /*!< GPDMA1 HW request is LPUART1_TX */ #if defined (SAI1) #define GPDMA1_REQUEST_SAI1_A 17U /*!< GPDMA1 HW request is SAI1_A */ #define GPDMA1_REQUEST_SAI1_B 18U /*!< GPDMA1 HW request is SAI1_B */ -#endif /* defined (SAI1) */ +#endif /* SAI1 */ #define GPDMA1_REQUEST_TIM1_CH1 19U /*!< GPDMA1 HW request is TIM1_CH1 */ #define GPDMA1_REQUEST_TIM1_CH2 20U /*!< GPDMA1 HW request is TIM1_CH2 */ #define GPDMA1_REQUEST_TIM1_CH3 21U /*!< GPDMA1 HW request is TIM1_CH3 */ @@ -297,17 +297,17 @@ typedef struct __DMA_HandleTypeDef #define GPDMA1_REQUEST_TIM3_CH4 34U /*!< GPDMA1 HW request is TIM3_CH4 */ #define GPDMA1_REQUEST_TIM3_UP 35U /*!< GPDMA1 HW request is TIM3_UP */ #define GPDMA1_REQUEST_TIM3_TRIG 36U /*!< GPDMA1 HW request is TIM3_TRIG */ -#endif /* defined (TIM3) */ +#endif /* TIM3 */ #define GPDMA1_REQUEST_TIM16_CH1 37U /*!< GPDMA1 HW request is TIM16_CH1 */ #define GPDMA1_REQUEST_TIM16_UP 38U /*!< GPDMA1 HW request is TIM16_UP */ #if defined (TIM17) #define GPDMA1_REQUEST_TIM17_CH1 39U /*!< GPDMA1 HW request is TIM17_CH1 */ #define GPDMA1_REQUEST_TIM17_UP 40U /*!< GPDMA1 HW request is TIM17_UP */ -#endif /* defined (TIM17) */ +#endif /* TIM17 */ #if defined (AES) #define GPDMA1_REQUEST_AES_IN 41U /*!< GPDMA1 HW request is AES_IN */ #define GPDMA1_REQUEST_AES_OUT 42U /*!< GPDMA1 HW request is AES_OUT */ -#endif /* defined (AES) */ +#endif /* AES */ #define GPDMA1_REQUEST_HASH_IN 43U /*!< GPDMA1 HW request is HASH_IN */ #if defined (SAES) #define GPDMA1_REQUEST_SAES_IN 44U /*!< GPDMA1 HW request is SAES_IN */ @@ -320,7 +320,7 @@ typedef struct __DMA_HandleTypeDef #define GPDMA1_REQUEST_LPTIM2_IC1 49U /*!< GPDMA1 HW request is LPTIM2_IC1 */ #define GPDMA1_REQUEST_LPTIM2_IC2 50U /*!< GPDMA1 HW request is LPTIM2_IC2 */ #define GPDMA1_REQUEST_LPTIM2_UE 51U /*!< GPDMA1 HW request is LPTIM2_UE */ -#endif /* defined (LPTIM2) */ +#endif /* LPTIM2 */ /* Software request */ #define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ @@ -672,12 +672,12 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co #if defined (DMA_RCFGLOCKR_LOCK0) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState); -#endif /* defined (DMA_RCFGLOCKR_LOCK0) */ -#endif /* defined (DMA_PRIVCFGR_PRIV0) */ +#endif /* DMA_RCFGLOCKR_LOCK0 */ +#endif /* DMA_PRIVCFGR_PRIV0 */ /** * @} */ @@ -771,7 +771,7 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons #define IS_DMA_REQUEST(REQUEST) \ (((REQUEST) == DMA_REQUEST_SW) || \ ((REQUEST) <= GPDMA1_REQUEST_LPTIM1_UE)) -#endif /* defined (LPTIM2) */ +#endif /* LPTIM2 */ #define IS_DMA_BLOCK_HW_REQUEST(MODE) \ (((MODE) == DMA_BREQ_SINGLE_BURST) || \ @@ -794,12 +794,12 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ (((INSTANCE)->SMISR & (GLOBAL_FLAG))) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ (((INSTANCE)->MISR & (GLOBAL_FLAG))) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_dma_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_dma_ex.h index b729881a9..e880d3556 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_dma_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_dma_ex.h @@ -102,7 +102,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t SrcSecure; /*!< Specifies the source security attribute */ uint32_t DestSecure; /*!< Specifies the destination security attribute */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ } DMA_NodeConfTypeDef; @@ -187,11 +187,9 @@ typedef struct __DMA_QListTypeDef => Left Aligned Right Truncated down to the destination data width */ #define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width - => Packed at the destination data width - (Available only for GPDMA) */ + => Packed at the destination data width */ #define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width - => Unpacked at the destination data width - (Available only for GPDMA) */ + => Unpacked at the destination data width */ /** * @} */ @@ -251,13 +249,13 @@ typedef struct __DMA_QListTypeDef #if defined (LPTIM2) #define GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ #define GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ -#endif /* defined (LPTIM2) */ +#endif /* LPTIM2 */ #if defined (COMP1) #define GPDMA1_TRIGGER_COMP1_OUT 15U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ -#endif /* defined (COMP1) */ +#endif /* COMP1 */ #if defined (COMP2) #define GPDMA1_TRIGGER_COMP2_OUT 16U /*!< GPDMA1 HW Trigger signal is COMP2_OUT */ -#endif /* defined (COMP2) */ +#endif /* COMP2 */ #define GPDMA1_TRIGGER_RTC_ALRA_TRG 17U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ #define GPDMA1_TRIGGER_RTC_ALRB_TRG 18U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ #define GPDMA1_TRIGGER_RTC_WUT_TRG 19U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ @@ -273,7 +271,7 @@ typedef struct __DMA_QListTypeDef #define GPDMA1_TRIGGER_ADC4_AWD1 29U /*!< GPDMA1 HW Trigger signal is ADC4_ADW1 */ #if defined (TIM3) #define GPDMA1_TRIGGER_TIM3_TRGO 30U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ -#endif /* defined (TIM3) */ +#endif /* TIM3 */ /** * @} */ @@ -553,7 +551,7 @@ typedef struct #else #define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ ((TRIGGER) <= GPDMA1_TRIGGER_ADC4_AWD1) -#endif /* defined (TIM3) */ +#endif /* TIM3 */ #define IS_DMA_NODE_TYPE(TYPE) \ ((TYPE) == DMA_GPDMA_LINEAR_NODE) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_flash.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_flash.h index 5641e7df8..4bba62cdc 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_flash.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_flash.h @@ -211,13 +211,13 @@ typedef struct * @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define FLASH_TYPEERASE_PAGES FLASH_SECCR1_PER /*!< Secure pages erase activation */ -#define FLASH_TYPEERASE_PAGES_NS (FLASH_NSCR1_PER | FLASH_NON_SECURE_MASK) /*!< Non-secure pages erase activation */ -#define FLASH_TYPEERASE_MASSERASE FLASH_SECCR1_MER /*!< Secure flash mass erase activation */ -#define FLASH_TYPEERASE_MASSERASE_NS (FLASH_NSCR1_MER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash mass erase activation */ +#define FLASH_TYPEERASE_PAGES FLASH_SECCR1_PER /*!< Secure pages erase activation */ +#define FLASH_TYPEERASE_PAGES_NS (FLASH_NSCR1_PER | FLASH_NON_SECURE_MASK) /*!< Non-secure pages erase activation */ +#define FLASH_TYPEERASE_MASSERASE FLASH_SECCR1_MER /*!< Secure flash mass erase activation */ +#define FLASH_TYPEERASE_MASSERASE_NS (FLASH_NSCR1_MER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash mass erase activation */ #else -#define FLASH_TYPEERASE_PAGES FLASH_NSCR1_PER /*!< Pages erase activation */ -#define FLASH_TYPEERASE_MASSERASE FLASH_NSCR1_MER /*!< Flash mass erase activation */ +#define FLASH_TYPEERASE_PAGES FLASH_NSCR1_PER /*!< Pages erase activation */ +#define FLASH_TYPEERASE_MASSERASE FLASH_NSCR1_MER /*!< Flash mass erase activation */ #endif /* __ARM_FEATURE_CMSE */ /** * @} @@ -226,7 +226,8 @@ typedef struct /** @defgroup FLASH_Banks FLASH Banks * @{ */ -#define FLASH_BANK_1 0x00000001U /*!< Bank 1 */ +#define FLASH_BANK_1 FLASH_NSCR1_MER /*!< Bank 1 */ +#define FLASH_BANK_BOTH FLASH_BANK_1 /*!< Bank 1 */ /** * @} */ @@ -297,20 +298,20 @@ typedef struct /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type * @{ */ -#define OB_USER_BOR_LEV FLASH_OPTR_BOR_LEV /*!< BOR reset Level */ -#define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */ -#define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */ -#define OB_USER_SRAM1_RST FLASH_OPTR_SRAM1_RST /*!< SRAM1 erase upon system reset */ -#define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ -#define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */ -#define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */ -#define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Window watchdog selection */ -#define OB_USER_SRAM2_PE FLASH_OPTR_SRAM2_PE /*!< SRAM2 parity error enable */ -#define OB_USER_SRAM2_RST FLASH_OPTR_SRAM2_RST /*!< SRAM2 Erase when system reset */ -#define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */ -#define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */ +#define OB_USER_BOR_LEV FLASH_OPTR_BOR_LEV /*!< BOR reset Level */ +#define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */ +#define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */ +#define OB_USER_SRAM1_RST FLASH_OPTR_SRAM1_RST /*!< SRAM1 erase upon system reset */ +#define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ +#define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */ +#define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */ +#define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Window watchdog selection */ +#define OB_USER_SRAM2_PE FLASH_OPTR_SRAM2_PE /*!< SRAM2 parity error enable */ +#define OB_USER_SRAM2_RST FLASH_OPTR_SRAM2_RST /*!< SRAM2 Erase when system reset */ +#define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */ +#define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */ #if defined(FLASH_OPTR_TZEN) -#define OB_USER_TZEN FLASH_OPTR_TZEN /*!< Global TrustZone enable */ +#define OB_USER_TZEN FLASH_OPTR_TZEN /*!< Global TrustZone enable */ #endif /* FLASH_OPTR_TZEN */ #if defined(FLASH_OPTR_TZEN) @@ -404,6 +405,7 @@ typedef struct * @} */ + /** @defgroup FLASH_OB_USER_SRAM2_PAR FLASH Option Bytes User SRAM2 Parity error enable * @{ */ @@ -440,6 +442,7 @@ typedef struct * @} */ + #if defined(FLASH_OPTR_TZEN) /** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes User Global TrustZone * @{ @@ -999,6 +1002,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) + #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) @@ -1007,6 +1011,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET)) + #define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_flash_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_flash_ex.h index f1795db1a..72ace1ff3 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_flash_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_flash_ex.h @@ -39,7 +39,7 @@ extern "C" { /** @defgroup FLASHEx_Private_Constants FLASH Extended Private Constants * @{ */ -#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) +#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) || defined(FLASH_SECBB1R1_SECBB0) || defined(FLASH_PRIVBB1R1_PRIVBB0) #define FLASH_BLOCKBASED_NB_REG (4U) /*!< Number of block-based registers available */ #endif /* FLASH_SECBBR1_SECBB0 || FLASH_PRIVBBR1_PRIVBB0 */ /** @@ -51,7 +51,7 @@ extern "C" { * @{ */ -#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) +#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) || defined(FLASH_SECBB1R1_SECBB0) || defined(FLASH_PRIVBB1R1_PRIVBB0) /** * @brief FLASHEx Block-based attributes structure definition */ @@ -78,6 +78,19 @@ typedef struct This parameter is given by bank, and must be a value between 0x0 and 0xFFFF0 */ } FLASH_OperationTypeDef; +/** + * @brief FLASH ECC information structure definition + */ +typedef struct +{ + uint32_t Area; /*!< Area from which an ECC was detected. + This parameter can be a value of @ref FLASHEx_ECC_Area */ + uint32_t Address; /*!< Flash address from which en ECC error was detected. + This parameter must be a value between begin address and end address of the Flash */ + uint32_t MasterID; /*!< Master that initiated transfer on which error was detected + This parameter can be a value of @ref FLASHEx_ECC_Master */ +} FLASH_EccInfoTypeDef; + /** * @} */ @@ -121,7 +134,7 @@ typedef struct * @} */ -#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) +#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) || defined(FLASH_SECBB1R1_SECBB0) || defined(FLASH_PRIVBB1R1_PRIVBB0) /** @defgroup FLASHEx_BB_Attributes FLASH Block-Based Attributes * @{ */ @@ -145,6 +158,23 @@ typedef struct * @} */ +/** @defgroup FLASHEx_ECC_Area FLASH ECC Area + * @{ + */ +#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */ +#define FLASH_ECC_AREA_SYSTEM FLASH_ECCR_SYSF_ECC /*!< System FLASH area */ +/** + * @} + */ + +/** @defgroup FLASHEx_ECC_Master FLASH ECC Master + * @{ + */ +#define FLASH_ECC_MASTER_CPU1 0x00000000U /*!< ECC error occurs on a CPU1 transaction */ +/** + * @} + */ + /** @defgroup FLASHEx_Suspend_Request FLASH Suspend Request * @{ */ @@ -196,7 +226,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); -#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) +#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) || defined(FLASH_SECBB1R1_SECBB0) || defined(FLASH_PRIVBB1R1_PRIVBB0) HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); #endif /* FLASH_SECBBR1_SECBB0 || FLASH_PRIVBBR1_PRIVBB0 */ @@ -229,6 +259,19 @@ void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperati * @} */ +/** @addtogroup FLASHEx_Exported_Functions_Group3 + * @{ + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt(void); +void HAL_FLASHEx_DisableEccCorrectionInterrupt(void); +void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData); +void HAL_FLASHEx_ECCD_IRQHandler(void); +__weak void HAL_FLASHEx_EccDetectionCallback(void); +__weak void HAL_FLASHEx_EccCorrectionCallback(void); +/** + * @} + */ + /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio.h index 974cd3083..3f6b6b763 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio.h @@ -272,6 +272,23 @@ typedef enum #define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) +#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0) ||\ + ((__PIN__) == GPIO_PIN_1) ||\ + ((__PIN__) == GPIO_PIN_2) ||\ + ((__PIN__) == GPIO_PIN_3) ||\ + ((__PIN__) == GPIO_PIN_4) ||\ + ((__PIN__) == GPIO_PIN_5) ||\ + ((__PIN__) == GPIO_PIN_6) ||\ + ((__PIN__) == GPIO_PIN_7) ||\ + ((__PIN__) == GPIO_PIN_8) ||\ + ((__PIN__) == GPIO_PIN_9) ||\ + ((__PIN__) == GPIO_PIN_10) ||\ + ((__PIN__) == GPIO_PIN_11) ||\ + ((__PIN__) == GPIO_PIN_12) ||\ + ((__PIN__) == GPIO_PIN_13) ||\ + ((__PIN__) == GPIO_PIN_14) ||\ + ((__PIN__) == GPIO_PIN_15)) + #define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio_ex.h index 4c03b37d9..735a5b393 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio_ex.h @@ -350,6 +350,8 @@ extern "C" { #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) #endif /* defined(STM32WBA50xx) */ + + /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gtzc.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gtzc.h index ad3c77fba..0d756f4de 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gtzc.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gtzc.h @@ -43,17 +43,19 @@ extern "C" { */ /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ -#define GTZC_MCPBB_NB_VCTR_REG_MAX (4U) -#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX (1U) +#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#define GTZC_MPCBB_NB_VCTR_REG_MAX 4U /*!< Maximum number of superblocks */ +#endif +#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX 1U /*!< Maximum number of 32-bit registers to lock superblocks */ typedef struct { - uint32_t MPCBB_SecConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for a super-block. + uint32_t MPCBB_SecConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for a super-block. Each bit corresponds to a block inside the super-block. 0 means non-secure, 1 means secure */ - uint32_t MPCBB_PrivConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for a super-block. + uint32_t MPCBB_PrivConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for a super-block. Each bit corresponds to a block inside the super-block. 0 means non-privilege, 1 means privilege */ - uint32_t MPCBB_LockConfig_array[GTZC_MCPBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of a super-block (32 blocks). + uint32_t MPCBB_LockConfig_array[GTZC_MPCBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of a super-block (32 blocks). 0 means unlocked, 1 means locked */ } MPCBB_Attribute_ConfigTypeDef; @@ -127,8 +129,8 @@ typedef struct * @{ */ -#define GTZC_MPCBB_SRWILADIS_ENABLE (0U) -#define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk) +#define GTZC_MPCBB_SRWILADIS_ENABLE 0U +#define GTZC_MPCBB_SRWILADIS_DISABLE GTZC_MPCBB_CR_SRWILADIS_Msk /** * @} @@ -138,8 +140,8 @@ typedef struct * @{ */ -#define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U) -#define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk) +#define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED 0U +#define GTZC_MPCBB_INVSECSTATE_INVERTED GTZC_MPCBB_CR_INVSECSTATE_Msk /** * @} @@ -162,16 +164,16 @@ typedef struct #define GTZC_PERIPH_USART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) #define GTZC_PERIPH_TIM16 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) #define GTZC_PERIPH_TIM17 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) -#if defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined (SAI1) #define GTZC_PERIPH_SAI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) -#endif /* STM32WBA54xx || STM32WBA55xx */ +#endif /* SAI1 */ #define GTZC_PERIPH_SPI3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI3_Pos) #define GTZC_PERIPH_LPUART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPUART1_Pos) #define GTZC_PERIPH_I2C3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_I2C3_Pos) #define GTZC_PERIPH_LPTIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPTIM1_Pos) -#if defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined (COMP1) #define GTZC_PERIPH_COMP (GTZC_PERIPH_REG2 | GTZC_CFGR2_COMP_Pos) -#endif /* STM32WBA54xx || STM32WBA55xx */ +#endif /* COMP1 */ #define GTZC_PERIPH_ADC4 (GTZC_PERIPH_REG2 | GTZC_CFGR2_ADC4_Pos) #define GTZC_PERIPH_CRC (GTZC_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) @@ -248,7 +250,7 @@ typedef struct */ /* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */ -#define GTZC_TZSC_LOCK_OFF (0U) +#define GTZC_TZSC_LOCK_OFF 0U #define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk /** @@ -262,8 +264,8 @@ typedef struct /* user-oriented definitions for MPCBB */ #define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */ #define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */ -#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED (0U) -#define GTZC_MCPBB_SUPERBLOCK_LOCKED (1U) +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED 0U +#define GTZC_MCPBB_SUPERBLOCK_LOCKED 1U #define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) #define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) @@ -271,8 +273,8 @@ typedef struct #define GTZC_MCPBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) /* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ -#define GTZC_MCPBB_LOCK_OFF (0U) -#define GTZC_MCPBB_LOCK_ON (1U) +#define GTZC_MCPBB_LOCK_OFF 0U +#define GTZC_MCPBB_LOCK_ON 1U /** * @} @@ -283,8 +285,8 @@ typedef struct */ /* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */ -#define GTZC_TZIC_NO_ILA_EVENT (0U) -#define GTZC_TZIC_ILA_EVENT_PENDING (1U) +#define GTZC_TZIC_NO_ILA_EVENT 0U +#define GTZC_TZIC_ILA_EVENT_PENDING 1U /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_i2c.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_i2c.h index c29d8b123..094b2cb33 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_i2c.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_i2c.h @@ -118,8 +118,6 @@ typedef enum HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception process is ongoing */ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ } HAL_I2C_StateTypeDef; diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pka.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pka.h index f41eb3b11..3ec411a3e 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pka.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pka.h @@ -147,6 +147,21 @@ typedef struct const uint8_t *primeOrder; /*!< pointer to order of the curve */ } PKA_ECCMulInTypeDef; +typedef struct +{ + uint32_t primeOrderSize; /*!< Number of element in primeOrder array */ + uint32_t scalarMulSize; /*!< Number of element in scalarMul array */ + uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *coefB; /*!< pointer to curve coefficient b */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */ + const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */ + const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */ + const uint8_t *primeOrder; /*!< pointer to order of the curve */ +} PKA_ECCMulExInTypeDef; + typedef struct { uint32_t modulusSize; /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */ @@ -572,6 +587,8 @@ uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka); HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout); HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in); void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out); HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout); diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr.h index 262939ab9..0afa50616 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr.h @@ -133,17 +133,17 @@ typedef struct /** @defgroup PWR_Flags PWR Flags * @{ */ -#define PWR_FLAG_VOSRDY (0x01U) /*!< Voltage scaling ready flag */ -#define PWR_FLAG_STOPF (0x02U) /*!< Stop flag */ -#define PWR_FLAG_SBF (0x03U) /*!< Standby flag */ -#define PWR_FLAG_ACTVOSRDY (0x04U) /*!< Currently applied VOS ready flag */ -#define PWR_FLAG_PVDO (0x05U) /*!< VDD voltage detector output flag */ +#define PWR_FLAG_VOSRDY (1U) /*!< Voltage scaling ready flag */ +#define PWR_FLAG_STOPF (2U) /*!< Stop flag */ +#define PWR_FLAG_SBF (3U) /*!< Standby flag */ +#define PWR_FLAG_ACTVOSRDY (4U) /*!< Currently applied VOS ready flag */ +#define PWR_FLAG_PVDO (5U) /*!< VDD voltage detector output flag */ #if defined(PWR_SVMSR_REGS) -#define PWR_FLAG_REGS (0x06U) /*!< Regulator selection flag */ +#define PWR_FLAG_REGS (6U) /*!< Regulator selection flag */ #endif /* defined(PWR_SVMSR_REGS) */ -#define PWR_FLAG_REGPARDYVDDRFPA (0x07U) /*!< Ready bit for VDDHPA voltage level when selecting VDDRFPA input */ +#define PWR_FLAG_REGPARDYVDDRFPA (7U) /*!< Ready bit for VDDHPA voltage level when selecting VDDRFPA input */ #if defined(PWR_RADIOSCR_REGPARDYV11) -#define PWR_FLAG_REGPARDYV11 (0x08U) /*!< Ready bit for VDDHPA voltage level when selecting VDD11 input */ +#define PWR_FLAG_REGPARDYV11 (8U) /*!< Ready bit for VDDHPA voltage level when selecting VDD11 input */ #endif /* defined(PWR_RADIOSCR_REGPARDYV11) */ /** * @} @@ -173,9 +173,9 @@ typedef struct * @{ */ #define PWR_WAKEUP_PIN1_HIGH_0 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_0) /*!< PA0 : Wakeup pin 1 (high polarity) */ -#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) #define PWR_WAKEUP_PIN1_HIGH_1 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_1) /*!< PB2 : Wakeup pin 1 (high polarity) */ -#endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ #if defined(PWR_WUCR1_WUPEN2) #define PWR_WAKEUP_PIN2_HIGH_0 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_SOURCE_SELECTION_0) /*!< PA4 : Wakeup pin 2 (high polarity) */ @@ -183,14 +183,14 @@ typedef struct #endif /* defined(PWR_WUCR1_WUPEN2) */ #define PWR_WAKEUP_PIN3_HIGH_1 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_1) /*!< PA1 : Wakeup pin 3 (high polarity) */ -#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) #define PWR_WAKEUP_PIN3_HIGH_2 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_2) /*!< PB6 : Wakeup pin 3 (high polarity) */ -#endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ #define PWR_WAKEUP_PIN4_HIGH_0 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_0) /*!< PA2 : Wakeup pin 4 (high polarity) */ -#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) #define PWR_WAKEUP_PIN4_HIGH_1 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_1) /*!< PB1 : Wakeup pin 4 (high polarity) */ -#endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ #if defined(PWR_WUCR1_WUPEN5) #define PWR_WAKEUP_PIN5_HIGH_1 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_SOURCE_SELECTION_1) /*!< PA3 : Wakeup pin 5 (high polarity) */ @@ -201,9 +201,9 @@ typedef struct #define PWR_WAKEUP_PIN6_HIGH_1 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_1) /*!< PA5 : Wakeup pin 6 (high polarity) */ #define PWR_WAKEUP_PIN6_HIGH_3 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 6 (high polarity) */ -#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) #define PWR_WAKEUP_PIN7_HIGH_0 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_0) /*!< PB14 : Wakeup pin 7 (high polarity) */ -#endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ #define PWR_WAKEUP_PIN7_HIGH_1 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_1) /*!< PA6 : Wakeup pin 7 (high polarity) */ #define PWR_WAKEUP_PIN7_HIGH_3 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 7 (high polarity) */ @@ -218,9 +218,9 @@ typedef struct * @{ */ #define PWR_WAKEUP_PIN1_LOW_0 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_0) /*!< PA0 : Wakeup pin 1 (low polarity) */ -#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) #define PWR_WAKEUP_PIN1_LOW_1 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_1) /*!< PB2 : Wakeup pin 1 (low polarity) */ -#endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ #if defined(PWR_WUCR1_WUPEN2) #define PWR_WAKEUP_PIN2_LOW_0 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_POLARITY_LOW | PWR_WAKEUP2_SOURCE_SELECTION_0) /*!< PA4 : Wakeup pin 2 (low polarity) */ @@ -228,14 +228,14 @@ typedef struct #endif /* defined(PWR_WUCR1_WUPEN2) */ #define PWR_WAKEUP_PIN3_LOW_1 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_1) /*!< PA1 : Wakeup pin 3 (low polarity) */ -#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) #define PWR_WAKEUP_PIN3_LOW_2 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_2) /*!< PB6 : Wakeup pin 3 (low polarity) */ -#endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ #define PWR_WAKEUP_PIN4_LOW_0 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_0) /*!< PA2 : Wakeup pin 4 (low polarity) */ -#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) #define PWR_WAKEUP_PIN4_LOW_1 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_1) /*!< PB1 : Wakeup pin 4 (low polarity) */ -#endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ #if defined(PWR_WUCR1_WUPEN5) #define PWR_WAKEUP_PIN5_LOW_1 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_POLARITY_LOW | PWR_WAKEUP5_SOURCE_SELECTION_1) /*!< PA3 : Wakeup pin 5 (low polarity) */ @@ -246,9 +246,9 @@ typedef struct #define PWR_WAKEUP_PIN6_LOW_1 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_1) /*!< PA5 : Wakeup pin 6 (low polarity) */ #define PWR_WAKEUP_PIN6_LOW_3 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 6 (low polarity) */ -#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) #define PWR_WAKEUP_PIN7_LOW_0 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_0) /*!< PB14 : Wakeup pin 7 (low polarity) */ -#endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ #define PWR_WAKEUP_PIN7_LOW_1 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_1) /*!< PA6 : Wakeup pin 7 (low polarity) */ #define PWR_WAKEUP_PIN7_LOW_3 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 7 (low polarity) */ @@ -642,9 +642,9 @@ typedef struct /* Defines wake up lines selection */ #define PWR_WAKEUP1_SOURCE_SELECTION_0 (0U) -#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) #define PWR_WAKEUP1_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL1_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ #if defined(PWR_WUCR1_WUPEN2) #define PWR_WAKEUP2_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ @@ -652,14 +652,14 @@ typedef struct #endif /* defined(PWR_WUCR1_WUPEN2) */ #define PWR_WAKEUP3_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL3_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) #define PWR_WAKEUP3_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL3_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ #define PWR_WAKEUP4_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ -#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) #define PWR_WAKEUP4_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL4_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ #if defined(PWR_WUCR1_WUPEN5) #define PWR_WAKEUP5_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL5_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ @@ -670,9 +670,9 @@ typedef struct #define PWR_WAKEUP6_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL6_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ #define PWR_WAKEUP6_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL6_0 | PWR_WUCR3_WUSEL6_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) #define PWR_WAKEUP7_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ -#endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ #define PWR_WAKEUP7_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL7_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ #define PWR_WAKEUP7_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL7_0 | PWR_WUCR3_WUSEL7_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ @@ -708,8 +708,8 @@ typedef struct */ /* Stop mode entry check macro */ -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_LOWPOWERMODE_STOP0) || \ + ((REGULATOR) == PWR_LOWPOWERMODE_STOP1)) /* Wake up pins check macro */ #if defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) @@ -815,7 +815,7 @@ typedef struct #define IS_PWR_ITEMS_ATTRIBUTES(ITEM) ((((ITEM) & (~PWR_ALL)) == 0U) && ((ITEM) != 0U)) #if defined(PWR_PRIVCFGR_SPRIV) -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* PWR attribute check macro (Secure) */ #define IS_PWR_ATTRIBUTES(ATTRIBUTES) ((((~(((ATTRIBUTES)& \ 0xF0U) >> 4U)) & ((ATTRIBUTES) & 0x0FU)) == 0U) && \ @@ -883,14 +883,14 @@ void HAL_PWR_PVD_Rising_Callback(void); void HAL_PWR_PVD_Falling_Callback(void); void HAL_PWR_WKUP_IRQHandler(void); void HAL_PWR_WKUP1_Callback(void); -#if defined (PWR_WUCR1_WUPEN2) +#if defined(PWR_WUCR1_WUPEN2) void HAL_PWR_WKUP2_Callback(void); -#endif /* defined (PWR_WUCR1_WUPEN2) */ +#endif /* defined(PWR_WUCR1_WUPEN2) */ void HAL_PWR_WKUP3_Callback(void); void HAL_PWR_WKUP4_Callback(void); -#if defined (PWR_WUCR1_WUPEN5) +#if defined(PWR_WUCR1_WUPEN5) void HAL_PWR_WKUP5_Callback(void); -#endif /* defined (PWR_WUCR1_WUPEN5) */ +#endif /* defined(PWR_WUCR1_WUPEN5) */ void HAL_PWR_WKUP6_Callback(void); void HAL_PWR_WKUP7_Callback(void); void HAL_PWR_WKUP8_Callback(void); diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr_ex.h index 4aec2cf63..3124b1713 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr_ex.h @@ -52,11 +52,11 @@ extern "C" { * @{ */ /* SRAM1 pages retention defines */ -#define PWR_SRAM1_FULL_STOP_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 full retention in Stop modes (Stop 0, 1) */ +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 full retention in Stop modes */ /* SRAM2 pages retention defines */ -#define PWR_SRAM2_FULL_STOP_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 full retention in Stop modes (Stop 0, 1) */ +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 full retention in Stop modes */ /* Cache RAMs retention defines */ -#define PWR_ICACHE_FULL_STOP_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM retention in Stop modes (Stop 0, 1) */ +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM retention in Stop modes */ /** * @} */ @@ -65,9 +65,8 @@ extern "C" { /** @defgroup PWREx_RAM_Contents_Standby_Retention PWR Extended SRAM Contents Standby Retention * @{ */ -#if defined(PWR_CR1_R1RSB1) #define PWR_SRAM1_FULL_STANDBY_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 full retention in Standby mode */ -#endif /* defined(PWR_CR1_R1RSB1) */ + #define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_CR1_R2RSB1 /*!< SRAM2 full retention in Standby mode */ #define PWR_RADIOSRAM_FULL_STANDBY_RETENTION PWR_CR1_RADIORSB /*!< 2.4GHz RADIO SRAMs (TXRX and Sequence) and Sleep clock retention in Standby mode */ @@ -219,16 +218,12 @@ extern "C" { * @{ */ - /* All available RAM retention in Stop mode define */ #define PWR_ALL_RAM_STOP_RETENTION_MASK (PWR_SRAM1_FULL_STOP_RETENTION | PWR_SRAM2_FULL_STOP_RETENTION | \ PWR_ICACHE_FULL_STOP_RETENTION ) + /* All available RAM retention in Standby mode define */ -#if defined(PWR_CR1_R1RSB1) #define PWR_ALL_RAM_STANDBY_RETENTION_MASK (PWR_SRAM1_FULL_STANDBY_RETENTION | PWR_SRAM2_FULL_STANDBY_RETENTION) -#else -#define PWR_ALL_RAM_STANDBY_RETENTION_MASK PWR_SRAM2_FULL_STANDBY_RETENTION -#endif /* defined(PWR_CR1_R1RSB1) */ /** * @} */ @@ -258,10 +253,8 @@ extern "C" { #define IS_PWR_GPIO_PIN_MASK(BIT_MASK) ((((BIT_MASK) & PWR_GPIO_PIN_MASK) != 0U) &&\ ((BIT_MASK) <= PWR_GPIO_PIN_MASK)) -#if defined(PWR_CR1_R1RSB1) /* SRAM1 retention in Standby mode check macro */ #define IS_PWR_SRAM1_STANDBY_RETENTION(CONTENT) ((CONTENT) == PWR_SRAM1_FULL_STANDBY_RETENTION) -#endif /* defined(PWR_CR1_R1RSB1) */ /* SRAM2 retention in Standby mode check macro */ #define IS_PWR_SRAM2_STANDBY_RETENTION(CONTENT) ((CONTENT) == PWR_SRAM2_FULL_STANDBY_RETENTION) @@ -317,10 +310,8 @@ void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pag void HAL_PWREx_DisableSRAM2ContentStandbyRetention(void); void HAL_PWREx_EnableRadioSRAMClockStandbyRetention(uint32_t RadioSRAM); void HAL_PWREx_DisableRadioSRAMClockStandbyRetention(void); -#if defined(PWR_CR1_R1RSB1) void HAL_PWREx_EnableSRAM1ContentStandbyRetention(uint32_t SRAM1Pages); void HAL_PWREx_DisableSRAM1ContentStandbyRetention(void); -#endif /* defined(PWR_CR1_R1RSB1) */ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection); void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection); void HAL_PWREx_EnableFlashFastWakeUp(void); @@ -329,12 +320,12 @@ void HAL_PWREx_DisableFlashFastWakeUp(void); * @} */ -/** @addtogroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions +/** @addtogroup PWREx_Exported_Functions_Group5 I/O Retention Functions * @{ */ HAL_StatusTypeDef HAL_PWREx_EnableStandbyIORetention(uint32_t GPIO_Port, uint32_t GPIO_Pin); HAL_StatusTypeDef HAL_PWREx_DisableStandbyIORetention(uint32_t GPIO_Port, uint32_t GPIO_Pin); -uint32_t HAL_PWREx_GetStandbyIORetentionStatus(uint32_t GPIO_Port); +uint32_t HAL_PWREx_GetStandbyIORetentionStatus(uint32_t GPIO_Port); HAL_StatusTypeDef HAL_PWREx_DisableStandbyRetainedIOState(uint32_t GPIO_Port, uint32_t GPIO_Pin); /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc_ex.h index 959149d20..64fa7e579 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc_ex.h @@ -539,7 +539,6 @@ typedef struct * @arg RCC_SYSTICKCLKSOURCE_HCLK_DIV8 : HCLK divided by 8 Clock selected as SYSTICK clock * @arg RCC_SYSTICKCLKSOURCE_LSI : LSI Clock selected as SYSTICK clock * @arg RCC_SYSTICKCLKSOURCE_LSE : LSE Clock selected as SYSTICK clock - * @note (1) Source is not available on all devices */ #define __HAL_RCC_SYSTICK_CONFIG(__SYSTICK_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (__SYSTICK_CLKSOURCE__)) @@ -549,8 +548,6 @@ typedef struct * @arg RCC_SYSTICKCLKSOURCE_HCLK_DIV8 : HCLK divided by 8 Clock selected as SYSTICK clock * @arg RCC_SYSTICKCLKSOURCE_LSI : LSI Clock selected as SYSTICK clock * @arg RCC_SYSTICKCLKSOURCE_LSE : LSE Clock selected as SYSTICK clock - * @arg RCC_SYSTICKCLKSOURCE_HSI : LSI Clock selected as SYSTICK clock (1) - * @note (1) Source is not available on all devices */ #define __HAL_RCC_GET_SYSTICK_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smbus.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smbus.h index 8b1cdffc8..b34718807 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smbus.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smbus.h @@ -100,8 +100,6 @@ typedef struct #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_spi_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_spi_ex.h index bfd6be033..21cd5a75f 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_spi_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_spi_ex.h @@ -172,8 +172,8 @@ typedef struct #if defined (SPI_TRIG_GRP1) #define IS_SPI_TRIG_SOURCE(__INSTANCE__, __SOURCE__) ((IS_SPI_GRP2_INSTANCE(__INSTANCE__)) ? \ - IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) : \ - IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__)) + IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) : \ + IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__)) #else #define IS_SPI_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__)) #endif /* SPI_TRIG_GRP1 */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim.h index b687cddd4..c0dc4c5a6 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim.h @@ -416,29 +416,28 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ @@ -1952,8 +1951,9 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ - ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -2008,7 +2008,6 @@ mode. #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) @@ -2409,7 +2408,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_bus.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_bus.h index 23abc6eba..27c5bde17 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_bus.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_bus.h @@ -118,6 +118,9 @@ extern "C" { * @{ */ #define LL_AHB5_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(PTACONV) +#define LL_AHB5_GRP1_PERIPH_PTACONV RCC_AHB5ENR_PTACONVEN +#endif /* PTACONV */ #define LL_AHB5_GRP1_PERIPH_RADIO RCC_AHB5ENR_RADIOEN /** * @} @@ -426,8 +429,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR PKAEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR SAESEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR PKAEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR SRAM2EN LL_AHB2_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL @@ -438,8 +442,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 * * (*) value not defined in all devices. @@ -463,8 +468,9 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR PKAEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR SAESEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR PKAEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR SRAM2EN LL_AHB2_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL @@ -475,8 +481,9 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 * * (*) value not defined in all devices. @@ -496,8 +503,9 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR PKAEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR SAESEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR PKAEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR SRAM2EN LL_AHB2_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL @@ -508,8 +516,9 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 * * (*) value not defined in all devices. @@ -529,8 +538,9 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR PKARST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR SAESRST LL_AHB2_GRP1_ForceReset + * AHB2RSTR SAESRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR HSEMRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR PKARST LL_AHB2_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA @@ -540,8 +550,9 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * * (*) value not defined in all devices. * @retval None @@ -560,8 +571,10 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR SAESRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR HSEMRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR PKARST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR SAESRST LL_AHB2_GRP1_ReleaseReset + * AHB2RSTR SRAM1RST LL_AHB2_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA @@ -571,8 +584,9 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * * (*) value not defined in all devices. * @retval None @@ -591,11 +605,10 @@ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR PKASMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR SAESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR PKASMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC @@ -603,8 +616,8 @@ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 * * (*) value not defined in all devices. @@ -628,11 +641,10 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * AHB2SMENR AESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR HASHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR RNGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR PKASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR SAESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR PKASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC @@ -640,8 +652,8 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 * * (*) value not defined in all devices. @@ -661,11 +673,10 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR PKASMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR SAESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR PKASMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC @@ -673,9 +684,11 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) @@ -823,10 +836,14 @@ __STATIC_INLINE void LL_AHB4_GRP1_DisableClockStopSleep(uint32_t Periphs) */ /** * @brief Enable AHB5 peripherals clock. - * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_EnableClock + * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_EnableClock\n + * AHB5ENR PTACONVEN LL_AHB5_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB5_GRP1_PERIPH_ALL * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs) @@ -840,10 +857,14 @@ __STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs) /** * @brief Check if AHB5 peripheral clock is enabled or not - * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_IsEnabledClock + * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR PTACONVEN LL_AHB5_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB5_GRP1_PERIPH_ALL * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs) @@ -853,10 +874,14 @@ __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs) /** * @brief Disable AHB5 peripherals clock. - * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_DisableClock + * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_DisableClock\n + * AHB5ENR PTACONVEN LL_AHB5_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB5_GRP1_PERIPH_ALL * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs) @@ -866,10 +891,14 @@ __STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs) /** * @brief Force AHB5 peripherals reset. - * @rmtoll AHB5RSTR RADIORST LL_AHB5_GRP1_ForceReset + * @rmtoll AHB5RSTR RADIORST LL_AHB5_GRP1_ForceReset\n + * AHB5RSTR PTACONVRST LL_AHB5_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB5_GRP1_PERIPH_ALL * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs) @@ -879,10 +908,14 @@ __STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs) /** * @brief Release AHB5 peripherals reset. - * @rmtoll AHB5RSTR RADIORST LL_AHB5_GRP1_ReleaseReset + * @rmtoll AHB5RSTR RADIORST LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTR PTACONVRST LL_AHB5_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB5_GRP1_PERIPH_ALL * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs) @@ -892,10 +925,14 @@ __STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs) /** * @brief Enable AHB5 peripheral clocks in Sleep and Stop modes - * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_EnableClockStopSleep + * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_EnableClockStopSleep\n + * AHB5SMENR PTACONVSMEN LL_AHB5_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB5_GRP1_PERIPH_ALL * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB5_GRP1_EnableClockStopSleep(uint32_t Periphs) @@ -909,10 +946,14 @@ __STATIC_INLINE void LL_AHB5_GRP1_EnableClockStopSleep(uint32_t Periphs) /** * @brief Check if AHB5 peripheral clocks in Sleep and Stop modes is enabled or not - * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_IsEnabledClockStopSleep + * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_IsEnabledClockStopSleep\n + * AHB5SMENR PTACONVSMEN LL_AHB5_GRP1_IsEnabledClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB5_GRP1_PERIPH_ALL * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) @@ -922,10 +963,14 @@ __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) /** * @brief Disable AHB5 peripheral clocks in Sleep and Stop modes - * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_DisableClockStopSleep + * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_DisableClockStopSleep\n + * AHB5SMENR PTACONVSMEN LL_AHB5_GRP1_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB5_GRP1_PERIPH_ALL * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB5_GRP1_DisableClockStopSleep(uint32_t Periphs) @@ -947,7 +992,7 @@ __STATIC_INLINE void LL_AHB5_GRP1_DisableClockStopSleep(uint32_t Periphs) * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock + * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -970,7 +1015,7 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) /** * @brief Enable APB1 peripherals clock. - * @rmtoll APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 @@ -991,7 +1036,7 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock + * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1010,7 +1055,7 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) /** * @brief Check if APB1 peripheral clock is enabled or not - * @rmtoll APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 @@ -1025,12 +1070,14 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) * @brief Disable APB1 peripherals clock. * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock + * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) * @@ -1044,7 +1091,7 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) /** * @brief Disable APB1 peripherals clock. - * @rmtoll APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 @@ -1060,7 +1107,7 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset + * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1078,7 +1125,7 @@ __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) /** * @brief Force APB1 peripherals reset. - * @rmtoll APB1RSTR2 LPTIM2RST LL_APB1_GRP2_DisableClock + * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 @@ -1094,7 +1141,7 @@ __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset + * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1112,7 +1159,7 @@ __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) /** * @brief Release APB1 peripherals reset. - * @rmtoll APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset + * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 @@ -1129,7 +1176,7 @@ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1156,7 +1203,7 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n * APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1179,7 +1226,7 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1198,7 +1245,7 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) /** * @brief Enable APB1 peripheral clocks in Sleep and Stop modes - * @rmtoll APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 @@ -1215,7 +1262,7 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) /** * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not - * @rmtoll APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockStopSleep + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 @@ -1228,10 +1275,9 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs) /** * @brief Disable APB1 peripheral clocks in Sleep and Stop modes - * @rmtoll APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) @@ -1557,7 +1603,7 @@ __STATIC_INLINE void LL_APB7_GRP1_DisableClock(uint32_t Periphs) * APB7RSTR LPUART1RST LL_APB7_GRP1_ForceReset\n * APB7RSTR I2C3RST LL_APB7_GRP1_ForceReset\n * APB7RSTR LPTIM1RST LL_APB7_GRP1_ForceReset\n - * APB7RSTR COMPRST LL_APB7_GRP1_ForceReset + * APB7RSTR COMPRST LL_APB7_GRP1_ForceReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB7_GRP1_PERIPH_ALL * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG @@ -1582,7 +1628,7 @@ __STATIC_INLINE void LL_APB7_GRP1_ForceReset(uint32_t Periphs) * APB7RSTR LPUART1RST LL_APB7_GRP1_ReleaseReset\n * APB7RSTR I2C3RST LL_APB7_GRP1_ReleaseReset\n * APB7RSTR LPTIM1RST LL_APB7_GRP1_ReleaseReset\n - * APB7RSTR COMPRST LL_APB7_GRP1_ReleaseReset + * APB7RSTR COMPRST LL_APB7_GRP1_ReleaseReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB7_GRP1_PERIPH_ALL * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_cortex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_cortex.h index 239bf6bcf..7ba4a5f9c 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_cortex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_cortex.h @@ -21,8 +21,9 @@ [..] The LL CORTEX driver contains a set of generic APIs that can be used by user: - (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick - functions + (+) SysTick configuration used by LL_mDelay and LL_Init1msTick with + HCLK source or LL_Init1msTick_HCLK_Div8 or LL_Init1msTick_LSI or + LL_Init1msTick_LSE with external source (+) Low power mode configuration (SCB register of Cortex-MCU) (+) API to access to MCU info (CPUID register) (+) API to enable fault handler (SHCSR accesses) @@ -74,13 +75,18 @@ extern "C" { /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source * @{ */ -#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick - clock source */ +#define LL_SYSTICK_CLKSOURCE_EXTERNAL 0x00000000U /*!< External clock source selected as + SysTick clock source */ #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source */ + +/** Legacy definitions for compatibility purpose +@cond 0 +*/ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 LL_SYSTICK_CLKSOURCE_EXTERNAL /** - * @} - */ +@endcond +*/ /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type * @{ @@ -227,7 +233,7 @@ __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) * @brief Configures the SysTick clock source * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK * @retval None */ @@ -247,7 +253,7 @@ __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) * @brief Get the SysTick clock source * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK */ __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_dma.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_dma.h index d2cba7b84..cafa3bac1 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_dma.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_dma.h @@ -309,7 +309,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t DestSecure; /*!< This field specify the destination secure. This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */ @@ -332,7 +332,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t SrcSecure; /*!< This field specify the source secure. This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */ @@ -452,7 +452,7 @@ typedef struct * @} */ -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ /* Exported constants --------------------------------------------------------*/ @@ -481,7 +481,7 @@ typedef struct #define LL_DMA_CHANNEL_15 (0x0FU) #if defined (USE_FULL_LL_DRIVER) #define LL_DMA_CHANNEL_ALL (0x10U) -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ /** * @} */ @@ -501,7 +501,7 @@ typedef struct /** * @} */ -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ /** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level * @{ @@ -732,7 +732,7 @@ typedef struct /** * @} */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type * @{ @@ -770,14 +770,14 @@ typedef struct #if defined (SPI1) #define LL_GPDMA1_REQUEST_SPI1_RX 1U /*!< GPDMA1 HW request is SPI1_RX */ #define LL_GPDMA1_REQUEST_SPI1_TX 2U /*!< GPDMA1 HW request is SPI1_TX */ -#endif /* defined (SPI1) */ +#endif /* SPI1 */ #define LL_GPDMA1_REQUEST_SPI3_RX 3U /*!< GPDMA1 HW request is SPI3_RX */ #define LL_GPDMA1_REQUEST_SPI3_TX 4U /*!< GPDMA1 HW request is SPI3_TX */ #if defined (I2C1) #define LL_GPDMA1_REQUEST_I2C1_RX 5U /*!< GPDMA1 HW request is I2C1_RX */ #define LL_GPDMA1_REQUEST_I2C1_TX 6U /*!< GPDMA1 HW request is I2C1_TX */ #define LL_GPDMA1_REQUEST_I2C1_EVC 7U /*!< GPDMA1 HW request is I2C1_EVC */ -#endif /* defined (I2C1) */ +#endif /* I2C1 */ #define LL_GPDMA1_REQUEST_I2C3_RX 8U /*!< GPDMA1 HW request is I2C3_RX */ #define LL_GPDMA1_REQUEST_I2C3_TX 9U /*!< GPDMA1 HW request is I2C3_TX */ #define LL_GPDMA1_REQUEST_I2C3_EVC 10U /*!< GPDMA1 HW request is I2C3_EVC */ @@ -786,13 +786,13 @@ typedef struct #if defined (USART2) #define LL_GPDMA1_REQUEST_USART2_RX 13U /*!< GPDMA1 HW request is USART2_RX */ #define LL_GPDMA1_REQUEST_USART2_TX 14U /*!< GPDMA1 HW request is USART2_TX */ -#endif /* defined (USART2) */ +#endif /* USART2 */ #define LL_GPDMA1_REQUEST_LPUART1_RX 15U /*!< GPDMA1 HW request is LPUART1_RX */ #define LL_GPDMA1_REQUEST_LPUART1_TX 16U /*!< GPDMA1 HW request is LPUART1_TX */ #if defined (SAI1) #define LL_GPDMA1_REQUEST_SAI1_A 17U /*!< GPDMA1 HW request is SAI1_A */ #define LL_GPDMA1_REQUEST_SAI1_B 18U /*!< GPDMA1 HW request is SAI1_B */ -#endif /* defined (SAI1) */ +#endif /* SAI1 */ #define LL_GPDMA1_REQUEST_TIM1_CH1 19U /*!< GPDMA1 HW request is TIM1_CH1 */ #define LL_GPDMA1_REQUEST_TIM1_CH2 20U /*!< GPDMA1 HW request is TIM1_CH2 */ #define LL_GPDMA1_REQUEST_TIM1_CH3 21U /*!< GPDMA1 HW request is TIM1_CH3 */ @@ -812,22 +812,22 @@ typedef struct #define LL_GPDMA1_REQUEST_TIM3_CH4 34U /*!< GPDMA1 HW request is TIM3_CH4 */ #define LL_GPDMA1_REQUEST_TIM3_UP 35U /*!< GPDMA1 HW request is TIM3_UP */ #define LL_GPDMA1_REQUEST_TIM3_TRIG 36U /*!< GPDMA1 HW request is TIM3_TRIG */ -#endif /* defined (TIM3) */ +#endif /* TIM3 */ #define LL_GPDMA1_REQUEST_TIM16_CH1 37U /*!< GPDMA1 HW request is TIM16_CH1 */ #define LL_GPDMA1_REQUEST_TIM16_UP 38U /*!< GPDMA1 HW request is TIM16_UP */ #if defined (TIM17) #define LL_GPDMA1_REQUEST_TIM17_CH1 39U /*!< GPDMA1 HW request is TIM17_CH1 */ #define LL_GPDMA1_REQUEST_TIM17_UP 40U /*!< GPDMA1 HW request is TIM17_UP */ -#endif /* defined (TIM17) */ +#endif /* TIM17 */ #if defined (AES) #define LL_GPDMA1_REQUEST_AES_IN 41U /*!< GPDMA1 HW request is AES_IN */ #define LL_GPDMA1_REQUEST_AES_OUT 42U /*!< GPDMA1 HW request is AES_OUT */ -#endif /* defined (AES) */ +#endif /* AES */ #define LL_GPDMA1_REQUEST_HASH_IN 43U /*!< GPDMA1 HW request is HASH_IN */ #if defined (SAES) #define LL_GPDMA1_REQUEST_SAES_IN 44U /*!< GPDMA1 HW request is SAES_IN */ #define LL_GPDMA1_REQUEST_SAES_OUT 45U /*!< GPDMA1 HW request is SAES_OUT */ -#endif /* defined (SAES) */ +#endif /* SAES */ #define LL_GPDMA1_REQUEST_LPTIM1_IC1 46U /*!< GPDMA1 HW request is LPTIM1_IC1 */ #define LL_GPDMA1_REQUEST_LPTIM1_IC2 47U /*!< GPDMA1 HW request is LPTIM1_IC2 */ #define LL_GPDMA1_REQUEST_LPTIM1_UE 48U /*!< GPDMA1 HW request is LPTIM1_UE */ @@ -835,7 +835,7 @@ typedef struct #define LL_GPDMA1_REQUEST_LPTIM2_IC1 49U /*!< GPDMA1 HW request is LPTIM2_IC1 */ #define LL_GPDMA1_REQUEST_LPTIM2_IC2 50U /*!< GPDMA1 HW request is LPTIM2_IC2 */ #define LL_GPDMA1_REQUEST_LPTIM2_UE 51U /*!< GPDMA1 HW request is LPTIM2_UE */ -#endif /* defined (LPTIM2) */ +#endif /* LPTIM2 */ /** * @} @@ -861,13 +861,13 @@ typedef struct #if defined (LPTIM2) #define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ #define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ -#endif /* defined (LPTIM2) */ +#endif /* LPTIM2 */ #if defined (COMP1) #define LL_GPDMA1_TRIGGER_COMP1_OUT 15U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ -#endif /* defined (COMP1) */ +#endif /* COMP1 */ #if defined (COMP2) #define LL_GPDMA1_TRIGGER_COMP2_OUT 16U /*!< GPDMA1 HW Trigger signal is COMP2_OUT */ -#endif /* defined (COMP2) */ +#endif /* COMP2 */ #define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 17U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ #define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 18U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ #define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 19U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ @@ -883,7 +883,7 @@ typedef struct #define LL_GPDMA1_TRIGGER_ADC4_AWD1 29U /*!< GPDMA1 HW Trigger signal is ADC4_ADW1 */ #if defined (TIM3) #define LL_GPDMA1_TRIGGER_TIM3_TRGO 30U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ -#endif /* defined (TIM3) */ +#endif /* TIM3 */ /** * @} */ @@ -1517,7 +1517,9 @@ __STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, ui uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC); } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined (DMA_SECCFGR_SEC0) /** * @brief Check security attribute of the DMA transfer to the destination. * @note This API is used for all available DMA channels. @@ -1540,7 +1542,9 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DM return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC) == (DMA_CTR1_DSEC)) ? 1UL : 0UL); } +#endif /* DMA_SECCFGR_SEC0 */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Enable security attribute of the DMA transfer from the source. * @note This API is used for all available DMA channels. @@ -1584,7 +1588,9 @@ __STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uin uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined (DMA_SECCFGR_SEC0) /** * @brief Check security attribute of the DMA transfer from the source. * @note This API is used for all available DMA channels. @@ -1607,7 +1613,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMA return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC) == (DMA_CTR1_SSEC)) ? 1UL : 0UL); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* DMA_SECCFGR_SEC0 */ /** * @brief Set destination allocated port. @@ -2216,7 +2222,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_ * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK - * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or * @ref LL_DMA_TRIG_POLARITY_FALLING * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER @@ -2976,7 +2982,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_UPDATE_CSAR * @arg @ref LL_DMA_UPDATE_CDAR * @arg @ref LL_DMA_UPDATE_CLLR - * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 (4 Bytes) + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. * @retval None. */ __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate, @@ -3405,7 +3411,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uin * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 - * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 (4 Bytes) + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. * @retval None. */ __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel, @@ -3503,7 +3509,9 @@ __STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Cha { CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))); } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined (DMA_SECCFGR_SEC0) /** * @brief Check if DMA channel secure is enabled. * @note This API is used for all available DMA channels. @@ -3525,7 +3533,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* DMA_SECCFGR_SEC0 */ #if defined (DMA_PRIVCFGR_PRIV0) /** * @brief Enable the DMA channel privilege attribute. @@ -3590,7 +3598,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMA return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); } -#endif /* defined (DMA_PRIVCFGR_PRIV0) */ +#endif /* DMA_PRIVCFGR_PRIV0 */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Enable the DMA channel lock attributes. @@ -3612,7 +3620,7 @@ __STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32 { SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #if defined (DMA_RCFGLOCKR_LOCK0) /** * @brief Check if DMA channel attributes are locked. @@ -3636,7 +3644,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); } -#endif /* defined (DMA_RCFGLOCKR_LOCK0) */ +#endif /* DMA_RCFGLOCKR_LOCK0 */ /** * @} */ @@ -4027,7 +4035,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint3 return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @} */ @@ -4530,7 +4538,7 @@ void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32 /** * @} */ -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ /** * @} @@ -4540,7 +4548,7 @@ void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32 * @} */ -#endif /* defined (GPDMA1) */ +#endif /* GPDMA1 */ /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_gpio.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_gpio.h index 1f7dbbcbc..ad2afbee3 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_gpio.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_gpio.h @@ -283,7 +283,8 @@ typedef struct */ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) { - MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)), + (Mode << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))); } /** @@ -317,8 +318,8 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 */ __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->MODER, - (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); + return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)); } /** @@ -422,8 +423,8 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uin */ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) { - MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)), - (Speed << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)), + (Speed << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))); } /** @@ -458,8 +459,8 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint */ __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, - (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)); } /** @@ -492,7 +493,8 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t */ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) { - MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)), + (Pull << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))); } /** @@ -524,8 +526,8 @@ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 */ __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->PUPDR, - (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); + return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)); } /** @@ -564,8 +566,8 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t */ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)), - (Alternate << (POSITION_VAL(Pin) * 4U))); + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)), + (Alternate << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))); } /** @@ -601,8 +603,8 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin */ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->AFR[0], - (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); + return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)); } /** @@ -641,8 +643,8 @@ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_ */ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)), - (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)), + (Alternate << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))); } /** @@ -679,8 +681,8 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui */ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->AFR[1], - (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); + return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))) + >> (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)); } diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_i2c.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_i2c.h index 9fe93a08c..fec55e843 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_i2c.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_i2c.h @@ -2317,11 +2317,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); + tmp); } /** diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_pwr.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_pwr.h index 0f5a80751..d32643d0d 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_pwr.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_pwr.h @@ -99,16 +99,16 @@ extern "C" { * @} */ -/** @defgroup PWR_LL_EC_SRAM1_SB_CONTENTS_RETENTION PWR SRAM1 Content Retention in Standby Mode +/** @defgroup PWR_LL_EC_SRAM1_SB_RETENTION PWR SRAM1 Retention in Standby Mode * @{ */ -#define LL_PWR_SRAM1_SB_NO_RETENTION 0U /*!< SRAM1 no retention in Standby mode */ -#define LL_PWR_SRAM1_SB_FULL_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 all pages retention in Standby mode */ +#define LL_PWR_SRAM1_SB_NO_RETENTION 0U /*!< SRAM1 no retention in Standby mode */ +#define LL_PWR_SRAM1_SB_FULL_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 all pages retention in Standby mode */ /** * @} */ -/** @defgroup PWR_LL_EC_SRAM2_SB_CONTENTS_RETENTION PWR SRAM2 Content Retention in Standby Mode +/** @defgroup PWR_LL_EC_SRAM2_SB_RETENTION PWR SRAM2 Retention in Standby Mode * @{ */ #define LL_PWR_SRAM2_SB_NO_RETENTION 0U /*!< SRAM2 no retention in Standby mode */ @@ -117,7 +117,7 @@ extern "C" { * @} */ -/** @defgroup PWR_LL_EC_RADIO_SB_CONTENTS_RETENTION PWR RADIO SRAMs and Sleep Clock Retention in Standby Mode +/** @defgroup PWR_LL_EC_RADIO_SB_RETENTION PWR RADIO SRAMs and Sleep Clock Retention in Standby Mode * @{ */ #define LL_PWR_RADIO_SB_NO_RETENTION 0U /*!< 2.4 GHz RADIO SRAMs and sleep timer content not retained in Standby mode */ @@ -126,29 +126,29 @@ extern "C" { * @} */ -/** @defgroup PWR_LL_EC_SRAM1_STOP_CONTENTS_RETENTION PWR SRAM1 Content Retention in Stop Mode +/** @defgroup PWR_LL_EC_SRAM1_STOP_RETENTION PWR SRAM1 Retention in Stop Mode * @{ */ -#define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode (Stop 0, 1) */ -#define LL_PWR_SRAM1_STOP_FULL_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 all pages retention in Stop mode (Stop 0, 1) */ +#define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode */ +#define LL_PWR_SRAM1_STOP_FULL_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 all pages retention in Stop mode */ /** * @} */ -/** @defgroup PWR_LL_EC_SRAM2_STOP_CONTENTS_RETENTION PWR SRAM2 Content Retention in Stop Mode +/** @defgroup PWR_LL_EC_SRAM2_STOP_RETENTION PWR SRAM2 Retention in Stop Mode * @{ */ -#define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode (Stop 0, 1) */ -#define LL_PWR_SRAM2_STOP_FULL_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 all pages retention in Stop mode (Stop 0, 1) */ +#define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode */ +#define LL_PWR_SRAM2_STOP_FULL_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 all pages retention in Stop mode */ /** * @} */ -/** @defgroup PWR_LL_EC_ICACHERAM_STOP_CONTENTS_RETENTION PWR ICACHE SRAM Content Retention in Stop Mode +/** @defgroup PWR_LL_EC_ICACHERAM_STOP_RETENTION PWR ICACHE SRAM Retention in Stop Mode * @{ */ -#define LL_PWR_ICACHERAM_STOP_NO_RETENTION 0U /*!< ICACHE SRAM no retention in Stop mode (Stop 0, 1) */ -#define LL_PWR_ICACHERAM_STOP_FULL_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM all pages retention in Stop mode (Stop 0, 1) */ +#define LL_PWR_ICACHERAM_STOP_NO_RETENTION 0U /*!< ICACHE SRAM no retention in Stop mode */ +#define LL_PWR_ICACHERAM_STOP_FULL_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM full retention in Stop mode */ /** * @} */ @@ -373,7 +373,7 @@ extern "C" { /** * @brief Set system power mode. - * @rmtoll CR1 LPMS LL_PWR_SetPowerMode + * @rmtoll CR1 LPMS LL_PWR_SetPowerMode * @param Mode This parameter can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STOP1 @@ -387,7 +387,7 @@ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode) /** * @brief Get system power mode. - * @rmtoll CR1 LPMS LL_PWR_GetPowerMode + * @rmtoll CR1 LPMS LL_PWR_GetPowerMode * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STOP1 @@ -400,7 +400,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) /** * @brief Set the SRAM2 page(s) retention in Standby mode. - * @rmtoll CR1 R2RSB1 LL_PWR_SetSRAM2SBRetention + * @rmtoll CR1 R2RSB1 LL_PWR_SetSRAM2SBRetention * @param SRAM2PageRetention This parameter can be one of the following values: * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION @@ -413,7 +413,7 @@ __STATIC_INLINE void LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention) /** * @brief Get the SRAM2 page(s) retention in Standby mode. - * @rmtoll CR1 R2RSB1 LL_PWR_GetSRAM2SBRetention + * @rmtoll CR1 R2RSB1 LL_PWR_GetSRAM2SBRetention * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION @@ -425,7 +425,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetSRAM2SBRetention(void) /** * @brief Set the SRAM1 page(s) retention in Standby mode. - * @rmtoll CR1 R1RSB1 LL_PWR_SetSRAM1SBRetention + * @rmtoll CR1 R1RSB1 LL_PWR_SetSRAM1SBRetention * @param SRAM1PageRetention This parameter can be one of the following values: * @arg @ref LL_PWR_SRAM1_SB_NO_RETENTION * @arg @ref LL_PWR_SRAM1_SB_FULL_RETENTION @@ -438,7 +438,7 @@ __STATIC_INLINE void LL_PWR_SetSRAM1SBRetention(uint32_t SRAM1PageRetention) /** * @brief Get the SRAM1 page(s) retention in Standby mode. - * @rmtoll CR1 R1RSB1 LL_PWR_GetSRAM1SBRetention + * @rmtoll CR1 R1RSB1 LL_PWR_GetSRAM1SBRetention * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_SRAM1_SB_NO_RETENTION * @arg @ref LL_PWR_SRAM1_SB_FULL_RETENTION @@ -450,7 +450,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetSRAM1SBRetention(void) /** * @brief Set the Radio retention in Standby mode. - * @rmtoll CR1 RADIORSB LL_PWR_SetRadioSBRetention + * @rmtoll CR1 RADIORSB LL_PWR_SetRadioSBRetention * @param RadioRetention This parameter can be one of the following values: * @arg @ref LL_PWR_RADIO_SB_NO_RETENTION * @arg @ref LL_PWR_RADIO_SB_FULL_RETENTION @@ -463,7 +463,7 @@ __STATIC_INLINE void LL_PWR_SetRadioSBRetention(uint32_t RadioRetention) /** * @brief Get the Radio retention in Standby mode. - * @rmtoll CR1 RADIORSB LL_PWR_GetRadioSBRetention + * @rmtoll CR1 RADIORSB LL_PWR_GetRadioSBRetention * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_RADIO_SB_NO_RETENTION * @arg @ref LL_PWR_RADIO_SB_FULL_RETENTION @@ -475,7 +475,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetRadioSBRetention(void) /** * @brief Enable BOR ultra low power mode. - * @rmtoll CR1 UPLMEN LL_PWR_EnableUltraLowPowerMode + * @rmtoll CR1 UPLMEN LL_PWR_EnableUltraLowPowerMode * @retval None */ __STATIC_INLINE void LL_PWR_EnableUltraLowPowerMode(void) @@ -485,7 +485,7 @@ __STATIC_INLINE void LL_PWR_EnableUltraLowPowerMode(void) /** * @brief Disable BOR ultra low-power mode. - * @rmtoll CR1 UPLMEN LL_PWR_DisableUltraLowPowerMode + * @rmtoll CR1 UPLMEN LL_PWR_DisableUltraLowPowerMode * @retval None */ __STATIC_INLINE void LL_PWR_DisableUltraLowPowerMode(void) @@ -495,7 +495,7 @@ __STATIC_INLINE void LL_PWR_DisableUltraLowPowerMode(void) /** * @brief Check if BOR ultra low power mode is enabled. - * @rmtoll CR1 UPLMEN LL_PWR_IsEnabledUltraLowPowerMode + * @rmtoll CR1 UPLMEN LL_PWR_IsEnabledUltraLowPowerMode * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void) @@ -506,7 +506,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void) /** * @brief Set the SRAM1 page(s) retention in Stop mode. - * @rmtoll CR2 SRAM1PDS1 LL_PWR_SetSRAM1StopRetention + * @rmtoll CR2 SRAM1PDS1 LL_PWR_SetSRAM1StopRetention * @param SRAM1PageRetention This parameter can be one of the following values: * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION * @arg @ref LL_PWR_SRAM1_STOP_FULL_RETENTION @@ -519,7 +519,7 @@ __STATIC_INLINE void LL_PWR_SetSRAM1StopRetention(uint32_t SRAM1PageRetention) /** * @brief Get the SRAM1 page(s) retention in Stop mode. - * @rmtoll CR2 SRAM1PDS1 LL_PWR_GetSRAM1StopRetention + * @rmtoll CR2 SRAM1PDS1 LL_PWR_GetSRAM1StopRetention * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION * @arg @ref LL_PWR_SRAM1_STOP_FULL_RETENTION @@ -531,7 +531,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention(void) /** * @brief Set the SRAM2 page(s) retention in Stop mode. - * @rmtoll CR2 SRAM2PDS1 LL_PWR_SetSRAM2StopRetention + * @rmtoll CR2 SRAM2PDS1 LL_PWR_SetSRAM2StopRetention * @param SRAM2PageRetention This parameter can be one of the following values: * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION @@ -544,7 +544,7 @@ __STATIC_INLINE void LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention) /** * @brief Get the SRAM2 page(s) retention in Stop mode. - * @rmtoll CR2 SRAM2PDS1 LL_PWR_GetSRAM2StopRetention + * @rmtoll CR2 SRAM2PDS1 LL_PWR_GetSRAM2StopRetention * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION @@ -556,9 +556,11 @@ __STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void) /** * @brief Set the ICACHE SRAM page(s) retention in Stop mode. - * @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention + * @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention +#if defined(STM32WBAXX_SI_CUT1_0) * @note On Silicon Cut 1.0, it is mandatory to disable the ICACHE before going into * stop modes otherwise an hard fault may occur when waking up from stop modes. +#endif * @param ICRAMPageRetention This parameter can be one of the following values: * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION @@ -572,7 +574,7 @@ __STATIC_INLINE void LL_PWR_SetICacheRAMStopRetention(uint32_t ICRAMPageRetentio /** * @brief Get the ICACHE SRAM page(s) retention in Stop mode. - * @rmtoll CR2 ICRAMPDS LL_PWR_GetICacheRAMStopRetention + * @rmtoll CR2 ICRAMPDS LL_PWR_GetICacheRAMStopRetention * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION @@ -584,7 +586,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetICacheRAMStopRetention(void) /** * @brief Enable the flash memory fast wakeup from Stop mode (Stop 0, 1). - * @rmtoll CR2 FLASHFWU LL_PWR_EnableFlashFastWakeUp + * @rmtoll CR2 FLASHFWU LL_PWR_EnableFlashFastWakeUp * @retval None */ __STATIC_INLINE void LL_PWR_EnableFlashFastWakeUp(void) @@ -594,7 +596,7 @@ __STATIC_INLINE void LL_PWR_EnableFlashFastWakeUp(void) /** * @brief Disable the flash memory fast wakeup from Stop mode (Stop 0, 1). - * @rmtoll CR2 FLASHFWU LL_PWR_DisableFlashFastWakeUp + * @rmtoll CR2 FLASHFWU LL_PWR_DisableFlashFastWakeUp * @retval None */ __STATIC_INLINE void LL_PWR_DisableFlashFastWakeUp(void) @@ -603,9 +605,8 @@ __STATIC_INLINE void LL_PWR_DisableFlashFastWakeUp(void) } /** - * @brief Check if the flash memory fast wakeup from Stop mode (Stop 0, 1) - * is enabled. - * @rmtoll CR2 FLASHFWU LL_PWR_IsEnabledFlashFastWakeUp + * @brief Check if the flash memory fast wakeup from Stop mode (Stop 0, 1) is enabled. + * @rmtoll CR2 FLASHFWU LL_PWR_IsEnabledFlashFastWakeUp * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashFastWakeUp(void) @@ -616,7 +617,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashFastWakeUp(void) #if defined(PWR_CR3_REGSEL) /** * @brief Set the VCore regulator supply. - * @rmtoll CR3 REGSEL LL_PWR_SetRegulatorSupply + * @rmtoll CR3 REGSEL LL_PWR_SetRegulatorSupply * @param RegulatorSupply This parameter can be one of the following values: * @arg @ref LL_PWR_LDO_SUPPLY * @arg @ref LL_PWR_SMPS_SUPPLY @@ -629,7 +630,7 @@ __STATIC_INLINE void LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply) /** * @brief Get the VCore regulator supply. - * @rmtoll CR3 REGSEL LL_PWR_GetRegulatorSupply + * @rmtoll CR3 REGSEL LL_PWR_GetRegulatorSupply * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_LDO_SUPPLY * @arg @ref LL_PWR_SMPS_SUPPLY @@ -643,7 +644,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulatorSupply(void) #if defined(PWR_CR2_FPWM) /** * @brief Enable the SMPS PWM mode. - * @rmtoll CR2 FPWM LL_PWR_EnableSMPSPWMMode + * @rmtoll CR2 FPWM LL_PWR_EnableSMPSPWMMode * @retval None */ __STATIC_INLINE void LL_PWR_EnableSMPSPWMMode(void) @@ -653,7 +654,7 @@ __STATIC_INLINE void LL_PWR_EnableSMPSPWMMode(void) /** * @brief Disable the SMPS PWM mode. - * @rmtoll CR2 FPWM LL_PWR_DisableSMPSPWMMode + * @rmtoll CR2 FPWM LL_PWR_DisableSMPSPWMMode * @retval None */ __STATIC_INLINE void LL_PWR_DisableSMPSPWMMode(void) @@ -663,7 +664,7 @@ __STATIC_INLINE void LL_PWR_DisableSMPSPWMMode(void) /** * @brief Check if the SMPS PWM mode is enabled. - * @rmtoll CR2 FPWM LL_PWR_IsEnabledSMPSPWMMode + * @rmtoll CR2 FPWM LL_PWR_IsEnabledSMPSPWMMode * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSPWMMode(void) @@ -674,7 +675,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSPWMMode(void) /** * @brief Enable the fast soft start for selected regulator. - * @rmtoll CR3 FSTEN LL_PWR_EnableFastSoftStart + * @rmtoll CR3 FSTEN LL_PWR_EnableFastSoftStart * @retval None */ __STATIC_INLINE void LL_PWR_EnableFastSoftStart(void) @@ -684,7 +685,7 @@ __STATIC_INLINE void LL_PWR_EnableFastSoftStart(void) /** * @brief Disable the fast soft start for selected regulator. - * @rmtoll CR3 FSTEN LL_PWR_DisableFastSoftStart + * @rmtoll CR3 FSTEN LL_PWR_DisableFastSoftStart * @retval None */ __STATIC_INLINE void LL_PWR_DisableFastSoftStart(void) @@ -694,7 +695,7 @@ __STATIC_INLINE void LL_PWR_DisableFastSoftStart(void) /** * @brief Check if the fast soft start for selected regulator is enabled. - * @rmtoll CR3 FSTEN LL_PWR_IsEnabledFastSoftStart + * @rmtoll CR3 FSTEN LL_PWR_IsEnabledFastSoftStart * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledFastSoftStart(void) @@ -704,7 +705,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledFastSoftStart(void) /** * @brief Set the regulator supply output voltage. - * @rmtoll VOSR VOS LL_PWR_SetRegulVoltageScaling + * @rmtoll VOSR VOS LL_PWR_SetRegulVoltageScaling * @param VoltageScaling This parameter can be one of the following values: * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 @@ -717,7 +718,7 @@ __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) /** * @brief Get the regulator supply output voltage. - * @rmtoll VOSR VOS LL_PWR_GetRegulVoltageScaling + * @rmtoll VOSR VOS LL_PWR_GetRegulVoltageScaling * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 @@ -729,7 +730,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) /** * @brief Set the Power voltage detector level. - * @rmtoll SVMCR PVDLS LL_PWR_SetPVDLevel + * @rmtoll SVMCR PVDLS LL_PWR_SetPVDLevel * @param PVDLevel This parameter can be one of the following values: * @arg @ref LL_PWR_PVDLEVEL_0 * @arg @ref LL_PWR_PVDLEVEL_1 @@ -748,7 +749,7 @@ __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) /** * @brief Get the Power voltage detector level. - * @rmtoll SVMCR PVDLS LL_PWR_GetPVDLevel + * @rmtoll SVMCR PVDLS LL_PWR_GetPVDLevel * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_PVDLEVEL_0 * @arg @ref LL_PWR_PVDLEVEL_1 @@ -766,7 +767,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) /** * @brief Enable the power voltage detector. - * @rmtoll SVMCR PVDE LL_PWR_EnablePVD + * @rmtoll SVMCR PVDE LL_PWR_EnablePVD * @retval None */ __STATIC_INLINE void LL_PWR_EnablePVD(void) @@ -776,7 +777,7 @@ __STATIC_INLINE void LL_PWR_EnablePVD(void) /** * @brief Disable the power voltage detector. - * @rmtoll SVMCR PVDE LL_PWR_DisablePVD + * @rmtoll SVMCR PVDE LL_PWR_DisablePVD * @retval None */ __STATIC_INLINE void LL_PWR_DisablePVD(void) @@ -786,7 +787,7 @@ __STATIC_INLINE void LL_PWR_DisablePVD(void) /** * @brief Check if the power voltage detector is enabled. - * @rmtoll SVMCR PVDE LL_PWR_IsEnabledPVD + * @rmtoll SVMCR PVDE LL_PWR_IsEnabledPVD * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) @@ -796,7 +797,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) /** * @brief Enable the wake up pin_x. - * @rmtoll WUCR1 WUPENx LL_PWR_EnableWakeUpPin + * @rmtoll WUCR1 WUPENx LL_PWR_EnableWakeUpPin * @param WakeUpPin This parameter can be a combination of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -815,7 +816,7 @@ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) /** * @brief Disable the wake up pin_x. - * @rmtoll WUCR1 WUPENx LL_PWR_DisableWakeUpPin + * @rmtoll WUCR1 WUPENx LL_PWR_DisableWakeUpPin * @param WakeUpPin This parameter can be a combination of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -834,7 +835,7 @@ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) /** * @brief Check if the wake up pin_x is enabled. - * @rmtoll WUCR1 WUPENx LL_PWR_IsEnabledWakeUpPin + * @rmtoll WUCR1 WUPENx LL_PWR_IsEnabledWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -853,7 +854,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) /** * @brief Set the wake up pin polarity low for the event detection. - * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityLow + * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityLow * @param WakeUpPin This parameter can be a combination of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -872,7 +873,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) /** * @brief Set the wake up pin polarity high for the event detection. - * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityHigh + * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityHigh * @param WakeUpPin This parameter can be a combination of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -891,7 +892,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) /** * @brief Get the wake up pin polarity for the event detection. - * @rmtoll WUCR2 WUPPx LL_PWR_GetWakeUpPinPolarity + * @rmtoll WUCR2 WUPPx LL_PWR_GetWakeUpPinPolarity * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -910,7 +911,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin) /** * @brief Set the wakeup pin_x selection 0. - * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal0Selection + * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal0Selection * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -930,7 +931,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin) /** * @brief Set the wakeup pin_x selection 1. - * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal1Selection + * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal1Selection * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -950,7 +951,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin) /** * @brief Set the wakeup pin_x selection 2. - * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal2Selection + * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal2Selection * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -970,7 +971,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin) /** * @brief Set the wakeup pin_x selection 3. - * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal3Selection + * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal3Selection * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -990,7 +991,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin) /** * @brief Get the wakeup pin_x selection. - * @rmtoll WUCR3 WUSELx LL_PWR_GetWakeUpPinSignalSelection + * @rmtoll WUCR3 WUSELx LL_PWR_GetWakeUpPinSignalSelection * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -1006,12 +1007,9 @@ __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin) return (READ_BIT(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)))); } - - - /** * @brief Enable access to the backup domain. - * @rmtoll DBPR DBP LL_PWR_EnableBkUpAccess + * @rmtoll DBPR DBP LL_PWR_EnableBkUpAccess * @retval None */ __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) @@ -1021,7 +1019,7 @@ __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) /** * @brief Disable access to the backup domain. - * @rmtoll DBPR DBP LL_PWR_DisableBkUpAccess + * @rmtoll DBPR DBP LL_PWR_DisableBkUpAccess * @retval None */ __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) @@ -1031,7 +1029,7 @@ __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) /** * @brief Check if the access to backup domain is enabled. - * @rmtoll DBPR DBP LL_PWR_IsEnabledBkUpAccess + * @rmtoll DBPR DBP LL_PWR_IsEnabledBkUpAccess * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) @@ -1039,12 +1037,9 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) return ((READ_BIT(PWR->DBPR, PWR_DBPR_DBP) == (PWR_DBPR_DBP)) ? 1UL : 0UL); } - - - /** * @brief Enable GPIO retention in Standby mode - * @rmtoll IORETENRx ENx LL_PWR_EnableGPIOStandbyRetention + * @rmtoll IORETENRx ENx LL_PWR_EnableGPIOStandbyRetention * @param GPIOPort This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB @@ -1074,10 +1069,9 @@ __STATIC_INLINE void LL_PWR_EnableGPIOStandbyRetention(uint32_t GPIOPort, uint32 SET_BIT(*((__IO uint32_t *)GPIOPort), GPIOPin); } - /** * @brief Disable GPIO retention in Standby mode - * @rmtoll IORETENRx ENx LL_PWR_DisableGPIOStandbyRetention + * @rmtoll IORETENRx ENx LL_PWR_DisableGPIOStandbyRetention * @param GPIOPort This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB @@ -1107,11 +1101,9 @@ __STATIC_INLINE void LL_PWR_DisableGPIOStandbyRetention(uint32_t GPIOPort, uint3 CLEAR_BIT(*((__IO uint32_t *)GPIOPort), GPIOPin); } - - /** * @brief Check if GPIO retention is enabled in Standby mode - * @rmtoll IORETENRx ENx LL_PWR_IsEnabledGPIOStandbyRetention + * @rmtoll IORETENRx ENx LL_PWR_IsEnabledGPIOStandbyRetention * @param GPIOPort This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB @@ -1143,7 +1135,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOStandbyRetention(uint32_t GPIOPort, /** * @brief Check if GPIO state was retained after Standby mode entry - * @rmtoll IORETRx RETx LL_PWR_IsGPIOStandbyStateRetained + * @rmtoll IORETRx RETx LL_PWR_IsGPIOStandbyStateRetained * @param GPIOPort This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB @@ -1175,7 +1167,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsGPIOStandbyStateRetained(uint32_t GPIOPort, ui /** * @brief Clear GPIO state retention status after Standby mode entry - * @rmtoll IORETRx RETx LL_PWR_ClearGPIOStandbyRetentionStatus + * @rmtoll IORETRx RETx LL_PWR_ClearGPIOStandbyRetentionStatus * @param GPIOPort This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB @@ -1207,7 +1199,7 @@ __STATIC_INLINE void LL_PWR_ClearGPIOStandbyRetentionStatus(uint32_t GPIOPort, u /** * @brief Get currently voltage scaling applied to VCORE. - * @rmtoll SVMSR ACTVOS LL_PWR_GetRegulCurrentVOS + * @rmtoll SVMSR ACTVOS LL_PWR_GetRegulCurrentVOS * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 @@ -1228,7 +1220,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulCurrentVOS(void) #if defined(PWR_RADIOSCR_REGPABYPEN) /** * @brief Enable regulator REG_VDDHPA bypass. - * @rmtoll RADIOSCR REGPABYPEN LL_PWR_EnableREGVDDHPABypass + * @rmtoll RADIOSCR REGPABYPEN LL_PWR_EnableREGVDDHPABypass * @note This bit shall only be written when the VDDHPA regulator is not used (When REGPASEL = 0) * @retval None */ @@ -1239,7 +1231,7 @@ __STATIC_INLINE void LL_PWR_EnableREGVDDHPABypass(void) /** * @brief Disable regulator REG_VDDHPA bypass. - * @rmtoll RADIOSCR REGPABYPEN LL_PWR_DisableREGVDDHPABypass + * @rmtoll RADIOSCR REGPABYPEN LL_PWR_DisableREGVDDHPABypass * @retval None */ __STATIC_INLINE void LL_PWR_DisableREGVDDHPABypass(void) @@ -1249,7 +1241,7 @@ __STATIC_INLINE void LL_PWR_DisableREGVDDHPABypass(void) /** * @brief Check if regulator REG_VDDHPA bypass is enabled. - * @rmtoll RADIOSCR REGPABYPEN LL_PWR_IsEnabledREGVDDHPABypass + * @rmtoll RADIOSCR REGPABYPEN LL_PWR_IsEnabledREGVDDHPABypass * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledREGVDDHPABypass(void) @@ -1261,7 +1253,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledREGVDDHPABypass(void) #if defined(PWR_RADIOSCR_REGPASEL) /** * @brief Set regulator REG_VDDHPA input supply. - * @rmtoll RADIOSCR REGPASEL LL_PWR_SetREGVDDHPAInputSupply + * @rmtoll RADIOSCR REGPASEL LL_PWR_SetREGVDDHPAInputSupply * @note This bit shall only be written when the VDDHPA regulator is not used (When REGPASEL = 0) * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_PIN * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_VDD11 @@ -1274,7 +1266,7 @@ __STATIC_INLINE void LL_PWR_SetREGVDDHPAInputSupply(uint32_t InputSupply) /** * @brief Get regulator REG_VDDHPA input supply. - * @rmtoll RADIOSCR REGPASEL LL_PWR_GetREGVDDHPAInputSupply + * @rmtoll RADIOSCR REGPASEL LL_PWR_GetREGVDDHPAInputSupply * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_PIN * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_VDD11 @@ -1287,7 +1279,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetREGVDDHPAInputSupply(void) /** * @brief Indicate whether the VDDHPA voltage output is ready when selecting VDDRFPA input. - * @rmtoll RADIOSCR REGPARDYVDDRFPA LL_PWR_IsActiveFlag_REGPARDYVDDRFPA + * @rmtoll RADIOSCR REGPARDYVDDRFPA LL_PWR_IsActiveFlag_REGPARDYVDDRFPA * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGPARDYVDDRFPA(void) @@ -1298,7 +1290,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGPARDYVDDRFPA(void) #if defined(PWR_RADIOSCR_REGPARDYV11) /** * @brief Indicate whether the VDDHPA voltage output is ready when selecting VDD11 input. - * @rmtoll RADIOSCR REGPARDYV11 LL_PWR_IsActiveFlag_REGPARDYV11 + * @rmtoll RADIOSCR REGPARDYV11 LL_PWR_IsActiveFlag_REGPARDYV11 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGPARDYV11(void) @@ -1309,7 +1301,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGPARDYV11(void) /** * @brief Get 2.4 GHz RADIO VDDHPA control word. - * @rmtoll RADIOSCR RFVDDHPA LL_PWR_GetRadioVDDHPAControlWord + * @rmtoll RADIOSCR RFVDDHPA LL_PWR_GetRadioVDDHPAControlWord * @retval 4-bit control word. */ __STATIC_INLINE uint32_t LL_PWR_GetRadioVDDHPAControlWord(void) @@ -1319,7 +1311,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetRadioVDDHPAControlWord(void) /** * @brief Indicate whether the 2.4 GHz RADIO encryption function is enabled - * @rmtoll RADIOSCR ENCMODE LL_PWR_IsEnabledRadioEncryption + * @rmtoll RADIOSCR ENCMODE LL_PWR_IsEnabledRadioEncryption * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledRadioEncryption(void) @@ -1329,7 +1321,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledRadioEncryption(void) /** * @brief Get 2.4 GHz RADIO PHY operating mode. - * @rmtoll RADIOSCR PHYMODE LL_PWR_GetRadioPhyMode + * @rmtoll RADIOSCR PHYMODE LL_PWR_GetRadioPhyMode * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_RADIO_PHY_SLEEP_MODE * @arg @ref LL_PWR_RADIO_PHY_STANDBY_MODE @@ -1341,7 +1333,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetRadioPhyMode(void) /** * @brief Get 2.4 GHz RADIO operating mode. - * @rmtoll RADIOSCR MODE LL_PWR_GetRadioMode + * @rmtoll RADIOSCR MODE LL_PWR_GetRadioMode * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_RADIO_DEEP_SLEEP_MODE * @arg @ref LL_PWR_RADIO_SLEEP_MODE @@ -1358,14 +1350,15 @@ __STATIC_INLINE uint32_t LL_PWR_GetRadioMode(void) return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_MODE_0)); } } - /** * @} */ + /** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management * @{ */ + /** * @brief Indicate whether the regulator voltage output is above voltage * scaling range or not. @@ -1377,9 +1370,10 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) return ((READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == (PWR_VOSR_VOSRDY)) ? 1UL : 0UL); } + /** * @brief Indicate whether the system was in standby mode or not. - * @rmtoll SR SBF LL_PWR_IsActiveFlag_SB + * @rmtoll SR SBF LL_PWR_IsActiveFlag_SB * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) @@ -1389,7 +1383,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) /** * @brief Indicate whether the system was in stop mode or not. - * @rmtoll SR STOPF LL_PWR_IsActiveFlag_STOP + * @rmtoll SR STOPF LL_PWR_IsActiveFlag_STOP * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void) @@ -1397,10 +1391,11 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void) return ((READ_BIT(PWR->SR, PWR_SR_STOPF) == (PWR_SR_STOPF)) ? 1UL : 0UL); } + #if defined(PWR_SVMSR_REGS) /** * @brief Indicate whether the regulator supply is LDO or SMPS. - * @rmtoll SVMSR REGS LL_PWR_IsActiveFlag_REGULATOR + * @rmtoll SVMSR REGS LL_PWR_IsActiveFlag_REGULATOR * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGULATOR(void) @@ -1411,7 +1406,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGULATOR(void) /** * @brief Indicate whether the VDD voltage is below the threshold or not. - * @rmtoll SVMSR PVDO LL_PWR_IsActiveFlag_PVDO + * @rmtoll SVMSR PVDO LL_PWR_IsActiveFlag_PVDO * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) @@ -1422,7 +1417,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) /** * @brief Indicate whether the regulator voltage output is equal to current * used voltage scaling range or not. - * @rmtoll SVMSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS + * @rmtoll SVMSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void) @@ -1430,11 +1425,9 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void) return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == (PWR_SVMSR_ACTVOSRDY)) ? 1UL : 0UL); } - - /** * @brief Indicate whether a wakeup event is detected on wake up pin 1. - * @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1 + * @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) @@ -1445,7 +1438,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) #if defined(PWR_WUSR_WUF2) /** * @brief Indicate whether a wakeup event is detected on wake up pin 2. - * @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2 + * @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) @@ -1456,7 +1449,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) /** * @brief Indicate whether a wakeup event is detected on wake up pin 3. - * @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3 + * @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) @@ -1466,7 +1459,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) /** * @brief Indicate whether a wakeup event is detected on wake up pin 4. - * @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4 + * @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) @@ -1477,7 +1470,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) #if defined(PWR_WUSR_WUF5) /** * @brief Indicate whether a wakeup event is detected on wake up pin 5. - * @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5 + * @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) @@ -1488,7 +1481,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) /** * @brief Indicate whether a wakeup event is detected on wake up pin 6. - * @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6 + * @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) @@ -1498,7 +1491,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) /** * @brief Indicate whether a wakeup event is detected on wake up pin 7. - * @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7 + * @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void) @@ -1508,7 +1501,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void) /** * @brief Indicate whether a wakeup event is detected on wake up pin 8. - * @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8 + * @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void) @@ -1516,9 +1509,10 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void) return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL); } + /** * @brief Clear stop flag. - * @rmtoll SR CSSF LL_PWR_ClearFlag_STOP + * @rmtoll SR CSSF LL_PWR_ClearFlag_STOP * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_STOP(void) @@ -1526,9 +1520,10 @@ __STATIC_INLINE void LL_PWR_ClearFlag_STOP(void) WRITE_REG(PWR->SR, PWR_SR_CSSF); } + /** * @brief Clear standby flag. - * @rmtoll SR CSSF LL_PWR_ClearFlag_SB + * @rmtoll SR CSSF LL_PWR_ClearFlag_SB * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) @@ -1538,7 +1533,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) /** * @brief Clear wake up flag 1. - * @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1 + * @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) @@ -1549,7 +1544,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) #if defined(PWR_WUSCR_CWUF2) /** * @brief Clear wake up flag 2. - * @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2 + * @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) @@ -1560,7 +1555,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) /** * @brief Clear wake up flag 3. - * @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3 + * @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) @@ -1570,7 +1565,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) /** * @brief Clear wake up flag 4. - * @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4 + * @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) @@ -1581,7 +1576,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) #if defined(PWR_WUSCR_CWUF5) /** * @brief Clear wake up flag 5. - * @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5 + * @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) @@ -1592,7 +1587,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) /** * @brief Clear wake up flag 6. - * @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6 + * @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) @@ -1602,7 +1597,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) /** * @brief Clear wake up flag 7. - * @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7 + * @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU7(void) @@ -1612,7 +1607,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU7(void) /** * @brief Clear wake up flag 8. - * @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8 + * @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU8(void) @@ -1622,13 +1617,14 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU8(void) /** * @brief Clear all wake up flags. - * @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU + * @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) { WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF); } + /** * @} */ @@ -1640,7 +1636,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) #if defined(PWR_PRIVCFGR_NSPRIV) /** * @brief Enable privileged mode for nsecure items. - * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege + * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege * @retval None */ __STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void) @@ -1650,7 +1646,7 @@ __STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void) /** * @brief Disable privileged mode for nsecure items. - * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege + * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege * @retval None */ __STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void) @@ -1660,7 +1656,7 @@ __STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void) /** * @brief Check if privileged mode for nsecure items is enabled. - * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege + * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void) @@ -1672,7 +1668,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Enable privileged mode for secure items. - * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege + * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege * @retval None */ __STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void) @@ -1682,7 +1678,7 @@ __STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void) /** * @brief Disable privileged mode for secure items. - * @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege + * @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege * @retval None */ __STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void) @@ -1694,7 +1690,7 @@ __STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void) #if defined(PWR_PRIVCFGR_NSPRIV) /** * @brief Check if privileged mode for secure items is enabled. - * @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege + * @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void) @@ -1707,17 +1703,17 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void) /** * @brief Configure secure attribute mode. * @note This API can be executed only by CPU in secure mode. - * @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP6SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP7SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP8SEC LL_PWR_ConfigSecure\n - * SECCFGR LPMSEC LL_PWR_ConfigSecure\n - * SECCFGR VDMSEC LL_PWR_ConfigSecure\n - * SECCFGR VBSEC LL_PWR_ConfigSecure + * @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP6SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP7SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP8SEC LL_PWR_ConfigSecure\n + * SECCFGR LPMSEC LL_PWR_ConfigSecure\n + * SECCFGR VDMSEC LL_PWR_ConfigSecure\n + * SECCFGR VBSEC LL_PWR_ConfigSecure * @param SecureConfig This parameter can be the full combination * of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC @@ -1741,17 +1737,17 @@ __STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig) /** * @brief Get secure attribute configuration. * @note This API can be executed only by CPU in secure mode. - * @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n - * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n - * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n - * SECCFGR VBSEC LL_PWR_GetConfigSecure + * @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n + * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n + * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n + * SECCFGR VBSEC LL_PWR_GetConfigSecure * @retval Returned value is the combination of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rcc.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rcc.h index 31a6f8a86..1e7393e4c 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rcc.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rcc.h @@ -446,7 +446,7 @@ typedef struct #define LL_RCC_SPI1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_0 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SYSCLK clock used as SPI1 clock source */ #define LL_RCC_SPI1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_1 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< HSI clock used as SPI1 clock source */ #endif /* SPI1 */ -#define LL_RCC_SPI3_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U)) /*!< PCLK3 clock used as SPI3 clock source */ +#define LL_RCC_SPI3_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U)) /*!< PCLK7 clock used as SPI3 clock source */ #define LL_RCC_SPI3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL_0 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SYSCLK clock used as SPI3 clock source */ #define LL_RCC_SPI3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL_1 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< HSI clock used as SPI3 clock source */ /** @@ -491,15 +491,22 @@ typedef struct #define LL_RCC_RNG_CLKSOURCE_LSE 0U /*!< LSE clock used as RNG clock source */ #define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR2_RNGSEL_0 /*!< LSI clock used as RNG clock source */ #define LL_RCC_RNG_CLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 /*!< HSI clock used as RNG clock source */ -#define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_CCIPR2_RNGSEL_1 | RCC_CCIPR2_RNGSEL_0) /*!< PLL1Q clock used as RNG clock source */ +#define LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2 (RCC_CCIPR2_RNGSEL_1 | RCC_CCIPR2_RNGSEL_0) /*!< PLL1Q/2 clock used as RNG clock source */ /** * @} */ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_RCC_RNG_CLKSOURCE_PLL1Q LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2 +/** +@endcond + */ /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC4 clock source selection * @{ */ -#define LL_RCC_ADC_CLKSOURCE_HCLK 0U /*!< HCLK1 clock used as ADC4 clock source */ +#define LL_RCC_ADC_CLKSOURCE_HCLK 0U /*!< HCLK1 clock used as ADC4 clock source */ #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR3_ADCSEL_0 /*!< SYSCLK clock used as ADC4 clock source */ #define LL_RCC_ADC_CLKSOURCE_PLL1P RCC_CCIPR3_ADCSEL_1 /*!< PLL1P clock used as ADC4 clock source */ #define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR3_ADCSEL_2 /*!< HSI clock used as ADC4 clock source */ @@ -509,11 +516,12 @@ typedef struct */ + /** @defgroup RCC_LL_EC_TIM_INPUT_CAPTURE_CLOCKSource TIM Input capture clock source selection * @{ */ -#define LL_RCC_TIMIC_CLKSOURCE_NONE 0U /*!< No clock available for TIM16/TIM17 and LPTIM2 input capture */ -#define LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL /*!< HSI/256 selected for TIM16/TIM17 and LPTIM2 input capture */ +#define LL_RCC_TIMIC_CLKSOURCE_NONE 0U /*!< No clock available for TIM16/TIM17 and LPTIM2 input capture */ +#define LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL /*!< HSI/256 selected for TIM16/TIM17 and LPTIM2 input capture */ /** * @} */ @@ -597,6 +605,7 @@ typedef struct * @} */ + /** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source * @{ */ @@ -1912,12 +1921,12 @@ __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) /** * @brief Configure RNG clock source - * @rmtoll CCIPR2 RNGSEL LL_RCC_SetRNGClockSource + * @rmtoll CCIPR2 RNGSEL LL_RCC_SetRNGClockSource * @param RNGxSource This parameter can be one of the following values: * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2 * @retval None */ __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) @@ -1942,7 +1951,6 @@ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADC4Source) } - /** * @brief Get USARTx clock source * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n @@ -2099,7 +2107,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2 */ __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) { @@ -2123,6 +2131,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) return (uint32_t)(READ_BIT(RCC->CCIPR3, ADCx)); } + /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rtc.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rtc.h index 21e16e3bb..42510c0a7 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rtc.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rtc.h @@ -1515,7 +1515,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma /** * @brief Get time format (AM or PM notation) - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1549,7 +1549,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get Hours in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1584,7 +1584,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get Minutes in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1619,7 +1619,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get Seconds in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1673,7 +1673,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, /** * @brief Get time (hour, minute and second) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1822,7 +1822,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) /** * @brief Get Year in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n @@ -1856,7 +1856,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get Week day - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay * @param RTCx RTC Instance @@ -1903,7 +1903,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) /** * @brief Get Month in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n @@ -1945,7 +1945,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get Day in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n @@ -2011,7 +2011,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, /** * @brief Get date (WeekDay, Day, Month and Year) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_spi.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_spi.h index a89c3da53..37db1561f 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_spi.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_spi.h @@ -1236,7 +1236,8 @@ __STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx) * @brief Set Baudrate Prescaler * @note This configuration can not be changed when SPI is enabled. * SPI BaudRate = fPCLK/Pescaler. - * @rmtoll CFG1 MBR BPASS LL_SPI_SetBaudRatePrescaler + * @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler\n + * CFG1 BPASS LL_SPI_SetBaudRatePrescaler * @param SPIx SPI Instance * @param Baudrate This parameter can be one of the following values: * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS @@ -1257,7 +1258,8 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau /** * @brief Get Baudrate Prescaler - * @rmtoll CFG1 MBR BPASS LL_SPI_GetBaudRatePrescaler + * @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler\n + * CFG1 BPASS LL_SPI_GetBaudRatePrescaler * @param SPIx SPI Instance * @retval Returned value can be one of the following values: * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_system.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_system.h index 926ebb325..09aff21e0 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_system.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_system.h @@ -24,6 +24,7 @@ (+) Some of the FLASH features need to be handled in the SYSTEM file. (+) Access to DBGCMU registers (+) Access to SYSCFG registers + (+) Access to VREFBUF registers (not available on all devices) @endverbatim */ @@ -52,7 +53,7 @@ extern "C" { /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM LL Private Constants * @{ */ @@ -60,13 +61,21 @@ extern "C" { * @brief Power-down in Run mode Flash key */ #define FLASH_PDKEY1_1 0x04152637U /*!< Flash power down key1 */ -#define FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 - to unlock the RUN_PD bit in FLASH_ACR */ +#define FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEYR + to unlock the PDREQ bit in FLASH_ACR */ /** * @} */ -/** @defgroup SYSTEM_LL_EC_CS1 SYSCFG Vdd compensation cell Code selection +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_CS1 SYSCFG SYSCFG Vdd compensation cell Code selection * @{ */ #define LL_SYSCFG_VDD_CELL_CODE 0U /*VDD I/Os code from the cell (available in the SYSCFG_CCVR)*/ @@ -75,7 +84,6 @@ extern "C" { * @} */ - /** @defgroup SYSTEM_LL_EC_ERASE_MEMORIES_STATUS SYSCFG MEMORIES ERASE * @{ */ @@ -85,14 +93,6 @@ extern "C" { * @} */ -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants - * @{ - */ - /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS * @{ */ @@ -178,7 +178,6 @@ extern "C" { * @} */ - /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY * @{ */ @@ -202,6 +201,7 @@ extern "C" { * @} */ + /** * @} */ @@ -552,11 +552,59 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void) * @} */ +/** @defgroup SYSTEM_LL_EF_SYSCFG_ERASE_MEMORIE_STATUS SYSCFG ERASE MEMORIE STATUS + * @{ + */ + +/** + * @brief Clear Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void) +{ + SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE); +} + +/** + * @brief Get Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done + * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE)); +} + + +/** + * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams + * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void) +{ + SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR); +} + +/** + * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams + * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done + * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR)); +} /** * @} */ -/** @defgroup SYSTEM_LL_EF_COMPENSATION SYSCFG COMPENSATION +/** @defgroup SYSTEM_LL_EF_SYSCFG_COMPENSATION SYSCFG COMPENSATION * @{ */ @@ -581,7 +629,6 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void) } - /** * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode @@ -698,6 +745,10 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void) return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1)); } +/** + * @} + */ + /** * @} */ @@ -773,9 +824,13 @@ __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) @@ -787,7 +842,10 @@ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) * @brief Freeze APB1 peripherals (group2 peripherals) * @rmtoll DBGMCU_APB1HFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) @@ -801,9 +859,13 @@ __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) @@ -815,7 +877,10 @@ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) * @brief Unfreeze APB1 peripherals (group2 peripherals) * @rmtoll DBGMCU_APB1HFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) @@ -948,14 +1013,14 @@ __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) * @note Flash must not be accessed when power down is enabled * @note Flash must not be put in power-down while a program or an erase operation * is on-going - * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n + * @rmtoll FLASH_ACR PDREQ LL_FLASH_EnableRunPowerDown\n * FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n * FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown * @retval None */ __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) { - /* Following values must be written consecutively to unlock the RUN_PD bit in + /* Following values must be written consecutively to unlock the PDREQ bit in FLASH_ACR */ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1_1); WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1_2); @@ -1019,57 +1084,6 @@ __STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void) */ -/** @defgroup SYSTEM_LL_EF_ERASE_MEMORIE_STATUS SYSCFG ERASE MEMORIE STATUS - * @{ - */ - -/** - * @brief Clear Status of End of Erase for ICACHE and PKA RAMs - * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void) -{ - SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE); -} - -/** - * @brief Get Status of End of Erase for ICACHE and PKA RAMs - * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus - * @retval Returned value can be one of the following values: - * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done - * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE)); -} - - -/** - * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams - * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void) -{ - SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR); -} - -/** - * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams - * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus - * @retval Returned value can be one of the following values: - * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done - * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR)); -} -/** - * @} - */ /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_tim.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_tim.h index cece65e43..033581374 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_tim.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_tim.h @@ -671,10 +671,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CR2, TIM_CR2_CCPC); } +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check @@ -3795,7 +3814,6 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2 (*) * @arg @ref LL_TIM_TIM3_ETRSOURCE_HSI * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR - * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD1 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD2 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD3 @@ -3974,18 +3992,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); } -/** - * @brief Re-arm the break input (when it operates in bidirectional mode). - * @note The Break input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); -} - /** * @brief Enable the break 2 function. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not @@ -4075,18 +4081,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); } -/** - * @brief Re-arm the break 2 input (when it operates in bidirectional mode). - * @note The Break 2 input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); -} - /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_utils.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_utils.h index 17fefa5c1..3e99dc55c 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_utils.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_utils.h @@ -261,6 +261,9 @@ __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) } void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency); +void LL_Init1msTick_LSE(void); +void LL_Init1msTick_LSI(void); void LL_mDelay(uint32_t Delay); /** diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal.c index 9f6ba80ef..25c5c1b9e 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal.c @@ -110,8 +110,8 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ * @note HAL_Init() function is called at the beginning of program after reset and before * the clock configuration. * - * @note In the default implementation the System Timer (Systick) is used as source of time base. - * The Systick configuration is based on HSI clock, as HSI is the clock + * @note In the default implementation the System Timer (SysTick) is used as source of time base. + * The SysTick configuration is based on HSI clock, as HSI is the clock * used after a system Reset and the NVIC configuration is set to Priority group 4. * Once done, time base tick starts incrementing: the tick variable counter is incremented * each 1ms in the SysTick_Handler() interrupt handler. @@ -131,6 +131,9 @@ HAL_StatusTypeDef HAL_Init(void) /* Ensure time base clock coherency */ SystemCoreClockUpdate(); + /* Select HCLK as SysTick clock source */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + /* Initialize 1ms tick time base (default SysTick based on HSI clock after Reset) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { @@ -220,29 +223,60 @@ __weak void HAL_MspDeInit(void) */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + uint32_t ticknumber = 0U; + uint32_t systicksel; + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ if ((uint32_t)uwTickFreq == 0UL) { return HAL_ERROR; } - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) + /* Check Clock source to calculate the tickNumber */ + if(READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) == SysTick_CTRL_CLKSOURCE_Msk) { - return HAL_ERROR; + /* HCLK selected as SysTick clock source */ + ticknumber = SystemCoreClock / (1000UL / (uint32_t)uwTickFreq); } - - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + else { - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - uwTickPrio = TickPriority; + systicksel = __HAL_RCC_GET_SYSTICK_SOURCE(); + switch (systicksel) + { + /* HCLK_DIV8 selected as SysTick clock source */ + case RCC_SYSTICKCLKSOURCE_HCLK_DIV8: + /* Calculate tick value */ + ticknumber = (SystemCoreClock / (8000UL / (uint32_t)uwTickFreq)); + break; + + /* LSI selected as SysTick clock source */ + case RCC_SYSTICKCLKSOURCE_LSI: + /* Calculate tick value */ + ticknumber = (LSI_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + + /* LSE selected as SysTick clock source */ + case RCC_SYSTICKCLKSOURCE_LSE: + /* Calculate tick value */ + ticknumber = (LSE_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + + default: + /* Nothing to do */ + break; + } } - else + + /* Configure the SysTick */ + if (HAL_SYSTICK_Config(ticknumber) > 0U) { return HAL_ERROR; } + /* Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + /* Return function status */ return HAL_OK; } @@ -278,7 +312,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. + * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None @@ -620,9 +654,8 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem) * @} */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - +#if defined(SYSCFG_SECCFGR_SYSCFGSEC) /** @defgroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions * @brief SYSCFG attributes management functions. * @@ -635,6 +668,7 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem) * @{ */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Configure the SYSCFG item attribute(s). * @note Available attributes are to secure SYSCFG items, so this function is @@ -668,6 +702,8 @@ void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes) SYSCFG_S->SECCFGR = tmp; } +#endif /* __ARM_FEATURE_CMSE */ + /** * @brief Get the attribute of a SYSCFG item. * @note Available attributes are to secure SYSCFG items, so this function is @@ -685,10 +721,10 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri } /* Check the parameters */ - assert_param(IS_SYSCFG_ITEMS_ATTRIBUTES(Item)); + assert_param(IS_SYSCFG_SINGLE_ITEMS_ATTRIBUTES(Item)); /* Get the secure attribute state */ - if ((SYSCFG_S->SECCFGR & Item) != 0U) + if ((SYSCFG->SECCFGR & Item) != 0U) { *pAttributes = SYSCFG_SEC; } @@ -704,7 +740,7 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri * @} */ -#endif /* __ARM_FEATURE_CMSE */ +#endif /* SYSCFG_SECCFGR_SYSCFGSEC */ /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cortex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cortex.c index 4c8c2e42b..d0b3a681e 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cortex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cortex.c @@ -48,30 +48,26 @@ [..] Setup SysTick Timer for time base. - (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which - is a CMSIS function that: - (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (+) The SysTick clock source shall be configured with HAL_SYSTICK_CLKSourceConfig(). + + (+) The SysTick IRQ priority shall be configured with HAL_NVIC_SetPriority(SysTick_IRQn,...). + The HAL_NVIC_SetPriority() calls the CMSIS NVIC_SetPriority() function. + + (+) The HAL_SYSTICK_Config() function: + (++) Configures the SysTick Reload register with the value passed as function parameter. (++) Resets the SysTick Counter register. - (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). (++) Enables the SysTick Interrupt. (++) Starts the SysTick Counter. - (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro - __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the - HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined - inside the stm32wbaxx_hal_cortex.h file. - - (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function - call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. - (+) To adjust the SysTick time base, use the following formula: Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function (++) Reload Value should not exceed 0xFFFFFF + (+) In case the HAL time base is the SysTick Timer, the HAL time base configuration must be completed + by calling the HAL_InitTick() function. + @endverbatim ****************************************************************************** @@ -188,11 +184,11 @@ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t Sub { uint32_t prioritygroup; - /* Check the parameters */ - assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + prioritygroup = (NVIC_GetPriorityGrouping() & 0x7U); - prioritygroup = NVIC_GetPriorityGrouping(); + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority, prioritygroup)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority, prioritygroup)); NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); } @@ -250,7 +246,23 @@ void HAL_NVIC_SystemReset(void) */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - return SysTick_Config(TicksNumb); + if ((TicksNumb - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + /* Reload value impossible */ + return (1UL); + } + + /* Set reload register */ + WRITE_REG(SysTick->LOAD, (uint32_t)(TicksNumb - 1UL)); + + /* Load the SysTick Counter Value */ + WRITE_REG(SysTick->VAL, 0UL); + + /* Enable SysTick IRQ and SysTick Timer */ + SET_BIT(SysTick->CTRL, (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk)); + + /* Function successful */ + return (0UL); } /** * @} @@ -407,6 +419,45 @@ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) } } +/** + * @brief Get the SysTick clock source configuration. + * @retval SysTick clock source that can be one of the following values: + * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + */ +uint32_t HAL_SYSTICK_GetCLKSourceConfig(void) +{ + uint32_t systick_source; + + /* Read SysTick->CTRL register for internal or external clock source */ + if(READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) != 0U) + { + /* Internal clock source */ + systick_source = SYSTICK_CLKSOURCE_HCLK; + } + else + { + /* External clock source, check the selected one in RCC */ + switch (__HAL_RCC_GET_SYSTICK_SOURCE()) + { + case RCC_SYSTICKCLKSOURCE_LSI: + systick_source = SYSTICK_CLKSOURCE_LSI; + break; + + case RCC_SYSTICKCLKSOURCE_LSE: + systick_source = SYSTICK_CLKSOURCE_LSE; + break; + + default: /* RCC_SYSTICKCLKSOURCE_HCLK_DIV8 */ + systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; + break; + } + } + return systick_source; +} + /** * @brief Handle SYSTICK interrupt request. * @retval None @@ -427,8 +478,6 @@ __weak void HAL_SYSTICK_Callback(void) */ } -#if (__MPU_PRESENT == 1) - /** * @brief Enable the MPU. * @param MPU_Control: Specifies the control mode of the MPU during hard fault, @@ -635,8 +684,6 @@ static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, MPU_Attributes_InitTypeDe *(mair) = attr_values | ((uint32_t)MPU_AttributesInit->Attributes << (attr_number * 8U)); } -#endif /* __MPU_PRESENT */ - /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_dma.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_dma.c index e937c26bb..a4e3e243d 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_dma.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_dma.c @@ -95,8 +95,7 @@ (++) can be a value of DMA_Transfer_Event_Mode (+) Mode : Specifies the transfer mode for the DMA channel - (++) can be a value of DMA_Transfer_Mode - + (++) can be DMA_NORMAL *** Polling mode IO operation *** ================================= @@ -321,7 +320,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) { #if defined (DMA_PRIVCFGR_PRIV0) DMA_TypeDef *p_dma_instance; -#endif /* defined (DMA_PRIVCFGR_PRIV0) */ +#endif /* DMA_PRIVCFGR_PRIV0 */ uint32_t tickstart = HAL_GetTick(); /* Check the DMA peripheral handle parameter */ @@ -335,7 +334,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) #if defined (DMA_PRIVCFGR_PRIV0) /* Get DMA instance */ p_dma_instance = GET_DMA_INSTANCE(hdma); -#endif /* defined (DMA_PRIVCFGR_PRIV0) */ +#endif /* DMA_PRIVCFGR_PRIV0 */ /* Disable the selected DMA Channel */ __HAL_DMA_DISABLE(hdma); @@ -367,11 +366,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) #if defined (DMA_PRIVCFGR_PRIV0) /* Clear privilege attribute */ CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); -#endif /* defined (DMA_PRIVCFGR_PRIV0) */ +#endif /* DMA_PRIVCFGR_PRIV0 */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Clear secure attribute */ CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | @@ -884,14 +883,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Global Interrupt Flag management *********************************************************************************/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U)) #else if (global_active_flag_ns == 0U) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ { return; /* the global interrupt flag for the current channel is down , nothing to do */ } @@ -988,16 +987,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) /* Reset the channel internal state and reset the FIFO */ hdma->Instance->CCR |= DMA_CCR_RESET; - if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ERROR; - } - else - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - } + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; /* Check DMA channel transfer mode */ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) @@ -1089,16 +1080,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) /* Reset the channel internal state and reset the FIFO */ hdma->Instance->CCR |= DMA_CCR_RESET; - if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ERROR; - } - else - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - } + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; /* Check DMA channel transfer mode */ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) @@ -1448,7 +1431,7 @@ HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC); } } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ return HAL_OK; } @@ -1482,7 +1465,7 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co /* Get DMA channel privilege attribute */ attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined (DMA_SECCFGR_SEC0) /* Get DMA channel security attribute */ attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC; @@ -1491,14 +1474,14 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co /* Get DMA channel destination security attribute */ attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC; +#endif /* DMA_SECCFGR_SEC0 */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* return value */ *pChannelAttributes = attributes; return HAL_OK; } -#endif /* defined (DMA_PRIVCFGR_PRIV0) */ +#endif /* DMA_PRIVCFGR_PRIV0 */ #if defined (DMA_RCFGLOCKR_LOCK0) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** @@ -1529,7 +1512,7 @@ HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const h return HAL_OK; } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Get the security and privilege attribute lock state of a DMA channel. @@ -1562,7 +1545,7 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons return HAL_OK; } -#endif /* defined (DMA_RCFGLOCKR_LOCK0) */ +#endif /* DMA_RCFGLOCKR_LOCK0 */ /** * @} */ @@ -1638,7 +1621,7 @@ static void DMA_Init(DMA_HandleTypeDef const *const hdma) MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg); #else WRITE_REG(hdma->Instance->CTR1, tmpreg); -#endif /* defined (DMA_CTR1_SSEC) */ +#endif /* DMA_CTR1_SSEC */ /* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/ tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode; diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_dma_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_dma_ex.c index 4babea8d0..4a02639bb 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_dma_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_dma_ex.c @@ -636,7 +636,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) #if defined (DMA_PRIVCFGR_PRIV0) /* Get DMA instance */ DMA_TypeDef *p_dma_instance; -#endif /* defined (DMA_PRIVCFGR_PRIV0) */ +#endif /* DMA_PRIVCFGR_PRIV0 */ /* Get tick number */ uint32_t tickstart = HAL_GetTick(); @@ -653,7 +653,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) #if defined (DMA_PRIVCFGR_PRIV0) /* Get DMA instance */ p_dma_instance = GET_DMA_INSTANCE(hdma); -#endif /* defined (DMA_PRIVCFGR_PRIV0) */ +#endif /* DMA_PRIVCFGR_PRIV0 */ /* Disable the selected DMA Channel */ __HAL_DMA_DISABLE(hdma); @@ -687,12 +687,12 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) #if defined (DMA_PRIVCFGR_PRIV0) /* Clear privilege attribute */ CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); -#endif /* defined (DMA_PRIVCFGR_PRIV0) */ +#endif /* DMA_PRIVCFGR_PRIV0 */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Clear secure attribute */ CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | @@ -1043,7 +1043,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNod #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->SrcSecure)); assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->DestSecure)); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Build the DMA channel node */ DMA_List_BuildNode(pNodeConfig, pNode); @@ -3538,7 +3538,7 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, { pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC; } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Add parameters related to DMA configuration */ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) @@ -3660,7 +3660,7 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, { pNodeConfig->DestSecure = DMA_CHANNEL_DEST_NSEC; } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*********************************************************************************** CTR1 fields values are updated */ diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash.c index 1727978f2..f70976247 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash.c @@ -297,7 +297,7 @@ void HAL_FLASH_IRQHandler(void) uint32_t param = 0U; uint32_t error; __IO uint32_t *reg_cr; - __IO uint32_t type; + uint32_t type; __IO uint32_t *reg_sr; type = (pFlash.ProcedureOnGoing & ~(FLASH_NON_SECURE_MASK)); @@ -328,13 +328,17 @@ void HAL_FLASH_IRQHandler(void) { param = pFlash.Address; } + else if (type == FLASH_TYPEPROGRAM_BURST) + { + param = pFlash.Address; + } else { /* Empty statement (to be compliant MISRA 15.7) */ } /* Clear operation bit on the on-going procedure */ - CLEAR_BIT((*reg_cr), (pFlash.ProcedureOnGoing & ~(FLASH_NON_SECURE_MASK))); + CLEAR_BIT((*reg_cr), (type | FLASH_NSCR1_PNB)); /* Check FLASH operation error flags */ if (error != 0U) @@ -401,6 +405,16 @@ void HAL_FLASH_IRQHandler(void) /* Process Unlocked */ __HAL_UNLOCK(&pFlash); } + + /* Check ECC Correction Error */ + if ((FLASH->ECCR & (FLASH_ECCR_ECCC | FLASH_ECCR_ECCIE)) == (FLASH_ECCR_ECCC | FLASH_ECCR_ECCIE)) + { + /* Call User callback */ + HAL_FLASHEx_EccCorrectionCallback(); + + /* Clear ECC correction flag in order to allow new ECC error record */ + SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCC); + } } /** diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash_ex.c index babdd39d4..b08994a33 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash_ex.c @@ -239,7 +239,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t } /* If the erase operation is completed, disable the associated bits */ - CLEAR_BIT((*reg_cr), (pEraseInit->TypeErase) & (~(FLASH_NON_SECURE_MASK))); + CLEAR_BIT((*reg_cr), (((pEraseInit->TypeErase) & (~(FLASH_NON_SECURE_MASK))) | FLASH_NSCR1_PNB)); } /* Process Unlocked */ @@ -306,7 +306,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) pFlash.Page = pEraseInit->Page; /* Erase first page and wait for IT */ - FLASH_PageErase(pEraseInit->Page); + FLASH_PageErase(pEraseInit->Page); } } @@ -466,7 +466,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) } } -#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) +#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) || defined(FLASH_SECBB1R1_SECBB0) || defined(FLASH_PRIVBB1R1_PRIVBB0) /** * @brief Configure the block-based secure area. * @@ -848,6 +848,124 @@ void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation) pFlashOperation->Address = opsr_reg & FLASH_OPSR_ADDR_OP; } +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group3 Extended ECC operation functions + * @brief Extended ECC operation functions + * +@verbatim + =============================================================================== + ##### Extended ECC operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + ECC Operations. + +@endverbatim + * @{ + */ +/** + * @brief Enable ECC correction interrupt + * @note ECC detection does not need to be enabled as directly linked to + * Non-Maskable Interrupt (NMI) + * @retval None + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt(void) +{ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ECCC); +} + +/** + * @brief Disable ECC correction interrupt + * @retval None + */ +void HAL_FLASHEx_DisableEccCorrectionInterrupt(void) +{ + __HAL_FLASH_DISABLE_IT(FLASH_IT_ECCC); +} + +/** + * @brief Get the ECC error information. + * @param pData Pointer to an FLASH_EccInfoTypeDef structure that contains the + * ECC error information. + * @note This function should be called before ECC bit is cleared + * (in callback function) + * @retval None + */ +void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData) +{ + uint32_t eccr; + /* Check Null pointer */ + assert_param(pData != NULL); + + /* Get back information from ECC register */ + eccr = FLASH->ECCR; + + /* Retrieve and sort information */ + pData->Area = (eccr & FLASH_ECCR_SYSF_ECC); + pData->Address = ((eccr & FLASH_ECCR_ADDR_ECC) << 3U); + + /* Add Base address depending on targeted area */ + if (pData->Area == FLASH_ECC_AREA_USER_BANK1) + { + pData->Address |= FLASH_BASE; + } + else + { +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + pData->Address |= SYSTEM_FLASH_BASE_S; +#else + pData->Address |= SYSTEM_FLASH_BASE_NS; +#endif /* __ARM_FEATURE_CMSE */ + } + + /* Set Master which initiates transaction. On WBA, it's necessary CPU1 */ + pData->MasterID = FLASH_ECC_MASTER_CPU1; +} + +/** + * @brief Handle Flash ECC Detection interrupt request. + * @note On STM32WBA, this Irq Handler should be called in Non-Maskable Interrupt (NMI) + * interrupt subroutine. + * @retval None + */ +void HAL_FLASHEx_ECCD_IRQHandler(void) +{ + /* Check ECC Detection Error */ + if ((FLASH->ECCR & FLASH_ECCR_ECCD) != 0U) + { + /* Call User callback */ + HAL_FLASHEx_EccDetectionCallback(); + + /* Clear ECC detection flag in order to allow new ECC error record */ + SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCD); + } +} + +/** + * @brief FLASH ECC Correction interrupt callback. + * @retval None + */ +__weak void HAL_FLASHEx_EccCorrectionCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASHEx_EccCorrectionCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH ECC Detection interrupt callback. + * @retval None + */ +__weak void HAL_FLASHEx_EccDetectionCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASHEx_EccDetectionCallback could be implemented in the user file + */ +} + /** * @} */ @@ -869,6 +987,7 @@ static void FLASH_MassErase() { __IO uint32_t *reg_cr; + /* Access to SECCR1 or NSCR1 registers depends on operation type */ #if defined(FLASH_SECCR1_LOCK) reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR1) : &(FLASH_NS->NSCR1); @@ -900,6 +1019,7 @@ void FLASH_PageErase(uint32_t Page) reg_cr = &(FLASH_NS->NSCR1); #endif /* FLASH_SECCR1_LOCK */ + /* Proceed to erase the page */ MODIFY_REG((*reg_cr), (FLASH_NSCR1_PNB | FLASH_NSCR1_PER | FLASH_NSCR1_STRT), ((Page << FLASH_NSCR1_PNB_Pos) | FLASH_NSCR1_PER | FLASH_NSCR1_STRT)); } @@ -1127,6 +1247,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_mask |= FLASH_OPTR_WWDG_SW; } + if ((UserType & OB_USER_SRAM2_PE) != 0U) { /* SRAM2_PAR option byte should be modified */ @@ -1167,6 +1288,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_mask |= FLASH_OPTR_nBOOT0; } + #if defined(FLASH_OPTR_TZEN) if ((UserType & OB_USER_TZEN) != 0U) { diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gpio.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gpio.c index d078c78ea..7ce20fd5a 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gpio.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gpio.c @@ -129,7 +129,7 @@ /** @addtogroup GPIO_Private_Constants * @{ */ -#define GPIO_NUMBER (16u) +#define GPIO_NUMBER (16U) /** * @} */ @@ -167,7 +167,7 @@ */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) { - uint32_t position = 0x00u; + uint32_t position = 0x00U; uint32_t iocurrent; uint32_t temp; @@ -177,12 +177,12 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ - while (((GPIO_Init->Pin) >> position) != 0x00u) + while (((GPIO_Init->Pin) >> position) != 0x00U) { /* Get current io position */ - iocurrent = (GPIO_Init->Pin) & (1uL << position); + iocurrent = (GPIO_Init->Pin) & (1UL << position); - if (iocurrent != 0x00u) + if (iocurrent != 0x00U) { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ @@ -193,8 +193,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); - temp |= (GPIO_Init->Speed << (position * 2u)); + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + temp |= (GPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos)); GPIOx->OSPEEDR = temp; /* Configure the IO Output Type */ @@ -211,8 +211,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); - temp |= ((GPIO_Init->Pull) << (position * 2u)); + temp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); + temp |= ((GPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos)); GPIOx->PUPDR = temp; } @@ -224,31 +224,31 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3u]; - temp &= ~(0xFu << ((position & 0x07u) * 4u)); - temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); - GPIOx->AFR[position >> 3u] = temp; + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + GPIOx->AFR[position >> 3U] = temp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + temp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos)); GPIOx->MODER = temp; /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ - if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) { - temp = EXTI->EXTICR[position >> 2u]; - temp &= ~(0x0FuL << (8u * (position & 0x03u))); - temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); - EXTI->EXTICR[position >> 2u] = temp; + temp = EXTI->EXTICR[position >> 2U]; + temp &= ~(0x0FUL << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + temp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + EXTI->EXTICR[position >> 2U] = temp; /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) { temp |= iocurrent; } @@ -256,7 +256,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) temp = EXTI->FTSR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) { temp |= iocurrent; } @@ -265,7 +265,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) /* Clear EXTI line configuration */ temp = EXTI->EMR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) { temp |= iocurrent; } @@ -273,7 +273,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) temp = EXTI->IMR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) { temp |= iocurrent; } @@ -294,7 +294,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { - uint32_t position = 0x00u; + uint32_t position = 0x00U; uint32_t iocurrent; uint32_t tmp; @@ -303,19 +303,19 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ - while ((GPIO_Pin >> position) != 0x00u) + while ((GPIO_Pin >> position) != 0x00U) { /* Get current io position */ - iocurrent = (GPIO_Pin) & (1uL << position); + iocurrent = (GPIO_Pin) & (1UL << position); - if (iocurrent != 0x00u) + if (iocurrent != 0x00U) { /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ - tmp = EXTI->EXTICR[position >> 2u]; - tmp &= (0x0FuL << (8u * (position & 0x03u))); - if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)))) + tmp = EXTI->EXTICR[position >> 2U]; + tmp &= (0x0FUL << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + if (tmp == (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos))) { /* Clear EXTI line configuration */ EXTI->IMR1 &= ~(iocurrent); @@ -325,25 +325,25 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) EXTI->FTSR1 &= ~(iocurrent); EXTI->RTSR1 &= ~(iocurrent); - tmp = 0x0FuL << (8u * (position & 0x03u)); - EXTI->EXTICR[position >> 2u] &= ~tmp; + tmp = 0x0FUL << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos); + EXTI->EXTICR[position >> 2U] &= ~tmp; } /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO in Analog Mode */ - GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ; /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); } position++; @@ -380,7 +380,7 @@ GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - if ((GPIOx->IDR & GPIO_Pin) != 0x00u) + if ((GPIOx->IDR & GPIO_Pin) != 0x00U) { bitstatus = GPIO_PIN_SET; } @@ -498,7 +498,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) tmp = GPIOx->LCKR; /* read again in order to confirm lock is active */ - if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U) { return HAL_OK; } @@ -516,13 +516,13 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { /* EXTI line interrupt detected */ - if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0x00u) + if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0x00U) { __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); } - if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0x00u) + if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0x00U) { __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); @@ -620,15 +620,16 @@ void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32 */ HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes) { + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin)); + /* Check null pointer */ if (pPinAttributes == NULL) { return HAL_ERROR; } - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - if ((GPIOx->SECCFGR & GPIO_Pin) != 0x00U) { *pPinAttributes = GPIO_PIN_SEC; diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gtzc.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gtzc.c index ffa784b9a..ae65a395a 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gtzc.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gtzc.c @@ -113,44 +113,28 @@ /* Definitions for GTZC TZSC & TZIC ALL register values */ /* TZSC1 / TZIC1 instances */ -#define TZSC1_SECCFGR1_ALL (0x000222C3UL) #if defined (STM32WBA54xx) || defined (STM32WBA55xx) +#define TZSC1_SECCFGR1_ALL (0x000222C3UL) #define TZSC1_SECCFGR2_ALL (0x018F00EBUL) #define TZSC1_SECCFGR3_ALL (0x01C17858UL) +#define TZIC1_IER4_ALL (0xC3C0EF87UL) #else +#define TZSC1_SECCFGR1_ALL (0x000222C3UL) #define TZSC1_SECCFGR2_ALL (0x010F006BUL) #define TZSC1_SECCFGR3_ALL (0x00C17858UL) -#endif /* STM32WBA54xx || STM32WBA55xx */ - -#define TZSC1_PRIVCFGR1_ALL (0x000222C3UL) -#if defined (STM32WBA54xx) || defined (STM32WBA55xx) -#define TZSC1_PRIVCFGR2_ALL (0x018F00EBUL) -#define TZSC1_PRIVCFGR3_ALL (0x01C17858UL) -#else -#define TZSC1_PRIVCFGR2_ALL (0x010F006BUL) -#define TZSC1_PRIVCFGR3_ALL (0x00C17858UL) -#endif /* STM32WBA54xx || STM32WBA55xx */ - -#define TZIC1_IER1_ALL (0x000222C3UL) -#if defined (STM32WBA54xx) || defined (STM32WBA55xx) -#define TZIC1_IER2_ALL (0x018F00EBUL) -#define TZIC1_IER3_ALL (0x01C1F858UL) -#else -#define TZIC1_IER2_ALL (0x010F006BUL) -#define TZIC1_IER3_ALL (0x00C1F858UL) -#endif /* STM32WBA54xx || STM32WBA55xx */ #define TZIC1_IER4_ALL (0xC3C0EF87UL) - -#define TZIC1_FCR1_ALL (0x000222C3UL) -#if defined (STM32WBA54xx) || defined (STM32WBA55xx) -#define TZIC1_FCR2_ALL (0x018F00EBUL) -#define TZIC1_FCR3_ALL (0x01C1F858UL) -#else -#define TZIC1_FCR2_ALL (0x010F006BUL) -#define TZIC1_FCR3_ALL (0x00C1F858UL) #endif /* STM32WBA54xx || STM32WBA55xx */ -#define TZIC1_FCR4_ALL (0xC3C0EF87UL) +#define TZSC1_PRIVCFGR1_ALL TZSC1_SECCFGR1_ALL +#define TZSC1_PRIVCFGR2_ALL TZSC1_SECCFGR2_ALL +#define TZSC1_PRIVCFGR3_ALL TZSC1_SECCFGR3_ALL +#define TZIC1_IER1_ALL TZSC1_SECCFGR1_ALL +#define TZIC1_IER2_ALL TZSC1_SECCFGR2_ALL +#define TZIC1_IER3_ALL TZSC1_SECCFGR3_ALL +#define TZIC1_FCR1_ALL TZIC1_IER1_ALL +#define TZIC1_FCR2_ALL TZIC1_IER2_ALL +#define TZIC1_FCR3_ALL TZIC1_IER3_ALL +#define TZIC1_FCR4_ALL TZIC1_IER4_ALL /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_hash.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_hash.c index 769cdda37..802757f48 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_hash.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_hash.c @@ -2479,15 +2479,58 @@ static void HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *pInBuffer, { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; + uint8_t tmp1; + uint8_t tmp2; + uint8_t tmp3; - - for (buffercounter = 0U; buffercounter < Size ; buffercounter += 4U) + for (buffercounter = 0U; buffercounter < (Size / 4U) ; buffercounter++) { /* Write input data 4 bytes at a time */ hhash->Instance->DIN = *(uint32_t *)inputaddr; inputaddr += 4U; hhash->HashInCount += 4U; } + + if ((Size % 4U) != 0U) + { + if (hhash->Init.DataType == HASH_HALFWORD_SWAP) + { + /* Write remaining input data */ + if ((Size % 4U) <= 2U) + { + hhash->Instance->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + hhash->Instance->DIN = *(uint32_t *)inputaddr; + } + } + else if ((hhash->Init.DataType == HASH_BYTE_SWAP) + || (hhash->Init.DataType == HASH_BIT_SWAP)) /* byte swap or bit swap or */ + { + /* Write remaining input data */ + if ((Size % 4U) == 1U) + { + hhash->Instance->DIN = (uint32_t) * (uint8_t *)inputaddr; + } + if ((Size % 4U) == 2U) + { + hhash->Instance->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + tmp1 = *(uint8_t *)inputaddr; + tmp2 = *(((uint8_t *)inputaddr) + 1U); + tmp3 = *(((uint8_t *)inputaddr) + 2U); + hhash->Instance->DIN = ((uint32_t)tmp1) | ((uint32_t)tmp2 << 8U) | ((uint32_t)tmp3 << 16U); + } + } + else + { + hhash->Instance->DIN = *(uint32_t *)inputaddr; + } + hhash->HashInCount += 4U; + } } /** diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_i2c.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_i2c.c index 22e592fdc..0befd7d3c 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_i2c.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_i2c.c @@ -2911,6 +2911,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ + hi2c->XferSize = 0U; hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; @@ -3512,22 +3513,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - /* Increment Trials */ I2C_Trials++; } while (I2C_Trials < Trials); @@ -5509,9 +5494,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5940,9 +5924,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -6544,14 +6527,14 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Disable Interrupts and Store Previous state */ - if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (tmpstate == HAL_I2C_STATE_LISTEN)) + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; @@ -6561,6 +6544,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } else { /* Do nothing */ @@ -6629,6 +6617,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -7217,6 +7256,12 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { @@ -7328,16 +7373,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + status = HAL_ERROR; } /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) { /* Check if an RXNE is pending */ /* Store Last receive data if any */ @@ -7345,19 +7392,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ - return HAL_OK; + status = HAL_OK; } - else + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -7371,12 +7413,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } } /* Check for the Timeout */ - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) { @@ -7386,11 +7432,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; } } } - return HAL_OK; + return status; } /** diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_icache.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_icache.c index fabc67724..ebcb7d319 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_icache.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_icache.c @@ -51,6 +51,11 @@ (#) Enable and disable the Instruction Cache with respectively HAL_ICACHE_Enable() and HAL_ICACHE_Disable(). Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status. + To ensure a deterministic cache behavior after power on, system reset or after + a call to @ref HAL_ICACHE_Disable(), the application must call + @ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset + or cache disable, an automatic cache invalidation procedure is launched and the + cache is bypassed until the operation completes. (#) Initiate the cache maintenance invalidation procedure with either HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT() @@ -183,32 +188,32 @@ HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode) /** * @brief DeInitialize the Instruction Cache. - * @retval HAL status (HAL_OK/HAL_TIMEOUT) + * @retval HAL status (HAL_OK) */ HAL_StatusTypeDef HAL_ICACHE_DeInit(void) { - HAL_StatusTypeDef status; + /* Reset interrupt enable value */ + WRITE_REG(ICACHE->IER, 0U); - /* Disable cache with reset value for 2-ways set associative mode */ + /* Clear any pending flags */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); + + /* Disable cache then set default associative mode value */ + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL); /* Stop monitor and reset monitor values */ - (void)HAL_ICACHE_Monitor_Stop(ICACHE_MONITOR_HIT_MISS); - (void)HAL_ICACHE_Monitor_Reset(ICACHE_MONITOR_HIT_MISS); + CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS); + SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); + CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); - /* No remapped regions */ - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_0); - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_1); - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_2); - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_3); + /* Reset regions configuration values */ + WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); - /* Wait for end of invalidate cache procedure */ - status = HAL_ICACHE_WaitForInvalidateComplete(); - - /* Clear any pending flags */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); - - return status; + return HAL_OK; } /** @@ -281,22 +286,15 @@ HAL_StatusTypeDef HAL_ICACHE_Invalidate(void) { HAL_StatusTypeDef status; - /* Check no ongoing operation */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) - { - status = HAL_ERROR; - } - else + /* Check if no ongoing operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U) { - /* Make sure BSYENDF is reset before to start cache invalidation */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - /* Launch cache invalidation */ SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); - - status = HAL_ICACHE_WaitForInvalidateComplete(); } + status = HAL_ICACHE_WaitForInvalidateComplete(); + return status; } diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pka.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pka.c index a83df7c1b..961b4b300 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pka.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pka.c @@ -309,6 +309,7 @@ HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode); void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in); void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in); void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in); +void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in); void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in); void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in); void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in); @@ -727,6 +728,7 @@ HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_Ca (++) HAL_PKA_ECCMulFastMode() (++) HAL_PKA_ECCMul_GetResult(); + (++) HAL_PKA_ECCMulEx() (++) HAL_PKA_ECCDoubleBaseLadder() (++) HAL_PKA_ECCDoubleBaseLadder_GetResult(); (++) HAL_PKA_ECCProjective2Affine() @@ -771,6 +773,7 @@ HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_Ca (++) HAL_PKA_ECCMulFastMode_IT(); (++) HAL_PKA_ECCMul_GetResult(); + (++) HAL_PKA_ECCMulEx_IT(); (++) HAL_PKA_ECCDoubleBaseLadder_IT() (++) HAL_PKA_ECCDoubleBaseLadder_GetResult(); (++) HAL_PKA_ECCProjective2Affine_IT() @@ -903,6 +906,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModE return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT); } + /** * @brief Retrieve operation result. * @param hpka PKA handle @@ -1151,6 +1155,40 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); } +/** + * @brief ECC scalar multiplication extended in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMulEx_Set(hpka, in); + + modulussize = in->modulusSize; + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); +} + +/** + * @brief ECC scalar multiplication extended in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMulEx_Set(hpka, in); + + modulussize = in->modulusSize; + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); +} /** * @brief Retrieve operation result. * @param hpka PKA handle @@ -1704,13 +1742,11 @@ void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka) void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) { uint32_t mode = PKA_GetMode(hpka); - FlagStatus addErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR); - FlagStatus ramErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR); - FlagStatus procEndFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_PROCEND); - FlagStatus operErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_OPERR); + uint32_t itsource = READ_REG(hpka->Instance->CR); + uint32_t flag = READ_REG(hpka->Instance->SR); /* Address error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_ADDRERR) == SET) && (addErrFlag == SET)) + if (((itsource & PKA_IT_ADDRERR) == PKA_IT_ADDRERR) && ((flag & PKA_FLAG_ADDRERR) == PKA_FLAG_ADDRERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR; @@ -1719,7 +1755,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* RAM access error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_RAMERR) == SET) && (ramErrFlag == SET)) + if (((itsource & PKA_IT_RAMERR) == PKA_IT_RAMERR) && ((flag & PKA_FLAG_RAMERR) == PKA_FLAG_RAMERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR; @@ -1728,7 +1764,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* OPERATION access error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_FLAG_OPERR) == SET) && (operErrFlag == SET)) + if (((itsource & PKA_IT_OPERR) == PKA_IT_OPERR) && ((flag & PKA_FLAG_OPERR) == PKA_FLAG_OPERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; @@ -1792,7 +1828,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* End Of Operation interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_PROCEND) == SET) && (procEndFlag == SET)) + if (((itsource & PKA_IT_PROCEND) == PKA_IT_PROCEND) && ((flag & PKA_FLAG_PROCEND) == PKA_FLAG_PROCEND)) { /* Clear PROCEND flag */ __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND); @@ -2591,7 +2627,50 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); } +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder)); + + /* Get the modulus length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + /* Move the input parameters coefficient b to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters scalar multiplier k to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters curve prime order N to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); +} /** * @brief Set input parameters. diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pwr.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pwr.c index 6eb920f4b..b5adac52b 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pwr.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pwr.c @@ -8,7 +8,6 @@ * + Initialization/De-Initialization Functions. * + Peripheral Control Functions. * + PWR Attributes Functions. - * ****************************************************************************** * @attention * @@ -129,7 +128,7 @@ * @{ */ -#if defined (HAL_PWR_MODULE_ENABLED) +#if defined(HAL_PWR_MODULE_ENABLED) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -594,7 +593,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * the content of SRAM and registers. All clocks in the VCORE domain * are stopped. The PLL, HSI16 and HSE32 oscillators are disabled. * The LSE or LSI is still running. - * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a + * @note When exiting Stop mode by issuing an interrupt or a * wakeup event, the HSI16 oscillator is selected as system clock * The MCU is in Run mode same range as before entering Stop mode. * @note On STM32WBAXX_SI_CUT1_0 : @@ -612,8 +611,8 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * HSEON, HSION and SYSCLK selection. * @param Regulator : Specifies the regulator state in Stop mode * This parameter can be one of the following values: - * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) - * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON) + * @arg @ref PWR_LOWPOWERMODE_STOP0 Stop 0 mode (main regulator ON) + * @arg @ref PWR_LOWPOWERMODE_STOP1 Stop 1 mode (low power regulator ON) * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE * instruction. * This parameter can be one of the following values : @@ -810,13 +809,13 @@ void HAL_PWR_WKUP_IRQHandler(void) /* PWR WKUP1 interrupt user callback */ HAL_PWR_WKUP1_Callback(); } -#if defined (PWR_WUCR1_WUPEN2) +#if defined(PWR_WUCR1_WUPEN2) if ((wakeuppin & PWR_WUSR_WUF2) != 0U) { /* PWR WKUP2 interrupt user callback */ HAL_PWR_WKUP2_Callback(); } -#endif /* defined (PWR_WUCR1_WUPEN2) */ +#endif /* defined(PWR_WUCR1_WUPEN2) */ if ((wakeuppin & PWR_WUSR_WUF3) != 0U) { /* PWR WKUP3 interrupt user callback */ @@ -828,13 +827,13 @@ void HAL_PWR_WKUP_IRQHandler(void) /* PWR WKUP4 interrupt user callback */ HAL_PWR_WKUP4_Callback(); } -#if defined (PWR_WUCR1_WUPEN5) +#if defined(PWR_WUCR1_WUPEN5) if ((wakeuppin & PWR_WUSR_WUF5) != 0U) { /* PWR WKUP5 interrupt user callback */ HAL_PWR_WKUP5_Callback(); } -#endif /* defined (PWR_WUCR1_WUPEN5) */ +#endif /* defined(PWR_WUCR1_WUPEN5) */ if ((wakeuppin & PWR_WUSR_WUF6) != 0U) { /* PWR WKUP6 interrupt user callback */ @@ -863,7 +862,7 @@ __weak void HAL_PWR_WKUP1_Callback(void) */ } -#if defined (PWR_WUCR1_WUPEN2) +#if defined(PWR_WUCR1_WUPEN2) /** * @brief PWR WKUP2 interrupt callback. * @retval None. @@ -874,7 +873,7 @@ __weak void HAL_PWR_WKUP2_Callback(void) the HAL_PWR_WKUP2Callback can be implemented in the user file */ } -#endif /* defined (PWR_WUCR1_WUPEN2) */ +#endif /* defined(PWR_WUCR1_WUPEN2) */ /** * @brief PWR WKUP3 interrupt callback. @@ -898,7 +897,7 @@ __weak void HAL_PWR_WKUP4_Callback(void) */ } -#if defined (PWR_WUCR1_WUPEN5) +#if defined(PWR_WUCR1_WUPEN5) /** * @brief PWR WKUP5 interrupt callback. * @retval None. @@ -909,7 +908,7 @@ __weak void HAL_PWR_WKUP5_Callback(void) the HAL_PWR_WKUP5Callback can be implemented in the user file */ } -#endif /* defined (PWR_WUCR1_WUPEN5) */ +#endif /* defined(PWR_WUCR1_WUPEN5) */ /** * @brief PWR WKUP6 interrupt callback. @@ -1039,7 +1038,7 @@ void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes) assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item)); assert_param(IS_PWR_ATTRIBUTES(Attributes)); -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Secure item management (TZEN = 1) */ if ((Attributes & PWR_ITEM_ATTR_SEC_PRIV_MASK) == PWR_ITEM_ATTR_SEC_PRIV_MASK) { @@ -1109,7 +1108,7 @@ HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut /* Check the parameter */ assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item)); -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Check item security */ if ((PWR->SECCFGR & Item) == Item) { @@ -1140,7 +1139,7 @@ HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut * @} */ -#endif /* defined (HAL_PWR_MODULE_ENABLED) */ +#endif /* defined(HAL_PWR_MODULE_ENABLED) */ /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pwr_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pwr_ex.c index 3cc6a895e..18ff98944 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pwr_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pwr_ex.c @@ -9,7 +9,7 @@ * + Low Power Control Functions * + Voltage Monitoring Functions * + Memories Retention Functions - * + I/O Pull-Up Pull-Down Configuration Functions + * + I/O Retention Functions ****************************************************************************** * @attention * @@ -101,7 +101,7 @@ * @{ */ -#if defined (HAL_PWR_MODULE_ENABLED) +#if defined(HAL_PWR_MODULE_ENABLED) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -109,21 +109,20 @@ /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines * @{ */ -#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) #define PWR_PORTA_AVAILABLE_PINS (0x0FFFFU) #define PWR_PORTB_AVAILABLE_PINS (0x0FFFFU) #define PWR_PORTC_AVAILABLE_PINS (0x0E000U) #define PWR_PORTH_AVAILABLE_PINS (0x00008U) -#elif defined (STM32WBA50xx) +#elif defined(STM32WBA50xx) #define PWR_PORTA_AVAILABLE_PINS (0x0F1E3U) #define PWR_PORTB_AVAILABLE_PINS (0x09318U) #define PWR_PORTC_AVAILABLE_PINS (0x0C000U) #define PWR_PORTH_AVAILABLE_PINS (0x00008U) -#endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ /*!< Time out value of flags setting */ #define PWR_VOSF_SETTING_DELAY_VALUE (0x32U) /*!< Time out value for VOSF flag setting */ #define PWR_MODE_CHANGE_DELAY_VALUE (0x32U) /*!< Time out for step down converter operating mode */ - /** * @} */ @@ -376,7 +375,6 @@ void HAL_PWREx_DisableFastSoftStart(void) * @} */ - /** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions * @brief Low power control functions */ @@ -403,8 +401,6 @@ void HAL_PWREx_DisableUltraLowPowerMode(void) { CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN); } - - /** * @} */ @@ -420,7 +416,7 @@ void HAL_PWREx_DisableUltraLowPowerMode(void) =============================================================================== [..] Several STM32WBA devices RAMs are configurable to retain or lose RAMs content - during Stop mode (Stop 0/1). + during Stop mode. (+) Retained content RAMs in Stop modes are : (++) SRAM1 (++) SRAM2 @@ -437,13 +433,12 @@ void HAL_PWREx_DisableUltraLowPowerMode(void) * @{ */ -#if defined(PWR_CR1_R1RSB1) /** * @brief Enable SRAM1 content retention in Standby mode. * @note When R1RSB1 bit is set, SRAM1 is powered by the low-power regulator in * Standby mode and its content is kept. * @param SRAM1Pages : Specifies the SRAM1 area - * This parameter can be one of the following values : + * This parameter can be combination of the following values : * @arg PWR_SRAM1_FULL_STANDBY_RETENTION : full SRAM1 retention. * @retval None. */ @@ -467,7 +462,6 @@ void HAL_PWREx_DisableSRAM1ContentStandbyRetention(void) /* Clear R1RSB1 bit */ CLEAR_BIT(PWR->CR1, PWR_SRAM1_FULL_STANDBY_RETENTION); } -#endif /* defined(PWR_CR1_R1RSB1) */ /** * @brief Enable SRAM2 content retention in Standby mode. @@ -531,17 +525,16 @@ void HAL_PWREx_DisableRadioSRAMClockStandbyRetention(void) } /** - * @brief Enable RAMs content retention in Stop mode (Stop 0, 1). + * @brief Enable RAMs content retention in Stop modes. * @note When enabling content retention for a given ram, memory is kept powered * on in Stop mode. (Consumption is not optimized) * @note On Silicon Cut 1.0, it is mandatory to disable the ICACHE before going into * stop modes otherwise an hard fault may occur when waking up from stop modes. * @param RAMSelection: Specifies RAMs content to be retained in Stop mode. - * This parameter can be one or a combination of the values - * @ref PWREx_RAM_Contents_Stop_Retention. - * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention when available. + * This parameter can be one or a combination of the values: + * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention . * @arg PWR_SRAM2_FULL_STOP_RETENTION : full SRAM2 retention. - * @arg PWR_ICACHE_FULL_STOP_RETENTION : full I-CACHE RAM retention. + * @arg PWR_ICACHE_FULL_STOP_RETENTION : I-CACHE SRAM retention. * @retval None. */ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) @@ -554,15 +547,14 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) } /** - * @brief Disable RAMs content retention in Stop mode (Stop 0, 1). + * @brief Disable RAMs content retention in Stop modes. * @note When disabling content retention for a given RAM, memory is * powered down in Stop mode. (Consumption is optimized) * @param RAMSelection: Specifies RAMs content to be lost in Stop mode. - * This parameter can be one or a combination of - * @ref PWREx_RAM_Contents_Stop_Retention. - * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention when available. + * This parameter can be one or a combination of the values: + * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention . * @arg PWR_SRAM2_FULL_STOP_RETENTION : full SRAM2 retention. - * @arg PWR_ICACHE_FULL_STOP_RETENTION : full I-CACHE RAM retention. + * @arg PWR_ICACHE_FULL_STOP_RETENTION : I-CACHE SRAM retention. * @retval None. */ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) @@ -605,12 +597,12 @@ void HAL_PWREx_DisableFlashFastWakeUp(void) * @} */ -/** @defgroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions - * @brief I/O pull-up / pull-down configuration functions +/** @defgroup PWREx_Exported_Functions_Group5 I/O Retention Functions + * @brief I/O retention functions * @verbatim =============================================================================== - ##### IOs configuration functions ##### + ##### IOs retention functions ##### =============================================================================== [..] In Standby mode, the GPIOs are by default in floating state. If Standby GPIO @@ -1046,7 +1038,7 @@ void HAL_PWREx_DisableREGVDDHPABypass(void) * @} */ -#endif /* defined (HAL_PWR_MODULE_ENABLED) */ +#endif /* defined(HAL_PWR_MODULE_ENABLED) */ /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rcc.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rcc.c index 7e293a4b0..e4b404d17 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rcc.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rcc.c @@ -1578,11 +1578,11 @@ void HAL_RCC_NMI_IRQHandler(void) /* Check RCC CSSF interrupt flag */ if (__HAL_RCC_GET_IT(RCC_IT_CSS)) { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); } } diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_sai.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_sai.c index 7973f9ce7..a764b53c8 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_sai.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_sai.c @@ -171,7 +171,7 @@ [..] Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. [..] @@ -186,10 +186,10 @@ [..] By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak functions: examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SAI_Init + reset to the legacy weak functions in the HAL_SAI_Init and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -206,7 +206,7 @@ [..] When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim ****************************************************************************** @@ -1344,6 +1344,12 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; @@ -1375,12 +1381,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) } } - /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - status = HAL_ERROR; - } - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1406,6 +1406,12 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Check SAI DMA is enabled or not */ if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { @@ -1445,12 +1451,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) hsai->Instance->IMR = 0; hsai->Instance->CLRFR = 0xFFFFFFFFU; - /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - status = HAL_ERROR; - } - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_smartcard.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_smartcard.c index 3ee8b3348..ebcdc2c38 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_smartcard.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_smartcard.c @@ -2490,7 +2490,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; } - MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg); + WRITE_REG(hsmartcard->Instance->RTOR, tmpreg); /*-------------------------- USART BRR Configuration -----------------------*/ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_smbus.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_smbus.c index 16c691e98..ccda2e6bf 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_smbus.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_smbus.c @@ -1007,8 +1007,15 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { - hsmbus->XferSize--; - hsmbus->XferCount--; + if (hsmbus->XferSize > 0U) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else + { + return HAL_ERROR; + } } } diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_spi.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_spi.c index 44c3974c4..cf6cc737a 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_spi.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_spi.c @@ -111,9 +111,8 @@ using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() or HAL_SPI_Init() function. - When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined, + the callback registering feature is not available and weak callbacks are used. SuspendCallback restriction: SuspendCallback is called only when MasterReceiverAutoSusp is enabled and @@ -152,7 +151,6 @@ * @{ */ #define SPI_DEFAULT_TIMEOUT 100UL -#define MAX_FIFO_LENGTH 16UL /** * @} */ @@ -568,6 +566,8 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) * the configuration information for the specified SPI. * @param CallbackID ID of the callback to be registered * @param pCallback pointer to the Callback function + * @note The HAL_SPI_RegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET + * to register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, @@ -582,8 +582,6 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call return HAL_ERROR; } - /* Lock the process */ - __HAL_LOCK(hspi); if (HAL_SPI_STATE_READY == hspi->State) { @@ -672,8 +670,6 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hspi); return status; } @@ -683,15 +679,14 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call * @param hspi Pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI. * @param CallbackID ID of the callback to be unregistered + * @note The HAL_SPI_UnRegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET + * to un-register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; - /* Lock the process */ - __HAL_LOCK(hspi); - if (HAL_SPI_STATE_READY == hspi->State) { switch (CallbackID) @@ -779,8 +774,6 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hspi); return status; } #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -837,31 +830,26 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData #endif /* __GNUC__ */ uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -919,11 +907,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -963,11 +952,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1012,11 +1002,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1032,16 +1023,19 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { return HAL_ERROR; } - return errorcode; + else + { + return HAL_OK; + } } /** @@ -1056,7 +1050,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; #if defined (__GNUC__) __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ @@ -1064,26 +1057,22 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1141,11 +1130,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1176,11 +1166,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1207,11 +1198,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1232,16 +1224,20 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { return HAL_ERROR; } - return errorcode; + else + { + return HAL_OK; + } } /** @@ -1257,22 +1253,19 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - HAL_StatusTypeDef errorcode = HAL_OK; #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ uint32_t tickstart; + uint32_t fifo_length; uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1281,18 +1274,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1310,6 +1302,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Set Full-Duplex mode */ SPI_2LINES(hspi); + /* Initialize FIFO length */ + if (IS_SPI_FULL_INSTANCE(hspi->Instance)) + { + fifo_length = SPI_HIGHEND_FIFO_SIZE; + } + else + { + fifo_length = SPI_LOWEND_FIFO_SIZE; + } + /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1324,10 +1326,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Transmit and Receive data in 32 Bit mode */ if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) { + /* Adapt fifo length to 32bits data width */ + fifo_length = (fifo_length / 4UL); + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { /* Check TXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) { *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); @@ -1350,11 +1356,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1362,10 +1369,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Transmit and Receive data in 16 Bit mode */ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { + /* Adapt fifo length to 16bits data width */ + fifo_length = (fifo_length / 2UL); + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { /* Check the TXP flag */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL)) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) { #if defined (__GNUC__) *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); @@ -1396,11 +1407,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1411,7 +1423,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { /* Check the TXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) { *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); @@ -1434,11 +1447,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1453,16 +1467,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { return HAL_ERROR; } - return errorcode; + else + { + return HAL_OK; + } } /** @@ -1475,28 +1492,22 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1540,6 +1551,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); + /* Enable EOT, TXP, FRE, MODF and UDR interrupts */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); @@ -1549,8 +1563,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -1563,28 +1576,22 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1632,6 +1639,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); + /* Enable EOT, RXP, OVR, FRE and MODF interrupts */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); @@ -1641,9 +1651,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - /* Unlock the process */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -1658,9 +1666,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; uint32_t tmp_TxXferCount; - #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); #endif /* __GNUC__ */ @@ -1668,23 +1674,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1755,6 +1757,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint } } + /* Unlock the process */ + __HAL_UNLOCK(hspi); + /* Enable EOT, DXP, UDR, OVR, FRE and MODF interrupts */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); @@ -1764,9 +1769,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - /* Unlock the process */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } @@ -1782,28 +1785,24 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode; + HAL_StatusTypeDef status; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1834,9 +1833,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE))) { /* Restriction the DMA data received is not allowed in this mode */ - errorcode = HAL_ERROR; __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } /* Adjust XferCount according to DMA alignment / Data size */ @@ -1905,39 +1903,30 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p /* Set DMA destination address */ hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; - errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmatx); + status = HAL_DMAEx_List_Start_IT(hspi->hdmatx); } else { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + status = HAL_ERROR; } } else { - errorcode = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, - hspi->TxXferCount); + status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount); } /* Check status */ - if (errorcode != HAL_OK) + if (status != HAL_OK) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + return HAL_ERROR; } /* Set the number of data at current transfer */ @@ -1967,7 +1956,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p /* Unlock the process */ __HAL_UNLOCK(hspi); - return errorcode; + + return HAL_OK; } /** @@ -1981,28 +1971,27 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode; + HAL_StatusTypeDef status; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2032,9 +2021,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) { /* Restriction the DMA data received is not allowed in this mode */ - errorcode = HAL_ERROR; __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } /* Clear RXDMAEN bit */ @@ -2103,39 +2091,30 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set DMA destination address */ hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; - errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmarx); + status = HAL_DMAEx_List_Start_IT(hspi->hdmarx); } else { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + status = HAL_ERROR; } } else { - errorcode = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, - hspi->RxXferCount); + status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount); } /* Check status */ - if (errorcode != HAL_OK) + if (status != HAL_OK) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + return HAL_ERROR; } /* Set the number of data at current transfer */ @@ -2165,7 +2144,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Unlock the process */ __HAL_UNLOCK(hspi); - return errorcode; + + return HAL_OK; } /** @@ -2181,28 +2161,24 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - HAL_StatusTypeDef errorcode; + HAL_StatusTypeDef status; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2229,10 +2205,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) { /* Restriction the DMA data received is not allowed in this mode */ - errorcode = HAL_ERROR; /* Unlock the process */ __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } /* Adjust XferCount according to DMA alignment / Data size */ @@ -2307,39 +2282,30 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Set DMA destination address */ hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; - errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmarx); + status = HAL_DMAEx_List_Start_IT(hspi->hdmarx); } else { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + status = HAL_ERROR; } } else { - errorcode = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, - hspi->RxXferCount); + status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount); } /* Check status */ - if (errorcode != HAL_OK) + if (status != HAL_OK) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + return HAL_ERROR; } /* Enable Rx DMA Request */ @@ -2381,39 +2347,33 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Set DMA destination address */ hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; - errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmatx); + status = HAL_DMAEx_List_Start_IT(hspi->hdmatx); } else { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + status = HAL_ERROR; } } else { - errorcode = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, - hspi->TxXferCount); + status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount); } /* Check status */ - if (errorcode != HAL_OK) + if (status != HAL_OK) { + /* Abort Rx DMA Channel already started */ + (void)HAL_DMA_Abort(hspi->hdmarx); + /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + return HAL_ERROR; } if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)) @@ -2442,7 +2402,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Unlock the process */ __HAL_UNLOCK(hspi); - return errorcode; + + return HAL_OK; } /** @@ -2487,8 +2448,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } - while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); /* Request a Suspend transfer */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); @@ -2500,8 +2460,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } - while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); /* Clear SUSP flag */ __HAL_SPI_CLEAR_SUSPFLAG(hspi); @@ -2513,8 +2472,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } - while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); } /* Disable the SPI DMA Tx request if enabled */ @@ -2570,12 +2528,12 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) hspi->ErrorCode = HAL_SPI_ERROR_NONE; } - /* Unlock the process */ - __HAL_UNLOCK(hspi); - /* Restore hspi->state to ready */ hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + return errorcode; } @@ -2621,8 +2579,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } - while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); /* Request a Suspend transfer */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); @@ -2634,8 +2591,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } - while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); /* Clear SUSP flag */ __HAL_SPI_CLEAR_SUSPFLAG(hspi); @@ -2647,8 +2603,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } - while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); } /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized @@ -2840,7 +2795,6 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) handled = 1UL; } - if (handled != 0UL) { return; @@ -3321,7 +3275,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) hspi->TxHalfCpltCallback(hspi); @@ -3338,7 +3293,8 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRA */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) hspi->RxHalfCpltCallback(hspi); @@ -3355,7 +3311,8 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) hspi->TxRxHalfCpltCallback(hspi); diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim.c index 983794003..de7fb7c7e 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim.c @@ -3854,7 +3854,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) { { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ @@ -3886,7 +3886,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) @@ -3916,7 +3916,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) @@ -3946,7 +3946,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) @@ -3976,7 +3976,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else @@ -3985,11 +3985,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Break input event */ - if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) + if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ + ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else @@ -4015,7 +4016,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else @@ -4028,7 +4029,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else @@ -4041,7 +4042,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->EncoderIndexCallback(htim); #else @@ -4054,7 +4055,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->DirectionChangeCallback(htim); #else @@ -4067,7 +4068,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IndexErrorCallback(htim); #else @@ -4080,7 +4081,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TransitionErrorCallback(htim); #else @@ -4634,7 +4635,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) { HAL_StatusTypeDef status = HAL_OK; uint32_t BlockDataLength = 0; @@ -5586,7 +5588,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /* Clear the OCREF clear selection bit */ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); - /* Clear TIMx_AF2_OCRSEL (reset value) */ + /* Set the clear input source */ MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); break; } @@ -7285,6 +7287,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; + + /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ + if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) + { + /* Clear the update flag */ + CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); + } } /** @@ -7409,7 +7418,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - } if (IS_TIM_BREAK_INSTANCE(TIMx)) diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim_ex.c index 76e9ff53f..714524960 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim_ex.c @@ -872,7 +872,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -1149,17 +1149,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - @endverbatim * @{ */ @@ -1403,7 +1392,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -2166,6 +2155,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); @@ -2182,15 +2172,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); - - /* Set BREAK AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { @@ -2198,20 +2180,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); - - /* Set BREAK2 AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); } /* Set TIMx_BDTR */ @@ -2235,7 +2210,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - { HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; @@ -2530,7 +2504,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B uint32_t tmpbdtr; /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) @@ -2547,7 +2521,6 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B } break; } - case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ @@ -2585,7 +2558,7 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint3 uint32_t tickstart; /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) @@ -2999,7 +2972,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim) */ /** - * @brief Hall commutation changed callback in non-blocking mode + * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3013,7 +2986,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) */ } /** - * @brief Hall commutation changed half complete callback in non-blocking mode + * @brief Commutation half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3028,7 +3001,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break detection callback in non-blocking mode + * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3043,7 +3016,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break2 detection callback in non blocking mode + * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ @@ -3283,6 +3256,11 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } else { /* nothing to do */ @@ -3314,13 +3292,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha { uint32_t tmp; - tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ } /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart.c index 7b70de996..e0e87bfde 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart.c @@ -965,10 +965,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = pCallback; } @@ -979,9 +976,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; } @@ -995,10 +989,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ } @@ -1009,8 +1000,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); return status; } @@ -3477,7 +3466,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ return HAL_TIMEOUT; } - if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) { diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_dma.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_dma.c index 4666d7d17..a828ceac1 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_dma.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_dma.c @@ -135,13 +135,13 @@ #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_TIM3_TRGO) #else #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_ADC4_AWD1) -#endif /* defined (TIM3) */ +#endif /* TIM3 */ #if defined (LPTIM2) #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM2_UE) #else #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM1_UE) -#endif /* defined (LPTIM2) */ +#endif /* LPTIM2 */ #define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \ ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \ @@ -200,7 +200,7 @@ #define IS_LL_DMA_CHANNEL_DEST_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_DEST_NSEC) || \ ((__VALUE__) == LL_DMA_CHANNEL_DEST_SEC)) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @} */ @@ -294,10 +294,10 @@ uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) #if defined (DMA_PRIVCFGR_PRIV0) /* Reset DMAx_Channely attribute */ LL_DMA_DisableChannelPrivilege(DMAx, Channel); -#endif /* defined (DMA_PRIVCFGR_PRIV0) */ +#endif /* DMA_PRIVCFGR_PRIV0 */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LL_DMA_DisableChannelSecure(DMAx, Channel); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ } return (uint32_t)status; @@ -624,7 +624,7 @@ void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct) /* Set DMA_InitNodeStruct fields to default values */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) DMA_InitNodeStruct->DestSecure = LL_DMA_CHANNEL_DEST_NSEC; -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0; DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE; DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE; @@ -633,7 +633,7 @@ void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct) DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) DMA_InitNodeStruct->SrcSecure = LL_DMA_CHANNEL_SRC_NSEC; -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0; DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE; DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD; @@ -696,7 +696,7 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) assert_param(IS_LL_DMA_CHANNEL_SRC_SEC(DMA_InitNodeStruct->SrcSecure)); assert_param(IS_LL_DMA_CHANNEL_DEST_SEC(DMA_InitNodeStruct->DestSecure)); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Check trigger polarity */ if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) @@ -744,7 +744,7 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestSecure | \ DMA_InitNodeStruct->SrcSecure); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Update CTR1 register fields */ pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \ @@ -900,11 +900,11 @@ void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t L * @} */ -#endif /* defined (GPDMA1) */ +#endif /* GPDMA1 */ /** * @} */ -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rcc.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rcc.c index 9a29f5454..7d95afada 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rcc.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rcc.c @@ -42,42 +42,51 @@ * @{ */ #if defined(USART2) -#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) +#define IS_LL_RCC_USART2_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) #else -#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART1_CLKSOURCE) +#define IS_LL_RCC_USART2_CLKSOURCE(__VALUE__) (0) #endif -#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || IS_LL_RCC_USART2_CLKSOURCE(__VALUE__)) #if defined(I2C1) -#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) +#define IS_LL_RCC_I2C1_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) #else -#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) +#define IS_LL_RCC_I2C1_CLKSOURCE(__VALUE__) (0) #endif +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ + || IS_LL_RCC_I2C1_CLKSOURCE(__VALUE__)) + #if defined(SPI1) -#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE)) +#define IS_LL_RCC_SPI1_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) #else -#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE) +#define IS_LL_RCC_SPI1_CLKSOURCE(__VALUE__) (0) #endif +#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI3_CLKSOURCE) \ + || IS_LL_RCC_SPI1_CLKSOURCE(__VALUE__)) + #if defined(LPTIM2) -#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)) +#define IS_LL_RCC_LPTIM2_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) #else -#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) +#define IS_LL_RCC_LPTIM2_CLKSOURCE(__VALUE__) (0) #endif +#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ + || IS_LL_RCC_LPTIM2_CLKSOURCE(__VALUE__)) + +#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) + #if defined(SAI1) #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) -#endif +#endif /* SAI1 */ #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_RNG_CLKSOURCE) #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_ADC_CLKSOURCE) + /** * @} */ @@ -740,12 +749,12 @@ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) } break; - case LL_RCC_RNG_CLKSOURCE_PLL1Q: /* PLL1Q clock used as RNG clock source */ + case LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2: /* PLL1Q/2 clock used as RNG clock source */ if (LL_RCC_PLL1_IsReady() != 0U) { if (LL_RCC_PLL1_IsEnabledDomain_PLL1Q() != 0U) { - rng_frequency = RCC_PLL1Q_GetFreqDomain(); + rng_frequency = RCC_PLL1Q_GetFreqDomain()/2U; } } break; @@ -816,6 +825,7 @@ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) } + /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_tim.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_tim.c index 95be8314e..04facfd21 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_tim.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_tim.c @@ -711,6 +711,8 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ @@ -723,8 +725,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); @@ -778,8 +778,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); @@ -807,8 +805,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); @@ -857,8 +857,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); @@ -886,8 +884,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); @@ -936,8 +936,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); @@ -965,8 +963,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); @@ -1015,8 +1015,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); @@ -1044,8 +1042,10 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U); @@ -1320,7 +1320,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - /* Select the Polarity and set the CC2E Bit */ + /* Select the Polarity and set the CC4E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_utils.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_utils.c index 513ea6e38..8073692d5 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_utils.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_utils.c @@ -133,7 +133,7 @@ static ErrorStatus UTILS_PLL_IsBusy(void); */ /** - * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with HCLK as SysTick clock source. * @note When a RTOS is used, it is recommended to avoid changing the Systick * configuration by calling this function, for a delay use rather osDelay RTOS service. * @param HCLKFrequency HCLK frequency in Hz @@ -147,16 +147,58 @@ void LL_Init1msTick(uint32_t HCLKFrequency) } /** - * @brief This function provides accurate delay (in milliseconds) based + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with HCLK/8 as SysTick clock source. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param HCLKFrequency HCLK frequency in Hz + * @retval None + */ +void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency) +{ + /* Configure the SysTick to have 1ms time base with HCLK/8 as SysTick clock source */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / 8000U) - 1UL); + SysTick->VAL = 0UL; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with LSE as SysTick clock source. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @retval None + */ +void LL_Init1msTick_LSE(void) +{ + /* Configure the SysTick to have 1ms time base with LSE as SysTick clock source */ + SysTick->LOAD = (uint32_t)((LSE_VALUE / 1000U) - 1UL); + SysTick->VAL = 0UL; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with LSI as SysTick clock source. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @retval None + */ +void LL_Init1msTick_LSI(void) +{ + /* Configure the SysTick to have 1ms time base with LSI as SysTick clock source */ + SysTick->LOAD = (uint32_t)((LSI_VALUE / 1000U) - 1UL); + SysTick->VAL = 0UL; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based * on SysTick counter flag * @note When a RTOS is used, it is recommended to avoid using blocking delay * and use rather osDelay service. * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which * will configure Systick to 1ms - * @param Delay specifies the delay time length, in milliseconds. + * @param Delay specifies the minimum delay time length, in milliseconds. * @retval None */ - void LL_mDelay(uint32_t Delay) { __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ diff --git a/stm32cube/stm32wbaxx/release_note.html b/stm32cube/stm32wbaxx/release_note.html index 82278524c..b820c609a 100644 --- a/stm32cube/stm32wbaxx/release_note.html +++ b/stm32cube/stm32wbaxx/release_note.html @@ -48,7 +48,7 @@

Purpose


-

The HAL/LL drivers provided within this package support the STM32WBA52xx product.

+

The HAL/LL drivers provided within this package support the STM32WBA52xx and STM32WBA55xx products.

For quick getting started with the STM32CubeWBA firmware package, you can refer to UM3131 and download firmware updates and all the latest documentation from www.st.com/stm32cubefw

Here is the list of references to user documents: