drivers: flash: flash_mcux_flexspi_hyperflash: disable cache during prgm

Disable the cache during erase and programming operations, as cache
pre-fetch operations can cause flash access outside of the application's
control

Also, reduce the SCLK frequency used after erase operations to 200MHz.
Without this, the RT1050 appears to hang after flash program operations

Signed-off-by: Daniel DeGrasse <[email protected]>

Author: danieldegrasse

drivers/flash/flash_mcux_flexspi_hyperflash.c

@@ -408,7 +408,6 @@ static int flash_flexspi_hyperflash_write(const struct device *dev, off_t offset
 		const void *buffer, size_t len)
 {
 	struct flash_flexspi_hyperflash_data *data = dev->data;
-	size_t size = len;
 	uint8_t *src = (uint8_t *)buffer;
 	unsigned int key = 0;
 	int i, j;
@@ -421,6 +420,11 @@ static int flash_flexspi_hyperflash_write(const struct device *dev, off_t offset
 		return -EINVAL;
 	}
 
+#ifdef CONFIG_HAS_MCUX_CACHE
+	L1CACHE_DisableICache();
+	L1CACHE_DisableDCache();
+#endif
+
 	if (memc_flexspi_is_running_xip(&data->controller)) {
 		/*
 		 * ==== ENTER CRITICAL SECTION ====
@@ -475,12 +479,13 @@ static int flash_flexspi_hyperflash_write(const struct device *dev, off_t offset
 		len -= i;
 	}
 
-	/* Clock FlexSPI at 332 MHZ (166 MHz SCLK in DDR mode) */
+	/* Clock FlexSPI at 200 MHZ (100 MHz SCLK in DDR mode) */
 	(void)memc_flexspi_update_clock(&data->controller, &data->config,
-					data->port, MHZ(332));
+					data->port, MHZ(200));
 
 #ifdef CONFIG_HAS_MCUX_CACHE
-	DCACHE_InvalidateByRange((uint32_t) dst, size);
+	L1CACHE_EnableICache();
+	L1CACHE_EnableDCache();
 #endif
 
 	if (memc_flexspi_is_running_xip(&data->controller)) {
@@ -503,6 +508,12 @@ static int flash_flexspi_hyperflash_erase(const struct device *dev, off_t offset
 			data->port,
 			offset);
 
+
+#ifdef CONFIG_HAS_MCUX_CACHE
+	L1CACHE_DisableICache();
+	L1CACHE_DisableDCache();
+#endif
+
 	if (!dst) {
 		return -EINVAL;
 	}
@@ -561,7 +572,8 @@ static int flash_flexspi_hyperflash_erase(const struct device *dev, off_t offset
 	}
 
 #ifdef CONFIG_HAS_MCUX_CACHE
-	DCACHE_InvalidateByRange((uint32_t) dst, size);
+	L1CACHE_EnableICache();
+	L1CACHE_EnableDCache();
 #endif
 
 	if (memc_flexspi_is_running_xip(&data->controller)) {