From cf6bad78c484383de6b564fe2738053a97d74582 Mon Sep 17 00:00:00 2001 From: Ederson de Souza Date: Fri, 29 Jul 2022 11:02:47 -0700 Subject: [PATCH] soc/xtensa/intel_adsp: Disable L2 cache at boot based on Kconfig Instead of deciding based on SoC version, add information to Kconfig and get it from there on code. Signed-off-by: Ederson de Souza --- soc/xtensa/intel_adsp/Kconfig | 3 +++ soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15 | 2 ++ soc/xtensa/intel_adsp/common/boot.c | 7 +------ 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/soc/xtensa/intel_adsp/Kconfig b/soc/xtensa/intel_adsp/Kconfig index 003b7c8e693e03..b21d7820f68c3b 100644 --- a/soc/xtensa/intel_adsp/Kconfig +++ b/soc/xtensa/intel_adsp/Kconfig @@ -90,4 +90,7 @@ config ADSP_INIT_HPSRAM help Need to init HP SRAM. +config ADSP_DISABLE_L2CACHE_AT_BOOT + bool + endif # SOC_FAMILY_INTEL_ADSP diff --git a/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15 b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15 index 469e167ca992ce..920a4d94701aba 100644 --- a/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15 +++ b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15 @@ -49,4 +49,6 @@ endif # DAI_INTEL_SSP config ADSP_INIT_HPSRAM default n +config ADSP_DISABLE_L2CACHE_AT_BOOT + default y endif diff --git a/soc/xtensa/intel_adsp/common/boot.c b/soc/xtensa/intel_adsp/common/boot.c index 353c5fd03a2bb4..06e30536062e6a 100644 --- a/soc/xtensa/intel_adsp/common/boot.c +++ b/soc/xtensa/intel_adsp/common/boot.c @@ -41,11 +41,6 @@ #define HOST_PAGE_SIZE 4096 #define MANIFEST_SEGMENT_COUNT 3 -/* FIXME: Use Kconfig or some other means */ -#if defined(CONFIG_SOC_INTEL_CAVS_V15) -#define PLATFORM_DISABLE_L2CACHE_AT_BOOT -#endif - /* FIXME: Use Kconfig or some other means */ #if !defined(CONFIG_SOC_SERIES_INTEL_ACE1X) #define RESET_MEMORY_HOLE @@ -161,7 +156,7 @@ __imr void boot_core0(void) { cpu_early_init(); -#ifdef PLATFORM_DISABLE_L2CACHE_AT_BOOT +#ifdef CONFIG_ADSP_DISABLE_L2CACHE_AT_BOOT ADSP_L2PCFG_REG = 0; #endif