From a8261b9214a24a21f9a516ea5a26375433498f18 Mon Sep 17 00:00:00 2001 From: Martin Kiepfer Date: Thu, 24 Aug 2023 06:55:29 +0200 Subject: [PATCH 1/4] boards: M5Stack Core2 module suppport This Pull-Request enables support for the M5Stack Core2 hardware. The module features a LCD display, touchscreen, battery, USB-Port, 8MB RAM and 16MB Flash. Basic features are working. Please refere to the board documentation for details. Signed-off-by: Martin Kiepfer gpio: gpio_axp192: fix dependecy between GET_DIRECTION and GET_CONFIG configuration Latest unit gpio get_direction unit test failes, as get_direction api internally requires get_config functionality. This commit fixes this dependecy. Signed-off-by: Martin Kiepfer --- boards/xtensa/m5stack_core2/Kconfig.board | 12 + boards/xtensa/m5stack_core2/Kconfig.defconfig | 51 ++++ boards/xtensa/m5stack_core2/board.cmake | 9 + .../m5stack_core2/doc/img/m5stack_core2.webp | Bin 0 -> 88824 bytes boards/xtensa/m5stack_core2/doc/index.rst | 194 ++++++++++++++ .../m5stack_core2/m5stack_core2-pinctrl.dtsi | 56 ++++ boards/xtensa/m5stack_core2/m5stack_core2.dts | 246 ++++++++++++++++++ .../xtensa/m5stack_core2/m5stack_core2.yaml | 20 ++ .../m5stack_core2/m5stack_core2_defconfig | 19 ++ .../xtensa/m5stack_core2/support/openocd.cfg | 5 + 10 files changed, 612 insertions(+) create mode 100644 boards/xtensa/m5stack_core2/Kconfig.board create mode 100644 boards/xtensa/m5stack_core2/Kconfig.defconfig create mode 100644 boards/xtensa/m5stack_core2/board.cmake create mode 100644 boards/xtensa/m5stack_core2/doc/img/m5stack_core2.webp create mode 100644 boards/xtensa/m5stack_core2/doc/index.rst create mode 100644 boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi create mode 100644 boards/xtensa/m5stack_core2/m5stack_core2.dts create mode 100644 boards/xtensa/m5stack_core2/m5stack_core2.yaml create mode 100644 boards/xtensa/m5stack_core2/m5stack_core2_defconfig create mode 100644 boards/xtensa/m5stack_core2/support/openocd.cfg diff --git a/boards/xtensa/m5stack_core2/Kconfig.board b/boards/xtensa/m5stack_core2/Kconfig.board new file mode 100644 index 00000000000000..9b48a15c24d084 --- /dev/null +++ b/boards/xtensa/m5stack_core2/Kconfig.board @@ -0,0 +1,12 @@ +# M5Stack Core2 board configuration + +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_CORE2 + bool "M5Stack Core2 Development Board" + depends on SOC_SERIES_ESP32 + +choice SOC_PART_NUMBER + default SOC_ESP32_D0WD_V3 +endchoice diff --git a/boards/xtensa/m5stack_core2/Kconfig.defconfig b/boards/xtensa/m5stack_core2/Kconfig.defconfig new file mode 100644 index 00000000000000..278ef95cd88407 --- /dev/null +++ b/boards/xtensa/m5stack_core2/Kconfig.defconfig @@ -0,0 +1,51 @@ +# M5Stack Core2 board configuration +# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STACK_CORE2 + +config BOARD + default "m5stack_core2" + depends on BOARD_M5STACK_CORE2 + +config ENTROPY_GENERATOR + default y + +config HEAP_MEM_POOL_SIZE + default 98304 if WIFI + default 65536 if BT + default 4096 + +config KERNEL_MEM_POOL + default y + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +config MFD_INIT_PRIORITY + default 60 + +config REGULATOR_AXP192_INIT_PRIORITY + default 76 + +config GPIO_AXP192_INIT_PRIORITY + default 80 + +config GPIO_HOGS_INIT_PRIORITY + default 81 + +config INPUT_FT5336_INTERRUPT + default y if INPUT + +config KSCAN + default y if DISPLAY + +config INPUT + default y if KSCAN + +config LV_COLOR_16_SWAP + default y if LVGL + +endif # BOARD_M5STACK_CORE2 diff --git a/boards/xtensa/m5stack_core2/board.cmake b/boards/xtensa/m5stack_core2/board.cmake new file mode 100644 index 00000000000000..2f04d1fe8861ea --- /dev/null +++ b/boards/xtensa/m5stack_core2/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/xtensa/m5stack_core2/doc/img/m5stack_core2.webp b/boards/xtensa/m5stack_core2/doc/img/m5stack_core2.webp new file mode 100644 index 0000000000000000000000000000000000000000..794c8e4c9cbe5944ac90334e7e8b8dab7e93e135 GIT binary patch literal 88824 zcmV)aK&rn|Nk&HSS^)r8MM6+kP&il$0000C0000V0{|Zb09H^qAnrZ^0MO9`odGH! z10VxFF%pJCq9F|DqKps$f>}^Y|E-rf#kEcSaBu0BQYI2b|2 zKmRZNr~HTg-|nCP|Ns6A|GWLW`**#+?f>Y%#(r-70REVNnf|N(Gyf0x-~a#r{<(kC zf3f$!{ulm-`@in~;D3^TO#eastM}*TU;WSd@AALBKQ#Zae~|xo{xkgF|No#5=0Dg! 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z2%iV9a>>vACT!U<`Y`F{;!Vmq2&~N4@2#7Kv(xUI(D4qLVRiZHp0)@6X@R*{+e@(2JvT9Ba@H%;jx;r(582r5 zs(-r(DooV}ystJs!G5zDWF~SwHL#@~S+{&4;Z|j8X~T@3MEBTz`+BGHE_rMp1YoQk zA^Jtb)&ARx8#B5IxA5d=@B~F;ra}R3L{bD)V(9}5V;4PU7&olP`LyYnZKA}kWt6?` z1#>4VW$i8WJe$@89L-hxOqymeM7Y@j>E*UY7xE1zL6M%x`MPV1M6Z*53e zL<&PgdK?gNxCa5uHhm9b+%r-rZ~$&qJG3eDo{z|dirv^F{LfYx`NL%X!qGt7;NDz| zNwvjt35J|t#hTFZiyQBf+z5n?26=izkEo*ZFxbkU-3RqW5SO1$YENEp!ay%vZOjP^pm69Lq=z^9LF)GWDE0eOFv zH@=QO)gXvo-AB#%`nFVDBBEAj#NuPq*=a$yKkJW_V32;(^)m{E0svCtFqE_cjkJUU z0Dw^D0=!uQCx8cRjc$f1DhHA5!X4}Nbr|;}$jAUt{uDw0fBxd3P#!rri$lTf4o|BHw z&CQM0jfvLI(Tt9PgM)*Po{^4`k>;lcjgyD1vw=H}trPKoG$3r^WaMaJ?`&abOYpA- z4GisEoOy^`Tr7+^O$|(042_LhXbcUQjA*;p9Z8BG}siT*>q zvC)5Ow|8;0{x{vmMsz0DCN?Iv&Q5d;vTn7&GBe?2)GdKMZ6CguO*Y0|PWGjP-WpXzbb{R_tb)Y1R7 zJ^z11i^A6)<7`fm~VZ&m)sy8glS-y-nes{D_2{r?Qt Se|fnkwm+_|+m8`` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! m5stack_core2 + +Debugging +--------- + +M5Stack Core2 debugging is not supported due to pinout limitations. + +Related Documents +***************** + +- `M5StickC PLUS schematic `_ (WEBP) +- `ESP32-PICO-D4 Datasheet `_ (PDF) +- `M5StickC PLUS docs `_ +- `ESP32 Datasheet `_ (PDF) +- `ESP32 Hardware Reference `_ diff --git a/boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi b/boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi new file mode 100644 index 00000000000000..658954ad18edd3 --- /dev/null +++ b/boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) + * Copyright (c) 2023 Martin Kiepfer + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_tx_gpio1: uart0_tx_gpio1 { + pinmux = ; + }; + + uart0_rx_gpio3: uart0_rx_gpio3 { + pinmux = ; + bias-pull-up; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + drive-open-drain; + output-high; + }; + }; + +}; diff --git a/boards/xtensa/m5stack_core2/m5stack_core2.dts b/boards/xtensa/m5stack_core2/m5stack_core2.dts new file mode 100644 index 00000000000000..93cfcf38741907 --- /dev/null +++ b/boards/xtensa/m5stack_core2/m5stack_core2.dts @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2023 Martin Kiepfer + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "m5stack_core2-pinctrl.dtsi" +#include +#include + +/ { + model = "esp32"; + compatible = "espressif,esp32"; + + aliases { + pwr-led = &pwr_led; + uart-0 = &uart0; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + rtc = &pfc8563_rtc; + led0 = &led_pwr; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,display = &ili9342c; + zephyr,keyboard-scan = &kscan_input; + zephyr,code-partition = &slot0_partition; + zephyr,rtc = &pfc8563_rtc; + }; + + leds { + compatible = "gpio-leds"; + led_pwr: led_pwr { + gpios = <&axp192_gpio 1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + label = "Power LED"; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&psram0 { + reg = <0x3f800000 DT_SIZE_M(8)>; + status = "disabled"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_tx_gpio1 &uart0_rx_gpio3>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + scl-timeout-us = <0>; + pinctrl-names = "default"; + + pfc8563_rtc: pfc8563@51 { + compatible = "nxp,pcf8523"; + reg = <0x51>; + status = "okay"; + battery-switch-over = "disabled"; + }; + + axp192_pmic: axp192@34 { + compatible = "x-powers,axp192"; + reg = <0x34>; + status = "okay"; + + axp192_regulator: axp192_regulator { + compatible = "x-powers,axp192-regulator"; + status = "okay"; + + vdd_mcu: DCDC1 { + regulator-init-microvolt = <3350000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + regulator-boot-on; + regulator-always-on; + }; + + lcd_bg: DCDC3 { + regulator-init-microvolt = <2800000>; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + v_peri: LDO2 { + regulator-init-microvolt = <3300000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + vib_motor: LDO3 { + regulator-init-microvolt = <2800000>; + }; + }; + + axp192_gpio: axp192_gpio { + compatible = "x-powers,axp192-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <5>; + status = "okay"; + + pwr_led: axp192_gpio1 { + gpio-hog; + gpios = <1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + output-high; + line-name = "pwr-led"; + }; + + bus_pwr_en: axp192_gpio0 { + gpio-hog; + gpios = <0 0>; + input; + }; + }; + }; + + ft5336@38 { + compatible = "focaltech,ft5336"; + reg = <0x38>; + int-gpios = <&gpio1 7 0>; + + kscan_input: kscan-input { + compatible = "zephyr,kscan-input"; + }; + }; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + dma-enabled; + clock-frequency = <20000000>; + cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + + ili9342c: ili9342c@0 { + compatible = "ilitek,ili9342c"; + spi-max-frequency = <30000000>; + reg = <0>; + cmd-data-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + vin-supply = <&lcd_bg>; + reset-gpios = <&axp192_gpio 4 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + pixel-format = ; + display-inversion; + width = <320>; + height = <240>; + rotation = <0>; + }; +}; + + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + reg = <0 DT_SIZE_M(16)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + /* 14MB storage */ + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00db0000>; + }; + }; +}; diff --git a/boards/xtensa/m5stack_core2/m5stack_core2.yaml b/boards/xtensa/m5stack_core2/m5stack_core2.yaml new file mode 100644 index 00000000000000..1ee36021b39bcd --- /dev/null +++ b/boards/xtensa/m5stack_core2/m5stack_core2.yaml @@ -0,0 +1,20 @@ +identifier: m5stack_core2 +name: M5Stack Core2 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - regulator + - uart + - pinmux + - nvs +testing: + default: true + ignore_tags: + - net + - bluetooth diff --git a/boards/xtensa/m5stack_core2/m5stack_core2_defconfig b/boards/xtensa/m5stack_core2/m5stack_core2_defconfig new file mode 100644 index 00000000000000..10fde73b47755c --- /dev/null +++ b/boards/xtensa/m5stack_core2/m5stack_core2_defconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BOARD_M5STACK_CORE2=y + +CONFIG_SOC_SERIES_ESP32=y + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_ESP_HEAP_MEM_POOL_REGION_1_SIZE=0 + +CONFIG_GPIO=y + +CONFIG_REGULATOR=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +# for debugging +CONFIG_SHELL=y diff --git a/boards/xtensa/m5stack_core2/support/openocd.cfg b/boards/xtensa/m5stack_core2/support/openocd.cfg new file mode 100644 index 00000000000000..338e6e4e6eae9a --- /dev/null +++ b/boards/xtensa/m5stack_core2/support/openocd.cfg @@ -0,0 +1,5 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +source [find interface/ftdi/esp32_devkitj_v1.cfg] +source [find target/esp32.cfg] From d06708f47daa0ea5196e97cffa50f3ad9b326d2c Mon Sep 17 00:00:00 2001 From: Martin Kiepfer Date: Fri, 8 Sep 2023 09:27:56 +0200 Subject: [PATCH 2/4] drivers: axp192_gpio: Fix for latest get_direction unit test This commit resolves an internal dependecy between GET_DIRECTION and GET_CONFIG configuration. GET_CONFIG api is internally needed by GET_DIRECTION api. Signed-off-by: Martin Kiepfer --- drivers/gpio/gpio_axp192.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio_axp192.c b/drivers/gpio/gpio_axp192.c index 95625d99dfe468..cf594c25abaa66 100644 --- a/drivers/gpio/gpio_axp192.c +++ b/drivers/gpio/gpio_axp192.c @@ -159,7 +159,18 @@ static int gpio_axp192_port_toggle_bits(const struct device *dev, gpio_port_pins return ret; } -#ifdef CONFIG_GPIO_GET_CONFIG +static int gpio_axp192_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, + enum gpio_int_mode mode, enum gpio_int_trig trig) +{ + ARG_UNUSED(dev); + ARG_UNUSED(pin); + ARG_UNUSED(mode); + ARG_UNUSED(trig); + + return -ENOTSUP; +} + +#if defined(CONFIG_GPIO_GET_CONFIG) || defined(CONFIG_GPIO_GET_DIRECTION) static int gpio_axp192_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *out_flags) { const struct gpio_axp192_config *config = dev->config; @@ -265,6 +276,7 @@ static const struct gpio_driver_api gpio_axp192_api = { .port_set_bits_raw = gpio_axp192_port_set_bits_raw, .port_clear_bits_raw = gpio_axp192_port_clear_bits_raw, .port_toggle_bits = gpio_axp192_port_toggle_bits, + .pin_interrupt_configure = gpio_axp192_pin_interrupt_configure, .manage_callback = gpio_axp192_manage_callback, #ifdef CONFIG_GPIO_GET_DIRECTION .port_get_direction = gpio_axp192_port_get_direction, From e5083795ed81acccb751b0ecbcf6849292f2d27e Mon Sep 17 00:00:00 2001 From: Martin Kiepfer Date: Wed, 30 Aug 2023 07:55:02 +0200 Subject: [PATCH 3/4] boards: m5stack_core2: Exclude board from device tree test m5stack_core2 enables i2c by default for regulator usage which conflicts with the test and is therefore excluded from the test. Signed-off-by: Martin Kiepfer --- tests/lib/devicetree/devices/testcase.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/lib/devicetree/devices/testcase.yaml b/tests/lib/devicetree/devices/testcase.yaml index b57489b9a11936..d7695220b8bdcb 100644 --- a/tests/lib/devicetree/devices/testcase.yaml +++ b/tests/lib/devicetree/devices/testcase.yaml @@ -14,4 +14,5 @@ tests: - bt610 - bl5340_dvk_cpuapp - bl5340_dvk_cpuapp_ns + - m5stack_core2 - mimxrt595_evk_cm33 From 751dcc47e59634afcad60f5ce889a2d3d2522535 Mon Sep 17 00:00:00 2001 From: Martin Kiepfer Date: Mon, 4 Sep 2023 19:58:14 +0200 Subject: [PATCH 4/4] devicetree: Add grove connector definition for m5stack_core2 Basic pinout definition. Signed-off-by: Martin Kiepfer --- .../m5stack_core2/grove_connectors.dtsi | 19 +++++++++++++++++++ .../m5stack_core2/m5stack_core2-pinctrl.dtsi | 17 +++++++++++++++++ boards/xtensa/m5stack_core2/m5stack_core2.dts | 17 +++++++++++++++++ 3 files changed, 53 insertions(+) create mode 100644 boards/xtensa/m5stack_core2/grove_connectors.dtsi diff --git a/boards/xtensa/m5stack_core2/grove_connectors.dtsi b/boards/xtensa/m5stack_core2/grove_connectors.dtsi new file mode 100644 index 00000000000000..3a49570382d9b5 --- /dev/null +++ b/boards/xtensa/m5stack_core2/grove_connectors.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2023 Joel Guittet + * Copyright (c) 2023 Martin Kiepfer + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + grove_header: grove_header { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio1 1 0>, /* D0/SCL/RX */ + <1 0 &gpio1 0 0>; /* D1/SDA/TX */ + }; +}; + +grove_i2c: &i2c1 {}; +grove_uart: &uart1 {}; diff --git a/boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi b/boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi index 658954ad18edd3..dce82fde545a71 100644 --- a/boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi +++ b/boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi @@ -20,6 +20,14 @@ bias-pull-up; }; + uart1_rx_gpio33: uart1_rx_gpio33 { + pinmux = ; + }; + + uart1_tx_gpio32: uart1_tx_gpio32 { + pinmux = ; + }; + spim3_default: spim3_default { group1 { pinmux = , @@ -53,4 +61,13 @@ }; }; + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + drive-open-drain; + output-high; + }; + }; + }; diff --git a/boards/xtensa/m5stack_core2/m5stack_core2.dts b/boards/xtensa/m5stack_core2/m5stack_core2.dts index 93cfcf38741907..0f804d5926b0a5 100644 --- a/boards/xtensa/m5stack_core2/m5stack_core2.dts +++ b/boards/xtensa/m5stack_core2/m5stack_core2.dts @@ -7,6 +7,7 @@ #include #include "m5stack_core2-pinctrl.dtsi" +#include "grove_connectors.dtsi" #include #include @@ -63,6 +64,13 @@ pinctrl-names = "default"; }; +&uart1 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart1_rx_gpio33 &uart1_tx_gpio32>; + pinctrl-names = "default"; +}; + &gpio0 { status = "okay"; }; @@ -157,6 +165,15 @@ }; }; +&i2c1 { + status = "disabled"; + clock-frequency = ; + sda-gpios = <&gpio0 32 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 33 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + &spi3 { #address-cells = <1>; #size-cells = <0>;