From b35df870af11e8d8837a6ba99354a2c6f110fd8a Mon Sep 17 00:00:00 2001 From: Eric Ackermann Date: Thu, 29 Aug 2024 10:58:33 +0200 Subject: [PATCH 1/2] soc: add OpenHW Group CVA6 SoC Adds support for the CVA6 family of RISC-V CPUs. CVA6 is commonly found as a soft core CPU on FPGA designs. Different configurations and instruction set extensions can be configured, and different SoCs targeting various FPGA boards are available. This commit adds support for the 32-bit and 64-bit configurations of CVA6, as well as three slightly different SoCs (a minimal 32-bit configuration, a 64-bit configuration without FPU, a 64-bit configuration with FPU). Signed-off-by: Eric Ackermann --- dts/riscv/openhwgroup/cv32a6.dtsi | 34 ++++ dts/riscv/openhwgroup/cv64a6.dtsi | 36 ++++ dts/riscv/openhwgroup/cva6.dtsi | 191 ++++++++++++++++++++ soc/openhwgroup/cva6/CMakeLists.txt | 17 ++ soc/openhwgroup/cva6/Kconfig | 8 + soc/openhwgroup/cva6/Kconfig.defconfig | 29 +++ soc/openhwgroup/cva6/Kconfig.soc | 31 ++++ soc/openhwgroup/cva6/cv32a6/CMakeLists.txt | 6 + soc/openhwgroup/cva6/cv32a6/Kconfig | 21 +++ soc/openhwgroup/cva6/cv32a6/Kconfig.soc | 21 +++ soc/openhwgroup/cva6/cv64a6/CMakeLists.txt | 6 + soc/openhwgroup/cva6/cv64a6/Kconfig | 35 ++++ soc/openhwgroup/cva6/cv64a6/Kconfig.soc | 31 ++++ soc/openhwgroup/cva6/cva6.h | 34 ++++ soc/openhwgroup/cva6/soc.yml | 11 ++ soc/openhwgroup/cva6/soc_cache_management.c | 25 +++ soc/openhwgroup/cva6/soc_poweroff.c | 41 +++++ soc/openhwgroup/cva6/soc_poweroff_fpga.c | 33 ++++ 18 files changed, 610 insertions(+) create mode 100644 dts/riscv/openhwgroup/cv32a6.dtsi create mode 100644 dts/riscv/openhwgroup/cv64a6.dtsi create mode 100644 dts/riscv/openhwgroup/cva6.dtsi create mode 100644 soc/openhwgroup/cva6/CMakeLists.txt create mode 100644 soc/openhwgroup/cva6/Kconfig create mode 100644 soc/openhwgroup/cva6/Kconfig.defconfig create mode 100644 soc/openhwgroup/cva6/Kconfig.soc create mode 100644 soc/openhwgroup/cva6/cv32a6/CMakeLists.txt create mode 100644 soc/openhwgroup/cva6/cv32a6/Kconfig create mode 100644 soc/openhwgroup/cva6/cv32a6/Kconfig.soc create mode 100644 soc/openhwgroup/cva6/cv64a6/CMakeLists.txt create mode 100644 soc/openhwgroup/cva6/cv64a6/Kconfig create mode 100644 soc/openhwgroup/cva6/cv64a6/Kconfig.soc create mode 100644 soc/openhwgroup/cva6/cva6.h create mode 100644 soc/openhwgroup/cva6/soc.yml create mode 100644 soc/openhwgroup/cva6/soc_cache_management.c create mode 100644 soc/openhwgroup/cva6/soc_poweroff.c create mode 100644 soc/openhwgroup/cva6/soc_poweroff_fpga.c diff --git a/dts/riscv/openhwgroup/cv32a6.dtsi b/dts/riscv/openhwgroup/cv32a6.dtsi new file mode 100644 index 00000000000000..5429088c1d3a64 --- /dev/null +++ b/dts/riscv/openhwgroup/cv32a6.dtsi @@ -0,0 +1,34 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright 2024 CISPA Helmholtz Center for Information Security + */ + +#include "cva6.dtsi" + +/* + * Least common denominator of CVA6 32-bit CPUs: no FPU, no compressed instructions, + * no MMU, no PMP. + * Boards can overwrite the node if additional configurations are available. + */ +/ { + cpus_0: cpus { + timebase-frequency = <25000000>; + + cpu_0: cpu { + clock-frequency = <50000000>; + device_type = "cpu"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv32ima"; + status="okay"; + + hlic: interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + status="okay"; + }; + }; + }; +}; diff --git a/dts/riscv/openhwgroup/cv64a6.dtsi b/dts/riscv/openhwgroup/cv64a6.dtsi new file mode 100644 index 00000000000000..535c9fd2424aff --- /dev/null +++ b/dts/riscv/openhwgroup/cv64a6.dtsi @@ -0,0 +1,36 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright 2024 CISPA Helmholtz Center for Information Security + */ + +#include "cva6.dtsi" +/* + * Application-class configuration of CVA6 64-bit CPUs: + * FPU for 32-bit and 64-bit floats, SV39 MMU. + * + */ +/ { + cpus_0: cpus { + timebase-frequency = <25000000>; + + cpu_0: cpu { + clock-frequency = <50000000>; + device_type = "cpu"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + tlb-split; + + status="okay"; + + hlic: interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + status="okay"; + }; + }; + }; +}; diff --git a/dts/riscv/openhwgroup/cva6.dtsi b/dts/riscv/openhwgroup/cva6.dtsi new file mode 100644 index 00000000000000..cae67c00ae8360 --- /dev/null +++ b/dts/riscv/openhwgroup/cva6.dtsi @@ -0,0 +1,191 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright 2024 CISPA Helmholtz Center for Information Security + */ + +/* + * CVA6 SoC without CPU, which comes in 32 and 64 bit variants + */ + +/ { + #address-cells = <0x01>; + #size-cells = <0x01>; + + clocks { + + clk_cpu { + #clock-cells = <0x00>; + clock-frequency = <50000000>; + compatible = "fixed-clock"; + }; + + clk_bus: clk_bus_0 { + #clock-cells = <0x00>; + clock-frequency = <50000000>; + compatible = "fixed-clock"; + }; + }; + + soc { + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + + /* Xilinx MIG memory controller */ + memory0:memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + status="okay"; + }; + + /* RISC-V Platform-level interrupt controller */ + plic: interrupt-controller@c000000 { + compatible = "sifive,plic-1.0.0"; + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&hlic 11 &hlic 9>; + reg = <0x0c000000 0x4000000>; + riscv,max-priority = <7>; + riscv,ndev = <30>; + status = "okay"; + }; + + /* USB UART */ + uart0:serial@10000000 { + clock-frequency = <50000000>; + clocks = <&clk_bus>; + compatible = "ns16550"; + current-speed = <115200>; + device_type = "serial"; + reg = <0x10000000 0x10000>; + reg-shift = <0x02>; + parity = "none"; + stop-bits = "1"; + data-bits = <8>; + + interrupt-parent = <&plic>; + interrupts = <11 0x04>; + + status="okay"; + }; + + /* SPI controller, connected to SD card */ + spi0: axi_quad_spi@20000000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "xlnx,xps-spi-2.00.a"; + reg = <0x20000000 0x10000>; + xlnx,num-ss-bits = <0x01>; + xlnx,num-transfer-bits = <0x8>; + interrupts=<10 4>; + interrupt-parent=<&plic>; + clocks=<&clk_bus>; + + status="okay"; + }; + + /* + * Core-local interrupt controller + * Clic in zephyr terminology, clint in CVA6 + */ + clint: clint_wrapper_verilog@2000000 { + compatible = "sifive,clint0"; + reg = <0x2000000 0x40000>; + interrupts-extended = <&hlic 3 &hlic 7>; + + status="okay"; + }; + + /* + * Xilinx AXI Ethernet subsystem and DMA. + * Only on CISPA fork of the project. + */ + dma0: dma@41e00000 { + #dma-cells = <0x01>; + clock-frequency = <50000000>; + clock-names = "s_axi_lite_aclk"; + clocks = <&clk_bus>; + compatible = "xlnx,eth-dma"; + reg = <0x41e00000 0x10000>; + xlnx,addrwidth = <0x40>; + xlnx,include-dre; + xlnx,num-queues = <0x1>; + + interrupt-parent = <&plic>; + // TX - RX + // active-high level-triggered + interrupts = <8 4>, <9 4>; + // TX and RX + dma-channels = <2>; + + status="disabled"; + }; + + axi-ethernet-subsystem@40c00000 { + reg = <0x40c00000 0x40000>; + compatible = "xlnx,axi-ethernet-subsystem-7.2"; + + eth0: ethernet-mac{ + axistream-connected = <&dma0>; + axistream-control-connected = <&dma0>; + clock-frequency = <50000000>; + compatible = "xlnx,axi-ethernet-7.2"; + local-mac-address = [00 0a 35 00 00 00]; /* change this in board device tree */ + device_type = "network"; + phy-mode = "rgmii"; + + /* full checksum offloading enabled */ + xlnx,rxcsum = <0x2>; + xlnx,txcsum = <0x2>; + + interrupt-parent = <&plic>; + interrupts = <13 4>; + + status="disabled"; + }; + + mdio0: mdio { + compatible = "xlnx,axi-ethernet-7.2-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + clock-frequency = <50000000>; + }; + }; + + /* + * LowRISC ethernet subsystem. + * Only on OpenHW Group original project. + */ + eth: lowrisc-eth@30000000 { + compatible = "lowrisc-eth"; + device_type = "network"; + interrupt-parent = <&plic>; + interrupts = <3 0>; + local-mac-address = [00 18 3e 02 e3 7f]; /* change this in board device tree */ + reg = <0x0 0x30000000 0x0 0x8000>; + }; + + /* Xilinx GPIO, connected to LEDs */ + xlnx_gpio: gpio@40000000 { + #gpio-cells = <2>; + compatible = "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x40000000 0x0 0x10000 >; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,gpio-width = <0x8>; + xlnx,gpio2-width = <0x8>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; + + status="disabled"; + }; + + }; +}; diff --git a/soc/openhwgroup/cva6/CMakeLists.txt b/soc/openhwgroup/cva6/CMakeLists.txt new file mode 100644 index 00000000000000..5389f664457762 --- /dev/null +++ b/soc/openhwgroup/cva6/CMakeLists.txt @@ -0,0 +1,17 @@ +# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) + +if(CONFIG_SOC_FAMILY_CVA6_PROVIDE_TEST_POWEROFF) + # need to force the linker to keep the symbol, such that the Ariane testbench can find it + set(CMAKE_EXE_LINKER_FLAGS "-u tohost" CACHE INTERNAL "" FORCE) +endif() + +zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_CVA6_PROVIDE_TEST_POWEROFF soc_poweroff.c) +zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS soc_cache_management.c) + + +zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF soc_poweroff_fpga.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/openhwgroup/cva6/Kconfig b/soc/openhwgroup/cva6/Kconfig new file mode 100644 index 00000000000000..a90cbce7cfd891 --- /dev/null +++ b/soc/openhwgroup/cva6/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_OPENHWGROUP_CVA6 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_OPENHWGROUP_CVA6 diff --git a/soc/openhwgroup/cva6/Kconfig.defconfig b/soc/openhwgroup/cva6/Kconfig.defconfig new file mode 100644 index 00000000000000..f58944db5a60de --- /dev/null +++ b/soc/openhwgroup/cva6/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_OPENHWGROUP_CVA6 + +rsource "*/Kconfig.defconfig" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 25000000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 13 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 186 + +config NUM_IRQS + default 186 + +endif # SOC_FAMILY_OPENHWGROUP_CVA6 diff --git a/soc/openhwgroup/cva6/Kconfig.soc b/soc/openhwgroup/cva6/Kconfig.soc new file mode 100644 index 00000000000000..0cc55c017eda6c --- /dev/null +++ b/soc/openhwgroup/cva6/Kconfig.soc @@ -0,0 +1,31 @@ +#Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +#SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_OPENHWGROUP_CVA6 + bool + select RISCV + help + CVA6 RISC-V CPUs, commonly used as soft cores on FPGAs. + There is a 64-bit version with imafdc extensions and sv39 MMU and + several 32-bit configurations, optionally with up to imafdc and sv32 MMU. + +config SOC_FAMILY + default "ariane_cva6" if SOC_FAMILY_OPENHWGROUP_CVA6 + + +config SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS + bool "Include non-standard cache management operations (currently global cache disable)" + depends on SOC_FAMILY_OPENHWGROUP_CVA6 + default n + +config SOC_FAMILY_CVA6_PROVIDE_TEST_POWEROFF + bool "Include methods for terminating a test in the CV32a6 test harness (hardware simulation)" + depends on SOC_FAMILY_OPENHWGROUP_CVA6 + default n + +config SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF + bool "Include methods for terminating a test on the FPGA" + depends on SOC_FAMILY_OPENHWGROUP_CVA6 + default n + +rsource "*/Kconfig.soc" diff --git a/soc/openhwgroup/cva6/cv32a6/CMakeLists.txt b/soc/openhwgroup/cva6/cv32a6/CMakeLists.txt new file mode 100644 index 00000000000000..da374abd68f7a5 --- /dev/null +++ b/soc/openhwgroup/cva6/cv32a6/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources() + +zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_OPENHWGROUP_CVA6 ".") diff --git a/soc/openhwgroup/cva6/cv32a6/Kconfig b/soc/openhwgroup/cva6/cv32a6/Kconfig new file mode 100644 index 00000000000000..a777f5f344387f --- /dev/null +++ b/soc/openhwgroup/cva6/cv32a6/Kconfig @@ -0,0 +1,21 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +# RISCV32 OpenHW Group cva6 configuration options + +config SOC_CV32A6 + select RISCV_PRIVILEGED + select ATOMIC_OPERATIONS_BUILTIN + select RISCV_GP + select RISCV_HAS_PLIC + select USE_SWITCH_SUPPORTED + select USE_SWITCH + select CPU_HAS_FPU + select CPU_HAS_FPU_DOUBLE_PRECISION + select SCHED_IPI_SUPPORTED + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select HAS_POWEROFF + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE diff --git a/soc/openhwgroup/cva6/cv32a6/Kconfig.soc b/soc/openhwgroup/cva6/cv32a6/Kconfig.soc new file mode 100644 index 00000000000000..4c1e5d460c1c68 --- /dev/null +++ b/soc/openhwgroup/cva6/cv32a6/Kconfig.soc @@ -0,0 +1,21 @@ +#Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +#SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CV32A6 + bool + select SOC_FAMILY_OPENHWGROUP_CVA6 + help + CVA6 32-bit RISC-V CPUs, commonly used as soft cores on FPGAs. + This configuration works with the upstream project (https://github.com/openhwgroup/cva6). + +config SOC_CV32A6 + bool + select SOC_SERIES_CV32A6 + help + Minimal CVA6 core in 32-bit configuration: ima extensions, no MMU or PMP, + SoC with CLINT, PLIC, UART, SPI, and Ethernet (Xilinx or lowRISC). +config SOC_SERIES + default "cv32a6" if SOC_SERIES_CV32A6 + +config SOC + default "cv32a6" if SOC_CV32A6 diff --git a/soc/openhwgroup/cva6/cv64a6/CMakeLists.txt b/soc/openhwgroup/cva6/cv64a6/CMakeLists.txt new file mode 100644 index 00000000000000..da374abd68f7a5 --- /dev/null +++ b/soc/openhwgroup/cva6/cv64a6/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources() + +zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_OPENHWGROUP_CVA6 ".") diff --git a/soc/openhwgroup/cva6/cv64a6/Kconfig b/soc/openhwgroup/cva6/cv64a6/Kconfig new file mode 100644 index 00000000000000..850e7c2b414124 --- /dev/null +++ b/soc/openhwgroup/cva6/cv64a6/Kconfig @@ -0,0 +1,35 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +# RISCV64 OpenHW Group cva6 configuration options + +# Shared properties +config SOC_CV64A6 + select RISCV_PRIVILEGED + select ATOMIC_OPERATIONS_BUILTIN + select RISCV_GP + select RISCV_HAS_PLIC + select USE_SWITCH_SUPPORTED + select USE_SWITCH + select SCHED_IPI_SUPPORTED + select 64BIT + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_F + select RISCV_ISA_EXT_D + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select HAS_POWEROFF + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + +# Variant with FPU +config SOC_CV64A6_IMAFDC + select SOC_CV64A6 + select CPU_HAS_FPU + select CPU_HAS_FPU_DOUBLE_PRECISION + +# Variant without FPU +config SOC_CV64A6_IMAC + select SOC_CV64A6 diff --git a/soc/openhwgroup/cva6/cv64a6/Kconfig.soc b/soc/openhwgroup/cva6/cv64a6/Kconfig.soc new file mode 100644 index 00000000000000..d37542b9ebb8f2 --- /dev/null +++ b/soc/openhwgroup/cva6/cv64a6/Kconfig.soc @@ -0,0 +1,31 @@ +#Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +#SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CV64A6 + bool + select SOC_FAMILY_OPENHWGROUP_CVA6 + help + CVA6 64-bit RISC-V CPUs, commonly used as soft cores on FPGAs. + This configuration works with the upstream project (https://github.com/openhwgroup/cva6) + as well as the forked project with support for the Xilinx AXI Ethernet Subsystem + (https://github.com/cispa/CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet). + +config SOC_CV64A6_IMAFDC + bool + select SOC_SERIES_CV64A6 + help + Standard CVA6 core in 64-bit configuration: SV39 MMU and SoC with CLINT, PLIC, UART, + SPI, and Ethernet (Xilinx or lowRISC). Supports imafdc instruction sets. + +config SOC_CV64A6_IMAC + bool + select SOC_SERIES_CV64A6 + help + Minimal CVA6 core in 64-bit configuration: SV39 MMU and SoC with CLINT, PLIC, UART, + SPI, and Ethernet (Xilinx or lowRISC). Supports imac instruction sets. + +config SOC_SERIES + default "cv64a6" if SOC_SERIES_CV64A6 + +config SOC + default "cv64a6" if SOC_CV64A6 diff --git a/soc/openhwgroup/cva6/cva6.h b/soc/openhwgroup/cva6/cva6.h new file mode 100644 index 00000000000000..f7cd36fd1530fd --- /dev/null +++ b/soc/openhwgroup/cva6/cva6.h @@ -0,0 +1,34 @@ +/* + * + * Copyright(c) 2024, CISPA Helmholtz Center for Information Security + * SPDX - License - Identifier : Apache-2.0 + */ + +/* + * @file + * OpenHwGroup CVA6 test harness success/failure callback + */ + +#ifndef ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H +#define ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * + * @brief In the cv[32|64]a6_testbench boards, inform the hardware simulator that + * a test case is over. In other cva6 boards, halts the CPU. + * + * @param status test status: 0 for success, other for failure + */ +void z_cva6_finish_test(const int32_t status); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H */ diff --git a/soc/openhwgroup/cva6/soc.yml b/soc/openhwgroup/cva6/soc.yml new file mode 100644 index 00000000000000..c1aaae2a79430e --- /dev/null +++ b/soc/openhwgroup/cva6/soc.yml @@ -0,0 +1,11 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +family: +- name: openhwgroup_cv64a6 + series: + - name: cv64a6 + socs: + - name: cv64a6 + - name: cv32a6 + socs: + - name: cv32a6 diff --git a/soc/openhwgroup/cva6/soc_cache_management.c b/soc/openhwgroup/cva6/soc_cache_management.c new file mode 100644 index 00000000000000..ec97f7284420bf --- /dev/null +++ b/soc/openhwgroup/cva6/soc_cache_management.c @@ -0,0 +1,25 @@ +/* + * Non-standard CVA6 cache management operations. + * + * Copyright(c) 2024, CISPA Helmholtz Center for Information Security + * SPDX - License - Identifier : Apache-2.0 + */ +#include +#include +#include + +void arch_dcache_enable(void) +{ + __asm__ volatile("csrwi 0x7C1, 0x01"); +} + +void arch_dcache_disable(void) +{ + __asm__ volatile("csrwi 0x7C1, 0x00"); +} + +/* FIXME there is no common implementation for RISC-V, so we provide a SoC-level definition */ +void __weak arch_cache_init(void) +{ + +} diff --git a/soc/openhwgroup/cva6/soc_poweroff.c b/soc/openhwgroup/cva6/soc_poweroff.c new file mode 100644 index 00000000000000..eb47f365c6dd53 --- /dev/null +++ b/soc/openhwgroup/cva6/soc_poweroff.c @@ -0,0 +1,41 @@ +/* + * CVA6 testbench poweroff / test finish operations. + * + * Copyright(c) 2024, CISPA Helmholtz Center for Information Security + * SPDX - License - Identifier : Apache-2.0 + */ +#include "cva6.h" + +#include +#include + +#include + +/* + * the CV64a6 testbench looks for a symbol called "tohost" and determines its load address + * when something is written to the symbol, this terminates the test + * the last bit of the written data indicate success or failure of the test + */ + +/* the test bench must be able to find the symbol in the ELF by reading its symbols + * this is accomplished using a linker script + */ + +volatile int32_t tohost; + +static int32_t cv64a6_test_status; + +void z_cva6_finish_test(const int32_t status) +{ + cv64a6_test_status = status; + + sys_poweroff(); +} + +void z_sys_poweroff(void) +{ + /* write to this special address signals to the sim that we wish to end the simulation */ + tohost = 0x1 | (cv64a6_test_status << 1); + + CODE_UNREACHABLE; +} diff --git a/soc/openhwgroup/cva6/soc_poweroff_fpga.c b/soc/openhwgroup/cva6/soc_poweroff_fpga.c new file mode 100644 index 00000000000000..d41ad6bec0ecd7 --- /dev/null +++ b/soc/openhwgroup/cva6/soc_poweroff_fpga.c @@ -0,0 +1,33 @@ +/* + * Busy-wait-forever poweroff for the CVA6 CPU on the FPGA + * + * Copyright(c) 2024, CISPA Helmholtz Center for Information Security + * SPDX - License - Identifier : Apache-2.0 + */ +#include "cva6.h" + +#include +#include + +#include + +void z_cva6_finish_test(const int32_t status) +{ + + printf("Finishing test with status %u-", status); + + if (status == 0) { + printf("TEST SUCCESS!\n"); + } else { + printf("TEST FAIL!\n"); + } + + sys_poweroff(); +} + +void z_sys_poweroff(void) +{ + printf("System poweroff!\n"); + for (;;) { + } +} From ac298c0d91a2f2e455a570066e2a86019e250f37 Mon Sep 17 00:00:00 2001 From: Eric Ackermann Date: Fri, 30 Aug 2024 10:47:29 +0200 Subject: [PATCH 2/2] boards: openhwgroup: add CVA6 on GenesysII board Adds support for the CVA6 CPU on a GenesysII FPGA board (https://github.com/openhwgroup/cva6). The SoC currently contains the CVA6 CPU with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the lowRISC ethernet subsystem. Two slightly different versions of the board are added, with a 64-bit and a 64-bit configuration of CVA6, respectively. Signed-off-by: Eric Ackermann --- .../cv32a6_genesysII/Kconfig.cv32a6_genesysII | 5 ++ .../openhwgroup/cv32a6_genesysII/board.cmake | 8 +++ boards/openhwgroup/cv32a6_genesysII/board.yml | 7 +++ .../cv32a6_genesysII/cv32a6_genesysII.dts | 58 +++++++++++++++++++ .../cv32a6_genesysII_defconfig | 40 +++++++++++++ .../cv32a6_genesysII/support/ariane.cfg | 49 ++++++++++++++++ .../cv64a6_genesysII/Kconfig.cv64a6_genesysII | 5 ++ .../openhwgroup/cv64a6_genesysII/board.cmake | 8 +++ boards/openhwgroup/cv64a6_genesysII/board.yml | 7 +++ .../cv64a6_genesysII/cv64a6_genesysII.dts | 58 +++++++++++++++++++ .../cv64a6_genesysII_defconfig | 40 +++++++++++++ .../cv64a6_genesysII/support/ariane.cfg | 49 ++++++++++++++++ 12 files changed, 334 insertions(+) create mode 100644 boards/openhwgroup/cv32a6_genesysII/Kconfig.cv32a6_genesysII create mode 100644 boards/openhwgroup/cv32a6_genesysII/board.cmake create mode 100644 boards/openhwgroup/cv32a6_genesysII/board.yml create mode 100644 boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII.dts create mode 100644 boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII_defconfig create mode 100644 boards/openhwgroup/cv32a6_genesysII/support/ariane.cfg create mode 100644 boards/openhwgroup/cv64a6_genesysII/Kconfig.cv64a6_genesysII create mode 100644 boards/openhwgroup/cv64a6_genesysII/board.cmake create mode 100644 boards/openhwgroup/cv64a6_genesysII/board.yml create mode 100644 boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII.dts create mode 100644 boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII_defconfig create mode 100644 boards/openhwgroup/cv64a6_genesysII/support/ariane.cfg diff --git a/boards/openhwgroup/cv32a6_genesysII/Kconfig.cv32a6_genesysII b/boards/openhwgroup/cv32a6_genesysII/Kconfig.cv32a6_genesysII new file mode 100644 index 00000000000000..5eec15ee619883 --- /dev/null +++ b/boards/openhwgroup/cv32a6_genesysII/Kconfig.cv32a6_genesysII @@ -0,0 +1,5 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +config BOARD_CV32A6_GENESYSII + select SOC_CV32A6 + select SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF \ No newline at end of file diff --git a/boards/openhwgroup/cv32a6_genesysII/board.cmake b/boards/openhwgroup/cv32a6_genesysII/board.cmake new file mode 100644 index 00000000000000..fffa2bed09562b --- /dev/null +++ b/boards/openhwgroup/cv32a6_genesysII/board.cmake @@ -0,0 +1,8 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg") +board_runner_args(openocd "--use-elf") +board_runner_args(openocd "--verify") +board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) \ No newline at end of file diff --git a/boards/openhwgroup/cv32a6_genesysII/board.yml b/boards/openhwgroup/cv32a6_genesysII/board.yml new file mode 100644 index 00000000000000..930b2788a08e4a --- /dev/null +++ b/boards/openhwgroup/cv32a6_genesysII/board.yml @@ -0,0 +1,7 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +board: + name: cv32a6_genesysII + vendor: openhwgroup + socs: + - name: cv32a6 \ No newline at end of file diff --git a/boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII.dts b/boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII.dts new file mode 100644 index 00000000000000..8926891a22a5d5 --- /dev/null +++ b/boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII.dts @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Openhardwaregroup CV32A6 on Genesys II"; + compatible = "ariane,cv32a6_genesysII"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &memory0; + }; +}; + +&uart0 { + status = "okay"; + // different interrupt than the CISPA version of the SoC + interrupts = <1 4>; +}; + +&spi0 { + status = "okay"; + // different interrupt than the CISPA version of the SoC + interrupts = <2 2>; +}; + +&clint{ + status = "okay"; +}; + +&dma0 { + status = "disabled"; +}; + + +&mdio0{ + status = "disabled"; +}; + +ð0 { + status = "disabled"; +}; + +ð { + status = "okay"; +}; + +&xlnx_gpio { + status = "okay"; +}; + + diff --git a/boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII_defconfig b/boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII_defconfig new file mode 100644 index 00000000000000..255ecb992244c2 --- /dev/null +++ b/boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII_defconfig @@ -0,0 +1,40 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_NS16550=y +CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y +CONFIG_CONSOLE_HANDLER=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=25000000 +CONFIG_FPU=y +CONFIG_POWEROFF=y + +# RNG +CONFIG_TIMER_RANDOM_GENERATOR=y +CONFIG_TEST_RANDOM_GENERATOR=y + +# IRQs +CONFIG_MULTI_LEVEL_INTERRUPTS=y +CONFIG_2ND_LEVEL_INTERRUPTS=y +# 1 PLIC +CONFIG_NUM_2ND_LEVEL_AGGREGATORS=1 +CONFIG_PLIC=y +CONFIG_3RD_LEVEL_INTERRUPTS=n + +# no networking support on this board + +# logging +CONFIG_LOG=y +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_THREAD_NAME=y + +# increased stack sizes +CONFIG_ISR_STACK_SIZE=524288 +CONFIG_MAIN_STACK_SIZE=524288 +CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=524288 +CONFIG_IDLE_STACK_SIZE=524288 \ No newline at end of file diff --git a/boards/openhwgroup/cv32a6_genesysII/support/ariane.cfg b/boards/openhwgroup/cv32a6_genesysII/support/ariane.cfg new file mode 100644 index 00000000000000..9bece8fca9c555 --- /dev/null +++ b/boards/openhwgroup/cv32a6_genesysII/support/ariane.cfg @@ -0,0 +1,49 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +# Based on the ariane.cfg from the cva6 project: +# https://github.com/openhwgroup/cva6/blob/master/corev_apu/fpga/ariane.cfg +adapter_khz 1000 + +interface ftdi +ftdi_vid_pid 0x0403 0x6010 + +# Channel 1 is taken by Xilinx JTAG +ftdi_channel 0 + +# links: +# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html +# +# Bit MPSSE FT2232 JTAG Type Description +# Bit0 TCK ADBUS0 TCK Out Clock Signal Output +# Bit1 TDI ADBUS1 TDI Out Serial Data Out +# Bit2 TDO ADBUS2 TDO In Serial Data In +# Bit3 TMS ADBUS3 TMS Out Select Signal Out +# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O +# this corresponds to the following in/out layout, with TMS initially set to 1 +ftdi_layout_init 0x0018 0x001b +# we only have to specify nTRST, the others are assigned correctly by default +ftdi_layout_signal nTRST -ndata 0x0010 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0 + +gdb_report_data_abort enable +gdb_report_register_access_error enable + +riscv set_reset_timeout_sec 120 +riscv set_command_timeout_sec 120 + +# prefer to use sba for system bus access +riscv set_prefer_sba off + +# Try enabling address translation (only works for newer versions) +if { [catch {riscv set_enable_virtual on} ] } { + echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." } + +init +halt +echo "Ready for Remote Connections" diff --git a/boards/openhwgroup/cv64a6_genesysII/Kconfig.cv64a6_genesysII b/boards/openhwgroup/cv64a6_genesysII/Kconfig.cv64a6_genesysII new file mode 100644 index 00000000000000..efc88b99877ff5 --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII/Kconfig.cv64a6_genesysII @@ -0,0 +1,5 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +config BOARD_CV64A6_GENESYSII + select SOC_CV64A6_IMAFDC + select SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF \ No newline at end of file diff --git a/boards/openhwgroup/cv64a6_genesysII/board.cmake b/boards/openhwgroup/cv64a6_genesysII/board.cmake new file mode 100644 index 00000000000000..fffa2bed09562b --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII/board.cmake @@ -0,0 +1,8 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg") +board_runner_args(openocd "--use-elf") +board_runner_args(openocd "--verify") +board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) \ No newline at end of file diff --git a/boards/openhwgroup/cv64a6_genesysII/board.yml b/boards/openhwgroup/cv64a6_genesysII/board.yml new file mode 100644 index 00000000000000..1c48d2b4f7de3e --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII/board.yml @@ -0,0 +1,7 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +board: + name: cv64a6_genesysII + vendor: openhwgroup + socs: + - name: cv64a6 \ No newline at end of file diff --git a/boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII.dts b/boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII.dts new file mode 100644 index 00000000000000..f1d86b80a9cfed --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII.dts @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Openhardwaregroup CV64A6 on Genesys II"; + compatible = "ariane,cv64a6_genesysII"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &memory0; + }; +}; + +&uart0 { + status = "okay"; + // different interrupt than the CISPA version of the SoC + interrupts = <1 4>; +}; + +&spi0 { + status = "okay"; + // different interrupt than the CISPA version of the SoC + interrupts = <2 2>; +}; + +&clint{ + status = "okay"; +}; + +&dma0 { + status = "disabled"; +}; + + +&mdio0{ + status = "disabled"; +}; + +ð0 { + status = "disabled"; +}; + +ð { + status = "okay"; +}; + +&xlnx_gpio { + status = "okay"; +}; + + diff --git a/boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII_defconfig b/boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII_defconfig new file mode 100644 index 00000000000000..255ecb992244c2 --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII_defconfig @@ -0,0 +1,40 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_NS16550=y +CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y +CONFIG_CONSOLE_HANDLER=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=25000000 +CONFIG_FPU=y +CONFIG_POWEROFF=y + +# RNG +CONFIG_TIMER_RANDOM_GENERATOR=y +CONFIG_TEST_RANDOM_GENERATOR=y + +# IRQs +CONFIG_MULTI_LEVEL_INTERRUPTS=y +CONFIG_2ND_LEVEL_INTERRUPTS=y +# 1 PLIC +CONFIG_NUM_2ND_LEVEL_AGGREGATORS=1 +CONFIG_PLIC=y +CONFIG_3RD_LEVEL_INTERRUPTS=n + +# no networking support on this board + +# logging +CONFIG_LOG=y +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_THREAD_NAME=y + +# increased stack sizes +CONFIG_ISR_STACK_SIZE=524288 +CONFIG_MAIN_STACK_SIZE=524288 +CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=524288 +CONFIG_IDLE_STACK_SIZE=524288 \ No newline at end of file diff --git a/boards/openhwgroup/cv64a6_genesysII/support/ariane.cfg b/boards/openhwgroup/cv64a6_genesysII/support/ariane.cfg new file mode 100644 index 00000000000000..9bece8fca9c555 --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII/support/ariane.cfg @@ -0,0 +1,49 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +# Based on the ariane.cfg from the cva6 project: +# https://github.com/openhwgroup/cva6/blob/master/corev_apu/fpga/ariane.cfg +adapter_khz 1000 + +interface ftdi +ftdi_vid_pid 0x0403 0x6010 + +# Channel 1 is taken by Xilinx JTAG +ftdi_channel 0 + +# links: +# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html +# +# Bit MPSSE FT2232 JTAG Type Description +# Bit0 TCK ADBUS0 TCK Out Clock Signal Output +# Bit1 TDI ADBUS1 TDI Out Serial Data Out +# Bit2 TDO ADBUS2 TDO In Serial Data In +# Bit3 TMS ADBUS3 TMS Out Select Signal Out +# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O +# this corresponds to the following in/out layout, with TMS initially set to 1 +ftdi_layout_init 0x0018 0x001b +# we only have to specify nTRST, the others are assigned correctly by default +ftdi_layout_signal nTRST -ndata 0x0010 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0 + +gdb_report_data_abort enable +gdb_report_register_access_error enable + +riscv set_reset_timeout_sec 120 +riscv set_command_timeout_sec 120 + +# prefer to use sba for system bus access +riscv set_prefer_sba off + +# Try enabling address translation (only works for newer versions) +if { [catch {riscv set_enable_virtual on} ] } { + echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." } + +init +halt +echo "Ready for Remote Connections"