From 13b5dc8fa6aecf897e4d37cb2742750ccf7634b9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Bj=C3=B6rnsson?= Date: Sun, 10 Nov 2024 04:45:20 +0100 Subject: [PATCH 1/5] dts: arm: st: f1: correct DMA interrupts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit remove an interrupt that doesn't exist for the STM32F103 line which caused gen_isr_tables.py to fail with error: IRQ 60 (offset=0) exceeds the maximum of 59. The interrupt does exist for STM32F105 and STM32F107 so most likely a copy-paste error. Signed-off-by: Benjamin Björnsson --- dts/arm/st/f1/stm32f103Xc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/arm/st/f1/stm32f103Xc.dtsi b/dts/arm/st/f1/stm32f103Xc.dtsi index d2a609a22de4..bc8bf8c2cfeb 100644 --- a/dts/arm/st/f1/stm32f103Xc.dtsi +++ b/dts/arm/st/f1/stm32f103Xc.dtsi @@ -159,7 +159,7 @@ #dma-cells = <2>; reg = <0x40020400 0x400>; clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; - interrupts = < 56 0 57 0 58 0 59 0 60 0>; + interrupts = < 56 0 57 0 58 0 59 0>; status = "disabled"; }; }; From 891aaba4bc580af6848bc69b6d25a0572f9bd578 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Bj=C3=B6rnsson?= Date: Sun, 10 Nov 2024 04:47:15 +0100 Subject: [PATCH 2/5] dts: arm: st: f1: add missing I2S nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds missing I2S nodes for the F1 series. Signed-off-by: Benjamin Björnsson --- dts/arm/st/f1/stm32f103Xe.dtsi | 26 ++++++++++++++++++++++++++ dts/arm/st/f1/stm32f103Xg.dtsi | 26 ++++++++++++++++++++++++++ dts/arm/st/f1/stm32f105Xc.dtsi | 26 ++++++++++++++++++++++++++ dts/arm/st/f1/stm32f107Xc.dtsi | 26 ++++++++++++++++++++++++++ 4 files changed, 104 insertions(+) diff --git a/dts/arm/st/f1/stm32f103Xe.dtsi b/dts/arm/st/f1/stm32f103Xe.dtsi index 18c0dcc83ff2..738ab7b7000c 100644 --- a/dts/arm/st/f1/stm32f103Xe.dtsi +++ b/dts/arm/st/f1/stm32f103Xe.dtsi @@ -18,5 +18,31 @@ erase-block-size = ; }; }; + + i2s2: i2s@40003800 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003800 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + interrupts = <36 5>; + dmas = <&dma1 5 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma1 4 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s3: i2s@40003c00 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003c00 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + interrupts = <51 5>; + dmas = <&dma2 2 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; }; }; diff --git a/dts/arm/st/f1/stm32f103Xg.dtsi b/dts/arm/st/f1/stm32f103Xg.dtsi index a40a4c403616..6bcc93c6adb8 100644 --- a/dts/arm/st/f1/stm32f103Xg.dtsi +++ b/dts/arm/st/f1/stm32f103Xg.dtsi @@ -29,6 +29,32 @@ }; }; + i2s2: i2s@40003800 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003800 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + interrupts = <36 5>; + dmas = <&dma1 5 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma1 4 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s3: i2s@40003c00 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003c00 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + interrupts = <51 5>; + dmas = <&dma2 2 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + timers9: timers@40014c00 { compatible = "st,stm32-timers"; reg = <0x40014c00 0x400>; diff --git a/dts/arm/st/f1/stm32f105Xc.dtsi b/dts/arm/st/f1/stm32f105Xc.dtsi index e2151b445485..b1fc75532307 100644 --- a/dts/arm/st/f1/stm32f105Xc.dtsi +++ b/dts/arm/st/f1/stm32f105Xc.dtsi @@ -18,5 +18,31 @@ reg = <0x08000000 DT_SIZE_K(256)>; }; }; + + i2s2: i2s@40003800 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003800 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + interrupts = <36 5>; + dmas = <&dma1 5 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma1 4 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s3: i2s@40003c00 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003c00 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + interrupts = <51 5>; + dmas = <&dma2 2 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; }; }; diff --git a/dts/arm/st/f1/stm32f107Xc.dtsi b/dts/arm/st/f1/stm32f107Xc.dtsi index ea7ad2e491cc..e5f0b4e233eb 100644 --- a/dts/arm/st/f1/stm32f107Xc.dtsi +++ b/dts/arm/st/f1/stm32f107Xc.dtsi @@ -18,5 +18,31 @@ reg = <0x08000000 DT_SIZE_K(256)>; }; }; + + i2s2: i2s@40003800 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003800 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + interrupts = <36 5>; + dmas = <&dma1 5 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma1 4 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s3: i2s@40003c00 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003c00 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + interrupts = <51 5>; + dmas = <&dma2 2 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; }; }; From 9146cd43de7c990d557a7d7942a1517edbfd00d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Bj=C3=B6rnsson?= Date: Wed, 13 Nov 2024 17:42:58 +0100 Subject: [PATCH 3/5] west.yml: Update STM32 HAL after adding F1 SDIO pinctrl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit updates hal_stm32 submodule after adding SDIO to F1 series pinctrl. Signed-off-by: Benjamin Björnsson --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 1d27186b2e9f..3d02dba4a3ec 100644 --- a/west.yml +++ b/west.yml @@ -233,7 +233,7 @@ manifest: groups: - hal - name: hal_stm32 - revision: 019d8255333f96bdd47d26b44049bd3e7af8ef55 + revision: pull/239/head path: modules/hal/stm32 groups: - hal From c26526bbcaacfe0718b2c6623df20670133a62f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Bj=C3=B6rnsson?= Date: Wed, 13 Nov 2024 19:40:10 +0100 Subject: [PATCH 4/5] drivers: disk: sdmmc_stm32: Add support for F1 series MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extend sdmmc driver to support the F1 series. This includes removing the RCC peripheral reset when building for F1 since this series doensn't have reset register for AHB peripherals. Therefore, it was neccesary to add an F1 specific compatible that removes the required resets property, as well as if-def the usage of reset in the device driver. Signed-off-by: Benjamin Björnsson --- drivers/disk/Kconfig.sdmmc | 2 +- drivers/disk/sdmmc_stm32.c | 9 +++++++++ dts/bindings/mmc/st,stm32f1-sdmmc.yaml | 15 +++++++++++++++ 3 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 dts/bindings/mmc/st,stm32f1-sdmmc.yaml diff --git a/drivers/disk/Kconfig.sdmmc b/drivers/disk/Kconfig.sdmmc index 42d82676b18f..8d8f560db765 100644 --- a/drivers/disk/Kconfig.sdmmc +++ b/drivers/disk/Kconfig.sdmmc @@ -37,7 +37,7 @@ config SDMMC_STM32 select USE_STM32_HAL_MMC if SDMMC_STM32_EMMC select USE_STM32_HAL_MMC_EX if SDMMC_STM32_EMMC && SOC_SERIES_STM32L4X select USE_STM32_LL_SDMMC - select USE_STM32_HAL_DMA if (SOC_SERIES_STM32L4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32F4X) + select USE_STM32_HAL_DMA if (SOC_SERIES_STM32L4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F1X) select DMA if $(DT_STM32_SDMMC_HAS_DMA) && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) select PINCTRL select RESET diff --git a/drivers/disk/sdmmc_stm32.c b/drivers/disk/sdmmc_stm32.c index 114e7d6b467a..4507ecd245ee 100644 --- a/drivers/disk/sdmmc_stm32.c +++ b/drivers/disk/sdmmc_stm32.c @@ -21,6 +21,7 @@ LOG_MODULE_REGISTER(stm32_sdmmc, CONFIG_SDMMC_LOG_LEVEL); #define STM32_SDMMC_USE_DMA DT_NODE_HAS_PROP(DT_DRV_INST(0), dmas) +#define STM32_SDMMC_USE_RESET !DT_NODE_HAS_COMPAT(DT_DRV_INST(0), st_stm32f1_sdmmc) #if STM32_SDMMC_USE_DMA #include @@ -84,7 +85,9 @@ struct stm32_sdmmc_priv { struct gpio_dt_spec pe; struct stm32_pclken *pclken; const struct pinctrl_dev_config *pcfg; +#if STM32_SDMMC_USE_RESET const struct reset_dt_spec reset; +#endif #if STM32_SDMMC_USE_DMA struct sdmmc_dma_stream dma_rx; @@ -302,11 +305,13 @@ static int stm32_sdmmc_access_init(struct disk_info *disk) return err; } +#if STM32_SDMMC_USE_RESET err = reset_line_toggle_dt(&priv->reset); if (err) { LOG_ERR("failed to reset peripheral"); return err; } +#endif #ifdef CONFIG_SDMMC_STM32_EMMC err = HAL_MMC_Init(&priv->hsd); @@ -690,10 +695,12 @@ static int disk_stm32_sdmmc_init(const struct device *dev) return -ENODEV; } +#if STM32_SDMMC_USE_RESET if (!device_is_ready(priv->reset.dev)) { LOG_ERR("reset control device not ready"); return -ENODEV; } +#endif /* Configure dt provided device signals when available */ err = pinctrl_apply_state(priv->pcfg, PINCTRL_STATE_DEFAULT); @@ -812,7 +819,9 @@ static struct stm32_sdmmc_priv stm32_sdmmc_priv_1 = { #endif .pclken = pclken_sdmmc, .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0), +#if STM32_SDMMC_USE_RESET .reset = RESET_DT_SPEC_INST_GET(0), +#endif SDMMC_DMA_CHANNEL(rx, RX) SDMMC_DMA_CHANNEL(tx, TX) }; diff --git a/dts/bindings/mmc/st,stm32f1-sdmmc.yaml b/dts/bindings/mmc/st,stm32f1-sdmmc.yaml new file mode 100644 index 000000000000..3db3cf52dd79 --- /dev/null +++ b/dts/bindings/mmc/st,stm32f1-sdmmc.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Benjamin Björnsson benjamin.bjornsson@gmail.com + +# SPDX-License-Identifier: Apache-2.0 + +description: | + ST STM32F1 family SDIO + Remove the resets property since there's no reset register + for AHB peripherals on F1 series. + +compatible: "st,stm32f1-sdmmc" + +include: + - name: st,stm32-sdmmc.yaml + property-blocklist: + - resets From b94c7a9ae9854a324fce3e0216aaab34b1678493 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Bj=C3=B6rnsson?= Date: Wed, 13 Nov 2024 19:49:25 +0100 Subject: [PATCH 5/5] dts: arm: st: f1: Add support for SDMMC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add sdmmc node to f103, this should cover all F1 series DTS files since SDIO exists on f103x(e-g) and f103xg dts file includes f103xe dtsi. Signed-off-by: Benjamin Björnsson --- dts/arm/st/f1/stm32f103Xe.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/dts/arm/st/f1/stm32f103Xe.dtsi b/dts/arm/st/f1/stm32f103Xe.dtsi index 738ab7b7000c..e622a4f811e9 100644 --- a/dts/arm/st/f1/stm32f103Xe.dtsi +++ b/dts/arm/st/f1/stm32f103Xe.dtsi @@ -44,5 +44,13 @@ dma-names = "tx", "rx"; status = "disabled"; }; + + sdmmc1: sdmmc@40018000 { + compatible = "st,stm32f1-sdmmc", "st,stm32-sdmmc"; + reg = <0x40018000 0x400>; + clocks = <&rcc STM32_CLOCK(AHB1, 10U)>; + interrupts = <49 0>; + status = "disabled"; + }; }; };