Verilog Syntax Examples

This repository is based on "Lab 1 Brief" documentation, which shows examples for Verilog syntax with testbenches (both Verilog testbenches and Cocotb testbenches).

• Example 1: AND Gate
• Example 2: 1-bit Full Adder
• Example 3: 4-bit Full Adder
• Example 4: 4-input Multiplexer
• Example 5: D Flip Flop
• Example 6: Parameterized Full Adder (N-bit Full Adder)

Running Cocotb Tests

To run Cocotb testbenches, you need to install Cocotb (using Python 3.6+) with GNU Make and Icarus Verilog. The guide for installation is on the lab 1 brief documentation.

• Go to the directory of example we want to run testbench and go to test directory.

cd test

• If Conda or Miniconda is used, activate the virtual environment that contains Cocotb and Pytest libraries.

conda activate <venv_name>

• Run the test using GNU Make.

make