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core-v-mini-mcu.core
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CAPI=2:
# Copyright 2022 OpenHW Group
# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
name: openhwgroup.org:systems:core-v-mini-mcu
description: CORE-V MINI-MCU Top.
filesets:
files_rtl_generic:
depend:
- x-heep::packages
- openhwgroup.org:ip:cv32e40p
- pulp-platform.org:ip:fpnew
- pulp-platform.org::common_cells
- pulp-platform.org::cluster_interconnect
- pulp-platform.org::riscv_dbg
- pulp-platform.org::register_interface
- openhwgroup.org:ip:soc_ctrl
- lowrisc:ip:uart:0.1
- lowrisc:ip:rv_plic_example:0.1
- lowrisc:ibex:ibex_core:0.1
- lowrisc:ip:rv_timer:0.1
- lowrisc:ip:gpio:0.1
- lowrisc:ip:spi_host:0.1
- yosyshq:picorv32_spimemio:0-r1
- x-heep:obi_spimemio:0.1.0
- x-heep:ip:boot_rom
files:
- hw/core-v-mini-mcu/core_v_mini_mcu.sv
- hw/core-v-mini-mcu/cpu_subsystem.sv
- hw/core-v-mini-mcu/memory_subsystem.sv
- hw/core-v-mini-mcu/system_bus.sv
- hw/core-v-mini-mcu/system_xbar.sv
- hw/core-v-mini-mcu/spi_subsystem.sv
- hw/core-v-mini-mcu/debug_subsystem.sv
- hw/core-v-mini-mcu/peripheral_subsystem.sv
- hw/core-v-mini-mcu/reg_to_tlul.sv
file_type: systemVerilogSource
rtl-simulation:
depend:
- pulp-platform.org::tech_cells_generic
files:
- hw/simulation/sram_wrapper.sv
- hw/simulation/pad_cell.sv
file_type: systemVerilogSource
tb-utils:
depend:
- x-heep::tb-utils
files_verilator_waiver:
depend:
- openhwgroup.org:ip:verilator_waiver
files:
- hw/core-v-mini-mcu/core_v_mini_mcu.vlt
- hw/ip/soc_ctrl/soc_ctrl.vlt
- hw/ip/boot_rom/boot_rom.vlt
- hw/ip/obi_spimemio/obi_spimemio.vlt
file_type: vlt
rtl-fpga:
files:
- hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
- hw/fpga/sram_wrapper.sv
file_type: systemVerilogSource
ip-fpga:
files:
- hw/fpga/scripts/xilinx_generate_clk_wizard.tcl: { file_type: tclSource }
- hw/fpga/scripts/generate_sram.tcl: { file_type: tclSource }
- hw/fpga/prim_xilinx_clk.sv: { file_type: systemVerilogSource }
- hw/fpga/cv32e40p_xilinx_clock_gate.sv: { file_type: systemVerilogSource }
- hw/fpga/pad_cell_xilinx.sv: { file_type: systemVerilogSource }
ip-asic:
depend:
- technology::prim_mytech
xdc-fpga-nexys:
files:
- hw/fpga/constraints/nexys/pin_assign.xdc
- hw/fpga/constraints/nexys/constraints.xdc
file_type: xdc
xdc-fpga-pynq-z2:
files:
- hw/fpga/constraints/pynq-z2/pin_assign.xdc
file_type: xdc
netlist-fpga:
files:
- build/openhwgroup.org_systems_core-v-mini-mcu_0/nexys-a7-100t-vivado/core_v_mini_mcu_xiling_postsynth.v
file_type: verilogSource
# Scripts for hooks
post_build_modelsim_scripts:
files:
- scripts/sim/modelsim/post_build_modelsim_vopt.sh
file_type: user
pre_build_remote_bitbang:
files:
- scripts/sim/compile_remote_bitbang.sh
file_type: user
pre_build_uartdpi:
files:
- scripts/sim/compile_uart_dpi.sh
file_type: user
pre_patch_modelsim_Makefile:
files:
- scripts/sim/modelsim/patch_modelsim_Makefile.py
file_type: user
tb-verilator:
files:
- tb/tb_top.cpp
file_type: cppSource
tb-sv:
files:
- tb/tb_top.sv
file_type: systemVerilogSource
parameters:
PULP_XPULP:
datatype: int
paramtype: vlogparam
default: 0
JTAG_DPI:
datatype: int
paramtype: vlogparam
default: 0
USE_EXTERNAL_DEVICE_EXAMPLE:
datatype: bool
paramtype: vlogdefine
default: false
SYNTHESIS:
datatype: bool
paramtype: vlogdefine
default: false
FPGA_NETLIST:
datatype: bool
paramtype: vlogdefine
default: false
# Make the parameter known to FuseSoC to enable overrides from the
# command line. If not overwritten, use the generic technology library.
PRIM_DEFAULT_IMPL:
datatype: str
paramtype: vlogdefine
description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
default: prim_pkg::ImplGeneri
scripts:
post_build_modelsim_scripts:
cmd:
- sh
- ../../../scripts/sim/modelsim/post_build_modelsim_vopt.sh
pre_build_remote_bitbang:
cmd:
- sh
- ../../../scripts/sim/compile_remote_bitbang.sh
pre_build_uartdpi:
cmd:
- sh
- ../../../scripts/sim/compile_uart_dpi.sh
pre_patch_modelsim_Makefile:
cmd:
- python
- ../../../scripts/sim/modelsim/patch_modelsim_Makefile.py
targets:
default: &default_target
filesets:
- files_rtl_generic
- target_sim ? (rtl-simulation)
- target_sim_opt ? (rtl-simulation)
- target_sim ? (tool_verilator? (files_verilator_waiver))
toplevel: [core_v_mini_mcu]
sim:
<<: *default_target
default_tool: modelsim
filesets_append:
- tb-utils
- tool_modelsim? (pre_build_remote_bitbang)
- tool_modelsim? (pre_build_uartdpi)
- tool_modelsim? (pre_patch_modelsim_Makefile)
- tool_vcs? (pre_build_remote_bitbang)
- tool_vcs? (pre_build_uartdpi)
- tool_verilator? (tb-verilator)
- tool_modelsim? (tb-sv)
- tool_vcs? (tb-sv)
toplevel:
- tool_modelsim? (tb_top)
- tool_vcs? (tb_top)
- tool_verilator? (testharness)
hooks:
pre_build:
- tool_modelsim? (pre_build_uartdpi)
- tool_modelsim? (pre_build_remote_bitbang)
- tool_modelsim? (pre_patch_modelsim_Makefile) # this is required by Questa 2020 on
parameters:
- PULP_XPULP=0
- use_jtag_dpi? (JTAG_DPI=1)
- "!use_jtag_dpi? (JTAG_DPI=0)"
- use_external_device_example? (USE_EXTERNAL_DEVICE_EXAMPLE=true)
tools:
modelsim:
vlog_options:
- -override_timescale 1ns/1ps
- -suppress vlog-2583
- -suppress vlog-2577
- -pedanticerrors
- -define MODELSIM
vsim_options:
- -sv_lib ../../../hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi
- -sv_lib ../../../hw/vendor/pulp_platform_pulpissimo/rtl/tb/remote_bitbang/librbs
vcs:
vcs_options:
- -override_timescale=1ns/1ps
- -assert disable_cover
- -assert svaext
- -debug_access+all
- -fgp
- -kdb
- -notice
- -ntb_opts error
- -race=all
- -xlrm uniq_prior_final
- -CFLAGS "-std=c++14 -pthread"
- -LDFLAGS "-pthread -lutil"
- -V
verilator:
mode: cc
verilator_options:
- '--cc'
- '--trace'
- '--trace-fst'
- '--trace-structs'
- '--trace-params'
- '--trace-max-array 1024'
- '--x-assign unique'
- '--x-initial unique'
- '--exe tb_top.cpp'
- '-CFLAGS "-std=c++11 -Wall -g -fpermissive"'
- '-LDFLAGS "-pthread -lutil -lelf"'
- "-Wall"
sim_opt:
<<: *default_target
default_tool: modelsim
filesets_append:
- tb-utils
- pre_build_remote_bitbang
- pre_build_uartdpi
- pre_patch_modelsim_Makefile
- post_build_modelsim_scripts
- tb-sv
toplevel: [tb_top_vopt]
hooks:
pre_build:
- pre_build_uartdpi
- pre_build_remote_bitbang
- pre_patch_modelsim_Makefile # this is required by Questa 2020 on
post_build: [post_build_modelsim_scripts]
parameters:
- PULP_XPULP=0
- use_jtag_dpi? (JTAG_DPI=1)
- "!use_jtag_dpi? (JTAG_DPI=0)"
- use_external_device_example? (USE_EXTERNAL_DEVICE_EXAMPLE=true)
tools:
modelsim:
vlog_options:
- -override_timescale 1ns/1ps
- -suppress vlog-2583
- -suppress vlog-2577
- -pedanticerrors
- -define MODELSIM
vsim_options:
- -sv_lib ../../../hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi
- -sv_lib ../../../hw/vendor/pulp_platform_pulpissimo/rtl/tb/remote_bitbang/librbs
nexys-a7-100t:
<<: *default_target
default_tool: vivado
description: Digilent Nexys-A7-100T Board
filesets_append:
- rtl-fpga
- ip-fpga
- xdc-fpga-nexys
parameters:
- PULP_XPULP=0
- SYNTHESIS=true
tools:
vivado:
part: xc7a100tcsg324-1
toplevel: [core_v_mini_mcu]
pynq-z2:
<<: *default_target
default_tool: vivado
description: TUL Pynq-Z2 Board
filesets_append:
- rtl-fpga
- ip-fpga
- xdc-fpga-pynq-z2
parameters:
- PULP_XPULP=0
- SYNTHESIS=true
tools:
vivado:
part: xc7z020clg400-1
toplevel: [xilinx_core_v_mini_mcu_wrapper]
sim_nexys_netlist:
filesets:
- netlist-fpga
- tb-rtl
- post_build_modelsim_scripts
toplevel: [tb_top_vopt]
hooks:
post_build: [post_build_modelsim_scripts]
parameters:
- PULP_XPULP=0
- FPGA_NETLIST=true
tools:
modelsim:
vlog_options:
- -override_timescale 1ns/1ps
- -suppress vlog-2583
- -suppress vlog-2577
- -pedanticerrors
asic_synthesis:
<<: *default_target
default_tool: design_compiler
description: Design Compiler Script
parameters:
- PULP_XPULP=0
- SYNTHESIS=true
filesets_append:
- ip-asic
parameters:
- PRIM_DEFAULT_IMPL=prim_pkg::your_target_technology
toplevel: [core_v_mini_mcu]
tools:
design_compiler:
script_dir:
- ../../../scripts/synthesis/dc_shell
report_dir:
- report
dc_script:
- dc_script.tcl