Pinned Loading

1. RV32I_Single_Cycle_CPU RV32I_Single_Cycle_CPU Public

   Processor Design of RV32I Single Cycle CPU

   SystemVerilog

2. UART UART Public

   RTL Design of Universal Asynchronous Receiver-Transmitter

   Verilog 1

3. SPI SPI Public

   RTL Design of Serial Peripheral Interface

   Verilog 1

4. AXI4 AXI4 Public

   RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle

   Verilog 4

5. ARTY_A7_I2C_BME280 ARTY_A7_I2C_BME280 Public

   Integration of Arty A7-100T with BME280 Pressure Sensor for Pressure Sensing and FPGA Testing

   Verilog

6. ARTY_A7_I2C_MPU-6050 ARTY_A7_I2C_MPU-6050 Public

   Integration of Arty A7-100T with MPU-6050 Gyroscope Sensor for Motion Sensing and FPGA Testing

   Verilog 1