-
MERL-UITU
- Karachi, Pakistan
-
10:37
(UTC +05:00) - in/ammar-bin-amir
Block or Report
Block or report Ammar-Bin-Amir
Contact GitHub support about this user’s behavior. Learn more about reporting abuse.
Report abusePinned Loading
-
RV32I_Single_Cycle_CPU
RV32I_Single_Cycle_CPU PublicProcessor Design of RV32I Single Cycle CPU
SystemVerilog
-
RV32I_5-Stage_Pipelined_CPU
RV32I_5-Stage_Pipelined_CPU PublicProcessor Design of RV32I 5-Stage Pipelined CPU
SystemVerilog
-
AXI4
AXI4 PublicRTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
Verilog
-
ARTY_A7_I2C_BME280
ARTY_A7_I2C_BME280 PublicIntegration of Arty A7-100T with BME280 Pressure Sensor for Pressure Sensing and FPGA Testing
Verilog
-
ARTY_A7_I2C_MPU-6050
ARTY_A7_I2C_MPU-6050 PublicIntegration of Arty A7-100T with MPU-6050 Gyroscope Sensor for Motion Sensing and FPGA Testing
Verilog
If the problem persists, check the GitHub status page or contact support.