Skip to content
View ArioKian's full-sized avatar

Block or report ArioKian

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
ArioKian/README.md
  • 👋 Hi, I’m @ArioKian
  • 👀 Interested in FPGA and Embedded System on Chip Designs based on Xilinx Zynq Soc Devices
  • 🌱 Side-Channel Analysis Researcher
  • 📫 How to reach me : [email protected]

Popular repositories Loading

  1. Xilinx-Zynq7000-ZynqUltraScalePlus-PS-SdCard-Drivers Xilinx-Zynq7000-ZynqUltraScalePlus-PS-SdCard-Drivers Public

    Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.

    C 1

  2. ArioKian ArioKian Public

    Config files for my GitHub profile.

  3. Xilinx-Zynq7000-PS-SLCR-Registers-Drivers Xilinx-Zynq7000-PS-SLCR-Registers-Drivers Public

    Zynq-7000 PS side drivers for SLCR Registers.

    C

  4. Correlation-Power-Analysis Correlation-Power-Analysis Public

    a Python Class including codes and methods to perform statistical correlation power analysis on AES-128 Encryption

    Python

  5. Xilinx-7-Series-FPGAs-Device-DNA Xilinx-7-Series-FPGAs-Device-DNA Public

    Two VHDL codes, including one for extracting the so called unique Device DNA of Xilinx 7-Series FPGA, and another for utilizing this extracted DNA in order to prevent the project to be cloned and p…

    VHDL