Building a RISC-V CPU Core

Helpful Resources used from Building a RISC-V CPU Core EdX course by Steve Hoover of Redwoodeda, Linux Foundation and RISC-V International

Welcome

This Repository contains the full code of RISC-V CPU CORE developed during the course and also includes resources provided in Linux Foundation by Steve Hoover

Solution Code

The Solution code for Building RISC-V CPU CORE on Makerchip IDE using TL-verilog was developed by Ashrit V during the course timeline.You can find the Solution here and it is encouraged to take up the course and write the code on your own for understanding the working of each stage during CPU build.

RISC-V Reference Solution

In case you get stuck, we've got your back! These reference solutions (Ctrl-click) will help with syntax, etc. without handing you the answers. Here's a pre-built logic diagram of the final CPU. Ctrl-click here to explore in its own tab.

RISC-V CPU Block Diagram

Keep going and Happy learning!!