Merge remote-tracking branch 'origin/aspeed-dev' into aspeed-master

Change-Id: Ifd30d3196d2e6e200809309d1b94a50804ad0e2a

README.md

@@ -4,9 +4,28 @@ applications are developing on top of [Zephyr BSP](https://github.com/AspeedTech
 
 
 # Building ASPEED-PFR firmware
+
 ```
-west init -m https://github.com/AspeedTech-BMC/aspeed-zephyr-sdk --mr aspeed-master workspace
+west init -m https://github.com/AspeedTech-BMC/aspeed-zephyr-project --mr aspeed-master workspace
 cd workspace
 west update
-west build -b ast1060_evb -p auto aspeed-zephyr-sdk/apps/aspeed-pfr
 ```
+
+## AST2600 L board
+
+```
+west build -b ast1060_evb -p auto aspeed-zephyr-project/apps/aspeed-pfr
+```
+
+## AST2600 DCSCM board
+
+```
+west build -b ast1060_dcscm -p auto aspeed-zephyr-project/apps/aspeed-pfr
+```
+
+## AST2600 Dual Flash
+
+```
+west build -b ast1060_dual_flash -p auto aspeed-zephyr-project/apps/aspeed-pfr
+```
+

apps/aspeed-pfr/Kconfig

@@ -0,0 +1,58 @@
+# Copyright (c) 2022 ASPEED Technology Inc.
+# # SPDX-License-Identifier: MIT
+
+config ASPEED_DC_SCM
+	default n
+	bool "ASPEED DC-SCM board"
+	help
+	  Enable ASPEED DC-SCM board basic settings.
+
+config BMC_DUAL_FLASH
+	default n
+	bool "Enable dual flash support"
+	help
+	  Enable if BMC has dual flash
+
+config SPI_MUX_INVERSE
+	default n
+	bool "Invert SPI MUX"
+	help
+	  Enable if SPI MUX connected to BMC/ROT is inverted
+
+config CHECKPOINT_RECOVERY
+	default n
+	bool "Checkpoint timeout recovery function"
+	help
+	  Enable if BMC/PCH supports mailbox checkpoint
+
+config PLATFORM_STATE_LED
+	default n
+	bool "Display platfrom state in 8 bits LED"
+	help
+	  Enable if the system has PlatformState LEDs
+
+config BMC_STAGING_SIZE
+	default 0x03DE0000
+	hex "BMC staging region size in BMC flash"
+	help
+	  The max size of BMC staging area for putting signed BMC capsule.
+
+config BMC_PCH_STAGING_SIZE
+	default 0x1000000
+	hex "PCH staging region size in BMC flash"
+	help
+	  The max size of PCH staging area for putting signed PCH capsule.
+
+config BMC_PFR_STAGING_SIZE
+	default 0x500000
+	hex "PFR staging region size in BMC flash"
+	help
+	  The max size of PFR staging area for putting signed ROT capsule.
+
+config PCH_STAGING_SIZE
+	default 0x1000000
+	hex "PCH staging region size in PCH flash"
+	help
+	  The max size of PCH staging area for putting signed PCH capsule.
+
+source "Kconfig.zephyr"

apps/aspeed-pfr/boards/ast1060_dcscm.conf

@@ -0,0 +1,23 @@
+CONFIG_GPIO_ASPEED_SGPIOM=y
+CONFIG_GPIO_ASPEED=y
+CONFIG_SPI_ASPEED=y
+CONFIG_SPI_MONITOR_ASPEED=y
+CONFIG_SPI_MONITOR_SHELL_ASPEED=y
+CONFIG_SPI_NOR_ADDR_MODE_FALLBACK_DISABLED=y
+CONFIG_PFR_SHELL_ASPEED=y
+CONFIG_I2C_ASPEED=y
+CONFIG_I2C_PFR=y
+CONFIG_I2C_PFR_INIT_PRIORITY=60
+CONFIG_I2C_PFR_FILTER=y
+CONFIG_SHELL_ARGC_MAX=70
+CONFIG_WATCHDOG=y
+CONFIG_WDT_ASPEED=y
+CONFIG_UART_ASPEED=y
+CONFIG_ASPEED_DC_SCM=y
+CONFIG_PFR_SW_MAILBOX=y
+CONFIG_I2C_SWMBX_SLAVE=y
+CONFIG_PLATFORM_STATE_LED=y
+CONFIG_BMC_STAGING_SIZE=0x3de0000
+CONFIG_BMC_PCH_STAGING_SIZE=0x1000000
+CONFIG_BMC_PFR_STAGING_SIZE=0x500000
+CONFIG_PCH_STAGING_SIZE=0x1000000