fix(comp): use verilog attributes for {parallel, full}_case modifiers

Verilog 2001 attributes are supported by Vivado, Quartus, and other
tools (like Yosys) in order to parallel/full case semantics. Usage of
synopsys-specific synthesis comments can be done better this way, and it
suppresses a real warning with Yosys.

This takes us *out* of v95 territory, because Verilog attributes were
added in Verilog 2001. Currently, no fallback is supported, though this
could be fixed. It's unclear to me how much this harms "portability" of
the output Verilog code, but such features can always be added back
later on demand...

Signed-off-by: Austin Seipp <[email protected]>

src/comp/Verilog.hs

@@ -441,13 +441,13 @@ instance PPrint VStmt where
              text "`endif // BSV_NO_INITIAL_BLOCKS"
         pPrint d p (VSeq ss) = text "begin" $+$ (text "  " <> ppLines d ss) $+$ text "end"
         pPrint d p s@(Vcasex {}) =
-            (text "casex" <+> pparen True (pPrint d 0 (vs_case_expr s))) <+>
-                pprintCaseAttributes (vs_parallel s) (vs_full s) $+$
+            pprintCaseAttributes (vs_parallel s) (vs_full s) <+>
+                (text "casex" <+> pparen True (pPrint d 0 (vs_case_expr s))) $+$
             (text "  " <> ppLines d (vs_case_arms s)) $+$
             (text "endcase")
         pPrint d p s@(Vcase {}) =
-            (text "case" <+> pparen True (pPrint d 0 (vs_case_expr s))) <+>
-                pprintCaseAttributes (vs_parallel s) (vs_full s) $+$
+            pprintCaseAttributes (vs_parallel s) (vs_full s) <+>
+                (text "case" <+> pparen True (pPrint d 0 (vs_case_expr s))) $+$
             (text "  " <> ppLines d (vs_case_arms s)) $+$
             (text "endcase")
         pPrint d p (VAssign v e) =
@@ -506,10 +506,9 @@ ppAs1 d i cs xs = text c1 <> ppAs1 d i c2 xs where
 
 pprintCaseAttributes :: Bool -> Bool -> Doc
 pprintCaseAttributes False False = empty
-pprintCaseAttributes True  False = mkSynthPragma "parallel_case"
-pprintCaseAttributes False True  = mkSynthPragma "full_case"
-pprintCaseAttributes True  True  = mkSynthPragma "parallel_case full_case"
-
+pprintCaseAttributes True  False = text "(* parallel_case *)"
+pprintCaseAttributes False True  = text "(* full_case *)"
+pprintCaseAttributes True  True  = text "(* parallel_case, full_case *)"
 
 -- hack to check if expressions are known to be true or false
 isOne :: VExpr -> Bool