minor review fixes

CQCL · Jun 17, 2024 · 2a7e7e6 · 2a7e7e6
1 parent b7e9dc5
commit 2a7e7e6
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Showing 2 changed files with 6 additions and 6 deletions.
diff --git a/hugr-py/src/hugr/_cfg.py b/hugr-py/src/hugr/_cfg.py
@@ -8,7 +8,7 @@
 
 
 class Block(DfBase[ops.DataflowBlock]):
-    def block_outputs(self, branching: Wire, *other_outputs: Wire) -> None:
+    def set_block_outputs(self, branching: Wire, *other_outputs: Wire) -> None:
         self.set_outputs(branching, *other_outputs)
 
     def single_successor_outputs(self, *outputs: Wire) -> None:

diff --git a/hugr-py/tests/test_cfg.py b/hugr-py/tests/test_cfg.py
@@ -7,7 +7,7 @@
 def build_basic_cfg(cfg: Cfg) -> None:
     entry = cfg.simple_entry(1, [tys.Bool])
 
-    entry.block_outputs(*entry.inputs())
+    entry.set_block_outputs(*entry.inputs())
     cfg.branch(entry.root.out(0), cfg.exit)
 
 
@@ -20,14 +20,14 @@ def test_basic_cfg() -> None:
 def test_branch() -> None:
     cfg = Cfg([tys.Bool, tys.Unit, INT_T], [INT_T])
     entry = cfg.simple_entry(2, [tys.Unit, INT_T])
-    entry.block_outputs(*entry.inputs())
+    entry.set_block_outputs(*entry.inputs())
 
     middle_1 = cfg.simple_block([tys.Unit, INT_T], 1, [INT_T])
-    middle_1.block_outputs(*middle_1.inputs())
+    middle_1.set_block_outputs(*middle_1.inputs())
     middle_2 = cfg.simple_block([tys.Unit, INT_T], 1, [INT_T])
     u, i = middle_2.inputs()
     n = middle_2.add(DivMod(i, i))
-    middle_2.block_outputs(u, n[0])
+    middle_2.set_block_outputs(u, n[0])
 
     cfg.branch(entry.root.out(0), middle_1.root)
     cfg.branch(entry.root.out(1), middle_2.root)
@@ -46,4 +46,4 @@ def test_nested_cfg() -> None:
     build_basic_cfg(cfg)
     dfg.set_outputs(cfg.root)
 
-    _validate(dfg.hugr, True)
+    _validate(dfg.hugr)