Update circuit.pyi

CQCL · Aug 31, 2023 · 9c1119f · 9c1119f
1 parent 0ae0af9
commit 9c1119f
Showing 1 changed file with 9 additions and 0 deletions.
diff --git a/pytket/pytket/_tket/circuit.pyi b/pytket/pytket/_tket/circuit.pyi
@@ -8,6 +8,11 @@ import pytket._tket.pauli
 import pytket._tket.unit_id
 import sympy
 
+class BarrierOp(Op):
+    def __init__(self, signature: List[EdgeType], data: str) -> None: ...
+    @property
+    def data(self) -> str: ...
+
 class BasisOrder:
     __members__: ClassVar[dict] = ...  # read-only
     __entries: ClassVar[dict] = ...
@@ -263,6 +268,10 @@ class Circuit:
     def ZZPhase(self, angle: Union[sympy.Expr,float], qubit0: int, qubit1: int, **kwargs: Any) -> Circuit: ...
     @overload
     def ZZPhase(self, angle: Union[sympy.Expr,float], qubit0: pytket._tket.unit_id.Qubit, qubit1: pytket._tket.unit_id.Qubit, **kwargs: Any) -> Circuit: ...
+    @overload
+    def _add_conditional_barrier(self, barrier_qubits: List[int], barrier_bits: List[int], condition_bits: List[int], value: int, data: str = ...) -> Circuit: ...
+    @overload
+    def _add_conditional_barrier(self, barrier_args: List[pytket._tket.unit_id.UnitID], condition_bits: List[pytket._tket.unit_id.UnitID], value: int, data: str = ...) -> Circuit: ...
     def _add_w_register(self, size: int) -> None: ...
     @overload
     def _add_wasm(self, funcname: str, wasm_uid: str, width_i_parameter: List[int], width_o_parameter: List[int], args: List[int], wasm_wire_args: List[int], **kwargs: Any) -> Circuit: ...