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Try to workaround https://github.com/CTSRD-CHERI/qemu/issues/165 #166

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Try to workaround https://github.com/CTSRD-CHERI/qemu/issues/165 #166

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5 changes: 4 additions & 1 deletion target/mips/translate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -32710,10 +32710,13 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
CPUMIPSState *env = &cpu->env;
int i;

// FIXME: will this be the right pc or start of TB?
// Correct fix would be to implement tcg_cpu_synchronize_state()
target_ulong pc_addr = cpu_get_current_pc(env, 0, 0);
qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx " ds %04x "
TARGET_FMT_lx " " TARGET_FMT_ld "\n",
PC_ADDR(env), env->active_tc.HI[0], env->active_tc.LO[0],
pc_addr, env->active_tc.HI[0], env->active_tc.LO[0],
env->hflags, env->btarget, env->bcond);
for (i = 0; i < 32; i++) {
if ((i & 3) == 0) {
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5 changes: 4 additions & 1 deletion target/riscv/cpu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -257,7 +257,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env));
}
#endif
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", PC_ADDR(env));
// FIXME: will this be the right pc or start of TB?
// Correct fix would be to implement tcg_cpu_synchronize_state()
target_ulong pc_addr = cpu_get_current_pc(env, 0, 0);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", pc_addr);
#ifdef TARGET_CHERI
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc (offset) ", GET_SPECIAL_REG_ARCH(env, pc, PCC));
#endif
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