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CHERI-RISC-V: slightly rearrange SLTI HINT decoder #180

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CHERI-RISC-V: slightly rearrange SLTI HINT decoder #180

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92 changes: 51 additions & 41 deletions target/riscv/insn_trans/trans_rvi.c.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -248,52 +248,62 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)

static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
#ifdef CONFIG_TCG_LOG_INSTR
/*
* If instruction tracing is enabled, we use slti zero, zero, <magic>
* to perform magic-nop tracing control operations.
* These will trigger a flush of the TCG buffer, so prepare to resume
* from next instruction.
*/
if (unlikely(a->rd == 0)) {
TCGv tpc = tcg_const_tl(ctx->base.pc_next);
TCGv_i32 ttmp;

switch (a->imm) {
case 0x01: case 0x02:
ttmp = tcg_const_i32(a->imm == 0x01);
gen_helper_qemu_log_instr_buffered_mode(cpu_env, ttmp);
tcg_temp_free_i32(ttmp);
break;
case 0x03:
gen_helper_qemu_log_instr_buffer_flush(cpu_env);
break;
case 0x1b:
gen_helper_qemu_log_instr_start(cpu_env, tpc);
ctx->base.is_jmp = DISAS_NORETURN;
break;
case 0x1e:
gen_helper_qemu_log_instr_stop(cpu_env, tpc);
ctx->base.is_jmp = DISAS_NORETURN;
break;
case 0x2b:
gen_helper_qemu_log_instr_user_start(cpu_env, tpc);
ctx->base.is_jmp = DISAS_NORETURN;
break;
case 0x2e:
gen_helper_qemu_log_instr_stop(cpu_env, tpc);
ctx->base.is_jmp = DISAS_NORETURN;
switch (a->rs1) {
case 0x0: /* x0: imm specifies particular hint */
/* imm == 0 reserved */
/* imm in [1, 0x2f] reserved for tracing framework */
if ((a->imm > 0) && (a->imm <= 0x2f)) {
#ifdef CONFIG_TCG_LOG_INSTR
/*
* If instruction tracing is enabled, we use slti zero, zero,
* <magic> to perform magic-nop tracing control operations.
* These will trigger a flush of the TCG buffer, so prepare to
* resume from next instruction.
*/
TCGv tpc = tcg_const_tl(ctx->base.pc_next);
TCGv_i32 ttmp;
switch (a->imm) {
case 0x01: case 0x02:
ttmp = tcg_const_i32(a->imm == 0x01);
gen_helper_qemu_log_instr_buffered_mode(cpu_env, ttmp);
tcg_temp_free_i32(ttmp);
break;
case 0x03:
gen_helper_qemu_log_instr_buffer_flush(cpu_env);
break;
case 0x1b:
gen_helper_qemu_log_instr_start(cpu_env, tpc);
ctx->base.is_jmp = DISAS_NORETURN;
break;
case 0x1e:
gen_helper_qemu_log_instr_stop(cpu_env, tpc);
ctx->base.is_jmp = DISAS_NORETURN;
break;
case 0x2b:
gen_helper_qemu_log_instr_user_start(cpu_env, tpc);
ctx->base.is_jmp = DISAS_NORETURN;
break;
case 0x2e:
gen_helper_qemu_log_instr_stop(cpu_env, tpc);
ctx->base.is_jmp = DISAS_NORETURN;
break;
}
tcg_temp_free(tpc);

if (ctx->base.is_jmp != DISAS_NEXT) {
gen_update_cpu_pc(ctx->pc_succ_insn);
exit_tb(ctx);
return true;
}
#endif
}
/* imm in [ 0x30, 0xFFF ] are reserved for future CHERI expansion */
break;
}
tcg_temp_free(tpc);

if (ctx->base.is_jmp != DISAS_NEXT) {
gen_update_cpu_pc(ctx->pc_succ_insn);
exit_tb(ctx);
return true;
/* rs1 in [1, 31] is reserved for future CHERI expansion */
}
}
#endif
return gen_arith_imm_tl(ctx, a, &gen_slt);
}

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