First step out on Open Source Chip Project by University (OSCPU)
Initial parts of a single cycle RISCV64I CPU include the following files: defines.v, if_stage.v, regfile.v, id_stage.v, exe_stage.v, mem_stage.v, ram_1w2r.v, wb.v. With SimTop.v as the top file for tests Up to now we have used difftest offered by NJU-ProjectN to test on the whole project, and successfully we have passed cpu-tests and riscv-tests. Although the first step out takes more time than we expect, its still a huge progress of our 5 weeks' work.
The next stage is on the road.