Daily bump.

gcc/ChangeLog

@@ -1,3 +1,62 @@
+2024-01-02  Jun Sha (Joshua)  <[email protected]>
+	    Jin Ma  <[email protected]>
+	    Xianmiao Qu  <[email protected]>
+	    Christoph Müllner  <[email protected]>
+
+	* config/riscv/vector.md:
+	Use vector_length_operand for vsetvl patterns.
+
+2024-01-02  Juzhe-Zhong  <[email protected]>
+
+	* config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
+	(expand_cond_len_op): Add simplification of dummy len and dummy mask.
+
+2024-01-02  Di Zhao  <[email protected]>
+
+	* config/aarch64/aarch64-tuning-flags.def
+	(AARCH64_EXTRA_TUNING_OPTION): New tuning option
+	AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
+	* config/aarch64/aarch64.cc
+	(aarch64_override_options_internal): Set
+	param_fully_pipelined_fma according to tuning option.
+	* config/aarch64/tuning_models/ampere1.h: Add
+	AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
+	* config/aarch64/tuning_models/ampere1a.h: Likewise.
+	* config/aarch64/tuning_models/ampere1b.h: Likewise.
+
+2024-01-02  Feng Wang  <[email protected]>
+
+	* config/riscv/vector-crypto.md: Modify copyright year.
+
+2024-01-02  Juzhe-Zhong  <[email protected]>
+
+	* config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
+
+2024-01-02  Lulu Cheng  <[email protected]>
+
+	* config.in: Regenerate.
+	* config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
+	* config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
+	Added TLS Le Relax support.
+	(loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
+	* config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
+	* configure: Regenerate.
+	* configure.ac: Check if binutils supports TLS le relax.
+
+2024-01-02  Feng Wang  <[email protected]>
+
+	* config/riscv/iterators.md: Add rotate insn name.
+	* config/riscv/riscv.md: Add new insns name for crypto vector.
+	* config/riscv/vector-iterators.md: Add new iterators for crypto vector.
+	* config/riscv/vector.md: Add the corresponding attr for crypto vector.
+	* config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
+
+2024-01-02  Juzhe-Zhong  <[email protected]>
+
+	PR target/113112
+	* config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
+	pointer type liveness count.
+
 2023-12-31  Uros Bizjak  <[email protected]>
 	    Roger Sayle  <[email protected]>
 

gcc/DATESTAMP

@@ -1 +1 @@
-20240102
+20240103

gcc/testsuite/ChangeLog

@@ -1,3 +1,22 @@
+2024-01-02  Szabolcs Nagy  <[email protected]>
+
+	* gfortran.dg/vect/vect-8.f90: Accept more vectorized loops.
+
+2024-01-02  Juzhe-Zhong  <[email protected]>
+
+	* gcc.target/riscv/rvv/base/vf_avl-3.c: New test.
+
+2024-01-02  Lulu Cheng  <[email protected]>
+
+	* lib/target-supports.exp: Add a function to check whether binutil supports
+	TLS Le Relax.
+	* gcc.target/loongarch/tls-le-relax.c: New test.
+
+2024-01-02  Juzhe-Zhong  <[email protected]>
+
+	PR target/113112
+	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: New test.
+
 2023-12-31  Uros Bizjak  <[email protected]>
 	    Roger Sayle  <[email protected]>
 

libsanitizer/ChangeLog

@@ -1,3 +1,7 @@
+2024-01-02  Andreas Schwab  <[email protected]>
+
+	* configure.tgt (riscv64-*-linux*): Enable LSan and TSan.
+
 2023-11-28  Rainer Orth  <[email protected]>
 
 	* LOCAL_PATCHES: Update.