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* Removed trailing whitespaces in the codebase. * Added boot0 Mask ROM dumping (as requested by @MasterLuma).
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build | ||
/*.elf | ||
/*.dol | ||
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# Clion files | ||
.idea | ||
cmake-build-debug | ||
CMakeLists.txt | ||
output | ||
*.elf | ||
*.dol | ||
*.bin | ||
*.cert | ||
*.txt |
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#include <ogc/machine/processor.h> | ||
#include <unistd.h> | ||
#include <string.h> | ||
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#include "boot0.h" | ||
#include "tools.h" | ||
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#define SRAM_MIRROR 0xD400000 | ||
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#define HW_SRNPROT 0xD800060 | ||
#define SRAM_MASK 0x20 | ||
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#define HW_BOOT0 0xD80018C | ||
#define BOOT0_MASK 0x1000 | ||
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#define BOOT0_BLK_SIZE 4 | ||
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u16 boot0_read(void *dst, u16 offset, u16 size) | ||
{ | ||
if (!dst || offset >= BOOT0_SIZE || !size || (offset + size) > BOOT0_SIZE) return 0; | ||
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u8 *ptr = (u8*)dst; | ||
u8 val[BOOT0_BLK_SIZE] = {0}; | ||
u16 cur_offset = 0; | ||
bool disable_sram_mirror = false; | ||
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// Calculate block offsets and sizes | ||
u32 start_addr = (SRAM_MIRROR + ALIGN_DOWN(offset, BOOT0_BLK_SIZE)); | ||
u8 start_addr_offset = (offset % BOOT0_BLK_SIZE); | ||
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u32 end_addr = (SRAM_MIRROR + ALIGN_UP(offset + size, BOOT0_BLK_SIZE)); | ||
u8 end_addr_size = ((offset + size) % BOOT0_BLK_SIZE); | ||
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// Make sure the SRAM mirror is enabled (unlikely to be disabled, but let's play it safe) | ||
if (!(read32(HW_SRNPROT) & SRAM_MASK)) | ||
{ | ||
// Enable SRAM mirror | ||
mask32(HW_SRNPROT, 0, SRAM_MASK); | ||
disable_sram_mirror = true; | ||
} | ||
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// Enable boot0 | ||
mask32(HW_BOOT0, BOOT0_MASK, 0); | ||
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for(u32 addr = start_addr; addr < end_addr; addr += BOOT0_BLK_SIZE) | ||
{ | ||
if (cur_offset >= size) break; | ||
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// Read SRAM mirror (actually holds boot0 data) | ||
*((u32*)val) = read32(addr); | ||
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// Copy data to destination buffer | ||
if (addr == start_addr && start_addr_offset != 0) | ||
{ | ||
// Handle unaligned read at start address | ||
memcpy(ptr + cur_offset, val + start_addr_offset, BOOT0_BLK_SIZE - start_addr_offset); | ||
cur_offset += (BOOT0_BLK_SIZE - start_addr_offset); | ||
} else | ||
if (addr >= (end_addr - BOOT0_BLK_SIZE) && end_addr_size != 0) | ||
{ | ||
// Handle unaligned read at end address | ||
memcpy(ptr + cur_offset, val, end_addr_size); | ||
cur_offset += end_addr_size; | ||
} else { | ||
// Normal read | ||
memcpy(ptr + cur_offset, val, BOOT0_BLK_SIZE); | ||
cur_offset += BOOT0_BLK_SIZE; | ||
} | ||
} | ||
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// Disable boot0 | ||
mask32(HW_BOOT0, 0, BOOT0_MASK); | ||
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// Disable SRAM mirror, if needed | ||
if (disable_sram_mirror) mask32(HW_SRNPROT, SRAM_MASK, 0); | ||
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return cur_offset; | ||
} |
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#ifndef __BOOT0_H__ | ||
#define __BOOT0_H__ | ||
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#define BOOT0_SIZE 0x1000 | ||
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u16 boot0_read(void *dst, u16 offset, u16 size); | ||
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#endif /* __BOOT0_H__ */ |
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