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1. Nonblocking-Cache Nonblocking-Cache Public

   A direct mapped, non-blocking cache implemented with a parameterized amount of allowed misses. Tracks entries in the miss status handling register with an operation or op code.

   SystemVerilog

2. 1D-Convolution-Speedup 1D-Convolution-Speedup Public

   Using Dr. Stitt's code framework, increased the speed of 1 dimensional convolution of a pixel stream with a kernel using a pipeline, buffers, and RAMs.

   VHDL