See Vitis™ Development Environment on xilinx.com |
The Introduction page contains important information including tool version, environment settings, and a table describing the platform, operating system, and supported features or flows of each tutorial. It is strongly recommended that you check the introduction page for details before starting to use the AIE tutorials.
The methodology for developing optimized accelerated applications is comprised of two major phases: architecting the application, and developing the kernels. In the first phase, you make key decisions about the application architecture by determining which software functions should be accelerated onto ACAP kernels, how much parallelism can be achieved, and how to deliver it in code. In the second phase, you implement the kernels by structuring the source code, and applying the necessary build options to create the kernel architecture needed to achieve the optimized performance target. The following examples illustrate the use of this methodology in real-world applications.
| Tutorial | Description |
| LeNet Tutorial | This tutorial uses the LeNet algorithm to implement a system-level design to perform image classification using the AI Engine and PL logic, including block RAM (BRAM). The design demonstrates functional partitioning between the AI Engine and PL. It also highlights memory partitioning and hierarchy among DDR memory, PL (BRAM) and AI Engine memory. |
| Super Sampling Rate FIR Filters | The purpose of this tutorial is to provide a methodology to enable you to make appropriate choices depending on the filter characteristics, and to provide examples on how to implement Super Sampling Rate (SSR) FIR Filters on a Versal® ACAP AI Engine processor array. |
| Beamforming Design | This tutorial demonstrates the creation of a beamforming system running on the AI Engine, PL, and PS, and the validation of the design running on this heterogeneous domain. |
| AIE Emulation on Custom Platforms | This tutorial demonstrates the creation and emulation of an AIE design including the Adaptive DataFlow (ADF) graph, RTL kernels, and a custom VCK190 platform. |
| 2D-FFT | This tutorial performs two implementations of a system-level design (2D-FFT): one with AI Engine, and the other with HLS using the DSP Engines. |
| FIR Filter | This tutorial demonstrates the implementations of a system-level design (FIR Filter) using AI Engines and HLS with DSP Engines in the Versal device plus PL including LUTs, flip-flops (FFs), and block RAMs. |
| N-Body Simulator | It is a system-level design that uses the AI Engine, PL, and PS resources to showcase the following features: |
| Tutorial | Description |
| Using GMIO with AIE | This tutorial introduces the usage of global memory I/O (GMIO) for sharing data between the AI Engines and external DDR |
| Runtime Parameter Reconfiguration | Learn how to dynamically update AI Engine runtime parameters |
| Packet Switching | This tutorial illustrates how to use data packet switching with AI Engine designs to optimize efficiency. |
| AI Engine Versal Integration for Hardware Emulation and Hardware | This tutorial demonstrates creating a system design running on the AI Engine, PS, and PL and validating the design running on these heterogeneous domains by running Hardware Emulation. |
| Versal System Design Clocking | This tutorial demonstrates clocking concepts for the Vitis compiler by defining clocking for ADF graph PL kernels and PLIO kernels, using the clocking automation functionality. |
| Using Floating-Point in the AI Engine | These examples demonstrate floating-point vector computations in the AI Engine. |
| DSP Library Tutorial | This tutorial demonstrates how to use kernels provided by the DSP library for a filtering application, how to analyze the design results, and how to use filter parameters to optimize the design's performance using simulation. |
| Debug Walkthrough Tutorial | This tutorial demonstrates how to debug a multi-processor application using the Versal ACAP AI Engines, using a beamformer example design. The tutorial illustrates functional debug and performance level debug techniques. |
| AI Engine DSP Library and Model Composer Tutorial | This tutorial shows how to design AI Engine applications using Model Composer. This set of blocksets for Simulink is used to demonstrate how easy it is to develop applications for Xilinx devices, integrating RTL/HLS blocks for the Programmable Logic, as well as AI Engine blocks for the AI Engine array. |
| Versal Emulation Waveform Analysis | This tutorial demonstrates how you can use the Vivado logic simulator (XSIM) waveform GUI, and the Vitis analyzer to debug and analyze your design for a Versal ACAP. |
| AXIS External Traffic Generator | This tutorial shows how to use AXI Traffic Generators to provide input and capture output from an AI Engine kernel in hardware emulation. |
| AI Engine Performance and Deadlock Analysis Tutorial | This tutorial introduces you to performance analysis and optimization methods, and shows you how synchronization works in graph execution. It also demonstrates the analysis of a hang issue using an example. |
| Implementing an IIR Filter on the AI Engine | This multi-part tutorial describes how to implement an [infinite impulse response (IIR) filter](https://en.wikipedia.org/wiki/Infinite_impulse_response) on the AI Engine. |
| A to Z Bare-metal Flow | This tutorial walks through the steps to create a custom Baremetal platform, and also integrate Baremetal host application along with an AI Engines graph and PL kernels. |
| Post-Link Recompile of an AI Engine Application | This tutorial shows you how to modify an AI Engine application after the platform has been frozen. It avoids a complete Vivado® tool run, which can take a long time if timing closure requires specific attention. The only limitation is that the hardware connection between the AI Engine array and the programmable logic (PL) must be kept fixed. The tutorial demonstrates a Vitis IDE flow and a Makefile flow. |
| Python and C++ External Traffic Generators for AI Engine Simulation and Emulation Flows | This tutorial develops a case in which the dataflow goes back and forth multiple times between the programmable logic (PL) and the AI Engine array. Some PL blocks are only source or destination kernels, whereas others are processing kernels within the dataflow. This tutorial demonstrates how to create external traffic generators as Python scripts or C++ applications to exercise the AI Engine kernels in the x86 simulator, AI Engine simulator, and in hardware emulation. |
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