Mlp example #172
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| Original file line number | Diff line number | Diff line change |
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| #!/usr/bin/env python3 | ||
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| import os, logging | ||
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| from mase_cocotb.random_test import check_results | ||
| from mase_cocotb.runner import mase_runner | ||
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| import cocotb | ||
| from cocotb.triggers import Timer | ||
| from cocotb.triggers import FallingEdge | ||
| from cocotb.clock import Clock | ||
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| logger = logging.getLogger(__name__) | ||
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| # DUT test specifications | ||
| class VerificationCase: | ||
| def __init__(self, iterations=1, samples=10): | ||
| self.samples = samples | ||
| self.iterations = iterations | ||
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| @cocotb.test() | ||
| async def test_top(dut): | ||
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There was a problem hiding this comment. This functionality is already implemented in |
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| """Test top-level model hardware design""" | ||
| samples = 1000 | ||
| test_case = VerificationCase(samples=samples) | ||
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| # Reset cycle | ||
| await Timer(20, units="ns") | ||
| dut.rst.value = 1 | ||
| await Timer(100, units="ns") | ||
| dut.rst.value = 0 | ||
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| # Create a 10ns-period clock on port clk | ||
| clock = Clock(dut.clk, 10, units="ns") | ||
| # Start the clock | ||
| cocotb.start_soon(clock.start()) | ||
| await Timer(500, units="ns") | ||
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| # Synchronize with the clock | ||
| dut.data_in_0_valid.value = 0 | ||
| dut.data_out_0_ready.value = 1 | ||
| debug_state(dut, "Pre-clk") | ||
| await FallingEdge(dut.clk) | ||
|
There was a problem hiding this comment. Driving handshakes manually by assigning signals and awaiting clock edges is too verbose and error prone. We should use mase_cocotb.interfaces.streaming.StreamDriver instead |
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| debug_state(dut, "Post-clk") | ||
| debug_state(dut, "Pre-clk") | ||
| await FallingEdge(dut.clk) | ||
| debug_state(dut, "Post-clk") | ||
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| done = False | ||
| # Set a timeout to avoid deadlock | ||
| for i in range(samples * 100): | ||
| await FallingEdge(dut.clk) | ||
| debug_state(dut, "Post-clk") | ||
| dut.data_in_0_valid.value = test_case.data_in.pre_compute() | ||
| await Timer(1, units="ns") | ||
| dut.data_out_0_ready.value = test_case.outputs.pre_compute( | ||
| dut.data_out_0_valid.value | ||
| ) | ||
| await Timer(1, units="ns") | ||
| debug_state(dut, "Post-clk") | ||
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| dut.data_in_0_valid.value, dut.data_in_0.value = test_case.data_in.compute( | ||
| dut.data_in_0_ready.value | ||
| ) | ||
| await Timer(1, units="ns") | ||
| dut.data_out_0_ready.value = test_case.outputs.compute( | ||
| dut.data_out_0_valid.value, dut.data_out_0.value | ||
| ) | ||
| debug_state(dut, "Pre-clk") | ||
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| if test_case.data_in.is_empty() and test_case.outputs.is_full(): | ||
| done = True | ||
| break | ||
| assert ( | ||
| done | ||
| ), "Deadlock detected or the simulation reaches the maximum cycle limit (fixed it by adjusting the loop trip count)" | ||
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| check_results(test_case.outputs.data, test_case.ref) | ||
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verification classes should inherit from mase_cocotb.testbench.Testbench