TIMG: Fix interrupt handler setup

Dominaezzz · Jun 24, 2024 · 16d6898 · 16d6898
1 parent fd467c2
commit 16d6898
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Showing 5 changed files with 35 additions and 52 deletions.
diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md
@@ -19,6 +19,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ### Fixed
 
+- TIMG: Fix interrupt handler setup (#1714)
+
 ### Changed
 
 - Refactor `Dac1`/`Dac2` drivers into a single `Dac` driver (#1661)

diff --git a/esp-hal/src/timer/systimer.rs b/esp-hal/src/timer/systimer.rs
@@ -32,7 +32,7 @@
 //!     peripherals.TIMG0,
 //!     &clocks,
 //!     Some(TimerInterrupts {
-//!         timer0_t0: Some(tg0_t0_level),
+//!         timer0: Some(tg0_t0_level),
 //!         ..Default::default()
 //!     }),
 //! );

diff --git a/esp-hal/src/timer/timg.rs b/esp-hal/src/timer/timg.rs
@@ -85,21 +85,13 @@ use crate::{
 /// Interrupts which can be registered in [Blocking] mode
 #[derive(Debug, Default)]
 pub struct TimerInterrupts {
-    /// T0 Interrupt for [`Timer0`]
-    pub timer0_t0: Option<InterruptHandler>,
-    /// T1 Interrupt for [`Timer0`]
-    pub timer0_t1: Option<InterruptHandler>,
-    /// WDT Interrupt for [`Timer0`]
-    pub timer0_wdt: Option<InterruptHandler>,
-    /// T0 Interrupt for [`Timer1`]
-    #[cfg(timg_timer1)]
-    pub timer1_t0: Option<InterruptHandler>,
-    /// T1 Interrupt for [`Timer1`]
-    #[cfg(timg_timer1)]
-    pub timer1_t1: Option<InterruptHandler>,
-    /// WDT Interrupt for [`Timer1`]
-    #[cfg(timg_timer1)]
-    pub timer1_wdt: Option<InterruptHandler>,
+    /// Interrupt for [`Timer0`]
+    pub timer0: Option<InterruptHandler>,
+    #[cfg(any(esp32, esp32s2, esp32s3))]
+    /// Interrupt for [`Timer1`]
+    pub timer1: Option<InterruptHandler>,
+    /// WDT Interrupt
+    pub wdt: Option<InterruptHandler>,
 }
 
 /// A timer group consisting of up to 2 timers (chip dependent) and a watchdog
@@ -274,50 +266,39 @@ where
         );
 
         if let Some(isr) = isr {
-            if let Some(handler) = isr.timer0_t0 {
+            let (t0, t2, wdt) = match T::id() {
+                0 => (
+                    Interrupt::TG0_T0_LEVEL,
+                    Interrupt::TG0_T1_LEVEL,
+                    Interrupt::TG0_WDT_LEVEL,
+                ),
+                #[cfg(timg_timer1)]
+                1 => (
+                    Interrupt::TG1_T0_LEVEL,
+                    Interrupt::TG1_T1_LEVEL,
+                    Interrupt::TG1_WDT_LEVEL,
+                ),
+                _ => unreachable!(),
+            };
+            if let Some(handler) = isr.timer0 {
                 unsafe {
-                    interrupt::bind_interrupt(Interrupt::TG0_T0_LEVEL, handler.handler());
-                    interrupt::enable(Interrupt::TG0_T0_LEVEL, handler.priority()).unwrap();
+                    interrupt::bind_interrupt(t0, handler.handler());
+                    interrupt::enable(t0, handler.priority()).unwrap();
                 }
             }
 
             #[cfg(any(esp32, esp32s2, esp32s3))]
-            if let Some(handler) = isr.timer0_t1 {
+            if let Some(handler) = isr.timer1 {
                 unsafe {
-                    interrupt::bind_interrupt(Interrupt::TG0_T1_LEVEL, handler.handler());
-                    interrupt::enable(Interrupt::TG0_T1_LEVEL, handler.priority()).unwrap();
+                    interrupt::bind_interrupt(t2, handler.handler());
+                    interrupt::enable(t2, handler.priority()).unwrap();
                 }
             }
 
-            if let Some(handler) = isr.timer0_wdt {
+            if let Some(handler) = isr.wdt {
                 unsafe {
-                    interrupt::bind_interrupt(Interrupt::TG0_WDT_LEVEL, handler.handler());
-                    interrupt::enable(Interrupt::TG0_WDT_LEVEL, handler.priority()).unwrap();
-                }
-            }
-
-            #[cfg(timg_timer1)]
-            {
-                if let Some(handler) = isr.timer1_t0 {
-                    unsafe {
-                        interrupt::bind_interrupt(Interrupt::TG1_T0_LEVEL, handler.handler());
-                        interrupt::enable(Interrupt::TG1_T0_LEVEL, handler.priority()).unwrap();
-                    }
-                }
-
-                #[cfg(any(esp32, esp32s2, esp32s3))]
-                if let Some(handler) = isr.timer1_t1 {
-                    unsafe {
-                        interrupt::bind_interrupt(Interrupt::TG1_T1_LEVEL, handler.handler());
-                        interrupt::enable(Interrupt::TG1_T1_LEVEL, handler.priority()).unwrap();
-                    }
-                }
-
-                if let Some(handler) = isr.timer1_wdt {
-                    unsafe {
-                        interrupt::bind_interrupt(Interrupt::TG1_WDT_LEVEL, handler.handler());
-                        interrupt::enable(Interrupt::TG1_WDT_LEVEL, handler.priority()).unwrap();
-                    }
+                    interrupt::bind_interrupt(wdt, handler.handler());
+                    interrupt::enable(wdt, handler.priority()).unwrap();
                 }
             }
         }

diff --git a/examples/src/bin/etm_timer.rs b/examples/src/bin/etm_timer.rs
@@ -39,7 +39,7 @@ fn main() -> ! {
         peripherals.TIMG0,
         &clocks,
         Some(TimerInterrupts {
-            timer0_t0: Some(tg0_t0_level),
+            timer0: Some(tg0_t0_level),
             ..Default::default()
         }),
     );

diff --git a/examples/src/bin/timer_interrupt.rs b/examples/src/bin/timer_interrupt.rs
@@ -33,7 +33,7 @@ fn main() -> ! {
         peripherals.TIMG0,
         &clocks,
         Some(TimerInterrupts {
-            timer0_t0: Some(tg0_t0_level),
+            timer0: Some(tg0_t0_level),
             ..Default::default()
         }),
     );