TinyComputerArchitecture

Tiny computer architecture having CPU and memory written in Verilog

Author: Amit Roy ([email protected])

RTL source is in:

• src/v directory for Verilog-95
• src/sv directory for System Verilog

For Verilog-95 simulation with free Verilog simulator:

• Download and build Veriwell from https://sourceforge.net/projects/veriwell
• Run: make program=<program_suffix> out=<suffix>

For System Verilog simulation with Synopsys VCS, run: make compile=sim

To simulate using Icarus Verilog, run: make compile=sim.iverilog