Reset synchronizer added

src/main/resources/ResetSync.sv

@@ -0,0 +1,24 @@
+module ResetGen(
+    input clock,
+    input reset_in,
+    output reset_out
+);
+
+reg sync_reg1;
+reg sync_reg2;
+
+always @(posedge clock or negedge reset_in) begin
+    if(~reset_in) begin
+        sync_reg1 <= 1'b1;
+        sync_reg2 <= 1'b1;
+    end 
+    else begin
+        sync_reg1 <= 1'b0;
+        sync_reg2 <= sync_reg1;
+    end
+
+end
+
+assign reset_out = sync_reg2;
+
+endmodule

src/main/scala/DtuTop.scala

@@ -1,16 +1,22 @@
 import chisel3._
 import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
 
-/**
- * Example design in Chisel.
- * A redesign of the Tiny Tapeout example as a starting point.
- */
+/*
+ * DTU Top level 
+ * Some notes on reset strategy:
+    * By default Chisel generates synchronous active high reset
+    * Remainder of SoC uses an asynchronous active low reset 
+    * Therefore DTU top level also expects an asyncronous active low reset
+    * A verilog blackbox module is added that generates a synchronous active high reset from an asynchrnous active low reset 
+*/
+
 class DtuTop(addrWidth:Int = 10, dataWidth:Int = 32) extends Module {
   val io = IO(new Bundle {
     // Interface: APB
-    val apb = new ApbTargetPort(addrWidth, dataWidth)
-
-    // Clock and Reset Interfaces are added implicitly
+    val apb = new ApbTargetPort(addrWidth, dataWidth)    
+
+    // Clock and reset are added implicity
+    // Reset is asynchronous active low
 
     // Interface: IRQ
     val irq1 = Output(Bool())
@@ -22,14 +28,23 @@ class DtuTop(addrWidth:Int = 10, dataWidth:Int = 32) extends Module {
     // Interface: GPIO pmod 0 
     val pmod0 = new PmodGpioPort()
 
-    // INterface GPIO pmod 1
+    // Interface GPIO pmod 1
     val pmod1 = new PmodGpioPort()    
   })
 
-  val ApbRegs = Module(new ApbRegTarget(addrWidth, dataWidth, 0, 2))
+  // Generate a synchronous active high reset
+  val ResetSync = Module(new ResetSync())
+  ResetSync.io.clock := clock
+  ResetSync.io.resetIn := reset
 
-  io.apb <> ApbRegs.io.apb
+  // All modules instantiated here are reset by synchronous active high reset
+  // All registers must be instantiated within this to ensure all have the same reset
+  withReset(ResetSync.io.resetOut) {
+    val ApbRegs = Module(new ApbRegTarget(addrWidth, dataWidth, 0, 2))
+    io.apb <> ApbRegs.io.apb
+  }
 
+  // interrup not generated
   io.irq1 := false.B
 
   // pmod 0 set to output
@@ -40,6 +55,7 @@ class DtuTop(addrWidth:Int = 10, dataWidth:Int = 32) extends Module {
   io.pmod1.oe := 0.U
   io.pmod1.gpo := 0.U
 
+
 }
 
 object DtuTop extends App {

src/main/scala/ResetSync.scala

@@ -0,0 +1,11 @@
+import chisel3._
+import chisel3.util._
+
+class ResetSync extends HasBlackBoxResource {
+    val io = IO(new Bundle{
+        val clock = Input(Clock())
+        val resetIn = Input(Bool())
+        val resetOut = Output(Bool())
+    })
+    addResource("ResetSync.sv")
+}