feat: top module to test

build/a.out1

@@ -10,39 +10,39 @@
      LOG[14]: 1 unaccounted
 **** module/scope: tt_um_waves.adsr_gen
      Flip-Flops   : 20
-     Logic Gates  : 263
+     Logic Gates  : 220
      ADDER[8]: 3 units
      EQUALITY[8]: 2 units
      MAGNITUDE[8]: 2 units
      MAGNITUDE[32]: 1 units
-     MUX[2]: 36 slices
+     MUX[2]: 16 slices
      LPM[5]: 6 unaccounted
      LPM[8]: 2 unaccounted
      LOG[13]: 3 unaccounted
      LOG[14]: 1 unaccounted
 **** module/scope: tt_um_waves.attack_encoder
-     Flip-Flops   : 12
-     Logic Gates  : 153
+     Flip-Flops   : 10
+     Logic Gates  : 149
      ADDER[32]: 2 units
-     MUX[2]: 12 slices
+     MUX[2]: 10 slices
      LPM[5]: 1 unaccounted
      LPM[8]: 2 unaccounted
      LOG[13]: 1 unaccounted
      LOG[14]: 1 unaccounted
 **** module/scope: tt_um_waves.decay_encoder
-     Flip-Flops   : 12
-     Logic Gates  : 153
+     Flip-Flops   : 10
+     Logic Gates  : 149
      ADDER[32]: 2 units
-     MUX[2]: 12 slices
+     MUX[2]: 10 slices
      LPM[5]: 1 unaccounted
      LPM[8]: 2 unaccounted
      LOG[13]: 1 unaccounted
      LOG[14]: 1 unaccounted
 **** module/scope: tt_um_waves.release_encoder
-     Flip-Flops   : 12
-     Logic Gates  : 153
+     Flip-Flops   : 10
+     Logic Gates  : 149
      ADDER[32]: 2 units
-     MUX[2]: 12 slices
+     MUX[2]: 10 slices
      LPM[5]: 1 unaccounted
      LPM[8]: 2 unaccounted
      LOG[13]: 1 unaccounted
@@ -69,10 +69,10 @@
      LOG[13]: 1 unaccounted
      LOG[14]: 1 unaccounted
 **** module/scope: tt_um_waves.sustain_encoder
-     Flip-Flops   : 12
-     Logic Gates  : 153
+     Flip-Flops   : 10
+     Logic Gates  : 149
      ADDER[32]: 2 units
-     MUX[2]: 12 slices
+     MUX[2]: 10 slices
      LPM[5]: 1 unaccounted
      LPM[8]: 2 unaccounted
      LOG[13]: 1 unaccounted
@@ -87,14 +87,14 @@
      LOG[13]: 1 unaccounted
      LOG[14]: 1 unaccounted
 **** TOTALS
-     Flip-Flops   : 159
-     Logic Gates  : 1540
+     Flip-Flops   : 151
+     Logic Gates  : 1481
      ADDER[8]: 6 units
      ADDER[32]: 9 units
      EQUALITY[8]: 2 units
      MAGNITUDE[8]: 4 units
      MAGNITUDE[32]: 4 units
-     MUX[2]: 242 slices
+     MUX[2]: 214 slices
      LPM[4]: 1 unaccounted
      LPM[5]: 12 unaccounted
      LPM[8]: 11 unaccounted

src/tt_um_waves.v

@@ -16,6 +16,10 @@ module tt_um_waves (
     input  wire       rst_n     // Reset_n - low to reset
 );
 
+    /* verilator lint_off UNUSEDSIGNAL */
+    // The `ena` signal is currently not used in this design
+    /* verilator lint_on UNUSEDSIGNAL */
+
     // Internal signals
     wire [5:0] freq_select = ui_in[5:0];    // Frequency selection from the first 6 bits of ui_in
     wire [1:0] wave_select = ui_in[7:6];    // Wave type selection from the last 2 bits of ui_in
@@ -536,7 +540,7 @@ module adsr_generator (
     localparam STATE_SUSTAIN  = 4'd3;
     localparam STATE_RELEASE  = 4'd4;
 
-    always @(posedge clk) begin
+    always @(posedge clk or negedge rst_n) begin
         if (!rst_n) begin
             state <= STATE_IDLE;
             amplitude <= 8'd0;
@@ -559,8 +563,9 @@ module adsr_generator (
                     end
                 end
                 STATE_DECAY: begin
+                    // Use the decay parameter to adjust the rate of decrease
                     if (amplitude > sustain) begin
-                        amplitude <= amplitude - 1;
+                        amplitude <= amplitude - decay;
                     end else begin
                         state <= STATE_SUSTAIN;
                     end
@@ -575,8 +580,9 @@ module adsr_generator (
                     end
                 end
                 STATE_RELEASE: begin
+                    // Use the release parameter to adjust the rate of decrease
                     if (amplitude > 0) begin
-                        amplitude <= amplitude - 1;
+                        amplitude <= amplitude - rel;
                     end else begin
                         state <= STATE_IDLE;
                     end
@@ -625,39 +631,31 @@ endmodule
 
 
 module encoder #(
-    parameter WIDTH = 8,        // Width of the output value
-    parameter INCREMENT = 1'b1  // Amount to increment or decrement
+    parameter WIDTH = 8,
+    parameter INCREMENT = 1'b1
 )(
-    input clk,                  // System clock
-    input rst_n,                // Active-low reset
-    input a,                    // Encoder input A
-    input b,                    // Encoder input B
-    output reg [WIDTH-1:0] value // Output value
+    input clk,
+    input rst_n,
+    input a,
+    input b,
+    output reg [WIDTH-1:0] value
 );
 
-    // Internal signals for previous states of encoder inputs
     reg old_a, old_b;
-    reg [1:0] state;  // State of encoder inputs
 
-    // Encoder state transition table based on Gray code
     always @(posedge clk) begin
         if (!rst_n) begin
             old_a <= 0;
             old_b <= 0;
             value <= 0;
-            state <= 2'b00;
         end else begin
             old_a <= a;
             old_b <= b;
-            state <= {a, b};
-
-            // Update value based on encoder state transitions
             case ({a, old_a, b, old_b})
-                4'b1000, 4'b0111: value <= value + INCREMENT; // Clockwise rotation
-                4'b0010, 4'b1101: value <= value - INCREMENT; // Counter-clockwise rotation
-                default: value <= value; // No change for invalid or noise states
+                4'b1000, 4'b0111: value <= value + INCREMENT;
+                4'b0010, 4'b1101: value <= value - INCREMENT;
+                default: value <= value;
             endcase
         end
     end
-
 endmodule