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Dummy core Compatibility with Diamond's Synplify Pro #31

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merged 2 commits into from
Sep 6, 2020
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@kammoh kammoh commented Sep 6, 2020

  • Use shift for dynamic range slicing. Should infer the same hardware.
  • Remove redundant "don't-care" else conditions (not required for Synplify, but just to make the code cleaner/simpler and possibly more efficient with some tools)

Tests are underway to verify these changes with other tools, including correctness of simulation or any changes to synthesis QoR (timing or resource usage).

- use shift for dynamic range slicing
- remove reduntant don't care conditions (not required for Synplify, but
just to make the code simpler)
@kammoh kammoh changed the base branch from master to dev September 6, 2020 13:45
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kammoh commented Sep 6, 2020

GHDL simulation: PASS

Vivado synthesis (xeda with dev's desing.json) passes.

            "fpga_part": "xc7a12tcsg325-3",
            "clock_period": 5.0,
            "strategy": "Timing",
            "optimize_power": "False",

lut 783
ff 246
slice 267
wns 0.146

dev's results (same params):
lut 722
ff 246
latch 0
slice 250
wns 0.176

Almost everything improved!!!

Vivado simulation segfaults!!! Seems something was wrong with my docker image, was also broken for dev. All good and PASS on venona.

Vivado simulation: PASS

@kammoh kammoh merged commit 1814579 into dev Sep 6, 2020
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kammoh commented Sep 6, 2020

So this PR turns out to be more than compatibility with Synplify Pro, but also general improvement in code quality.

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