The GPro Lexington CPU is a single-cycle RISC-V RV32I implementation. It features a read-only program memory and separate read/write data memory. Figure 1 shows a simplified diagram of the CPU core
Figure 1. GPro Lexington minimal core implementation
Detailed behavior of each submodule is contained in these documents:
- ROM
- RAM
- Register File
- PC
- Fetch Unit
- Decode Unit
- Arithmetic Logic Unit (ALU)
- Load/Store Unit (LSU)
- Data Bus (DBus)
- Control and Status Registers (CSR)
- Trap Unit
The list of supported instructions can be found in the Decoder section.
Information about programming the device is found in the Toolchain section.
A full diagram of the SoC (minus peripherals) is shown in Figure 2.
Figure 2. GPro Lexington SoC
Memory is divided into four major regions as shown in Figure 3:
- ROM: This read-only executable memory region contains the reset instruction location (0x0000_0000). Memory must begin at address 0x0000_0000 and may be up to 1 GB (default 4 KB). This is where the instruction memory is located.
- RAM: This secondary memory region and is where the data memory is located. Memory must begin at address 0x8000_000 and may be up to 1 GB (default 4 KB).
- Reserved: This region is reserved for future use
- SYSTEM: This region is for memory mapped system devices such as the system timer
mtime. See Load/Store specification for device addresses. - AXI I/O: This region is for memory mapped I/O peripherals such as UART. See Load/Store specification for device addresses.
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Figure 3. Memory Map
Addresses for system devices, such as the machine-mode timer (mtime), can be found in the DBus section. Addresses for peripheral devices can be found in the AXI4-Lite Crossbar section.
Upon reset, the pc is set to 0x0000_0000.
NMIs are triggered by hardware error conditions.
They case an immediate jump to 0x0000_0000 and set the mepc CSR to the address of the instruction that was interrupted.
Additionally, the MSB of mcause is set to one, indicating an interrupt, and all other bits are set to zero.
This implementation has no NMI sources.