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@GProCPU

GProCPU

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  1. Lexington Lexington Public

    The GPro 1 (Lexington) is the first generation of RISC-V processors designed by Gerber Prototyping

    SystemVerilog 4

  2. Saratoga Saratoga Public

    Forked from GProCPU/Lexington

    The GPro 2 (Saratoga) adds a 3-stage pipeline to Gerber Prototyping's line of RISC-V CPUs.

    SystemVerilog 1

Repositories

Showing 4 of 4 repositories
  • Ranger Public Forked from GProCPU/Saratoga

    The GPro 3 (Ranger) is planned to be a 5-stage pipeline RV32IM processor.

    GProCPU/Ranger’s past year of commit activity
    SystemVerilog 0 GPL-3.0 4 0 0 Updated May 20, 2024
  • Saratoga Public Forked from GProCPU/Lexington

    The GPro 2 (Saratoga) adds a 3-stage pipeline to Gerber Prototyping's line of RISC-V CPUs.

    GProCPU/Saratoga’s past year of commit activity
    SystemVerilog 0 GPL-3.0 4 0 0 Updated May 20, 2024
  • Lexington Public

    The GPro 1 (Lexington) is the first generation of RISC-V processors designed by Gerber Prototyping

    GProCPU/Lexington’s past year of commit activity
    SystemVerilog 0 GPL-3.0 4 0 0 Updated Apr 19, 2024
  • RISCOF_Saratoga Public

    Architecture test for GPro 2 Saratoga

    GProCPU/RISCOF_Saratoga’s past year of commit activity
    0 0 0 0 Updated Oct 21, 2023

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