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    4 repositories

    • Ranger

      Public
      The GPro 3 (Ranger) is planned to be a 5-stage pipeline RV32IM processor.
      SystemVerilog
      •
      GNU General Public License v3.0
      •4•1•0•0•Updated May 20, 2024May 20, 2024

    • Saratoga

      Public
      The GPro 2 (Saratoga) adds a 3-stage pipeline to Gerber Prototyping's line of RISC-V CPUs.
      SystemVerilog
      •
      GNU General Public License v3.0
      •4•1•0•0•Updated May 20, 2024May 20, 2024

    • Lexington

      Public
      The GPro 1 (Lexington) is the first generation of RISC-V processors designed by Gerber Prototyping
      SystemVerilog
      •
      GNU General Public License v3.0
      •4•1•0•0•Updated Apr 19, 2024Apr 19, 2024

    • RISCOF_Saratoga

      Public
      Architecture test for GPro 2 Saratoga
      0•0•0•0•Updated Oct 21, 2023Oct 21, 2023